AT88SC0404CA Atmel CryptoMemory SUMMARY DATASHEET Features  One of a family of devices with user memories from 1-Kbit to 8-Kbits  4-Kbit (512-byte) EEPROM user memory  Four 1-Kbit (1-Kbit, 128-byte) zones  Self-timed write cycle  Single byte or 16-byte page write mode  Programmable access rights for each zone  2-Kbit configuration zone  37-byte OTP (One-Time Programmable) area for user-defined codes  160-byte area for user-defined keys and passwords  High security features  64-bit mutual authentication protocol (under license of ELVA)  Cryptographic Message Authentication Codes (MAC)  Stream encryption  Four key sets for authentication and encryption  Eight sets of two 24-bit passwords  Anti-tearing function  Voltage and frequency monitors  Smart card features  ISO 7816 Class B (3V) operation  ISO 7816-3 asynchronous T=0 protocol (Gemplus® Patent) *  Multiple zones, key sets and passwords for multi-application use  Synchronous 2-wire serial interface for faster device initialization *  Programmable 8-byte answer-to-reset register (ATR)  ISO 7816-2 compliant modules  Embedded application features  Low voltage supply: 2.7V – 3.6V  Secure nonvolatile storage for sensitive system or user information  2-wire serial interface (TWI, 5V compatible)  1.0MHz compatibility for fast operation  Standard 8-lead plastic packages, green compliant (exceeds RoHS)  Same pin configuration as Atmel® AT24CXXX Serial EEPROM in SOIC and PDIP packages  High reliability  Endurance: 100,000 cycles  Data retention: 10 years This is a summary document.  ESD protection: 2,000V min The complete document is available on the Atmel website at www.atmel.com. * Note: Modules available with either T=0 / 2-wire modes or 2-wire mode only Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

Table 1. Pin Assignments Pad Description ISO Module TWI Module “SOIC, PDIP” TSSOP Mini-MAP VCC Supply Voltage C1 C1 8 8 4 GND Ground C5 C5 4 1 5 SCL/CLK Serial Clock Input C3 C3 6 6 2 SDA/IO Serial Data Input/Output C7 C7 5 3 7 RST Reset Input C2 NC NC NC NC Figure 1. Pin Configuration ISO Smart Card Module 8-lead SOIC, PDIP V =C1 C5=GND CC NC 1 8 V RST=C2 C6=NC CC NC 2 7 NC SCL/CLK=C3 C7=S DA /IO NC 3 6 SCL NC=C4 C8=NC GND 4 5 SDA 8-lead TSSOP 8-lead UltraThin Mini-MAP (MLP 2x3) GND 1 8 VCC NC 8 1 NC NC 2 7 NC SDA 7 2 CLK NC 6 3 NC SDA 3 6 CLK GND 5 4 V CC NC 4 5 NC BottomView TWI Smart Card Module V =C1 C5=GND CC NC=C2 C6=NC SCL/CLK=C3 C7=S DA /IO NC=C4 C8=NC   2 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

1. Description The Atmel AT88SC0404CA member of the Atmel CryptoMemory® family is a high-performance secure memory providing 4- Kbit of user memory with advanced security and cryptographic features built in. The user memory is divided into four 128-byte zones, each of which may be individually set with different security access rights or effectively combined together to provide space for one to four data files. The AT88SC0404CA features an enhanced command set that allows direct communication with microcontroller hardware 2-wire interface thereby allowing for faster firmware development with reduced code space requirements. 1.1 Smart Card Applications The AT88SC0404CA provides high security, low cost, and ease of implementation without the need for a microprocessor operating system. The embedded cryptographic engine provides for dynamic, symmetric-mutual authentication between the device and host, as well as performing stream encryption for all data and passwords exchanged between the device and host. Up to four unique key sets may be used for these operations. The AT88SC0404CA offers the ability to communicate with virtually any smart card reader using the asynchronous T = 0 protocol (Gemplus Patent) defined in ISO 7816-3. 1.2 Embedded Applications Through dynamic, symmetric-mutual authentication, data encryption, and the use of cryptographic Message Authentication Codes (MAC), the AT88SC0404CA provides a secure place for storage of sensitive information within a system. With its tamper detection circuits, this information remains safe even under attack. A 2-wire serial interface running at speeds up to 1.0MHz provides fast and efficient communications with up to 15 individually addressable devices. The AT88SC0404CA is available in industry standard 8-lead packages with the same familiar pin configuration as Atmel AT24CXXX Serial EEPROM devices. Note: Does not apply to either the TSSOP or the Ultra Thin Mini-Map pinouts Figure 1-1. Block Diagram Authentication, V Power Random CC Encryption and GND Management Generator Certification Unit Synchronous Data Transfer Interface SCL/CLK Asynchronous Password EEPROM SDA/IO ISO Interface Verification RST Reset Block Answer to Reset 3 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

2. Connection Diagram Figure 2-1. Connection Diagram 2.7v - 5.5v 2.7v - 3.6v Microprocessor CryptoMemory SDA SCL 3. Pin Descriptions 3.1 Supply Voltage (V ) CC The V input is a 2.7V to 3.6V positive voltage supplied by the host. CC 3.2 Clock (SCL/CLK) When using the asynchronous T = 0 protocol, the CLK (SCL) input provides the device with a carrier frequency f. The nominal length of one bit emitted on I/O is defined as an “elementary time unit” (ETU) and is equal to 372/ f. When using the synchronous protocol, data clocking is done on the positive edge of the clock when writing to the device and on the negative edge of the clock when reading from the device. 3.3 Reset (RST) The AT88SC0404CA provides an ISO 7816-3 compliant asynchronous answer-to-reset (ATR) sequence. Upon activation of the reset sequence, the device outputs bytes contained in the 64-bit ATR register. An internal pull-up on the RST input pad allows the device to operate in synchronous mode without bonding RST. The AT88SC0404CA does not support an ATR sequence in the synchronous mode of operation. 3.4 Serial Data (SDA/IO) The SDA/IO pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wired with any number of other open-drain or open-collector devices. An external pull-up resistor should be connected between SDA/IO and V . The CC value of this resistor and the system capacitance loading the SDA/IO bus will determine the rise time of SDA/IO. This rise time will determine the maximum frequency during read operations. Low value pull-up resistors will allow higher frequency operations while drawing higher average power supply current. SDA/IO information applies to both asynchronous and synchronous protocols.   4 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

4. Absolute Maximum Ratings* *Notice: Stresses beyond those listed under “Absolute Operating temperature .................... −40°C to +85°C Maximum Ratings” may cause permanent damage to Storage temperature ................... −65°C to + 150°C the device. This is a stress rating only and functional operation of the device at these or any other condition Voltage on any pin beyond those indicated in the operational sections of with respect to ground ................ −0.7 to V +0.7V CC this specification is not implied. Exposure to absolute Maximum operating voltage ............................. 4.0V maximum rating conditions for extended periods of time may affect device reliability. DC output current ......................................... 5.0mA Table 4-1. DC Characteristics Applicable over recommended operating range from VCC = +2.7 to 3.6V, TAC = -40°C to +85°C (unless otherwise noted) Symbol Parameter Test Conditions Min Typ Max Units V (1) Supply Voltage 2.7 3.6 V CC I Supply Current Async read at 3.57MHz 5 mA CC I Supply Current Async write at 3.57MHz 5 mA CC I Supply Current Synch read at 1MHz 5 mA CC I Supply Current Synch write at 1MHz 5 mA CC ISB Standby Current VIN = VCC or GND 100 A V SDA/IO Input Low Voltage 0 V x 0.2 V IL CC V CLK Input Low Voltage 0 V x 0.2 V IL CC V RST Input Low Voltage 0 V x 0.2 V IL CC V (1) SDA/IO Input High Voltage V x 0.7 5.5 V IH CC V (1) SCL/CLK Input High Voltage V x 0.7 5.5 V IH CC V (1) RST Input High Voltage V x 0.7 5.5 V IH CC IIL SDA/IO Input Low Current 0 < VIL < VCC x 0.15 15 A IIL SCL/CLK Input Low Current 0 < VIL < VCC x 0.15 15 A IIL RST Input Low Current 0 < VIL < VCC x 0.15 50 A IIH SDA/IO Input High Current VCC x 0.7 < VIH < VCC 20 A IIH SCL/CLK Input High Current VCC x 0.7 < VIH < VCC 100 A IIH RST Input High Current VCC x 0.7 < VIH < VCC 150 A V SDA/IO Output High Voltage 20K ohm external pull-up V x 0.7 V V OH CC CC V SDA/IO Output Low Voltage I = 1mA 0 V x 0.15 V OL OL CC IOH SDA/IO Output High Current VOH 20 A I SDA/IO Output Low Current V 10 mA OL OL Note: 1. To prevent latch up conditions from occurring during power up of the AT88SC0404CA, V must be turned on CC before applying V . For powering down, V must be removed before turning V off. IH IH CC 5 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

Table 4-2. AC Characteristics Applicable over recommended operating range from V = +2.7 to 3.6V, T = -40°C to +85°C, CL = 30pF CC AC (unless otherwise noted) Symbol Parameter Min Max Units f Async Clock Frequency 1 4 MHz CLK f Synch Clock Frequency 0 1 MHz CLK Clock Duty cycle 40 60 % tR “Rise Time - SDA/IO, RST” 1 S tF “Fall Time - SDA/IO, RST” 1 S tR Rise Time - SCL/CLK 9% x period S tF Fall Time - SCL/CLK 9% x period S t Clock Low to Data Out Valid 250 nS AA t Start Hold Time 200 nS HD.STA t Start Set-up Time 200 nS SU.STA t Data In Hold Time 10 nS HD.DAT t Data In Set-up Time 100 nS SU.DAT t Stop Set-up Time 200 nS SU.STO t Data Out Hold Time 20 nS DH t Write Cycle Time 5 mS WR 5. Device Operations for Synchronous Protocols 5.1 Clock and Data Transitions The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 5-3 on page 8). Data changes during SCL high periods will indicate a start or stop condition as defined below. 5.1.1 Start condition A high-to-low transition of SDA with SCL high defines a start condition which must precede all commands (see Figure 5-4 on page 8). 5.1.2 Stop condition A low-to-high transition of SDA with SCL high defines a stop condition. After a read sequence, the STOP condition will place the EEPROM in a standby power mode (see Figure 5-4 on page 8). 5.1.3 Acknowledge All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle (see Figure 5-5 on page 8).   6 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

5.2 Memory Reset After an interruption in communication due protocol errors, power loss or any reason, perform "Acknowledge Polling" to properly recover from the condition. Acknowledge polling consists of sending a start condition followed by a valid CryptoMemory command byte and determining if the device responded with an acknowledge. Figure 5-1. Bus Time for 2-wire Serial Communications SCL: Serial Clock, SDA: Serial Data I/O t t HIGH t F R t t SCL LOW LOW t t t t t SU.STA HD.STA HD.DAT SU.DAT SU.STO SDA IN t t t AA DH BUF SDA OUT Figure 5-2. Write Cycle Timing SCL: Serial Clock, SDA: Serial Data I/O SCL SDA 8th BIT ACK WORDn (1) t wr STOP START CONDITION CONDITION Note: The write cycle time t is the time from a valid stop condition of a write sequence to the end of the internal WR clear/write cycle 7 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

Figure 5-3. Data Validity Figure 5-4. Start and Stop Definitions Figure 5-5. Output Acknowledge 1 8 9 SCL DATA IN DATA OUT START ACKNOWLEDGE   8 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

6. Device Architecture 6.1 User Zones The EEPROM user memory is divided into four zones of 1-Kbits each. Multiple zones allow for storage of different types of data or files in different zones. Access to user zones is permitted only after meeting proper security requirements. These security requirements are user definable in the configuration memory during device personalization. If the same security requirements are selected for multiple zones, then these zones may effectively be accessed as one larger zone. Figure 6-1. User Zones Zone $0 $1 $2 $3 $4 $5 $6 $7 $00 - 128 bytes User 0 - $78 $00 - 128 bytes User 1 - $78 $00 - 128 bytes User 2 - $78 $00 - 128 bytes User 3 - $78 7. Control Logic Access to the user zones occur only through the control logic built into the device. This logic is configurable through access registers, key registers and keys programmed into the configuration memory during device personalization. Also implemented in the control logic is a cryptographic engine for performing the various higher-level security functions of the device. 9 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

8. Configuration Memory The configuration memory consists of 2048 bits of EEPROM memory used for storage of passwords, keys, codes, and also used for definition of security access rights for the user zones. Access rights to the configuration memory are defined in the control logic and are not alterable by the user after completion of personalization. Figure 8-1. Configuration Memory $0 $1 $2 $3 $4 $5 $6 $7 $00 Answer To Reset Identifitcation $08 Fab Code MTZ Card Manufacturer Code $10 Lot History Code Read Only $18 DCR Identification Number Nc $20 AR0 PR0 AR1 PR1 AR2 PR2 AR3 PR3 $28 $30 Reserved Access Control $38 $40 Issuer Code $48 $50 $58 $60 $68 For Authentication and Encryption use Cryptography $70 $78 $80 $88 $90 $98 For Authentication and Encryption use Secret $A0 $A8 $B0 PAC Write 0 PAC Read 0 $B8 PAC Write 1 PAC Read 1 $C0 PAC Write 2 PAC Read 2 $C8 PAC Write 3 PAC Read 3 Password $D0 PAC Write 4 PAC Read 4 $D8 PAC Write 5 PAC Read 5 $E0 PAC Write 6 PAC Read 6 $E8 PAC Write 7 PAC Read 7 $F0 Reserved Forbidden $F8   10 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

8.1 Security Fuses There are three fuses on the device that must be blown during the device personalization process. Each fuse locks certain portions of the configuration zone as OTP (One-Time Programmable) memory. Fuses are designed for the module manufacturer, card manufacturer and card issuer and should be blown in sequence, although all programming of the device and blowing of the fuses may be performed at one final step. 9. Communication Security Modes Communications between the device and host operate in three basic modes. Standard mode is the default mode for the device after power-up. Authentication mode is activated by a successful authentication sequence. Encryption mode is activated by a successful encryption activation following a successful authentication. Table 9-1. Communication Security Modes(1) Mode Configuration Data User Data Passwords Data Integrity Check Standard Clear Clear Clear MDC(1) Authentication Clear Clear Encrypted MAC(1) Encryption Clear Encrypted Encrypted MAC(1) Note: 1. Configuration data include viewable areas of the configuration zone except the passwords:  MDC: Modification Detection Code  MAC: Message Authentication Code 10. Security Options 10.1 Anti-tearing In the event of a power loss during a write cycle, the integrity of the device’s stored data is recoverable. This function is optional: the host may choose to activate the anti-tearing function, depending on application requirements. When anti-tearing is active, write commands take longer to execute, since more write cycles are required to complete them, and data is limited to a maximum of eight bytes for each write request. Data is written first into a buffer zone in EEPROM instead of the intended destination address, but with the same access conditions. The data is then written in the required location. If this second write cycle is interrupted due to a power loss, the device will automatically recover the data from the system buffer zone at the next power-up. Non-volatile buffering of the data is done automatically by the device. During power-up in applications using Anti-Tearing, the host is required to perform ACK polling in the event that the device needs to carry out the data recovery process. 10.2 Write Lock If a user zone is configured in the write lock mode, the lowest address byte of an 8-byte page constitutes a write access byte for the bytes of that page. Example: The write lock byte at $080 controls the bytes from $081 to $087 Figure 10-1. Write Lock Example Address $0 $1 $2 $3 $4 $5 $6 $7 $080 11011001 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx locked locked locked 11 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

The write lock byte itself may be locked by writing its least significant (rightmost) bit to “0”. Moreover, when write lock mode is activated, the write lock byte can only be programmed – that is, bits written to “0” cannot return to “1”. In the write lock configuration, write operations are limited to writing only one byte at a time. Attempts to write more than one byte will result in writing of just the first byte into the device. 10.3 Password Verification Passwords may be used to protect read and/or write access of any user zone. When a valid password is presented, it is memorized and active until power is turned off, unless a new password is presented or RST becomes active. There are eight password sets that may be used to protect any user zone. Only one password is active at a time. Presenting the correct write password also grants read access privileges. 10.4 Authentication Protocol The access to a user zone may be protected by an authentication protocol. Any one of four keys may be selected to use with a user zone. Authentication success is memorized and active as long as the chip is powered, unless a new authentication is initialized or RST becomes active. If the new authentication request is not validated, the card loses its previous authentication which must be presented again to gain access. Only the latest request is memorized. Figure 10-2. Password and Authentication Operations Device (Card) Host (Reader) AUTHENTICATION Card Number COMPUTE Challenge A VERIFY A Challenge A COMPUTE Challenge B Challenge B VERIFY B READ ACCESS VERIFY RPW Read Password (RPW) DATA Checksum (CS) VERIFY CS WRITE ACCESS VERIFY WPW Write Password (WPW) DATA VERIFY CS CS Write DATA Note: Authentication and password verification may be attempted at any time and in any order. Exceeding corresponding authentication or password attempts trial limit renders subsequent authentication or password verification attempts futile.   12 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

10.5 Cryptographic Message Authentication Codes AT88SC0404CA implements a data validity check function in the standard, authentication or encryption modes of operation. In the standard mode, data validity check is done through a Modification Detection Code (MDC), in which the host may read an MDC from the device in order to verify that the data sent was received correctly. In authentication and encryption modes, the data validity check becomes more powerful since it provides a bidirectional data integrity check and data origin authentication capability in the form of a Message Authentication Codes (MAC). Only the host/device that carried out a valid authentication is capable of computing a valid MAC. While operating in the authentication or encryption modes, the use of MAC is required. For an ingoing command, if the device calculates a MAC different from the MAC transmitted by the host, not only is the command abandoned but the security privilege is revoked. A new authentication and/or encryption activation will be required to reactivate the MAC. 10.6 Encryption The data exchanged between the device and the host during read, write and verify password commands may be encrypted to ensure data confidentiality. The issuer may choose to require encryption for a user zone by settings made in the configuration memory. Any one of four keys may be selected for use with a user zone. In this case, activation of the encryption mode is required in order to read/write data in the zone and only encrypted data will be transmitted. Even if not required, the host may still elect to activate encryption provided the proper keys are known. 10.7 Supervisor Mode Enabling this feature allows the holder of one specific password to gain full access to all eight password sets, including the ability to change passwords. 10.8 Modify Forbidden No write access is allowed in a user zone protected with this feature at any time. The user zone must be written during device personalization prior to blowing the security fuses. 10.9 Program Only For a user zones protected by this feature, data can only be programmed (bits change from a “1” to a “0”), but not erased (bits change from a “0” to a “1”). 13 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

11. Protocol Selection The AT88SC0404CA supports two different communication protocols.  Smartcard Applications: Smartcard applications use ISO 7816-B protocol in asynchronous T = 0 mode for compatibility and interoperability with industry standard smartcard readers.  Embedded Applications: A 2-wire serial interface provides fast and efficient connectivity with other logic devices or microcontrollers. The power-up sequence determines establishes the communication protocol for use within that power cycle. Protocol selection is allowed only during power-up. 11.1 Synchronous 2-wire Serial Interface The synchronous mode is the default mode after power up. This is due to the presence of an internal pull-up on RST. For embedded applications using CryptoMemory in standard plastic packages, this is the only available communication protocol.  Power-up V , RST goes high also CC  After stable V , SCL(CLK) and SDA(I/O) may be driven CC  Once synchronous mode has been selected, it is not possible to switch to asynchronous mode without first powering off the device Figure 11-1. Synchronous 2-wire Protocol Vcc I/O-SDA RST CLK-SCL 1 2 3 4 5 Note: Five clock pulses must be sent before the first command is issued   14 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

11.2 Asynchronous T = 0 Protocol This power-up sequence complies to ISO 7816-3 for a cold reset in smart card applications.  V goes high; RST, I/O (SDA) and CLK (SCL) are low CC  Set I/O (SDA) in receive mode  Provide a clock signal to CLK (SCL)  RST goes high after 400 clock cycles The device will respond with a 64-bit ATR code, including historical bytes to indicate the memory density within the CryptoMemory family. Once asynchronous mode has been selected, it is not possible to switch to synchronous mode without first powering off the device. Figure 11-2. Asynchronous T = 0 Protocol (Gemplus Patent) V cc ATR I/O-SDA RST CLK-SCL 12. Initial Device Programming Enabling the security features of CryptoMemory requires prior personalization. Personalization entails setting up of desired access rights by zones, passwords and key values, programming these values into the configuration memory with verification using simple write and read commands, and then blowing fuses to lock this information in place. Gaining access to the configuration memory requires successful presentation of a secure (or transport) code. The initial signature of the secure (transport) code for the AT88SC0404CA device is $60 57 34. This is the same as the Write 7 password. The user may elect to change the signature of the secure code anytime after successful presentation. After writing and verifying data in the configuration memory, the security fuses must be blown to lock this information in the device. For additional information on personalizing CryptoMemory, please see the application notes Programming CryptoMemory for Embedded Applications and Initializing CryptoMemory for Smart Card Applications from the product page at www.atmel.com/products/securemem. 15 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

13. Ordering Information Delivery Information Voltage Atmel Ordering Code Package Operating Range Range Form Quantity AT88SC0404CA-MJ M2 – J Module - ISO AT88SC0404CA-MP M2 – P Module - ISO Commercial Tape and Reel — Temperature AT88SC0404CA-MJTG M2 – J Module - TWI (0°C to 70°C) AT88SC0404CA-MPTG M2 – P Module - TWI AT88SC0404CA-PU 8P3 Bulk (Tubes) 50 per Tube Green Compliant (Exceeds RoHS) AT88SC0404CA-SH Bulk (Tubes) 100 per Tube 2.7V to 5.5V Industrial Temperature 8S1 AT88SC0404CA-SH-T Tape and Reel 4,000 per Reel (-40°C to 85°C) AT88SC0404CA-TH Bulk (Tubes) 100 per Tube 8X AT88SC0404CA-TH-T Tape and Reel 5,000 per Reel Industrial Temperature (-40°C to 85°C) AT88SC0404CA-Y6H-T 8MA2 Tape and Reel 5,000 per Reel AT88SC0404CA-WI 7 mil Wafer — — Package Type(1) (2) Description M2 – J Module : ISO or TWI M2 ISO 7816 Smart Card Module M2 – P Module : ISO or TWI M2 ISO 7816 Smart Card Module with Atmel® Logo 8P3 8-lead, 0.300” wide, Plastic Dual Inline (PDIP) 8S1 8-lead, 0.150” wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8X 8-lead, 4.4mm body, Plastic Thin Shrink Small Outline (TSSOP) 8MA2 8-lead, 2.0x3.0mm, 0.50mm pitch, Ultra Thin Mini-Map, Dual No Lead (DFN), (MLP 2x3) Note: 1. Formal drawings may be obtained from an Atmel sales office. 2. Both the J and P module packages are used for either ISO (T=0 / 2-wire mode) or TWI (2-wire mode only).   16 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

14. Package Information Ordering Code: MJ or MJTG Ordering Code: MP or MPTG Module Size: M2 Module Size: M2 Dimension*: 12.6 x 11.4 [mm] Dimension*: 12.6 x 11.4 [mm] Glob Top: Round - ∅ 8.5 [mm] Glob Top: Square - 8.8 x 8.8 [mm] Thickness: 0.58 [mm] Thickness: 0.58 [mm] Pitch: 14.25mm Pitch: 14.25mm Note: * The module dimensions listed refer to the dimensions of the exposed metal contact area. The actual dimensions of the module after excise or punching from the carrier tape are generally 0.4mm greater in both directions (i.e., a punched M2 module will yield 13.0 x 11.8mm). 17 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

14.1 Atmel AT88SC0404CA Package Marking Information AT88SC0404CA: Package Marking Information 8-lead SOIC 8-lead PDIP AT88SC AT88SC 0404CA 0404CA H YMXX @ U YYWW Top side only marking this package 8-lead UDFN 8-leadTSSOP 2.0 x 3.0 mm Body 84 YWWH H40 800440 YXX AAAAAAA Note 1: designates pin 1 Note 2:Package drawings are not to scale Catalog Number Truncation AT88SC0404CA Truncation Code ######: 0404CA ##: 44 #: 4 Date Codes Y =Year M = Month YY =Year WW =WorkWeek ofAssembly 2: 2012 6: 2016 A = January 12: 2014 16: 2016 02: Week 2 3: 2013 7: 2017 B = February 13: 2013 17: 2017 04: Week 4 4: 2014 8: 2018 ... 14: 2014 18: 2018 ... 5: 2015 9: 2019 L = December 15: 2015 19: 2019 52: Week 52 Country ofAssembly Lot Number Grade/Lead Finish Material @ = Country ofAssembly AAA...A =AtmelWafer Lot Number U: Industrial/MatteTin Marked on bottom side for PDIP Marked on Bottom side for H: Industrial/NiPdAu only unless in injector mold PDIP only Trace Code AtmelTruncation XX =Trace Code (Atmel Lot Numbers to Correspond to Code) AT: Atmel Example: AA,AB....YZ, ZZ 3/6/12 TITLE DRAWING NO. REV. Package Mark Contact: 88SC0404CASM, AT88SC0404CA Package Marking Information 88SC0404CASM A DL-CSO-Assy_eng@atmel.com   18 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

14.2 Ordering Code: SH 8S1 – 8-lead JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 A – – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.90 BSC D E 6.00 BSC E1 3.90 BSC SIDE VIEW e 1.27 BSC Notes: This drawing is for general information only. L 0.40 – 1.27 Refer to JEDEC Drawing MS-012,VariationAA 0° – 8° for proper dimensions, tolerances, datums, etc. 3/6/2015 TITLE GPC DRAWING NO. REV. 8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing SWB 8S1 H Package Drawing Contact: Small Outline (JEDEC SOIC) packagedrawings@atmel.com 19 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

14.3 Ordering Code: PU 8P3 – 8-lead PDIP   20 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

14.4 Ordering Code: TH 8X – 8-lead TSSOP C 1 Pin 1 indicator(cid:3) this corner E1 E L1 N L Top View End View A b A1 COMMON DIMENSIONS e A2 (Unit of Measure = mm) D SYMBOL MIN NOM MAX NOTE Side View A - - 1.20 A1 0.05 - 0.15 Notes: 1. This drawing is for general information only. A2 0.80 1.00 1.05 Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. D 2.90 3.00 3.10 2, 5 2. Dimension D does not include mold Flash, protrusions or gate E 6.40 BSC burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. E1 4.30 4.40 4.50 3, 5 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25mm b 0.19 0.25 0.30 4 (0.010in) per side. e 0.65 BSC 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess L 0.45 0.60 0.75 of the b dimension at maximum material condition. Dambar L1 1.00 REF cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm. C 0.09 - 0.20 5. Dimension D and E1 to be determined at Datum Plane H. 2/27/14 TITLE GPC DRAWING NO. REV. 8X, 8-lead 4.4mm Body, Plastic Thin Package Drawing Contact: Shrink Small Outline Package (TSSOP) TNR 8X E packagedrawings@atmel.com 21 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

14.5 Ordering Code: Y6H-T 8MA2 – 8-lead Ultra Thin Mini-Map E 1 8 Pin 1 ID 2 7 D 3 6 4 5 TOP VIEW C SIDE VIEW A2 A A1 E2 b (8x) 8 1 7 2 COMMON DIMENSIONS Pin#1 ID (Unit of Measure = mm) D2 6 3 SYMBOL MIN NOM MAX NOTE A 0.50 0.55 0.60 5 4 A1 0.0 0.02 0.05 e (6x) A2 - - 0.55 L (8x) K D 1.90 2.00 2.10 BOTTOM VIEW D2 1.40 1.50 1.60 Notes: 1. This drawing is for general information only. Refer to E 2.90 3.00 3.10 Drawing MO-229, for proper dimensions, tolerances, E2 1.20 1.30 1.40 datums, etc. 2. The Pin #1 ID is a laser-marked feature onTopView. b 0.18 0.25 0.30 3 3. Dimensions b applies to metallized terminal and is C 1.52 REF measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on L 0.30 0.35 0.40 the other end of the terminal, the dimension should e 0.50 BSC not be measured in that radius area. 4. The Pin #1 ID on the BottomView is an orientation K 0.20 - - feature on the thermal pad. 11/26/14 TITLE GPC DRAWING NO. REV. 8MA2, 8-pad 2 x 3 x 0.6mm Body,Thermally Package Drawing Contact: Enhanced Plastic UltraThin Dual Flat No-Lead YNZ 8MA2 G packagedrawings@atmel.com Package (UDFN)   22 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

15. Revision History Doc. Rev. Date Comments 5203IS 07/2015 Add the AT88SC0404CA-TH-T tape and reel option. 5203HS 03/2015 Update 8P3, 8S1, 8X, and 8MA2 package drawings. Add JEDEC SOIC tape and reel package option and update the ordering information table. 5203GS 12/2013 Add package marking information. Update Atmel logos and disclaimer page. 5203FS 12/2011 Update template and package drawings. Replace 8A2 with 8X and 8Y6 with 8MA2. Change AT88SC0404CA-SU to AT88SC0404CA-SH. 5203ES 08/2009 Minor edits and TWI module update. 5203DS 07/2009 Minor updates to package drawing information and ordering information. 5203CS 05/2009 Added Mini-MAP column to Table 1-1 and Mini-MAP pin-out drawing. 5203BS 02/2009 Connection Diagram inserted; DC Characteristics table updated. 5203AS 07/2008 Initial document release. 23 AT88SC0404CA [Summary DATASHEET] Atmel-5203IS-CryptoMem-AT88SC0404CA-Datasheet-Summary_072015

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