AT45DB641E 64-Mbit DataFlash (with Extra 2-Mbits), 1.7V Minimum SPI Serial Flash Memory Features (cid:1) Single 1.7V - 3.6V supply (cid:1) Serial Peripheral Interface (SPI) compatible (cid:1) Supports SPI modes 0 and 3 (cid:1) Supports RapidS™ operation (cid:1) Continuous read capability through entire array (cid:1) Up to 85MHz (cid:1) Low-power read option up to 15MHz (cid:1) Clock-to-output time (t ) of 8ns maximum V (cid:1) User configurable page size (cid:1) 256 bytes per page (cid:1) 264 bytes per page (default) (cid:1) Page size can be factory pre-configured for 256 bytes (cid:1) Two fully independent SRAM data buffers (256/264 bytes) (cid:1) Allows receiving data while reprogramming the main memory array (cid:1) Flexible programming options (cid:1) Byte/Page Program (1 to 256/264 bytes) directly into main memory (cid:1) Buffer Write | Buffer to Main Memory Page Program (cid:1) Flexible erase options (cid:1) Page Erase (256/264 bytes) (cid:1) Block Erase (2KB) (cid:1) Sector Erase (256KB) (cid:1) Chip Erase (64-Mbits) (cid:1) Program and Erase Suspend/Resume (cid:1) Advanced hardware and software data protection features (cid:1) Individual sector protection (cid:1) Individual sector lockdown to make any sector permanently read-only (cid:1) 128-byte, One-Time Programmable (OTP) Security Register (cid:1) 64 bytes factory programmed with a unique identifier (cid:1) 64 bytes user programmable (cid:1) Hardware and software controlled reset options (cid:1) JEDEC Standard Manufacturer and Device ID Read (cid:1) Low-power dissipation (cid:1) 400nA Ultra-Deep Power-Down current (typical) (cid:1) 5µA Deep Power-Down current (typical) (cid:1) 25µA Standby current (typical) (cid:1) 7mA Active Read current (typical) (cid:1) Endurance: 100,000 program/erase cycles per page minimum (cid:1) Data retention: 20 years (cid:1) Complies with full industrial temperature range (cid:1) Green (Pb/Halide-free/RoHS compliant) packaging options (cid:1) 8-lead SOIC (0.208" wide) (cid:1) 8-pad Ultra-thin DFN (5 x 6 x 0.6mm) (cid:1) 8-pad Very-thin DFN (6 x 8 x 1.0mm) (cid:1) 44-ball dBGA (6 x 8 modified ball array) (cid:1) Die in Wafer Form DS-45DB641E-027K–DFLASH–2/2019

Description The AT45DB641E is a 1.7V minimum, serial-interface sequential access Flash memory ideally suited for a wide variety of digital voice, image, program code, and data storage applications. The AT45DB641E also supports the RapidS serial interface for applications requiring very high speed operation. Its 69,206,016 bits of memory are organized as 32,768 pages of 256 bytes or 264 bytes each. In addition to the main memory, the AT45DB641E also contains two SRAM buffers of 256/264 bytes each. Interleaving between both buffers can dramatically increase a system's ability to write a continuous data stream. In addition, the SRAM buffers can be used as additional system scratch pad memory, and E2PROM emulation (bit or byte alterability) can be easily handled with a self-contained three step read-modify-write operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash® uses a serial interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage, and low-power are essential. To allow for simple in-system re-programmability, the AT45DB641E does not require high input voltages for programming. The device operates from a single 1.7V to 3.6V power supply for the erase and program and read operations. The AT45DB641E is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK). All programming and erase cycles are self-timed. 1. Pin Configurations and Pinouts Figure 1-1. Pinouts 8-lead SOIC 8-pad UDFN Top View Top View (through package) SI 1 8 SO SI 1 8 SO SCK 2 7 GND SCK 2 7 GND RESET 3 6 VCC RESET 3 6 VCC CS 4 5 WP CS 4 5 WP 44-ball dBGA T op View Note: 1. The metal pad on the bottom of the DFN package is not internally connected to a voltage potential.This pad can be a “no connect” 1 2 3 4 5 6 or connected to GND. Care must be taken to avoid the Metal Pad shorting on PCB tracks. A (NC) (NC) (NC) (NC) (NC) B (NC) SI RST CS (NC) C (NC) SI SCK RST CS (NC) D (NC) SI SCK RST CS (NC) E (NC) SO GND Vcc WP (NC) F (NC) SO GND Vcc WP (NC) G (NC) SO Vcc WP (NC) H (NC) (NC) (NC) (NC) (NC) AT45DB641E 2 DS-45DB641E-027K–DFLASH–2/2019

Table 1-1. Pin Configurations Asserted Symbol Name and Function State Type Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in the standby mode (not Deep Power-Down mode) and the output pin (SO) will be in a high-impedance state. When the device is deselected, data will not be accepted on the input pin (SI). CS Low Input A high-to-low transition on the CS pin is required to start an operation and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is SCK — Input always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising SI — Input edge of SCK. Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted). Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is SO always clocked out on the falling edge of SCK. The SO pin will be in a high-impedance state — Output whenever the device is deselected (CS is deasserted). Write Protect: When the WP pin is asserted, all sectors specified for protection by the Sector Protection Register will be protected against program and erase operations regardless of whether the Enable Sector Protection command has been issued or not. The WP pin functions independently of the software controlled protection method. After the WP pin goes low, the contents of the Sector Protection Register cannot be modified. If a program or erase command is issued to the device while the WP pin is asserted, the device WP will simply ignore the command and perform no operation. The device will return to the idle Low Input state once the CS pin has been deasserted. The Enable Sector Protection command and the Sector Lockdown command, however, will be recognized by the device when the WP pin is asserted. The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to V whenever possible. CC Reset: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin RESET is brought back to a high level. Low Input The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. If this pin and feature is not utilized, then it is recommended that the RESET pin be driven high externally. Device Power Supply: The V pin is used to supply the source voltage to the device. V CC — Power CC Operations at invalid V voltages may produce spurious results and should not be attempted. CC Ground: The ground reference for the power supply. GND should be connected to the system GND — Ground ground. AT45DB641E 3 DS-45DB641E-027K–DFLASH–2/2019

2. Block Diagram Figure 2-1. Block Diagram WP Flash Memory Array Page (256/264 bytes) Buffer 1 (256/264 bytes) Buffer 2 (256/264 bytes) SCK CS I/O Interface RESET V CC GND SI SO AT45DB641E 4 DS-45DB641E-027K–DFLASH–2/2019

3. Memory Array To provide optimal flexibility, the AT45DB641E memory array is divided into three levels of granularity comprising of sectors, blocks, and pages. Figure 3-1, Memory Architecture Diagram illustrates the breakdown of each level and details the number of pages per sector and block. Program operations to the DataFlash can be done at the full page level or at the byte level (a variable number of bytes). The erase operations can be performed at the chip, sector, block, or page level. Figure 3-1. Memory Architecture Diagram Sector Architecture Block Architecture Page Architecture Sector 0a = 8 pages Sector 0a Block 0 8 Pages Page 0 2,048 / 2,112 bytes Block 1 Page 1 S2e6c0t,o09r 60 b/ 2=6 18,,021264 pbaygteess or 0b Block 2 Block 0 ct Page 6 e S Page 7 Block 126 Sector 1 = 1,024 pages Block 127 Page 8 262,144 / 270,336 bytes Page 9 Block 128 1 Block 129 k c 2S6e2c,t1o4r4 2 / =2 710,0,32346 p baygteess ctor 1 Blo Page 14 e S Page 15 Block 254 Page 16 Block 255 Page 17 Block 256 Page 18 Sector 30 = 1,024 pages Block 257 262,144 / 270,336 bytes Sector 31 = 1,,024 pages 262,144 / 270,336 bytes Block 4,094 Page 32,766 Block 4,095 Page 32,767 Block = 2,048 / 2,112 bytes Page = 256 / 264 bytes AT45DB641E 5 DS-45DB641E-027K–DFLASH–2/2019

4. Device Operation The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Table 15-1 on page 40 through Table 15-4 on page 41. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address location through the SI (Serial Input) pin. All instructions, addresses, and data are transferred with the Most Significant Bit (MSB) first. Three address bytes are used to address memory locations in either the main memory array or in one of the SRAM buffers. The three address bytes will be comprised of a number of dummy bits and a number of actual device address bits, with the number of dummy bits varying depending on the operation being performed and the selected device page size. Buffer addressing for the standard DataFlash page size (264 bytes) is referenced in the datasheet using the terminology BFA8 - BFA0 to denote the 9 address bits required to designate a byte address within a buffer. The main memory addressing is referenced using the terminology PA14 - PA0 and BA8 - BA0, where PA14 - PA0 denotes the 15 address bits required to designate a page address, and BA8 - BA0 denotes the 9 address bits required to designate a byte address within the page. Therefore, when using the standard DataFlash page size, a total of 24 address bits are used. For the “power of 2” binary page size (256 bytes), the buffer addressing is referenced in the datasheet using the conventional terminology BFA7 - BFA0 to denote the eight address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology A22 - A0, where A22 - A8 denotes the 15 address bits required to designate a page address, and A7 - A0 denotes the 8 address bits required to designate a byte address within a page. Therefore, when using the binary page size, a total of 23 address bits are used. AT45DB641E 6 DS-45DB641E-027K–DFLASH–2/2019

5. Read Commands By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please see Section 25., Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3 diagrams in this datasheet for details on the clock cycle sequences for each mode. 5.1 Continuous Array Read (Legacy Command: E8h Opcode) By supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one continuous read from memory to be performed without the need for additional address sequences. To perform a Continuous Array Read using the standard DataFlash page size (264 bytes), an opcode of E8h must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and four dummy bytes. The first 15 bits (PA14 - PA0) of the 24-bit address sequence specify which page of the main memory array to read and the last 9 (BA8 - BA0) of the 24-bit address sequence specify the starting byte address within the page. To perform a Continuous Array Read using the binary page size (256 bytes), an opcode of E8h must be clocked into the device followed by three address bytes and four dummy bytes. The first 15 bits (A22 - A8) of the 23-bit address sequence specify which page of the main memory array to read and the last 8 bits (A7 - A0) of the 23-bit address sequence specify the starting byte address within the page. The dummy bytes that follow the address bytes are needed to initialize the read operation. Following the dummy bytes, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the f specification. The Continuous Array Read CAR1 bypasses the data buffers and leaves the contents of the buffers unchanged. Warning: This command is not recommended for new designs. 5.2 Continuous Array Read (High Frequency Mode: 1Bh Opcode) This command can be used to read the main memory array sequentially at the highest possible operating clock frequency up to the maximum specified by f . To perform a Continuous Array Read using the standard DataFlash CAR4 page size (264 bytes), the CS pin must first be asserted, and then an opcode of 1Bh must be clocked into the device followed by three address bytes and two dummy bytes. The first 15 bits (PA14 - PA0) of the 24-bit address sequence specify which page of the main memory array to read and the last 9 bits (BA8 - BA0) of the 24-bit address sequence specify the starting byte address within the page. To perform a Continuous Array Read using the binary page size (256 bytes), the opcode 1Bh must be clocked into the device followed by three address bytes (A22 - A0) and two dummy bytes. Following the dummy bytes, additional clock pulses on the SCK pin will result in data being output on the SO (Serial Output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. AT45DB641E 7 DS-45DB641E-027K–DFLASH–2/2019

A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the f specification. The Continuous Array CAR4 Read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.3 Continuous Array Read (High Frequency Mode: 0Bh Opcode) This command can be used to read the main memory array sequentially at higher clock frequencies up to the maximum specified by f . To perform a Continuous Array Read using the standard DataFlash page size (264 bytes), the CS pin CAR1 must first be asserted, and then an opcode of 0Bh must be clocked into the device followed by three address bytes and one dummy byte. The first 15 bits (PA14 - PA0) of the 24-bit address sequence specify which page of the main memory array to read and the last 9 bits (BA8 - BA0) of the 24-bit address sequence specify the starting byte address within the page. To perform a Continuous Array Read using the binary page size (256 bytes), the opcode 0Bh must be clocked into the device followed by three address bytes (A22 - A0) and one dummy byte. Following the dummy byte, additional clock pulses on the SCK pin will result in data being output on the SO pin. The CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the f specification. The Continuous Array CAR1 Read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.4 Continuous Array Read (Low Frequency Mode: 03h Opcode) This command can be used to read the main memory array sequentially at lower clock frequencies up to maximum specified by f . Unlike the previously described read commands, this Continuous Array Read command for the lower CAR2 clock frequencies does not require the clocking in of dummy bytes after the address byte sequence. To perform a Continuous Array Read using the standard DataFlash page size (264 bytes), the CS pin must first be asserted, and then an opcode of 03h must be clocked into the device followed by three address bytes. The first 15 bits (PA14 - PA0) of the 24-bit address sequence specify which page of the main memory array to read and the last 9 bits (BA8 - BA0) of the address sequence specify the starting byte address within the page. To perform a Continuous Array Read using the binary page size (256 bytes), the opcode 03h must be clocked into the device followed by three address bytes (A22 - A0). Following the address bytes, additional clock pulses on the SCK pin will result in data being output on the SO pin. The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the f specification. The Continuous Array CAR2 Read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.5 Continuous Array Read (Low Power Mode: 01h Opcode) This command is ideal for applications that want to minimize power consumption and do not need to read the memory array at high frequencies. Like the 03h opcode, this Continuous Array Read command allows reading the main memory array sequentially without the need for dummy bytes to be clocked in after the address byte sequence. The memory can be read at clock frequencies up to maximum specified by f . To perform a Continuous Array Read using the standard CAR3 DataFlash page size (264 bytes), the CS pin must first be asserted, and then an opcode of 01h must be clocked into the device followed by three address bytes. The first 15 bits (PA14 - PA0) of the 24-bit address sequence specify which page AT45DB641E 8 DS-45DB641E-027K–DFLASH–2/2019

of the main memory array to read and the last 9 bits (BA8 - BA0) of the 24-bit address sequence specify the starting byte address within the page. To perform a Continuous Array Read using the binary page size (256 bytes), the opcode 01h must be clocked into the device followed by three address bytes (A22 - A0). Following the address bytes, additional clock pulses on the SCK pin will result in data being output on the SO pin. The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the f specification. The Continuous Array CAR3 Read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.6 Main Memory Page Read A Main Memory Page Read allows the reading of data directly from a single page in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read using the standard DataFlash page size (264 bytes), an opcode of D2h must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and four dummy bytes. The first 15 bits (PA14 - PA0) of the 24-bit address sequence specify the page in main memory to be read and the last 9 bits (BA8 - BA0) of the 24-bit address sequence specify the starting byte address within that page. To start a page read using the binary page size (256 bytes), the opcode D2h must be clocked into the device followed by three address bytes and four dummy bytes. The first 15 bits (A22 - A8) of the 23-bit address sequence specify which page of the main memory array to read, and the last 8 bits (A7 - A0) of the 23-bit address sequence specify the starting byte address within that page. The dummy bytes that follow the address bytes are sent to initialize the read operation. Following the dummy bytes, the additional pulses on SCK result in data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of data. Unlike the Continuous Array Read command, when the end of a page in main memory is reached, the device will continue reading back at the beginning of the same page rather than the beginning of the next page. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Main Memory Page Read is defined by the f specification. The Main Memory Page SCK Read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.7 Buffer Read The SRAM data buffers can be accessed independently from the main memory array, and utilizing the Buffer Read command allows data to be sequentially read directly from either one of the buffers. Four opcodes, D4h or D1h for Buffer 1 and D6h or D3h for Buffer 2, can be used for the Buffer Read command. The use of each opcode depends on the maximum SCK frequency that will be used to read data from the buffers. The D4h and D6h opcode can be used at any SCK frequency up to the maximum specified by f while the D1h and D3h opcode can be used for lower CAR1 frequency read operations up to the maximum specified by f . CAR2 To perform a Buffer Read using the standard DataFlash buffer size (264 bytes), the opcode must be clocked into the device followed by three address bytes comprised of 15 dummy bits and 9 buffer address bits (BFA8 - BFA0). To perform a Buffer Read using the binary buffer size (256 bytes), the opcode must be clocked into the device followed by three address bytes comprised of 16 dummy bits and 8 buffer address bits (BFA7 - BFA0). Following the address bytes, one dummy byte must be clocked into the device to initialize the read operation if using opcodes D4h or D6h. The CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte (if using opcodes D4h or D6h), and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). AT45DB641E 9 DS-45DB641E-027K–DFLASH–2/2019

6. Program and Erase Commands 6.1 Buffer Write Utilizing the Buffer Write command allows data clocked in from the SI pin to be written directly into either one of the SRAM data buffers. To load data into a buffer using the standard DataFlash buffer size (264 bytes), an opcode of 84h for Buffer 1 or 87h for Buffer 2 must be clocked into the device followed by three address bytes comprised of 15 dummy bits and 9 buffer address bits (BFA8 - BFA0). The 9 buffer address bits specify the first byte in the buffer to be written. To load data into a buffer using the binary buffer size (256 bytes), an opcode of 84h for Buffer 1 or 87h for Buffer 2, must be clocked into the device followed by 16 dummy bits and 8 buffer address bits (BFA7 - BFA0). The 8 buffer address bits specify the first byte in the buffer to be written. After the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. If the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. Data will continue to be loaded into the buffer until a low-to-high transition is detected on the CS pin. 6.2 Buffer to Main Memory Page Program with Built-In Erase The Buffer to Main Memory Page Program with Built-In Erase command allows data that is stored in one of the SRAM buffers to be written into an erased or programmed page in the main memory array. It is not necessary to pre-erase the page in main memory to be written because this command will automatically erase the selected page prior to the program cycle. To perform a Buffer to Main Memory Page Program with Built-In Erase using the standard DataFlash page size (264 bytes), an opcode of 83h for Buffer 1 or 86h for Buffer 2 must be clocked into the device followed by three address bytes comprised of 15 page address bits (PA14 - PA0) that specify the page in the main memory to be written, and 9 dummy bits. To perform a Buffer to Main Memory Page Program with Built-In Erase using the binary page size (256 bytes), an opcode of 83h for Buffer 1 or 86h for Buffer 2 must be clocked into the device followed by three address bytes comprised of 1 dummy bit, 15 page address bits (A22 - A8) that specify the page in the main memory to be written, and 8 dummy bits. When a low-to-high transition occurs on the CS pin, the device will first erase the selected page in main memory (the erased state is a Logic 1) and then program the data stored in the appropriate buffer into that same page in main memory. Both the erasing and the programming of the page are internally self-timed and should take place in a maximum time of t . During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy. EP The device also incorporates an intelligent erase and program algorithm that can detect when a byte location fails to erase or program properly. If an erase or programming error arises, it will be indicated by the EPE bit in the Status Register. 6.3 Buffer to Main Memory Page Program without Built-In Erase The Buffer to Main Memory Page Program without Built-In Erase command allows data that is stored in one of the SRAM buffers to be written into a pre-erased page in the main memory array. It is necessary that the page in main memory to be written be previously erased in order to avoid programming errors. To perform a Buffer to Main Memory Page Program without Built-In Erase using the standard DataFlash page size (264 bytes), an opcode of 88h for Buffer 1 or 89h for Buffer 2 must be clocked into the device followed by three address bytes comprised of 15 page address bits (PA14 - PA0) that specify the page in the main memory to be written, and 9 dummy bits. To perform a Buffer to Main Memory Page Program using the binary page size (256 bytes), an opcode of 88h for Buffer 1 or 89h for Buffer 2 must be clocked into the device followed by three address bytes comprised of 1 dummy bit, 15 page address bits (A22 - A8) that specify the page in the main memory to be written, and 8 dummy bits. AT45DB641E 10 DS-45DB641E-027K–DFLASH–2/2019

When a low-to-high transition occurs on the CS pin, the device will program the data stored in the appropriate buffer into the specified page in the main memory. The page in main memory that is being programmed must have been previously erased using one of the erase commands (Page Erase, Block Erase, Sector Erase, or Chip Erase). The programming of the page is internally self-timed and should take place in a maximum time of t . During this time, the RDY/BUSY bit in the P Status Register will indicate that the device is busy. The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register. 6.4 Main Memory Page Program through Buffer with Built-In Erase The Main Memory Page Program through Buffer with Built-In Erase command combines the Buffer Write and Buffer to Main Memory Page Program with Built-In Erase operations into a single operation to help simplify application firmware development. With the Main Memory Page Program through Buffer with Built-In Erase command, data is first clocked into either Buffer 1 or Buffer 2, the addressed page in memory is then automatically erased, and then the contents of the appropriate buffer are programmed into the just-erased main memory page. To perform a Main Memory Page Program through Buffer using the standard DataFlash page size (264 bytes), an opcode of 82h for Buffer 1 or 85h for Buffer 2 must first be clocked into the device followed by three address bytes comprised of 15 page address bits (PA14 - PA0) that specify the page in the main memory to be written, and 9 buffer address bits (BFA8 - BFA0) that select the first byte in the buffer to be written. To perform a Main Memory Page Program through Buffer using the binary page size (256 bytes), an opcode of 82h for Buffer 1 or 85h for Buffer 2 must first be clocked into the device followed by three address bytes comprised of 1 dummy bit, 15 page address bits (A22 - A8) that specify the page in the main memory to be written, and 8 buffer address bits (BFA7 - BFA0) that select the first byte in the buffer to be written. After all address bytes have been clocked in, the device will take data from the input pin (SI) and store it in the specified data buffer. If the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. When there is a low-to-high transition on the CS pin, the device will first erase the selected page in main memory (the erased state is a Logic 1) and then program the data stored in the buffer into that main memory page. Both the erasing and the programming of the page are internally self-timed and should take place in a maximum time of t . During this time, the EP RDY/BUSY bit in the Status Register will indicate that the device is busy. The device also incorporates an intelligent erase and programming algorithm that can detect when a byte location fails to erase or program properly. If an erase or program error arises, it will be indicated by the EPE bit in the Status Register. 6.5 Main Memory Byte/Page Program through Buffer 1 without Built-In Erase The Main Memory Byte/Page Program through Buffer 1 without Built-In Erase command combines both the Buffer Write and Buffer to Main Memory Program without Built-In Erase operations to allow any number of bytes (1 to 256/264 bytes) to be programmed directly into previously erased locations in the main memory array. With the Main Memory Byte/Page Program through Buffer 1 without Built-In Erase command, data is first clocked into Buffer 1, and then only the bytes clocked into the buffer are programmed into the pre-erased byte locations in main memory. Multiple bytes up to the page size can be entered with one command sequence. To perform a Main Memory Byte/Page Program through Buffer 1 using the standard DataFlash page size (264 bytes), an opcode of 02h must first be clocked into the device followed by three address bytes comprised of 15 page address bits (PA14 - PA0) that specify the page in the main memory to be written, and 9 buffer address bits (BFA8 - BFA0) that select the first byte in the buffer to be written. After all address bytes are clocked in, the device will take data from the input pin (SI) and store it in Buffer 1. Any number of bytes (1 to 264) can be entered. If the end of the buffer is reached, then the device will wrap around back to the beginning of the buffer. To perform a Main Memory Byte/Page Program through Buffer 1 using the binary page size (256 bytes), an opcode of 02h for Buffer 1 using must first be clocked into the device followed by three address bytes comprised of 1 dummy bit, 15 page address bits (A22 - A8) that specify the page in the main memory to be written, and 8 buffer address bits (BFA7 - BFA0) that selects the first byte in the buffer to be written. After all address bytes are clocked in, the device will take data from the input pin (SI) and store it in Buffer 1. Any number of bytes (1 to 256) can be entered. If the end of the buffer is AT45DB641E 11 DS-45DB641E-027K–DFLASH–2/2019

reached, then the device will wrap around back to the beginning of the buffer. When using the binary page size, the page and buffer address bits correspond to a 23-bit logical address (A22-A0) in the main memory. After all data bytes have been clocked into the device, a low-to-high transition on the CS pin will start the program operation in which the device will program the data stored in Buffer 1 into the main memory array. Only the data bytes that were clocked into the device will be programmed into the main memory. Example: If only two data bytes were clocked into the device, then only two bytes will be programmed into main memory and the remaining bytes in the memory page will remain in their previous state. The CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the operation will be aborted and no data will be programmed. The programming of the data bytes is internally self-timed and should take place in a maximum time of t (the program time will be a multiple of the t time depending on the number of bytes being P BP programmed). During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy. The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register. 6.6 Read-Modify-Write A completely self-contained read-modify-write operation can be performed to reprogram any number of sequential bytes in a page in the main memory array without affecting the rest of the bytes in the same page. This command allows the device to easily emulate an EEPROM by providing a method to modify a single byte or more in the main memory in a single operation, without the need for pre-erasing the memory or the need for any external RAM buffers. The Read-Modify-Write command is essentially a combination of the Main Memory Page to Buffer Transfer, Buffer Write, and Buffer to Main Memory Page Program with Built-in Erase commands. To perform a Read-Modify-Write using the standard DataFlash page size (264 bytes), an opcode of 58h for Buffer 1 or 59h for Buffer 2 must be clocked into the device followed by three address bytes comprised of 15 page address bits (PA14 - PA0) that specify the page in the main memory to be written, and 9 byte address bits (BA8 - BA0) that designate the starting byte address within the page to reprogram. To perform a Read-Modify-Write using the binary page size (256 bytes), an opcode of 58h for Buffer 1 or 59h for Buffer 2 must be clocked into the device followed by three address bytes comprised of 1 dummy bit, 15 page address bits (A22 - A8) that specify the page in the main memory to be written, and 8 byte address bits (A7 - A0) designate the starting byte address within the page to reprogram. After the address bytes have been clocked in, any number of sequential data bytes from one to 256/264 bytes can be clocked into the device. If the end of the buffer is reached when clocking in the data, then the device will wrap around back to the beginning of the buffer. After all data bytes have been clocked into the device, a low-to-high transition on the CS pin will start the self-contained, internal read-modify-write operation. Only the data bytes that were clocked into the device will be reprogrammed in the main memory. Example: If only one data byte was clocked into the device, then only one byte in main memory will be reprogrammed and the remaining bytes in the main memory page will remain in their previous state. The CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the operation will be aborted and no data will be programmed. The reprogramming of the data bytes is internally self-timed and should take place in a maximum time of t . During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy. P The device also incorporates an intelligent erase and programming algorithm that can detect when a byte location fails to erase or program properly. If an erase or program error arises, it will be indicated by the EPE bit in the Status Register. Note: The Read-Modify-Write command uses the same opcodes as the Auto Page Rewrite command. If no data bytes are clocked into the device, then the device will perform an Auto Page Rewrite operation. See the Auto Page Rewrite command description on page 27 for more details. AT45DB641E 12 DS-45DB641E-027K–DFLASH–2/2019

6.7 Page Erase The Page Erase command can be used to individually erase any page in the main memory array allowing the Buffer to Main Memory Page Program without Built-In Erase command or the Main Memory Byte/Page Program through Buffer 1 command to be utilized at a later time. To perform a Page Erase with the standard DataFlash page size (264 bytes), an opcode of 81h must be clocked into the device followed by three address bytes comprised of 15 page address bits (PA14 - PA0) that specify the page in the main memory to be erased, and 9 dummy bits. To perform a Page Erase with the binary page size (256 bytes), an opcode of 81h must be clocked into the device followed by three address bytes comprised of 1 dummy bit, 15 page address bits (A22 - A8) that specify the page in the main memory to be erased, and 8 dummy bits. When a low-to-high transition occurs on the CS pin, the device will erase the selected page (the erased state is a Logic 1). The erase operation is internally self-timed and should take place in a maximum time of t . During this time, the PE RDY/BUSY bit in the Status Register will indicate that the device is busy. The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If an erase error arises, it will be indicated by the EPE bit in the Status Register. 6.8 Block Erase The Block Erase command can be used to erase a block of eight pages at one time. This command is useful when needing to pre-erase larger amounts of memory and is more efficient than issuing eight separate Page Erase commands. To perform a Block Erase with the standard DataFlash page size (264 bytes), an opcode of 50h must be clocked into the device followed by three address bytes comprised of 12 page address bits (PA14 - PA3), and 12 dummy bits. The 12 page address bits are used to specify which block of 8 pages is to be erased. To perform a Block Erase with the binary page size (256 bytes), an opcode of 50h must be clocked into the device followed by three address bytes comprised of 1 dummy bit, 12 page address bits (A22 - A11), and 11 dummy bits. The 12 page address bits are used to specify which block of 8 pages is to be erased. When a low-to-high transition occurs on the CS pin, the device will erase the selected block of eight pages. The erase operation is internally self-timed and should take place in a maximum time of t . During this time, the RDY/BUSY bit in BE the Status Register will indicate that the device is busy. The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If an erase error arises, it will be indicated by the EPE bit in the Status Register. Table 6-1. Block Erase Addressing PA14 PA13 PA12 PA11/ PA10 PA9/ PA8/ PA7/ PA6/ PA5/ PA4/ PA3/ PA2/ PA1/ PA0/ /A22 /A21 /A20 A19 /A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 Block 0 0 0 0 0 0 0 0 0 0 0 0 X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 X X X 1 0 0 0 0 0 0 0 0 0 0 1 0 X X X 2 0 0 0 0 0 0 0 0 0 0 1 1 X X X 3 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 1 1 1 1 1 1 1 1 1 1 0 0 X X X 4092 1 1 1 1 1 1 1 1 1 1 0 1 X X X 4093 1 1 1 1 1 1 1 1 1 1 1 0 X X X 4094 1 1 1 1 1 1 1 1 1 1 1 1 X X X 4095 AT45DB641E 13 DS-45DB641E-027K–DFLASH–2/2019

6.9 Sector Erase The Sector Erase command can be used to individually erase any sector in the main memory. The main memory array is comprised of thirty-three sectors, and only one sector can be erased at a time. To perform an erase of Sector 0a or Sector 0b with the standard DataFlash page size (264 bytes), an opcode of 7Ch must be clocked into the device followed by three address bytes comprised of 12 page address bits (PA14 - PA3), and 12 dummy bits. To perform a Sector 1-31 erase, an opcode of 7Ch must be clocked into the device followed by three address bytes comprised of 5 page address bits (PA14 - PA10), and 19 dummy bits. To perform a Sector 0a or Sector 0b erase with the binary page size (256 bytes), an opcode of 7Ch must be clocked into the device followed by three address bytes comprised of 1 dummy bit, 12 page address bits (A22 - A11), and 11 dummy bits. To perform a Sector 1-31 erase, an opcode of 7Ch must be clocked into the device followed by 1 dummy bit, 5 page address bits (A22 - A18), and 18 dummy bits. The page address bits are used to specify any valid address location within the sector to be erased. When a low-to high transition occurs on the CS pin, the device will erase the selected sector. The erase operation is internally self-timed and should take place in a maximum time of t . During this time, the RDY/BUSY bit in the Status Register will SE indicate that the device is busy. The device also incorporates an intelligent algorithm that can detect when a byte location fails to erase properly. If an erase error arises, it will be indicated by the EPE bit in the Status Register. Table 6-2. Sector Erase Addressing PA14 PA13 PA12 PA11/ PA10 PA9/ PA8/ PA7/ PA6/ PA5/ PA4/ PA3/ PA2/ PA1/ PA0/ /A22 /A21 /A20 A19 /A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 Sector 0 0 0 0 0 0 0 0 0 0 0 0 X X X 0a 0 0 0 0 0 0 0 0 0 0 0 1 X X X 0b 0 0 0 0 1 X X X X X X X X X X 1 0 0 0 1 0 X X X X X X X X X X 2 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 1 1 1 0 0 X X X X X X X X X X 28 1 1 1 0 1 X X X X X X X X X X 29 1 1 1 1 0 X X X X X X X X X X 30 1 1 1 1 1 X X X X X X X X X X 31 6.10 Chip Erase The Chip Erase command allows the entire main memory array to be erased can be erased at one time. To execute the Chip Erase command, a 4-byte command sequence of C7h, 94h, 80h, and 9Ah must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to start the erase process. The erase operation is internally self-timed and should take place in a time of t . During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy. CE The Chip Erase command will not affect sectors that are protected or locked down; the contents of those sectors will remain unchanged. Only those sectors that are not protected or locked down will be erased. AT45DB641E 14 DS-45DB641E-027K–DFLASH–2/2019

The WP pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle completes. The device also incorporates an intelligent algorithm that can detect when a byte location fails to erase properly. If an erase error arises, it will be indicated by the EPE bit in the Status Register. Table 6-3. Chip Erase Command Command Byte 1 Byte 2 Byte 3 Byte 4 Chip Erase C7h 94h 80h 9Ah Figure 6-1. Chip Erase CS C7h 94h 80h 9Ah Each transition represents eight bits 6.11 Program/Erase Suspend In some code and data storage applications, it may not be possible for the system to wait the milliseconds required for the Flash memory to complete a program or erase cycle. The Program/Erase Suspend command allows a program or erase operation in progress to a particular 256KB sector of the main memory array to be suspended so that other device operations can be performed. Example: By suspending an erase operation to a particular sector, the system can perform functions such as a program or read operation within a different 256KB sector. Other device operations, such as Read Status Register, can also be performed while a program or erase operation is suspended. To perform a Program/Erase Suspend, an opcode of B0h must be clocked into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the program or erase operation currently in progress will be suspended within a time of t . One of the Program Suspend SUSP bits (PS1 or PS2) or the Erase Suspend bit (ES) in the Status Register will then be set to the Logic 1 state. In addition, the RDY/BUSY bit in the Status Register will indicate that the device is ready for another operation. Read operations are not allowed to a 256KB sector that has had its program or erase operation suspended. If a read is attempted to a suspended sector, then the device will output undefined data. Therefore, when performing a Continuous Array Read operation and the device's internal address counter increments and crosses the sector boundary to a suspended sector, the device will then start outputting undefined data continuously until the address counter increments and crosses a sector boundary to an unsuspended sector. A program operation is not allowed to a sector that has been erase suspended. If a program operation is attempted to an erase suspended sector, then the program operation will abort. During an Erase Suspend, a program operation to a different 256KB sector can be started and subsequently suspended. This results in a simultaneous Erase Suspend/Program Suspend condition and will be indicated by the states of both the ES and PS1 or PS2 bits in the Status Register being set to a Logic 1. If a Reset command is performed, or if the RESET pin is asserted while a sector is erase suspended, then the suspend operation will be aborted and the contents of the sector will be left in an undefined state. However, if a reset is performed while a page is program or erase suspended, the suspend operation will abort but only the contents of the page that was being programmed or erased will be undefined; the remaining pages in the 256KB sector will retain their previous contents. AT45DB641E 15 DS-45DB641E-027K–DFLASH–2/2019

Table 6-4. Operations Allowed and Not Allowed During Suspend Operation During Operation During Program Suspend in Program Suspend in Operation During Command Buffer 1 (PS1) Buffer 2 (PS2) Erase Suspend (ES) Read Commands Read Array (All Opcodes) Allowed Allowed Allowed Read Buffer 1 (All Opcodes) Allowed Allowed Allowed Read Buffer 2 (All Opcodes) Allowed Allowed Allowed Program and Erase Commands Buffer 1 Write Not Allowed Allowed Allowed Buffer 2 Write Allowed Not Allowed Allowed Buffer 1 to Memory Program w/ Erase Not Allowed Not Allowed Not Allowed Buffer 2 to Memory Program w/ Erase Not Allowed Not Allowed Not Allowed Buffer 1 to Memory Program w/o Erase Not Allowed Not Allowed Allowed Buffer 2 to Memory Program w/o Erase Not Allowed Not Allowed Allowed Memory Program through Buffer 1 w/ Erase Not Allowed Not Allowed Not Allowed Memory Program through Buffer 2 w/ Erase Not Allowed Not Allowed Not Allowed Memory Program through Buffer 1 w/o Erase Not Allowed Not Allowed Allowed Auto Page Rewrite through Buffer 1 Not Allowed Not Allowed Not Allowed Auto Page Rewrite through Buffer 2 Not Allowed Not Allowed Not Allowed Read-Modify-Write through Buffer 1 Not Allowed Not Allowed Not Allowed Read-Modify-Write through Buffer 2 Not Allowed Not Allowed Not Allowed Page Erase Not Allowed Not Allowed Not Allowed Block Erase Not Allowed Not Allowed Not Allowed Sector Erase Not Allowed Not Allowed Not Allowed Chip Erase Not Allowed Not Allowed Not Allowed Protection and Security Commands Enable Sector Protection Not Allowed Not Allowed Not Allowed Disable Sector Protection Not Allowed Not Allowed Not Allowed Erase Sector Protection Register Not Allowed Not Allowed Not Allowed Program Sector Protection Register Not Allowed Not Allowed Not Allowed Read Sector Protection Register Allowed Allowed Allowed Sector Lockdown Not Allowed Not Allowed Not Allowed Read Sector Lockdown Allowed Allowed Allowed Freeze Sector Lockdown State Not Allowed Not Allowed Not Allowed Program Security Register Not Allowed Not Allowed Not Allowed Read Security Register Allowed Allowed Allowed Additional Commands Main Memory to Buffer 1 Transfer Not Allowed Allowed Allowed Main Memory to Buffer 2 Transfer Allowed Not Allowed Allowed Main Memory to Buffer 1 Compare Not Allowed Allowed Allowed Main Memory to Buffer 2 Compare Allowed Not Allowed Allowed Enter Deep Power-Down Not Allowed Not Allowed Not Allowed Resume from Deep Power-Down Not Allowed Not Allowed Not Allowed Enter Ultra-Deep Power-Down mode Not Allowed Not Allowed Not Allowed Read Configuration Register Allowed Allowed Allowed Read Status Register Allowed Allowed Allowed Read Manufacturer and Device ID Allowed Allowed Allowed Reset (via Hardware or Software) Allowed Allowed Allowed AT45DB641E 16 DS-45DB641E-027K–DFLASH–2/2019

6.12 Program/Erase Resume The Program/Erase Resume command allows a suspended program or erase operation to be resumed and continue where it left off. To perform a Program/Erase Resume, an opcode of D0h must be clocked into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the program or erase operation currently suspended will be resumed within a time of t . The PS1 bit, PS2 bit, or ES bit in RES the Status Register will then be reset back to a Logic 0 state to indicate that the program or erase operation is no longer suspended. In addition, the RDY/BUSY bit in the Status Register will indicate that the device is busy performing a program or erase operation. During a simultaneous Erase Suspend/Program Suspend condition, issuing the Program/Erase Resume command will result in the program operation resuming first. After the program operation has been completed, the Program/Erase Resume command must be issued again in order for the erase operation to be resumed. While the device is busy resuming a program or erase operation, any attempts at issuing the Program/Erase Suspend command will be ignored. Therefore, if a resumed program or erase operation needs to be subsequently suspended again, the system must either wait the entire t time before issuing the Program/Erase Suspend command, or it must RES check the status of the RDY/BUSY bit or the appropriate PS1, PS2, or ES bit in the Status Register to determine if the previously suspended program or erase operation has resumed. AT45DB641E 17 DS-45DB641E-027K–DFLASH–2/2019

7. Sector Protection Two protection methods, hardware and software controlled, are provided for protection against inadvertent or erroneous program and erase cycles. The software controlled method relies on the use of software commands to enable and disable sector protection while the hardware controlled method employs the use of the Write Protect (WP) pin. The selection of which sectors that are to be protected or unprotected against program and erase operations is specified in the Nonvolatile Sector Protection Register. The status of whether or not sector protection has been enabled or disabled by either the software or the hardware controlled methods can be determined by checking the Status Register. 7.1 Software Sector Protection Software controlled protection is useful in applications in which the WP pin is not or cannot be controlled by a host processor. In such instances, the WP pin may be left floating (the WP pin is internally pulled high) and sector protection can be controlled using the Enable Sector Protection and Disable Sector Protection commands. If the device is power cycled, then the software controlled protection will be disabled. Once the device is powered up, the Enable Sector Protection command should be reissued if sector protection is desired and if the WP pin is not used. 7.1.1 Enable Sector Protection Sectors specified for protection in the Sector Protection Register can be protected from program and erase operations by issuing the Enable Sector Protection command. To enable the sector protection, a 4-byte command sequence of 3Dh, 2Ah, 7Fh, and A9h must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to enable the Sector Protection. Table 7-1. Enable Sector Protection Command Command Byte 1 Byte 2 Byte 3 Byte 4 Enable Sector Protection 3Dh 2Ah 7Fh A9h Figure 7-1. Enable Sector Protection CS SI 3Dh 2Ah 7Fh A9h Each transition represents eight bits 7.1.2 Disable Sector Protection To disable the sector protection, a 4-byte command sequence of 3Dh, 2Ah, 7Fh, and 9Ah must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to disable the sector protection. Table 7-2. Disable Sector Protection Command Command Byte 1 Byte 2 Byte 3 Byte 4 Disable Sector Protection 3Dh 2Ah 7Fh 9Ah AT45DB641E 18 DS-45DB641E-027K–DFLASH–2/2019

Figure 7-2. Disable Sector Protection CS SI 3Dh 2Ah 7Fh 9Ah Each transition represents eight bits 7.2 Hardware Controlled Protection Sectors specified for protection in the Sector Protection Register and the Sector Protection Register itself can be protected from program and erase operations by asserting the WP pin and keeping the pin in its asserted state. The Sector Protection Register and any sector specified for protection cannot be erased or programmed as long as the WP pin is asserted. In order to modify the Sector Protection Register, the WP pin must be deasserted. If the WP pin is permanently connected to GND, then the contents of the Sector Protection Register cannot be changed. If the WP pin is deasserted or permanently connected to V , then the contents of the Sector Protection Register can be modified. CC The WP pin will override the software controlled protection method but only for protecting the sectors. Example: If the sectors were not previously protected by the Enable Sector Protection command, then simply asserting the WP pin would enable the sector protection within the maximum specified t time. When the WPE WP pin is deasserted, however, the sector protection would no longer be enabled (after the maximum specified t time) as long as the Enable Sector Protection command was not issued while the WP pin was WPD asserted. If the Enable Sector Protection command was issued before or while the WP pin was asserted, then simply deasserting the WP pin would not disable the sector protection. In this case, the Disable Sector Protection command would need to be issued while the WP pin is deasserted to disable the sector protection. The Disable Sector Protection command is also ignored whenever the WP pin is asserted. A noise filter is incorporated to help protect against spurious noise that may inadvertently assert or deassert the WP pin. Figures 7-3 and Table 7-3 detail the sector protection status for various scenarios of the WP pin, the Enable Sector Protection command, and the Disable Sector Protection command. Figure 7-3. WP Pin and Protection Status 1 2 3 WP Table 7-3. WP Pin and Protection Status Sector Sector Time Disable Sector Protection Protection Period WP Pin Enable Sector Protection Command Protection Command Status Register Command Not Issued Previously X Disabled Read/Write 1 High — Issue Command Disabled Read/Write Issue Command — Enabled Read/Write 2 Low X X Enabled Read Command Issued During Period 1 or 2 Not Issued Yet Enabled Read/Write 3 High — Issue Command Disabled Read/Write Issue Command — Enabled Read/Write AT45DB641E 19 DS-45DB641E-027K–DFLASH–2/2019

7.3 Sector Protection Register The nonvolatile Sector Protection Register specifies which sectors are to be protected or unprotected with either the software or hardware controlled protection methods. The Sector Protection Register contains thirty two bytes of data, of which byte locations zero through thirty one contain values that specify whether Sectors 0 through 31 will be protected or unprotected. The Sector Protection Register is user modifiable and must be erased before it can be reprogrammed. Table 7-4 illustrates the format of the Sector Protection Register. Table 7-4. Sector Protection Register Sector Number 0 (0a, 0b) 1 to 31 Protected FFh See Table 7-5 Unprotected 00h Note: 1. The default values for bytes 0 through 31 are 00h when shipped from Adesto. Table 7-5. Sector 0 (0a, 0b) Sector Protection Register Byte Value Bit 7:6 Bit 5:4 Bit 3:2 Bit 1:0 Sector 0a Sector 0b Data (Page 0-7) (Page 8-1023) N/A N/A Value Sectors 0a and 0b Unprotected 00 00 XX XX 0xh Protect Sector 0a 11 00 XX XX Cxh Protect Sector 0b 00 11 XX XX 3xh Protect Sectors 0a and 0b 11 11 XX XX Fxh Note: 1. x = Don’t care 7.3.1 Erase Sector Protection Register In order to modify and change the values of the Sector Protection Register, it must first be erased using the Erase Sector Protection Register command. To erase the Sector Protection Register, a 4-byte command sequence of 3Dh, 2Ah, 7Fh, and CFh must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-timed erase cycle. The erasing of the Sector Protection Register should take place in a maximum time of t . During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy. If the device is PE powered-down before the completion of the erase cycle, then the contents of the Sector Protection Register cannot be guaranteed. The Sector Protection Register can be erased with sector protection enabled or disabled. Since the erased state (FFh) of each byte in the Sector Protection Register is used to indicate that a sector is specified for protection, leaving the sector protection enabled during the erasing of the register allows the protection scheme to be more effective in the prevention of accidental programming or erasing of the device. If for some reason an erroneous program or erase command is sent to the device immediately after erasing the Sector Protection Register and before the register can be reprogrammed, then the erroneous program or erase command will not be processed because all sectors would be protected. Table 7-6. Erase Sector Protection Register Command Command Byte 1 Byte 2 Byte 3 Byte 4 Erase Sector Protection Register 3Dh 2Ah 7Fh CFh AT45DB641E 20 DS-45DB641E-027K–DFLASH–2/2019

Figure 7-4. Erase Sector Protection Register CS SI 3Dh 2Ah 7Fh CFh Each transition represents eight bits 7.3.2 Program Sector Protection Register Once the Sector Protection Register has been erased, it can be reprogrammed using the Program Sector Protection Register command. To program the Sector Protection Register, a 4-byte command sequence of 3Dh, 2Ah, 7Fh, and FCh must be clocked into the device followed by thirty two bytes of data corresponding to Sectors 0 through 31. After the last bit of the opcode sequence and data have been clocked in, the CS pin must be deasserted to initiate the internally self-timed program cycle. The programming of the Sector Protection Register should take place in a maximum time of t . During this time, P the RDY/BUSY bit in the Status Register will indicate that the device is busy. If the device is powered-down before the completion of the erase cycle, then the contents of the Sector Protection Register cannot be guaranteed. If the proper number of data bytes is not clocked in before the CS pin is deasserted, then the protection status of the sectors corresponding to the bytes not clocked in cannot be guaranteed. Example: If only the first two bytes are clocked in instead of the complete thirty two bytes, then the protection status of the last thirty sectors cannot be guaranteed. Furthermore, if more than thirty two bytes of data is clocked into the device, then the data will wrap back around to the beginning of the register. For instance, if thirty three bytes of data are clocked in, then the thirty third byte will be stored at byte location 0 of the Sector Protection Register. The data bytes clocked into the Sector Protection Register need to be valid values (0xh, 3xh, Cxh, and Fxh for Sector 0a or Sector 0b, and 00h or FFh for other sectors) in order for the protection to function correctly. If a non-valid value is clocked into a byte location of the Sector Protection Register, then the protection status of the sector corresponding to that byte location cannot be guaranteed. Example: If a value of 17h is clocked into byte location 2 of the Sector Protection Register, then the protection status of Sector 2 cannot be guaranteed. The Sector Protection Register can be reprogrammed while the sector protection is enabled or disabled. Being able to reprogram the Sector Protection Register with the sector protection enabled allows the user to temporarily disable the sector protection to an individual sector rather than disabling sector protection completely. The Program Sector Protection Register command utilizes Buffer 1 for processing. Therefore, the contents of Buffer 1 will be altered from its previous state when this command is issued. Table 7-7. Program Sector Protection Register Command Command Byte 1 Byte 2 Byte 3 Byte 4 Program Sector Protection Register 3Dh 2Ah 7Fh FCh AT45DB641E 21 DS-45DB641E-027K–DFLASH–2/2019

Figure 7-5. Program Sector Protection Register CS SI 3Dh 2Ah 7Fh FCh Data Byte Data Byte Data Byte n n + 1 n + 31 Each transition represents eight bits 7.3.3 Read Sector Protection Register To read the Sector Protection Register, an opcode of 32h and three dummy bytes must be clocked into the device. After the last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on the SCK pin will result in the Sector Protection Register contents being output on the SO pin. The first byte (byte location 0) corresponds to Sector 0 (0a and 0b), the second byte corresponds to Sector 1, and the last byte (byte location 31) corresponds to Sector 31. Once the last byte of the Sector Protection Register has been clocked out, any additional clock pulses will result in undefined data being output on the SO pin. The CS pin must be deasserted to terminate the Read Sector Protection Register operation and put the output into a high-impedance state. Table 7-8. Read Sector Protection Register Command Command Byte 1 Byte 2 Byte 3 Byte 4 Read Sector Protection Register 32h XXh XXh XXh Note: 1. XX = Dummy byte Figure 7-6. Read Sector Protection Register CS SI 32h XX XX XX SO Data Data Data n n + 1 n + 31 Each transition represents eight bits 7.3.4 About the Sector Protection Register The Sector Protection Register is subject to a limit of 10,000 erase/program cycles. Users are encouraged to carefully evaluate the number of times the Sector Protection Register will be modified during the course of the application’s life cycle. If the application requires that the Security Protection Register be modified more than the specified limit of 10,000 cycles because the application needs to temporarily unprotect individual sectors (sector protection remains enabled while the Sector Protection Register is reprogrammed), then the application will need to limit this practice. Instead, a combination of temporarily unprotecting individual sectors along with disabling sector protection completely will need to be implemented by the application to ensure that the limit of 10,000 cycles is not exceeded. AT45DB641E 22 DS-45DB641E-027K–DFLASH–2/2019

8. Security Features 8.1 Sector Lockdown The device incorporates a sector lockdown mechanism that allows each individual sector to be permanently locked so that it becomes read-only (ROM). This is useful for applications that require the ability to permanently protect a number of sectors against malicious attempts at altering program code or security information. Warning: Once a sector is locked down, it can never be erased or programmed, and it can never be unlocked. To issue the sector lockdown command, a 4-byte command sequence of 3Dh, 2Ah, 7Fh, and 30h must be clocked into the device followed by three address bytes specifying any address within the sector to be locked down. After the last address bit has been clocked in, the CS pin must be deasserted to initiate the internally self-timed lockdown sequence. The lockdown sequence should take place in a maximum time of t . During this time, the RDY/BUSY bit in the Status P Register will indicate that the device is busy. If the device is powered-down before the completion of the lockdown sequence, then the lockdown status of the sector cannot be guaranteed. In this case, it is recommended that the user read the Sector Lockdown Register to determine the status of the appropriate sector lockdown bits or bytes and re-issue the Sector Lockdown command if necessary. Table 8-1. Sector Lockdown Command Command Byte 1 Byte 2 Byte 3 Byte 4 Sector Lockdown 3Dh 2Ah 7Fh 30h Figure 8-1. Sector Lockdown CS SI Address Address Address 3Dh 2Ah 7Fh 30h byte byte byte Each transition represents eight bits 8.1.1 Read Sector Lockdown Register The nonvolatile Sector Lockdown Register specifies which sectors in the main memory are currently unlocked or have been permanently locked down. The Sector Lockdown Register is a read-only register and contains thirty two bytes of data which correspond to Sectors 0 through 31. To read the Sector Lockdown Register, an opcode of 35h must be clocked into the device followed by three dummy bytes. After the last bit of the opcode and dummy bytes have been clocked in, the data for the contents of the Sector Lockdown Register will be clocked out on the SO pin. The first byte (byte location 0) corresponds to Sector 0 (0a and 0b), the second byte corresponds to Sector 1, and the last byte (byte location 31) corresponds to Sector 31. After the last byte of the Sector Lockdown Register has been read, additional pulses on the SCK pin will result in undefined data being output on the SO pin. Deasserting the CS pin will terminate the Read Sector Lockdown Register operation and put the SO pin into a high-impedance state. Table 8-2 details the format the Sector Lockdown Register. Table 8-2. Sector Lockdown Register Sector Number 0 (0a, 0b) 1 to 31 Locked FFh See Table 8-3 Unlocked 00h AT45DB641E 23 DS-45DB641E-027K–DFLASH–2/2019

Table 8-3. Sector 0 (0a and 0b) Sector Lockdown Register Byte Value Bit 7:6 Bit 5:4 Bit 3:2 Bit 1:0 Sector 0a Sector 0b Data (Page 0-7) (Page 8-1023) N/A N/A Value Sectors 0a and 0b Unlocked 00 00 00 00 00h Sector 0a Locked 11 00 00 00 C0h Sector 0b Locked 00 11 00 00 30h Sectors 0a and 0b Locked 11 11 00 00 F0h Table 8-4. Read Sector Lockdown Register Command Command Byte 1 Byte 2 Byte 3 Byte 4 Read Sector Lockdown Register 35h XXh XXh XXh Figure 8-2. Read Sector Lockdown Register CS SI 32h XX XX XX SO Data Data Data n n + 1 n + 31 Each transition represents eight bits 8.1.2 Freeze Sector Lockdown The Sector Lockdown command can be permanently disabled, and the current sector lockdown state can be permanently frozen so that no additional sectors can be locked down aside from those already locked down. Any attempts to issue the Sector Lockdown command after the Sector Lockdown State has been frozen will be ignored. To issue the Freeze Sector Lockdown command, the CS pin must be asserted and the opcode sequence of 34h, 55h, AAh, and 40h must be clocked into the device. Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the current sector lockdown state will be permanently frozen within a time of t . In addition, the SLE LOCK bit in the Status Register will be permanently reset to a Logic 0 to indicate that the Sector Lockdown command is permanently disabled. Table 8-5. Freeze Sector Lockdown Command Byte 1 Byte 2 Byte 3 Byte 4 Freeze Sector Lockdown 34h 55h AAh 40h Figure 8-3. Freeze Sector Lockdown CS SI 34h 55h AAh 40h Each transition represents eight bits AT45DB641E 24 DS-45DB641E-027K–DFLASH–2/2019

8.2 Security Register The device contains a specialized Security Register that can be used for purposes such as unique device serialization or locked key storage. The register is comprised of a total of 128 bytes that is divided into two portions. The first 64 bytes (byte locations 0 through 63) of the Security Register are allocated as a One-Time Programmable space. Once these 64 bytes have been programmed, they cannot be erased or reprogrammed. The remaining 64 bytes of the register (byte locations 64 through 127) are factory programmed by Adesto and will contain a unique value for each device. The factory programmed data is fixed and cannot be changed. Table 8-6. Security Register Security Register Byte Number 0 1 · · · 63 64 65 · · · 127 Data Type One-Time User Programmable Factory Programmed by Adesto 8.2.1 Programming the Security Register The user programmable portion of the Security Register does not need to be erased before it is programmed. To program the Security Register, a 4-byte opcode sequence of 9Bh, 00h, 00h, and 00h must be clocked into the device. After the last bit of the opcode sequence has been clocked into the device, the data for the contents of the 64-byte user programmable portion of the Security Register must be clocked in. After the last data byte has been clocked in, the CS pin must be deasserted to initiate the internally self-timed program cycle. The programming of the Security Register should take place in a time of t , during which time the RDY/BUSY bit in P the Status Register will indicate that the device is busy. If the device is powered-down during the program cycle, then the contents of the 64-byte user programmable portion of the Security Register cannot be guaranteed. If the full 64 bytes of data are not clocked in before the CS pin is deasserted, then the values of the byte locations not clocked in cannot be guaranteed. Example: If only the first two bytes are clocked in instead of the complete 64 bytes, then the remaining 62 bytes of the user programmable portion of the Security Register cannot be guaranteed. Furthermore, if more than 64 bytes of data is clocked into the device, then the data will wrap back around to the beginning of the register. For example, if 65 bytes of data are clocked in, then the 65th byte will be stored at byte location 0 of the Security Register. Warning: The user programmable portion of the Security Register can only be programmed one time. Therefore, it is not possible, for example, to only program the first two bytes of the register and then program the remaining 62 bytes at a later time. The Program Security Register command utilizes Buffer 1 for processing. Therefore, the contents of Buffer 1 will be altered from its previous state when this command is issued. Figure 8-4. Program Security Register CS SI 9Bh 00h 00h 00h Data Data Data n n + 1 n + 63 Each transition represents eight bits AT45DB641E 25 DS-45DB641E-027K–DFLASH–2/2019

8.2.2 Reading the Security Register To read the Security Register, an opcode of 77h and three dummy bytes must be clocked into the device. After the last dummy bit has been clocked in, the contents of the Security Register can be clocked out on the SO pin. After the last byte of the Security Register has been read, additional pulses on the SCK pin will result in undefined data being output on the SO pin. Deasserting the CS pin will terminate the Read Security Register operation and put the SO pin into a high-impedance state. Figure 8-5. Read Security Register CS SI 77h XX XX XX SO Data Data Data n n + 1 n + x Each transition represents eight bits AT45DB641E 26 DS-45DB641E-027K–DFLASH–2/2019

9. Additional Commands 9.1 Main Memory Page to Buffer Transfer A page of data can be transferred from the main memory to either Buffer 1 or Buffer 2. To transfer a page of data using the standard DataFlash page size (264 bytes), an opcode of 53h for Buffer 1 or 55h for Buffer 2 must be clocked into the device followed by three address bytes comprised of 15 page address bits (PA14 - PA0) which specify the page in main memory to be transferred, and 9 dummy bits. To transfer a page of data using the binary page size (256 bytes), an opcode of 53h for Buffer 1 and 55h for Buffer 2 must be clocked into the device followed by three address bytes comprised of 1 dummy bit, 15 page address bits (A22 - A8) which specify the page in the main memory to be transferred, and 8 dummy bits. The CS pin must be low while toggling the SCK pin to load the opcode and the three address bytes from the input pin (SI). The transfer of the page of data from the main memory to the buffer will begin when the CS pin transitions from a low to a high state. During the page transfer time (t ), the RDY/BUSY bit in the Status Register can be read to XFR determine whether or not the transfer has been completed. 9.2 Main Memory Page to Buffer Compare A page of data in main memory can be compared to the data in Buffer 1 or Buffer 2 as a method to ensure that data was successfully programmed after a Buffer to Main Memory Page Program command. To compare a page of data with the standard DataFlash page size (264 bytes), an opcode of 60h for Buffer 1 or 61h for Buffer 2 must be clocked into the device followed by three address bytes comprised of 15 page address bits (PA14 - PA0) which specify the page in the main memory to be compared to the buffer, and 9 dummy bits. To compare a page of data with the binary page size (256 bytes), an opcode of 60h for Buffer 1 or 61h for Buffer 2 must be clocked into the device followed by three address bytes comprised of 1 dummy bit, 15 page address bits (A22 - A8) which specify the page in the main memory to be compared to the buffer, and 8 dummy bits. The CS pin must be low while toggling the SCK pin to load the opcode and the address bytes from the input pin (SI). On the low-to-high transition of the CS pin, the data bytes in the selected Main Memory Page will be compared with the data bytes in Buffer 1 or Buffer 2. During the compare time (t ), the RDY/BUSY bit in the Status Register will indicate that COMP the part is busy. On completion of the compare operation, bit 6 of the Status Register will be updated with the result of the compare. 9.3 Auto Page Rewrite This command only needs to be used if the possibility exists that static (non-changing) data may be stored in a page or pages of a sector and the other pages of the same sector are erased and programmed a large number of times. Applications that modify data in a random fashion within a sector may fall into this category. To preserve data integrity of a sector, each page within a sector must be updated/rewritten at least once within every 50,000 cumulative page erase/program operations within that sector. The Auto Page Rewrite command provides a simple and efficient method to “refresh” a page in the main memory array in a single operation. The Auto Page Rewrite command is a combination of the Main Memory Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-In Erase commands. With the Auto Page Rewrite command, a page of data is first transferred from the main memory to Buffer 1 or Buffer 2 and then the same data (from Buffer 1 or Buffer 2) is programmed back into the same page of main memory, essentially “refreshing” the contents of that page. To start the Auto Page Rewrite operation with the standard DataFlash page size (264 bytes), a 1-byte opcode, 58H for Buffer 1 or 59H for Buffer 2, must be clocked into the device followed by three address bytes comprised of 15 page address bits (PA14-PA0) that specify the page in main memory to be rewritten, and 9 dummy bits. AT45DB641E 27 DS-45DB641E-027K–DFLASH–2/2019

To initiate an Auto Page Rewrite with the a binary page size (256 bytes), the opcode 58H for Buffer 1 or 59H for Buffer 2, must be clocked into the device followed by three address bytes consisting of 1 dummy bit, 15 page address bits (A22 - A8) that specify the page in the main memory that is to be rewritten, and 8 dummy bits. When a low-to-high transition occurs on the CS pin, the part will first transfer data from the page in main memory to a buffer and then program the data from the buffer back into same page of main memory. The operation is internally self-timed and should take place in a maximum time of t . During this time, the RDY/BUSY Status Register will indicate that the part is busy. EP If a sector is programmed or reprogrammed sequentially page by page and the possibility does not exist that there will be a page or pages of static data, then the programming algorithm shown in Figure 26-1 on page 61 is recommended. Otherwise, if there is a chance that there may be a page or pages of a sector that will contain static data, then the programming algorithm shown in Figure 26-2 on page 62 is recommended. Please contact Adesto for availability of devices that are specified to exceed the 50,000 cycle cumulative limit. Note: The Auto Page Rewrite command uses the same opcodes as the Read-Modify-Write command. If data bytes are clocked into the device, then the device will perform a Read-Modify-Write operation. See the Read-Modify-Write command description on page 12 for more details. 9.4 Status Register Read The 2-byte Status Register can be used to determine the device's ready/busy status, page size, a Main Memory Page to Buffer Compare operation result, the sector protection status, Freeze Sector Lockdown status, erase/program error status, Program/Erase Suspend status, and the device density. The Status Register can be read at any time, including during an internally self-timed program or erase operation. To read the Status Register, the CS pin must first be asserted and then the opcode D7h must be clocked into the device. After the opcode has been clocked in, the device will begin outputting Status Register data on the SO pin during every subsequent clock cycle. After the second byte of the Status Register has been clocked out, the sequence will repeat itself, starting again with the first byte of the Status Register, as long as the CS pin remains asserted and the clock pin is being pulsed. The data in the Status Register is constantly being updated, so each repeating sequence may output new data. The RDY/BUSY status is available for both bytes of the Status Register and is updated for each byte. Deasserting the CS pin will terminate the Status Register Read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Table 9-1. Status Register Format – Byte 1 Bit Name Type(1) Description 0 Device is busy with an internal operation. 7 RDY/BUSY Ready/Busy Status R 1 Device is ready. 0 Main memory page data matches buffer data. 6 COMP Compare Result R 1 Main memory page data does not match buffer data. 5:2 DENSITY Density Code R 1111 64-Mbit 0 Sector protection is disabled. 1 PROTECT Sector Protection Status R 1 Sector protection is enabled. 0 Device is configured for standard DataFlash page size (264 bytes). 0 PAGE SIZE Page Size Configuration R 1 Device is configured for “power of 2” binary page size (256 bytes). Note: 1. R = Readable only AT45DB641E 28 DS-45DB641E-027K–DFLASH–2/2019

Table 9-2. Status Register Format – Byte 2 Bit Name Type(1) Description 0 Device is busy with an internal operation. 7 RDY/BUSY Ready/Busy Status R 1 Device is ready. 6 RES Reserved for Future Use R 0 Reserved for future use. 0 Erase or program operation was successful. 5 EPE Erase/Program Error R 1 Erase or program error detected. 4 RES Reserved for Future Use R 0 Reserved for future use. 0 Sector Lockdown command is disabled. 3 SLE Sector Lockdown Enabled R 1 Sector Lockdown command is enabled. 0 No program operation has been suspended while using Buffer 2. Program Suspend Status 2 PS2 R (Buffer 2) 1 A sector is program suspended while using Buffer 2. 0 No program operation has been suspended while using Buffer 1. Program Suspend Status 1 PS1 R (Buffer 1) 1 A sector is program suspended while using Buffer 1. 0 No sectors are erase suspended. 0 ES Erase Suspend R 1 A sector is erase suspended. Note: 1. R = Readable only 9.4.1 RDY/BUSY Bit The RDY/BUSY bit is used to determine whether or not an internal operation, such as a program or erase, is in progress. To poll the RDY/BUSY bit to detect the completion of an internally timed operation, new Status Register data must be continually clocked out of the device until the state of the RDY/BUSY bit changes from a Logic 0 to a Logic 1. 9.4.2 COMP Bit The result of the most recent Main Memory Page to Buffer Compare operation is indicated using the COMP bit. If the COMP bit is a Logic 1, then at least one bit of the data in the Main Memory Page does not match the data in the buffer. 9.4.3 DENSITY Bits The device density is indicated using the DENSITY bits. For the AT45DB641E, the four bit binary value is 1111. The decimal value of these four binary bits does not actually equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices. The DENSITY bits are not the same as the density code indicated in the JEDEC Device ID information. The DENSITY bits are provided only for backward compatibility to older generation DataFlash devices. 9.4.4 PROTECT Bit The PROTECT bit provides information to the user on whether or not the sector protection has been enabled or disabled, either by the software-controlled method or the hardware-controlled method. 9.4.5 PAGE SIZE Bit The PAGE SIZE bit indicates whether the buffer size and the page size of the main memory array is configured for the “power of 2” binary page size (256 bytes) or the standard DataFlash page size (264 bytes). AT45DB641E 29 DS-45DB641E-027K–DFLASH–2/2019

9.4.6 EPE Bit The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one byte during the erase or program operation did not erase or program properly, then the EPE bit will be set to the Logic 1 state. The EPE bit will not be set if an erase or program operation aborts for any reason, such as an attempt to erase or program a protected region or a locked down sector or an attempt to erase or program a suspended sector. The EPE bit is updated after every erase and program operation. 9.4.7 SLE Bit The SLE bit indicates whether or not the Sector Lockdown command is enabled or disabled. If the SLE bit is a Logic 1, then the Sector Lockdown command is still enabled and sectors can be locked down. If the SLE bit is a Logic 0, then the Sector Lockdown command has been disabled and no further sectors can be locked down. 9.4.8 PS2 Bit The PS2 bit indicates if a program operation has been suspended while using Buffer 2. If the PS2 bit is a Logic 1, then a program operation has been suspended while Buffer 2 was being used, and any command attempts that would modify the contents of Buffer 2 will be ignored. 9.4.9 PS1 Bit The PS1 bit indicates if a program operation has been suspended while using Buffer 1. If the PS1 bit is a Logic 1, then a program operation has been suspended while Buffer 1 was being used, and any command attempts that would modify the contents of Buffer 1 will be ignored. 9.4.10 The ES bit The ES bit indicates whether or not an erase has been suspended. If the ES bit is a Logic 1, then an erase operation (page, block, sector, or chip) has been suspended. AT45DB641E 30 DS-45DB641E-027K–DFLASH–2/2019

10. Deep Power-Down During normal operation, the device will be placed in the standby mode to consume less power as long as the CS pin remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability to place the device into an even lower power consumption state called the Deep Power-Down mode. When the device is in the Deep Power-Down mode, all commands including the Status Register Read command will be ignored with the exception of the Resume from Deep Power-Down command. Since all commands will be ignored, the mode can be used as an extra protection mechanism against program and erase operations. Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode B9h, and then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is deasserted, the device will enter the Deep Power-Down mode within the maximum time of t . EDPD The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode once the CS pin is deasserted. In addition, the device will default to the standby mode after a power cycle. The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-Down mode. Figure 10-1. Deep Power-Down CS t EDPD 0 1 2 3 4 5 6 7 SCK Opcode SI 1 0 1 1 1 0 0 1 MSB High-impedance SO Active Current I CC Standby Mode Current Deep Power-Down Mode Current AT45DB641E 31 DS-45DB641E-027K–DFLASH–2/2019

10.1 Resume from Deep Power-Down In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-Down command must be issued. The Resume from Deep Power-Down command is the only command that the device will recognize while in the Deep Power-Down mode. To resume from the Deep Power-Down mode, the CS pin must first be asserted and then the opcode ABh must be clocked into the device. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is deasserted, the device will exit the Deep Power-Down mode and return to the standby mode within the maximum time of t . After the device has returned to the standby mode, normal command operations such as Continuous Array Read RDPD can be resumed. If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on an even byte boundary (multiples of eight bits), then the device will abort the operation and return to the Deep Power-Down mode. Figure 10-2. Resume from Deep Power-Down CS t RDPD 0 1 2 3 4 5 6 7 SCK Opcode SI 1 0 1 0 1 0 1 1 MSB High-impedance SO Active Current I CC Standby Mode Current Deep Power-Down Mode Current AT45DB641E 32 DS-45DB641E-027K–DFLASH–2/2019

10.2 Ultra-Deep Power-Down The Ultra-Deep Power-Down mode allows the device to consume far less power compared to the standby and Deep Power-Down modes by shutting down additional internal circuitry. Since almost all active circuitry is shutdown in this mode to conserve power, the contents of the SRAM buffers cannot be maintained. Therefore, any data stored in the SRAM buffers will be lost once the device enters the Ultra-Deep Power-Down mode. When the device is in the Ultra-Deep Power-Down mode, all commands including the Status Register Read and Resume from Deep Power-Down commands will be ignored. Since all commands will be ignored, the mode can be used as an extra protection mechanism against program and erase operations. Entering the Ultra-Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode 79h, and then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is deasserted, the device will enter the Ultra-Deep Power-Down mode within the maximum time of t . EUDPD The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode once the CS pin is deasserted. In addition, the device will default to the standby mode after a power cycle. The Ultra-Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Ultra-Deep Power-Down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Ultra-Deep Power-Down mode. Figure 10-3. Ultra-Deep Power-Down CS t EUDPD 0 1 2 3 4 5 6 7 SCK Opcode SI 0 1 1 1 1 0 0 1 MSB High-impedance SO Active Current I CC Standby Mode Current Ultra-Deep Power-Down Mode Current AT45DB641E 33 DS-45DB641E-027K–DFLASH–2/2019

10.2.1 Exit Ultra-Deep Power-Down To exit from the Ultra-Deep Power-Down mode, the CS pin must simply be pulsed by asserting the CS pin, waiting the minimum necessary t time, and then deasserting the CS pin again. To facilitate simple software development, a CSLU dummy byte opcode can also be entered while the CS pin is being pulsed just as in a normal operation like the Program Suspend operation; the dummy byte opcode is simply ignored by the device in this case. After the CS pin has been deasserted, the device will exit from the Ultra-Deep Power-Down mode and return to the standby mode within a maximum time of t . If the CS pin is reasserted before the t time has elapsed in an attempt to start a new XUDPD XUDPD operation, then that operation will be ignored and nothing will be performed. The system must wait for the device to return to the standby mode before normal command operations such as Continuous Array Read can be resumed. Since the contents of the SRAM buffers cannot be maintained while in the Ultra-Deep Power-Down mode, the SRAM buffers will contain undefined data when the device returns to the standby mode. Figure 10-4. Exit Ultra-Deep Power-Down CS t CSLU t XUDPD High-impedance SO Active Current I CC Standby Mode Current Ultra-Deep Power-Down Mode Current Chip Select Low By asserting the CS pin, waiting the minimum necessary t time, and then clocking in the first bit of the next XUDPD Opcode command cycle. If the first bit of the next command is clocked in before the t time has elapsed, the XUDPD device will exit Ultra Deep Power Down, however the intended operation will be ignored. Figure 10-5. Exit Ultra-Deep Power-Down (Chip Select Low) AT45DB641E 34 DS-45DB641E-027K–DFLASH–2/2019

11. Buffer and Page Size Configuration The memory array of DataFlash devices is actually larger than other Serial Flash devices in that extra user-accessible bytes are provided in each page of the memory array. For the AT45DB641E, there are an extra eight bytes of memory in each page for a total of an extra 256KB (2-Mbits) of user-accessible memory. Some applications, however, may not want to take advantage of this extra memory and instead architect their software to operate on a “power of 2” binary, logical addressing scheme. To allow this, the DataFlash can be configured so that the buffer and page sizes are 256 bytes instead of the standard 264 bytes. In addition, the configuration of the buffer and page sizes is reversible and can be changed from 264 bytes to 256 bytes or from 256 bytes to 264 bytes. The configured setting is stored in an internal nonvolatile register so that the buffer and page size configuration is not affected by power cycles. The nonvolatile register has a limit of 10,000 erase/program cycles; therefore, care should be taken to not switch between the size options more than 10,000 times. Devices are initially shipped from Adesto with the buffer and page sizes set to 264 bytes. Devices can be ordered from Adesto pre-configured for the “power of 2” binary size of 256 bytes. For details, see Section 27., Ordering Information (Standard DataFlash Page Size) on page 63. To configure the device for “power of 2” binary page size (256 bytes), a 4-byte opcode sequence of 3Dh, 2Ah, 80h, and A6h must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-timed configuration process and nonvolatile register program cycle. The programming of the nonvolatile register should take place in a time of t , during which time the RDY/BUSY bit in the EP Status Register will indicate that the device is busy. The device does not need to be power cycled after the completion of the configuration process and register program cycle in order for the buffer and page size to be configured to 256 bytes. To configure the device for standard DataFlash page size (264 bytes), a 4-byte opcode sequence of 3Dh, 2Ah, 80h, and A7h must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-timed configuration process and nonvolatile register program cycle. The programming of the nonvolatile register should take place in a time of t , during which time the RDY/BUSY bit in the EP Status Register will indicate that the device is busy. The device does not need to be power cycled after the completion of the configuration process and register program cycle in order for the buffer and page size to be configured to 264 bytes. Table 11-1. Buffer and Page Size Configuration Commands Command Byte 1 Byte 2 Byte 3 Byte 4 “Power of 2” binary page size (256 bytes) 3Dh 2Ah 80h A6h DataFlash page size (264 bytes) 3Dh 2Ah 80h A7h Figure 11-1. Buffer and Page Size Configuration CS SI 3Dh 2Ah 80h Opcode Byte 4 Each transition represents eight bits AT45DB641E 35 DS-45DB641E-027K–DFLASH–2/2019

12. Manufacturer and Device ID Read Identification information can be read from the device to enable systems to electronically query and identify the device while it is in the system. The identification method and the command opcode comply with the JEDEC Standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The type of information that can be read from the device includes the JEDEC-defined Manufacturer ID, the vendor-specific Device ID, and the vendor-specific Extended Device Information. The Read Manufacturer and Device ID command is limited to a maximum clock frequency of f . Since not all Flash CLK devices are capable of operating at very high clock frequencies, applications should be designed to read the identification information from the devices at a reasonably low clock frequency to ensure that all devices to be used in the application can be identified properly. Once the identification process is complete, the application can then increase the clock frequency to accommodate specific Flash devices that are capable of operating at the higher clock frequencies. To read the identification information, the CS pin must first be asserted and then the opcode 9Fh must be clocked into the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during the subsequent clock cycles. The first byte to be output will be the Manufacturer ID, followed by two bytes of the Device ID information. The fourth byte output will be the Extended Device Information (EDI) String Length, which will be 01h indicating that one byte of EDI data follows. After the one byte of EDI data is output, the SO pin will go into a high-impedance state; therefore, additional clock cycles will have no affect on the SO pin and no data will be output. As indicated in the JEDEC Standard, reading the EDI String Length and any subsequent data is optional. Deasserting the CS pin will terminate the Manufacturer and Device ID Read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Table 12-1. Manufacturer and Device ID Information Byte No. Data Type Value 1 Manufacturer ID 1Fh 2 Device ID (Byte 1) 28h 3 Device ID (Byte 2) 00h 4 [Optional to Read] Extended Device Information (EDI) String Length 01h 5 [Optional to Read] EDI Byte 1 00h Table 12-2. Manufacturer and Device ID Details Hex Data Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value Details JEDEC Assigned Code Manufacturer ID 1Fh JEDEC code: 0001 1111 (1Fh for Adesto) 0 0 0 1 1 1 1 1 Family Code Density Code Family code: 001 (AT45Dxxx Family) Device ID (Byte 1) 28h Density code: 01000 (64-Mbit) 0 0 1 0 1 0 0 0 Sub Code Product Variant Sub code: 000 (Standard Series) Device ID (Byte 2) 00h Product variant: 00000 0 0 0 0 0 0 0 0 AT45DB641E 36 DS-45DB641E-027K–DFLASH–2/2019

Table 12-3. EDI Data Hex Byte Number Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value Details RFU Device Revision RFU: Reserved for Future Use 1 00h Device revision: 00000 (Initial Version) 0 0 0 0 0 0 0 0 Figure 12-1. Read Manufacturer and Device ID CS 0 6 7 8 14 15 16 22 23 24 30 31 32 38 39 40 46 SCK Opcode SI 9Fh High-impedance SO 1Fh 28h 00h 01h 00h Manufacturer ID Device ID Device ID EDI EDI Byte 1 Byte 2 String Length Data Byte 1 Note: Each transition shown for SI and SO represents one byte (8 bits) AT45DB641E 37 DS-45DB641E-027K–DFLASH–2/2019

13. Software Reset In some applications, it may be necessary to prematurely terminate a program or erase cycle early rather than wait the hundreds of microseconds or milliseconds necessary for the program or erase operation to complete normally. The Software Reset command allows a program or erase operation in progress to be ended abruptly and returns the device to an idle state. To perform a Software Reset, the CS pin must be asserted and a 4-byte command sequence of F0h, 00h, 00h, and 00h must be clocked into the device. Any additional data clocked into the device after the last byte will be ignored. When the CS pin is deasserted, the program or erase operation currently in progress will be terminated within a time t . Since SWRST the program or erase operation may not complete before the device is reset, the contents of the page being programmed or erased cannot be guaranteed to be valid. The Software Reset command has no effect on the states of the Sector Protection Register, the Sector Lockdown Register, or the buffer and page size configuration. The PS2, PS1, and ES bits of the Status Register, however, will be reset back to their default states. If a Software Reset operation is performed while a sector is erase suspended, the suspend operation will abort and the contents of the page or block being erased in the suspended sector will be left in an undefined state. If a Software Reset is performed while a sector is program suspended, the suspend operation will abort and the contents of the page that was being programmed and subsequently suspended will be undefined. The remaining pages in the sector will retain their previous contents. The complete 4-byte opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, no reset operation will be performed. Table 13-1. Software Reset Command Byte 1 Byte 2 Byte 3 Byte 4 Software Reset F0h 00h 00h 00h Figure 13-1. Software Reset CS SI F0h 00h 00h 00h Each transition represents eight bits AT45DB641E 38 DS-45DB641E-027K–DFLASH–2/2019

14. Operation Mode Summary The commands described previously can be grouped into four different categories to better describe which commands can be executed at what times. Group A commands consist of: 1. Main Memory Page Read 2. Continuous Array Read (SPI) 3. Read Sector Protection Register 4. Read Sector Lockdown Register 5. Read Security Register 6. Buffer 1 (or 2) Read Group B commands consist of: 1. Page Erase 2. Block Erase 3. Sector Erase 4. Chip Erase 5. Main Memory Page to Buffer 1 (or 2) Transfer 6. Main Memory Page to Buffer 1 (or 2) Compare 7. Buffer 1 (or 2) to Main Memory Page Program with Built-In Erase 8. Buffer 1 (or 2) to Main Memory Page Program without Built-In Erase 9. Main Memory Page Program through Buffer 1 (or 2) with Built-In Erase 10. Main Memory Byte/Page Program through Buffer 1 without Built-In Erase 11. Auto Page Rewrite 12. Read-Modify-Write Group C commands consist of: 1. Buffer 1 (or 2) Write 2. Status Register Read 3. Manufacturer and Device ID Read Group D commands consist of: 1. Erase Sector Protection Register 2. Program Sector Protection Register 3. Sector Lockdown 4. Program Security Register 5. Buffer and Page Size Configuration 6. Freeze Sector Lockdown If a Group A command is in progress (not fully completed), then another command in Group A, B, C, or D should not be started. However, during the internally self-timed portion of Group B commands, any command in Group C can be executed. The Group B commands using Buffer 1 should use Group C commands using Buffer 2 and vice versa. Finally, during the internally self-timed portion of a Group D command, only the Status Register Read command should be executed. Most of the commands in Group B can be suspended and resumed, except the Buffer Transfer, Buffer Compare, Auto Page Rewrite and Read-Modify-Write operations. If a Group B command is suspended, all of the Group A commands can be executed. See Table 6-4 to determine which of the Group B, Group C, and Group D commands are allowed. AT45DB641E 39 DS-45DB641E-027K–DFLASH–2/2019

15. Command Tables Table 15-1. Read Commands Command Opcode Main Memory Page Read D2h Continuous Array Read (Low Power Mode) 01h Continuous Array Read (Low Frequency) 03h Continuous Array Read (High Frequency) 0Bh Continuous Array Read (High Frequency) 1Bh Continuous Array Read (Legacy Command – Not Recommended for New Designs) E8h Buffer 1 Read (Low Frequency) D1h Buffer 2 Read (Low Frequency) D3h Buffer 1 Read (High Frequency) D4h Buffer 2 Read (High Frequency) D6h Table 15-2. Program and Erase Commands Command Opcode Buffer 1 Write 84h Buffer 2 Write 87h Buffer 1 to Main Memory Page Program with Built-In Erase 83h Buffer 2 to Main Memory Page Program with Built-In Erase 86h Buffer 1 to Main Memory Page Program without Built-In Erase 88h Buffer 2 to Main Memory Page Program without Built-In Erase 89h Main Memory Page Program through Buffer 1 with Built-In Erase 82h Main Memory Page Program through Buffer 2 with Built-In Erase 85h Main Memory Byte/Page Program through Buffer 1 without Built-In Erase 02h Page Erase 81h Block Erase 50h Sector Erase 7Ch Chip Erase C7h + 94h + 80h + 9Ah Program/Erase Suspend B0h Program/Erase Resume D0h Read-Modify-Write through Buffer 1 58h Read-Modify-Write through Buffer 2 59h AT45DB641E 40 DS-45DB641E-027K–DFLASH–2/2019

Table 15-3. Protection and Security Commands Command Opcode Enable Sector Protection 3Dh + 2Ah + 7Fh + A9h Disable Sector Protection 3Dh + 2Ah + 7Fh + 9Ah Erase Sector Protection Register 3Dh + 2Ah + 7Fh + CFh Program Sector Protection Register 3Dh + 2Ah + 7Fh + FCh Read Sector Protection Register 32h Sector Lockdown 3Dh + 2Ah + 7Fh + 30h Read Sector Lockdown Register 35h Freeze Sector Lockdown 34h + 55h + AAh + 40h Program Security Register 9Bh + 00h + 00h + 00h Read Security Register 77h Table 15-4. Additional Commands Command Opcode Main Memory Page to Buffer 1 Transfer 53h Main Memory Page to Buffer 2 Transfer 55h Main Memory Page to Buffer 1 Compare 60h Main Memory Page to Buffer 2 Compare 61h Auto Page Rewrite 58h Auto Page Rewrite 59h Deep Power-Down B9h Resume from Deep Power-Down ABh Ultra-Deep Power-Down 79h Status Register Read D7h Manufacturer and Device ID Read 9Fh Configure “Power of 2” (Binary) Page Size 3Dh + 2Ah + 80h + A6h Configure Standard DataFlash Page Size 3Dh + 2Ah + 80h + A7h Software Reset F0h + 00h + 00h + 00h Table 15-5. Legacy Commands(1)(2) Command Opcode Buffer 1 Read 54H Buffer 2 Read 56H Main Memory Page Read 52H Continuous Array Read 68H Status Register Read 57H Notes: 1. Legacy commands are not recommended for new designs. 2. Legacy commands operate from 2.30V to 3.60V Vcc only. AT45DB641E 41 DS-45DB641E-027K–DFLASH–2/2019

Table 15-6. Detailed Bit-level Addressing Sequence for Binary Page Size (256 bytes) Page Size = 256 bytes Address Byte Address Byte Address Byte d e Additional v Opcode Opcode eser 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBuymtemsy R A A A A A A A A A A A A A A A A A A A A A A A 01h 0 0 0 0 0 0 0 1 X A A A A A A A A A A A A A A A A A A A A A A A N/A 02h 0 0 0 0 0 0 1 0 X A A A A A A A A A A A A A A A A A A A A A A A N/A 03h 0 0 0 0 0 0 1 1 X A A A A A A A A A A A A A A A A A A A A A A A N/A 0Bh 0 0 0 0 1 0 1 1 X A A A A A A A A A A A A A A A A A A A A A A A 1 1Bh 0 0 0 1 1 0 1 1 X A A A A A A A A A A A A A A A A A A A A A A A 2 32h 0 0 1 1 0 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X N/A 35h 0 0 1 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X N/A 50h 0 1 0 1 0 0 0 0 X A A A A A A A A A A A A X X X X X X X X X X X N/A 53h 0 1 0 1 0 0 1 1 X A A A A A A A A A A A A A A A X X X X X X X X N/A 55h 0 1 0 1 0 1 0 1 X A A A A A A A A A A A A A A A X X X X X X X X N/A 58h(1) 0 1 0 1 1 0 0 0 X A A A A A A A A A A A A A A A X X X X X X X X N/A 59h(1) 0 1 0 1 1 0 0 1 X A A A A A A A A A A A A A A A X X X X X X X X N/A 58h(2) 0 1 0 1 1 0 0 0 X A A A A A A A A A A A A A A A A A A A A A A A N/A 59h(2) 0 1 0 1 1 0 0 1 X A A A A A A A A A A A A A A A A A A A A A A A N/A 60h 0 1 1 0 0 0 0 0 X A A A A A A A A A A A A A A A X X X X X X X X N/A 61h 0 1 1 0 0 0 0 1 X A A A A A A A A A A A A A A A X X X X X X X X N/A 77h 0 1 1 1 0 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X N/A 79h 0 1 1 1 1 0 0 1 N/A N/A N/A N/A 7Ch 0 1 1 1 1 1 0 0 X A A A A A X X X X X X X X X X X X X X X X X X N/A 81h 1 0 0 0 0 0 0 1 X A A A A A A A A A A A A A A A X X X X X X X X N/A 82h 1 0 0 0 0 0 1 0 X A A A A A A A A A A A A A A A A A A A A A A A N/A 83h 1 0 0 0 0 0 1 1 X A A A A A A A A A A A A A A A X X X X X X X X N/A 84h 1 0 0 0 0 1 0 0 X X X X X X X X X X X X X X X X A A A A A A A A N/A 85h 1 0 0 0 0 1 0 1 X A A A A A A A A A A A A A A A A A A A A A A A N/A 86h 1 0 0 0 0 1 1 0 X A A A A A A A A A A A A A A A X X X X X X X X N/A 87h 1 0 0 0 0 1 1 1 X X X X X X X X X X X X X X X X A A A A A A A A N/A 88h 1 0 0 0 1 0 0 0 X A A A A A A A A A A A A A A A X X X X X X X X N/A 89h 1 0 0 0 1 0 0 1 X A A A A A A A A A A A A A A A X X X X X X X X N/A 9Fh 1 0 0 1 1 1 1 1 N/A N/A N/A N/A B9h 1 0 1 1 1 0 0 1 N/A N/A N/A N/A ABh 1 0 1 0 1 0 1 1 N/A N/A N/A N/A B0h 1 0 1 1 0 0 0 0 N/A N/A N/A N/A D0h 1 1 0 1 0 0 0 0 N/A N/A N/A N/A D1h 1 1 0 1 0 0 0 1 X X X X X X X X X X X X X X X X A A A A A A A A N/A D2h 1 1 0 1 0 0 1 0 X A A A A A A A A A A A A A A A A A A A A A A A 4 D3h 1 1 0 1 0 0 1 1 X X X X X X X X X X X X X X X X A A A A A A A A N/A D4h 1 1 0 1 0 1 0 0 X X X X X X X X X X X X X X X X A A A A A A A A 1 D6h 1 1 0 1 0 1 1 0 X X X X X X X X X X X X X X X X A A A A A A A A 1 D7h 1 1 0 1 0 1 1 1 N/A N/A N/A N/A Note: 1. Shown to indicate when the Auto Page Rewrite operation is executed. 2. Shown to indicate when the Read-Modify-Write operation is executed. 3. X = Dummy Bit AT45DB641E 42 DS-45DB641E-027K–DFLASH–2/2019

Table 15-7. Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size (264 bytes) Page Size = 264 bytes Address Byte Address Byte Address Byte Additional 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Dummy Opcode Opcode A A A A A A A A A A A A A A A A A A A A A A A A Bytes P P P P P P P P P P P P P P P B B B B B B B B B 01h 0 0 0 0 0 0 0 1 P P P P P P P P P P P P P P P B B B B B B B B B N/A 02h 0 0 0 0 0 0 1 0 P P P P P P P P P P P P P P P B B B B B B B B B N/A 03h 0 0 0 0 0 0 1 1 P P P P P P P P P P P P P P P B B B B B B B B B N/A 0Bh 0 0 0 0 1 0 1 1 P P P P P P P P P P P P P P P B B B B B B B B B 1 1Bh 0 0 0 1 1 0 1 1 P P P P P P P P P P P P P P P B B B B B B B B B 2 32h 0 0 1 1 0 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X N/A 35h 0 0 1 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X N/A 50h 0 1 0 1 0 0 0 0 P P P P P P P P P P P P X X X X X X X X X X X X N/A 53h 0 1 0 1 0 0 1 1 P P P P P P P P P P P P P P P X X X X X X X X X N/A 55h 0 1 0 1 0 1 0 1 P P P P P P P P P P P P P P P X X X X X X X X X N/A 58h(1) 0 1 0 1 1 0 0 0 P P P P P P P P P P P P P P P X X X X X X X X X N/A 59h(1) 0 1 0 1 1 0 0 1 P P P P P P P P P P P P P P P X X X X X X X X X N/A 58h(2) 0 1 0 1 1 0 0 0 P P P P P P P P P P P P P P P B B B B B B B B B N/A 59h(2) 0 1 0 1 1 0 0 1 P P P P P P P P P P P P P P P B B B B B B B B B N/A 60h 0 1 1 0 0 0 0 0 P P P P P P P P P P P P P P P X X X X X X X X X N/A 61h 0 1 1 0 0 0 0 1 P P P P P P P P P P P P P P P X X X X X X X X X N/A 77h 0 1 1 1 0 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X N/A 79h 0 1 1 1 1 0 0 1 N/A N/A N/A N/A 7Ch 0 1 1 1 1 1 0 0 P P P P P X X X X X X X X X X X X X X X X X X X N/A 81h 1 0 0 0 0 0 0 1 P P P P P P P P P P P P P P P X X X X X X X X X N/A 82h 1 0 0 0 0 0 1 0 P P P P P P P P P P P P P P P B B B B B B B B B N/A 83h 1 0 0 0 0 0 1 1 P P P P P P P P P P P P P P P X X X X X X X X X N/A 84h 1 0 0 0 0 1 0 0 X X X X X X X X X X X X X X X B B B B B B B B B N/A 85h 1 0 0 0 0 1 0 1 P P P P P P P P P P P P P P P B B B B B B B B B N/A 86h 1 0 0 0 0 1 1 0 P P P P P P P P P P P P P P P X X X X X X X X X N/A 87h 1 0 0 0 0 1 1 1 X X X X X X X X X X X X X X X B B B B B B B B B N/A 88h 1 0 0 0 1 0 0 0 P P P P P P P P P P P P P P P X X X X X X X X X N/A 89h 1 0 0 0 1 0 0 1 P P P P P P P P P P P P P P P X X X X X X X X X N/A 9Fh 1 0 0 1 1 1 1 1 N/A N/A N/A N/A B9h 1 0 1 1 1 0 0 1 N/A N/A N/A N/A ABh 1 0 1 0 1 0 1 1 N/A N/A N/A N/A B0h 1 0 1 1 0 0 0 0 N/A N/A N/A N/A D0h 1 1 0 1 0 0 0 0 N/A N/A N/A N/A D1h 1 1 0 1 0 0 0 1 X X X X X X X X X X X X X X X B B B B B B B B B N/A D2h 1 1 0 1 0 0 1 0 P P P P P P P P P P P P P P P B B B B B B B B B 4 D3h 1 1 0 1 0 0 0 1 X X X X X X X X X X X X X X X B B B B B B B B B N/A D4h 1 1 0 1 0 1 0 0 X X X X X X X X X X X X X X X B B B B B B B B B 1 D6h 1 1 0 1 0 1 1 0 X X X X X X X X X X X X X X X B B B B B B B B B 1 D7h 1 1 0 1 0 1 1 1 N/A N/A N/A N/A Notes: 1. Shown to indicate when the Auto Page Rewrite operation is executed. 2. Shown to indicate when the Read-Modify-Write operation is executed. 3. P = Page Address Bit, B = Byte/Buffer Address Bit, X = Dummy Bit AT45DB641E 43 DS-45DB641E-027K–DFLASH–2/2019

16. Power-On/Reset State When power is first applied to the device, or when recovering from a reset condition, the output pin (SO) will be in a high impedance state, and a high-to-low transition on the CSB pin will be required to start a valid instruction. The SPI mode (Mode 3 or Mode 0) will be automatically selected on every falling edge of CSB by sampling the inactive clock state. 16.1 Power-Up/Power-Down Voltage and Timing Requirements During power-up, the device must not be READ for at least the minimum t time after the supply voltage reaches the VCSL minimum V level (V min). While the device is being powered-up, the internal Power-On Reset (POR) circuitry POR POR keeps the device in a reset mode until the supply voltage rises above the minimum V . During this time, all operations cc are disabled and the device will not respond to any commands. If the first operation to the device after power-up will be a program or erase operation, then the operation cannot be started until the supply voltage reaches the minimum V level and an internal device delay has elapsed. This delay will CC be a maximum time of t . After the t time, the device will be in the standby mode if CSB is at logic high or active PUW PUW mode if CSB is at logic low. For the case of Power-down then Power-up operation, or if a power interruption occurs (such that VCC drops below V max), the V of the Flash device must be maintained below V for at least the minimum POR cc PWD specified T time. This is to ensure the Flash device will reset properly after a power interruption. PWD Table 16-1. Voltage and Timing Requirements for Power-Up/Power-Down Symbol Parameter Min Max Units V (1) V for device initialization 1.0 V PWD CC t (1) Minimum duration for device initialization 300 µs PWD t Minimum V to chip select low time for Read command 70 µs VCSL CC t (1) V rise time 1 500000 µs/V VR CC V Power on reset voltage 1.45 1.6 V POR t Power up delay time before Program or Erase is allowed 3 ms PUW 1. Not 100% tested (value guaranteed by design and characterization). Figure 16-1. Power-Up Timing VCC Chip Select Not Permitted V max POR t PUW Full Operation Permitted t Read Operation VCSL Permitted Max V PWD t t PWD VR Time AT45DB641E 44 DS-45DB641E-027K–DFLASH–2/2019

17. System Considerations The serial interface is controlled by the Serial Clock (SCK), Serial Input (SI), and Chip Select (CS) pins. These signals must rise and fall monotonically and be free from noise. Excessive noise or ringing on these pins can be misinterpreted as multiple edges and cause improper operation of the device. PCB traces must be kept to a minimum distance or appropriately terminated to ensure proper operation. If necessary, decoupling capacitors can be added on these pins to provide filtering against noise glitches. As system complexity continues to increase, voltage regulation is becoming more important. A key element of any voltage regulation scheme is its current sourcing capability. Like all Flash memories, the peak current for DataFlash devices occurs during the programming and erasing operations. The supply voltage regulator needs to be able to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during programming or erasing can lead to improper operation and possible data corruption. AT45DB641E 45 DS-45DB641E-027K–DFLASH–2/2019

18. Electrical Specifications 18.1 Absolute Maximum Ratings* *Notice: Stresses beyond those listed under “Absolute Maximum Temperature under Bias . . . . . . . -55°C to +125°C Ratings” may cause permanent damage to the device. The “Absolute Maximum Ratings” are stress ratings only and Storage Temperature. . . . . . . . . . -65°C to +150°C functional operation of the device at these or any other conditions beyond those indicated in the operational All Input Voltages sections of this specification is not implied. Exposure to (except V but including NC pins) absolute maximum rating conditions for extended periods CC with Respect to Ground. . . . . .-0.6V to V + 0.6V may affect device reliability. Voltage extremes referenced in CC the “Absolute Maximum Ratings” are intended to accommodate short duration undershoot/overshoot All Output Voltages conditions and does not imply or guarantee functional device with Respect to Ground. . . . . .-0.6V to V + 0.6V CC operation at these levels for any extended period of time. 18.2 DC and AC Operating Range AT45DB641E Operating Temperature (Case) Industrial -40°C to 85°C V Power Supply 1.7V to 3.6V CC AT45DB641E 46 DS-45DB641E-027K–DFLASH–2/2019

18.3 DC Characteristics 1.7V to 3.6V 2.3V to 3.6V Unit Symbol Parameter Condition Min Typ Max Min Typ Max s Ultra-Deep Power- CS = V All other I CC. 0.3 1 0.4 1 µA UDPD Down Current inputs at 0V or V CC. Deep Power-Down CS = V All other I CC. 5 25 6 25 µA DPD Current inputs at 0V or V CC. CS = V All other I Standby Current CC. 25 45 25 45 µA SB inputs at 0V or V CC. Active Current, f = 1MHz; I = 0mA 6 9 6 9 mA OUT Low I CC1 Power Read (01h) f = 15MHz; I = 0mA 7 11 7 11 mA Operation OUT Active Current, f = 50MHz; IOUT = 0mA 12 17 12 17 mA I (1)(2) CC2 Read Operation f = 85MHz; I = 0mA 16 22 16 22 mA OUT Active Current, I CS = V 14 16 14 16 mA CC3 Program Operation CC Active Current, I CS = V 8 12 8 12 mA CC4 Erase Operation CC All inputs at CMOS I Input Load Current 1 1 µA LI levels Output Leakage All inputs at CMOS I 1 1 µA LO Current levels V Input Low Voltage V x 0.3 V x 0.3 V IL CC CC V Input High Voltage V x 0.7 V + 0.6 V x 0.7 V + 0.6 V IH CC CC CC CC Output Low V I = 100µA 0.4 0.4 V OL Voltage OL Output High V I = -100µA V - 0.2V V - 0.2V V OH Voltage OH CC CC Notes: 1. Typical values measured at 3.0V at 25°C. 2. I during a Buffer Read is 20mA maximum @ 20MHz. CC2 AT45DB641E 47 DS-45DB641E-027K–DFLASH–2/2019

18.4 AC Characteristics 1.7V to 3.6V 2.3V to 3.6V Symbol Parameter Min Max Min Max Units f SCK Frequency 50 85 MHz SCK f SCK Frequency for Continuous Read (0x0B) 50 85 MHz CAR1 f SCK Frequency for Continuous Read (Low Frequency)(0x03) 40 50 MHz CAR2 SCK Frequency for Continuous Read (Low Power Mode f 15 15 MHz CAR3 – 01h Opcode) f SCK Frequency for Continuous Read (0x1B) 66 104 MHz CAR4 t SCK High Time 4.5 4.5 ns WH t SCK Low Time 4.5 4.5 ns WL t (1) SCK Rise Time, Peak-to-peak 0.1 0.1 V/ns SCKR t (1) SCK Fall Time, Peak-to-peak 0.1 0.1 V/ns SCKF t Minimum CS High Time 30 30 ns CS t CS Setup Time 6 5 ns CSS t CS Hold Time 5 5 ns CSH t Data In Setup Time 2 2 ns SU t Data In Hold Time 1 1 ns H t Output Hold Time 0 0 ns HO t (1) Output Disable Time 8 6 ns DIS t Output Valid 7 6 ns V t WP Low to Protection Enabled 1 1 µs WPE t WP High to Protection Disabled 1 1 µs WPD t Freeze Sector Lockdown Time (from CS High) 200 200 µs LOCK t (1) CS High to Ultra-Deep Power-Down 3 3 µs EUDPD t Minimum CS Low Time to Exit Ultra-Deep Power-Down 20 20 ns CSLU t Exit Ultra-Deep Power-Down Time 100 100 µs XUDPD t (1) CS High to Deep Power-Down 2 2 µs EDPD t Resume from Deep Power-Down Time 35 35 µs RDPD t Page to Buffer Transfer Time 180 180 µs XFR t Page to Buffer Compare Time 180 180 µs COMP t RESET Pulse Width 10 10 µs RST t RESET Recovery Time 1 1 µs REC t Software Reset Time 35 35 µs SWRST Note: 1. Values are based on device characterization, not 100% tested in production. AT45DB641E 48 DS-45DB641E-027K–DFLASH–2/2019

18.5 Program and Erase Characteristics 1.7V to 3.6V 2.3V to 3.6V Symbol Parameter Min Typ Max Min Typ Max Units Page Erase and Programming t 10 35 8 35 ms EP Time (256/264 bytes) t Page Programming Time 1.5 5 1.5 3 ms P t Byte Programming Time 8 8 µs BP t Page Erase Time 7 35 7 35 ms PE t Block Erase Time 25 50 25 50 ms BE t Sector Erase Time 2.5 6.5 2.5 6.5 s SE t Chip Erase Time 80 208 80 208 s CE Program 8 12 8 12 t Suspend Time µs SUSP Erase 20 30 20 30 Program 3 5 3 5 t Resume Time µs RES Erase 3 5 3 5 t OTP Security Register Program Time 200 500 200 500 µs OTPP Notes: 1. Values are based on device characterization, not 100% tested in production. 2. Not 100% tested (value guaranteed by design and characterization). 19. Input Test Waveforms and Measurement Levels 0.9V AC CC AC Driving V /2 Measurement CC Levels Level 0.1V CC t , t < 2ns (10% to 90%) R F 20. Output Test Load Device Under Test 30pF AT45DB641E 49 DS-45DB641E-027K–DFLASH–2/2019

21. Utilizing the RapidS Function To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full clock cycle must be used to transmit data back and forth across the serial bus. The DataFlash is designed to always clock its data out on the falling edge of the SCK signal and clock data in on the rising edge of SCK. For full clock cycle operation to be achieved, when the DataFlash is clocking data out on the falling edge of SCK, the host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order to give the DataFlash a full clock cycle to latch the incoming data in on the next rising edge of SCK. Figure 21-1. RapidS Mode Slave CS 1 8 1 8 1 2 3 4 5 6 7 2 3 4 5 6 7 SCK B E A C D MOSI MSB LSB BYTE-MOSI H G I F MISO MSB LSB BYTE-SO MOSI = Master Out, Slave In MISO = Master In, Slave Out The Master is the host controller and the Slave is the DataFlash. The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK. The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK. A. Master clocks out first bit of BYTE-MOSI on the rising edge of SCK B. Slave clocks in first bit of BYTE-MOSI on the next rising edge of SCK C. Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK D. Last bit of BYTE-MOSI is clocked out from the Master E. Last bit of BYTE-MOSI is clocked into the slave F. Slave clocks out first bit of BYTE-SO G. Master clocks in first bit of BYTE-SO H. Slave clocks out second bit of BYTE-SO I. Master clocks in last bit of BYTE-SO AT45DB641E 50 DS-45DB641E-027K–DFLASH–2/2019

Figure 21-2. Command Sequence for Read/Write Operations for Page Size 256 bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) CMD 8-bits 8-bits 8-bits MSB X X X X X X X X X X X X X X X X X X X XX X X X LSB 1 Dummy Bit Page Address Byte/Buffer Address (A22 - A8) (A7 - A0/BFA7 - BFA0) Figure 21-3. Command Sequence for Read/Write Operations for Page Size 264 bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) CMD 8-bits 8-bits 8-bits MSB X X X XX X X X X X X XX X X X X X X X X X X X LSB Page Address Byte/Buffer Address (PA14 - PA0) (BA8 - BA0/BFA8 - BFA0) AT45DB641E 51 DS-45DB641E-027K–DFLASH–2/2019

22. AC Waveforms Four different timing waveforms are shown in Figure 22-1 through Figure 22-4. Waveform 1 shows the SCK signal being low when CS makes a high-to-low transition and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. In both cases, output SO becomes valid while the SCK signal is still low (SCK low time is specified as t ). Timing Waveforms 1 and 2 conform to RapidS serial interface but for frequencies up to 85MHz. Waveforms 1 WL and 2 are compatible with SPI Mode 0 and SPI Mode 3, respectively. Waveform 3 and 4 illustrate general timing diagram for RapidS serial interface. These are similar to Waveform 1 and 2, except that output SO is not restricted to become valid during the t period. These timing waveforms are valid over the WL full frequency range (maximum frequency = 85MHz) of the RapidS serial case. Figure 22-1. Waveform 1 = SPI Mode 0 Compatible t CS CS t t t t CSS WH WL CSH SCK t t t V HO DIS High-impedance High-impedance SO Valid Out t t SU H SI Valid In Figure 22-2. Waveform 2 = SPI Mode 3 Compatible t CS CS t t t t CSS WL WH CSH SCK t t t V HO DIS High Z High-impedance SO Valid Out t t SU H SI Valid In AT45DB641E 52 DS-45DB641E-027K–DFLASH–2/2019

Figure 22-3. Waveform 3 = RapidS Mode 0 t CS CS t t t t CSS WH WL CSH SCK t t t V HO DIS High-impedance High-impedance SO Valid Out t t SU H SI Valid In Figure 22-4. Waveform 4 = RapidS Mode 3 t CS CS t t t t CSS WL WH CSH SCK t t t V HO DIS High Z High-impedance SO Valid Out t t SU H SI Valid In AT45DB641E 53 DS-45DB641E-027K–DFLASH–2/2019

23. Write Operations The following block diagram and waveforms illustrate the various write sequences available. Figure 23-1. Block Diagram WP Flash Memory Array Page (256/264 bytes) Buffer 1 (256/264 bytes) Buffer 2 (256/264 bytes) SCK CS I/O Interface RESET V CC GND SI SO Figure 23-2. Buffer Write Completes Writing into Selected Buffer CS Binary Page Size 16 Dummy Bits + BFA7-BFA0 SI (Input) CMD X X BFA7-0 n n + 1 Last Byte n = 1st byte read Each transition represents eight bits n+1 = 2nd byte read Figure 23-3. Buffer to Main Memory Page Program Starts Self-timed Erase/Program Operation CS Binary Page Size A22-A8 + 8 Dummy Bits SI (Input) CMD X,A22-A16 A15-A8 XXXX XXXX Each transition represents eight bits AT45DB641E 54 DS-45DB641E-027K–DFLASH–2/2019

24. Read Operations The following block diagram and waveforms illustrate the various read sequences available. Figure 24-1. Block Diagram Flash Memory Array Page (256/264 bytes) Main Memory Main Memory Page To Page To Buffer 1 Buffer 2 Buffer 1 (256/264 bytes) Buffer 2 (256/264 bytes) Buffer 1 Main Memory Buffer 2 Read Page Read Read I/O Interface SO Figure 24-2. Main Memory Page Read CS Address for Binary Page Size X,A22-A16 A15-A8 A7-A0 SI (Input) CMD PA14-7 PA6-0, BA8 BA7-0 X X 4 Dummy Bytes SO (Output) nn n + 1 AT45DB641E 55 DS-45DB641E-027K–DFLASH–2/2019

Figure 24-3. Main Memory Page to Buffer Transfer Data From the selected Flash Page is read into either SRAM Buffer Starts Reading Page Data into Buffer CS Binary Page Size X, A22-A16 + A15- A8 + 8 Dummy Bits SI (Input) CMD PA14-7 PA6-0, XX XXXX XXXX SO (Output) Figure 24-4. Buffer Read CS Address for Binary Page Size 1 6 D u m m y B i t s + BFA7-BFA0 SI (Input) CMD XXXX XXXX XXXX XXXX BFA7-0 X No Dummy Byte (opcodes D1H and D3H) 1 Dummy Byte (opcodes D4H and D6H) SO (Output) nn n + 1 Each transition represents eight bits AT45DB641E 56 DS-45DB641E-027K–DFLASH–2/2019

25. Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3 Figure 25-1. Continuous Array Read (Legacy Opcode E8h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 62 63 64 65 66 67 68 69 70 71 72 SCK Opcode Address Bits 32 Dummy Bits SI 1 1 1 0 1 0 0 0 A A A A A A A A A X X X X X X MSB MSB MSB Data Byte 1 High-impedance SO D D D D D D D D D D MSB MSB Bit 2048/2112 Bit 0 of of Page n Page n+1 Figure 25-2. Continuous Array Read (Opcode 0Bh) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SCK Opcode Address Bits A22 - A0 Dummy Bits SI 0 0 0 0 1 0 1 1 A A A A A A A A A X X X X X X X X MSB MSB MSB Data Byte 1 High-impedance SO D D D D D D D D D D MSB MSB Figure 25-3. Continuous Array Read (Opcode 01h or 03h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK Opcode Address Bits A22-A0 SI 0 0 0 0 0 0 1 1 A A A A A A A A A MSB MSB Data Byte 1 High-impedance SO D D D D D D D D D D MSB MSB AT45DB641E 57 DS-45DB641E-027K–DFLASH–2/2019

Figure 25-4. Main Memory Page Read (Opcode D2h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 62 63 64 65 66 67 68 69 70 71 72 SCK Opcode Address Bits 32 Dummy Bits SI 1 1 0 1 0 0 1 0 A A A A A A A A A X X X X X X MSB MSB MSB Data Byte 1 High-impedance SO D D D D D D D D D D MSB MSB Figure 25-5. Buffer Read (Opcode D4h or D6h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SCK Address Bits Binary Page Size = 16 Dummy Bits + BFA7-BFA0 Standard DataFlash Page Size = Dummy Bits Opcode 15 Dummy Bits + BFA8-BFA0 SI 1 1 0 1 0 1 0 0 X X X X X X A A A X X X X X X X X MSB MSB MSB Data Byte 1 High-impedance SO D D D D D D D D D D MSB MSB Figure 25-6. Buffer Read – Low Frequency (Opcode D1h or D3h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK Address Bits Binary Page Size = 16 Dummy Bits + BFA7-BFA0 Standard DataFlashPage Size = Opcode 15 Dummy Bits + BFA8-BFA0 SI 1 1 0 1 0 0 0 1 X X X X X X A A A MSB MSB Data Byte 1 High-impedance SO D D D D D D D D D D MSB MSB AT45DB641E 58 DS-45DB641E-027K–DFLASH–2/2019

Figure 25-7. Read Sector Protection Register (Opcode 32h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK Opcode Dummy Bits SI 0 0 1 1 0 0 1 0 X X X X X X X X X MSB MSB Data Byte 1 High-impedance SO D D D D D D D D D MSB MSB Figure 25-8. Read Sector Lockdown Register (Opcode 35h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK Opcode Dummy Bits SI 0 0 1 1 0 1 0 1 X X X X X X X X X MSB MSB Data Byte 1 High-impedance SO D D D D D D D D D MSB MSB Figure 25-9. Read Security Register (Opcode 77h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK Opcode Dummy Bits SI 0 1 1 1 0 1 1 1 X X X X X X X X X MSB MSB Data Byte 1 High-impedance SO D D D D D D D D D MSB MSB AT45DB641E 59 DS-45DB641E-027K–DFLASH–2/2019

Figure 25-10. Status Register Read (Opcode D7h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCK Opcode SI 1 1 0 1 0 1 1 1 MSB Status Register Data Status Register Data High-impedance SO D D D D D D D D D D D D D D D D D D MSB MSB MSB Figure 25-11. Manufacturer and Device Read (Opcode 9Fh) CS 0 6 7 8 14 15 16 22 23 24 30 31 32 38 39 40 46 SCK Opcode SI 9Fh High-impedance SO 1Fh 28h 00h 01h 00h Manufacturer ID Device ID Device ID EDI EDI Byte 1 Byte 2 String Length Data Byte 1 Note: Each transition shown for SI and SO represents one byte (8 bits) Figure 25-12.Reset Timing CS tREC tCSS SCK tRST RESET High Impedance High Impedance SO (Output) SI (Input) Note: 1. The CS signal should be in the high state before the RESET signal is deasserted. AT45DB641E 60 DS-45DB641E-027K–DFLASH–2/2019

26. Auto Page Rewrite Flowchart Figure 26-1. Algorithm for Programming or Re-programming of the Entire Array Sequentially START Provide Address and Data Buffer Write (84h, 87h) Main Memory Page Program through Buffer (82h, 85h) Buffer To Main Memory Page Program (83h, 86h) END Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-page. 2. A page can be written using either a Main Memory Page Program operation or a buffer write operation followed by a buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. AT45DB641E 61 DS-45DB641E-027K–DFLASH–2/2019

Figure 26-2. Algorithm for Programming or Re-programming of the Entire Array Randomly START Provide Address of Page to Modify Main Memory Page If planning to modify multiple to Buffer Transfer bytes currently stored within (53h, 55h) a page of the Flash array Buffer Write (84h, 87h) Main Memory Page Program through Buffer (82h, 85h) Buffer to Main Memory Page Program (83h, 86h) (2) Auto Page Rewrite (58h, 59h) Increment Page (2) Address Pointer END Notes: 1. To preserve data integrity, each page of an DataFlash sector must be updated/rewritten at least once within every 50,000 cumulative page erase and program operations. 2. A page address pointer must be maintained to indicate which page is to be rewritten. The Auto Page Rewrite command must use the address specified by the page address pointer. 3. Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 50,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. AT45DB641E 62 DS-45DB641E-027K–DFLASH–2/2019

27. Ordering Information (Standard DataFlash Page Size) 27.1 Ordering Detail A T 4 5 D B 6 4 1 E - S H N 2 B - B Designator Shipping Carrier Option B = Bulk (tubes) T = Tape and reel Y = Trays Product Family 45DB = DataFlash Page Size Option “ ” = Standard (264 bytes/page) Device Density 2B = Binary (256 bytes/page) 64 = 6-Mbit Operating Voltage N = 1.7V minimum (1.7V to 3.6V) Interface Device Grade 1 = Serial H = Green, NiPdAu lead finish, Industrial temperature range Device Revision (–40°C to +85°C) U = Green, Matte Sn or Sn alloy, Industrial temperature range (–40°C to +85°C) Package Option S = 8-lead, 0.208” wide SOIC M = 8-pad, 5 x 6 x 0.6mm UDFN MW = 8-pad, 6 x 8 x 1.0mm VDFN CUCU N= 9=-b 4al4l, - 3b ax l3l, (61m xm 8 p idtcBh)G UABGA UDUWNF = = 4 D4-ibea ilnl 6W xa 8f e(0r .F5omrmm pitch) dBGA DWF = Die in Wafer Form 27.2 Ordering Codes (Standard DataFlash Page Size) Ordering Code Package Lead Finish Operating Voltage f Device Grade SCK AT45DB641E-SHN-B(1) 8S2 AT45DB641E-SHN-T(1) AT45DB641E-MHN-Y(1) 8MA1 NiPdAu AT45DB641E-MHN-T(1) Industrial 1.7V to 3.6V 85MHz AT45DB641E-MWHN-Y(1) (-40°C to 85°C) 8MW1 AT45DB641E-MWHN-T(1) AT45DB641E-UUN-T 44-WLCSP SnAgCu AT45DB641E-DWF(2) DWF Notes: 1. The shipping carrier suffix is not marked on the device. 2. Contact Adesto for mechanical drawing or Die Sales information. AT45DB641E 63 DS-45DB641E-027K–DFLASH–2/2019

Package Type 8S2 8-lead 0.208" wide, Plastic Gull Wing Small Outline (EIAJ SOIC) 8MA1 8-pad (5 x 6 x 0.6mm body), Thermally Enhanced Plastic Ultra Thin Dual Flat No-lead (UDFN) 8MW1 8-pad (6 x 8 x 1.0mm body), Thermally Enhanced Plastic Very Thin Dual Flat No-lead (VDFN) 44-WLCSP 44-ball modified 6 x 8 array x 0.5mm pitch, die Ball Grid Array (dBGA) DWF Die in Wafer Form 27.3 Ordering Codes (Binary Page Size) Ordering Code Package Lead Finish Operating Voltage f Device Grade SCK AT45DB641E-SHN2B-T(1)(2) 8S2 AT45DB641E-MHN2B-T (1)(2) 8MA1 NiPdAu Industrial 1.7V to 3.6V 85MHz AT45DB641E-MWHN2B-T (1)(2) 8MW1 (-40°C to 85°C) AT45DB641E-UUN2B-T 44-WLCSP SnAgCu Notes: 1. The shipping carrier suffix is not marked on the device. 2. Parts ordered with suffix code ‘2B’ are shipped in tape and reel (T&R) with the page size set to 256 bytes. This option is only available for shipping in T&R (-T). Package Type 8S2 8-lead 0.208" wide, Plastic Gull Wing Small Outline (EIAJ SOIC) 8MA1 8-pad (5 x 6 x 0.6mm body), Thermally Enhanced Plastic Ultra Thin Dual Flat No-lead (UDFN) 8MW1 8-pad (6 x 8 x 1.0mm body), Thermally Enhanced Plastic Very Thin Dual Flat No-lead (VDFN) 44-WLCSP 44-ball modified 6 x 8 array x 0.5 mm pitch, die Ball Grid Array (dBGA) AT45DB641E 64 DS-45DB641E-027K–DFLASH–2/2019

28. Packaging Information 28.1 8S2 – 8-lead EIAJ SOIC C 1 E E1 L N TOP VIEW q END VIEW e b COMMON DIMENSIONS A (U nit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 A 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 D E1 5.18 5.40 2 E 7.70 8.26 L 0.51 0.85 SIDE VIEW q 0° 8° e 1.27 BSC 3 Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. 4/15/08 TITLE GPC DRAWING NO. REV. 8S2, 8-lead, 0.208” Body, Plastic Small Package Drawing Contact: Outline Package (EIAJ) STN 8S2 F contact@adestotech.com AT45DB641E 65 DS-45DB641E-027K–DFLASH–2/2019

28.2 8MA1 – 8-pad UDFN E C Pin 1 ID D SIDE VIEW y TOP VIEW A1 A K E2 0.45 Option A 8 1 Pin #1 Pin #1 Notch Cham fe r COMMON DIMENSIONS (0.20 R) (C 0.35) (Unit of Measure = mm) (Option B) 7 2 SYMBOL MIN NOM MAX N OT E A 0.45 0.55 0.60 D2 e A1 0.00 0.02 0.05 6 3 b 0.35 0.40 0.48 C 0.152 REF 5 4 D 4.90 5.00 5.10 D2 3.80 4.00 4.20 b E 5.90 6.00 6.10 BOTTOM VIEW L E2 3.20 3.40 3.60 e 1.27 L 0.50 0.60 0.75 y 0.00 – 0.08 K 0.20 – – 4/15/08 TITLE GPC DRAWING NO. REV. Package Drawing Contact: 8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally contact@adestotech.com Enhanced Plastic Ultra Thin Dual Flat No Lead YFG 8MA1 D Package (UDFN) AT45DB641E 66 DS-45DB641E-027K–DFLASH–2/2019

28.3 8MW1 - 8-pad VDFN C E Pin 1 ID D Side View Top View A1 A E1 8 1 Pin #1 ID Pin #1 COMMON DIMENSIONS Option A Chamfer (C 0.40 max) (Unit of Measure = mm) 7 2 SYMBOL MIN NOM MAX NOTE D1 A 0.80 – 1.00 6 3 e Option B A1 – – 0.05 5 4 b 0.35 0.40 0.48 C 0.203 REF b D 5.90 6.00 6.10 L K Pin #1 Notch D1 4.25 4.90 (0.20 R) E 7.90 8.00 8.10 Bottom View E1 3.35 5.00 e 1.27 L 0.45 0.50 0.55 K 1.05 REF 8/4/17 TITLE DRAWING NO. REV. 8MW1, 8-pad (6 x 8 x 1.0 mm Body), Thermally Package Drawing Contact: Enhanced Plastic Very Thin Dual Flat No Lead 8MW1 F contact@adestotech.com Package (VDFN) AT45DB641E 67 DS-45DB641E-027K–DFLASH–2/2019

28.4 44-WLCSP — 44-ball die Ball Grid Array 44-WLCSP — 44-ball die Ball Grid Array - Pinout Diagram 1 2 3 4 5 6 A (NC) (NC) (NC) (NC) (NC) B (NC) SI RST CS (NC) C (NC) SI SCK RST CS (NC) D (NC) SI SCK RST CS (NC) E (NC) SO GND Vcc WP (NC) F (NC) SO GND Vcc WP (NC) G (NC) SO Vcc WP (NC) H (NC) (NC) (NC) (NC) (NC) AT45DB641E 68 DS-45DB641E-027K–DFLASH–2/2019

12/23/13 ® TITLE GPC DRAWING NO. REV. 44-WLCSP, 44-ball, 3.5 x 4.2mm body, modified 6 x 8 array Package Drawing Contact: 0.5mm pitch, die Ball Grid Array (dBGA), WLCSP GCL 646747PO 0A contact@adestotech.com AT45DB641E 69 DS-45DB641E-027K–DFLASH–2/2019

29. Revision History Doc. Rev. Date Comments DS-45DB641E-027A 8/2013 Initial document release. Updated spec in Continuous Array Read (1Bh Opcode) to f . Corrected Low Power CAR4 Read Option (up to 15MHz). Corrected Ultra-Deep Power-Down current (400nA typical). DS-45DB641E-027B 10/2013 Updated spec for Input High Voltage (Max) to V + 0.6V. Updated DC and AC CC parameters, and Program and Erase Characteristics. Updated datasheet status to Preliminary. DS-45DB641E-027C 11/2013 Corrected Memory Architecture Diagram, Figure 3.1. DS-45DB641E-027D 1/2014 Added Exit Ultra-Deep Power-Down (Chip Select Low). DS-45DB641E-027E 1/2014 Updated specifications for I , I , I , f , and t . Removed Preliminary status. DPD SB CC2 CAR2 XUDPD Added WLCSP package. Expanded explanation of Power up/Power down (Section 16). DS-45DB641E-027F 4/2015 Corrected Table 6-4 (Additional Commands, “Main Memory to Buffer”). Corrected Ordering Code Detail Diagram (voltage range). DS-45DB641E-027G 6/2015 Added Die in Wafer Form package option. Updated 44-WLCSP package title. Corrected page size reference in Ordering Detail Diagram. Updated UUN package DS-45DB641E-027H 1/2016 diagram. DS-45DB641E-027I 1/2017 Added patent information. DS-45DB641E-027J 8/2017 Updated 6 x 8 VDFN package drawing. DS-45DB641E-027K 2/2019 Removed 9CC, 9-ball UBGA package option. AT45DB641E 70 DS-45DB641E-027K–DFLASH–2/2019

Corporate Office California | USA Adesto Headquarters 3600 Peterson Way Santa Clara, CA 95054 Phone: (+1) 408.400.0578 Email: contact@adestotech.com © 2019 Adesto Technologies. All rights reserved. / Rev.: DS-45DB641E-027K–DFLASH–2/2019 Adesto®, the Adesto logo, CBRAM®, and DataFlash® are registered trademarks or trademarks of Adesto Technologies. All other marks are the property of their respective owners. Adesto products in this datasheet are covered by certain Adesto patents registered in the United States and potentially other countries. Please refer to http://www.adestotech.com/patents for details. Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by the Company in connection with the sale of Adesto products, expressly or by implication. Adesto's products are not authorized for use as critical components in life support devices or systems.

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