Features • Fast Read Access Time – 70 ns (cid:129) Automatic Page Write Operation – Internal Address and Data Latches for 64 Bytes – Internal Control Timer (cid:129) Fast Write Cycle Times – Page Write Cycle Time: 3 ms or 10 ms Maximum – 1 to 64-byte Page Write Operation (cid:129) Low Power Dissipation 256K (32K x 8) – 80 mA Active Current – 3 mA Standby Current High-speed (cid:129) Hardware and Software Data Protection (cid:129) DATA Polling for End of Write Detection Parallel (cid:129) High Reliability CMOS Technology – Endurance: 104 or 105 Cycles EEPROM – Data Retention: 10 Years (cid:129) Single 5V ± 10% Supply (cid:129) CMOS and TTL Compatible Inputs and Outputs AT28HC256 (cid:129) JEDEC Approved Byte-wide Pinout (cid:129) Full Military and Industrial Temperature Ranges (cid:129) Green (Pb/Halide-free) Packaging Option 1. Description The AT28HC256 is a high-performance electrically erasable and programmable read- only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac- tured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256 offers access times to 70 ns with power dissipation of just 440 mW. When the AT28HC256 is deselected, the standby current is less than 5 mA. The AT28HC256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64 bytes of data are internally latched, freeing the addresses and data bus for other oper- ations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA Polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel’s 28HC256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking. 0007N–PEEPR–9/09

2. Pin Configurations Pin Name Function A0 - A14 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect DC Don’t Connect 2.1 28-lead TSOP Top View 2.3 32-pad LCC, 32-lead PLCC Top View A7 A12 A14 DC VCC WE A13 OE 1 28 A10 A11 2 27 CE 4 3 2 1 2 1 0 3 3 3 A9 3 26 I/O7 A6 5 29 A8 A8 4 25 I/O6 A5 6 28 A9 A13 5 24 I/O5 A4 7 27 A11 WE 6 23 I/O4 A3 8 26 NC VCC 7 22 I/O3 A2 9 25 OE A14 8 21 GND A1 10 24 A10 A12 9 20 I/O2 A0 11 23 CE A7 10 19 I/O1 NC 12 22 I/O7 A6 11 18 I/O0 I/O0 134 5 6 7 8 9 021 I/O6 1 1 1 1 1 1 2 A5 12 17 A0 A4 13 16 A1 1 2 D C 3 4 5 O O N D O O O A3 14 15 A2 I/ I/ G I/ I/ I/ Note: PLCC package pins 1 and 17 are Don’t Connect. 2.4 28-lead Cerdip/Flatpack/SOIC – 2.2 28-lead PGA Top View Top View A14 1 28 VCC A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 GND 14 15 I/O3 AT28HC256 2 0007N–PEEPR–9/09

AT28HC256 3. Block Diagram 4. Device Operation 4.1 Read The AT28HC256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. 4.2 Byte Write A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of t , a read operation will effectively be a polling operation. WC 4.3 Page Write The page write operation of the AT28HC256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 150 µs (t ) of the previous byte. If the BLC t limit is exceeded the AT28C256 will cease accepting data and commence the internal BLC programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. That is, for each WE high to low transition dur- ing the page write operation, A6 - A14 must be the same. The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. 4.4 DATA Polling The AT28HC256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. 3 0007N–PEEPR–9/09

4.5 Toggle Bit In addition to DATA Polling the AT28HC256 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Testing the toggle bit may begin at any time during the write cycle. 4.6 Data Protection If precautions are not taken, inadvertent writes to any 5-volt-only nonvolatile memory may occur during transition of the host system power supply. Atmel® has incorporated both hard- ware and software features that will protect the memory against inadvertent writes. 4.6.1 Hardware Protection Hardware features protect against inadvertent writes to the AT28HC256 in the following ways: (a) V sense – if V is below 3.8V (typical) the write function is inhibited; (b) V power-on CC CC CC delay – once V has reached 3.8V the device will automatically time out 5 ms typical) before CC allowing a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. 4.6.2 Software Data Protection A software controlled data protection feature has been implemented on the AT28HC256. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28HC256 is shipped from Atmel with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to “Software Data Protection” algo- rithm). After writing the 3-byte command sequence and after t the entire AT28HC256 will be WC protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28HC256. This is done by preceding the data to be written by the same 3-byte command sequence. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28HC256 during power-up and power-down conditions. All command sequences must conform to the page write timing spec- ifications. It should also be noted that the data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the three byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of t , read operations will effectively be polling operations. WC 4.7 Device Identification An extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array. 4.8 Optional Chip Erase Mode The entire device can be erased using a 6-byte software code. Please see “Software Chip Erase” application note for details. AT28HC256 4 0007N–PEEPR–9/09

AT28HC256 5. DC and AC Operating Range AT28HC256-70 AT28HC256-90 AT28HC256-12 Operating Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C Temperature (Case) Mil. -55°C - 125°C -55°C - 125°C V Power Supply 5V ± 10% 5V ± 10% 5V ± 10% CC 6. Operating Modes Mode CE OE WE I/O Read V V V D IL IL IH OUT Write(2) V V V D IL IH IL IN Standby/Write Inhibit V X(1) X High Z IH Write Inhibit X X V IH Write Inhibit X V X IL Output Disable X V X High Z IH Chip Erase V V (3) V High Z IL H IL Notes: 1. X can be V or V . IL IH 2. Refer to AC programming waveforms. 3. V = 12.0V ± 0.5V. H 7. Absolute Maximum Ratings* Temperature under Bias................................-55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- Storage Temperature.....................................-65°C to +150°C age to the device. This is a stress rating only and functional operation of the device at these or any All Input Voltages other conditions beyond those indicated in the (including NC Pins) operational sections of this specification is not with Respect to Ground...................................-0.6V to +6.25V implied. Exposure to absolute maximum rating conditions for extended periods may affect All Output Voltages device reliability with Respect to Ground.............................-0.6V to V + 0.6V CC Voltage on OE and A9 with Respect to Ground...................................-0.6V to +13.5V 8. DC Characteristics Symbol Parameter Condition Min Max Units I Input Load Current V = 0V to V + 1V 10 µA LI IN CC I Output Leakage Current V = 0V to V 10 µA LO I/O CC AT28HC256-90, -12 3 mA I V Standby Current TTL CE = 2.0V to V SB1 CC CC AT28HC256-70 60 mA I V Standby Current CMOS CE = V - 0.3V to V AT28HC256-90, -12 300 µA SB2 CC CC CC I V Active Current f = 5 MHz; I = 0 mA 80 mA CC CC OUT V Input Low Voltage 0.8 V IL V Input High Voltage 2.0 V IH V Output Low Voltage I = 6.0 mA 0.45 V OL OL V Output High Voltage I = -4 mA 2.4 V OH OH 5 0007N–PEEPR–9/09

9. AC Read Characteristics AT28HC256-70 AT28C256-90 AT28HC256-12 Symbol Parameter Min Max Min Max Min Max Units t Address to Output Delay 70 90 120 ns ACC t (1) CE to Output Delay 70 90 120 ns CE t (2) OE to Output Delay 0 35 0 40 0 50 ns OE t (3)(4) CE or OE to Output Float 0 35 0 40 0 50 ns DF Output Hold from OE, CE or Address, t 0 0 0 ns OH whichever occurred first 10. AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to t - t after the address transition without impact on t . ACC CE ACC 2. OE may be delayed up to t - t after the falling edge of CE without impact on t or by t - t after an address change CE OE CE ACC OE without impact on t . ACC 3. t is specified from OE or CE whichever occurs first (C = 5 pF). DF L 4. This parameter is characterized and is not 100% tested. AT28HC256 6 0007N–PEEPR–9/09

AT28HC256 11. Input Test Waveforms and Measurement Level t , t < 5 ns R F 12. Output Test Load 13. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units Conditions C 4 6 pF V = 0V IN IN C 8 12 pF V = 0V OUT OUT Note: 1. This parameter is characterized and is not 100% tested. 7 0007N–PEEPR–9/09

14. AC Write Characteristics Symbol Parameter Min Max Units t , t Address, OE Setup Time 0 ns AS OES t Address Hold Time 50 ns AH t Chip Select Setup Time 0 ns CS t Chip Select Hold Time 0 ns CH t Write Pulse Width (WE or CE) 100 ns WP t Data Setup Time 50 ns DS t , t Data, OE Hold Time 0 ns DH OEH t Time to Data Valid NR(1) DV Note: 1. NR = No Restriction. 15. AC Write Waveforms 15.1 WE Controlled 15.2 CE Controlled AT28HC256 8 0007N–PEEPR–9/09

AT28HC256 16. Page Mode Write Characteristics Symbol Parameter Min Typ Max Units AT28HC256 5 10 ms t Write Cycle Time (option available) WC AT28HC256F 2 3 ms t Address Setup Time 0 ns AS t Address Hold Time 50 ns AH t Data Setup Time 50 ns DS t Data Hold Time 0 ns DH t Write Pulse Width 100 ns WP t Byte Load Cycle Time 150 µs BLC t Write Pulse Width High 50 ns WPH 17. Page Mode Write Waveforms(1)(2) Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low. 18. Chip Erase Waveforms t = t = 5 µsec (min.) S H t = 10 msec (min.) W V = 12.0V ± 0.5V H 9 0007N–PEEPR–9/09

19. Software Data Protection 20. Software Data Protection Enable Algorithm(1) Disable Algorithm(1) LOAD DATA AA LOAD DATA AA TO TO ADDRESS 5555 ADDRESS 5555 LOAD DATA 55 LOAD DATA 55 TO TO ADDRESS 2AAA ADDRESS 2AAA LOAD DATA A0 LOAD DATA 80 TO TO ADDRESS 5555 WRITES ENABLED(2) ADDRESS 5555 LOAD DATA XX LOAD DATA AA TO TO ANY ADDRESS(4) ADDRESS 5555 LOAD LAST BYTE LOAD DATA 55 TO TO LAST ADDRESS ADDRESS 2AAA ENTER DATA PROTECT STATE Notes: 1. Data Format: I/O7 - I/O0 (Hex); LOAD DATA 20 TO Address Format: A14 - A0 (Hex). ADDRESS 5555 EXIT DATA 2. Write Protect state will be activated at end of write PROTECT STATE(3) even if no other data is loaded. LOAD DATA XX 3. Write Protect state will be deactivated at end of write TO ANY ADDRESS(4) period even if no other data is loaded. 4. 1 to 64 bytes of data are loaded. LOAD LAST BYTE TO LAST ADDRESS 21. Software Protected Write Cycle Waveforms(1)(2) Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. 2. OE must be high only when WE and CE are both low. AT28HC256 10 0007N–PEEPR–9/09

AT28HC256 22. Data Polling Characteristics(1) Symbol Parameter Min Typ Max Units t Data Hold Time 0 ns DH t OE Hold Time 0 ns OEH t OE to Output Delay(2) ns OE t Write Recovery Time 0 ns WR Notes: 1. These parameters are characterized and not 100% tested. 2. See “AC Read Characteristics” on page 6. 23. Data Polling Waveforms 24. Toggle Bit Characteristics(1) Symbol Parameter Min Typ Max Units t Data Hold Time 10 ns DH t OE Hold Time 10 ns OEH t OE to Output Delay(2) ns OE t OE High Pulse 150 ns OEHP t Write Recovery Time 0 ns WR Notes: 1. These parameters are characterized and not 100% tested. 2. See “AC Read Characteristics” on page 6. 25. Toggle Bit Waveforms Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 11 0007N–PEEPR–9/09

26. Normalized I Graphs CC AT28HC256 12 0007N–PEEPR–9/09

AT28HC256 27. Ordering Information 27.1 Military Dual Marked Package 27.1.1 AT28HC256 tACC ICC (mA) (ns) Active Standby Ordering Code Package Operation Range AT28HC256-90DM/883 28D6 5962-88634 03 XX AT28HC256-90FM/883 28F 5962-88634 03 ZX 90 80 0.3 AT28HC256-90LM/883 32L 5962-88634 03 YX AT28HC256-90UM/883 28U Military/883C 5962-88634 03 UX Class B, Fully Compliant AT28HC256-12DM/883 28D6 (-55°C to 125°C) 5962-88634 01 XX AT28HC256-12FM/883 28F 5962-88634 01 ZX 120 80 0.3 AT28HC256-12LM/883 32L 5962-88634 01 YX AT28HC256-12UM/883 28U 5962-88634 01 UX Package Type 28D6 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip) 28F 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (Flatpack) 32L 32-pad, Non-windowed, Ceramic Leadless Chip Carrier (LCC) 28U 28-pin, Ceramic Pin Grid Array (PGA) Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles F Fast Write Option: Write Time = 3 ms 13 0007N–PEEPR–9/09

27.1.2 AT28HC256E(1) tACC ICC (mA) (ns) Active Standby Ordering Code Package Operation Range AT28HC256E-90DM/883 28D6 AT28HC256E-90FM/883 28F 90 80 0.3 AT28HC256E-90LM/883 32L Military/883C AT28HC256E-90UM/883 28U Class B, Fully Compliant AT28HC256E-12DM/883 28D6 (-55°C to 125°C) AT28HC256E-12FM/883 28F 120 80 0.3 AT28HC256E-12LM/883 32L AT28HC256E-12UM/883 28U Note: 1. No dual marking for this device. 27.1.3 AT28HC256F tACC ICC (mA) (ns) Active Standby Ordering Code Package Operation Range AT28HC256F-90DM/883 28D6 5962-88634 04 XX AT28HC256F-90FM/883 28F 5962-88634 04 ZX 90 80 0.3 AT28HC256F-90LM/883 32L 5962-88634 04 YX AT28HC256F-90UM/883 28U Military/883C 5962-88634 04 UX Class B, Fully Compliant AT28HC256F-12DM/883 28D6 (-55°C to 125°C) 5962-88634 02 XX AT28HC256F-12FM/883 28F 5962-88634 02 ZX 120 80 0.3 AT28HC256F-12LM/883 32L 5962-88634 02 YX AT28HC256F-12UM/883 28U 5962-88634 02 UX Package Type 28D6 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip) 28F 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (Flatpack) 32L 32-pad, Non-windowed, Ceramic Leadless Chip Carrier (LCC) 28U 28-pin, Ceramic Pin Grid Array (PGA) Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles F Fast Write Option: Write Time = 3 ms AT28HC256 14 0007N–PEEPR–9/09

AT28HC256 27.2 Industrial Green Package Option (Pb/Halide-free) 27.2.1 AT28HC256 tACC ICC (mA) (ns) Active Standby Ordering Code Package Operation Range AT28HC256-70JU 32J 70 80 0.3 AT28HC256-70SU 28S AT28HC256-70TU 28T AT28HC256-90JU 32J Industrial 90 80 0.3 AT28HC256-90SU 28S (-40°C to 85°C) AT28HC256-90TU 28T AT28HC256-12JU 32J 120 80 0.3 AT28HC256-12SU 28S AT28HC256-12TU 28T 27.2.2 AT28HC256E tACC ICC (mA) (ns) Active Standby Ordering Code Package Operation Range AT28HC256E-90JU 32J 90 80 0.3 AT28HC256E-90SU 28S AT28HC256E-90TU 28T Industrial AT28HC256E-12JU 32J (-40°C to 85°C) 120 80 0.3 AT28HC256E-12SU 28S AT28HC256E-12TU 28T 27.2.3 AT28HC256F tACC ICC (mA) (ns) Active Standby Ordering Code Package Operation Range AT28HC256F-90JU 32J Industrial 90 80 0.3 AT28HC256F-90SU 28S (-40°C to 85°C) AT28HC256F-90TU 28T Package Type 32J 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28S 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 28T 28-lead, Plastic Thin Small Outline Package (TSOP) Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles F Fast Write Option: Write Time = 3 ms 27.3 Ordering Information Note Previous datasheets included the low power suffixes L, LE and LF on the AT28HC256 for 120 ns and 90 ns speeds. The low power parameters are now standard; therefore, the L, LE and LF suffixes are no longer required. 15 0007N–PEEPR–9/09

27.4 Die Products Contact Atmel Sales for die sales options. AT28HC256 16 0007N–PEEPR–9/09

AT28HC256 28. Packaging Information 28.1 28D6 – Cerdip Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 D-10 Config A (Glass Sealed) 37.85(1.490) 36.58(1.440) PIN 1 15.49(0.610) 12.95(0.510) 33.02(1.300) REF 5.72(0.225) 0.127(0.005)MIN MAX SEATING PLANE 1.52(0.060) 5.08(0.200) 0.38(0.015) 3.18(0.125) 0.66(0.026) 1.65(0.065) 0.36(0.014) 2.54(0.100)BSC 1.14(0.045) 15.70(0.620) 15.00(0.590) 0.46(0.018) 0º~ 15º REF 0.20(0.008) 17.80(0.700) MAX 10/23/03 TITLE DRAWING NO. REV. 2325 Orchard Parkway 28D6, 28-lead, 0.600" Wide, Non-windowed, San Jose, CA 95131 28D6 B R Ceramic Dual Inline Package (Cerdip) 17 0007N–PEEPR–9/09

28.2 28F – Flatpack Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 F-12 Config B 9.40(0.370) PIN #1 ID 6.35(0.250) 0.56(0.022) 0.38(0.015) 1.27(0.050) BSC 18.49(0.728) 18.08(0.712) 1.14(0.045) MAX 10.57(0.416) 9.75(0.384) 0.23(0.009) 3.02(0.119) 0.10(0.004) 2.29(0.090) 1.96(0.077) 1.09(0.043) 1.14(0.045) 7.26(0.286) 0.660(0.026) 6.96(0.274) 10/21/03 TITLE DRAWING NO. REV. 2325 Orchard Parkway 28F, 28-lead, Non-windowed, Ceramic Bottom-brazed San Jose, CA 95131 28F B R Flat Package (FlatPack) AT28HC256 18 0007N–PEEPR–9/09

AT28HC256 28.3 32J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ IDENTIFIER 0.318(0.0125) 0.191(0.0075) E1 E B1 E2 B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D2 A 3.175 – 3.556 A1 1.524 – 2.413 A2 0.381 – – D 12.319 – 12.573 D1 11.354 – 11.506 Note 2 D2 9.906 – 10.922 Notes: 1.This package conforms to JEDEC reference MS-016, Variation AE. E 14.859 – 15.113 2.Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 E1 13.894 – 14.046 Note 2 and E1 include mold mismatch and are measured at the extreme E2 12.471 – 13.487 material condition at the upper or lower parting line. B 0.660 – 0.813 3. Lead coplanarity is 0.004" (0.102 mm) maximum. B1 0.330 – 0.533 e 1.270 TYP 10/04/01 TITLE DRAWING NO. REV. 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) San Jose, CA 95131 32J B R 19 0007N–PEEPR–9/09

28.4 32L – LCC Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 C-12 11.63(0.458) 11.23(0.442) 2.54(0.100) 2.16(0.085) 14.22(0.560) 13.72(0.540) 1.91(0.075) 1.40(0.055) PIN 1 1.40(0.055) 2.41(0.095) 1.14(0.045) INDEX CORNER 1.91(0.075) 0.635(0.025) X 45˚ 0.381(0.015) 0.305(0.012) RADIUS 0.178(0.007) 10.16(0.400) BSC 0.737(0.029) 0.533(0.021) 1.27(0.050) TYP 1.02(0.040) X 45˚ 2.16(0.085) 7.62(0.300) BSC 1.65(0.065) 10/21/03 TITLE DRAWING NO. REV. 2325 Orchard Parkway 32L, 32-pad, Non-windowed, Ceramic Lid, Leadless Chip San Jose, CA 95131 32L B R Carrier (LCC) AT28HC256 20 0007N–PEEPR–9/09

AT28HC256 28.5 28S – SOIC Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 0.51(0.020) 0.33(0.013) 7.60(0.2992) 10.65(0.419) 7.40(0.2914) 10.00(0.394) PIN 1 1.27(0.50) BSC TOP VIEW 18.10(0.7125) 2.65(0.1043) 17.70(0.6969) 2.35(0.0926) 0.30(0.0118) 0.10(0.0040) SIDE VIEWS 0º ~ 8º 0.32(0.0125) 0.23(0.0091) 1.27(0.050) 0.40(0.016) 8/4/03 TITLE DRAWING NO. REV. 2325 Orchard Parkway 28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC) San Jose, CA 95131 28S B R JEDEC Standard MS-013 21 0007N–PEEPR–9/09

28.6 28T – TSOP PIN 1 0º ~ 5º c Pin 1 Identifier Area D1 D L e b L1 E A2 A SEATING PLANE GAGE PLANE COMMON DIMENSIONS A1 (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 1.20 A1 0.05 – 0.15 A2 0.90 1.00 1.05 Notes: 1.This package conforms to JEDEC reference MO-183. D 13.20 13.40 13.60 2.Dimensions D1 and E do not include mold protrusion. Allowable D1 11.70 11.80 11.90 Note 2 protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. E 7.90 8.00 8.10 Note 2 L 0.50 0.60 0.70 L1 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e 0.55 BASIC 12/06/02 TITLE DRAWING NO. REV. 2325 Orchard Parkway 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline San Jose, CA 95131 28T C R Package, Type I (TSOP) AT28HC256 22 0007N–PEEPR–9/09

AT28HC256 28.7 28U – PGA Dimensions in Millimeters and (Inches). Controlling dimension: Inches. 7.26(0.286) 6.50(0.256) 13.74(0.540) 2.57(0.101) 13.36(0.526) 2.06(0.081) 1.40(0.055) 1.14(0.045) 0.58(0.023) 15.24(0.600) 0.43(0.017) 14.88(0.586) 3.12(0.123) 2.62(0.103) 1.83(0.072) 1.57(0.062) 14.17(0.558) 13.77(0.542) 2.54(0.100) TYP 16.71(0.658) 12.70(0.500) TYP 16.31(0.642) 2.54(0.100) TYP 10.41(0.410) 9.91(0.390) 10/21/03 TITLE DRAWING NO. REV. 2325 Orchard Parkway 28U, 28-pin, Ceramic Pin Grid Array (PGA) San Jose, CA 95131 28U B R 23 0007N–PEEPR–9/09

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