AT24C128C I2C-Compatible (2-Wire) Serial EEPROM 128-Kbit (16,384 x 8) DATASHEET Features  Low-voltage and Standard-voltage Operation ̶ V = 1.7V to 5.5V CC  Internally Organized as 16,384 x 8  2-wire Serial Interface  Schmitt Trigger, Filtered Inputs for Noise Suppression  Bidirectional Data Transfer Protocol  400kHz (1.7V) and 1MHz (2.5V, 2.7V, 5.0V) Compatibility  Write Protect Pin for Hardware Protection  64-byte Page Write Mode ̶ Partial Page Writes Allowed  Self-timed Write Cycle (5ms Max)  High Reliability ̶ Endurance: 1,000,000 Write Cycles ̶ Data Retention: 40 Years  Lead-free/Halogen-free Devices Available  Green Package Options (Pb/Halide-free/RoHS Compliant) ̶ 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, 8-ball VFBGA, and 4-ball WLCSP Packages  Die Sale Options: Wafer Form, Waffle Pack, and Bumped Wafers Description The Atmel® AT24C128C provides 131,072-bits of Serial Electrically Erasable and Programmable Read-Only Memory (EEPROM) organized as 16,384 words of 8 bits each. The device’s cascading feature allows up to eight devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, 8-ball VFBGA, and 4-ball WLCSP packages. In addition, this device operates from 1.7V to 5.5V. Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

1. Pin Configurations and Pinouts Table 1-1. Pin Configuration 8-lead SOIC 8-lead TSSOP Pin Function A Address Input A0 1 8 VCC A0 1 8 VCC 0 A1 2 7 WP A1 2 7 WP A Address Input A2 3 6 SCL A2 3 6 SCL 1 GND 4 5 SDA GND 4 5 SDA A Address Input 2 Top View Top View GND Ground 8-pad UDFN/XDFN 8-ball VFBGA SDA Serial Data SCL Serial Clock Input AA01 12 87 VWCPC A0 1 8 VCC WP Write Protect A2 3 6 SCL A1 2 7 WP GND 4 5 SDA A2 3 6 SCL VCC Device Power Supply Top View GND 4 5 SDA Top View 4-ball WLCSP VCC SCL SDA GND Top View 2. Absolute Maximum Ratings* Operating Temperature . . . . . . . . . . .-55°C to +125°C *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage Storage Temperature . . . . . . . . . . . -65°C to + 150°C to the device. This is a stress rating only and functional operation of the device at these or any Voltage on any pin other conditions beyond those indicated in the with respect to ground . . . . . . . . . . . . . . .-1.0 V +7.0V operational sections of this specification are not implied. Exposure to absolute maximum rating Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V conditions for extended periods may affect device DC Output Current. . . . . . . . . . . . . . . . . . . . . . .5.0mA reliability. 2 AT24C128C [DATASHEET] Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

3. Block Diagram Figure 3-1. Block Diagram VCC GND WP Start SCL Stop SDA Logic Serial EN Control H.V. Pump/Timing Logic LOAD Device COMP Data Recovery Address Comparator LOAD INC A A21 R/W Data Word EC EEPROM A0 Addr/Counter XD YDEC Serial MUX D D /ACK IN OUT LOGIC D OUT 4. Pin Descriptions Serial Clock (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negative- edge clock data out of each device. Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may be wire-ORed with any number of other open-drain or open-collector devices. Device Addresses (A , A , A ): The A , A , and A pins are device address inputs that are hard wired (directly to 2 1 0 2 1 0 GND or to V ) for compatibility with other Atmel AT24C devices. When the pins are hard wired, as many as eight CC 128K devices may be addressed on a single bus system. (Device addressing is discussed in detail in Section 7. “Device Addressing” on page 9). A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A , A , and A pins will be internally pulled down to GND. However, due to 2 1 0 capacitive coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10k or less. Write Protect (WP): The Write Protect input, when connected to GND, allows normal write operations. When WP is connected directly to V , all write operations to the memory are inhibited. If the pin is left floating, the WP pin CC will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10k or less. Table 4-1. Write Protect WP Pin Status Part of the Array Protected At V Full Array CC At GND Normal Read/Write Operations AT24C128C [DATASHEET] 3 Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

5. Memory Organization AT24C128C, 128K Serial EEPROM: The 128K is internally organized as 256 pages of 64-bytes each. Random word addressing requires a 14-bit data word address. 5.1 Pin Capacitance Table 5-1. Pin Capacitance(1) Applicable over recommended operating range from: T = 25°C, f = 1.0MHz, V = 1.7V to 5.5V. A CC Symbol Test Condition Max Units Conditions C Input/Output Capacitance (SDA) 8 pF V = 0V I/O I/O C Input Capacitance (A , A , A , and SCL) 6 pF V = 0V IN 0 1 2 IN Note: 1. This parameter is characterized and is not 100% tested. 5.2 DC Characteristics Table 5-2. DC Characteristics Applicable over recommended operating range from: T = -40°C to +85°C, V = 1.7V to 5.5V (unless otherwise noted). AI CC Symbol Parameter Test Condition Min Typ Max Units V Supply Voltage 1.7 5.5 V CC1 I Supply Current V = 5.0V Read at 400kHz 1.0 2.0 mA CC1 CC I Supply Current V = 5.0V Write at 400kHz 2.0 3.0 mA CC2 CC V = 1.7V 1.0 A CC I Standby Current V = V or V SB1 IN CC SS V = 5.0V 6.0 A CC Input Leakage I V = V or V 0.10 3.0 A LI Current V = 5.0V IN CC SS CC Output Leakage I V = V or V 0.05 3.0 A LO Current V = 5.0V OUT CC SS CC V Input Low Level(1) -0.6 V x 0.3 V IL CC V Input High Level((1) V x 0.7 V + 0.5 V IH CC CC V Output Low Level V = 1.7V I = 0.15mA 0.2 V OL1 CC OL V Output Low Level V = 3.0V I = 2.1mA 0.4 V OL2 CC OL Note: 1. V min and V max are reference only and are not tested. IL IH 4 AT24C128C [DATASHEET] Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

5.3 AC Characteristics Table 5-3. AC Characteristics (Industrial Temperature) Applicable over recommended operating range from: T = -40°C to +85°C, V = 1.7V to 5.5V, CL = 100pF (unless AI CC otherwise noted). Test conditions are listed in Note 2. 1.7V 2.5V, 5.0V Symbol Parameter Min Max Min Max Units f Clock Frequency, SCL 400 1000 kHz SCL t Clock Pulse Width Low 1300 400 ns LOW t Clock Pulse Width High 600 400 ns HIGH t Noise Suppression Time(1) 100 50 ns I t Clock Low to Data Out Valid 50 900 50 550 ns AA Time the bus must be free before a new transmission t 1300 500 ns BUF can start(1) t Start Hold Time 600 250 ns HD.STA t Start Set-up Time 600 250 ns SU.STA t Data In Hold Time 0 0 ns HD.DAT t Data In Set-up Time 100 100 ns SU.DAT t Inputs Rise Time(1) 300 300 ns R t Inputs Fall Time(1) 300 100 ns F t Stop Set-up Time 600 250 ns SU.STO t Data Out Hold Time 50 50 ns DH t Write Cycle Time 5 5 ms WR Endurance(1) 25°C, Page Mode, 3.3V 1,000,000 Write Cycles Notes: 1. This parameter is ensured by characterization and is not 100% tested. 2. AC measurement conditions:  R (connects to V ): 1.3kΩ (2.5V, 5.5V), 10kΩ (1.7V) L CC  Input pulse voltages: 0.3V to 0.7V CC CC  Input rise and fall times: ≤ 50ns  Input and output timing reference voltages: 0.5 x V CC AT24C128C [DATASHEET] 5 Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

6. Device Operation Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will indicate a start or stop condition as defined below. Figure 6-1. Data Validity SDA SCL Data Stable Data Stable Data Change Start Condition: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command. Stop Condition: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode. Figure 6-2. Start and Stop Definition SDA SCL Start Stop 6 AT24C128C [DATASHEET] Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. Figure 6-3. Output Acknowledge 1 8 9 SCL Data In Data Out Start Acknowledge Standby Mode: AT24C128C features a low-power standby mode that is enabled upon power-up and after the receipt of the stop bit and the completion of any internal operations. Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: 1. Create a Start condition (if possible). 2. Clock nine cycles. 3. Create another Start condition followed by Stop condition as shown below. The device should be ready for the next communication after above steps have been completed. In the event that the device is still non-responsive or remains active on the SDA bus, a power cycle must be used to reset the device. Figure 6-4. Software Reset Dummy Clock Cycles SCL 1 2 3 8 9 Start Start Stop Condition Condition Condition SDA AT24C128C [DATASHEET] 7 Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

Figure 6-5. Bus Timing t t HIGH t F R t t LOW LOW SCL t t t t t SU.STA HD.STA HD.DAT SU.DAT SU.STO SDA In t t t AA DH BUF SDA Out Figure 6-6. Write Cycle Timing SCL SDA 8th Bit ACK WORDN (1) t WR Stop Start Condition Condition Note: 1. The write cycle time t is the time from a valid stop condition of a write sequence to the end of WR the internal clear/write cycle. 8 AT24C128C [DATASHEET] Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

7. Device Addressing The 128K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation. The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all 2-wire EEPROM devices. Table 7-1. Device Address Byte Device Type Identifier Hardware Slave Address Bits Read/ Write Package Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SOIC, TSSOP, UDFN, 1 0 1 0 A A A R/W XDFN, VFBGA 2 1 0 WLCSP 1 0 1 0 0 0 1 R/W The next three bits are the A2, A1, and A0 device address bits to allow as many as eight devices on the same bus. These bits must compare to their corresponding hard wired input pins. The A , A , and A pins use an 2 1 0 internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. When using the WLCSP package, the A , A , and A signals are not accessible. The A and A pins are left 2 1 0 2 1 floating, and the previously mentioned automatic pull-down circuit will set these signals to a Logic 0 state. The A signal is internally connected to V . As a result, to properly communicate with the device in the WLCSP 0 CC package, the A2 and A1 software bits must always be set to a Logic 0, and the A0 software bit must be set to Logic 1 for any operation. This requirement has been shown in Table 7-1. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high, and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state. Data Security: AT24C128C has a hardware data protection scheme that allows the user to write protect the whole memory when the WP pin is at V . CC AT24C128C [DATASHEET] 9 Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

8. Write Operations Byte Write: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero, and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller, must then terminate the write sequence with a stop condition. At this time, the EEPROM enters an internally-timed write cycle, t , to the nonvolatile memory. All inputs are WR disabled during this write cycle and the EEPROM will not respond until the write is complete. Figure 8-1. Byte Write S W T R S A I T R Device T First Second O T Address E Word Address Word Address Data P SDA Line M R A A A A S / C C C C B W K K K K Note: * = Don’t care bit Page Write: The 128K EEPROM is capable of 64-byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition. Figure 8-2. Page Write S W T R S A I T R Device T First Second O T Address E Word Address Word Address Data (n) Data (n + x) P SDA Line M R A A A A A S / C C C C C B WK K K K K Note: * = Don’t care bit The data word address lower six bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 64 data words are transmitted to the EEPROM, the data word address will roll-over and the previous data will be overwritten. The address roll-over during write is from the last byte of the current page to the first byte of the same page. Acknowledge Polling: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue. 10 AT24C128C [DATASHEET] Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

9. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations:  Current Address Read  Random Address Read  Sequential Read Current Address Read: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address roll-over during read is from the last byte of the last memory page, to the first byte of the first page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition. Figure 9-1. Current Address Read S T R S A E T R Device A O T Address D Data P SDA Line M R A N S / C O B WK A C K Random Read: A Random Read requires a dummy byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a Current Address Read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition. Figure 9-2. Random Read S W S T R T R S A I A E T R Device T First Word Second Word R Device A O T Address E Address Address T Address D Data (n) P SDA LINE M R A A L A R A N S / C C S C / C O B W K K B K WK A C Dummy Write K Note: * = Don’t care bit AT24C128C [DATASHEET] 11 Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

Sequential Read: Sequential Reads are initiated by either a Current Address Read or a Random Address Read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address maximum address is reached, the data word address will roll-over and the Sequential Read will continue from the beginning of the array. The Sequential Read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition. Figure 9-3. Sequential Read S W T R A I R Device T First Word Second Word T Address E Address Address . . . SDA LINE M R A A L A S / C C S C B W K K B K Dummy Write S T R S A E T R Device A O T Address D Data (n) Data (n + 1) Data (n + 2) Data (n + x) P . . . R A A A A N / C C C C O WK K K K A C K Note: * = Don’t care bit 12 AT24C128C [DATASHEET] Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

10. Ordering Information 10.1 Ordering Code Detail A T 2 4 C 1 2 8 C - S S H M x x - B Atmel Designator Shipping Carrier Option B = Bulk (Tubes) T = Tape and Reel, Standard Quantity Option E = Tape and Reel, Expanded Quantity Option Product Family 24C = Standard I2C Product Variation Serial EEPROM xx = Applies to select packages only. See ordering code table for variation details. Device Density Operating Voltage 128 = 128K M = 1.7V to 5.5V Device Revision Package Device Grade or Wafer/Die Thickness H = Green, NiPdAu Lead Finish, Industrial Temperature Range (-40°C to +85°C) U = Green, Matte Sn Lead Finish, Industrial Temperature Range (-40°C to +85°C) 11 = 11mil wafer thickness Package Option SS = JEDEC SOIC X = TSSOP MA = UDFN ME = XDFN C = VFBGA U = WLCSP WWU = Wafer Unsawn WDT = Die in Tape and Reel AT24C128C [DATASHEET] 13 Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

10.2 Ordering Code Information Delivery Information Operating Atmel Ordering Code Lead Finish Package Form Quantity Range AT24C128C-SSHM-B Bulk (Tubes) 100 per Tube 8S1 AT24C128C-SSHM-T Tape and Reel 4,000 per Reel AT24C128C-XHM-B Bulk (Tubes) 100 per Tube 8X AT24C128C-XHM-T Tape and Reel 5,000 per Reel NiPdAu (Lead-free/Halogen-free) AT24C128C-MAHM-T 5,000 per Reel AT24C128C-MAHM-E 8MA2 Tape and Reel 15,000 per Reel Industrial Temperature AT24C128C-MAHMML-T 5,000 per Reel (-40°C to 85°C) AT24C128C-MEHM-T 8ME1 Tape and Reel 5,000 per Reel AT24C128C-CUM-T 8U2-1 Tape and Reel 5,000 per Reel SnAgCu Ball AT24C128C-UUM0B-T(1) (Lead-free/Halogen-free) 4U-9 Tape and Reel 5,000 per Reel AT24C128C-UUMML-T(1) AT24C128C-WWU11M(2) N/A Wafer Sale Note 2 Notes: 1. WLCSP Package:  This device includes a backside coating to increase product robustness.  CAUTION: Exposure to ultraviolet (UV) light can degrade the data stored in the EEPROM cells. Therefore, customers who use a WLCSP product must ensure that exposure to ultraviolet light does not occur. 2. Contact Atmel Sales for Wafer sales. Package Type 8S1 8-lead, 0.150” wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8X 8-lead, 4.40mm body, Plastic Thin Shrink Small Outline Package (TSSOP) 8MA2 8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Dual No Lead (UDFN) 8ME1 8-pad, 1.80mm x 2.20mm body, Extra Thin DFN (XDFN) 8U2-1 8-ball, Die Ball Grid Array (VFBGA) 4U-9 4-ball, 2 x 2 Grid Array, 0.40mm minimum pitch, Wafer Level Chip Scale Package (WLCSP) 14 AT24C128C [DATASHEET] Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

11. Part Markings AT24C128C: Package Marking Information 8-lead SOIC 8-lead TSSOP 8-lead UDFN 2.0 x 3.0 mm Body ### ATMLHYWW ATHYWW H%@ ###% @ ###% @ AAAAAAAA AAAAAAA YXX 8-ball VFBGA 8-lead XDFN 4-ball WLCSP 2.35 x 3.73 mm Body 1.8 x 2.2 mm Body ###U ### ###U @YMXX YXX YMXX Note 1: designates pin 1 Note 2: Package drawings are not to scale Catalog Number Truncation AT24C128C Truncation Code ###: 2DC Date Codes Voltages Y = Year M = Month WW = Work Week of Assembly % = Minimum Voltage 5: 2015 9: 2019 A: January 02: Week 2 M: 1.7V min 6: 2016 0: 2020 B: February 04: Week 4 7: 2017 1: 2021 ... ... 8: 2018 2: 2022 L: December 52: Week 52 Country of Assembly L ot Number Grade/Lead Finish Material @ = Country of Assembly AAA...A = Atmel Wafer Lot Number U: Industrial/Matte Tin H: Industrial/NiPdAu Trace Code A tmel Truncation XX = Trace Code (Atmel Lot Numbers Correspond to Code) AT: Atmel Example: AA, AB.... YZ, ZZ ATM: Atmel ATML: Atmel 1/5/15 TITLE DRAWING NO. REV. 24C128CSM, AT24C128C Standard Package Marking Package Mark Contact: Information 24C128CSM D DL-CSO-Assy_eng@atmel.com AT24C128C [DATASHEET] 15 Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

12. Packaging Information 12.1 8S1 — 8-lead JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 A – – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.90 BSC D E 6.00 BSC E1 3.90 BSC SIDE VIEW e 1.27 BSC Notes: This drawing is for general information only. L 0.40 – 1.27 Refer to JEDEC Drawing MS-012, Variation AA ØØ 0° – 8° for proper dimensions, tolerances, datums, etc. 3/6/2015 TITLE GPC DRAWING NO. REV. 8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing SWB 8S1 H Package Drawing Contact: Small Outline (JEDEC SOIC) packagedrawings@atmel.com 16 AT24C128C [DATASHEET] Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

12.2 8X — 8-lead TSSOP C 1 Pin 1 indicator this corner E1 E L1 N L Top View End View A b A1 COMMON DIMENSIONS e A2 (Unit of Measure = mm) D SYMBOL MIN NOM MAX NOTE Side View A - - 1.20 A1 0.05 - 0.15 Notes: 1. This drawing is for general information only. A2 0.80 1.00 1.05 Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. D 2.90 3.00 3.10 2, 5 2. Dimension D does not include mold Flash, protrusions or gate E 6.40 BSC burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. E1 4.30 4.40 4.50 3, 5 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25mm b 0.19 0.25 0.30 4 (0.010in) per side. e 0.65 BSC 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess L 0.45 0.60 0.75 of the b dimension at maximum material condition. Dambar L1 1.00 REF cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm. C 0.09 - 0.20 5. Dimension D and E1 to be determined at Datum Plane H. 2/27/14 TITLE GPC DRAWING NO. REV. 8X, 8-lead 4.4mm Body, Plastic Thin Package Drawing Contact: Shrink Small Outline Package (TSSOP) TNR 8X E packagedrawings@atmel.com AT24C128C [DATASHEET] 17 Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

12.3 8MA2 — 8-pad UDFN E 1 8 Pin 1 ID 2 7 D 3 6 4 5 TOP VIEW C SIDE VIEW A2 A A1 E2 b (8x) 8 1 COMMON DIMENSIONS 7 2 Pin#1 ID (Unit of Measure = mm) D2 6 3 SYMBOL MIN NOM MAX NOTE A 0.50 0.55 0.60 5 4 A1 0.0 0.02 0.05 e (6x) A2 - - 0.55 L (8x) K D 1.90 2.00 2.10 BOTTOM VIEW D2 1.40 1.50 1.60 Notes: 1. This drawing is for general information only. Refer to E 2.90 3.00 3.10 Drawing MO-229, for proper dimensions, tolerances, E2 1.20 1.30 1.40 datums, etc. 2. The Pin #1 ID is a laser-marked feature on Top View. b 0.18 0.25 0.30 3 3. Dimensions b applies to metallized terminal and is C 1.52 REF measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on L 0.30 0.35 0.40 the other end of the terminal, the dimension should e 0.50 BSC not be measured in that radius area. 4. The Pin #1 ID on the Bottom View is an orientation K 0.20 - - feature on the thermal pad. 11/26/14 TITLE GPC DRAWING NO. REV. 8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally Package Drawing Contact: Enhanced Plastic Ultra Thin Dual Flat No-Lead YNZ 8MA2 G packagedrawings@atmel.com Package (UDFN) 18 AT24C128C [DATASHEET] Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

12.4 8ME1 — 8-pad XDFN D 8 7 6 5 PIN #1 ID E 1 2 3 4 A1 Top View A Side View e1 b L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 0.10 A – – 0.40 PIN #1 ID A1 0.00 – 0.05 D 1.70 1.80 1.90 0.15 E 2.10 2.20 2.30 b 0.15 0.20 0.25 b e 0.40 TYP e e1 1.20 REF L 0.26 0.30 0.35 End View 9/10/2012 TITLE GPC DRAWING NO. REV. 8ME1, 8-pad (1.80mm x 2.20mm body) DTP 8ME1 B Package Drawing Contact: Extra Thin DFN (XDFN) packagedrawings@atmel.com AT24C128C [DATASHEET] 19 Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

12.5 8U2-1 — 8-ball VFBGA f 0.10 C d0.10 (4X) d0.08 C A1 BALL D A C A1 BALL PAD CORNER PAD CORNER 2 1 Øb A j n0.15m C A B j n0.08m C B E e C D (e1) A1 B d A2 (d1) A TOP VIEW SIDE VIEW BOTTOM VIEW 8 SOLDER BALLS COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.81 0.91 1.00 A1 0.15 0.20 0.25 A2 0.40 0.45 0.50 b 0.25 0.30 0.35 D 2.35 BSC Notes: E 3.73 BSC 1. This drawing is for general e 0.75 BSC 2. Dimension 'b' is measured at the maximum solder ball diameter. e1 0.74 REF 3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu. d 0.75 BSC d1 0.80 REF 6/11/13 TITLE GPC DRAWING NO. REV. 8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch, Package Drawing Contact: Very Thin, Fine-Pitch Ball Grid Array Package GWW 8U2-1 G packagedrawings@atmel.com (VFBGA) 20 AT24C128C [DATASHEET] Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

12.6 4U-9 — 4-ball WLCSP TOP VIEW BOTTOM SIDE k 0.015 (4X) A A1 CORNER 1 2 2 1 A1 CORNER A A E e1 B B db D B d1 d m v 0.015 C d m 0.05 C A B SIDE VIEW A3 A2 A1 COMMON DIMENSIONS (Unit of Measure = mm) A SEATING PLANE SYMBOL MIN TYP MAX NOTE C A 0.260 0.295 0.330 k A1 0.080 0.095 0.110 0.075 C A2 0.160 0.175 0.190 PIN ASSIGNMENT MATRIX A3 0.025 REF 3 D Contact Atmel for details 1 2 d1 0.400 A V SCL CC E Contact Atmel for details B SDA GND e1 0.500 b 0.170 0.185 0.200 Note: 1. Dimensions are NOT to scale. 2. Solder ball composition is 95.5Sn-4.0Ag-0.5Cu. 3. Product offered with Back Side Coating (BSC) 12/23/14 TITLE GPC DRAWING NO. REV. 4U-9, 4-ball 2x2 Array, 0.40/0.50mm Pitch Package Drawing Contact: GFC 4U-9 A Wafer Level Chip-Scale Package (WLCSP) with BSC packagedrawings@atmel.com AT24C128C [DATASHEET] 21 Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

13. Revision History Doc. Rev. Date Comments Added the AT24C128C-MAHMML-T and AT24C128C-UUMML-T package options. Updated 8735D 08/2015 the 8S1 package outline drawing. Corrected reference of the 8U-9 to reflect the 4U-9 package option. Added the UDFN Expanded Quantity Option and the WLCSP package option. 8734C 01/2015 Updated the 8MA2 package outline drawing and the ordering information section. 8734B 09/2012 Updated UDFN package drawing and template and Atmel logo. 8734A 04/2011 Initial document release. 22 AT24C128C [DATASHEET] Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: AT24C128C-MAHM-T AT24C128C-SSHM-B AT24C128C-SSHM-T AT24C128C-XHM-B AT24C128C-XHM-T AT24C128C-MAHM-E AT24C128C-CUM-T AT24C128C-UUM0B-T