Datasheet AS3421 AS3422 Low Power Ambient Noise-Cancelling Speaker Driver 1 General Description Line Input (cid:1) Volume control via serial interface or push buttons The AS3421/22 are speaker driver with Ambient Noise Cancelling (cid:1) 64 steps @ 0.75dB and MUTE, pop-free gain setting function for headsets, headphones or ear pieces. It is intended to improve quality of e.g. music listening, a phone conversation etc. by (cid:1) Fully differential stereo line inputs reducing background ambient noise. ANC processing The fully analog implementation allows the lowest power (cid:1) Feed-forward cancellation consumption, lowest system BOM cost and most natural received voice enhancement otherwise difficult to achieve with DSP (cid:1) Feed-back cancellation with filter loop transfer function implementations. The device is designed to be easily applied to definable via simple RC components existing architectures. (cid:1) Simple in production SW calibration An internal OTP-ROM can be optionally used to store the (cid:1) 12-30dB noise reduction (headset dependent) microphone gain calibration settings as well as all application specific settings. (cid:1) 10-3000Hz wide frequency active noise attenuation (headset dependent) The AS3421/22 can be used in different configurations for best trade-off of noise cancellation, required filtering functions and Monitor Function mechanical designs. (cid:1) For assisted hearing, i.e. to monitor announcements The simpler feed-forward topology is used to effectively reduce frequencies typically up to 2-3kHz. The feed-back topology with (cid:1) Fixed (OTP prog.) ambient sound amplification to compensate either 1 or 2 filtering stages has it strengths especially at very low headphone passive attenuation frequencies. The typical bandwidth for feedback system is from 20Hz up to 1kHz which is a little bit lower than with feed forward systems. Incremental Functions (cid:1) ANC with or without music on the receiving path The filter loop for both systems is determined by measurements, for each specific headset individually, and depends very much on (cid:1) Music Playback mode for lowest power consumption mechanical designs. The gain and phase compensation filter (cid:1) OTP ROM for automatic trimming during production (4 times network is implemented with cheap resistors and capacitors for programmable) lowest system costs. AS3421/22 features also an audio playback only mode which allows Performance Parameter the user to easily switch between ANC on and off mode. In ANC off (cid:1) 7mA @ 1.5V stereo ANC; <1µA quiescent mode unused blocks are automatically switch off to guaranty lowest power consumption in each operating mode. (cid:1) Extended PSRR for 217Hz (cid:1) Increased TDMA noise immunity 2 Key Features Interfaces (cid:1) 2-wire serial control mode & volume inputs Microphone Input (cid:1) Calibration via Line-In or 2-wire serial interface (cid:1) 128 gain steps @ 0.375dB and MUTE with AGC (cid:1) Fixed 1.0-1.8V supply with internal CP (cid:1) Differential, low noise microphone amplifier (cid:1) Single ended or differential mode Package (cid:1) AS3421 QFN24 [4x4mm] 0.5mm pitch (cid:1) Improved supply for electret microphone (cid:1) AS3422 QFN32 [5x5mm] 0.5mm pitch (cid:1) MIC gain OTP programmable High Efficiency Headphone Amplifier 3 Applications (cid:1) 2x23mW, 0.1% THD+N @ 32W , 1.5V supply, 100dB SNR The devices are ideal for wireless devices like stereo Bluetooth (cid:1) Bridged mode for e.g. 300W loads headsets as well as stereo wireless headsets. (cid:1) Click and pop less start-up and mode switching www.austriamicrosystems.com Revision 0.90 1 - 61

AS3421 AS3422 Datasheet - Applications Figure 1. AS3421 Feed Forward ANC Block Diagram Figure 2. AS3422 Feed-Back Block Diagram www.austriamicrosystems.com Revision 0.90 2 - 61

AS3421 AS3422 Datasheet - Contents 4 Contents 1 General Description.................................................................................................................................................................. 1 2 Key Features............................................................................................................................................................................. 1 3 Applications............................................................................................................................................................................... 1 4 Contents.................................................................................................................................................................................... 3 5 Pin Assignments....................................................................................................................................................................... 4 5.1 Pin Descriptions.................................................................................................................................................................................... 5 6 Absolute Maximum Ratings...................................................................................................................................................... 6 7 Electrical Characteristics........................................................................................................................................................... 7 8 Typical Operating Characteristics............................................................................................................................................. 8 9 Detailed Description ................................................................................................................................................................11 9.1 Audio Line Input .................................................................................................................................................................................11 9.2 Microphone Input ...............................................................................................................................................................................12 9.3 Headphone Output .............................................................................................................................................................................14 9.4 Operational Amplifier ..........................................................................................................................................................................15 9.5 SYSTEM ............................................................................................................................................................................................17 9.6 VNEG Charge Pump ..........................................................................................................................................................................20 9.7 OTP Memory & Internal Registers .....................................................................................................................................................20 9.8 2-Wire-Serial Control Interface ...........................................................................................................................................................23 10 Register Description .............................................................................................................................................................27 11 Application Information .........................................................................................................................................................43 11.1 AS3422 Feedback Application Examples ........................................................................................................................................43 11.2 AS3421 Feed Forward Application Examples ..................................................................................................................................47 11.3 Layout Recommendation ................................................................................................................................................................51 11.4 Bill of Materials ................................................................................................................................................................................52 11.5 PCB Footprint Recommendation ......................................................................................................................................................53 12 Package Drawings and Marking...............................................................................................................................................55 Ordering Information ....................................................................................................................................................................59 www.austriamicrosystems.com Revision 0.90 3 - 61

AS3421 AS3422 Datasheet - Pin Assignments 5 Pin Assignments Note: Pin assignment may change in preliminary data sheets. Figure 3. Pin Assignments (Top View) CAUTION: Exposed pad must be connect to VNEG or left unconnected. Exposed pad must NOT be connected to GND or AGND! www.austriamicrosystems.com Revision 0.90 4 - 61

AS3421 AS3422 Datasheet - Pin Assignments 5.1 Pin Descriptions Note: Pin description may change in preliminary data sheets. Table 1. Pin Description for AS3421 AS3422 Pin Number Pin Name Type Description AS3421 AS3422 IOP1L 24 1 ANA IN Filter OpAmp1 Input Left Channel QLINL 2 ANA OUT Line In Gain Stage Output Left Channel QMICL 1 3 ANA OUT MIC GainS tage Output Right Channel AGND 2 4 ANA IN Analog Reference LINL_N 3 5 ANA IN Negative Line In pin of Left Channel LINL_P 4 6 ANA IN Positive Line In pin of Left Channel LINR_P 5 7 ANA IN Positive Line In pin of Right Channel LINR_N 6 8 ANA IN Negative Line In pin of Right Channel Serial Interface Data ANC_CSDA 7 9 MIXED IO ANC Pin (Enable/Disable ANC function) Mode Pin (Power Up/Down, Monitor) MODE_CSCL 8 10 DIG IN Serial Interface Clock MICL 9 11 ANA IN Microphone In Left Channel MICS 10 12 ANA OUT Microphone Supply MICR 11 13 ANA IN Microphone Input Right Channel QMICR 12 14 ANA OUT MIC Gain Stage Output Right Channel QLINR 15 ANA OUT Line In Gain Stage Output Right Channel IOP1R 13 16 ANA IN FilterOpAmp1 Input Right Channel QOP1R 14 17 ANA IN Filter OpAmp1 Output Right Channel IOP2R 18 ANA IN Filter OpAmp2 Input Right Channel QOP2R 19 ANA OUT Filter OpAmp2 Output Right Channel VSS 20 SUP IN VSS supply terminal HPL 15 21 ANA OUT Headphone Output Left Channel HPVSS 22 SUP IN Headphone amplifier VSS supply terminal HPR 16 23 ANA OUT Headphone Output Right Channel HPVDD 17 24 SUP IN Headphone VDD Supply VBAT 18 25 SUP IN Positive supply terminal of IC CPP 19 26 ANA OUT VNEG ChargePump Flying Capacitor Positive Terminal GND 20 27 GND VNEG ChargePump Negative Supply CPN 21 28 ANA OUT VNEG ChargePump Flying Capacitor Negative Terminal VNEG 22 29 SUP IO VNEG ChargePump Output QOP2L 30 ANA OUT Filter OpAmp2 Output Left Channel IOP2L 31 ANA IN Filter OpAmp2 Input Left Channel QOP1L 23 32 ANA OUT Filter OpAmp1 Output Right Channel VNEG 25 33 SUP IN Exposed Pad: connect to VNEG or leave it unconnected www.austriamicrosystems.com Revision 0.90 5 - 61

AS3421 AS3422 Datasheet - Absolute Maximum Ratings 6 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 7 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The device should be operated under recommended operating conditions. Table 2. Absolute Maximum Ratings Parameter Min Max Units Comments Reference Ground Defined as in GND Supply terminals -0.5 2.0 V Applicable for pin VBAT, HPVDD Ground terminals -0.5 0.5 V Applicable for pins AGND Negative terminals -2.0 0.5 V Applicable for pins VNEG, VSS, HPVSS Voltage difference at VSS terminals -0.5 0.5 V Applicable for pins VSS, HPVSS VNEG 5.0 Pins with protection to VBAT V Applicable for pins CPP, CPN -0.5 VBAT+0.5 VSS 5.0 Applicable for pins LINL_P/N, LINR_P/N, MICL/ Pins with protection to HPVDD V -0.5 HPVDD+0.5 R, HPR, HPL, QMICL/R, QLINL/R, IOPx, QOPx VSS Applicable for pins MICS, ANC_CSDA, other pins 5 -0.5 MODE_CSCL Input Current (latch-up immunity) -100 100 mA Norm: JEDEC 17 Continuous Power Dissipation (TA = +70ºC) Continuous Power Dissipation - 200 mW PT1 for QFN16/24/32 package Electrostatic Discharge Electrostatic Discharge HBM +/-2 kV Norm: JEDEC JESD22-A114C Temperature Ranges and Storage Conditions Junction Temperature +110 ºC Storage Temperature Range -55 +125 ºC Humidity non-condensing 5 85 % Moisture Sensitive Level 3 Represents a max. floor life time of 168h The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/ Package Body Temperature 260 ºC JEDEC J-STD-020“Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. 1. Depending on actual PCB layout and PCB used www.austriamicrosystems.com Revision 0.90 6 - 61

AS3421 AS3422 Datasheet - Electrical Characteristics 7 Electrical Characteristics VBAT = 1.0V to 1.8V, TA = -20ºC to +85ºC. Typical values are at VBAT = 1.5V, TA = +25ºC, unless otherwise specified. All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Table 3. Electrical Characteristics Symbol Parameter Condition Min Max Unit TA Ambient Temperature Range -20 +85 °C Supply Voltages GND Reference Ground 0 0 V normal operation with MODE pin high 1.0 1.8 V VBAT, Battery Supply Voltage HPVDD Two wire interface operation 1.4 1.8 V VNEG ChargePump Voltage -1.8 -0.7 V Analog neg. Supply Voltages VSS -1.8 -0.7 V HPVSS, VSS, VNEG To achieve good performance, the negative Difference of Ground Supplies VDELTA- GND, AGND supply terminals should be connected to low -0.1 0.1 V impedance ground plane. Difference of Negative Supplies VDELTA-- VSS, VNEG, HPVSS Charge pump output or external supply -0.1 0.1 V VDELTA+ Difference of Positive Supplies VBAT-HPVDD -0.25 0.25 V Other pins VMICS Microphone Supply Voltage MICS 0 3.6 V MICL/R, HPR, HPL, QMICL/R, QLINL/R, VHPVDD Pins with diode to HPVDD IOPx, QOPx VSS 3.6 V VVBAT Pins with diode to VBAT CPP, CPN VNEG VBAT V VCONTROL Control Pins MODE_CSCL, ANC_CSDA VSS 3.7 V VNEG -0.5 HPVDD +0.5 VTRIM Line Input & Application Trim Pins LINL_P, LINL_N, LINR_P, LINR_N or -1.8 or 1.8 V Symbol Parameter Condition Min Typ Max Unit VBAT<0.8V 20 µA Ileak Leakage current VBAT<0.6V 10 µA Block Power Requirements @ 1.5V VBAT IOFF Off mode current MODE pin low, device switched off 1 µA ISYS Reference supply current Bias generation, oscillator, ADC6, VNEG 0.25 mA ILIN LineIn gain stage current no signal, stereo 0.5 mA IMIC Mic gain stage current no signal, stereo 2.10 mA IHP Headphone stage current no signal 1.70 mA IMICS MICS charge pump current no load 30 µA IMIN Minimal supply current Sum of all above blocks 4.6 mA IOP1 OP1 supply current no load 0.64 mA IOP2 OP2 supply current no load 0.64 mA www.austriamicrosystems.com Revision 0.90 7 - 61

AS3421 AS3422 Datasheet - Electrical Characteristics Symbol Parameter Condition Min Typ Max Unit IMICB Microphone bias current 200µA per microphone via charge pump 0.9 mA VBAT = 1.8V 2,8 mA IPB Low Power Playback Mode VBAT = 1.5V 2,5 mA VBAT = 1.0V 2 mA www.austriamicrosystems.com Revision 0.90 8 - 61

AS3421 AS3422 Datasheet - Typical Operating Characteristics 8 Typical Operating Characteristics VBAT = +1.5V, C1=100nF, C2=10µF, C3=1µF, C6=100nF, C5=10µF, C13=10µF, C12=2.2µF, C14=2.2µF TA = +25ºC and HP_MUX_OTP set to ‘3’ unless otherwise specified. Figure 4. THD+N vs. Pout; Line to HPH; 16W single ended stereo Figure 5. THD+N vs. Pout; Line to HPH; 32W single ended stereo 10 10 1V 1V 1.5V 1.5V 1.8V 1.8V 1 1 %] %] N [ N [ + + D D H H T 0,1 T 0,1 0,01 0,01 1 10 100 1 10 100 Pout [mW] Pout [mW] Figure 6. THD+N vs. f; Line to HPH; 1mW load per channel Figure 7. THD+N vs. f; Line to HPH; 10mW load per channel 1,5 15 1 16 Ohm 1 16 Ohm 32 Ohm 32 Ohm Pout Pout 1,0 10 %] 0,1 W] %] 0,1 W] D+N [ out [m D+N [ out [m H P H P T 0,01 0,5 T 0,01 5 0,001 0,0 0,001 0 10 100 1k 10k 10 100 1k 10k f [Hz] f [Hz] Figure 8. THD+N vs. f; 20mW and 30mW per channel Figure 9. Frequency Response 30mW@16W ; Line to HPH 0,5 1 0,4 30 B] d 0,3 se [ 0,2 n HD+N [%] 0,1 20 Pout [mW] ncy Respo -00,,011 T e 0,01 10 qu -0,2 e THD+N 16 Ohm Fr -0,3 THD+N 32 Ohm Pout 16 Ohm -0,4 Pout 32 Ohm 0,001 0 -0,5 10 100 1k 10k 10 100 1k 10k f [Hz] f [Hz] www.austriamicrosystems.com Revision 0.90 9 - 61

AS3421 AS3422 Datasheet - Typical Operating Characteristics Figure 10. Frequency Response 20mW@32W ; Line to HPH Figure 11. Microphone Supply FFT 0,5 0 0,4 -20 B] d 0,3 se [ 0,2 -40 on V] -60 p 0,1 B s d Re 0 s [ -80 y m nc -0,1 Vr-100 e u -0,2 q e -120 Fr -0,3 -140 -0,4 -0,5 -160 10 100 1k 10k 10 100 1k 10k f [Hz] f [Hz] Figure 12. VNEG CP Voltage vs. CP load current with different Figure 13. VNEG Efficiency vs.IVNEG with different VBAT supply VBAT supply voltages voltages 0 0 1.8V 1.8V 1.5V 1.5V 1.0V 1.0V -0,5 -0,5 V[V]NEG -1 V[V]NEG -1 -1,5 -1,5 -2 -2 0 25 50 75 100 125 150 175 200 0 25 50 75 100 125 150 175 200 IVNEG[mA] IVNEG[mA] Figure 14. VMIC_OUT vs. IMIC_OUT 4 VBAT = 1.8V 3,5 VBAT = 1.5V 3 2,5 V] [ UT 2 O _ C MI 1,5 V 1 0,5 0 0 200 400 600 800 I [µA] MIC_OUT www.austriamicrosystems.com Revision 0.90 10 - 61

AS3421 AS3422 Datasheet - Typical Operating Characteristics Figure 15. Typical Performance Data, Feed Forward configuration with an over the ear headset Feed Forward Topology - Over the Ear Headset 10 5 ] B 0 d [ e -5 c n a m -10 r o rf -15 e P C -20 N A -25 -30 10 100 1000 10000 f [Hz] Figure 16. Typical Performance Data, Feedback configuration with an on ear headset Feedback Topology - On Ear Headset 10 5 ] B 0 d [ e c -5 n a m -10 r o f r -15 e P C -20 N A -25 -30 10 100 1000 10000 f [Hz] www.austriamicrosystems.com Revision 0.90 11 - 61

AS3421 AS3422 Datasheet - Detailed Description 9 Detailed Description This section provides a detailed description of the device related components. 9.1 Audio Line Input The chip features one line input. The blocks can work in mono differential or in stereo single ended mode. In addition to the 12.5-25kW input impedance, LineIn has a termination resistor of 10kW which is also effective during MUTE to charge eventually given input capacitors. 9.1.1 Gain Stage The Line In gain stage is designed to have 63 gain steps of 0.75dB with a max gain of 0dB plus MUTE per default. By setting the bit Line Gain +3dB in register 0x33 the gain range can be changed from -46.5dB....0dB to -43.5dB ....+3dB. In default, the gain will be ramped up from MUTE to 0dB during startup. There is a possibility to make the playback volume user controlled by the VOL pin with an ADC converted VOL voltage or UP/DOWN buttons. If the device is configured to control the line input volume via push-buttons the device ramps the gain from -46.5dB to 0dB if no button is pressed. If a user presses a button while ramping up the ramping mechanism will be stopped automatically. In monitor mode, the gain stage can be set to an fixed default attenuation level for reducing the loudness of the music. To avoid unwanted pop noise in this special mode the internal state machine support very smooth gain fading to avoid unwanted acoustic effects. Figure 17. Fully Differential Stereo Line Inputs 9.1.2 Parameter VBAT=1.5V, TA= 25ºC, unless otherwise specified. Table 4. Line Input Parameter Symbol Parameter Condition Min Typ Max Unit 0.6* VLIN Input Signal Level VBAT VBAT VPEAK 0dB gain (12.5k // 10k) 5.6 kΩ RLIN Input Impedance -46.5dB gain (25k // 10k) 7.2 kΩ MUTE 10 kΩ ∆RLIN Input Impedance Tolerance ±30 % CLIN Input Capacitance 5 pF ALIN Programmable Gain -46.5 +0 dB Gain Steps Discrete logarithmic gain steps 0.75 dB Gain Step Accuracy 0.5 dB ALINMUTE Mute Attenuation 100 dB www.austriamicrosystems.com Revision 0.90 12 - 61

AS3421 AS3422 Datasheet - Detailed Description Table 4. Line Input Parameter (Continued) Symbol Parameter Condition Min Typ Max Unit Button Mode, Tinit=400ms 80 ∆ALIN Gain Ramp Rate ms/step Monitor Mode 8 VATTACK Limiter Activation Level HPL/R start of neg. clipping VPEAK VNEG VDECAY Limiter Release Level HPL/R +0.3 VPEAK tATTACK Limiter Attack Time 4 µs tDECAY Limiter Decay Time 8 ms 9.2 Microphone Input The AFE offers two microphone inputs and one low noise microphone voltage supply (microphone bias). The inputs can be switched to single ended or differential mode. Figure 18. Microphone Input MICR MICR QMICR QMICR AGND AGND QMICL QMICL MICL MICL AGND stereo mode mono differential mode 9.2.1 Gain Stage & Limiter The Mic Gain Stage has programmable Gain within -11.25dB…+36dB in 128 steps of 0.375dB. As soft-start function is implemented for an automatic gain ramping implemented with steps of 4ms to fade in the audio at the end of the start-up sequence. A limiter automatically attenuates high input signals. The AGC has 127 steps with 0.375dB with a dynamic range of the full gain stage. In some design it is necessary to switch of the AGC functionality. This can be done in register 0x17 by setting bit ‘1’. In monitor mode, the gain stage can be set to an fixed (normally higher) gain level or be controlled by the VOL pin. 9.2.2 Microphone Supply The MICS charge pump is providing a proper microphone supply voltage for low supply voltage supply. The integrated microphone supply supports basically 3 different modes. The first mode, also called SWITCH-MODE, for 1.8V supply is to have a direct connection with an integrated switch from VBAT to MICS. The microphone supply pin of AS3421/22 is in this mode directly connected to VBAT. For some applications a 1.8V microphone supply is high enough to operate a microphone properly. This mode is more commonly used in devices with a fixed power supply like in Bluetooth headsets. The internal microphone charge pump is switched off in this mode. This can help also reducing the external filter capacitors for the microphone supply. Please mind that the sensitivity of your microphone can be reduced in this mode. www.austriamicrosystems.com Revision 0.90 13 - 61

AS3421 AS3422 Datasheet - Detailed Description The second mode, with the name CHAREGPUMP_MODE, is the most commonly used mode which is per default enabled. In this mode the internal charge pump is enabled. The charge pump doubles the supply voltage of AS3421/22 with a high output impedance of the charge pump in order to make external passive filters more effective. If doubling the supply voltage is not enough the microphone supply can be switched to a special regulated mode which increases the output voltage but with a little bit higher output noise. This setting can be found in register 0x35. The third mode is the OFF MODE. This mode allows the user to switch of the microphone supply if not needed (e.g. playback without ANC) 9.2.3 Parameter VBAT=1.5V, TA= 25ºC unless otherwise specified. Table 5. Microphone Input Parameter Symbol Parameter Condition Min Typ Max Unit VMICIN0 Input Signal Level AMIC = 24dB 40 mVP VMICIN1 AMIC = 30dB 20 mVP VMICIN2 AMIC = 36dB 10 mVP RMICIN Input Impedance MICP to AGND 7.5 kW -7 ∆MICIN Input Impedance Tolerance +33 % CMICIN Input Capacitance 5 pF AMIC Programmable Gain -11.25 +36 dB Gain Steps Discrete logarithmic gain steps 0.375 dB Gain Step Precision 0.15 dB ∆AMIC Gain Ramp Rate Tinit=64ms 4 ms/step VATTACK Limiter Activation Level 0.67 1 VPEAK related to VBAT or VNEG VDECAY Limiter Release Level 0.4 1 AMICLIMIT Limiter Gain Overdrive 127 @ 0.375dB 36 dB tATTACK Limiter Attack Time 5 µs/step tDECAY-DEB Limiter Decay Debouncing Time 64 ms tDECAY Limiter Decay Time 4 ms/step VMICS Microphone Output Voltage no output load 2.7 V IMICS Microphone Supply Current no output load 30 µA ROUT_CP CP Output Resistance 400µA load 900 W Recommended minimum microphone output 170 µA current @ Vbat = 1.5V IMIC_MIN Microphone Output Current Recommended minimum microphone output 300 µA current @ Vbat = 1.8V Recommended maximum microphone output 500 µA current @Vbat = 1.5V IMIC_MAX Microphone Output Current Recommended maximum microphone output 700 µA current @Vbat = 1.8V www.austriamicrosystems.com Revision 0.90 14 - 61

AS3421 AS3422 Datasheet - Detailed Description 9.3 Headphone Output The headphone output is a true ground output using VNEG as negative supply, designed to provide the audio signal with 2x12mW @ 16W -64W , which are typical values for headphones. It is also capable to operate in bridged mode for higher impedance (e.g. 300)W headphone. In this mode the left output is carrying the inverted signal of the right output shown in Figure20. Figure 19. Headphone Output Single Ended Mode QMicR HPVDD QOP1R X U QOP2R M open LineInR HPR AGND HPL LineInL Pop open Click Control QOP2L X U QOP1L M HPVSS QMicL LineIn gain stage Figure 20. Headphone Output Differential Mode 9.3.1 Input Multiplexer The signal from the line-input gain stage gets summed at the input of the headphone stage with the microphone gain stage output, the first filter opamp output or the second filter opamp output. The microphone gain stage output is used per default. It is also possible to playback without ANC by only using the line-input gain stage with no other signal on the multiplexer. For the monitor mode, the setting of this input multiplexer can be changed to another source, normally to the microphone. 9.3.2 No-Pop Function The No-Pop startup of the headphone stage takes 60ms to 120ms dependent on the supply voltage. 9.3.3 No-Clip Function The headphone output stage gets monitored by comparator stages which detect if the output signal starts to clip. This signal is used to reduce the LineIn gain to avoid distortion of the output signal. A hystereses avoids jumping between 2 gain steps for a signal with constant amplitude. www.austriamicrosystems.com Revision 0.90 15 - 61

AS3421 AS3422 Datasheet - Detailed Description 9.3.4 Over-Current Protection The over-current protection has a threshold of 150-200mA and a debouncing time of 8µs. The stage is forced to OFF mode in an over-current situation. After this, the headphone stage tries to power up again every 8ms as long as the over-current situation still exists or the stage is turned off manually. 9.3.5 Parameter VBAT=1.5V, TA= 25ºC, unless otherwise specified. Table 6. Headphone Output Parameter Symbol Parameter Condition Min Typ Max Unit RL_HP Load Impedance Stereo mode 16 W CL_HP Load Capacitance Stereo mode 100 pF RL=64W 12 mW PHP Nominal Output Power RL=32W 24 mW RL=16W 34 mW PSRRHP Power Supply Rejection Ratio 200Hz-20kHz, 720mVpp, RL=16Ω 90 dB 9.4 Operational Amplifier While AS3421 offers only one operational amplifier for feed-forward ANC, AS3422 features an additional operational amplifier stage to support feed-back ANC or any other additional needed filtering. Both operational amplifiers stages can be activated and used individually. While OP1 stage is always configured as inverting amplifier, OP2 stage can be also switched to a non-inverting mode with an adjustable gain of 0...+10.5dB. Figure 21. Operational Amplifiers 0..10.5dB IOP1R IOP2R AGND QOP1R QOP2R QOP2R IOP2R AGND AGND IOP2L QOP1L QOP2L QOP2L IOP1L IOP2L AGND 0..10.5dB OP1 OP2 inverting mode OP2 non-inverting mode www.austriamicrosystems.com Revision 0.90 16 - 61

AS3421 AS3422 Datasheet - Detailed Description 9.4.1 Parameter VBAT=1.5V, TA= 25ºC, unless otherwise specified. Table 7. Headphone Output Parameter Symbol Parameter Condition Min Typ Max Unit RL_OP Load Impedance Single ended 1 kW CL_OP Load Capacitance Single ended 100 pF GBWOP Gain Band Width 4.3 MHz VOS_OP Offset Voltage 6 mV VEIN_HP Equivalent Input Noise 200Hz-20kHz 2.6 µV www.austriamicrosystems.com Revision 0.90 17 - 61

AS3421 AS3422 Datasheet - Detailed Description 9.5 SYSTEM The system block handles the power up and power down sequencing, as well as, the mode switching. 9.5.1 Power Up/Down Conditions The chip powers up when one of the following conditions is true: Table 8. Power UP Conditions # Source Description 1 MODE_CSCL pin In stand-alone mode, MODE pin has to be driven high to turn on the device 2 I2C start In I2C mode, a I2C start condition turns on the device The chip automatically shuts off if one of the following conditions arises: Table 9. Power DOWN Conditions # Source Description 1 MODE pin Power down by driving MODE_CSCL pin to low 2 SERIF Power down by SERIF writing 0h to register 20h bit <0> 3 Low Battery Power down if VBAT is lower than the supervisor off-threshold 4 VNEG CP OVC Power down if VNEG is higher than the VNEG off-threshold 9.5.2 Start-up Sequence The start-up sequence depends on the used mode. In stand-alone mode the sequence runs automatically, in I2C mode(I2C MODE bit has to be pre-trimmed) the sequence runs till a defined state and waits then for an I2C command. Either the automatic sequence is started by setting the CONT_PWRUP bit in addition to the PWR_HOLD bit. If only the PWR_HOLD is set all enable bits for headphone, microphone, etc have to be set manually. Figure 22. Stand-Alone Mode Start-Up Sequence www.austriamicrosystems.com Revision 0.90 18 - 61

AS3421 AS3422 Datasheet - Detailed Description Figure 23. I2C Mode Start-Up Sequence The total start-up time (including fade-in of the gain stages) can be reduced to 600ms by OTP setting. 9.5.3 MODE_CSCL Switching When the chip is in stand-alone mode (no I2C control), the mode can be switched with different levels on the MODE pin. Table 10. MODE_CSCL Operation Modes MODE MODE_CSCL pin Description OFF LOW (VSS) Chip is turned off ANC HIGH (VBAT) Chip is turned on and active noise cancellation is active Chip is turned on and monitor mode is active In Monitor mode, a different (normally higher) microphone preamplifier gain can be chosen to get an amplification of the surrounding noise. This volume can be either fixed or be controlled by the VOL input. MONITOR VBAT/2 To get rid of the low pass filtering needed for the noise cancellation, the headphone input multiplexer can be set to a different (normally to MIC) source. In addition, the LineIn gain can be lowered to reduce the loudness of the music currently played back. In I2C mode, the monitor mode can be activated be setting the corresponding bit in the system register. www.austriamicrosystems.com Revision 0.90 19 - 61

AS3421 AS3422 Datasheet - Detailed Description 9.5.4 ANC_CSDA Switching For Bluetooth applications it is sometimes a requirement to switch off the ANC function while listening to music or having a phone call. Because the fully differential audio outputs of the Bluetooth chip are directly connected to the line input of the AS3421/22 it is not possible to simply switch off the ANC chip to do music playback without ANC.In order to avoid an expensive bypass path with mechanical or electrical switches the AS3421/22 features a special low power audio playback mode. In this mode the device enters a low power mode where the ANC function is disabled and the blocks which are not necessary in this mode are automatically switched off to safe system power. This audio playback mode can be entered by simply pulling the ANC_SCDA pin to low. Figure 24. ANC / CSDA Switching An example how to implement this feature is shown in Figure24. In default operation (ANC enabled) the ANC_CSDA pin is pulled high. If the device should enter the low power playback mode the pin is pulled low with the switch S1. Once the pin is pulled low the device enters after 200ms the playback mode. As long as the pin is low the device stays in the playback only mode. If the feature is for some reason not required it can also be disabled by setting the bit NO_PB_MODE_OTP in register 0x33. Once this bit is set to ‘1’ the status of pin ANC_CSDA has no influence on the device any more. Besides the low power playback mode the ANC_CSDA pin supports also volume control via push buttons. In order to enable this feature the corresponding bit VOL_BUTTON_MODE_OTP is register 0x33 has to be set to ‘1’. Once this bit is set, the device can not support the low power playback mode via ANC_CSDA pin any more. An example on how to connect the push buttons for volume control is shown in Figure24 with the push buttons S2 and S3. Table 11. ANC_CSDA Operation Modes NO_PB_MODE_OTP VOL_BUTTON_MODE_OTP ANC_CSDA Description Bit Bit Pin 0 0 high Normal ANC operation 0 0 high -> low Device enters low power playback mode 0 0 low -> high Device returns to normal ANC operation Normal ANC operation. No influence on operation via 1 0 X ANC_CSDA pin. X 1 high Volume Control Mode via Button - Volume up X 1 High Imp. Volume Control Mode via Button - No Volume change X 1 low Volume Control Mode via Button - Volume down www.austriamicrosystems.com Revision 0.90 20 - 61

AS3421 AS3422 Datasheet - Detailed Description 9.6 VNEG Charge Pump The VNEG charge pump uses one external 1uF capacitor to generate a negative supply voltage out of the battery input voltage to supply all audio related blocks. This allows a true-ground headphone output with no more need of external dc-decoupling capacitors. 9.6.1 Parameter VBAT=1.5V, TA= 25ºC, unless otherwise specified. Table 12. Headphone Output Parameter Symbol Parameter Condition Min Typ Max Unit VIN Input voltage VBAT 1.0 1.5 1.8 V VOUT Output voltage VNEG -0.7 -1.5 -1.8 V CEXT External flying capacitor 1 µF 9.7 OTP Memory & Internal Registers The OTP memory consists of OTP register and the OTP fuses.The OTP register can be written as often as wanted but will lose the content on power off. The OTP fuses are intended to store basic chip configurations as well as the microphone gain settings to optimize the ANC performance and get rid of sensitivity variations of different microphones. Burning the fuses can only be done once and is a permanent change, which means the fuses keep the content even if the chip is powered down. This AS3421/22 offers 4 register set for storing the microphone gain making it possible to change the gain 3 times for re-calibration or other purposes. When the chip is controlled by a microcontroller via I2C, the OTP memory don’t has to be used. The chip configuration can be stored in the flash memory of the Bluetooth- or wireless chipset. 9.7.1 Register & OTP Memory Configuration Figure25 is showing the principal register interaction. Figure 25. Register Access OTP WRITE BURN OTP Register OTP 10h...16h; 30h...35h Fuses I2 OTP READ LOAD C IF normal I2C write RReeggiisstteerr 0x88h,0..x.291,0hxA 0xB, 0xC, 0x21 normal I2C read OTP path is default but can be switched by register setting Registers 0x8, 0x9, 0xA, 0xB, 0xC and 0x21 have only effect when the corresponding “REG_ON” bit is set, otherwise the chip operates with the OTP Register settings which are loaded from the OTP fuses at every start-up. All registers settings can be changed several times, but will loose the content on power off. When using the I2C mode, the chip configuration has to be loaded from the micro controller after every start-up. In stand alone mode the OTP fuses have to be programmed for a permanent change of the chip configuration. A single OTP cell can be programmed only once. Per default, the cell is “0”; a programmed cell will contain a “1”. While it is not possible to reset a programmed bit from “1” to “0”, multiple OTP writes are possible, but only additional unprogrammed “0”-bits can be programmed to “1”. Independent of the OTP programming, it is possible to overwrite the OTP register temporarily with an OTP write command at any time. This setting will be cleared and overwritten with the hard programmed OTP settings at each power-up sequence or by a LOAD operation. www.austriamicrosystems.com Revision 0.90 21 - 61

AS3421 AS3422 Datasheet - Detailed Description The OTP memory can be accessed in the following ways: LOAD Operation. The LOAD operation reads the OTP fuses and loads the contents into the OTP register. A LOAD operation is automatically executed after each power-on-reset. WRITE Operation. The WRITE operation allows a temporary modification of the OTP register. It does not program the OTP. This operation can be invoked multiple times and will remain set while the chip is supplied with power and while the OTP register is not modified with another WRITE or LOAD operation. READ Operation. The READ operation reads the contents of the OTP register, for example to verify a WRITE command or to read the OTP memory after a LOAD command. BURN Operation. The BURN operation programs the contents of the OTP register permanently into the OTP fuses. Don’t use old or nearly empty batteries for burning the fuses. Attention: If you once burn the OTP_LOCK bit, no further programming, e.g. setting additional “0” to “1”, of the OTP can be done. For production, the OTP_LOCK bit must be set to avoid an unwanted change of the OTP content during the lifetime of the product. 9.7.2 OTP Fuse Burning As many wireless applications like Bluetooth single chip solutions support programmable solutions as well as ROM versions it is in ROM versions necessary to store microphone gain compensation data and the general ANC configuration inside the ANC chip because there is not other way to configure the ANC chip during startup. In order to guaranty successful trimming of AS3421/22 it is necessary to provide a decent environment for the trimming process. In Figure26 a principal block diagram is shown for trimming the AS3421/22 properly in production. Figure 26. Block Diagram for Production Environment The most important block is the external power supply. Usually it is possible to trim the AS3421/22 with a single supply voltage of min. 1.7V in laboratory environment but as soon as it comes to mass production we highly recommend buffering also VNEG supply of the chip. As highlighted in the block diagram it is mandatory to get a voltage difference between VPOS and VNEG of min. 3.4V to guaranty proper trimming of the device. no current sink capability, therefore it is possible to buffer it external with a negative power supply. The VNEG voltage applied to VNEG pin must be lower than the voltage created with the charge pump. This means if the typical VNEG output voltage is -1.5V you can easily apply externally - 1.7V. The charge pump switches then automatically into skip mode. Important for applying an external buffer and switching on the ANC device is the timing in order to avoid latch up on the ANC device. The timing diagram in Figure 2 shows clearly that it is important that there is a certain delay between VBAT and the MODE /CSCL pin necessary. This delay is mandatory in order to guaranty that the device starts up properly. In case AS350x is used the delay between VBAT and MODE/CSCL is not necessary. The MODE /CSCL pin powers the ANC device up and the whole sequence to power up the internal charge pump of AS34x0 and AS350x takes approximately 1ms. Once VNEG is settled the external VNEG buffer (e.g. power supply) can be enabled in order to support the charge pump especially during the trim process which can now be started. www.austriamicrosystems.com Revision 0.90 22 - 61

AS3421 AS3422 Datasheet - Detailed Description Figure 27. Timing Diagram for VNEG Buffering To guaranty a successful trimming process it is important to follow exactly the predefined trimming sequence shown inFigure28. As a first step it is important to do a register dump of all OTP registers. This register backup in your system memory is a backup of all register setting and is necessary for the verification after the trim process to make sure that all bits are trimmed correctly. Once the register dump has been done it is important to check the OTP_LOCK in register 0x35. This register indicates if the device is already trimmed or not. In case this bit is set to ‘1’ there is no more trimming possible. The device has obviously already been trimmed before. In case the bit is ‘0’ there is initial or further trimming of the device possible. You enter the trim mode and start the trimming process. Once the trimming is done the most important step is comparing the values trimmed to the device with the original register dump we did right before we started with the actual trimming process. If the verification was successful we know that all bits have been trimmed correctly to AS3501/AS3502. What is important to mention is that the AS3502 and AS3501 have a couple of test bits inside which are per default set to ‘1’. We do not recommend overwriting these bytes. Furthermore it is important to know that it is not possible to change bits once they are trimmed. With AS3501 and AS3502 it is possible to trim the device again if the MAIN_LOCK bit is not set to ‘1’. What is not possible is, is changing a bit from ‘1’ back to zero. If an additional trimming is done it is only possible to change bits from ‘0’ to ‘1’. An example would be the following. A register contains a value of 0x41. If the MAIN_LOCK bit is not set to ‘1’ you can basically re-trim the part but it doesn’t work to change the value from 0x41 to 0x40. What is possible would be a change from 0x41 to 0x43. It is important that all necessary bits are trimmed exactly like in the block diagram shown in Figure28. The internal state machine needs the MAIN_LOCK bit as well as the ALTx_LOCK bits to determine the right microphone register at start-up of the device. If the MAIN_LOCK bit and the ALTx_LOCK bits are not set correctly the result can be malfunction of the device. for detailed implementation of the I2C trimming there is also an application note available which describes the whole process in more detail and includes also some code examples. www.austriamicrosystems.com Revision 0.90 23 - 61

AS3421 AS3422 Datasheet - Detailed Description Figure 28. OTP Burning Process enter “Application Trimm” mode ANC pre burning measurements MAIN_LOCK Y ALT1_LOCK Y ALT2_LOCK Y ALT3_LOCK Y set? set? set? set? N N N N write, burn OTP fuses MIC trimm #2 MIC trimm #3 MIC trimm #4 30-35h, 16-17h write, burn OTP fuses write, burn OTP fuses write, burn OTP fuses Set MAIN_LOCK and 10-11h 12-13h 14-15h SEQ_LOCK Set ALT1_LOCK Set ALT2_LOCK Set ALT3_LOCK trimm verification verification N leave “Application Trimm” OK? mode Y leave “Application Trim” mode ANC post burning measurements verification N Device trimming leave No further MIC OK? failed “Application Trimm” trimming possible mode Y Device trimming succeeded 9.8 2-Wire-Serial Control Interface There is an I2C slave block implemented to have access to 64 byte of setting information. The I2C address is: Adr_Group8 - audio processors (cid:1) 8Eh_write (cid:1) 8Fh_read 9.8.1 Protocol Table 13. 2-Wire Serial Symbol Definition Symbol Definition RW Note S Start condition after stop R 1 bit Sr Repeated start R 1 bit DW Device address for write R 1000 1110b (8Eh) DR Device address for read R 1000 1111b (8Fh) WA Word address R 8 bit A Acknowledge W 1 bit N No Acknowledge R 1 bit reg_data Register data/write R 8 bit data (n) Register data/read W 8 bit www.austriamicrosystems.com Revision 0.90 24 - 61

AS3421 AS3422 Datasheet - Detailed Description Table 13. 2-Wire Serial Symbol Definition Symbol Definition RW Note P Stop condition R 1 bit WA++ Increment word address internally R during acknowledge AS3421 AS3422 (=slave) receives data AS3421 AS3422 (=slave) transmits data Figure 29. Byte Write S DW A WA A reg_data A P write register WA++ Figure 30. Page Write S DW A WA A reg_data 1 A reg_data 2 A ... reg_data n A P write register write register write register WA++ WA++ WA++ Byte Write and Page Write formats are used to write data to the slave. The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The device- write address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data bytes on subsequent address locations. For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated START condition followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register byte transmitted from the slave. In Read Mode any number of subsequent register bytes can be read from the slave. The word address is incremented internally. www.austriamicrosystems.com Revision 0.90 25 - 61

AS3421 AS3422 Datasheet - Detailed Description Figure 31. Random Read S DW A WA A Sr DR A data N P read register WA++ Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer from the master. The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the device-write address and the word address. In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus. Figure 32. Sequential Read S DW A WA A Sr DR A data A reg_data 2 A ... reg_data n N P read register read register read register WA++ WA++ WA++ Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. In difference to the Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently. Figure 33. Current Address Read S DR A data A reg_data 2 A ... reg_data n N P read register read register read register WA++ WA++ WA++ To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master sends a not-acknowledge following the last data byte and a subsequent STOP condition. www.austriamicrosystems.com Revision 0.90 26 - 61

AS3421 AS3422 Datasheet - Detailed Description 9.8.2 Parameter Figure 34. 2-Wire Serial Timing TS TSU TH THD TL TPD CSDA CSCL 1-7 88 9 1-7 88 9 1-7 88 9 Start Address R/W ACK Data ACK Data ACK Stop Condition Condition 1 VBAT >=1.4V , TA=25ºC, unless otherwise specified. Table 14. 2-Wire Serial Parameter Symbol Parameter Condition Min Typ Max Unit VCSL CSCL, CSDA Low Input Level (max 30%VBAT) 0 - 0.42 V VCSH CSCL, CSDA High Input Level CSCL, CSDA (min 70%VBAT) 0.98 - V HYST CSCL, CSDA Input Hysteresis 200 450 800 mV VOL CSDA Low Output Level at 3mA - - 0.4 V Tsp Spike insensitivity 50 100 - ns TH Clock high time max. 400kHz clock speed 500 ns TL Clock low time max. 400kHz clock speed 500 ns CSDA has to change Tsetup before rising edge TSU of CSCL 250 - - ns No hold time needed for CSDA relative to rising THD edge of CSCL 0 - - ns CSDA H hold time relative to CSDA edge for TS 200 - - ns start/stop/rep_start CSDA prop delay relative to low going edge of TPD CSCL 50 ns 1. Serial interface operates down to VBAT = 1.0V but with 100kHz clock speed and degraded parameters. www.austriamicrosystems.com Revision 0.90 27 - 61

w 10 Register Description D A ww.austriamicros TAabulAdei do1d5 Rr. e Ig2iCs tReresgNisatemr eOverview b7 b6 b5 b4 b3 b2 b1 b0 atasheet - Registe S3421 AS3422 yste 00-07h reserved r De ms.com 08h MIC_L M01:: ISMCtoe_nreoMoDSOififnDglEeEnd MGaICinL _frVomO LM<I6C:0L> to QMICL or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB scriptio n MIC_REG_ON MICR_VOL<6:0> 09h MIC_R 0: use reg 30h & 31h Gain from MICR to QMICR or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB 1: use reg 08h & 09h LIN_VOL<5:0> LIN_REG_ON LIN_GAIN_+3dB 0Ah LINE_IN 0: use reg 33h and VOL pin 0: 0dB max. Line Gain 0: MUTE; 0x01..0x3F: Gain from LINR/L to QLINR/L or Mixer = -46.5dB...+0dB; 63 steps of 0.75dB with LIN_GAIN_+3dB bit set to ‘0’ 1: use reg 0Ah 1: +3dB max. Line Gain 0x01..0x3F: Gain from LINR/L to QLINR/L or Mixer = -43.5dB...+3dB; 63 steps of 0.75dB with LIN_GAIN_+3dB bit set to ‘1’ HP_MUX<1:0> OP2L<3:0> 0Bh GP_OP_L 0: MIC; 1: OP1; 0: OP2L inverting mode; OP2L_ON OP1L_ON 2: OP2; 3: open 0x1..0xF: OP2L non inverting mode gain = 0...10.5dB; 15 steps of 0.75dB OP_REG_ON HP_MODE OP2R<3:0> R 0Ch GP_OP_R 0: use reg 34h 0: StereoSingleEnd 0: OP2R inverting mode; OP2R_ON OP1R_ON e 1: use reg 0Bh & 0Ch 1: MonoDiff 0x1..0xF: OP2R non inverting mode gain = 0...10.5dB; 15 steps of 0.75dB v isio 0Dh-0Fh reserved n 0 18h-1Fh reserved .9 0 System Register 20h SYSTEM Design_Version<3:0> 1001 REG3F_ON MONITOR_ON CONT_PWRUP PWR_HOLD PWR_REG_ON 0: use reg 0x35 HP_ON MIC_ON LIN_ON MICS_CP_ON MICS_ON 21h PWR_SET 1: use reg 0x21h PWRUP_ LOW_BAT COMPLETE 22h-2Fh reserved 2 8 - 6 1

w Table 15. I2C Register Overview D A ww.austriamicros O10ThAPd RdergisteArNCN_La2me TEST_BITb_75 MGaICinL _frVomOb L6M_IOCTLP t2o< Q6M:0I>CL or Mb5ixer = MUTE, -11.25bd4B...+36dB; 127 stepbs3 of 0.375dB b2 b1 b0 atasheet - Registe S3421 AS3422 yste 11h ANC_R2 ALT1_LOCK MICR_VOL_OTP2<6:0> r De ms.com 12h ANC_L3 TEST_BIT_6 GMaICinL f_rVomO LM_IOCTRP t3o< Q6:M0>ICR or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB scriptio Gain from MICL to QMICL or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB n MICR_VOL_OTP3<6:0> 13h ANC_R3 ALT2_LOCK Gain from MICR to QMICR or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB MICL_VOL_OTP4<6:0> 14h ANC_L4 TEST_BIT_7 Gain from MICL to QMICL or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB MICR_VOL_OTP4<6:0> 15h ANC_R4 ALT3_LOCK Gain from MICR to QMICR or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB 16h MICS_CNTR LowBat + 100mV DEL_ ANC_MUX FAST_START<4:0> 17h PWRUP SEQ_LOCK LIN_AGC_OFF MIC_AGC_OFF 0: ~900ms; 0Eh: ~600ms R ev MICL_VOL_OTP<6:0> is 30h ANC_L TEST_BIT_1 io Gain from MICL to QMICL or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB n 0.90 31h ANC_R TEST_BIT_2 MICR_VOL_OTP<6:0> Gain from MICR to QMICR or Mixer =MUTE, -11.25dB...+36dB; 127 steps of 0.375dB MIC_MON_OTP<6:0> MON_MODE 32h MIC_MON 0: fixed volume Gain from MICl/R to QMICL/R or Mixer = MUTE, -5.625dB...+41.6dB; 0.375dB steps, if MON_MODE is set to 0 1: adj. volume Gain from MICl/R to QMICL/R or Mixer = MUTE, -5.625dB...+41.6dB; 0.375dB steps, adjustable by VOL pin if MON_MODE is set to 1 VOL_BUTTON_ LINE_GAIN_+3dB MIC_MODE_ HP_MODE_ LIN_MON_ATTEN<2:0> NO_PB_MODE_OTP 33h AUDIO_SET 0: PB mode enabled MODE_OTP OTP OTP OTP 0: no attenuation; 1: PB mode disabled 0: Volume Mode disabled 0: 0dB max. Line Gain 0: StereoSingleEnd 0: StereoSingleEnd 1..6: LIN_VOL<6:0> shift by -6dB...-36dB 1: Volume Mode enabled 1: +3dB max. Line Gain 1: MonoDiff 1: MonoDiff 7: MUTE HP_MUX_OTP<1:0> OP2_OTP<3:0> 34h GP_OP 0: MIC; 1: OP1; 0: OP2 inverting mode; OP2_ON_OTP OP1_ON_OTP 2: OP2; 3: - 0x1..0xF: OP2 non inverting mode gain = 0...10.5dB; 15 steps of 0.75dB MAIN_LOCK MON_HP_MUX<1:0> CP_MODE 35h OTP_SYS 0: write reg 30h.. 35h TEST_BIT_3 0: MIC; 1: OP1; 0: Low noise, low voltage MICS_CP_OFF I2C_MODE 1: lock reg 30h..35h 2: OP2; 3: - 1: High output voltage; 3Eh CONFIG_1 EXTBURNCLK OTP_MODE<1:0> 3Fh CONFIG_2 TM34 BURNSW TM_REG34-35 TM_REG30-33 0: READ; 1: LOAD; 2 2: WRITE; 3: BURN 9 - 6 1

AS3421 AS3422 Datasheet - Register Description Table 16. MIC_L Register Name Base Default MIC_L 2-wire serial 00h Left Microphone Input Register Offset: 08h Configures the gain for the left microphone input and defines the microphone operation mode. This register is reset at POR. Bit Bit Name Default Access Bit Description 7 MIC_MODE 0 R/W Selects the microphone input mode 0: single ended stereo mode 1: mono differential mode 6:0 MICL_VOL<6:0> 000 0000 R/W Volume settings for left microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -11.25 dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625 dB gain 11 1111: 36 dB gain Table 17. MIC_R Register Name Base Default MIC_R 2-wire serial 00h Right Microphone Input Register Offset: 09h Configures the gain for the right microphone input and enables register 08h & 09h. This register is reset at POR. Bit Bit Name Default Access Bit Description 7 MIC_REG_ON 0 R/W Defines which registers are used for the microphone settings. 0: settings of register 30h and 31h are used 1: settings of register 08h and 09h are used 6:0 MICR_VOL<6:0> 000 0000 R/W Volume settings for right microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -11.25B gain 00 0010: -10.875 dB gain .. 11 1110: 35.625 dB gain 11 1111: 36 dB gain www.austriamicrosystems.com Revision 0.90 30 - 61

AS3421 AS3422 Datasheet - Register Description Table 18. LINE_IN Register Name Base Default LINE_IN 2-wire serial 00h Line Input Register Offset: 0Ah Configures the attenuation for the line input, defines the line input operation mode and enables register 0Ah. This register is reset at POR. Bit Bit Name Default Access Bit Description 7 LIN_REG_ON 0 R/W Defines which source is used for the line input settings. 0: settings of register 33h and VOL pin are used 1: register 0Ah is used 6 LINE_GAIN_+3dB 0 R/W Selects the line input operating gain range. If this bit is set the gain range of the line input amplifiers is shifted by +3dB. 0: Line Input gain range from -46.5dB...0dB 1: Line Input gain range from -43.5dB...+3dB 5:0 LIN_VOL<5:0> 00 0000 R/W Volume settings for line input, adjustable in 63 steps of 0.75dB. the following gain settings are valid if LINE_GAIN_+3dB bit is set to ‘0’. 00 0000: MUTE 00 0001:-46.5dB gain 00 0010:-45.75dB gain .. 11 1110:-0.75dB gain 11 1111:.0 dB gain Volume settings for line input, adjustable in 63 steps of 0.75dB. the following gain settings are valid if LINE_GAIN_+3dB bit is set to ‘1’. 00 0000: MUTE 00 0001:-43.5dB gain 00 0010:-42.75dB gain .. 11 1110:+2.25dB gain 11 1111:+3 dB gain Table 19. GP_OP_L Register Name Base Default GP_OP_L 2-wire serial 00h Left General Purpose Operational Amplifier Register Offset: 0Bh Enables the left opamp stages, defines opamp 2 mode and gain and sets the HP input multiplexer. This register is reset at POR. Bit Bit Name Default Access Bit Description 7:6 HP_MUX<1:0> 00 R/W Multiplexes the analog audio signal to HP amp 00: MIC: selects QMICL/R output 01: OP1: selects QOP1L/R outputs 10:OP2: selects QOP2L/R output 11: open: no signal mixed together with the line input signal 5:2 OP2L<3:0> 0000 R/W Mode and volume settings for left OP2, adjustable in 15 steps of 0.75dB 0000: OP2L in inverting mode 0001: 0 dB gain, OP2L in non inverting mode 0001: 0.75 dB gain, non inverting .., 1110: 9.75dB gain, non inverting 1111:.10.5 dB gain, non inverting www.austriamicrosystems.com Revision 0.90 31 - 61

AS3421 AS3422 Datasheet - Register Description Table 19. GP_OP_L Register Name Base Default GP_OP_L 2-wire serial 00h Left General Purpose Operational Amplifier Register Offset: 0Bh Enables the left opamp stages, defines opamp 2 mode and gain and sets the HP input multiplexer. This register is reset at POR. Bit Bit Name Default Access Bit Description 1 OP2L_ON 0 R/W Enables left OP 2 0: left OP2 is switched off 1: left OP2 is enabled 0 OP1L_ON 0 R/W Enables left OP 1 0: left OP1 is switched off 1: left OP1 is enabled Table 20. GP_OP_R Register Name Base Default GP_OP_R 2-wire serial 00h Right General Purpose Operational Amplifier Register Offset: 0Ch Enables the right opamp stages, defines opamp 2 mode and gain and sets the HP mode. This register is reset at POR. Bit Bit Name Default Access Bit Description 7 OP_REG_ON 0 R/W Defines which register is used for the opamp and HP settings. 0: settings of register 33h and 34h are used 1: register 0B and 0Ch are used 6 HP_MODE 0 R/W Selects the line input mode 0: single ended stereo mode 1: mono differential mode 5:2 OP2R<3:0> 0000 R/W Mode and volume settings for right OP2, adjustable in 15 steps of 0.75dB 0000: OP2R in inverting mode 0001: 0 dB gain, OP2R in non inverting mode 0001: 0.75 dB gain, non inverting .., 1110: 9.75dB gain, non inverting 1111:.10.5 dB gain, non inverting 1 OP2R_ON 0 R/W Enables right OP 2 0: right OP2 is switched off 1: right OP2 is enabled 0 OP1R_ON 0 R/W Enables right OP 1 0: right OP1 is switched off 1: right OP1 is enabled www.austriamicrosystems.com Revision 0.90 32 - 61

AS3421 AS3422 Datasheet - Register Description Table 21. SYSTEM Register Name Base Default SYSTEM 2-wire serial 31h SYSTEM Register Offset: 20h This register is reset at a POR. Bit Bit Name Default Access Bit Description 7:4 Design_Version<3:0> 1001 R AFE number to identify the design version 1001: for chip version 1v1 3 TESTREG_ON 0 R/W 0: normal operation 1: enables writing to test register 3Eh & 3Fh to configure the OTP and set the access mode. 2 MONITOR_ON 0 R/W Enables the monitor mode 0: normal operation 1: monitor mode enabled 1 CONT_PWRUP 0 R/W Continues the automatic power-up sequence when using the I2C mode 0: chip stops the power-up sequence after the supplies are stable, switching on individual blocks has to be done via I2C commands 1: automatic power-up sequence is continued 0 PWR_HOLD 1 R/W 0: power up hold is cleared and AFE will power down 1: is automatically set to on after power on Table 22. PWR_SET Register Name Base Default 0x11 1111b (stand alone mode) PWR_SET 2-wire serial 0x00 0000b (I2C mode) Power Setting Register Please be aware that writing to this register will enable/disable the corresponding blocks, Offset: 21h while reading gets the actual status. It is not possible to read back e.g ILED settings. This register is reset at POR. Bit Bit Name Default Access Bit Description 7 PWR_REG_ON 0 R/W Defines which register is used for the power settings. 0: all blocks stay on as defined in the start-up sequence 1: register 21h is used 6 LOW_BAT x R VBAT supervisor status 0: VBAT is above brown out level 1: BVDD has reached brown out level 5 PWRUP_COMPLETE x R Power-Up sequencer status 0: power-up sequence incomplete 1: power-up sequence completed 4 HP_ON 0 W 0: switches HP stage off 1: switches HP stage on x R 0: HP stage not powered 1: normal operation 3 MIC_ON 0 W 0: switches microphone stage off 1: switches microphone stage on x R 0: microphone stage not powered 1: normal operation www.austriamicrosystems.com Revision 0.90 33 - 61

AS3421 AS3422 Datasheet - Register Description Table 22. PWR_SET Register Name Base Default 0x11 1111b (stand alone mode) PWR_SET 2-wire serial 0x00 0000b (I2C mode) Power Setting Register Please be aware that writing to this register will enable/disable the corresponding blocks, Offset: 21h while reading gets the actual status. It is not possible to read back e.g ILED settings. This register is reset at POR. Bit Bit Name Default Access Bit Description 2 LIN_ON 0 W 0: switches line input stage off 1: switches line input stage on x R 0: line input stage not powered 1: normal operation 1 MICS_CP_ON 0 W 0: switches microphone supply charge pump off 1: switches microphone supply charge pump on x R 0: microphone supply charge pump not powered 1: normal operation 0 MICS_ON 0 W 0: switches microphone supply off 1: switches microphone supply on x R 0: microphone supply not enabled 1: normal operation www.austriamicrosystems.com Revision 0.90 34 - 61

AS3421 AS3422 Datasheet - Register Description Table 23. ANC_L2 Register Name Base Default ANC_L2 2-wire serial 80h (OTP) Left OTP Microphone Input Register (2nd OTP option) Offset: 10h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 TEST_BIT_5 1 R for testing purpose only 6:0 MICL_VOL_OTP2 000 0000 R/W Volume settings for left microphone input, adjustable in 127 steps of <6:0> 0.375dB 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain Table 24. ANC_R2 Register Name Base Default ANC_R2 2-wire serial 00h (OTP) Right OTP Microphone Input Register (2nd OTP option) Offset: 11h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 ALT1_LOCK 0 R/W 0: additional bits can be fused inside register 10h & 11h 1: OTP fusing for register 10h & 11h gets locked, no more changes can be done. 6:0 MICR_VOL_OTP2 000 0000 R/W Volume settings for right microphone input, adjustable in 127 steps of <6:0> 0.375dB 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain www.austriamicrosystems.com Revision 0.90 35 - 61

AS3421 AS3422 Datasheet - Register Description Table 25. ANC_L3 Register Name Base Default ANC_L3 2-wire serial 80h (OTP) Left OTP Microphone Input Register (3rd OTP option) Offset: 12h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 TEST_BIT_6 1 R for testing purpose only 6:0 MICL_VOL_OTP3 000 0000 R/W Volume settings for left microphone input, adjustable in 127 steps of <6:0> 0.375dB 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain Table 26. ANC_R3 Register Name Base Default ANC_R3 2-wire serial 00h (OTP) Right OTP Microphone Input Register (3rd OTP option) Offset: 13h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 ALT2_LOCK 0 R/W 0: additional bits can be fused inside register 12h & 13h 1: OTP fusing for register 12h & 13h gets locked, no more changes can be done. 6:0 MICR_VOL_OTP3 000 0000 R/W Volume settings for right microphone input, adjustable in 127 steps of <6:0> 0.375dB 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain www.austriamicrosystems.com Revision 0.90 36 - 61

AS3421 AS3422 Datasheet - Register Description Table 27. ANC_L4 Register Name Base Default ANC_L4 2-wire serial 80h (OTP) Left OTP Microphone Input Register (4th OTP option) Offset: 14h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 TEST_BIT_7 1 R for testing purpose only 6:0 MICL_VOL_OTP4 000 0000 R/W Volume settings for left microphone input, adjustable in 127 steps of <6:0> 0.375dB 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain Table 28. ANC_R4 Register Name Base Default ANC_R4 2-wire serial 00h (OTP) Right OTP Microphone Input Register (4th OTP option) Offset: 15h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 ALT3_LOCK 0 R/W 0: additional bits can be fused inside register 14h & 15h 1: OTP fusing for register 14h & 15h gets locked, no more changes can be done. 6:0 MICR_VOL_OTP4 000 0000 R/W Volume settings for right microphone input, adjustable in 127 steps of <6:0> 0.375dB 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain www.austriamicrosystems.com Revision 0.90 37 - 61

AS3421 AS3422 Datasheet - Register Description Table 29. MICS_CNTR Register Name Base Default MICS_CNTR 2-wire serial 00h (OTP) Microphone Supply Regsiter Offset: 16h Configures the low battery threshold value Bit Bit Name Default Access Bit Description 3 LowBat 0 R/W 0: default LowBat value 1: 100mV increase of LowBat threshold 0 DEL_ ANC_MUX 0 R/W 0: default startup timing of AS3421/22 1: HP_MUX_OTP is set to OTP value 0.8s after device startup Table 30. PWRUP_CNTR Register Name Base Default PWRUP_CNTR 2-wire serial 00h (OTP) PowerUp Control Register Offset: 17h Configures chip start-up speed. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 SEQ_LOCK 0 R/W 0: additional bits can be fused inside register 16h & 17h 1: OTP fusing for register 16h & 17h gets locked, no more changes can be done. 6:2 FAST_START 0 0000 R/W 0h: ~900ms start-up time <4:0> 0Eh: ~600ms start-up time 1 LIN_AGC_OFF 0 R/W 0: Line Input AGC enabled 1: Line Input AGC switched off 0 MIC_AGC_OFF 0 R/W 0:Microphone Input AGC enabled 1: Microphone Input AGC switched off Table 31. ANC_L Register Name Base Default ANC_L 2-wire serial 80h (OTP) Left OTP Microphone Input Register Offset: 30h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 TEST_BIT_1 1 R for testing purpose only 6:0 MICL_VOL_OTP 000 0000 R/W Volume settings for left microphone input, adjustable in 127 steps of 0.375dB <6:0> 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain www.austriamicrosystems.com Revision 0.90 38 - 61

AS3421 AS3422 Datasheet - Register Description Table 32. ANC_R Register Name Base Default ANC_R 2-wire serial 80h (OTP) Right OTP Microphone Input Register Offset: 31h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 TEST_BIT_2 1 R for testing purpose only 6:0 MICR_VOL_OTP 000 0000 R/W Volume settings for right microphone input, adjustable in 127 steps of <6:0> 0.375dB 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain www.austriamicrosystems.com Revision 0.90 39 - 61

AS3421 AS3422 Datasheet - Register Description Table 33. MIC_MON Register Name Base Default MIC_MON 2-wire serial 00h (OTP) OPT Microphone Monitor Mode Register Configures the gain for the microphone input in monitor mode. This is a special register, writing needs to Offset: 32h be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 MON_MODE 0 R/W 0: monitor mode is working with fixed microphone gain 1: monitor mode uses adjustable gain via the VOL pin 6:0 MIC_MON_OTP 000 0000 R/W Volume settings for microphone input during monitor mode, adjustable in <6:0> 127 steps of 0.375dB. If MON_MODE bit is set to 1 the gain can be further adjusted via the VOL pin. 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain Table 34. AUDIO_SET Register Name Base Default AUDIO_SET 2-wire serial 00h (OTP) OPT Audio Setting Register Offset: 33h Configures the audio settings. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 NO_PB_MODE 0 R/W This bit defines if the low power music playback mode is enabled or not. In case the bit is set to ‘0’, music playback mode can be entered by pulling the ANC_CSDA pin low. In case the bit is set to ‘1’ the music playback mode is disabled. Pulling the ANC_CSDA pin low has no influence. 0: Music playback mode enabled 1: Music playback mode disabled 6 VOL_BUTTON_MODE 0 R/W If bit is set to ‘1’ the ANC_CSDA pin allows the user to control the line input gain via push-buttons. If bit is set to ‘0’, the volume control is disabled. Please mind that if VOL_BUTTON_MODE bit is set to ‘1’ entering music playback mode via ANC_CSDA pin is not possible any more. 0: Volume mode via push-button disabled 1: Volume mode via push-button enabled 5 LINE_GAIN_+3dB_OTP 0 R/W Selects the line input operating gain range. If this bit is set the gain range of the line input amplifiers is shifted by +3dB. 0: Line Input gain range from -46.5dB...0dB 1: Line Input gain range from -43.5dB...+3dB 4 MIC_MODE_OTP 0 R/W 0: microphone input stage operating in single ended mode 1: normal operating in mono balanced www.austriamicrosystems.com Revision 0.90 40 - 61

AS3421 AS3422 Datasheet - Register Description Table 34. AUDIO_SET Register Name Base Default AUDIO_SET 2-wire serial 00h (OTP) OPT Audio Setting Register Offset: 33h Configures the audio settings. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 3 HP_MODE_OTP 0 R/W 0: headphone stage operating in single ended mode 1: normal operating in mono balanced 2:0 LIN_MON_ATTEN 000 R/W Volume settings for line input during monitor mode, adjustable in 7 steps of <6:0> 6dB and mute. 000: 0dB gain 001: -6dB gain .. 110: -36dB gain 111: MUTE www.austriamicrosystems.com Revision 0.90 41 - 61

AS3421 AS3422 Datasheet - Register Description Table 35. GP_OP Register Name Base Default GP_OP 2-wire serial 00h (OTP) OTP General Purpose Operational Amplifier Register Enables the opamp stages, defines opamp 2 mode and gain and sets the HP input multiplexer. This is Offset: 34h a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7:6 HP_MUX_OTP<1:0> 00 R/W Multiplexes the analog audio signal to HP amp 00: MIC: selects QMICL/R output 01:OP1: selects QOP1L/R outputs 10:OP2: selects QOP2L/R output 11: open: no signal mixed together with the line input signal 5:2 OP2_OTP<3:0> 0000 R/W Mode and volume settings for OP2, adjustable in 15 steps of 0.75dB 0000: OP2L in inverting mode 0001: 0 dB gain, OP2L in non inverting mode 0001: 0.75 dB gain, non inverting .., 1110: 9.75dB gain, non inverting 1111:.10.5 dB gain, non inverting 1 OP2_ON 0 R/W 0: OP2 is switched off 1: left OP2 is enabled 0 OPL_ON 0 R/W 0: OP1 is switched off 1: OP1 is enabled Table 36. OTP_SYS Register Name Base Default OTP_SYS 2-wire serial 40h (OTP) OTP System Settings Register Offset: 35h Defines several system settings for OTP operation. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 MAIN_LOCK 0 R/W 0: additional bits can be fused inside the OTP 1: OTP fusing gets locked, no more changes can be done 6 TEST_BIT_3 1 R for testing purpose only 5:4 MON_HP_MUX 00 R/W Multiplexes the analog audio signal to HP amp in monitor mode <1:0> 00: MIC: selects QMICL/R output 01: OP1: selects QOP1L/R outputs 10:OP2: selects QOP2L/R output 11: open: no signal mixed together with the line input signal 2 CP_MODE_OTP 0 R/W This bit controls the operating mode of the microphone supply charge pump. 0: Standard low noise operation 1: Increased output voltage 1 MICS_CP_OFF 0 R/W 0: MICS charge pump is enabled 1: MICS charge pump is switched off 0 I2C 0 R/W 0: I2C and stand alone mode start-up possible 1: chip starts-up in I2C mode only www.austriamicrosystems.com Revision 0.90 42 - 61

AS3421 AS3422 Datasheet - Register Description Table 37. CONFIG_1 Register Name Base Default CONFIG_1 2-wire serial 00h OTP Configuration Register Offset: 3Eh Controls the clock configuration. This is a special register, writing needs to be enabled by writing 9h to Reg 20h first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7:4 - 0000 n/a 3 EXTBURNCLK 0 n/a 0: ext. clock for OTP burning disabled 1: ext. clock for OTP burning enabled 2:0 - 000 n/a Table 38. CONFIG_2 Register Name Base Default CONFIG_2 2-wire serial 00h OTP Access Configuration Register Offset: 3Fh Controls the OTP access. This is a special register, writing needs to be enabled by writing 9h to Reg 20h first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7:6 - 000 n/a 5 TM34 0 n/a This Register defines the Register bank selection for Register TM_REG34-35 and TMREG30-33. Depending on TM34 you can select either between Register bank 14h-17h and 10h-13h enabled or 30h-33h and 34h-37h enabled. 0: test mode Registers 14h-17h and 10h-13h disabled test mode Registers 30h-33h and 34h-37h enabled 1: test mode Registers 14h-17h and 10h-13h enabled test mode Registers 30h-33h and 34h-37h disabled 4 BURNSW 0 n/a 0: BURN switch from LINL to VNEG is disabled 1: BURN switch from LINL to VNEG is enabled 3 TM_REG34-35 0 n/a 0: test mode for Register 34h-35h disabled test mode for Register 14h-17h disabled 1: test mode for Register 34h-35h enabled test mode for Register 14h-17h enabled 2 TM_REG30-33 0 n/a 0: test mode for Register 30h-33h disabled test mode for Register 10h-13h disabled 1: test mode for Register 30h-33h enabled test mode for Register 10h-13h enabled 1:0 OTP_MODE<1:0> 00 R/W Controls the OTP access 00: READ 01: LOAD 10: WRITE 11: BURN www.austriamicrosystems.com Revision 0.90 43 - 61

AS3421 AS3422 Datasheet - Application Information 11 Application Information 11.1 AS3422 Feedback Application Examples Figure 35. AS3422 Feedback Application Example with Bluetooth I2C Control www.austriamicrosystems.com Revision 0.90 44 - 61

AS3421 AS3422 Datasheet - Application Information Figure 36. AS3422 Feedback Application Example with Bluetooth ROM Version (No I2C Control) www.austriamicrosystems.com Revision 0.90 45 - 61

AS3421 AS3422 Datasheet - Application Information Figure 37. AS3422 Schematic - Stereo Bluetooth Feedback Application with I2C Control A B C D Speaker Right Speaker Left D 4 R715k R8 47k DGND C6 100n AGN T-a1 AGND 4 U2Vdcdc16INOUTINOUTC1525POKSETPOKSET1uF34ENGNDENGND AS1363-ADGND ANC POWERGNC31u Vanc should beVanca low noise supply C5GND10uU167852222AS3422 TPDNAPPNBCCGGNDV24HPVDD 23HPR 22HPVSSVneg21HPL342220VSS 19QOP2R 18IOP2R 17QOP1RRRRCRN1ICPIMLIOMQQI 34561111 RC Filter Networksto be developedindividually for eachFuheadset.7.4 41C MICSDR6 2k2 Right ANC Microphone GNDAGND C2 10u 9023 LG2EPNOVQ AS SLCCIIMM 1211 FFuu70.14 3211CC GN 3 C1Vneg100n GND RC Filter Networksto be developedindividually for eachheadset. Vneg 123333 LLG12EPPNOOVIQ1IOP1L 2QLINL 3QMICL 4AGND 5LINL_N 6LINL_P 7LINR_P 8LINR_NALDCSSCC 901 MICS MICS R5 2k2 C Microphone AGND 3 ed. Left AN nect ND! ND R4 10k ncon r AG AG Vanc R3 10k u o r left GND 220nF 220nF 220nF 220nF 2 EG o d to C7 C8 C9 C10 2 N e V ct o ne ct t on e c n e n b co T e O b N st st u u m m d d a a p p d d e e s s o o p p 1 x x 1 E E CAUTION: A B C D www.austriamicrosystems.com Revision 0.90 46 - 61

AS3421 AS3422 Datasheet - Application Information Figure 38. AS3422 Schematic - Stereo Bluetooth Feedback Application with ROM Version (No I2C Control) A B C D Speaker Right Speaker Left D 4 R715k R8 47k DGND C6 100n AGN T-a1 AGND 4 U2Vdcdc16INOUTINIIOUTC15C225POKSETPOKSET1uF10u34ENGNDENGND AS1363-ADGND ANC POWERGNC31u VancVanc should bea low noise supply C5GND10uU1678905222232AS3422 PLTNDGP2APENPCCBNGGNDOVVQ24HPVDD 23HPR 22HPVSSVneg21HPLAS342220VSS 19QOP2R 18IOP2R 17QOP1RRRRCRLSN1ICCCIPMLIIIOMMMQQI 123456111111 RC Filter Networksto be developedindividually for eachFFFuuheadset.u770..144 342111CCC MICSGNDR6 2k2 Right ANC Microphone GNDAGND 3 1 C1 ed.Vneg100n GND RC Filter Networksto be developedindividually for eachheadset. Vneg 123333 LLG21EPPNOOVIQ1IOP1L 2QLINL 3QMICL 4AGND 5LINL_N 6LINL_P 7LINR_P 8LINR_NALDCSSCC 901 MICS T2 Testpoint CSCL1 MICS1 R5T12k2Testpoint CSCL Left ANC Microphone AGND 3 T3Testpoint VNEG eft unconnect ND or AGND! 220nFAGND220nF 220nF 220nF VancVanc R3R4 10k10k 1 S1ANC ON/OFF 2 GND r l G 2 EG o d to C7 C8 C9 C10 2 N e V ct o ne ct t on e c n e n b co T e O b N st st u u m m d d a a p p d d e e s s o o p p 1 x x 1 E E CAUTION: A B C D www.austriamicrosystems.com Revision 0.90 47 - 61

AS3421 AS3422 Datasheet - Application Information 11.2 AS3421 Feed Forward Application Examples Figure 39. AS3421 Feed-Forward Application Example with Bluetooth I2C Control www.austriamicrosystems.com Revision 0.90 48 - 61

AS3421 AS3422 Datasheet - Application Information Figure 40. AS3421 Feed-Forward Application Example with Bluetooth ROM Version (No I2C Control) www.austriamicrosystems.com Revision 0.90 49 - 61

AS3421 AS3422 Datasheet - Application Information Figure 41. AS3421 Schematic - Stereo Feed-Forward Bluetooth Application with I2C Control A B C D 15k Speaker Right Speaker Left T-a1 DAGND 4 6 R75 R84 47k GNDGND Vanc should bea low noise supply C6 100n AGND GN 4 U2Vdcdc1INOUTINOUTC152POKSETPOKSET1uF3ENGNDENGND AS1363-ADGND ANC POWER 1u Vanc GND9U11C5AS342110uPPC 18VBATGND17HPVDD 16HPR 15HPL 14QOP1R 13IOP1R RCIMQ 21 RC Filter NetworksMICSto be developedindividually for eachheadset. MICS R6 2k2 Right ANC Microphone AGND 02 DNG 1 RCIM 11 Fu7.4 41C C3 12 NPC 342 SCIM 01 Fµ01 31C GND 22 GENV S LCIM 9 Fu7.4 21C A 32 L1POQ LCSC_EDOM 8 3 C2C1 10u100n GND RC Filter Networksto be developedindividually for eachheadset. Vneg 5422 LD1APPO_IXE1QMICL 2AGND 3LINL_N 4LINL_P 5LINR_P 6ALINR_NDSC_CNA 7 MICS R5 2k2 Microphone AGND 3 C N A ed. Vneg Left ct D! R4 10k ne N ND ncon r AG AG Vanc R3 10k u o eft ND 220nF 220nF 220nF 220nF r l G 2 EG o d to C7 C8 C9 C10 2 N e V ct o ne ct t on e c n e n b co T e O b N st st u u m m d d a a p p d d e e s s o o p p 1 x x 1 E E CAUTION: A B C D www.austriamicrosystems.com Revision 0.90 50 - 61

AS3421 AS3422 Datasheet - Application Information Figure 42. AS3421 Schematic - Stereo Feed-Forward Bluetooth Application ROM Version (No I2C Control) A B C D 15k Speaker Right Speaker Left T-a1 DAGND 4 6 R75 R84 47k GNDGND Vanc should bea low noise supply C6 100n AGND GN 4 U2Vdcdc1INOUTINIIOUTC152POKSETPOKSET1uF3ENGNDENGND AS1363-ADGND ANC POWER 1u Vanc GND9U11C5AS342110uPPC 18VBATGND17HPVDD 16HPR 15HPL 14QOP1R 13IOP1R RCIMQ 21 RC Filter NetworksMICSto be developedindividually for eachheadset. MICS R6 2k2 Right ANC Microphone AGND 02 DNG 1 RCIM 11 Fu7.4 41C C3 12 NPC 342 SCIM 01 Fµ01 31C GND 22 GENV S LCIM 9 Fu7.4 21C A 32 L1POQ LCSC_EDOM 8 3 C2C1 10u100n GND RC Filter Networksto be developedindividually for eachheadset. Vneg 4522 LD1APPO_IXE1QMICL 2AGND 3LINL_N 4LINL_P 5LINR_P 6ALINR_NDSC_CNA 7 CSCL MICS R5 2k2 NC Microphone AGND 3 1T3Testpoint VNEG Vneg eft unconnected. ND or AGND! 220nFAGND 220nF 220nF 220nF VancVanc R3R4T210k10kTestpoint 1 1 1 S1T1ANC ON/OFFTestpoint CSCL2 Left A GND r l G C7 C8 C9 C10 2 EG o d to 2 N e V ct o ne ct t on e c n e n b co T e O b N st st u u m m d d a a p p d d e e s s o o p p 1 x x 1 E E ACAUTION: B C D www.austriamicrosystems.com Revision 0.90 51 - 61

AS3421 AS3422 Datasheet - Application Information 11.3 Layout Recommendation Whereever you have audio circuits mixed with power management layout of the blocks is a critical issue. The AS3421/22 has an integrated charge pump which operates at a frequency of 1Mhz. If the layout of the PCB is not done properly the charge pump can directly influence the audio performance of the device. Therefore it is very important to make sure that the layout of the charge pump is done properly. The layout recommendation shown in Figure43 below shows an example placement of the components of the charge pump. The reference designators of the components used in the example refer to the schematic shown in Figure37. It can be seen clearly that the ground pins of all capacitors as well as the ground pin of AS3422 are placed closely. This compact placement of the components help to minimize high frequency cross over currents all over the PCB and therefore helps to improve the audio quality. A dedicated ground plane on the top (red) layer minimizes the resistance between the ground pads of the components. The ground plane (GND) is then connected to the analog ground (AGND) at a single point which is indicated with three vias in the example. Figure 43. AS3422 CP Layout Recommendation IA connection to analog round plane (AGND) 4. 2 e ur g o fi er t ef e r as e pl es nc e er ef nt r e n o p m o or c F If the physical alignment of the components allows it, it is also recommended to connect the charge pump ground plane on top layer directly to the battery ground terminal of your device. The analogue- (AGND) and charge pump ground plane (GND) are then connected together directly at the battery terminal. This concept is also know as star shaped ground concept shown in Figure44 below. Figure 44. AS3422 Star Shaped Ground Concept Charge pump ground (GND) and analog ground (AGND) are directly connected together at negative battery terminal. 4. 2 e ur g o fi er t ef e r as e pl es nc e er ef nt r e n o p m o or c F www.austriamicrosystems.com Revision 0.90 52 - 61

AS3421 AS3422 Datasheet - Application Information The layout examples showed in the examples before are based on AS3422. The AS3421 has of course a smaller package than AS3422, therefore the alignment of the charge pump components is different. A layout recommendation for AS3421 is shown in Figure45 below. Figure 45. AS3421 CP Layout Recommendation VIA connection to analog round plane (AGND) 6. 2 e ur g o fi er t ef e r as e pl es nc e er ef nt r e n o p m o or c F 11.4 Bill of Materials The following section shows the Bill of Materials which is necessary to operate the device. The necessary R-C filter networks which are necessary for gain- and phase compensation are excluded. These components very much depend on the acoustic design of each headset. Both devices basically need 17 external component for standard operation without the necessary filter components. The reference designator of the components shown in Table 39 refer to the schematics shown in Figure37 and Figure41. Table 39. AS3421/22 Bill of Materials POS Reference Value/Name Description Count 1 U1 AS3421 Stereo Bluetooth ANC headphone driver circuit 1 2 U2 AS1363-AD Low Drop Voltage Regulator 1 3 C3, C15 1µF Charge Pump flying capacitor; +/- 10% tolerance and LDO support 2 4 C1, C6 100nF PMU Blocking capacitors; +/- 10% tolerance 2 5 C7, C8, C9, C10 220nF Audio DC coupling capacitors; +/- 10% tolerance 4 6 C13 10µF Microphone supply filter capacitor; +/- 10% tolerance 1 7 C12, C14 4.7uF Microphone DC coupling capacitors; +/-5% tolerance 2 8 R5, R6 2k2 Microphone bias resistors; +/- 5%tolerance 2 9 C2, C5 10µF PMU Blocking capacitors; +/- 10% tolerance 2 10 R7 15k Voltage Regulator feedback resistor 1 11 R8 47k Voltage Regulator feedback resistor 1 12 R3, R4 10k Two wire interface pull up resistors; +/- 10% tolerance 2 Sum 21 www.austriamicrosystems.com Revision 0.90 53 - 61

AS3421 AS3422 Datasheet - Application Information 11.5 PCB Footprint Recommendation Figure 46. AS3421 PCB Footprint Recommendation d Pin 1 e e n ht g mi s RECOMMENDED LAND PATTERN nt OW COMPONENT DENSITY ri p TOP VIEW ot o e f h T d. ar Silk Screen d n a st B 1 5 3 7 - C P Pin 1 o I g t n rdin! oo accucti RMEECDOIUMMM CEONMDPEOD NLEANNTD DPEATNTSEITRYN d d eo TOP VIEW signn pr re debility i aa ations est reli Silk Screen db ene mev mhi oc ca eo e rr t Pin 1 he at tord d ths in ne mig RECOMMENDED LAND PATTERN n e a HIGH COMPONENT DENSITY sh ac TOP VIEW ee CAUTION: Pl littl Silk Screen www.austriamicrosystems.com Revision 0.90 54 - 61

AS3421 AS3422 Datasheet - Application Information Figure 47. AS3422 PCB Footprint Recommendation Pin 1 d e e n ht g mi s RECOMMENDED LAND PATTERN nt OW COMPONENT DENSITY ri p TOP VIEW ot o e f h T d. Silk Screen r a d n a st B 1 5 3 7 C- Pin 1 P o I g t n rdin! oo accucti RMEECDOIUMMM CEONMDPEOD NLEANNTD DPEATNTSEITRYN d d eo TOP VIEW signn pr re debility i aa ations est reli Silk Screen db ene mev mhi oc ca eo e rr t Pin 1 he at tord d ths in ne mig RECOMMENDED LAND PATTERN n e a HIGH COMPONENT DENSITY sh ac TOP VIEW ee CAUTION: Pl littl Silk Screen www.austriamicrosystems.com Revision 0.90 55 - 61

AS3421 AS3422 Datasheet - Package Drawings and Marking 12 Package Drawings and Marking Figure 48. QFN Marking Table 40. Package Code YYWWIZZ YY WW X ZZ last two digits of the year manufacturing week plant identifier free choice / traceability code www.austriamicrosystems.com Revision 0.90 56 - 61

AS3421 AS3422 Datasheet - Package Drawings and Marking Figure 49. AS3421, 24-pin QFN 0.5mm Pitch www.austriamicrosystems.com Revision 0.90 57 - 61

AS3421 AS3422 Datasheet - Package Drawings and Marking Figure 50. AS2322 32-pin QFN 0.5mm Pitch www.austriamicrosystems.com Revision 0.90 58 - 61

AS3421 AS3422 Datasheet - Revision History Revision History Revision Date Owner Description 0.2 25.1.2012 hgt initial release 0.3 14.3.2012 hgt updated low power playback mode and pin descriptions 0.4 11.6.2012 hgt updated microphone parameters Note: Typos may not be explicitly mentioned under revision history. www.austriamicrosystems.com Revision 0.90 59 - 61

AS3421 AS3422 Datasheet - Ordering Information 13 Ordering Information The devices are available as the standard products shown in Table 41. Table 41. Ordering Information Ordering Code Description Delivery Form Package Tape & Reel QFN 24 [4.0x4.0x0.85mm] 0.5mm AS3421-EQFP Low Power Ambient Noise-Cancelling Speaker Driver dry pack pitch Tape & Reel QFN 24 [4.0x4.0x0.85mm] 0.5mm AS3421-EQFP-500 Low Power Ambient Noise-Cancelling Speaker Driver dry pack pitch Tape & Reel QFN 32 [5.0x5.0x0.85mm] 0.5mm AS3422-EQFP Low Power Ambient Noise-Cancelling Speaker Driver dry pack pitch Tape & Reel QFN 32 [5.0x5.0x0.85mm] 0.5mm AS3422-EQFP-500 Low Power Ambient Noise-Cancelling Speaker Driver dry pack pitch Note: All products are RoHS compliant and austriamicrosystems green. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect For further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor www.austriamicrosystems.com Revision 0.90 60 - 61

AS3421 AS3422 Datasheet - Copyrights Copyrights Copyright © 1997-2012, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystemsAG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystemsAG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com Revision 0.90 61 - 61