AMIS-30542 Micro-Stepping Motor Driver Introduction The AMIS−30542 is a micro−stepping stepper motor driver for bipolar stepper motors. The chip is connected through I/O pins and a http://onsemi.com SPI interface with an external microcontroller. It has an on−chip voltage regulator, reset−output and watchdog reset, able to supply peripheral devices. AMIS−30542 contains a current−translation table and takes the next micro−step depending on the clock signal on the “NXT” input pin and the status of the “DIR” (=direction) register or input pin. The chip provides a so−called “speed and load angle” output. This allows the creation of stall detection algorithms and control loops based on load−angle to adjust torque and speed. It is NQFP−32, 7x7 using a proprietary PWM algorithm for reliable current control. CASE 560AA The AMIS−30542 is implemented in I2T100 technology, enabling both high−voltage analog circuitry and digital functionality on the same chip. The chip is fully compatible with the automotive voltage MARKING DIAGRAM requirements. The AMIS−30542 is ideally suited for general−purpose stepper motor applications in the automotive, industrial, medical, and marine environment. With the on−chip voltage regulator it further reduces the BOM for mechatronic stepper applications. Key Features • Dual H−Bridge for 2−Phase Stepper Motors • Programmable Peak−Current Up to 2.2 A Continuous† (5 A Short Time) Using a 5−bit Current DAC • On−Chip Current Translator • SPI Interface • Speed and Load Angle Output C542−001 = Specific Device Code • XXXX = Date Code Seven Step Modes from Full Step Up to 32 Micro−Steps Y = Assembly Location • Fully Integrated Current−Sense ZZ = Traceability Code • PWM Current Control with Automatic Selection of Fast and Slow Decay • ORDERING INFORMATION Low EMC PWM with Selectable Voltage Slopes • See detailed ordering and shipping information in the package Active Fly−Back Diodes dimensions section on page 27 of this data sheet. • Full Output Protection and Diagnosis • Thermal Warning and Shutdown • Compatible with 5 V and 3.3 V Microcontrollers • Integrated 5 V Regulator to Supply External Microcontroller • Integrated Reset Function to Reset External Microcontroller • Integrated Watchdog Function • These Devices are Pb−Free and are RoHS Compliant* †Output current level may be limited by ambient temperature and heat sinking. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: August, 2012 − Rev. 1 AMIS−30542/D

AMIS−30542 BLOCK DIAGRAM VDD CPN CPP VCP VBB CLK Timebase Vreg Chargepump POR EMC MOTXP CS P T W OTP DI SPI R M A I−sense MOTXN DO N S NXT L DIR RLeoggisict e&rs ALnogalde OAT EMC P MOTYP SLA R W M POR/WD STeenm.spe I−sense MOTYN CLR AMIS−30542 ERR Band− gap TST0 GND Figure 1. Block Diagram AMIS−30542 Table 1. PIN LIST AND DESCRIPTION Equivalent Name Pin Description Type Schematic GND 1 Ground Supply DI 2 SPI Data In Digital Input Type 2 CLK 3 SPI Clock Input Digital Input Type 2 NXT 4 Next micro−step input Digital Input Type 2 DIR 5 Direction input Digital Input Type 2 ERR 6 Error output (open drain) Digital Output Type 4 SLA 7 Speed load angle output Analog Output Type 5 / 8 No function (to be left open in normal operation) CPN 9 Negative connection of charge pump capacitor High Voltage CPP 10 Positive connection of charge pump capacitor High Voltage VCP 11 Charge pump filter−capacitor High Voltage CLR 12 “Clear” = chip reset input Digital Input Type 1 CS 13 SPI chip select input Digital Input Type 2 VBB 14 High voltage supply Input Supply Type 3 MOTYP 15, 16 Negative end of phase Y coil output Driver Output GND 17, 18 Ground, heat sink Supply MOTYN 19, 20 Positive end of phase Y coil output Driver Output MOTXN 21, 22 Positive end of phase X coil output Driver Output GND 23, 24 Ground, heat sink Supply MOTXP 25, 26 Negative end of phase X coil output Driver Output VBB 27 High voltage supply input Supply Type 3 / 30 No function (to be left open in normal operation) POR/WD 28 Power−on−reset and watchdog reset output (open drain) Digital Output Type 2 TST0 29 Test pin input (to be tied to ground in normal operation) Digital Input DO 31 SPI data output (open drain) Digital Output Type 4 VDD 32 Logic supply output (needs external decoupling capacitor) Supply Type 6 http://onsemi.com 2

AMIS−30542 P O M M T R O O VD D ST /W VB TX TX D O O D B P P 32 31 30 29 28 27 26 25 GND 1 24 GND DI 2 23 GND CLK 3 22 MOTXN NXT 4 AMIS−30542 21 MOTXN DIR 5 20 MOTYN ERR 6 19 MOTYN SLA 7 18 GND 8 17 GND 9 10 11 12 13 14 15 16 C C V C C V M M P P C L S B O O N P P R B T T Y Y P P Figure 2. Pin Out AMIS−30542 Table 2. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Unit VBB Analog DC supply voltage (Note 1) −0.3 +40 V TST Storage temperature −55 +160 °C TJ Junction Temperature under bias (Note 2) −50 +175 °C VESD Electrostatic discharges on component level, All pins (Note 3) −2 +2 kV VESD Electrostatic discharges on component level, HiV pins (Note 4) −8 +8 kV Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. For limited time < 0.5 s. 2. Circuit functionality not guaranteed. 3. Human body model (100 pF via 1.5 k(cid:2), according to JEDEC EIA−JESD22−A114−B). 4. HiV = High Voltage Pins MOTxx, VBB, GND; (100 pF via 1.5 k(cid:2), according to JEDEC EIA−JESD22−A114−B). Table 3. THERMAL RESISTANCE Thermal Resistance Junction–to–Ambient Package Junction–to–Exposed Pad 1S0P board 2S2P board Unit NQFP−32 0.95 60 30 K/W http://onsemi.com 3

AMIS−30542 EQUIVALENT SCHEMATICS Following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified representations of the circuits used. 4K IN OUT R in TYPE 1:CLR input TYPE 4:DO and ERRB open drain outputs 4K IN Rout SLA TYPE 2:CLK,DI,CSB,NXT,DIR inputs TYPE 5:SLA analog output VDD VBB VDD VBB . TYPE 3:VDD and VBB power supply inputs Figure 3. In− and Output Equivalent Diagrams PACKAGE THERMAL CHARACTERISTICS The AMIS−30542 is available in a NQFP32 package. For The Rthja for 2S2P is simulated conform JEDEC cooling optimizations, the NQFP has an exposed thermal JESD−51 as follows: pad which has to be soldered to the PCB ground plane. The • A 4−layer printed circuit board with inner power planes ground plane needs thermal vias to conduct the heat to the and outer (top and bottom) signal layers is used bottom layer. Figure 3 gives an example for good power • Board thickness is 1.46 mm (FR4 PCB material) distribution solutions. • The 2 signal layers: 70 (cid:3)m thick copper with an area of For precise thermal cooling calculations the major 5500 mm2 copper and 20% conductivity thermal resistances of the device are given. The thermal • The 2 power internal planes: 36 (cid:3)m thick copper with media to which the power of the devices has to be given are: • an area of 5500 mm2 copper and 90% conductivity Static environmental air (via the case) • The Rthja for 1S0P is simulated conform to JEDEC PCB board copper area (via the exposed pad) JESD−51 as follows: The thermal resistances are presented in Table 5: DC • A 1−layer printed circuit board with only 1 layer Parameters. • Board thickness is 1.46 mm (FR4 PCB material) The major thermal resistances of the device are the Rth from the junction to the ambient (Rthja) and the overall Rth • The layer has a thickness of 70 (cid:3)m copper with an area from the junction to exposed pad (Rthjp). In Table 5 below of 5500 mm2 copper and 20% conductivity one can find the values for the Rthja and Rthjp, simulated according to JESD−51: http://onsemi.com 4

AMIS−30542 ÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉ ÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉ ÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉ ÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉ ÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉNÏÉQFPÏÉ−32ÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉ ÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉ ÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉ ÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉ ÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉÏÉ Figure 4. Example of NQFP−32 PCB Ground Plane Layout in Top View (Preferred Layout at Top and Bottom) ELECTRICAL SPECIFICATION Recommend Operation Conditions ranges is not guaranteed. Operating outside the Operating ranges define the limits for functional recommended operating ranges for extended periods of time operation and parametric characteristics of the device. Note may affect device reliability. that the functionality of the chip outside these operating Table 4. OPERATING RANGES Symbol Parameter Min Max Unit VBB Analog DC Supply +6 +30 V TJ Junction Temperature (Note 5) −40 +172 °C 5. No more than 100 cumulative hours in life time above Ttw. http://onsemi.com 5

AMIS−30542 Table 5. DC PARAMETERS (The DC parameters are given for VBB and temperature in their operating ranges unless otherwise specified) Convention: currents flowing in the circuit are defined as positive. Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit SUPPLY AND VOLTAGE REGULATORS VBB Nominal operating supply range 6 30 V IBB VBB Total internal current consumption Unloaded outputs 8 mA (Note 6) VDD Regulated Output Voltage 4.75 5 5.25 V IINT Internal load current (Note 6) Unloaded outputs 8 mA ILOAD Max Output Current (external and 6 V (cid:2) VBB < 8 V 20 VDD internal loads) 8 V (cid:2) VBB (cid:2) 30 V 50 IDDLIM Current limitation Pin shorted to ground 150 mA ILOAD_PD Output current in Power Down 1 mA POWER−ON−RESET (POR) VDDH Internal POR comparator threshold VDD rising 4.0 4.25 4.4 V VDD VDDL Internal POR comparator threshold VDD falling 3.68 V MOTORDRIVER IMDmax,Peak Max current through motor coil in TJ = −40°C 5525 mA normal operation MOTXP IMdmax,RMS MOTXN Max RMS current through coil in TJ = −40°C 3906 mA normal operation MOTYP IMdabs MOTYN Absolute error on coil current −10 10 % IMdrel Error on current ratio ICOILx / ICOILy −7 7 % ISET_TC1 Temperature coefficient of coil −40°C (cid:2) TJ (cid:2) 160°C −240 ppm/K current set−level, CUR[4:0] = 0...27 ISET_TC2 Temperature coefficient of coil −40°C (cid:2) TJ (cid:2) 160°C −490 ppm/K current set−level, CUR[4:0] = 28...31 RHS On−resistance high−side driver, VBB = 12 V, TJ = 27°C 0.10 0.16 (cid:2) CUR[4:0] = 0...31 (Note 7) VBB = 12 V, TJ = 160°C 0.16 0.31 (cid:2) RLS3 On−resistance low−side driver, VBB = 12 V, TJ = 27°C 0.11 0.16 (cid:2) CUR[4:0] = 23...31 (Note 7) VBB = 12 V, TJ = 160°C 0.18 0.31 (cid:2) RLS2 On−resistance low−side driver, VBB = 12 V, TJ = 27°C 0.22 0.31 (cid:2) CUR[4:0] = 16...22 (Note 7) VBB = 12 V, TJ = 160°C 0.35 0.63 (cid:2) RLS1 On−resistance low−side driver, VBB = 12 V, TJ = 27°C 0.47 0.63 (cid:2) CUR[4:0] = 9...15 (Note 7) VBB = 12 V, TJ = 160°C 0.74 1.25 (cid:2) RLS0 On−resistance low−side driver, VBB = 12 V, TJ = 27°C 0.92 1.25 (cid:2) CUR[4:0] = 0...8 (Note 7) VBB = 12 V, TJ = 160°C 1.51 2.50 (cid:2) IMpd Pull down current HiZ mode 10 mA DIGITAL INPUTS Ileak Input Leakage (Note 8) TJ = 160°C 1 (cid:3)A DI, CLK VIL NXT, DIR Logic Low Threshold 0 0.65 V CLR, CS VIH Logic High Threshold 2.20 VDD V Rpd_CLR CLR Internal Pulldown Resistor 120 300 k(cid:2) Rpd_TST TST0 Internal Pulldown Resistor 3 9 k(cid:2) 6. Current with oscillator running, all analogue cells active, SPI communication and NXT pulses applied. No floating inputs. Parameter guaranteed by design. 7. Characterization Data Only 8. Not valid for pins with internal Pulldown resistor http://onsemi.com 6

AMIS−30542 Table 5. DC PARAMETERS (The DC parameters are given for VBB and temperature in their operating ranges unless otherwise specified) Convention: currents flowing in the circuit are defined as positive. Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit DIGITAL OUTPUTS VOL DO, ERR, Logic Low level open drain IOL = 5 mA 0.5 V POR/WD THERMAL WARNING AND SHUTDOWN Ttw Thermal Warning 138 145 152 °C Ttsd Thermal shutdown (Notes 9 Ttw + 20 °C and 10) CHARGE PUMP Vcp Output voltage 6 V< VBB < 15 V 2 * VBB – V 1.5 VCP 15 V < VBB < 30 V VBB+8 VBB+11.5 VBB+15 V Cbuffer External buffer capacitor 180 220 470 nF Cpump CPP CPN External pump capacitor 180 220 470 nF PACKAGE THERMAL RESISTANCE VALUE Rthja Thermal Resistance Simulated Conform JEDEC 30 K/W Junction−to−Ambient JESD−51, (2S2P) NQFP Rthjp Thermal Resistance 0.95 K/W Junction−to−Exposed Pad SPEED AND LOAD ANGLE OUTPUT Vout Output Voltage Range 0.2 VDD − V 0.2 Voff Output Offset SLA pin SLAG = 0 −50 50 mV SLAG = 1 −30 30 mV SLA Gsla Gain of SLA Pin = VBEMF / VCOIL SLAG = 0 0.5 SLAG = 1 0.25 Rout Output Resistance SLA pin 0.23 1 k(cid:2) Cload Load Capacitance SLA pin 50 pF 9. No more than 100 cumulated hours in life time above Ttw. 10.Thermal shutdown is derived from thermal warning Characterization Data Only. http://onsemi.com 7

AMIS−30542 Table 6. AC PARAMETERS (The AC parameters are given for VBB and temperature in their operating ranges) Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit INTERNAL OSCILLATOR fosc Frequency of internal oscillator 3.6 4 4.4 MHz MOTOR DRIVER fPWM PWM frequency 20.8 22.8 24.8 kHz Frequency depends only on MOTxx Double PWM frequency 41.6 45.6 49.6 kHz internal oscillator fd PWM jitter Depth (Note 11) 10 % fPWM tbrise EMC[1:0] = 00 350 V/(cid:3)s EMC[1:0] = 01 250 V/(cid:3)s Turn−on voltage slope, 10% to MOTxx 90% EMC[1:0] = 10 200 V/(cid:3)s EMC[1:0] = 11 100 V/(cid:3)s tbfall EMC[1:0] = 00 350 V/(cid:3)s EMC[1:0] = 01 250 V/(cid:3)s Turn−off voltage slope, 90% to MOTxx 10% EMC[1:0] = 10 200 V/(cid:3)s EMC[1:0] = 11 100 V/(cid:3)s DIGITAL OUTPUTS tH2L DO Output fall−time from VinH to VinL Capacitive load 400 pF and 50 ns ERR pullup resistor of 1.5 k(cid:2) CHARGE PUMP fCP CPN CPP Charge pump frequency 250 kHz tCPU MOTxx Startup time of charge pump Spec external components 5 ms (Note 12) CLR FUNCTION tCLR CLR Hard reset duration time 100 (cid:3)s POWER−UP tPU Powerup time VBB = 12 V, ILOAD = 50 mA, 110 (cid:3)s CLOAD = 220 nF POR/WD tPOR Reset duration See FIgure 16 100 ms tRF Reset filter time See FIgure 16 1 (cid:3)s WATCHDOG tWDTO Watchdog time out interval 32 512 ms tWDPR POR/WD Prohibited watchdog 2 ms acknowledge delay NXT FUNCTION tNXT_HI NXT Minimum, High Pulse Width See Figure 5 2 (cid:3)s tNXT_HI NXT Minimum, Low Pulse Width See Figure 5 2 (cid:3)s tDIR_SET NXT NXT Hold Time, Following See Figure 5 0.5 (cid:3)s Change of DIR tDIR_HOLD NXT Hold Time, Before Change See Figure 5 0.5 (cid:3)s of DIR 11.Characterization Data Only 12.Guaranteed by design http://onsemi.com 8

AMIS−30542 t t NXT_HI NXT_LO NXT 0.5VCC t t DIR_SET DIR_HOLD ÌÌÌ ÌÌÌÌÌÌÌÌÌ DÌIRÌÌ VALID ÌÌÌÌÌÌÌÌÌ ÌÌÌ ÌÌÌÌÌÌÌÌÌ Figure 5. NXT−Input Timing Diagram Table 7. SPI TIMING PARAMETERS Symbol Parameter Min Typ Max Unit tCLK SPI Clock Period 1 (cid:3)s tCLK_HIGH SPI Clock High Time 100 ns tCLK_LOW SPI Clock Low Time 100 ns tSET_DI DI Set Up Time, Valid Data Before Rising Edge of CLK 50 ns tHOLD_DI DI Hold Time, Hold Data After Rising Edge of CLK 50 ns tCSB_HIGH CS High Time 2.5 (cid:3)s tSET_CSB CS Set Up Time, CS Low Before Rising Edge of CLK 100 ns tSET_CLK CLK Set Up Time, CLK Low Before Rising Edge of CS 100 ns CS 0.2VCC 0.2VCC t t t SET_CSB CLK SET_CLK 0.8VCC CLK 0,2VCC 0.2VCC tCLK_HI tCLK_LO tSET_DI tHOLD_DI ÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌ DIÌÌÌ 0.8VCVCALID ÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌ Figure 6. SPI Timing http://onsemi.com 9

AMIS−30542 TYPICAL APPLICATION SCHEMATIC D 100nF 100 nF 100nF 1 V C4 C2 C3 C1 BAT C5 C6 100(cid:3)F R R R 2 3 4 100nF VDD VBB VBB 220 nF 32 14 27 VCP 11 POR/WD 28 9 CPN DIR C7 5 AMIS−30542 NXT 4 10 220 nF CPP DO 31 MOTXP 25,26 DI 2 (cid:3) C CLK MOTXN 3 21,22 CS 13 M CLR 12 15,16 MOTYP ERR 6 MOTYN 19,20 SLA 7 R1 C8 1 17 18 23 24 29 TSTO GND Figure 7. Typical Application Schematic AMIS−30542 Table 8. EXTERNAL COMPONENTS LIST AND DESCRIPTION Component Function Typ Value Tolerance Unit C1 VBB Buffer Capacitor (Note 13) 100 −20 +80% (cid:3)F C2, C3 VBB Decoupling Block Capacitor 100 −20 +80% nF C4 VDD Buffer Capacitor 100 (cid:3)20% nF C5 VDD Buffer Capacitor 100 (cid:3)20% nF C6 Charge Pump Buffer Capacitor 220 (cid:3)20% nF C7 Charge Pump Pumping Capacitor 220 (cid:3)20% nF C8 Low Pass Filter SLA 1 (cid:3)20% nF R1 Low Pass Filter SLA 5.6 (cid:3)1% k(cid:2) R2, R3, R4 Pullup Resistor Open Drain Output 4.7 (cid:3)1% k(cid:2) D1 Optional Reverse Protection Diode MURD530 13.ESR < 1 (cid:2). http://onsemi.com 10

AMIS−30542 FUNCTIONAL DESCRIPTION H−Bridge Drivers transistors will be adapted such that excellent current−sense A full H−bridge is integrated for each of the two stator accuracy is maintained. The R of the high−side DS(on) windings. Each H−bridge consists of two low−side and two transistors remain unchanged; see Table 5 DC Parameters high−side N−type MOSFET switches. Writing logic ‘0’ in for more details. bit <MOTEN> disables all drivers (high−impedance). PWM Current Control Writing logic ‘1’ in this bit enables both bridges and current A PWM comparator compares continuously the actual can flow in the motor stator windings. winding current with the requested current and feeds back In order to avoid large currents through the H−bridge the information to a digital regulation loop. This loop then switches, it is guaranteed that the top− and bottom−switches generates a PWM signal, which turns on/off the H−bridge of the same half−bridge are never conductive switches. The switching points of the PWM duty−cycle are simultaneously (interlock delay). synchronized to the on−chip PWM clock. The frequency of A two−stage protection against shorts on motor lines is the PWM controller can be doubled and an artificial jitter implemented. In a first stage, the current in the driver is can be added (see Table 14 SPI Control Parameter Overview limited. Secondly, when excessive voltage is sensed across PWMJ). The PWM frequency will not vary with changes in the transistor, the transistor is switched off. the supply voltage. Also variations in motor−speed or In order to reduce the radiated/conducted emission, load−conditions of the motor have no effect. There are no voltage slope control is implemented in the output switches. external components required to adjust the PWM frequency. The output slope is defined by the gate−drain capacitance of output transistor and the (limited) current that drives the Automatic Forward and Slow−Fast Decay gate. There are two trimming bits for slope control (see The PWM generation is in steady−state using a Table 14 SPI Control Parameter Overview EMC[1:0]). combination of forward and slow−decay. The absence of The power transistors are equipped with so−called “active fast−decay in this mode, guarantees the lowest possible diodes”: when a current is forced trough the transistor switch current−ripple “by design”. For transients to lower current in the reverse direction, i.e. from source to drain, then the levels, fast−decay is automatically activated to allow transistor is switched on. This ensures that most of the high−speed response. The selection of fast or slow decay is current flows through the channel of the transistor instead of completely transparent for the user and no additional through the inherent parasitic drain−bulk diode of the parameters are required for operation. transistor. Depending on the desired current range and the micro−step position at hand, the R of the low−side DS(on) Icoil Set value Actual value t 0 T PWM Forward&Slow Decay Forward&Slow Decay FastDecay&Forward Figure 8. Forward and Slow/Fast Decay PWM http://onsemi.com 11

AMIS−30542 Automatic Duty Cycle Adaptation process is completely automatic and requires no additional In case the supply voltage is lower than 2*Bemf, then the parameters for operation. The over−all current−ripple is duty cycle of the PWM is adapted automatically to > 50% to divided by two if PWM frequency is doubled (see Table 14 maintain the requested average current in the coils. This SPI Control Parameter Overview PWMF) Icoil Duty Cycle < 50% Duty Cycle> 50% Duty Cycle<50% Actual value Set value t Figure 9. Automatic Duty Cycle Adaption T PWM Step Translator and Step Mode corresponding stepping mode. When remaining in the same The step translator provides the control of the motor by step mode, subsequent translator positions are all in the same means of SPI register Stepmode: SM[2:0], SPI register column and increased or decreased with 1. Table 10 lists the DIRCNTRL and input pins DIR and NXT. It is translating output current vs. the translator position. consecutive steps in corresponding currents in both motor As shown in Figure 10 the output current−pairs can be coils for a given step mode. projected approximately on a circle in the (I , I ) plane. x y One out of seven possible stepping modes can be selected There are, however, two exceptions: uncompensated half through SPI−bits SM[2:0] (see Table 14 SPI Control step and full step. In these step modes the currents are not Parameter Overview ) After power−on or hard reset, the regulated to a fraction of I but are in all intermediate steps max coil−current translator is set to the default 1/32 regulated at 100%. In the (I , I ) plane the current−pairs are x y micro−stepping at position ‘0’. Upon changing the step projected on a square. Table 9 lists the output current vs. the mode, the translator jumps to position 0* of the translator position for these cases. Table 9. SQUARE TRANSLATOR TABLE FOR FULL STEP AND UNCOMPENSATED HALF STEP Stepmode ( SM[2:0] ) % of Imax 101 110 MSP[6:0] Uncompensated Half Step Full Step Coil x Coil y 000 0000 0* − 0 100 001 0000 1 1 100 100 010 0000 2 − 100 0 011 0000 3 2 100 −100 100 0000 4 − 0 −100 101 0000 5 3 −100 −100 110 0000 6 − −100 0 111 0000 7 0 −100 100 http://onsemi.com 12

AMIS−30542 Table 10. CIRCULAR TRANSLATOR TABLE Stepmode (SM[2:0]) % of Imax 000 001 010 011 100 MSP[6:0] 1/32 1/16 1/8 1/4 1/2 Coil x Coil y 000 0000 ‘0’ 0* 0* 0* 0* 0 100 000 0001 1 − − − − 3.5 98.8 000 0010 2 1 − − − 8.1 97.7 000 0011 3 − − − − 12.7 96.5 000 0100 4 2 1 − − 17.4 95.3 000 0101 5 − − − − 22.1 94.1 000 0110 6 3 − − − 26.7 93 000 0111 7 − − − − 31.4 91.8 000 1000 8 4 2 1 − 34.9 89.5 000 1001 9 − − − − 38.3 87.2 000 1010 10 5 − − − 43 84.9 000 1011 11 − − − − 46.5 82.6 000 1100 12 6 3 − − 50 79 000 1101 13 − − − − 54.6 75.5 000 1110 14 7 − − − 58.1 72.1 000 1111 15 − − − − 61.6 68.6 001 0000 16 8 4 2 1 65.1 65.1 001 0001 17 − − − − 68.6 61.6 001 0010 18 9 − − − 72.1 58.1 001 0011 19 − − − − 75.5 54.6 001 0100 20 10 5 − − 79 50 001 0101 21 − − − − 82.6 46.5 001 0110 22 11 − − − 84.9 43 001 0111 23 − − − − 87.2 38.3 001 1000 24 12 6 3 − 89.5 34.9 001 1001 25 − − − − 91.8 31.4 001 1010 26 13 − − − 93 26.7 001 1011 27 − − − − 94.1 22.1 001 1100 28 14 7 − − 95.3 17.4 001 1101 29 − − − − 96.5 12.7 001 1110 30 15 − − − 97.7 8.1 001 1111 31 − − − − 98.8 3.5 010 0000 32 16 8 4 2 100 0 010 0001 33 − − − − 98.8 −3.5 010 0010 34 17 − − − 97.7 −8.1 010 0011 35 − − − − 96.5 −12.7 010 0100 36 18 9 − − 95.3 −17.4 010 0101 37 − − − − 94.1 −22.1 010 0110 38 19 − − − 93 −26.7 010 0111 39 − − − − 91.8 −31.4 010 1000 40 20 10 5 − 89.5 −34.9 010 1001 41 − − − − 87.2 −38.3 010 1010 42 21 − − − 84.9 −43 010 1011 43 − − − − 82.6 −46.5 010 1100 44 22 11 − − 79 −50 010 1101 45 − − − − 75.5 −54.6 010 1110 46 23 − − − 72.1 −58.1 010 1111 47 − − − − 68.6 −61.6 011 0000 48 24 12 6 3 65.1 −65.1 011 0001 49 − − − − 61.6 −68.6 011 0010 50 25 − − − 58.1 −72.1 011 0011 51 − − − − 54.6 −75.5 011 0100 52 26 13 − − 50 −79 011 0101 53 − − − − 46.5 −82.6 011 0110 54 27 − − − 43 −84.9 011 0111 55 − − − − 38.3 −87.2 011 1000 56 28 14 7 − 34.9 −89.5 011 1001 57 − − − − 31.4 −91.8 011 1010 58 29 − − − 26.7 −93 011 1011 59 − − − − 22.1 −94.1 011 1100 60 30 15 − − 17.4 −95.3 011 1101 61 − − − − 12.7 −96.5 011 1110 62 31 − − − 8.1 −97.7 011 1111 63 − − − − 3.5 −98.8 http://onsemi.com 13

AMIS−30542 Table 11. CIRCULAR TRANSLATOR TABLE (CONTINUED) Stepmode ( SM[2:0] ) % of Imax 000 001 010 011 100 MSP[6:0] 1/32 1/16 1/8 1/4 1/2 Coil x Coil y 100 0000 64 32 16 8 4 0 −100 100 0001 65 − − − − −3.5 −98.8 100 0010 66 33 − − − −8.1 −97.7 100 0011 67 − − − − −12.7 −96.5 100 0100 68 34 17 − − −17.4 −95.3 100 0101 69 − − − − −22.1 −94.1 100 0110 70 35 − − − −26.7 −93 100 0111 71 − − − − −31.4 −91.8 100 1000 72 36 18 9 − −34.9 −89.5 100 1001 73 − − − − −38.3 −87.2 100 1010 74 37 − − − −43 −84.9 100 1011 75 − − − − −46.5 −82.6 100 1100 76 38 19 − − −50 −79 100 1101 77 − − − − −54.6 −75.5 100 1110 78 39 − − − −58.1 −72.1 100 1111 79 − − − − −61.6 −68.6 101 0000 80 40 20 10 5 −65.1 −65.1 101 0001 81 − − − − −68.6 −61.6 101 0010 82 41 − − − −72.1 −58.1 101 0011 83 − − − − −75.5 −54.6 101 0100 84 42 21 − − −79 −50 101 0101 85 − − − − −82.6 −46.5 101 0110 86 43 − − − −84.9 −43 101 0111 87 − − − − −87.2 −38.3 101 1000 88 44 22 11 − −89.5 −34.9 101 1001 89 − − − − −91.8 −31.4 101 1010 90 45 − − − −93 −26.7 101 1011 91 − − − − −94.1 −22.1 101 1100 92 46 23 − − −95.3 −17.4 101 1101 93 − − − − −96.5 −12.7 101 1110 94 47 − − − −97.7 −8.1 101 1111 95 − − − − −98.8 −3.5 110 0000 96 48 24 12 6 −100 0 110 0001 97 − − − − −98.8 3.5 110 0010 98 49 − − − −97.7 8.1 110 0011 99 − − − − −96.5 12.7 110 0100 100 50 25 − − −95.3 17.4 110 0101 101 − − − − −94.1 22.1 110 0110 102 51 − − − −93 26.7 110 0111 103 − − − − −91.8 31.4 110 1000 104 52 26 13 − −89.5 34.9 110 1001 105 − − − − −87.2 38.3 110 1010 106 53 − − − −84.9 43 110 1011 107 − − − − −82.6 46.5 110 1100 108 54 27 − − −79 50 110 1101 109 − − − − −75.5 54.6 110 1110 110 55 − − − −72.1 58.1 110 1111 111 − − − − −68.6 61.6 111 0000 112 56 28 14 7 −65.1 65.1 111 0001 113 − − − − −61.6 68.6 111 0010 114 57 − − − −58.1 72.1 111 0011 115 − − − − −54.6 75.5 111 0100 116 58 29 − − −50 79 111 0101 117 − − − − −46.5 82.6 111 0110 118 59 − − − −43 84.9 111 0111 119 − − − − −38.3 87.2 111 1000 120 60 30 15 − −34.9 89.5 111 1001 121 − − − − −31.4 91.8 111 1010 122 61 − − − −26.7 93 111 1011 123 − − − − −22.1 94.1 111 1100 124 62 31 − − −17.4 95.3 111 1101 125 − − − − −12.7 96.5 111 1110 126 63 − − − −8.1 97.7 111 1111 127 − − − − −3.5 98.8 http://onsemi.com 14

AMIS−30542 I I I y y y Start=0 Step1 Start=0 Step1 Start=0 Step1 Step2 Step3 I Step2 I I x x x Step3 Step3 Step2 1/4th micro step Uncompensated Half Step Full Step SM[2:0] =011 SM[2:0] =101 SM[2:0] = 110 Figure 10. Translator Table: Circular and Square Direction NXT−polarity bit <NXTP> (see Table 14 SPI Control The direction of rotation is selected by means of following Parameter Overview), the next step is initiated either on the combination of the DIR input pin and the SPI−controlled rising edge or the falling edge of the NXT input. direction bit <DIRCTRL>. (see Table 14 SPI Control Translator Position Parameter Overview) The translator position MSP[6:0] can be read in SPI Status NXT input Register 3 (See Table 15 SR3). This is a 7−bit number Changes on the NXT input will move the motor current equivalent to the 1/32th micro−step from see Table 10 one step up/down in the translator table (even when the “Circular Translator Table”. The translator position is motor is disabled: <MOTEN> = 0). Depending on the updated immediately following a NXT trigger. NXT Update Update Translator Position Translator Position Figure 11. Translator Position Timing Diagram Synchronization of Step Mode and NXT Input If the step resolution is decreased at a translator table When step mode is re−programmed to another resolution position that is shared both by the old and new resolution (Figure 12), then this is put in effect immediately upon the setting, then the offset is zero and micro−stepping is first arriving “NXT” input. If the micro−stepping resolution proceeds according to the translator table. is increased, the coil currents will be regulated to the nearest If the translator position is not shared both by the old and micro−step, according to the fixed grid of the increased new resolution setting, then the micro−stepping proceeds resolution. If however the micro−stepping resolution is with an offset relative to the translator table (See Figure 12 decreased, then it is possible to introduce an offset (or phase right hand side). shift) in the micro−step translator table. http://onsemi.com 15

AMIS−30542 Change from lower to higher resolution Change from higher to lower resolution Iy Iy Iy Iy DIR DIR DIR DIR endpos NXT3NXT2 NXT1 endpos NXT1 startpos NXT4 startpos NXT2 Ix Ix Ix Ix NXT3 Halfstep 1/4th step 1/8th step Halfstep PC20070604.6 Figure 12. NXT−Step Mode Synchronization Left: Change from lower to higher resolution. The left−hand side depicts the ending half−step position during which a new step mode resolution was programmed. The right−hand side diagram shows the effect of subsequent NXT commands on the micro−step position. Right: Change from higher to lower resolution. The left−hand side depicts the ending micro−step position during which a new step mode resolution was programmed. The right−hand side diagram shows the effect of subsequent NXT commands on the half−step position. Note: It is advised to reduce the micro−stepping resolution only at micro−step positions that overlap with desired micro−step positions of the new resolution. Programmable Peak−Current Overview). Whenever this parameter is changed, the The amplitude of the current waveform in the motor coils coil−currents will be updated immediately at the next PWM (coil peak current = I ) is adjusted by means of an SPI period. Figure 13 presents the Peak−Current and Current max parameter “CUR[4:0]” (see Table 14 SPI Control Parameter Ratings in conjunction to the Current setting CUR[4:0]. Peak Current 4.75A Current Range3 CUR[4:0] =23−>31 2.40A Current Range2 CUR[4:0] =16−>22 1.20A Current Range1 CUR[4:0] =9−>15 615mA Current Range0 CUR[4:0] =0−>8 0 8 15 22 31 CUR[4:0] Figure 13. Programmable Peak−Current Overview http://onsemi.com 16

AMIS−30542 Speed and Load Angle Output current zero crossings”. Per coil, two zero−current positions The SLA−pin provides an output voltage that indicates the exist per electrical period, yielding in total four zero−current level of the Back−e.m.f. voltage of the motor. This observation points per electrical period. Back−e.m.f. voltage is sampled during every so−called ”coil ICOIL VBEMF t ZOOM Previous Next Coil Current Zero Crossing Micro−step Micro−step ICOIL Current Decay Zero Current t V COIL Voltage Transient VBB |V | BEMF t Figure 14. Principle of Bemf Measurement Because of the relatively high recirculation currents in the behavior of the coil voltage is not visible anymore, this mode coil during current decay, the coil voltage V shows a generates smoother Back e.m.f. input for post−processing, COIL transient behavior. As this transient is not always desired in e.g. by software. application software, two operating modes can be selected In order to bring the sampled Back e.m.f. to a descent by means of the bit <SLAT> (see “SLA−transparency” in output level (0 V to 5 V), the sampled coil voltage V is COIL Table 14 SPI Control Parameter Overview). The SLA pin divided by 2 or by 4. This divider is set through an SPI bit shows in “transparent mode” full visibility of the voltage <SLAG>. (see Table 14 SPI Control Parameter Overview) transient behavior. This allows a sanity−check of the The following drawing illustrates the operation of the speed−setting versus motor operation and characteristics SLA−pin and the transparency−bit. “PWMsh” and “I = COIL and supply voltage levels. If the bit “SLAT” is cleared, then 0” are internal signals that define together with SLAT the only the voltage samples at the end of each coil current zero sampling and hold moments of the coil voltage. crossing are visible on the SLA−pin. Because the transient http://onsemi.com 17

AMIS−30542 Ssh Sh VCOIL ddiivv24 buf SLA−pin Ch Csh Icoil=0 SLAT PWMsh NOT(Icoil=0) PWMsh Icoil=0 SLAT VCOIL t SLA−pin laiss rt estaaminpelde VBEMF retain last sample previous output is kept at SLA pin t SLAT = 1 => SLA−pin is “transparent” during SLAT = 0 => SLA−pin is not “transparent” during VBEMF sampling @ Coil Current Zero VBEMF sampling @ Coil Current Zero Crossing. Crossing. SLA−pin is updated “real−time”. SLA−pin is updated when leaving current−less state. Figure 15. Timing Diagram of SLA−Pin Warning, Error Detection and Diagnostics Open Coil/Current Not Reached Detection Feedback Open coil detection is based on the observation of 100% duty cycle of the PWM regulator. If in a coil 100% duty cycle Thermal Warning and Shutdown is detected for longer than 200 ms then the related driver When junction temperature rises above T , the thermal TW transistors are disabled (high−impedance) and an warning bit <TW> is set (Table 16 SPI Status registers appropriate bit in the SPI status register is set (<OPENX> or Address SR0). If junction temperature increases above <OPENY>). (Table 16) thermal shutdown level, then the circuit goes in “Thermal When the resistance of a motor coil is very large and the Shutdown” mode (<TSD>) and all driver transistors are supply voltage is low, it can happen that the motor driver is disabled (high impedance) (see Table 16 SPI Status registers not able to deliver the requested current to the motor. Under Address SR2). The conditions to reset flag <TSD> is to be these conditions the PWM controller duty cycle will be at a temperature lower than Ttw and to clear the <TSD> flag 100% and after 200 ms the error pin and <OPENX>, by reading it using any SPI read command. <OPENY> will flag this situation (motor current is kept alive). This feature can be used to test if the operating Overcurrent Detection conditions (supply voltage, motor coil resistance) still allow The overcurrent detection circuit monitors the load reaching the requested coil−current or else the coil current current in each activated output stage. If the load current should be reduced. exceeds the over−current detection threshold, then the overcurrent flag is set and the drivers are switched off to Charge Pump Failure reduce the power dissipation and to protect the integrated The charge pump is an important circuit that guarantees circuit. Each driver transistor has an individual detection bit low R for all drivers, especially for low supply DS(on) in (see Table 16 SPI Status registers Address SR1 and SR2: voltages. If supply voltage is too low or external components <OVCXij> and <OVCYij>). Error condition is latched are not properly connected to guarantee R of the DS(on) and the microcontroller needs to clean the status bits to drivers, then the bit <CPFAIL> is set (Table 16). Also after reactivate the drivers. POR the charge pump voltage will need some time to exceed Note: Successive reading the SPI StatusRegisters 1 and 2 in the required threshold. During that time <CPFAIL> will be case of a short circuit condition, may lead to damage to the set to “1”. drivers. http://onsemi.com 18

AMIS−30542 Error Output circuitry, the specified I should be reduced with the load This is a digital output to flag a problem to the external consumption of internal circuitry (unloaded outputs) and the microcontroller. The signal on this output is active low and loads connected to logic outputs. See Table 5. DC the logic combination of: parameters NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR Power−On Reset (POR) Function <OVCYij> OR <OPENi> OR <CPFAIL> The open drain output pin POR/WD provides an “active low” reset for external purposes. At powerup of Logic Supply Regulator AMIS−30542, this pin will be kept low for some time to reset AMIS−30542 has an on−chip 5 V low−drop regulator for example an external microcontroller. A small analogue with external capacitor to supply the digital part of the chip, filter avoids resetting due to spikes or noise on the V some low−voltage analog blocks and external circuitry. The DD supply. voltage level is derived from an internal bandgap reference. To calculate the available drive−current for external VBB t VDD tPU tPD VDDH VDDL t <tRF POR/WD pin tPOR tRF Figure 16. Power−on−Reset Timing Diagram Watchdog Function analog circuits is depending on the reset state of the digital, The watchdog function is enabled/disabled through charge pump remains active. Logic 0 on CLR pin resumes <WDEN> bit (Table 13: SPI CONTROL REGISTERS normal operation again. (ALL SPI control registers have Read/Write Access and The voltage regulator remains functional during and after default to “0” after power−on or hard reset.)). Once this bit the reset and the POR/WD pin is not activated. Watchdog has been set to “1” (watchdog enable), the microcontroller function is reset completely. needs to re−write this bit to clear an internal timer before the Sleep Mode watchdog timeout interval expires. In case the timer is The bit <SLP> in SPI Control Register 2 (See Table 12) activated and WDEN is acknowledged too early (before is provided to enter a so−called “sleep mode”. This mode t ) or not within the interval (after t ), then a reset WDPR WDTO allows reduction of current−consumption when the motor is of the microcontroller will occur through POR/WD pin. In not in operation. The effect of sleep mode is as follows: addition, a warm/cold boot bit <WD> is available (see • Tables 16 and 17) for further processing when the external The drivers are put in HiZ • microcontroller is alive again. All analog circuits are disabled and in low−power mode • All internal registers are maintaining their logic content CLR pin (=Hard Reset) • NXT and DIR inputs are forbidden Logic 0 on CLR pin allows normal operation of the chip. • To reset the complete digital inside AMIS−30542, the input SPI communication remains possible (slight current CLR needs to be pulled to logic 1 during minimum time increase during SPI communication) • given by tCLR. (Table 6 AC Parameters). This reset function Oscillator and digital clocks are silent, except during clears all internal registers without the need of a SPI communication power−cycle, except in sleep mode. The operation of all http://onsemi.com 19

AMIS−30542 The voltage regulator remains active but with reduced Normal operation is resumed after writing logic ‘0’ to bit current−output capability (I ). The watchdog timer <SLP>. A startup time is needed for the charge pump to LOADSLP stops running and it’s value is kept in the counter. Upon stabilize. After this time, NXT commands can be issued. leaving sleep mode, this timer continues from the value it had before entering sleep mode. VBB t VDD tPU VDDH t tPOR POR/WD pin tDSPI tWDRD tPOR Enable WD >tWDPRand<tWDTO =tWDPRor=tWDTO Acknowledge WD t tWDTO WD timer t Figure 17. Watchdog Timing Diagram NOTE: tDSPI is the time needed by the external microcontroller to shift−in the <WDEN> bit after a powerup. The duration of the watchdog timeout interval is programmable through the WDT[3:0] bits (See also Table 13: SPI CONTROL REGISTERS (ALL SPI control registers have Read/Write Access and default to “0” after power−on or hard reset). The timing is given in Table 12 below. Table 12. WATCHDOG TIMEOUT INTERVAL AS FUNCTION OF WDT[3.0] Index WDT[3:0] tWDTO (ms) Index WDT[3:0] tWDTO (ms) 0 0000 32 8 1000 288 1 0001 64 9 1001 320 2 0010 96 10 1010 352 3 0011 128 11 1011 384 4 0100 160 12 1100 416 5 0101 192 13 1101 448 6 0110 224 14 1110 480 7 0111 256 15 1111 512 http://onsemi.com 20

AMIS−30542 SPI INTERFACE The serial peripheral interface (SPI) allows an external DO signal is the output from the Slave (AMIS−30542), and microcontroller (Master) to communicate with DI signal is the output from the Master. A chip select line AMIS−30542. The implemented SPI block is designed to (CS) allows individual selection of a Slave SPI device in a interface directly with numerous micro−controllers from multiple−slave system. The CS line is active low. If several manufacturers. AMIS−30542 acts always as a Slave AMIS−30542 is not selected, DO is pulled up with the and can’t initiate any transmission. The operation of the external pull up resistor. Since AMIS−30542 operates as a device is configured and controlled by means of SPI Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks registers which are observable for read and/or write from the data out on the falling edge and samples data in on rising Master. edge of clock. The Master SPI port must be configured in MODE 0 too, to match this operation. The SPI clock idles SPI Transfer Format and Pin Signals low between the transferred bytes. During a SPI transfer, data is simultaneously transmitted The diagram below is both a Master and a Slave timing (shifted out serially) and received (shifted in serially). A diagram since CLK, DO and DI pins are directly connected serial clock line (CLK) synchronizes shifting and sampling between the Master and the Slave. of the information on the two serial data lines (DO and DI). #CLK cycle 1 2 3 4 5 6 7 8 CS CLK ÌÌÌÌ ÌÌÌÌ DI MSB 6 5 4 3 2 1 LSB ÌÌÌ ÌÌÌ DO MSB 6 5 4 3 2 1 LSB ÌÌÌ Figure 18. Timing Diagram of a SPI Transfer NOTE: At the falling edge of the eight clock pulse the data−out shift register is updated with the content of the addressed internal SPI register. The internal SPI registers are updated at the first rising edge of the AMIS−30542 system clock when CS = High Transfer Packet: Serial data transfer is assumed to follow MSB first rule. The transfer packet contains one or more bytes. BYTE 1 BYTE 2 Command and SPI Register Address Data MSB LSB MSB LSB CMD2 CMD1 CMD0 ADDR4ADDR3 ADDR2ADDR1 ADDR0 D7 D6 D5 D4 D3 D2 D1 D0 Command SPI Register Address Figure 19. SPI Transfer Packet Byte 1 contains the Command and the SPI Register sent from the Master in a WRITE operation, or received Address and indicates to AMIS−30542 the chosen type of from AMIS−30542 in a READ operation. operation and addressed register. Byte 2 contains data, or http://onsemi.com 21

AMIS−30542 Two command types can be distinguished in the READ command. This READ command contains the communication between master and AMIS−30542: address of the SPI register to be read out. At the falling edge • READ from SPI Register with address ADDR[4:0]: of the eight clock pulse the data−out shift register is updated CMD2 = “0” with the content of the corresponding internal SPI register. • In the next 8−bit clock pulse train this data is shifted out via WRITE to SPI Register with address ADDR[4:0]: DO pin. At the same time the data shifted in from DI CMD2 = “1” (Master) should be interpreted as the following successive READ Operation command or dummy data. If the Master wants to read data from Status or Control Registers, it initiates the communication by sending a Registers are updated with internal status at the rising edge of the internal AMIS−30542 clock when CS = 1 CS COMMAND DI READ DATA from ADDR1 COMMAND or DUMMY DATA from previous command or NOT VALID after POR or RESET DATA DATA DO OLD DATA or NOT VALID DATA from ADDR1 Figure 20. Single READ Operation where DATA from SPI Register with Address 1 is Read by the Master All 4 Status Registers (see SPI Registers) contain 7 data should force CS high immediately after the READ bits and a parity check bit The most significant bit (D7) operation. For the same reason it is recommended to keep represents a parity of D[6:0]. If the number of logical ones the CS line high always when the SPI bus is idle. in D[6:0] is odd, the parity bit D7 equals “1”. If the number WRITE Operation of logical ones in D[6:0] is even then the parity bit D7 equals If the Master wants to write data to a Control Register it “0”. This simple mechanism protects against noise and initiates the communication by sending a WRITE increases the consistency of the transmitted data. If a parity command. This contains the address of the SPI register to check error occurs it is recommended to initiate an write to. The command is followed with a data byte. This additional READ command to obtain the status again. incoming data will be stored in the corresponding Control Also the Control Registers can be read out following the Register after CS goes from low to high! AMIS−30542 same routine. Control Registers don’t have a parity check. responds on every incoming byte by shifting out via DO the The CS line is active low and may remain low between data stored in the last received address. successive READ commands as illustrated in Figure 22. It is important that the writing action (command − address There is however one exception. In case an error condition and data) to the Control Register is exactly 16 bits long. If is latched in one of Status Registers (see SPI Registers) the more or less bits are transmitted the complete transfer packet ERR pin is activated. (See Section Error Output). This signal is ignored. flags a problem to the external microcontroller. By reading A WRITE command executed for a read−only register the Status Registers information about the root cause of the (e.g. Status Registers) will not affect the addressed register problem can be determined. After this READ operation the and the device operation. Status Registers are cleared. Because the Status Registers Because after a power−on−reset the initial address is and ERR pin (see SPI Registers) are only updated by the unknown the data shifted out via DO is not valid. internal system clock when the CS line is high, the Master http://onsemi.com 22

AMIS−30542 The NEW DATA is written into the corresponding internal register at the rising edge of CS CS COMMAND DATA DI WRITE DATA to ADDR3 NEW DATA for ADDR3 DATA from previous command or NOT VALID after POR or RESET DATA DATA DO OLD DATA or NOT VALID OLD DATA from ADDR3 Figure 21. Single WRITE Operation Where DATA from the Master is Written in SPI Register with Address 3 Examples of combined READ and WRITE by writing a control byte in Control Register at ADDR2. Operations Note that during the write command the old data of the In the following examples successive READ and WRITE pointed register is returned at the moment the new data is operations are combined. In Figure 22 the Master first reads shifted in the status from Register at ADDR4 and at ADDR5 followed Registers are updated with the internal The NEW DATA is written into the status at the rising edge of the internal corresponding internal register at AMIS−30542 clock when CS = 1 the rising edge of CS CS COMMAND COMMAND COMMAND DATA READ DATA READ DATA WRITE DATA NEW DATA DI from ADDR4 from ADDR5 to ADDR2 for ADDR2 DATA from previous command or NOT VALID after POR or RESET DATA DATA DATA DATA OLD DATA DATA DATA OLD DATA DO or NOT VALID from ADDR4 from ADDR5 from ADDR2 Figure 22. 2 Successive READ Commands Followed by a WRITE Command After the write operation the Master could initiate a read transmitted. This rule also applies when the master device back command in order to verify the data correctly written wants to initiate an SPI transfer to read the Status Registers. as illustrated in Figure 23. During reception of the READ Because the internal system clock updates the Status command the old data is returned for a second time. Only Registers only when CS line is high, the first read out byte after receiving the READ command the new data is might represent old status information. http://onsemi.com 23

AMIS−30542 Registers are updated with The NEW DATA is written into the the internal status at the corresponding internal register at rising edge of CS the rising edge of CS CS COMMAND DATA COMMAND WRITE DATA NEW DATA READ DATA COMMAND DI to ADDR2 for ADDR2 from ADDR2 or DUMMY DATA from previous command or NOT VALID after POR or RESET DATA DATA DATA DATA DO OLD DATA OLD DATA OLD DATA NEW DATA or NOT VALID from ADDR2 from ADDR2 from ADDR2 Figure 23. A WRITE Operation Where DATA from the Master is Written in SPI Register with Address 2 Followed by a READ Back Operation to Confirm a Correct WRITE Operation NOTE: The internal data−out shift buffer of AMIS−30542 is updated with the content of the selected SPI register only at the last (every eight) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data. Table 13. SPI CONTROL REGISTERS (All SPI control registers have Read/Write Access and default to “0” after power−on or hard reset) Structure Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Address Reset 0 0 0 0 0 0 0 0 WR (00h) Data WDEN WDT[3:0] − − − CR0 (01h) Data SM[2:0] CUR[4:0] CR1 (02h) Data DIRCTRL NXTP − − PWMF PWMJ EMC[1:0] CR2 (03h) Data MOTEN SLP SLAG SLAT − − − − CR2 (08h) Data M[1:0] StrB[1:0] − StrC StrE[1:0] Where: R/W Read and Write access Reset: Status after power−On or hard reset http://onsemi.com 24

AMIS−30542 Table 14. SPI CONTROL PARAMETER OVERVIEW Symbol Description Status Value DIRCTRL Controls the direction of rotation (in combination with <DIR> = 0 <DIRCTRL> = 0 CW motion (Note 15) logic level on input DIR) <DIRCTRL> = 1 CCW motion (Note 15) <DIR> = 1 <DIRCTRL> = 0 CCW motion (Note 15) <DIRCTRL> = 1 CW motion (Note 15) NXTP Selects if NXT triggers on rising or falling edge <NXTP> = 0 Trigger on rising edge <NXTP> = 1 Trigger on falling edge EMC[1:0] Turn On – Turn−off Slopes of motor driver (Note 14) 00 Very Fast 01 Fast 10 Slow 11 Very Slow SLAT Speed load angle transparency bit <SLAT> = 0 SLA is transparent <SLAT> = 1 SLA is NOT transparent SLAG Speed load angle gain setting <SLAG> = 0 Gain = 0.5 <SLAG> = 1 Gain = 0.25 PWMF Enables doubling of the PWM frequency (Note 14) <PWMF> = 0 Default Frequency <PWMF> = 1 Double Frequency PWMJ Enables jittery PWM <PWMJ> = 0 Jitter disabled <PWMJ> = 1 Jitter enabled SM[2:0] Stepmode 000 1/32 Micro − Step 001 1/16 Micro − Step 010 1/8 Micro − Step 011 1/4 Micro − Step 100 Compensated Half Step 101 Uncompensated Half Step 110 Full Step 111 n.a. SLP Enables sleep mode <SLP> = 0 Active mode <SLP> = 1 Sleep mode MOTEN Activates the motor driver outputs <MOTEN> = 0 Drivers disabled <MOTEN> = 1 Drivers enabled M[1:0] PWM Mode Control 00 Default control 01 DCMin Mode 1 10 DCMin Mode 1’ 11 DCMin Mode 2 StrB[1:0] PWM Strobe B Control: DON mask comparator time 00 4 PWM clock cycles (Note 16) 01 8 PWM clock cycles 10 12 PWM clock cycles 11 19 PWM clock cycles StrC PWM Strobe C Control: Switch time top/bottom <StrC> = 0 86% duty cycle PWM regulator regulation <StrC> = 1 75% duty cycle PWM regulator StrE[1:0] PWM Strobe E Control: Compensation bridge active 00 4 PWM clock cycles time (Note 16) 01 8 PWM clock cycles 10 12 PWM clock cycles 11 19 PWM clock cycles 14.The typical values can be found in Table 5: DC Parameters and in Table 6: AC parameters 15.Depending on the wiring of the motor connections 16.The duration is depending on the selected PWM frequency http://onsemi.com 25

AMIS−30542 CUR[4:0] Selects IMCmax peak. This is the peak or amplitude of the regulated current waveform in the motor coils. Table 15. SPI CONTROL PARAMETER OVERVIEW CUR[4:0] Current Range Current (mA) Current Range Current (mA) (Note 18) Index CUR[4:0] (Note 17) (Note 18) Index CUR[4:0] (Note 17) 0 00000 122 16 10000 1390 1 00001 230 17 10001 1520 2 00010 350 18 10010 1680 3 00011 370 2 19 10011 1810 0 4 00100 410 20 10100 2000 5 00101 455 21 10101 2165 6 00110 500 22 10110 2400 7 00111 550 23 10111 2650 8 01000 615 24 11000 2880 9 01001 680 25 11001 3090 10 01010 750 26 11010 3325 11 01011 840 3 27 11011 3570 1 12 01100 916 28 11100 3825 13 01101 1010 29 11101 4090 14 01110 1110 30 11110 4370 15 01111 1205 31 11111 4750 17.Typical current amplitude at TJ = 125 18.Reducing the current over different current ranges might trigger overcurrent detection. See dedicated application note for solutions SPI Status Register Description All 4 SPI status registers have Read Access and are default to “0” after power−on or hard reset. Table 16. SPI STATUS REGISTERS Structure Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R R R R R R R R Address Reset 0 0 0 0 0 0 0 0 SR0 (04h) Data is not latched PAR TW CPfail WD OPENX OPENY − − SR1 (05h) Data is latched PAR OVCXPT OVCXPB OVCXNT OVCXNB − − − SR2 (06h) Data is latched PAR OVCYPT OVCYPB OVCYYNT OVCYNB TSD − − SR3 (07h) Data is not latched PAR MSP[6:0] Where: R Read only mode access Reset Status after power−on or hard reset PAR Parity check http://onsemi.com 26

AMIS−30542 Table 17. SPI STATUS FLAGS OVERVIEW Length Related Reset Mnemonic Flag (bit) SPI Register Comment State CPFail Charge pump failure 1 Status Register 0 ‘0’ = no failure ‘0’ ‘1’ = failure: indicates that the charge pump does not reach the required voltage level. Note 1 MSP[6:0] Micro−step position 7 Status Register 3 Translator micro step position ‘0000000’ OPENX OPEN Coil X 1 Status Register 0 ‘1’ = Open coil detected ‘0’ OPENY OPEN Coil Y 1 Status Register 0 ‘1’ = Open coil detected ‘0’ OVCXNB OVer Current on X 1 Status Register 1 ‘0’ = no failure ‘0’ H−bridge; MOTXN ‘1’ = failure: indicates that over current is detected terminal; Bottom at bottom transistor XN−terminal tran. OVCXNT OVer Current on X 1 Status Register 1 ‘0’ = no failure ‘0’ H−bridge; MOTXN ‘1’ = failure: indicates that over current is detected terminal; Top transist. at top transistor XN−terminal OVCXPB OVer Current on X 1 Status Register 1 ‘0’ = no failure ‘0’ H−bridge; MOTXP ‘1’ = failure: indicates that over current is detected terminal; Bottom at bottom transistor XP−terminal tran. OVCXPT OVer Current on X 1 Status Register 1 ‘0’ = no failure ‘0’ H−bridge; MOTXP ‘1’ = failure: indicates that over current is detected terminal; Top transist. at top transistor XP−terminal OVCYNB OVer Current on Y 1 Status Register 2 ‘0’ = no failure ‘0’ H−bridge; MOTYN ‘1’ = failure: indicates that over current is detected terminal; Bottom tran. at bottom transistor YN−terminal OVCYNT OVer Current on Y 1 Status Register 2 ‘0’ = no failure ‘0’ H−bridge; MOTYN ‘1’ = failure: indicates that over current is detected terminal; Top transist. at top transistor YN−terminal OVCYPB OVer Current on Y 1 Status Register 2 ‘0’ = no failure ‘0’ H−bridge; MOTYP ‘1’ = failure: indicates that over current is detected terminal; Bottom at bottom transistor YP−terminal tran. OVCYPT OVer Current on Y 1 Status Register 2 ‘0’ = no failure ‘0’ H−bridge; MOTYP ‘1’ = failure: indicates that over current is detected terminal; Top transist. at top transistor YP−terminal TSD Thermal shutdown 1 Status Register 2 ‘0’ TW Thermal warning 1 Status Register 0 ‘0’ WD Watchdog event 1 Status Register 0 ‘1’ = watchdog reset after time−out ‘0’ NOTE: WD − This bit indicates that the watchdog timer has not been cleared properly. If the master reads that WD is set to “1” after reset, it means that a watchdog reset occurred (warm boot) instead of POR (cold boot). WD bit will be cleared only when the master writes “0” to WDEN bit. Table 18. ORDERING INFORMATION Temperature Part No. Peak Current Range Package Shipping† AMIS30542C5421RG 3200 mA −40°C to 125°C NQFP−32 (7 x 7 mm) Tape & Reel (Pb−Free) AMIS30542C5421G 3200 mA −40°C to 125°C NQFP−32 (7 x 7 mm) Tube (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 27

AMIS−30542 PACKAGE DIMENSIONS NQFP−32, 7x7 CASE 560AA ISSUE O http://onsemi.com 28

AMIS−30542 PACKAGE DIMENSIONS NQFP−32, 7x7 CASE 560AA ISSUE O ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com AMIS−30542/D 29