1 kV RMS Quad-Channel Digital Isolators Data Sheet ADuM7440/ADuM7441/ADuM7442 FEATURES GENERAL DESCRIPTION Small, 16-lead QSOP The ADuM7440/ADuM7441/ADuM74421 are 4-channel digital 1000 V rms isolation rating isolators based on the Analog Devices, Inc., iCoupler® technology. Safety and regulatory approvals Combining high speed CMOS and monolithic air core transformer UL recognition technologies, these isolation components provide outstanding UL 1577: 1000 V rms for 1 minute performance characteristics superior to the alternatives, such as Low power operation optocoupler devices and other integrated couplers. 5 V operation The ADuM7440/ADuM7441/ADuM7442 family of quad 1 kV 2.25 mA per channel maximum at 0 Mbps to 1 Mbps digital isolation devices is packaged in a small 16-lead QSOP. 11.5 mA per channel maximum at 25 Mbps While most 4-channel isolators come in 16-lead wide SOIC 3.3 V operation packages, the ADuM7440/ADuM7441/ADuM7442 free almost 1.5 mA per channel maximum at 0 Mbps to 1 Mbps 70% of board space and yet can still withstand high isolation 8.25 mA per channel maximum at 25 Mbps voltage and meet UL regulatory requirements. In addition to the Bidirectional communication space savings, the ADuM7440/ADuM7441/ADuM7442 offer a Up to 25 Mbps data rate (NRZ) lower price than 2.5 kV or 5 kV isolators where only functional 3 V/5 V level translation isolation is needed. High temperature operation: 105°C High common-mode transient immunity: >15 kV/μs This family, like many Analog Devices isolators, offers very low power consumption, consuming one-tenth to one-sixth the APPLICATIONS power of comparable isolators at comparable data rates up to General-purpose, multichannel isolation 25 Mbps. Despite the low power consumption, all models of the SPI interface/data converter isolation ADuM7440/ADuM7441/ADuM7442 provide low pulse width RS-232/RS-422/RS-485 transceivers distortion (<5 ns for C grade). In addition, every model has an Industrial field bus isolation input glitch filter to protect against extraneous noise disturbances. The ADuM7440/ADuM7441/ADuM7442 isolators provide four independent isolation channels in a variety of channel configurations and two data rates (see the Ordering Guide) up to 25 Mbps. All models operate with the supply voltage on either side ranging from 3.0 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. All products also have an output default high logic state in the absence of the input power. 1 Protected by U.S. Patents 5,952,849, 6,873,065 and 7,075,329. Other patents pending. FUNCTIONAL BLOCK DIAGRAMS VDD1A 1 ADuM7440 16VDD2A VDD1A 1 ADuM7441 16VDD2A VDD1A 1 ADuM7442 16VDD2A GND1 2 15GND2 GND1 2 15GND2 GND1 2 15GND2 VIA 3 ENCODE DECODE 14VOA VIA 3 ENCODE DECODE 14VOA VIA 3 ENCODE DECODE 14VOA VIB 4 ENCODE DECODE 13VOB VIB 4 ENCODE DECODE 13VOB VIB 4 ENCODE DECODE 13VOB VIC 5 ENCODE DECODE 12VOC VIC 5 ENCODE DECODE 12VOC VOC 5 DECODE ENCODE 12VIC VID 6 ENCODE DECODE 11VOD VOD 6 DECODE ENCODE 11VID VOD 6 DECODE ENCODE 11VID VGDNDD1B1 87 190VGDNDD22B 08340-001 VGDNDD1B1 87 190VGDNDD22B 08340-002 VGDNDD1B1 87 190VGDNDD22B 08340-003 Figure 1. ADuM7440 Figure 2. ADuM7441 Figure 3. ADuM7442 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADuM7440/ADuM7441/ADuM7442 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Recommended Operating Conditions .......................................7 Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................8 General Description ......................................................................... 1 ESD Caution...................................................................................8 Functional Block Diagrams ............................................................. 1 Pin Configurations and Function Descriptions ............................9 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 12 Specifications ..................................................................................... 3 Applications Information .............................................................. 14 Electrical Characteristics—5 V Operation................................ 3 PC Board Layout ........................................................................ 14 Electrical Characteristics—3.3 V Operation ............................ 4 Propagation Delay-Related Parameters ................................... 14 Electrical Characteristics—Mixed 5 V/3.3 V Operation ........ 5 DC Correctness and Magnetic Field Immunity ........................... 14 Electrical Characteristics—Mixed 3.3 V/5 V Operation ........ 6 Power Consumption .................................................................. 15 Package Characteristics ............................................................... 7 Insulation Lifetime ..................................................................... 15 Regulatory Information ............................................................... 7 Outline Dimensions ....................................................................... 17 Insulation and Safety-Related Specifications ............................ 7 Ordering Guide .......................................................................... 17 REVISION HISTORY 10/15—Rev. C to Rev. D 8/10—Rev. 0 to Rev. A Change to Features Section and General Description Section ........ 1 Change to Features ............................................................................ 1 Changes to Table 14 .......................................................................... 7 Changes to Table 1 ............................................................................. 3 Updated Outline Dimensions ....................................................... 17 Added Note 1, Table 1 ....................................................................... 3 Changes to Table 4 ............................................................................. 4 2/12—Rev. B to Rev. C Added Note 1, Table 4 ....................................................................... 4 Created Hyperlink for Safety and Regulatory Approvals Changes to Table 7 ............................................................................. 5 Entry in Features Section ................................................................. 1 Added Note 1, Table 7 ....................................................................... 5 Change to PC Board Layout Section ............................................ 14 Changes to Table 10 .......................................................................... 6 Added Note 1, Table 10 ..................................................................... 6 2/11—Rev. A to Rev. B Changes to Table 14 .......................................................................... 7 Changes to Figure 7 ........................................................................ 11 10/09—Revision 0: Initial Version Rev. D | Page 2 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION All typical specifications are at T = 25°C, V = V = 5 V. Minimum/maximum specifications apply over the entire recommended A DD1 DD2 operation range of 4.5 V ≤ V ≤ 5.5 V, 4.5 V ≤ V ≤ 5.5 V, and −40°C ≤ T ≤ +105°C, unless otherwise noted. Switching specifications DD1 DD2 A are tested with C = 15 pF, and CMOS signal levels, unless otherwise noted. L Table 1. A Grade C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS Data Rate 1 25 Mbps Within PWD limit Propagation Delay t , t 50 75 29 40 50 ns 50% input to 50% output PHL PLH Pulse Width Distortion PWD 10 25 2 5 ns |t − t | PLH PHL Change vs. Temperature 5 3 ps/°C Pulse Width PW 250 40 ns Within PWD limit Propagation Delay Skew1 t 20 10 ns PSK Channel Matching Codirectional t 25 2 4 ns PSKCD Opposing-Direction t 30 3 6 ns PSKOD Jitter 2 2 ns 1 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Table 2. 1 Mbps—A Grade 25 Mbps—C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments SUPPLY CURRENT ADuM7440 I 4.3 5.4 28 35 mA DD1 I 2.5 3.6 6.0 11 mA DD2 ADuM7441 I 4.1 4.9 18 26 mA DD1 I 3.6 4.7 8.5 14 mA DD2 ADuM7442 I 3.2 4.0 15 20 mA DD1 I 3.2 4.0 12 17 mA DD2 Table 3. For All Models Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Logic High Input Threshold V 0.7 V V IH DDx Logic Low Input Threshold V 0.3 V V IL DDx Logic High Output Voltages V V − 0.1 5.0 V I = −20 µA, V = V OH DDx Ox Ix IxH V − 0.4 4.8 V I = −4 mA, V = V DDx Ox Ix IxH Logic Low Output Voltages V 0.0 0.1 V I = 20 µA, V = V OL Ox Ix IxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL Input Current per Channel I −10 +0.01 +10 µA 0 V ≤ V ≤ V I Ix DDx Supply Current per Channel Quiescent Input Supply Current IDDI(Q) 0.76 0.95 mA Quiescent Output Supply Current I 0.57 0.73 mA DDO(Q) Dynamic Input Supply Current I 0.26 mA/Mbps DDI(D) Dynamic Output Supply Current I 0.05 mA/Mbps DDO(D) AC SPECIFICATIONS Output Rise/Fall Time t/t 2.0 ns 10% to 90% R F Common-Mode Transient Immunity1 |CM| 15 25 kV/µs V = V , V = 1000 V, Ix DDx CM transient magnitude = 800 V Refresh Rate f 1.2 Mbps r 1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. D | Page 3 of 20

ADuM7440/ADuM7441/ADuM7442 Data Sheet ELECTRICAL CHARACTERISTICS—3.3 V OPERATION All typical specifications are at T = 25°C, V = V = 3.3 V. Minimum/maximum specifications apply over the entire recommended A DD1 DD2 operation range of 3.0 V ≤ V ≤ 3.6 V, 3.0 V ≤ V ≤ 3.6 V; and −40°C ≤ T ≤ +105°C, unless otherwise noted. Switching specifications DD1 DD2 A are tested with C = 15 pF and CMOS signal levels, unless otherwise noted. L Table 4. A Grade C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS Data Rate 1 25 Mbps Within PWD limit Propagation Delay t , t 60 85 37 51 66 ns 50% input to 50% output PHL PLH Pulse Width Distortion PWD 10 25 2 5 ns |t − t | PLH PHL Change vs. Temperature 5 3 ps/°C Pulse Width PW 250 40 ns Within PWD limit Propagation Delay Skew1 t 20 10 ns PSK Channel Matching Codirectional t 25 3 5 ns PSKCD Opposing-Direction t 30 4 7 ns PSKOD Jitter 2 2 ns 1 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Table 5. 1 Mbps—A, C Grades 25 Mbps—C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments SUPPLY CURRENT ADuM7440 I 3.0 3.8 20 28 mA DD1 I 1.8 2.3 4.0 5.0 mA DD2 ADuM7441 I 2.8 3.5 14 20 mA DD1 I 2.5 3.3 5.5 7.5 mA DD2 ADuM7442 I 2.2 2.7 10 13 mA DD1 I 2.2 2.8 8.4 11 mA DD2 Table 6. For All Models Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Logic High Input Threshold VIH 0.7 VDDx V Logic Low Input Threshold VIL 0.3 VDDx V Logic High Output Voltages V V − 0.2 3.3 V I = −20 µA, V = V OH DDx Ox Ix IxH V − 0.4 3.1 V I = −4 mA, V = V DDx Ox Ix IxH Logic Low Output Voltages V 0.0 0.1 V I = 20 µA, V = V OL Ox Ix IxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL Input Current per Channel I −10 +0.01 +10 µA 0 V ≤ V ≤ V I Ix DDx Supply Current per Channel Quiescent Input Supply Current I 0.50 mA DDI(Q) Quiescent Output Supply Current I 0.41 mA DDO(Q) Dynamic Input Supply Current I 0.18 mA/Mbps DDI(D) Dynamic Output Supply Current I 0.02 mA/Mbps DDO(D) AC SPECIFICATIONS Output Rise/Fall Time t/t 2.8 ns 10% to 90% R F Common-Mode Transient Immunity1 |CM| 15 20 kV/µs V = V , V = 1000 V, Ix DDx CM transient magnitude = 800 V Refresh Rate f 1.1 Mbps r 1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. D | Page 4 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OPERATION All typical specifications are at T = 25°C, V = 5 V, V = 3.3 V. Minimum/maximum specifications apply over the entire recommended A DD1 DD2 operation range of 4.5 V ≤ V ≤ 5.5 V, 3.0 V ≤ V ≤ 3.6 V; and −40°C ≤ T ≤ +105°C, unless otherwise noted. Switching specifications DD1 DD2 A are tested with C = 15 pF and CMOS signal levels, unless otherwise noted. L Table 7. A Grade C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS Data Rate 1 25 Mbps Within PWD limit Propagation Delay t , t 55 80 30 42 55 ns 50% input to 50% output PHL PLH Pulse Width Distortion PWD 10 25 2 5 ns |t − t | PLH PHL Change vs. Temperature 5 3 ps/°C Pulse Width PW 250 40 ns Within PWD limit Propagation Delay Skew1 t 20 10 ns PSK Channel Matching Codirectional t 25 2 5 ns PSKCD Opposing-Direction t 30 3 6 ns PSKOD Jitter 2 2 ns 1 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Table 8. 1 Mbps—A, C Grades 25 Mbps—C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments SUPPLY CURRENT ADuM7440 I 4.4 5.5 28 35 mA DD1 I 1.6 2.1 3.5 4.5 mA DD2 ADuM7441 I 3.7 5.0 19 27 mA DD1 I 2.2 2.8 5.2 7.0 mA DD2 ADuM7442 I 3.2 3.9 15 20 mA DD1 I 2.0 2.6 7.8 12 mA DD2 Table 9. For All Models Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Logic High Input Threshold V 0.7 V V IH DDx Logic Low Input Threshold V 0.3 V V IL DDx Logic High Output Voltages V V − 0.1 V V I = −20 µA, V = V OH DDx DDx Ox Ix IxH V − 0.4 V − 0.2 V I = −4 mA, V = V DDx DDx Ox Ix IxH Logic Low Output Voltages V 0.0 0.1 V I = 20 µA, V = V OL Ox Ix IxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL Input Current per Channel I −10 +0.01 +10 µA 0 V ≤ V ≤ V I Ix DDx Supply Current per Channel Quiescent Input Supply Current I 0.77 mA DDI(Q) Quiescent Output Supply Current I 0.40 mA DDO(Q) Dynamic Input Supply Current I 0.26 mA/Mbps DDI(D) Dynamic Output Supply Current I 0.02 mA/Mbps DDO(D) AC SPECIFICATIONS Output Rise/Fall Time t/t 2.5 ns 10% to 90% R F Common-Mode Transient Immunity1 |CM| 15 20 kV/µs V = V , V = 1000 V, Ix DDx CM transient magnitude = 800 V Refresh Rate f 1.2 Mbps r 1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. D | Page 5 of 20

ADuM7440/ADuM7441/ADuM7442 Data Sheet ELECTRICAL CHARACTERISTICS—MIXED 3.3 V/5 V OPERATION All typical specifications are at T = 25°C, V = 3.3 V, V = 5 V. Minimum/maximum specifications apply over the entire recommended A DD1 DD2 operation range of 3.0 V ≤ V ≤ 3.6 V, 4.5 V ≤ V ≤ 5.5 V, and −40°C ≤ T ≤ +105°C, unless otherwise noted. Switching specifications DD1 DD2 A are tested with C = 15 pF and CMOS signal levels, unless otherwise noted. L Table 10. A Grade C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS Data Rate 1 25 Mbps Within PWD limit Propagation Delay t , t 55 80 31 46 60 ns 50% input to 50% output PHL PLH Pulse Width Distortion PWD 10 25 2 5 ns |t − t | PLH PHL Change vs. Temperature 5 3 ps/°C Pulse Width PW 250 40 ns Within PWD limit Propagation Delay Skew1 t 20 10 ns PSK Channel Matching Codirectional t 25 2 5 ns PSKCD Opposing-Direction t 30 3 7 ns PSKOD Jitter 2 2 ns 1 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Table 11. 1 Mbps—A, C Grades 25 Mbps—C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments SUPPLY CURRENT ADuM7440 I 2.7 3.3 18 24 mA DD1 I 2.5 3.3 5.7 8.0 mA DD2 ADuM7441 I 2.5 3.3 12 20 mA DD1 I 3.6 4.6 8.0 11 mA DD2 ADuM7442 I 2.0 2.4 8.9 13 mA DD1 I 3.2 4.0 12 15 mA DD2 Table 12. For All Models Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Logic High Input Threshold V 0.7 V V IH DDx Logic Low Input Threshold V 0.3 V V IL DDx Logic High Output Voltages V V − 0.1 V V I = −20 µA, V = V OH DDx DDx Ox Ix IxH V − 0.4 V − 0.2 V I = −4 mA, V = V DDx DDx Ox Ix IxH Logic Low Output Voltages V 0.0 0.1 V I = 20 µA, V = V OL Ox Ix IxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL Input Current per Channel I −10 +0.01 +10 µA 0 V ≤ V ≤ V I Ix DDx Supply Current per Channel Quiescent Input Supply Current I 0.50 0.60 mA DDI(Q) Quiescent Output Supply Current I 0.61 0.73 mA DDO(Q) Dynamic Input Supply Current I 0.17 mA/Mbps DDI(D) Dynamic Output Supply Current I 0.03 mA/Mbps DDO(D) AC SPECIFICATIONS Output Rise/Fall Time t/t 2.5 ns 10% to 90% R F Common-Mode Transient Immunity1 |CM| 15 20 kV/µs V = V , V = 1000 V, Ix DDx CM transient magnitude = 800 V Refresh Rate f 1.1 Mbps r 1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. D | Page 6 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442 PACKAGE CHARACTERISTICS Table 13. Parameter Symbol Min Typ Max Unit Test Conditions/Comments Resistance (Input-to-Output)1 R 1013 Ω I-O Capacitance (Input-to-Output)1 C 2 pF f = 1 MHz I-O Input Capacitance2 C 4.0 pF I IC Junction-to-Ambient Thermal θ 76 °C/W Thermocouple located at center of package JA Resistance underside 1 The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together and Pin 9 through Pin 16 are shorted together. 2 Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM7440/ADuM7441/ADuM7442 are approved by the organization listed in Table 14. See Table 18 and the Insulation Lifetime section for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 14. UL Recognized under UL 1577 Component Recognition Program1 Single Protection, 1000 V rms Isolation Voltage File E214100 1 In accordance with UL 1577, each ADuM7440/ADuM7441/ADuM7442 is proof tested by applying an insulation test voltage ≥1200 V rms for 1 sec (current leakage detection limit = 5 µA). INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 15. Parameter Symbol Value Unit Test Conditions/Comments Rated Dielectric Insulation Voltage 1000 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 3.8 mm min Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 2.8 mm min Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 2.6 μm min Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) 350 RECOMMENDED OPERATING CONDITIONS 300 Table 16. A) m Parameter Symbol Min Max Unit T ( 250 EN Operating Temperature TA −40 +105 °C R UR 200 Supply Voltages1 VDD1, VDD2 3.0 5.5 V C G Input Signal Rise and Fall Times 1.0 ms N TI 150 LIMI 1 All voltages are relative to their respective ground. See the DC Correctness Y- 100 and Magnetic Field Immunity section for information on immunity to external T E magnetic fields. F A S 50 00 50CASE TEMP1E0R0ATURE (°C)150 200 08340-007 Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. D | Page 7 of 20

ADuM7440/ADuM7441/ADuM7442 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 17. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational Storage Temperature (T ) Range −65°C to +150°C ST section of this specification is not implied. Operation beyond Ambient Operating Temperature (T) −40°C to +105°C A the maximum operating conditions for extended periods may Supply Voltages (V , V ) −0.5 V to +7.0 V DD1 DD2 affect product reliability. Input Voltages (V , V , V , V )1, 2 −0.5 V to V + 0.5 V IA IB IC ID DDI Output Voltages (V , V , V , V )1, 2 −0.5 V to V + 0.5 V ESD CAUTION OA OB OC OD DDO Average Output Current per Pin3 Side 1 (I ) −10 mA to +10 mA O1 Side 2 (I ) −10 mA to +10 mA O2 Common-Mode Transients3 −100 kV/μs to +100 kV/μs 1 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the Printed Circuit Board (PCB) Layout section. 2 See Figure 4 for maximum rated current values for various temperatures. 3 Refers to common-mode transients across the insulation barrier. Common- mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. Table 18. Maximum Continuous Working Voltage1 Parameter Max Unit Constraint AC Voltage, Bipolar Waveform 420 V peak 50-year minimum lifetime AC Voltage, Unipolar Waveform Basic Insulation 420 V peak 50-year minimum lifetime DC Voltage Basic Insulation 420 V peak 50-year minimum lifetime 1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Table 19. Truth Table (Positive Logic) V Input1 V State2 V State3 V Output1 Description Ix DDI DDO Ox H Powered Powered H Normal operation; data is high. L Powered Powered L Normal operation; data is low. X Unpowered Powered H Input unpowered. Outputs are in the default high state. Outputs return to input state within 1 μs of V power restoration. See the pin function DDI descriptions (Table 20 through Table 22) for more details. X Powered Unpowered Z Output unpowered. Output pins are in high impedance state. Outputs return to input state within 1 μs of V power restoration. See the pin function DDO descriptions (Table 20 through Table 22) for more details. 1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). 2 VDDI refers to the power supply on the input side of a given channel (A, B, C, or D). 3 VDDO refers to the power supply on the output side of a given channel (A, B, C, or D). Rev. D | Page 8 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1A 1 16 VDD2A GND1* 2 15 GND2* VIA 3 ADuM7440 14 VOA VIB 4 TOP VIEW 13 VOB VIC 5 (Not to Scale) 12 VOC VID 6 11 VOD VDD1B 7 10 VDD2B GND1* 8 9 GND2* *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH TCOO NGNNEDC1T IESD R. ECCOONMNMEECNTIDNEGD B. POITNH 9 TAON DG NPDIN2 I1S5 RAERCEO INMTMEERNNDAELDL.Y 08340-004 Figure 5. ADuM7440 Pin Configuration Table 20. ADuM7440 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a ceramic DD1A bypass capacitor of value 0.01 μF to 0.1 μF between V (Pin 1) and GND (Pin 2). DD1A 1 2 GND Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND is 1 1 recommended. 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Input C. IC 6 V Logic Input D. ID 7 V Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a ceramic DD1B bypass capacitor of value 0.01 μF to 0.1 μF between V (Pin 7) and GND (Pin 8). DD1B 1 8 GND Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND is 1 1 recommended. 9 GND Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND is 2 2 recommended. 10 V Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 10 must be connected externally to Pin 16. Connect a ceramic DD2B bypass capacitor of value 0.01 μF to 0.1 μF between V (Pin 10) and GND (Pin 9). DD2B 2 11 V Logic Output D. OD 12 V Logic Output C. OC 13 V Logic Output B. OB 14 V Logic Output A. OA 15 GND Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND is 2 2 recommended. 16 V Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 16 must be connected externally to Pin 10. Connect a DD2A ceramic bypass capacitor of value 0.01 μF to 0.1 μF between V (Pin 16) and GND (Pin 15). DD2A 2 Rev. D | Page 9 of 20

ADuM7440/ADuM7441/ADuM7442 Data Sheet VDD1A 1 16 VDD2A GND1* 2 15 GND2* VIA 3 ADuM7441 14 VOA VIB 4 TOP VIEW 13 VOB VIC 5 (Not to Scale) 12 VOC VOD 6 11 VID VDD1B 7 10 VDD2B GND1* 8 9 GND2* *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH CTOO NGNNEDC1T IESD R. ECCOONMNMEECNTIDNEGD B. POITNH 9 TAON DG NPDIN2 1IS5 RAERCEO INMTMEERNNDAELDL.Y 08340-005 Figure 6. ADuM7441 Pin Configuration Table 21. ADuM7441 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a ceramic DD1A bypass capacitor of value 0.01 μF to 0.1 μF between V (Pin 1) and GND (Pin 2). DD1A 1 2 GND Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND is 1 1 recommended. 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Input C. IC 6 V Logic Output D. OD 7 V Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a ceramic DD1B bypass capacitor of value 0.01 μF to 0.1 μF between V (Pin 7) and GND (Pin 8). DD1B 1 8 GND Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND is 1 1 recommended. 9 GND Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND is 2 2 recommended. 10 V Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 10 must be connected externally to Pin 16. Connect a ceramic DD2B bypass capacitor of value 0.01 μF to 0.1 μF between V (Pin 10) and GND (Pin 9). DD2B 2 11 V Logic Input D. ID 12 V Logic Output C. OC 13 V Logic Output B. OB 14 V Logic Output A. OA 15 GND Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND is 2 2 recommended. 16 V Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 16 must be connected externally to Pin 10. Connect a DD2A ceramic bypass capacitor of value 0.01 μF to 0.1 μF between V (Pin 16) and GND (Pin 15). DD2A 2 Rev. D | Page 10 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442 VDD1A 1 16 VDD2A GND1* 2 15 GND2* VIA 3 ADuM7442 14 VOA VIB 4 TOP VIEW 13 VOB VOC 5 (Not to Scale) 12 VIC VOD 6 11 VID VDD1B 7 10 VDD2B GND1* 8 9 GND2* *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH TCOO NGNNEDC1T IESD R. ECCOONMNMEECNTIDNEGD B. POITNH 9 TAON DG NPDIN2 1IS5 RAERCEO INMTMEERNNDAELDL.Y 08340-006 Figure 7. ADuM7442 Pin Configuration Table 22. ADuM7442 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a ceramic DD1A bypass capacitor of value 0.01 μF to 0.1 μF between V (Pin 1) and GND (Pin 2). DD1A 1 2 GND Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND is 1 1 recommended. 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Output C. OC 6 V Logic Output D. OD 7 V Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a ceramic DD1B bypass capacitor of value 0.01 μF to 0.1 μF between V (Pin 7) and GND (Pin 8). DD1B 1 8 GND Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND is 1 1 recommended. 9 GND Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND is 2 2 recommended. 10 V Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 10 must be connected externally to Pin 16. Connect a ceramic DD2B bypass capacitor of value 0.01 μF to 0.1 μF between V (Pin 10) and GND (Pin 9). DD2B 2 11 V Logic Input D. ID 12 V Logic Input C. IC 13 V Logic Output B. OB 14 V Logic Output A. OA 15 GND Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND is 2 2 recommended. 16 V Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 16 must be connected externally to Pin 10. Connect a DD2A ceramic bypass capacitor of value 0.01 μF to 0.1 μF between V (Pin 16) and GND (Pin 15). DD2A 2 Rev. D | Page 11 of 20

ADuM7440/ADuM7441/ADuM7442 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 10 35 30 8 25 A) A) 5V m 6 m NT ( 5V NT ( 20 E E R R UR 4 UR 15 C C 3V 3V 10 2 5 0 0 0 5 10DATA RA1T5E (Mbps)20 25 30 08340-015 0 5 10DATA RA1T5E (Mbps)20 25 30 08340-018 Figure 8. Typical Supply Current per Input Channel vs. Data Rate Figure 11. Typical ADuM7440 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation for 5 V and 3 V Operation 4 10 8 3 A) A) m m 6 T ( T ( 5V EN 2 EN R R UR UR 4 C 5V C 3V 1 2 3V 00 5 10DATA RA1T5E (Mbps)20 25 30 08340-016 00 5 10DATA RA1T5E (Mbps)20 25 30 08340-019 Figure 9. Typical Supply Current per Output Channel vs. Data Rate Figure 12. Typical ADuM7440 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation (No Output Load) for 5 V and 3 V Operation 4 35 30 3 25 mA) mA) CURRENT ( 2 5V CURRENT ( 1250 53VV 3V 1 10 5 00 5 10DATA RA1T5E (Mbps)20 25 30 08340-017 00 5 10DATA RA1T5E (Mbps)20 25 30 08340-020 Figure 10. Typical Supply Current per Output Channel vs. Data Rate Figure 13. Typical ADuM7441 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load) for 5 V and 3 V Operation Rev. D | Page 12 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442 10 25 8 20 A) A) m 6 m 15 NT ( 5V NT ( 5V E E R R UR 4 UR 10 C 3V C 3V 2 5 00 5 10DATA RA1T5E (Mbps)20 25 30 08340-021 00 5 10DATA RA1T5E (Mbps)20 25 30 08340-022 Figure 14. Typical ADuM7441 VDD2 Supply Current vs. Data Rate Figure 15. Typical ADuM7442 VDD1 or VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation for 5 V and 3 V Operation Rev. D | Page 13 of 20

ADuM7440/ADuM7441/ADuM7442 Data Sheet APPLICATIONS INFORMATION PRINTED CIRCUIT BOARD (PCB) LAYOUT Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single The ADuM7440/ADuM7441/ADuM7442 digital isolators ADuM7440/ADuM7441/ADuM7442 component. require no external interface circuitry for the logic interfaces. Propagation delay skew refers to the maximum amount the Power supply bypassing is strongly recommended at the input propagation delay differs between multiple ADuM7440/ and output supply pins (see Figure 16). A total of four bypass ADuM7441/ADuM7442 components operating under the capacitors should be connected between Pin 1 and Pin 2 for same conditions. V , between Pin 7 and Pin 8 for V , between Pin 9 and DD1A DD1B Pin 10 for V , and between Pin 15 and Pin 16 for V . DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY DD2B DD2A Supply V Pin 1 and V Pin 7 should be connected DD1A DD1B Positive and negative logic transitions at the isolator input cause together and supply V Pin 10 and V Pin 16 should be DD2B DD2A narrow (~1 ns) pulses to be sent to the decoder using the connected together. The capacitor values should be between transformer. The decoder is bistable and is, therefore, either set 0.01 μF and 0.1 μF. The total lead length between both ends of or reset by the pulses, indicating input logic transitions. In the the capacitor and the power supply pin should not exceed 20 mm. absence of logic transitions at the input for more than ~1 μs, a VDD1A VDD2A periodic set of refresh pulses indicative of the correct input state GNVDIA1 GVONAD2 is sent to ensure dc correctness at the output. If the decoder VIB VOB receives no internal pulses of more than approximately 5 μs, the VVIIVCDGD//VVNDOOD1BCD1 VVVGOODNDCDD2//VV2BIICD 08340-014 icwnaapsteuc htt hsdieod iges oitsil maatseosrur mcoiurectdpu tuiott. bise fuonrcpeodw teore ad doerf nauolnt fhuingchti ostnaatel, biny wthheic h Figure 16. Recommended Printed Circuit Board Layout The magnetic field immunity of the ADuM7440/ADuM7441/ In applications involving high common-mode transients, it is ADuM7442 is determined by the changing magnetic field, important to minimize board coupling across the isolation barrier. which induces a voltage in the transformer’s receiving coil large Furthermore, users should design the board layout so that any enough to either falsely set or reset the decoder. The following coupling that does occur equally affects all pins on a given analysis defines the conditions under which this can occur. The component side. Failure to ensure this can cause voltage differentials 3 V operating condition of the ADuM7440/ADuM7441/ between pins exceeding the absolute maximum ratings of the ADuM7442 is examined because it represents the most device, thereby leading to latch-up or permanent damage. susceptible mode of operation. See the AN-1109 Application Note for board layout guidelines. The pulses at the transformer output have an amplitude greater PROPAGATION DELAY-RELATED PARAMETERS than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be Propagation delay is a parameter that describes the time it takes tolerated. The voltage induced across the receiving coil is given by a logic signal to propagate through a component. The input-to- output propagation delay time for a high-to-low transition may V = (−dβ / dt) ∑ π r2; n = 1, 2, … , N n differ from the propagation delay time of a low-to-high transition. where: β is magnetic flux density (gauss). INPUT (VIx) 50% r is the radius of the nth turn in the receiving coil (cm). n t t PLH PHL N is the number of turns in the receiving coil. OUTPUT (VOx) 50% 08340-008 Given the geometry of the receiving coil in the ADuM7440/ Figure 17. Propagation Delay Parameters ADuM7441/ADuM7442 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the Pulse width distortion is the maximum difference between decoder, a maximum allowable magnetic field at a given these two propagation delay values and an indication of how frequency can be calculated. The result is shown in Figure 18. accurately the timing of the input signal is preserved. Rev. D | Page 14 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442 s) 1000 POWER CONSUMPTION s u a g k The supply current at a given channel of the ADuM7440/ X ( 100 U ADuM7441/ADuM7442 isolator is a function of the supply L F C voltage, the data rate of the channel, and the output load of the TI 10 NE channel. G A M 1 For each input channel, the supply current is given by E L WAB 0.1 IDDI = IDDI (Q) f ≤ 0.5 fr O L I = I × (2f − f) + I f > 0.5 f L DDI DDI (D) r DDI (Q) r A UM 0.01 For each output channel, the supply current is given by M XI MA 0.0011k 1M0kAGNETIC1F0I0EkLDFREQ1UMENCY(Hz)10M 100M 08340-009 IIDDDDOO == (IIDDDDOO ( (QD)) + (0.5 × 10−3) × CL × VDDO) × (2f − frf) ≤ + 0 I.D5D Ofr ( Q) Figure 18. Maximum Allowable External Magnetic Flux Density f > 0.5 fr For example, at a magnetic field frequency of 1 MHz, the where: maximum allowable magnetic field of 0.5 kgauss induces a IDDI (D), IDDO (D) are the input and output dynamic supply currents voltage of 0.25 V at the receiving coil. This is about 50% of the per channel (mA/Mbps). sensing threshold and does not cause a faulty output transition. CL is the output load capacitance (pF). Similarly, if such an event occurred during a transmitted pulse VDDO is the output supply voltage (V). (and was of the worst-case polarity), it would reduce the f is the input logic signal frequency (MHz); it is half the input received pulse from >1.0 V to 0.75 V, still well above the 0.5 V data rate, expressed in Mbps. sensing threshold of the decoder. fr is the input stage refresh rate (Mbps). I , I are the specified input and output quiescent The preceding magnetic flux density values correspond to DDI (Q) DDO (Q) supply currents (mA). specific current magnitudes at given distances from the ADuM7440/ADuM7441/ADuM7442 transformers. Figure 19 To calculate the total VDD1 and VDD2 supply current, the supply shows these allowable current magnitudes as a function of currents for each input and output channel corresponding to frequency for selected distances. As shown, the ADuM7440/ VDD1 and VDD2 are calculated and totaled. Figure 8 and Figure 9 ADuM7441/ADuM7442 are extremely immune and can be show per-channel supply currents as a function of data rate for affected only by extremely large currents operated at high an unloaded output condition. Figure 10 shows the per-channel frequency very close to the component. For the 1 MHz example supply current as a function of data rate for a 15 pF output noted previously, a 1.2 kA current would have to be placed condition. Figure 11 through Figure 15 show the total VDD1 and 5 mm away from the ADuM7440/ADuM7441/ADuM7442 to VDD2 supply current as a function of data rate for ADuM7440/ affect the operation of the component. ADuM7441/ADuM7442 channel configurations. 1000 INSULATION LIFETIME A) All insulation structures eventually break down when subjected k T ( 100 to voltage stress over a sufficiently long period. The rate of N E R insulation degradation is dependent on the characteristics of the R U E C 10 voltage waveform applied across the insulation. In addition to BL the testing performed by the regulatory agencies, Analog Devices A W carries out an extensive set of evaluations to determine the LLO 1 lifetime of the insulation structure within the ADuM7440/ A M ADuM7441/ADuM7442. U M AXI 0.1 DISTANCE=5mm Analog Devices performs accelerated life testing using voltage M DISTANCE=100mm levels higher than the rated continuous working voltage. DISTANCE=1m 0.011k 1M0kAGNETIC1F0I0EkLDFREQ1UMENCY(Hz)10M 100M 08340-010 Adectceerlmerianteiodn. Tfahcetsoer sf afcotro sresv aelrloawl o cpaelrcautliantgio cno nodf tithieo ntism aere t o Figure 19. Maximum Allowable Current for Various failure at the actual working voltage. The values shown in Current-to-ADuM7440/ADuM7441/ADuM7442 Spacings Table 18 summarize the peak voltage for 50 years of service life Note that at combinations of strong magnetic field and high for a bipolar ac operating condition and the maximum CSA frequency, any loops formed by printed circuit board traces can approved working voltages. In many cases, the approved working induce error voltages sufficiently large enough to trigger the voltage is higher than 50-year service life voltage. Operation at thresholds of succeeding circuitry. Take care in the layout of these high working voltages can lead to shortened insulation life such traces to avoid this possibility. in some cases. Rev. D | Page 15 of 20

ADuM7440/ADuM7441/ADuM7442 Data Sheet The insulation lifetime of the ADuM7440/ADuM7441/ Note that the voltage presented in Figure 21 is shown as sinusoidal ADuM7442 depends on the voltage waveform type imposed for illustration purposes only. It is meant to represent any voltage across the isolation barrier. The iCoupler insulation structure waveform varying between 0 V and some limiting value. The degrades at different rates depending on whether the waveform limiting value can be positive or negative, but the voltage cannot is bipolar ac, unipolar ac, or dc. Figure 20, Figure 21, and Figure 22 cross 0 V. illustrate these different isolation voltage waveforms. RATED PEAK VOLTAGE Bofi pao 5la0r- yaeca vr oolptaegrea tiisn tgh lei fmetoimste s turnindgeern tth een avci rboipnomlaern tc.o Tnhdeit gioona l 0V 08340-011 determines the Analog Devices recommended maximum Figure 20. Bipolar AC Waveform working voltage. In the case of unipolar ac or dc voltage, the stress on the insulation RATED PEAK VOLTAGE is significantly lower. This allows operation at higher working vvoollttaaggeess lwistheidle i nst Tilal balceh 1i8ev cianng bae 5 a0p-pyleieadr wsehrivleic me laifine.t aTihnein wg otrhkei ng 0V 08340-012 Figure 21. Unipolar AC Waveform 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage case. Any cross-insulation voltage waveform that does not conform to Figure 21 or RATED PEAK VOLTAGE Figure 22 should be treated as a bipolar ac waveform, and its vpaelauke vliosltteadg ei ns hToaubllde 1b8e. limited to the 50-year lifetime voltage 0V 08340-013 Figure 22. DC Waveform Rev. D | Page 16 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442 OUTLINE DIMENSIONS 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 16 9 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 1 8 0.236 (5.99) 0.228 (5.79) 0.010 (0.25) 0.020 (0.51) 0.065 (1.65) 0.069 (1.75) 0.006 (0.15) 0.010 (0.25) 0.049 (1.25) 0.053 (1.35) 0.010 (0.25) CO0P.0L0A4 N(0A.1R0I)TY 0.02B5S (C0.64) 0.012 (0.30) SPLEAATNIENG 80°° 0.050 (1.27) 0R.E0F41 (1.04) 0.004 (0.10) 0.016 (0.41) 0.008 (0.20) COMPLIANTTO JEDEC STANDARDS MO-137-AB C(RINEOFNPEATRRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO IPFNRFCO HINPECRSHI;A METEQIL UFLIOIVMRAE LUTEESNRET DISNI M FDOEERNSSIGIONN.S 09-12-2014-A Figure 23. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches and (millimeters) ORDERING GUIDE Number Number Maximum Maximum Maximum of Inputs, of Inputs, Data Rate Propagation Pulse Width Temperature Package Package Model1 V Side V Side (Mbps) Delay, 5 V (ns) Distortion (ns) Range Description Option DD1 DD2 ADuM7440ARQZ 4 0 1 75 25 −40°C to +105°C 16-Lead QSOP RQ-16 ADuM7440ARQZ-RL7 4 0 1 75 25 −40°C to +105°C 16-Lead QSOP, RQ-16 7” Tape and Reel ADuM7440CRQZ 4 0 25 50 5 −40°C to +105°C 16-Lead QSOP RQ-16 ADuM7440CRQZ-RL7 4 0 25 50 5 −40°C to +105°C 16-Lead QSOP, RQ-16 7” Tape and Reel ADuM7441ARQZ 3 1 1 75 25 −40°C to +105°C 16-Lead QSOP RQ-16 ADuM7441ARQZ-RL7 3 1 1 75 25 −40°C to +105°C 16-Lead QSOP, RQ-16 7” Tape and Reel ADuM7441CRQZ 3 1 25 50 5 −40°C to +105°C 16-Lead QSOP RQ-16 ADuM7441CRQZ-RL7 3 1 25 50 5 −40°C to +105°C 16-Lead QSOP, RQ-16 7” Tape and Reel ADuM7442ARQZ 2 2 1 75 25 −40°C to +105°C 16-Lead QSOP RQ-16 ADuM7442ARQZ-RL7 2 2 1 75 25 −40°C to +105°C 16-Lead QSOP, RQ-16 7” Tape and Reel ADuM7442CRQZ 2 2 25 50 5 −40°C to +105°C 16-Lead QSOP RQ-16 ADuM7442CRQZ-RL7 2 2 25 50 5 −40°C to +105°C 16-Lead QSOP, RQ-16 7” Tape and Reel 1 Z = RoHS Compliant Part. Rev. D | Page 17 of 20

ADuM7440/ADuM7441/ADuM7442 Data Sheet NOTES Rev. D | Page 18 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442 NOTES Rev. D | Page 19 of 20

ADuM7440/ADuM7441/ADuM7442 Data Sheet NOTES ©2009–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08340-0-10/15(D) Rev. D | Page 20 of 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADUM7441ARQZ-RL7 ADUM7440ARQZ-RL7 ADUM7442CRQZ-RL7 ADUM7442ARQZ ADUM7441CRQZ-RL7 ADUM7441ARQZ ADUM7440CRQZ-RL7 ADUM7440ARQZ ADUM7442CRQZ ADUM7442ARQZ-RL7 ADUM7440CRQZ ADUM7441CRQZ