Quad-Channel, 2.5 kV Isolators with Integrated DC-to-DC Converter Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404 FEATURES FUNCTIONAL BLOCK DIAGRAMS isoPower integrated, isolated dc-to-dc converter Regulated 3.3 V or 5.0 V output Up to 500 mW output power VDD1 1 OSC RECT REG 16 VISO Quad dc-to-25 Mbps (NRZ) signal isolation channels GND1 2 15 GNDISO 16-lead SOIC package with 7.6 mm creepage VIA/VOA 3 4 CHANNELiCOUPLER CORE 14 VOA/VIA High temperature operation: 105°C maximum VIB/VOB 4 13 VOB/VIB ADuM5401/ADuM5402/ High common-mode transient immunity: >25 kV/μs VIC/VOC 5 ADuM5403/ADuM5404 12 VOC/VIC Safety and regulatory approvals VOD 6 11 VID UL recognition RCOUT 7 10 VSEL CS2A5 C0o0m Vp romnse fnotr A 1c mceipntuatnec pee Nr oUtLic 1e5 57A7 GND1 8 9 GNDISO06577-001 Figure 1. VDE certificate of conformity IEC 60747-5-2 (VDE 0884, Part 2) VIA VOA 3 14 VIORM = 560 V peak VIB 4 ADuM540113VOB APPLICATIONS VIC 5 12VOC RS-232/RS-422/RS-485 transceivers VOD6 11VID 06577-100 Industrial field bus isolation Figure 2. ADuM5401 Power supply start-up bias and gate drives VIA VOA Isolated sensor interfaces VIB 3 ADuM540214VOB Industrial PLCs 4 13 VOC VIC 5 12 GThEeN AEDRuAML5 D40E1S/ACDRuIMPT5I4O02N/A DuM5403/ADuM54041 are VOD6 11VID 06577-101 Figure 3. ADuM5402 quad-channel digital isolators with isoPower®, an integrated, isolated dc-to-dc converter. Based on the Analog Devices, Inc., VIA 3 14VOA iCoupler® technology, the dc-to-dc converter provides up to VOB 4 ADuM540313VIB 500 mW of regulated, isolated power at either 5.0 V or 3.3 V VOC 5 12VIC fproowme ra l5e.v0e lVs sinhpowutn s uinp pTlayb, loer 1 a. tT 3h.3e sVe dfreovmic eas 3e.l3im Vi nsuatpep tlhy ea tn teheed VOD6 11VID 06577-102 Figure 4. ADuM5403 for a separate, isolated dc-to-dc converter in low power, isolated designs. The iCoupler chip scale transformer technology is used VOA 3 14VIA to isolate the logic signals and for the power and feedback paths VOB 4 ADuM540413VIB in the dc-to-dc converter. The result is a small form factor, total VOC VIC 5 12 isolation solution. VOD6 11VID 06577-103 The ADuM5401/ADuM5402/ADuM5403/ADuM5404 isolators Figure 5. ADuM5404 provide four independent isolation channels in a variety of Table 1. Power Levels channel configurations and data rates (see the Ordering Guide Input Voltage (V) Output Voltage (V) Output Power (mW) for more information). 5.0 5.0 500 isoPower uses high frequency switching elements to transfer 5.0 3.3 330 power through its transformer. Special care must be taken 3.3 3.3 200 during printed circuit board (PCB) layout to meet emissions standards. See the AN-0971 Application Note for board layout recommendations. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  ESD Caution................................................................................ 12  Applications ....................................................................................... 1  Pin Configurations and Function Descriptions ......................... 13  General Description ......................................................................... 1  Truth Table .................................................................................. 16  Functional Block Diagrams ............................................................. 1  Typical Performance Characteristics ........................................... 17  Revision History ............................................................................... 3  Terminology .................................................................................... 20  Specifications ..................................................................................... 4  Applications Information .............................................................. 21  Electrical Characteristics—5 V Primary Input Supply/5 V PCB Layout ................................................................................. 21  Secondary Isolated Supply .......................................................... 4  Thermal Analysis ....................................................................... 21  Electrical Characteristics—3.3 V Primary Input Supply/3.3 V Propagation Delay-Related Parameters ................................... 22  Secondary Isolated Supply .......................................................... 6  Start-Up Behavior....................................................................... 22  Electrical Characteristics—5 V Primary Input Supply/3.3 V Secondary Isolated Supply .......................................................... 8  EMI Considerations ................................................................... 22  Package Characteristics ............................................................. 10  DC Correctness and Magnetic Field Immunity .......................... 22  Regulatory Information ............................................................. 10  Power Consumption .................................................................. 23  Insulation and Safety-Related Specifications .......................... 10  Power Considerations ................................................................ 24  Increasing Available Power ....................................................... 24  IEC 60747-5-2 (VDE 0884, Part 2):2003-01 Insulation Characteristics ............................................................................ 11  Insulation Lifetime ..................................................................... 25  Recommended Operating Conditions .................................... 11  Outline Dimensions ....................................................................... 26  Absolute Maximum Ratings .......................................................... 12  Ordering Guide .......................................................................... 26  Rev. D | Page 2 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404 REVISION HISTORY 3/2019—Rev. C to Rev. D Changes to DC Correctness and Magnetic Field Immunity Change to Features Section .............................................................. 1 Section .............................................................................................. 21 Change to Table 15 .......................................................................... 10 Changes to Power Consumption Section and Figure 29 ........... 22 Changes to Power Considerations ................................................ 23 6/2012—Rev. B to Rev. C Added Increasing Available Power Section and Table 26 .......... 23 Created Hyperlink for Safety and Regulatory Approvals Added Table 27 ................................................................................ 24 Entry in Features Section ................................................................. 1 Changes to Insulation Lifetime Section ....................................... 24 Updated Outline Dimensions ........................................................ 26 11/2008—Rev. 0 to Rev. A 9/2011—Rev. A to Rev. B Changes to Figure 1 and General Description Section ................ 1 Changes to Product Title, Features Section, and General Changes to Table 1 ............................................................................ 3 Description Section ........................................................................... 1 Changes to Table 2 ............................................................................ 5 Added Table 1; Renumbered Sequentially ..................................... 1 Changes to Table 4 ............................................................................ 7 Changes to Specifications Section ................................................... 3 Changes to Table 6 and Table 7 ....................................................... 8 Changes to Table 19 and Table 20 ................................................. 11 Changes to Table 8 and Table 9 ....................................................... 9 Changes to Table 21 ........................................................................ 12 Changes to Figure 7 and Table 10 ................................................. 10 Changes to Table 22 ........................................................................ 13 Changes to Figure 8 and Table 11 ................................................. 11 Changes to Table 23 ........................................................................ 14 Changes to Figure 9 and Table 12 ................................................. 12 Changes to Table 24 and Table 25 ................................................. 15 Changes to Figure 10 and Table 13 ............................................... 13 Changes to Figure 11 to Figure 13 ................................................ 16 Moved Truth Table Section ............................................................ 13 Changes to Figure 11, Figure 12 Caption, Figure 14 Caption, Changes to Applications Information Section and PCB Layout and Figure 16 Caption .................................................................... 16 Section .............................................................................................. 17 Added Figure 19 and Figure 20; Renumbered Sequentially ...... 17 Changes to DC Correctness and Magnetic Field Immunity Changes to Figure 21 and Figure 22 ............................................. 17 Section .............................................................................................. 18 Changes to Terminology Section .................................................. 19 Changes to Power Considerations Section .................................. 20 Changes to Applications Information Section ............................ 20 Added Increasing Available Power Section, Table 15, Deleted Increasing Available Power, Figure 15, and Figure 16; and Table 16 ..................................................................................... 20 Renumbered Sequentially .............................................................. 20 Changes to PCB Layout Section .................................................... 20 5/2008—Revision 0: Initial Version Added Start-Up Behavior Section ................................................. 21 Moved and Changes to EMI Considerations Section ................ 21 Rev. D | Page 3 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY Typical specifications are at T = 25°C, V = V = V = 5 V. Minimum/maximum specifications apply over the entire recommended A DD1 SEL ISO operation range which is 4.5 V ≤ V , V , V ≤ 5.5 V; and −40°C ≤ T ≤ +105°C, unless otherwise noted. Switching specifications are DD1 SEL ISO A tested with C = 15 pF and CMOS signal levels, unless otherwise noted. L Table 2. DC-to-DC Converter Static Specifications Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC-TO-DC CONVERTER SUPPLY Setpoint V 4.7 5.0 5.4 V I = 0 mA ISO ISO Line Regulation V 1 mV/V I = 50 mA, V = 4.5 V to 5.5 V ISO (LINE) ISO DD1 Load Regulation V 1 5 % I = 10 mA to 90 mA ISO (LOAD) ISO Output Ripple V 75 mV p-p 20 MHz bandwidth, C = 0.1 μF||10 μF, I = 90 mA ISO (RIP) BO ISO Output Noise V 200 mV p-p C = 0.1 μF||10 μF, I = 90 mA ISO (NOISE) BO ISO Switching Frequency f 180 MHz OSC PWM Frequency f 625 kHz PWM Output Supply Current I 100 mA V > 4.5 V ISO (MAX) ISO Efficiency at I 34 % I = 100 mA ISO (MAX) ISO I , No V Load I 19 30 mA DD1 ISO DD1 (Q) I , Full V Load I 290 mA DD1 ISO DD1 (MAX) Table 3. DC-to-DC Converter Dynamic Specifications 1 Mbps—A Grade, C Grade 25 Mbps—C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments SUPPLY CURRENT Input I DD1 ADuM5401 19 68 mA No V load ISO ADuM5402 19 71 mA No V load ISO ADuM5403 19 75 mA No V load ISO ADuM5404 19 78 mA No V load ISO Available to Load I ISO (LOAD) ADuM5401 100 87 mA ADuM5402 100 85 mA ADuM5403 100 83 mA ADuM5404 100 81 mA Table 4. Switching Specifications A Grade C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS Data Rate 1 25 Mbps Within PWD limit Propagation Delay t , t 55 100 45 60 ns 50% input to 50% output PHL PLH Pulse Width Distortion PWD 40 6 ns |t − t | PLH PHL Change vs. Temperature 5 ps/°C Pulse Width PW 1000 40 ns Within PWD limit Propagation Delay Skew t 50 15 ns Between any two units PSK Channel Matching Codirectional1 t 50 6 ns PSKCD Opposing Directional2 t 50 15 ns PSKOD 1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation 7 barrier. 2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. Rev. D | Page 4 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404 Table 5. Input and Output Characteristics Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Logic High Input Threshold V 0.7 × V or 0.7 × V V IH ISO DD1 Logic Low Input Threshold V 0.3 × V or 0.3 × V IL ISO V DD1 Logic High Output Voltages V V − 0.3 or V − 0.3 5.0 V I = −20 μA, V = V OH DD1 ISO Ox Ix IxH V − 0.5 or V − 0.5 4.8 V I = −4 mA, V = V DD1 ISO Ox Ix IxH Logic Low Output Voltages V 0.0 0.1 V I = 20 μA, V = V OL Ox Ix IxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL Undervoltage Lockout UVLO V , V , V supplies DD1 DDL ISO Positive Going Threshold V 2.7 V UV+ Negative Going Threshold V 2.4 V UV− Hysteresis V 0.3 V UVH Input Currents per Channel I −20 +0.01 +20 μA 0 V ≤ V ≤ V I Ix DDx AC SPECIFICATIONS Output Rise/Fall Time t/t 2.5 ns 10% to 90% R F Common-Mode Transient |CM| 25 35 kV/μs V = V or V , V = 1000 V, Ix DD1 ISO CM Immunity1 transient magnitude = 800 V Refresh Rate f 1.0 Mbps r 1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. D | Page 5 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY Typical specifications are at T = 25°C, V = V = 3.3 V, V = GND . Minimum/maximum specifications apply over the entire A DD1 ISO SEL ISO recommended operation range which is 3.0 V ≤ V , V , V ≤ 3.6 V; and −40°C ≤ T ≤ +105°C, unless otherwise noted. Switching DD1 SEL ISO A specifications are tested with C = 15 pF and CMOS signal levels, unless otherwise noted. L Table 6. DC-to-DC Converter Static Specifications Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC-TO-DC CONVERTER SUPPLY Setpoint V 3.0 3.3 3.6 V I = 0 mA ISO ISO Line Regulation V 1 mV/V I = 30 mA, V = 3.0 V to 3.6 V ISO (LINE) ISO DD1 Load Regulation V 1 5 % I = 6 mA to 54 mA ISO (LOAD) ISO Output Ripple V 50 mV p-p 20 MHz bandwidth, C = 0.1 μF||10 μF, I = 54 mA ISO (RIP) BO ISO Output Noise V 130 mV p-p C = 0.1 μF||10 μF, I = 54 mA ISO (NOISE) BO ISO Switching Frequency f 180 MHz OSC PWM Frequency f 625 kHz PWM Output Supply Current I 60 mA V > 3 V ISO (MAX) ISO Efficiency at I 33 % I = 60 mA ISO (MAX) ISO I , No V Load I 14 20 mA DD1 ISO DD1 (Q) I , Full V Load I 175 mA DD1 ISO DD1 (MAX) Table 7. DC-to-DC Converter Dynamic Specifications 1 Mbps—A or C Grade 25 Mbps—C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments SUPPLY CURRENT Input I DD1 ADuM5401 14 44 mA No V load ISO ADuM5402 14 46 mA No V load ISO ADuM5403 14 47 mA No V load ISO ADuM5404 14 51 mA No V load ISO Available to Load I ISO (LOAD) ADuM5401 60 52 mA ADuM5402 60 51 mA ADuM5403 60 49 mA ADuM5404 60 48 mA Table 8. Switching Specifications A Grade C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS Data Rate 1 25 Mbps Within PWD limit Propagation Delay t , t 60 100 45 60 ns 50% input to 50% output PHL PLH Pulse Width Distortion PWD 40 6 ns |t − t | PLH PHL Change vs. Temperature 5 ps/°C Pulse Width PW 1000 40 ns Within PWD limit Propagation Delay Skew t 50 45 ns Between any two units PSK Channel Matching Codirectional1 t 50 6 ns PSKCD Opposing Directional2 t 50 15 ns PSKOD 1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation 7 barrier. 2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. Rev. D | Page 6 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404 Table 9. Input and Output Characteristics Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Logic High Input Threshold V 0.7 × V or 0.7 × V V IH ISO DD1 Logic Low Input Threshold V 0.3 × V or 0.3 × V IL ISO V DD1 Logic High Output Voltages V V − 0.3 or V − 0.3 3.3 V I = −20 μA, V = V OH DD1 ISO Ox Ix IxH V − 0.5 or V − 0.5 3.1 V I = −4 mA, V = V DD1 ISO Ox Ix IxH Logic Low Output Voltages V 0.0 0.1 V I = 20 μA, V = V OL Ox Ix IxL 0.0 0.4 V I = 4 mA, V = V Ox Ix IxL Undervoltage Lockout UVLO V , V , V supplies DD1 DDL ISO Positive Going Threshold V 2.7 V UV+ Negative Going Threshold V 2.4 V UV− Hysteresis V 0.3 V UVH Input Currents per Channel I −10 +0.01 +10 μA 0 V ≤ V ≤ V I Ix DDx AC SPECIFICATIONS Output Rise/Fall Time t/t 2.5 ns 10% to 90% R F Common-Mode Transient |CM| 25 35 kV/μs V = V or V , V = 1000 V, Ix DD1 ISO CM Immunity1 transient magnitude = 800 V Refresh Rate f 1.0 Mbps r 1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. D | Page 7 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY Typical specifications are at T = 25°C, V = 5.0 V, V = 3.3 V, V = GND . Minimum/maximum specifications apply over the entire A DD1 ISO SEL ISO recommended operation range which is 4.5 V ≤ V ≤ 5.5 V, 3.0 V ≤ V ≤ 3.6 V; and −40°C ≤ T ≤ +105°C, unless otherwise noted. DD1 ISO A Switching specifications are tested with C = 15 pF and CMOS signal levels, unless otherwise noted. L Table 10. DC-to-DC Converter Static Specifications Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC-TO-DC CONVERTER SUPPLY Setpoint V 3.0 3.3 3.6 V I = 0 mA ISO ISO Line Regulation V 1 mV/V I = 50 mA, V = 3.0 V to 3.6 V ISO (LINE) ISO DD1 Load Regulation V 1 5 % I = 6 mA to 54 mA ISO (LOAD) ISO Output Ripple V 50 mV p-p 20 MHz bandwidth, C = 0.1 μF||10 μF, I = 90 mA ISO (RIP) BO ISO Output Noise V 130 mV p-p C = 0.1 μF||10 μF, I = 90 mA ISO (NOISE) BO ISO Switching Frequency f 180 MHz OSC PWM Frequency f 625 kHz PWM Output Supply Current I 100 mA V > 3 V ISO (MAX) ISO Efficiency at I 30 % I = 90 mA ISO (MAX) ISO I , No V Load I 14 20 mA DD1 ISO DD1 (Q) I , Full V Load I 230 mA DD1 ISO DD1 (MAX) Table 11. DC-to-DC Converter Dynamic Specifications 1 Mbps—A or C Grade 25 Mbps—C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments SUPPLY CURRENT Input I DD1 ADuM5401 9 44 mA No V load ISO ADuM5402 9 45 mA No V load ISO ADuM5403 9 46 mA No V load ISO ADuM5404 9 47 mA No V load ISO Available to Load I ISO (LOAD) ADuM5401 100 92 mA ADuM5402 100 91 mA ADuM5403 100 89 mA ADuM5404 100 88 mA Table 12. Switching Specifications A Grade C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS Data Rate 1 25 Mbps Within PWD limit Propagation Delay t , t 60 100 45 60 ns 50% input to 50% output PHL PLH Pulse Width Distortion PWD 40 6 ns |t − t | PLH PHL Change vs. Temperature 5 ps/°C Pulse Width PW 1000 40 ns Within PWD limit Propagation Delay Skew t 50 15 ns Between any two units PSK Channel Matching Codirectional1 t 50 6 ns PSKCD Opposing Directional2 t 50 15 ns PSKOD 1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. Rev. D | Page 8 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404 Table 13. Input and Output Characteristics Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Logic High Input Threshold V 0.7 × V or 0.7 × V IH ISO V DD1 Logic Low Input Threshold V 0.3 × V or 0.3 × V IL ISO V DD1 Logic High Output Voltages V V − 0.2, V − 0.2 V or V V I = −20 μA, V = V OH DD1 ISO DD1 ISO Ox Ix IxH V − 0.5 or V − 0.2 or V I = −4 mA, V = V DD1 DD1 Ox Ix IxH V − 0.5 V − 0.2 ISO ISO Logic Low Output Voltages V 0.0 0.1 V I = 20 μA, V = V OL Ox Ix IxL 0.0 0.4 V I = 4 mA, V = V Ox Ix IxL Undervoltage Lockout UVLO V , V , V supplies DD1 DDL ISO Positive Going Threshold V 2.7 V UV+ Negative Going Threshold V 2.4 V UV− Hysteresis V 0.3 V UVH Input Currents per Channel I −10 +0.01 +10 μA 0 V ≤ V ≤ V I Ix DDx AC SPECIFICATIONS Output Rise/Fall Time t/t 2.5 ns 10% to 90% R F Common-Mode Transient |CM| 25 35 kV/μs V = V or V , V = 1000 V, Ix DD1 ISO CM Immunity1 transient magnitude = 800 V Refresh Rate f 1.0 Mbps r 1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. D | Page 9 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet PACKAGE CHARACTERISTICS Table 14. Parameter Symbol Min Typ Max Unit Test Conditions/Comments RESISTANCE AND CAPACITANCE Resistance (Input-to-Output)1 R 1012 Ω I-O Capacitance (Input-to-Output)1 C 2.2 pF f = 1 MHz I-O Input Capacitance2 C 4.0 pF I IC Junction-to-Ambient Thermal θ 45 °C/W Thermocouple located at center of package underside, JA Resistance test conducted on 4-layer board with thin traces3 1 This device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. 2 Input capacitance is from any input data pin to ground. 3 See the Thermal Analysis section for thermal model definitions. REGULATORY INFORMATION The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are approved by the organizations listed in Table 15. Refer to Table 20 and the Insulation Lifetime section for more information about the recommended maximum working voltages for specific cross-insulation waveforms and insulation levels. Table 15. UL1 CSA VDE2 Recognized Under 1577 Component Approved under CSA Component Certified according to IEC 60747-5-2 Recognition Program1 Acceptance Notice 5A (VDE 0884 Part 2):2003-012 Single Protection, 2500 V rms Testing was conducted per CSA 60950-1-07 Basic insulation, 560 V peak Isolation Voltage and IEC 60950-1 2nd Ed. at 2.5 kV rated voltage Basic insulation at 600 V rms (848 V peak) working voltage Reinforced insulation at 250 V rms (353 V peak) working voltage File E214100 File 205078 File 2471900-4880-0001 1 In accordance with UL 1577, each ADuM5401/ADuM5402/ADuM5403/ADuM5404 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 10 μA). 2 In accordance with IEC 60747-5-2 (VDE 0884 Part 2):2003-01, each ADuM5401/ADuM5402/ADuM5403/ADuM5404 is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates IEC 60747-5-2 (VDE 0884 Part 2):2003-01 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 16. Critical Safety-Related Dimensions and Material Properties Parameter Symbol Value Unit Test Conditions/Comments Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Distance L(I01) 8.0 mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 7.6 mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.017 min mm Distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303, Part 1 Material Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Rev. D | Page 10 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404 IEC 60747-5-2 (VDE 0884, PART 2):2003-01 INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by the protective circuits. The asterisk (*) marking branded on the package denotes IEC 60747-5-2 (VDE 0884, Part 2) approval. Table 17. VDE Characteristics Description Conditions Symbol Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V 560 V peak IORM Input-to-Output Test Voltage, Method b1 V × 1.875 = V , 100% production test, t = 1 sec, V 1050 V peak IORM PR m PR partial discharge < 5 pC Input-to-Output Test Voltage, Method a V PR After Environmental Tests Subgroup 1 V × 1.6 = V , t = 60 sec, partial discharge < 5 pC 896 V peak IORM PR m After Input and/or Safety Test Subgroup 2 V × 1.2 = V , t = 60 sec, partial discharge < 5 pC 672 V peak IORM PR m and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, t = 10 sec V 4000 V peak TR TR Safety Limiting Values Maximum value allowed in the event of a failure (see Figure 6) Case Temperature T 150 °C S Side 1 I Current I 555 mA DD1 S1 Insulation Resistance at T V = 500 V R >109 Ω S IO S 600 A) m500 T ( N E R R400 U C D1 VD300 G N TI RA200 E P O E F100 A S 00 50AMBIENT TEM1P00ERATURE (°C1)50 200 06577-002 Figure 6. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2 RECOMMENDED OPERATING CONDITIONS Table 18. Parameter Symbol Min Max Unit Operating Temperature1 T −40 +105 °C A Supply Voltages2 V @ V = 0 V V 3.0 5.5 V DD1 SEL DD V @ V = V V 4.5 5.5 V DD1 SEL ISO DD 1 Operation at 105°C requires reduction of the maximum load current as specified in Table 19. 2 Each voltage is relative to its respective ground. Rev. D | Page 11 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 19. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational Storage Temperature Range (T ) −55°C to +150°C ST section of this specification is not implied. Operation beyond Ambient Operating Temperature −40°C to +105°C the maximum operating conditions for extended periods may Range (T ) A affect product reliability. Supply Voltages (V , V )1 −0.5 V to +7.0 V DD1 ISO Input Voltage (V , V , V , V , V )1, 2 −0.5 V to V + 0.5 V ESD CAUTION IA IB IC ID SEL DDI Output Voltage (V , V , V , V )1, 2 −0.5 V to V + 0.5 V OA OB OC OD DDO Average Output Current per Pin3 −10 mA to +10 mA Common-Mode Transients4 −100 kV/μs to +100 kV/μs 1 Each voltage is relative to its respective ground. 2 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PCB Layout section. 3 See Figure 6 for maximum rated current values for various temperatures. 4 Common-mode transients exceeding the absolute maximum slew rate may cause latch-up or permanent damage. Table 20. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime1 Parameter Max Unit Applicable Certification AC Voltage, Bipolar Waveform 424 V peak All certifications, 50-year operation AC Voltage, Unipolar Waveform Basic Insulation 600 V peak Working voltage per IEC 60950-1 Reinforced Insulation 353 V peak Working voltage per IEC 60950-1 DC Voltage Basic Insulation 600 V peak Working voltage per IEC 60950-1 Reinforced Insulation 353 V peak Working voltage per IEC 60950-1 1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information. Rev. D | Page 12 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1 1 16 VISO GND1 2 15 GNDISO VIA 3 ADuM5401 14 VOA VIB 4 TOP VIEW 13 VOB VIC 5 (Not to Scale) 12 VOC VOD 6 11 VID RGCNODUT1 87 190 VGSNEDLISO06577-004 Figure 7. ADuM5401 Pin Configuration Table 21. ADuM5401 Pin Function Descriptions Pin No. Mnemonic Description 1 V Primary Supply Voltage, 3.0 V to 5.5 V. DD1 2, 8 GND Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that 1 both pins be connected to a common ground. 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Input C. IC 6 V Logic Output D. OD 7 RCOUT Regulation Control Output. This pin is connected to the RCIN pin of a slave isoPower device to allow the ADuM5401 to control the regulation of the slave device. 9, 15 GND Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins ISO be connected to a common ground. 10 V Output Voltage Selection. When V = V , the V setpoint is 5.0 V. When V = GND , the V setpoint is 3.3 V. SEL SEL ISO ISO SEL ISO ISO 11 V Logic Input D. ID 12 V Logic Output C. OC 13 V Logic Output B. OB 14 V Logic Output A. OA 16 V Secondary Supply Voltage Output for External Loads, 3.3 V (V Low) or 5.0 V (V High). ISO SEL SEL Rev. D | Page 13 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet VDD1 1 16 VISO GND1 2 15 GNDISO VIA 3 ADuM5402 14 VOA VIB 4 TOP VIEW 13 VOB VOC 5 (Not to Scale) 12 VIC VOD 6 11 VID RGCNODUT1 87 190 VGSNEDLISO06577-005 Figure 8. ADuM5402 Pin Configuration Table 22. ADuM5402 Pin Function Descriptions Pin No. Mnemonic Description 1 V Primary Supply Voltage, 3.0 V to 5.5 V. DD1 2, 8 GND Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that 1 both pins be connected to a common ground. 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Output C. OC 6 V Logic Output D. OD 7 RCOUT Regulation Control Output. This pin is connected to the RCIN pin of a slave isoPower device to allow the ADuM5402 to control the regulation of the slave device. 9, 15 GND Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins ISO be connected to a common ground. 10 V Output Voltage Selection. When V = V , the V setpoint is 5.0 V. When V = GND , the V setpoint is 3.3 V. SEL SEL ISO ISO SEL ISO ISO 11 V Logic Input D. ID 12 V Logic Input C. IC 13 V Logic Output B. OB 14 V Logic Output A. OA 16 V Secondary Supply Voltage Output for External Loads, 3.3 V (V Low) or 5.0 V (V High). ISO SEL SEL Rev. D | Page 14 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404 VDD1 1 16 VISO GND1 2 15 GNDISO VIA 3 ADuM5403 14 VOA VOB 4 TOP VIEW 13 VIB VOC 5 (Not to Scale) 12 VIC VOD 6 11 VID RGCNODUT1 87 190 VGSNEDLISO06577-006 Figure 9. ADuM5403 Pin Configuration Table 23. ADuM5403 Pin Function Descriptions Pin No. Mnemonic Description 1 V Primary Supply Voltage, 3.0 V to 5.5 V. DD1 2, 8 GND Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that 1 both pins be connected to a common ground. 3 V Logic Input A. IA 4 V Logic Output B. OB 5 V Logic Output C. OC 6 V Logic Output D. OD 7 RCOUT Regulation Control Output. This pin is connected to the RCIN pin of a slave isoPower device to allow the ADuM5403 to control the regulation of the slave device. 9, 15 GND Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins ISO be connected to a common ground. 10 V Output Voltage Selection. When V = V , the V setpoint is 5.0 V. When V = GND , the V setpoint is 3.3 V. SEL SEL ISO ISO SEL ISO ISO 11 V Logic Input D. ID 12 V Logic Input C. IC 13 V Logic Input B. IB 14 V Logic Output A. OA 16 V Secondary Supply Voltage Output for External Loads, 3.3 V (V Low) or 5.0 V (V High). ISO SEL SEL Rev. D | Page 15 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet VDD1 1 16 VISO GND1 2 15 GNDISO VOA 3 ADuM5404 14 VIA VOB 4 TOP VIEW 13 VIB VOC 5 (Not to Scale) 12 VIC VOD 6 11 VID RGCNODUT1 87 190 VGSNEDLISO06577-007 Figure 10. ADuM5404 Pin Configuration Table 24. ADuM5404 Pin Function Descriptions Pin No. Mnemonic Description 1 V Primary Supply Voltage, 3.0 V to 5.5 V. DD1 2, 8 GND Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended 1 that both pins be connected to a common ground. 3 V Logic Output A. OA 4 V Logic Output B. OB 5 V Logic Output C. OC 6 V Logic Output D. OD 7 RCOUT Regulation Control Output. This pin is connected to the RCIN pin of a slave isoPower device to allow the ADuM5404 to control the regulation of the slave device. 9, 15 GND Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both ISO pins be connected to a common ground. 10 V Output Voltage Selection. When V = V , the V setpoint is 5.0 V. When V = GND , the V setpoint is 3.3 V. SEL SEL ISO ISO SEL ISO ISO 11 V Logic Input D. ID 12 V Logic Input C. IC 13 V Logic Input B. IB 14 V Logic Input A. IA 16 V Secondary Supply Voltage Output for External Loads, 3.3 V (V Low) or 5.0 V (V High). ISO SEL SEL TRUTH TABLE Table 25. Truth Table (Positive Logic) V 1 RC 2 V (V) V (V) Notes SEL OUT DD1 ISO H PWM 5 5 Master mode, normal operation L PWM 5 3.3 Master mode, normal operation L PWM 3.3 3.3 Master mode, normal operation H PWM 3.3 5 This supply configuration is not recommended due to extremely poor efficiency 1 H refers to a high logic, and L refers to a low logic. 2 PWM refers to the regulation control signal. This signal is derived from the secondary side regulator and can be used to control other isoPower devices. Rev. D | Page 16 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404 TYPICAL PERFORMANCE CHARACTERISTICS 40 4.0 4.0 35 3.5 3.5 POWER 30 3.0 3.0 %) (A) EFFICIENCY (122505 PUTCURRENT122...550 212...055 POWER(W) N I 10 1.0 1.0 IDD 5 3.3V INPUT/3.3V OUTPUT 0.5 0.5 5V INPUT/3.3V OUTPUT 5V INPUT/5V OUTPUT 00 0.02 0.O0U4TPUT 0C.U06RRENT 0(A.0)8 0.10 0.12 06577-033 03.0 3.5 I4N.0PUTSU4.P5PLYVO5.L0TAGE5(V.5) 6.0 6.50 06577-011 Figure 11. Typical Power Supply Efficiency at 5 V Input/5 V Output Figure 14. Typical Short-Circuit Input Current and Power and 3.3 V Input/3.3 V Output vs. VDD1 Supply Voltage 1.0 E G 0.9 TAV) 0.8 VOLV/DI N (W)0.7 TPUT (500m O U TI0.6 O A P SI0.5 S 10% LOAD 90% LOAD DI D ER 0.4 OA POW0.3 MIC L A 0.2 N 0.1 VVVDDDDDD111=== 553.VV3,,V VV, IIVSSOOISO== =53 V.33.V3V DY 06577-012 00 0.02 0.04 IIS0O.0 (6A) 0.08 0.10 0.12 06577-026 (100µs/DIV) Figure 12. Typical Total Power Dissipation vs. Isolated Output Supply Current Figure 15. Typical VISO Transient Load Response, 5 V Output, in All Supported Power Configurations 10% to 90% Load Step 0.12 E G TAV) 0.10 VOLV/DI RENT (A)0.08 OUTPUT (500m R U C0.06 T U D P A T O OU 0.04 C L 10% LOAD 90% LOAD MI A N 0.02 355.VV3 VIINN IPPNUUPTTU//T35/.V33 .VO3 VUO TUOPTUUPTTUPTUT DY 06577-013 00 0.05 0.10 INPU0.T1 5CURR0E.2N0T (A)0.25 0.30 0.35 06577-027 (100µs/DIV) Figure 13. Typical Isolated Output Supply Current vs. Input Current Figure 16. Typical VISO Transient Load Response, 3.3 V Output, in All Supported Power Configurations 10% to 90% Load Step Rev. D | Page 17 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet 5 DIV) 4 10% LOAD V/ m 0 1 E ( 3 RIPPL (V)SO 90% LOAD T VI PU 2 T U O V 5 1 BW = 20MHz (400ns/DIV) 06577-014 0 06577-031 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 TIME (ms) Figure 17. Typical VISO = 5 V Output Voltage Ripple at 90% Load Figure 20. Typical Output Voltage Start-Up Transient at 10% and 90% Load, VISO = 3.3 V 20 5V INPUT/5V OUTPUT 3.3V INPUT/3.3V OUTPUT 5V INPUT/3.3V OUTPUT V) 16 mV/DI mA) E (10 ENT ( 12 L R RIPP CUR UT LY 8 P P T P U U O S V 3.3 4 BW = 20MHz (400ns/DIV) 06577-015 00 5 DA1T0A RATE (Mb1p5s) 20 25 06577-028 Figure 18. Typical VISO = 3.3 V Output Voltage Ripple at 90% Load Figure 21. Typical ICH Supply Current per Forward Data Channel (15 pF Output Load) 7 20 10% LOAD 5V INPUT/5V OUTPUT 3.3V INPUT/3.3V OUTPUT 6 5V INPUT/3.3V OUTPUT 16 5 A) m T ( N 12 (V)SO 4 90% LOAD URRE VI 3 LY C 8 P P 2 SU 4 1 0–1 0 TIME1 (ms) 2 306577-030 00 5 DA1T0A RATE (M1b5ps) 20 2506577-029 Figure 19. Typical Output Voltage Start-Up Transient Figure 22. Typical ICH Supply Current per Reverse Data Channel at 10% and 90% Load, VISO = 5 V (15 pF Output Load) Rev. D | Page 18 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404 5 3.0 2.5 4 A) A) NT(m 3 NT(m2.0 RE RE CUR 5V CUR1.5 5V UPPLY 2 UPPLY1.0 S 3.3V S 3.3V 1 0.5 00 5 DA1T0ARATE(M1b5ps) 20 25 06577-119 00 5 DA1T0ARATE(Mb1p5s) 20 25 06577-118 Figure 23. Typical IISO (D) Dynamic Supply Current per Input Figure 24. Typical IISO (D) Dynamic Supply Current per Output (15 pF Output Load) Rev. D | Page 19 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet TERMINOLOGY IDD1 (Q) tPLH Propagation Delay IDD1 (Q) is the minimum operating current drawn at the VDD1 tPLH propagation delay is measured from the 50% level of the pin when there is no external load at VISO and the I/O pins are rising edge of the VIx signal to the 50% level of the rising edge operating below 2 Mbps, requiring no additional dynamic supply of the V signal. Ox current. I reflects the minimum current operating condition. DD1 (Q) Propagation Delay Skew, t PSK IDD1 (D) tPSK is the magnitude of the worst-case difference in tPHL and/or IDD1 (D) is the typical input supply current with all channels tPLH that is measured between units at the same operating temper- simultaneously driven at a maximum data rate of 25 Mbps ature, supply voltages, and output load within the recommended with full capacitive load representing the maximum dynamic operating conditions. load conditions. Resistive loads on the outputs should be Channel-to-Channel Matching, (t /t ) PSKCD PSKOD treated separately from the dynamic load. Channel-to-channel matching is the absolute value of the IDD1 (MAX) difference in propagation delays between two channels when IDD1 (MAX) is the input current under full dynamic and VISO load operated with identical loads. conditions. Minimum Pulse Width ISO (LOAD) The minimum pulse width is the shortest pulse width at which ISO (LOAD) is the current available to the load. the specified pulse width distortion is guaranteed. tPHL Propagation Delay Maximum Data Rate The tPHL propagation delay is measured from the 50% level of The maximum data rate is the fastest data rate at which the the falling edge of the VIx signal to the 50% level of the falling specified pulse width distortion is guaranteed. edge of the V signal. Ox Rev. D | Page 20 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404 APPLICATIONS INFORMATION The dc-to-dc converter section of the ADuM5401/ADuM5402/ BYPASS < 2mm ADuM5403/ADuM5404 works on principles that are common to VDD1 VISO GND1 GNDISO most switching power supplies. It has a secondary side controller VIA/VOA VOA/VIA architecture with isolated pulse-width modulation (PWM) VIB/VOB VOB/VIB feedback. VDD1 power is supplied to an oscillating circuit that VIC/VOC VOC/VIC switches current into a chip scale air core transformer. Power VOD VID teritahnesrf e3r.3re Vd otor 5th Ve. sTehceo nsedcaornyd sairdye (iVs IrSeO)c tsiifdieed c oanntdro rlelegru rleagteudla ttoes RGCNODUT1 VGSNEDLISO 06577-120 the output by creating a PWM control signal that is sent to the Figure 25. Recommended PCB Layout primary (V ) side by a dedicated iCoupler data channel. The DD1 In applications involving high common-mode transients, ensure PWM modulates the oscillator circuit to control the power being that board coupling across the isolation barrier is minimized. sent to the secondary side. Feedback allows for significantly higher Furthermore, design the board layout such that any coupling that power and efficiency. does occur affects all pins equally on a given component side. The ADuM5401/ADuM5402/ADuM5403/ADuM5404 implement Failure to ensure this can cause voltage differentials between undervoltage lockout (UVLO) with hysteresis on the V power pins exceeding the absolute maximum ratings for the device DD1 input. This feature ensures that the converter does not enter as specified in Table 19, thereby leading to latch-up and/or oscillation due to noisy input power or slow power-on ramp rates. permanent damage. PCB LAYOUT The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are power devices that dissipate approximately 1 W of power when fully The ADuM5401/ADuM5402/ADuM5403/ADuM5404 digital loaded and running at maximum speed. Because it is not possible isolators with 0.5 W isoPower integrated dc-to-dc converter to apply a heat sink to an isolation device, the devices primarily require no external interface circuitry for the logic interfaces. depend on heat dissipation into the PCB through the GND Power supply bypassing is required at the input and output pins. If the devices are used at high ambient temperatures, provide supply pins (see Figure 25). Note that low ESR bypass capacitors a thermal path from the GND pins to the PCB ground plane. are required between Pin 1 and Pin 2 and between Pin 15 and The board layout in Figure 25 shows enlarged pads for Pin 8 and Pin 16, as close to the chip pads as possible. Pin 9. Large diameter vias should be implemented from the pad to The power supply section of the ADuM5401/ADuM5402/ the ground, and power planes should be used to reduce inductance. ADuM5403/ADuM5404 uses a 180 MHz oscillator frequency Multiple vias should be implemented from the pad to the ground to pass power efficiently through its chip scale transformers. In plane to significantly reduce the temperature inside the chip. addition, the normal operation of the data section of the iCoupler The dimensions of the expanded pads are at the discretion of introduces switching transients on the power supply pins. Bypass the designer and depend on the available board space. capacitors are required for several operating frequencies. Noise THERMAL ANALYSIS suppression requires a low inductance, high frequency capacitor; ripple suppression and proper regulation require a large value The ADuM5401/ADuM5402/ADuM5403/ADuM5404 devices capacitor. These are most conveniently connected between Pin 1 consist of four internal die attached to a split lead frame with two and Pin 2 for V and between Pin 15 and Pin 16 for V . die attach paddles. For the purposes of thermal analysis, the die DD1 ISO is treated as a thermal unit, with the highest junction temperature To suppress noise and reduce ripple, a parallel combination of reflected in the θ from Table 14. The value of θ is based on at least two capacitors is required. The recommended capacitor JA JA measurements taken with the devices mounted on a JEDEC values are 0.1 μF and 10 μF for V and V . The smaller DD1 ISO standard, 4-layer board with fine width traces and still air. capacitor must have a low ESR; for example, use of a ceramic Under normal operating conditions, the ADuM5401/ADuM5402/ capacitor is advised. ADuM5403/ ADuM5404 devices operate at full load across the The total lead length between the ends of the low ESR capacitor full temperature range without derating the output current. and the input power supply pin must not exceed 2 mm. Installing However, following the recommendations in the PCB Layout the bypass capacitor with traces more than 2 mm in length may section decreases thermal resistance to the PCB, allowing result in data corruption. Consider bypassing between Pin 1 and increased thermal margins in high ambient temperatures. Pin 8 and between Pin 9 and Pin 16 unless both common ground pins are connected together close to the package. Rev. D | Page 21 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet PROPAGATION DELAY-RELATED PARAMETERS As a result, the ADuM5401/ADuM5402/ADuM5403/ADuM5404 devices can draw large amounts of current at low voltage for Propagation delay is a parameter that describes the time it takes extended periods of time. a logic signal to propagate through a component (see Figure 26). The propagation delay to a logic low output may differ from the The output voltage of the ADuM5401/ADuM5402/ADuM5403/ propagation delay to a logic high. ADuM5404 devices exhibits V overshoot during startup. If ISO this overshoot could potentially damage components attached INPUT (VIx) 50% to V , a voltage-limiting device such as a Zener diode can be ISO tPLH tPHL used to clamp the voltage. Typical behavior is shown in Figure 19 OUTPUT (VOx) 50% 06577-018 aEnMd IF CigOurNe S20ID. ERATIONS Figure 26. Propagation Delay Parameters The dc-to-dc converter section of the ADuM5401/ADuM5402/ Pulse width distortion is the maximum difference between ADuM5403/ADuM5404 devices must operate at 180 MHz to these two propagation delay values and is an indication of allow efficient power transfer through the small transformers. how accurately the input signal timing is preserved. This creates high frequency currents that can propagate in circuit Channel-to-channel matching refers to the maximum amount board ground and power planes, causing edge emissions and the propagation delay differs between channels within a single dipole radiation between the primary and secondary ground ADuM5401/ADuM5402/ADuM5403/ADuM5404 component. planes. Grounded enclosures are recommended for applications Propagation delay skew refers to the maximum amount the that use these devices. If grounded enclosures are not possible, propagation delay differs between multiple ADuM5401/ follow good RF design practices in the layout of the PCB. See the ADuM5402/ADuM5403/ADuM5404 components operating AN-0971 Application Note for board layout recommendations under the same conditions. DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY START-UP BEHAVIOR Positive and negative logic transitions at the isolator input cause The ADuM5401/ADuM5402/ADuM5403/ADuM5404 do not narrow (~1 ns) pulses to be sent to the decoder via the transformer. contain a soft start circuit. Therefore, the start-up current and The decoder is bistable and is, therefore, either set or reset by the voltage behavior must be taken into account when designing pulses, indicating input logic transitions. In the absence of logic with this device. transitions at the input for more than 1 μs, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc When power is applied to V , the input switching circuit begins DD1 correctness at the output. If the decoder receives no internal pulses to operate and draw current when the UVLO minimum voltage for more than approximately 5 μs, the input side is assumed to is reached. The switching circuit drives the maximum available be unpowered or nonfunctional, and the isolator output is forced to power to the output until it reaches the regulation voltage where a default low state by the watchdog timer circuit. This situation PWM control begins. The amount of current and the time should occur in the ADuM5401/ADuM5402/ADuM5403/ required to reach regulation voltage depends on the load and ADuM5404 during power-up and power-down operations. the V slew rate. DD1 The limitation on the magnetic field immunity of the With a fast V slew rate (200 μs or less), the peak current draws DD1 ADuM5401/ADuM5402/ADuM5403/ADuM5404 is set by the up to 100 mA/V of V . The input voltage goes high faster than DD1 condition in which induced voltage in the receiving coil of the the output can turn on, so the peak current is proportional to transformer is sufficiently large to either falsely set or reset the the maximum input voltage. decoder. The following analysis defines the conditions under With a slow VDD1 slew rate (in the millisecond range), the input which this may occur. The 3.3 V operating condition of the voltage is not changing quickly when VDD1 reaches the UVLO ADuM5401/ADuM5402/ADuM5403/ADuM5404 is examined minimum voltage. The current surge is approximately 300 mA because it represents the most susceptible mode of operation. because V is nearly constant at the 2.7 V UVLO voltage. The DD1 The pulses at the transformer output have an amplitude greater behavior during startup is similar to when the device load is a than 1.0 V. The decoder has a sensing threshold at approximately short circuit; these values are consistent with the short-circuit 0.5 V, thus establishing a 0.5 V margin in which induced voltages current shown in Figure 14. can be tolerated. The voltage induced across the receiving coil is When starting the device for VISO = 5 V operation, do not limit given by the current available to the V power pin to less than 300 mA. DD1 V = (−dβ/dt)∑πr2; n = 1, 2, … , N n The ADuM5401/ADuM5402/ADuM5403/ADuM5404 devices may not be able to drive the output to the regulation point if a where: current-limiting device clamps the V voltage during startup. β is the magnetic flux density (gauss). DD1 r is the radius of the nth turn in the receiving coil (cm). n N is the total number of turns in the receiving coil. Rev. D | Page 22 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404 Given the geometry of the receiving coil in the ADuM5401/ Note that, at combinations of strong magnetic field and high ADuM5402/ADuM5403/ADuM5404, and an imposed frequency, any loops formed by PCB traces can induce error requirement that the induced voltage be, at most, 50% of the voltages sufficiently large to trigger the thresholds of succeeding 0.5 V margin at the decoder, a maximum allowable magnetic circuitry. Exercise care in the layout of such traces to avoid this field is calculated as shown in Figure 27. possibility. 100 POWER CONSUMPTION X FLU The VDD1 power supply input provides power to the iCoupler data C 10 channels, as well as to the power converter. For this reason, the TI NE quiescent currents drawn by the data converter and the primary LE MAGkgauss) 1 arantdel sye. cAolnl odfa rthye isnep quut/ioesuctepnutt pcohwanenr edles mcaannndost hbaev de ebteeermn cinoemdb sienpead- ABY ( ALLOWDENSIT0.1 icnutror etnhte iIsD tDh1 e(Q )s ucumr roefn tth, ea sq suhioeswcnen itn o Fpiegruartein 2g9 .c Turhree ntot;t athl IeD dDy1 nsuapmpilcy UM current, IDD1 (D), demanded by the I/O channels; and any external XIM 0.01 IISO load. A M IDD1(Q) IISO 0.0011k 10kMAGNETI1C0 0FkIELD FREQ1MUENCY (Hz1)0M 100M 06577-019 IDD1(D) COPNRVIMEARRTYER SCEOCNOVNEDRATERRY Figure 27. Maximum Allowable External Magnetic Flux Density IDDP(D) IISO(D) For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at PRIMARY SECONDARY the receiving coil. This voltage is approximately 50% of the sensing DATA DATA threshold and does not cause a faulty output transition. Similarly, if INPUT/OUTPUT INPUT/OUTPUT 4-CHANNEL 4-CHANNEL swuocrhs ta-nca esve epnotl aorcitcyu)r, sit d ruedriuncge sa t threa nrescmeiivtteedd p puulsles ef r(oamnd > i1s. 0o fV t htoe 06577-024 0.75 V, still well above the 0.5 V sensing threshold of the decoder. Figure 29. Power Consumption Within the ADuM5401/ADuM5402/ADuM5403/ADuM5404 The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM5401/ Both dynamic input and output current is consumed only ADuM5402/ADuM5403/ADuM5404 transformers. Figure 28 when operating at channel speeds higher than the refresh rate, expresses these allowable current magnitudes as a function of fr. Each channel has a dynamic current determined by its data frequency for selected distances. As shown in Figure 28, the rate. Figure 21 shows the current for a channel in the forward ADuM5401/ADuM5402/ADuM5403/ADuM5404 are extremely direction, which means that the input is on the primary side of immune and can be affected only by extremely large currents the device. Figure 22 shows the current for a channel in the reverse operated at high frequency very close to the component. For the direction, which means that the input is on the secondary side of 1 MHz example, a 0.5 kA current placed 5 mm away from the the device. Both figures assume a typical 15 pF load. The following ADuM5401/ADuM5402/ADuM5403/ADuM5404 is required relationship allows the total IDD1 current to be calculated: to affect the operation of the device. I = (I × V )/(E × V ) + Σ I ; n = 1 to 4 (1) DD1 ISO ISO DD1 CHn 1k where: kA) DISTANCE = 1m IDD1 is the total supply input current. NT ( 100 ICHn is the current drawn by a single channel determined from E R Figure 21 or Figure 22, depending on channel direction. R E CU 10 IISO is the current drawn by the secondary side external load. L E is the power supply efficiency at 100 mA load from Figure 11 AB DISTANCE = 100mm W at the V and V condition of interest. O ISO DD1 L 1 M AL DISTANCE = 5mm U M XI 0.1 A M 0.01 1k 10kMAGNET1IC00 FkIELD FRE1QMUENCY (H1z0)M 100M 06577-020 Figure 28. Maximum Allowable Current for Various Current-to- ADuM5401/ADuM5402/ADuM5403/ADuM5404 Spacings Rev. D | Page 23 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet The maximum external load can be calculated by subtracting As the secondary side converter begins to accept power from the the dynamic output load from the maximum allowable load. primary, the V voltage starts to rise. When the secondary side ISO UVLO is reached, the secondary side outputs are initialized to I = I − Σ I ; n = 1 to 4 (2) ISO (LOAD) ISO (MAX) ISO (D)n their default low state until data is received from the corresponding where: primary side input. It can take up to 1 μs after the secondary I is the current available to supply an external secondary ISO (LOAD) side is initialized for the state of the output to correlate to the side load. primary side input. I is the maximum external secondary side load current ISO (MAX) Secondary side inputs sample their state and transmit it to the available at V . ISO primary side. Outputs are valid about 1 μs after the secondary I is the dynamic load current drawn from V by an input ISO (D)n ISO side becomes active. or output channel, as shown in Figure 23 and Figure 24. Because the rate of charge of the secondary side power supply is The preceding analysis assumes a 15 pF capacitive load on each dependent on loading conditions, the input voltage, and the output data output. If the capacitive load is larger than 15 pF, the additional voltage level selected, take care that the design allows the converter current must be included in the analysis of I and I . DD1 ISO (LOAD) sufficient time to stabilize before valid data is required. POWER CONSIDERATIONS When power is removed from V , the primary side converter DD1 The ADuM5401/ADuM5402/ADuM5403/ADuM5404 power and coupler shut down when the UVLO level is reached. The input, data input channels on the primary side, and data channels secondary side stops receiving power and starts to discharge. on the secondary side are all protected from premature operation The outputs on the secondary side hold the last state that they by undervoltage lockout (UVLO) circuitry. Below the minimum received from the primary side. Either the UVLO level is reached operating voltage, the power converter holds its oscillator inactive and the outputs are placed in their high impedance state, or the and all input channel drivers and refresh circuits are idle. Outputs outputs detect a lack of activity from the primary side inputs and remain in a high impedance state to prevent transmission of the outputs are set to their default low value before the secondary undefined states during power-up and power-down operations. power reaches UVLO. During application of power to V , the primary side circuitry DD1 INCREASING AVAILABLE POWER is held idle until the UVLO preset voltage is reached. At that time, the data channels initialize to their default low output The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are state until they receive data pulses from the secondary side. designed with the capability of running in combination with other compatible isoPower devices. The RC pin allows the When the primary side is above the UVLO threshold, the data OUT ADuM5401/ADuM5402/ADuM5403/ADuM5404 to provide its input channels sample their inputs and begin sending encoded PWM signal to another device acting as a master to regulate its pulses to the inactive secondary output channels. The outputs self and slave devices. Power outputs are combined in parallel on the primary side remain in their default low state because no while sharing output power equally. data comes from the secondary side inputs until secondary side power is established. The primary side oscillator also begins to The ADuM5401/ADuM5402/ADuM5403/ADuM5404 can only operate, transferring power to the secondary power circuits. be a master/standalone, and the ADuM5200 can only be a slave/ standalone device. The ADuM5000 can operate as either a master The secondary V voltage is below its UVLO limit at this ISO or slave. This means that the ADuM5000, ADuM520x, and point; the regulation control signal from the secondary side ADuM540x can only be used in the master/slave combinations is not being generated. The primary side power oscillator is listed in Table 26. allowed to free run under these conditions, supplying the maximum amount of power to the secondary side. Table 26. Allowed Combinations of isoPower Devices As the secondary side voltage rises to its regulation setpoint, Slave a large inrush current transient is present at VDD1. When the Master ADuM5000 ADuM520x ADuM540x regulation point is reached, the regulation control circuit produces ADuM5000 Yes Yes No the regulation control signal that modulates the oscillator on the ADuM520x No No No primary side. The V current is then reduced and is propor- DD1 ADuM540x Yes Yes No tional to the load current. The inrush current is less than the short-circuit current shown in Figure 14. The duration of the The allowed combinations of master and slave configured devices inrush current depends on the V loading conditions and on listed in Table 26 is sufficient to make any combination of power ISO the current and voltage available at the V pin. and channel count. DD1 Rev. D | Page 24 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404 Table 27 illustrates how isoPower devices can provide many combinations of data channel count and multiples of the single unit power. Table 27. Configurations for Power and Data Channels Number of Data Channels Power Unit 0 Channels 2 Channels 4 Channels 6 Channels 1-Unit Power ADuM5000 master ADuM520x master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master ADuM121x 2-Unit Power ADuM5000 master ADuM5000 master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master ADuM5000 slave ADuM520x slave ADuM520x slave ADuM520x slave 3-Unit Power ADuM5000 master ADuM5000 master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master ADuM5000 slave ADuM5000 slave ADuM5000 slave ADuM520x slave ADuM5000 slave ADuM520x slave ADuM5000 slave ADuM5000 slave INSULATION LIFETIME In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working All insulation structures eventually break down when subjected to voltages while still achieving a 50-year service life. The working voltage stress over a sufficiently long period. The rate of insulation voltages listed in Table 20 can be applied while maintaining the degradation is dependent on the characteristics of the voltage 50-year minimum lifetime, provided that the voltage conforms waveform applied across the insulation. In addition to the testing to either the unipolar ac or dc voltage cases. performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime Any cross-insulation voltage waveform that does not conform of the insulation structure within the ADuM5401/ADuM5402/ to Figure 31 or Figure 32 should be treated as a bipolar ac wave- ADuM5403/ADuM5404 devices. form and its peak voltage limited to the 50-year lifetime voltage value listed in Table 20. Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration The voltage presented in Figure 32 is shown as sinusoidal for factors for several operating conditions are determined. These illustration purposes only. It is meant to represent any voltage factors allow calculation of the time to failure at the actual working waveform varying between 0 V and some limiting value. The voltage. The values shown in Table 20 summarize the peak voltage limiting value can be positive or negative, but the voltage cannot for 50 years of service life for a bipolar ac operating condition cross 0 V. and the maximum CSA/VDE approved working voltages. In RATED PEAK VOLTAGE many cases, the approved working voltage is higher than the 5vo0-ltyaegaers scearnv ilceea dli fteo v sohlotargteen. Oedp ienrsautiloanti oant tlhifees ien h siogmh we coarskeisn.g 0V 06577-021 Figure 30. Bipolar AC Waveform The insulation lifetime of the ADuM5401/ADuM5402/ ADuM5403/ADuM5404 devices depends on the voltage wave- RATED PEAK VOLTAGE form type imposed across the isolation barrier. The iCoupler iwnhsuetlhateiro tnh set wruacvteufroer mde igsr baidpeosl aart adcif, fuenreipnot lraart easc ,d oerp decn.d Finiggu roen 3 0, 0V 06577-023 Figure 31, and Figure 32 illustrate these different isolation Figure 31. DC Waveform voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal RATED PEAK VOLTAGE of a 50-year operating lifetime under the bipolar ac condition determines the maximum working voltage recommended by Analog Devices. 0V NOTES: 1. THE VOLTAGE IS SHOWN AS SINUSOIDAL FOR ILLUSTRATION PURPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE WTVHOAELV TLEAIFMGOIETR IMCNA GVN AVNRAOYLTIUN CEGR C BOAESNTS WB 0EEV E.PNO S0VIT IAVNED O SRO NMEEG LAITMIIVTEIN, GBU VTA TLHUEE.06577-022 Figure 32. Unipolar AC Waveform Rev. D | Page 25 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet OUTLINE DIMENSIONS 10.50(0.4134) 10.10(0.3976) 16 9 7.60(0.2992) 7.40(0.2913) 1 8 10.65(0.4193) 10.00(0.3937) 1.27(0.0500) 0.75(0.0295) BSC 2.65(0.1043) 0.25(0.0098) 45° 0.30(0.0118) 2.35(0.0925) 8° 0.10(0.0039) 0° COPLANARITY 0.10 0.51(0.0201) SPLEAATNIENG 0.33(0.0130) 1.27(0.0500) 0.31(0.0122) 0.20(0.0079) 0.40(0.0157) C(RINOEFNPEATRRREOENNLCLTEIHNCEOGOSNDMELISPYM)LAEAIANNRNDSETIAORTRNOOESUJNANEORDDETEEDAICN-POSMPFTRIFALONLMPIDMIRLAELIRATIMTDEEESRTFSMEO;SRIRN-0ECU1QH3SU-EADIVAIINMAELDENENSSTIIOGSNNFS.OR 03-27-2007-B Figure 33. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Number Number Maximum Maximum Maximum of Inputs, of Inputs, Data Rate Propagation Pulse Width Temperature Package Package Model1, 2 V Side V Side (Mbps) Delay, 5 V (ns) Distortion (ns) Range (°C) Description Option DD1 ISO ADuM5401ARWZ 3 1 1 100 40 −40 to +105 16-Lead SOIC_W RW-16 ADuM5401CRWZ 3 1 25 60 6 −40 to +105 16-Lead SOIC_W RW-16 ADuM5402ARWZ 2 2 1 100 40 −40 to +105 16-Lead SOIC_W RW-16 ADuM5402CRWZ 2 2 25 60 6 −40 to +105 16-Lead SOIC_W RW-16 ADuM5403ARWZ 1 3 1 100 40 −40 to +105 16-Lead SOIC_W RW-16 ADuM5403CRWZ 1 3 25 60 6 −40 to +105 16-Lead SOIC_W RW-16 ADuM5404ARWZ 0 4 1 100 40 −40 to +105 16-Lead SOIC_W RW-16 ADuM5404CRWZ 0 4 25 60 6 −40 to +105 16-Lead SOIC_W RW-16 1 Z = RoHS Compliant Part. 2 Tape and reel are available. The addition of an RL suffix designates a 13” (1,000 units) tape and reel option. Rev. D | Page 26 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404 NOTES Rev. D | Page 27 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet NOTES ©2008–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06577-0-3/19(D) Rev. D | Page 28 of 28