Dual-Channel, 2.5 kV Isolators with Integrated DC-to-DC Converter Data Sheet ADuM5200/ADuM5201/ADuM5202 FEATURES FUNCTIONAL BLOCK DIAGRAMS isoPower integrated, isolated dc-to-dc converter Regulated 3.3 V or 5 V output VDD1 1 OSC RECT REG 16 VISO Up to 500 mW output power GND1 2 15 GNDISO Dual, dc-to-25 Mbps (NRZ) signal isolation channels VIA/VOA 3 14 VIA/VOA 16-lead SOIC package with 7.6 mm creepage 2-CHANNELiCOUPLER CORE High temperature operation: 105°C maximum VIB/VOB 4 13 VIB/VOB High common-mode transient immunity: >25 kV/μs RCIN 5 12 NC Safety and regulatory approvals UL recognition RCSEL 6 ADuM5200/ 11 VSEL 2500 V rms for 1 minute per UL 1577 VE1/NC 7 ADuM5201/ 10 VE2/NC CSA Component Acceptance Notice #5A) GND1 8 ADuM5202 9 GNDISO07540-001 VDE certificate of conformity (pending) Figure 1. IEC 60747-5-2 (VDE 0884, Part 2):2003-01 V = 560 V IORM PEAK VIA VOA APPLICATIONS 3 14 ADuM5200 RInSd-u23st2r/iRalS f-i4e2ld2 /bRuSs- 4is8o5l atrtaionns ceivers VIB 4 13VOB 07540-002 Power supply start-up bias and gate drives Figure 2. ADuM5200 Isolated sensor interfaces Industrial PLCs VIA VOA GENERAL DESCRIPTION 3 14 ADuM5201 iTsholea AtoDrsu wMit5h2 i0s0o/PAoDweurM®, 5a2n0 i1n/tAegDrautMed5, 2is0o2l1a taerde dduc-atlo-c-dhca ncnonelv derigteitra. l VOB 4 13VIB 07540-003 Based on the Analog Devices, Inc., iCoupler® technology, the Figure 3. ADuM5201 dc-to-dc converter provides up to 500 mW of regulated, isolated power at either 5.0 V or 3.3 V from a 5.0 V input supply, or 3.3 V VOA VIA from a 3.3 V supply at the power levels shown in Table 1. These 3 14 devices eliminate the need for a separate, isolated dc-to-dc converter ADuM5202 itnec lhonwo ploogwye irs iusosleadte tdo diseosilagtnes .t hTeh leo igCico usipglnera lcsh ainp ds cfaolre tthraen msfaogrnmeetric VOB 4 13VIB 07540-004 Figure 4. ADuM5202 components of the dc-to-dc converter. The result is a small form factor, total isolation solution. The ADuM5200/ADuM5201/ADuM5202 isolators provide two Table 1. Power Levels independent isolation channels in a variety of channel configurations Input Voltage (V) Output Voltage (V) Output Power (mW) and data rates (see the Ordering Guide for more information). 5.0 5.0 500 5.0 3.3 330 isoPower uses high frequency switching elements to transfer power 3.3 3.3 200 through its transformer. Special care must be taken during printed circuit board (PCB) layout to meet emissions standards. See the AN-0971 Application Note for board layout recommendations. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009-2012 Analog Devices, Inc. All rights reserved.

ADuM5200/ADuM5201/ADuM5202 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configurations and Function Descriptions ......................... 12 Applications ....................................................................................... 1 Truth Table .................................................................................. 14 General Description ......................................................................... 1 Typical Performance Characteristics ........................................... 15 Functional Block Diagrams ............................................................. 1 Terminology .................................................................................... 18 Revision History ............................................................................... 2 Applications Information .............................................................. 19 Specifications ..................................................................................... 3 PCB Layout ................................................................................. 19 Electrical Characteristics—5 V Primary Input Supply/ Start-Up Behavior....................................................................... 19 5 V Secondary Isolated Supply ................................................... 3 EMI Considerations ................................................................... 20 Electrical Characteristics—3.3 V Primary Input Supply/ Propagation Delay Parameters ................................................. 20 3.3 V Secondary Isolated Supply ................................................ 5 DC Correctness and Magnetic Field Immunity.......................... 20 Electrical Characteristics—5 V Primary Input Supply/ 3.3 V Secondary Isolated Supply ................................................ 7 Power Consumption .................................................................. 21 Package Characteristics ............................................................... 9 Current Limit and Thermal Overload Protection ................. 22 Regulatory Information ............................................................... 9 Power Considerations ................................................................ 22 Insulation and Safety-Related Specifications ............................ 9 Thermal Analysis ....................................................................... 23 Increasing Available Power ....................................................... 23 IEC 60747-5-2 (VDE 0884, Part 2):2003-01 Insulation Characteristics ............................................................................ 10 Insulation Lifetime ..................................................................... 24 Recommended Operating Conditions .................................... 10 Outline Dimensions ....................................................................... 25 Absolute Maximum Ratings .......................................................... 11 Ordering Guide .......................................................................... 25 ESD Caution ................................................................................ 11 REVISION HISTORY 5/12—Rev. A to Rev. B Changes to Pin 5 Description, Table 22 ....................................... 13 Created Hyperlink for Safety and Regulatory Approvals Changes to Pin 5 Description, Table 23 and Table 24 ............... 14 Entry in Features Section ................................................................. 1 Changes to Figure 9 to Figure 11 .................................................. 15 Updated Outline Dimensions ....................................................... 25 Added Figure 17 and Figure 18; Renumbered Sequentially ..... 16 Changes to Figure 19 and Figure 20 ............................................ 16 9/11—Rev. 0 to Rev. A Changes to Terminology Section ................................................. 18 Changes to Product Title, Features Section, and General Changes to Applications Information Section ........................... 19 Description Section .......................................................................... 1 Added Start-Up Behavior Section ................................................ 19 Added Table 1; Renumbered Sequentially .................................... 1 Changes to EMI Considerations Section .................................... 20 Changes to Specifications Section .................................................. 3 Changes to Table 19 and Table 20 ................................................ 11 10/08—Revision 0: Initial Version Changes to Pin 5 Description, Table 21 ....................................... 12 Rev. B | Page 2 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY All typical specifications are at T = 25°C, V = V = V = 5 V. Minimum/maximum specifications apply over the entire recommended A DD1 SEL ISO operation range which is 4.5 V ≤ V , V , V ≤ 5.5 V; and −40°C ≤ T ≤ +105°C, unless otherwise noted. Switching specifications are DD1 SEL ISO A tested with C = 15 pF and CMOS signal levels, unless otherwise noted. L Table 2. DC-to-DC Converter Static Specifications Parameter Symbol Min Typ Max Unit Test Conditions DC-TO-DC CONVERTER SUPPLY Setpoint V 4.7 5.0 5.4 V I = 0 mA ISO ISO Line Regulation V 1 mV/V I = 50 mA, V = 4.5 V to 5.5 V ISO (LINE) ISO DD1 Load Regulation V 1 5 % I = 10 mA to 90 mA ISO (LOAD) ISO Output Ripple V 75 mV p-p 20 MHz bandwidth, C = 0.1 µF||10 µF, I = 90 mA ISO (RIP) BO ISO Output Noise V 200 mV p-p C = 0.1 µF||10 µF, I = 90 mA ISO (NOISE) BO ISO Switching Frequency f 180 MHz OSC PW Modulation Frequency f 625 kHz PWM Output Supply I 100 mA V > 4.5 V ISO (MAX) ISO Efficiency at I 34 % I = 100 mA ISO (MAX) ISO I , No V Load I 8 22 mA DD1 ISO DD1 (Q) I , Full V Load I 290 mA DD1 ISO DD1 (MAX) Table 3. DC-to-DC Converter Dynamic Specifications 1 Mbps—A Grade or C Grade 25 Mbps—C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions SUPPLY CURRENT Input No V load ISO ADuM5200 I 6 34 mA DD1 ADuM5201 I 7 38 mA DD1 ADuM5202 I 7 41 mA DD1 Available to Load ADuM5200 I 100 94 mA ISO (LOAD) ADuM5201 I 100 92 mA ISO (LOAD) ADuM5202 I 100 90 mA ISO (LOAD) Table 4. Switching Specifications A Grade C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions SWITCHING SPECIFICATIONS Data Rate 1 25 Mbps Within PWD limit Propagation Delay t , t 55 100 45 60 ns 50% input to 50% output PHL PLH Pulse Width Distortion PWD 40 6 ns |t − t | PLH PHL Change vs. Temperature 5 ps/°C Pulse Width PW 1000 40 ns Within PWD limit Propagation Delay Skew t 50 15 ns Between any two units PSK Channel Matching Codirectional1 t 50 6 ns PSKCD Opposing Directional2 t 50 15 ns PSKOD 1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation 7 barrier. 2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. Rev. B | Page 3 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet Table 5. Input and Output Characteristics Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Logic High Input Threshold V 0.7 V or 0.7 V V IH ISO DD1 Logic Low Input Threshold V 0.3 V or 0.3 V V IL ISO DD1 Logic High Output Voltages V V − 0.3 or V − 0.3 5.0 V I = −20 µA, V = V OH DD1 ISO Ox Ix IxH V − 0.5 or V − 0.5 4.8 V I = −4 mA, V = V DD1 ISO Ox Ix IxH Logic Low Output Voltages V 0.0 0.1 V I = 20 µA, V = V OL Ox Ix IxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL Undervoltage Lockout V , V , V supplies DD1 DDL ISO Positive Going Threshold V 2.7 V UV+ Negative Going Threshold V 2.4 V UV− Hysteresis V 0.3 V UVH Input Currents per Channel I −20 +0.01 +20 µA 0 V ≤ V ≤ V I Ix DDx AC SPECIFICATIONS Output Rise/Fall Time t /t 2.5 ns 10% to 90% R F Common-Mode Transient |CM| 25 35 kV/µs V = V or V , V = 1000 V, Ix DD1 ISO CM Immunity1 transient magnitude = 800 V Refresh Rate f 1.0 Mbps r 1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining V > 0.7 × V or 0.7 × V for a high output or V < 0.3 × V or 0.3 × V for a O DD1 ISO O DD1 ISO low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. B | Page 4 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202 ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY All typical specifications are at T = 25°C, V = V = 3.3 V, V = GND . Minimum/maximum specifications apply over the entire A DD1 ISO SEL ISO recommended operation range which is 3.0 V ≤ V , V , V ≤ 3.6 V; and −40°C ≤ T ≤ +105°C, unless otherwise noted. Switching DD1 SEL ISO A specifications are tested with C = 15 pF and CMOS signal levels, unless otherwise noted. L Table 6. DC-to-DC Converter Static Specifications Parameter Symbol Min Typ Max Unit Test Conditions DC-TO-DC CONVERTER SUPPLY Setpoint V 3.0 3.3 3.6 V I = 0 mA ISO ISO Line Regulation V 1 mV/V I = 30 mA, V = 3.0 V to 3.6 V ISO (LINE) ISO DD1 Load Regulation V 1 5 % I = 6 mA to 54 mA ISO (LOAD) ISO Output Ripple V 50 mV p-p 20 MHz bandwidth, C = 0.1 µF||10 µF, I = 54 mA ISO (RIP) BO ISO Output Noise V 130 mV p-p C = 0.1 µF||10 µF, I = 54 mA ISO (NOISE) BO ISO Switching Frequency f 180 MHz OSC PW Modulation Frequency f 625 kHz PWM Output Supply I 60 mA V > 3 V ISO (MAX) ISO Efficiency at I 34 % I = 60 mA ISO (MAX) ISO I , No V Load I 6 15 mA DD1 ISO DD1 (Q) I , Full V Load I 175 mA DD1 ISO DD1 (MAX) Table 7. DC-to-DC Converter Dynamic Specifications 1 Mbps—A Grade or C Grade 25 Mbps—C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions SUPPLY CURRENT Input No V load ISO ADuM5200 I 4 23 mA DD1 ADuM5201 I 4 25 mA DD1 ADuM5202 I 5 27 mA DD1 Available to Load ADuM5200 I 60 56 mA ISO (LOAD) ADuM5201 I 60 55 mA ISO (LOAD) ADuM5202 I 60 54 mA ISO (LOAD) Table 8. Switching Specifications A Grade C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions SWITCHING SPECIFICATIONS Data Rate 1 25 Mbps Within PWD limit Propagation Delay t , t 60 100 45 60 ns 50% input to 50% output PHL PLH Pulse Width Distortion PWD 40 6 ns |t − t | PLH PHL Change vs. Temperature 5 ps/°C Pulse Width PW 1000 40 ns Within PWD limit Propagation Delay Skew t 50 45 ns Between any two units PSK Channel Matching Codirectional1 t 50 6 ns PSKCD Opposing Directional2 t 50 15 ns PSKOD 1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation 7 barrier. 2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. Rev. B | Page 5 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet Table 9. Input and Output Characteristics Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Logic High Input Threshold V 0.7 V or 0.7 V V IH ISO DD1 Logic Low Input Threshold V 0.3 V or 0.3 V V IL ISO DD1 Logic High Output Voltages V V − 0.3 or V − 0.3 3.3 V I = −20 µA, V = V OH DD1 ISO Ox Ix IxH V − 0.5 or V − 0.5 3.1 V I = −4 mA, V = V DD1 ISO Ox Ix IxH Logic Low Output Voltages V 0.0 0.1 V I = 20 µA, V = V OL Ox Ix IxL 0.0 0.4 V I = 4 mA, V = V Ox Ix IxL Undervoltage Lockout V , V , V supplies DD1 DDL ISO Positive Going Threshold V 2.7 V UV+ Negative Going Threshold V 2.4 V UV− Hysteresis V 0.3 V UVH Input Currents per Channel I −20 +0.01 +20 µA 0 V ≤ V ≤ V I Ix DDx AC SPECIFICATIONS Output Rise/Fall Time t /t 2.5 ns 10% to 90% R F Common-Mode Transient |CM| 25 35 kV/µs V = V or V , V = 1000 V, Ix DD1 ISO CM Immunity1 transient magnitude = 800 V Refresh Rate f 1.0 Mbps r 1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining V > 0.7 × V or 0.7 × V for a high output or V < 0.3 × V or 0.3 × V for a O DD1 ISO O DD1 ISO low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. B | Page 6 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202 ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY All typical specifications are at T = 25°C, V = 5.0 V, V = 3.3 V, V = GND . Minimum/maximum specifications apply over the A DD1 ISO SEL ISO entire recommended operation range which is 4.5 V ≤ V ≤ 5.5 V, 3.0 V ≤ V ≤ 3.6 V; and −40°C ≤ T ≤ +105°C, unless otherwise DD1 ISO A noted. Switching specifications are tested with C = 15 pF and CMOS signal levels, unless otherwise noted. L Table 10. DC-to-DC Converter Static Specifications Parameter Symbol Min Typ Max Unit Test Conditions DC-TO-DC CONVERTER SUPPLY Setpoint V 3.0 3.3 3.6 V I = 0 mA ISO ISO Line Regulation V 1 mV/V I = 50 mA, V = 3.0 V to 3.6 V ISO (LINE) ISO DD1 Load Regulation V 1 5 % I = 6 mA to 54 mA ISO (LOAD) ISO Output Ripple V 50 mV p-p 20 MHz bandwidth, C = 0.1 µF||10 µF, I = 90 mA ISO (RIP) BO ISO Output Noise V 130 mV p-p C = 0.1 µF||10 µF, I = 90 mA ISO (NOISE) BO ISO Switching Frequency f 180 MHz OSC PW Modulation Frequency f 625 kHz PWM Output Supply I 100 mA V > 3 V ISO (MAX) ISO Efficiency at I 30 % I = 90 mA ISO (MAX) ISO I , No V Load I 5 15 mA DD1 ISO DD1 (Q) I , Full V Load I 230 mA DD1 ISO DD1 (MAX) Table 11. DC-to-DC Converter Dynamic Specifications 1 Mbps—A Grade or C Grade 25 Mbps—C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions SUPPLY CURRENT Input No V load ISO ADuM5200 I 5 22 mA DD1 ADuM5201 I 5 23 mA DD1 ADuM5202 I 5 24 mA DD1 Available to Load ADuM5200 I 100 96 mA ISO (LOAD) ADuM5201 I 100 95 mA ISO (LOAD) ADuM5202 I 100 94 mA ISO (LOAD) Table 12. Switching Specifications A Grade C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions SWITCHING SPECIFICATIONS Data Rate 1 25 Mbps Within PWD limit Propagation Delay t , t 60 100 45 60 ns 50% input to 50% output PHL PLH Pulse Width Distortion PWD 40 6 ns |t − t | PLH PHL Change vs. Temperature 5 ps/°C Pulse Width PW 1000 40 ns Within PWD limit Propagation Delay Skew t 50 15 ns Between any two units PSK Channel Matching Codirectional1 t 50 6 ns PSKCD Opposing Directional2 t 50 15 ns PSKOD 1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 7 2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. Rev. B | Page 7 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet Table 13. Input and Output Characteristics Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Logic High Input Threshold V 0.7 V or 0.7 V V IH ISO DD1 Logic Low Input Threshold V 0.3 V or 0.3 V V IL ISO DD1 Logic High Output Voltages V V − 0.2, V − 0.2 V or V V I = −20 μA, V = V OH DD1 ISO DD1 ISO Ox Ix IxH V − 0.5 or V − 0.2 or V I = −4 mA, V = V DD1 DD1 Ox Ix IxH V − 0.5 V − 0.2 ISO ISO Logic Low Output Voltages V 0.0 0.1 V I = 20 μA, V = V OL Ox Ix IxL 0.0 0.4 V I = 4 mA, V = V Ox Ix IxL Undervoltage Lockout V , V , V supplies DD1 DDL ISO Positive Going Threshold V 2.7 V UV+ Negative Going Threshold V 2.4 V UV− Hysteresis V 0.3 V UVH Input Currents per Channel I −20 +0.01 +20 μA 0 V ≤ V ≤ V I Ix DDx AC SPECIFICATIONS Output Rise/Fall Time t/t 2.5 ns 10% to 90% R F Common-Mode Transient |CM| 25 35 kV/μs V = V or V , V = 1000 V, Ix DD1 ISO CM Immunity1 transient magnitude = 800 V Refresh Rate f 1.0 Mbps r 1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. B | Page 8 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202 PACKAGE CHARACTERISTICS Table 14. Thermal and Isolation Characteristics Parameter Symbol Min Typ Max Unit Test Conditions RESISTANCE AND CAPACITANCE Resistance (Input-to-Output)1 R 102 Ω I-O Capacitance (Input-to-Output)1 C 2.2 pF f = 1 MHz I-O Input Capacitance2 C 4.0 pF I IC Junction to Ambient Thermal Resistance θ 45 °C/W Thermocouple located at the center of the package JA underside; test conducted on a 4-layer board with thin traces 3 THERMAL SHUTDOWN Threshold TS 150 °C T rising SD J Hysteresis TS 20 °C SD-HYS 1 This device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. 2 Input capacitance is from any input data pin to ground. 3 Refer to the Power Considerations section for thermal model definitions. REGULATORY INFORMATION The ADuM5200/ADuM5201/ADuM5202 are approved by the organizations listed in Table 15. Refer to Table 20 and the Insulation Lifetime section for more information about the recommended maximum working voltages for specific cross-insulation waveforms and insulation levels. Table 15. UL1 CSA VDE (Pending)2 Recognized under UL 1577 component Approved under CSA Component Certified according to IEC 60747-5-2 recognition program1 Acceptance Notice #5A (VDE 0884, Part 2):2003-012 Single protection, 2500 V rms Testing was conducted per CSA 60950-1-07 Basic insulation, 560 V PEAK isolation voltage and IEC 60950-1 2nd Ed. at 2.5 kV rated voltage Basic insulation at 600 V rms (848 V ) PEAK working voltage Reinforced insulation at 250 V rms (353 V ) PEAK working voltage File E214100 File 205078 File 2471900-4880-0001 1 In accordance with UL 1577, each ADuM5200/ADuM5201/ADuM5202 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 10 μA). 2 In accordance with IEC 60747-5-2 (VDE 0884 Part 2):2003-01, each ADuM520x is proof tested by applying an insulation test voltage ≥ 1590 VPEAK for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates IEC 60747-5-2 (VDE 0884, Part 2):2003-01 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 16. Critical Safety-Related Dimensions and Material Properties Parameter Symbol Value Unit Test Conditions/Comments Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap L(I01) 8.0 mm Distance measured from input terminals to output terminals; shortest distance through air along the PCB mounting plane, as an aid to PC board layout Minimum External Tracking (Creepage) L(I02) 7.6 mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Distance (Internal Clearance) 0.017 min mm Distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303, Part 1 Isolation Group IIIa Material group (DIN VDE 0110, 1/89, Table 1) Rev. B | Page 9 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet IEC 60747-5-2 (VDE 0884, PART 2):2003-01 INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by the protective circuits. The asterisk (*) marking branded on the components designates IEC 60747-5-2 (VDE 0884, Part 2):2003-1 approval. Table 17. VDE Characteristics Description Conditions Symbol Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V 560 V IORM PEAK Input-to-Output Test Voltage, Method b1 V × 1.875 = V , 100% production test, t = t = V 1050 V IORM pd (m) ini m pd (m) PEAK 1 sec, partial discharge < 5 pC Input-to-Output Test Voltage, Method a After Environmental Tests Subgroup 1 V × 1.5 = V , t = 60 sec, t = 10 sec, partial V 840 V IORM pd (m) ini m pd (m) PEAK discharge < 5 pC After Input and/or Safety Test Subgroup 2 V × 1.2 = V , t = 60 sec, t = 10 sec, partial V 672 V IORM pd (m) ini m pd (m) PEAK and Subgroup 3 discharge < 5 pC Highest Allowable Overvoltage V 4000 V IOTM PEAK Withstand Isolation Voltage 1 minute withstand rating V 2500 V ISO RMS Surge Isolation Voltage V = 6 kV, 1.2 µs rise time, 50 µs, 50% fall time V 6000 V PEAK IOSM PEAK Safety Limiting Values Maximum value allowed in the event of a failure (see Figure 5) Case Temperature T 150 °C S Side 1 I Current I 555 mA DD1 S1 Insulation Resistance at T V = 500 V R >109 Ω S IO S 600 A) m 500 T ( N E R R 400 U C D1 VD300 G N TI A R 200 E P O E AF 100 S 00 50AMBIENT TEM1P00ERATURE (°C1)50 200 07540-005 Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2 RECOMMENDED OPERATING CONDITIONS Table 18. Parameter Symbol Min Max Unit Operating Temperature1 T −40 +105 °C A Supply Voltages2 V @ V = 0 V V 3.0 5.5 V DD1 SEL DD1 V @ V = V V 4.5 5.5 V DD1 SEL ISO DD1 1 Operation at 105°C requires reduction of the maximum load current as specified in Table 19. 2 Each voltage is relative to its respective ground. Rev. B | Page 10 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 19. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational Storage Temperature Range (T ) −55°C to +150°C ST section of this specification is not implied. Exposure to absolute Ambient Operating Temperature −40°C to +105°C Range (T ) maximum rating conditions for extended periods may affect A Supply Voltages (V , V )1 −0.5 V to +7.0 V device reliability. DD1 ISO Input Voltage (V , V , RC , RC , V )1, 2 −0.5 V to V + 0.5 V IA IB IN SEL SEL DDI Output Voltage (V , V )1, 2 −0.5 V to V + 0.5 V ESD CAUTION OA OB DDO Average Output Current per Pin3 −10 mA to +10 mA Common-Mode Transients4 −100 kV/µs to +100 kV/µs 1 Each voltage is relative to its respective ground. 2 V and V refer to the supply voltages on the input and output sides of a DDI DDO given channel, respectively. See the PCB Layout section. 3 See Figure 5 for maximum rated current values for various temperatures. 4 Common-mode transients exceeding the absolute maximum slew rate may cause latch-up or permanent damage. Table 20. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime1 Parameter Max Unit Applicable Certification AC Voltage, Bipolar Waveform 424 V All certifications, 50-year operation PEAK AC Voltage, Unipolar Waveform Basic Insulation 600 V Working voltage, 50-year operation PEAK Reinforced Insulation 353 V Working voltage per IEC 60950-1 PEAK DC Voltage Basic Insulation 600 V Working voltage, 50-year operation PEAK Reinforced Insulation 353 V Working voltage per IEC 60950-1 PEAK 1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information. Rev. B | Page 11 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1 1 16 VISO GND1 2 15 GNDISO VIA 3 ADuM5200 14 VOA VIB 4 TOP VIEW 13 VOB RCIN 5 (Not to Scale) 12 NC RCSEL 6 11 VSEL GNNDC1 87 190 VGEN2DISO07540-006 NC = NO CONNECT Figure 6. ADuM5200 Pin Configuration Table 21. ADuM5200 Pin Function Descriptions Pin No. Mnemonic Description 1 V Primary Supply Voltage, 3.0 V to 5.5 V. DD1 2, 8 GND Ground 1. Ground reference for the isolator primary side. Pin 2 and Pin 8 are internally connected to each other, and 1 it is recommended that both pins be connected to a common ground. 3 V Logic Input A. IA 4 V Logic Input B. IB 5 RC Regulation Control Input. This pin must be connected to the RC pin of a master isoPower device or tied low. Note IN OUT that this pin must not be tied high if RC is low; this combination causes excessive voltage on the secondary side, SEL damaging the ADuM5200 and possibly the devices that it powers. 6 RC Control Input. Determines self-regulation mode (RC high) or slave mode (RC low), allowing external regulation. SEL SEL SEL This pin is weakly pulled to the high state. In noisy environments, tie this pin either high or low. 7, 12 NC No Internal Connection. 9, 15 GND Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each other, and it is recommended ISO that both pins be connected to a common ground. 10 V Data Enable Input. When this pin is high or not connected, the secondary outputs are active; when this pin is low, E2 the outputs are in a high-Z state. 11 V Output Voltage Selection. When V = V , the V setpoint is 5.0 V. When V = GND , the V setpoint is 3.3 V. SEL SEL ISO ISO SEL ISO ISO In slave regulation mode, this pin has no function. 13 V Logic Output B. OB 14 V Logic Output A. OA 16 V Secondary Supply Voltage. Output for secondary side isolated data channels and external loads. ISO Rev. B | Page 12 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202 VDD1 1 16 VISO GND1 2 15 GNDISO VIA 3 ADuM5201 14 VOA VOB 4 TOP VIEW 13 VIB RCIN 5 (Not to Scale) 12 NC RCSEL 6 11 VSEL GNVDE11 78 190 VGEN2DISO07540-007 NC = NO CONNECT Figure 7. ADuM5201 Pin Configuration Table 22. ADuM5201 Pin Function Descriptions Pin No. Mnemonic Description 1 V Primary Supply Voltage, 3.0 V to 5.5 V. DD1 2, 8 GND Ground 1. Ground reference for isolator primary side. Pin 2 and Pin 8 are internally connected to each other, and it is 1 recommended that both pins be connected to a common ground. 3 V Logic Input A. IA 4 V Logic Output B. OB 5 RC Regulation Control Input. This pin must be connected to the RC pin of a master isoPower device or tied low. Note IN OUT that this pin must not be tied high if RC is low; this combination causes excessive voltage on the secondary side, SEL damaging the ADuM5201 and possibly the devices that it powers. 6 RC Control Input. Determines self-regulation mode (RC high) or slave mode (RC low), allowing external regulation. SEL SEL SEL This pin is weakly pulled to the high state. In noisy environments, tie this pin either high or low. 7 V Data Enable Input. When this pin is high or not connected, the primary output is active; when this pin is low, the E1 output is in a high-Z state. 9, 15 GND Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each other, and it is recommended ISO that both pins be connected to a common ground. 10 V Data Enable Input. When this pin is high or not connected, the secondary output is active; when this pin is low, the E2 output is in a high-Z state. 11 V Output Voltage Selection. When V = V , the V setpoint is 5.0 V. When V = GND , the V setpoint is 3.3 V. SEL SEL ISO ISO SEL ISO ISO In slave regulation mode, this pin has no function. 12 NC No Internal Connection. 13 V Logic Input B. IB 14 V Logic Output A. OA 16 V Secondary Supply Voltage. Output for secondary side isolated data channels and external loads. ISO Rev. B | Page 13 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet VDD1 1 16 VISO GND1 2 15 GNDISO VOA 3 ADuM5202 14 VIA VOB 4 TOP VIEW 13 VIB RCIN 5 (Not to Scale) 12 NC RCSEL 6 11 VSEL GNVDE11 78 190 NGCNDISO07540-008 NC = NO CONNECT Figure 8. ADuM5202 Pin Configuration Table 23. ADuM5202 Pin Function Descriptions Pin No. Mnemonic Description 1 V Primary Supply Voltage, 3.0 V to 5.5 V. DD1 2, 8 GND Ground 1. Ground reference for the isolator primary side. Pin 2 and Pin 8 are internally connected to each other, and 1 it is recommended that both pins be connected to a common ground. 3 V Logic Output A. OA 4 V Logic Output B. OB 5 RC Regulation Control Input. This pin must be connected to the RC pin of a master isoPower device or tied low. Note IN OUT that this pin must not be tied high if RC is low; this combination causes excessive voltage on the secondary side, SEL damaging the ADuM5202 and possibly the devices that it powers. 6 RC Control Input. Determines self-regulation mode (RC high) or slave mode (RC low), allowing external regulation. SEL SEL SEL This pin is weakly pulled to the high state. In noisy environments, tie this pin either high or low. 7 V Data Enable Input. When this pin is high or not connected, the primary output is active; when this pin is low, the E1 output is in a high-Z state. 9, 15 GND Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each other, and it is recommended ISO that both pins be connected to a common ground. 10, 12 NC No Internal Connection. 11 V Output Voltage Selection. When V = V , the V setpoint is 5.0 V. When V = GND , the V setpoint is 3.3 V. SEL SEL ISO ISO SEL ISO ISO In slave regulation mode, this pin has no function. 13 V Logic Input B. IB 14 V Logic Input A. IA 16 V Secondary Supply Voltage. Output for secondary side isolated data channels and external loads. ISO TRUTH TABLE Table 24. Power Section Truth Table (Positive Logic)1 RC RC V V SEL IN SEL DD1 Input Input Input Input (V)2 V (V) Operation ISO H X H 5.0 5.0 Self regulation mode, normal operation. H X L 5.0 3.3 Self regulation mode, normal operation. H X L 3.3 3.3 Self regulation mode, normal operation. H X H 3.3 5.0 This supply configuration is not recommended due to extremely poor efficiency. L H X X X Part runs at maximum open-loop voltage; therefore, damage can occur. L L X X 0 Power supply is disabled. L RC X X X Slave mode, RC supplied by a master isoPower device. OUT(EXT) OUT(EXT) 1 H refers to a high logic, L refers to a low logic, and X is don’t care or unknown. 2 V must be common between all isoPower devices being regulated by a master isoPower part. DD1 Rev. B | Page 14 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202 TYPICAL PERFORMANCE CHARACTERISTICS 40 3.5 %) T) ( 35 3.0 U O OWER 30 R (W) 2.5 DISPSOIPWAETRION P 25 E R IN/ POW 2.0 WE 20 ND O A 1.5 CIENCY (P 1105 I(A) DD1 1.0 EFFI 5 3.3V INPUT/3.3V OUTPUT 0.5 IDD 5V INPUT/3.3V OUTPUT 5V INPUT/5V OUTPUT 00 0.02 0.O0U4TPUT 0C.U06RRENT 0(A.0)8 0.10 0.12 07540-022 03.0 3.5 4.V0DD1(V)4.5 5.0 5.5 6.0 07540-011 Figure 9. Typical Power Supply Efficiency Figure 12. Typical Short-Circuit Input Current and Power in All Supported Power Configurations vs. V Supply Voltage DD1 1.0 E G 0.9 TAV) 0.8 VOLV/DI N (W)0.7 TPUT (500m O U TI0.6 O A SIP0.5 90% LOAD S DI D R 0.4 A E O W L O0.3 C P MI 0.2 NA 0.1 VVVDDDDDD111=== 535.VV3,,V VV, IIVSSOOISO== =53 V.33.V3V DY 10% LOAD 07540-012 00 0.02 0.04 IIS0O.0 (6A) 0.08 0.10 0.12 07540-023 (100µs/DIV) Figure 10. Typical Total Power Dissipation vs. Isolated Output Supply Current Figure 13. Typical V Transient Load Response, 5 V Output, ISO in All Supported Power Configurations 10% to 90% Load Step 0.12 E G TAV) 0.10 VOLV/DI RENT (A)0.08 OUTPUT (500m R U C0.06 UT D 90% LOAD P A OUT 0.04 C LO MI A 0.0200 0.05 0.10 INPU0.T1 5CURR0E.2N0355T.VV3 ( VAIINN )IPPN0UUP.2TTU5//T35/.V33 .VO3 VUO0 .TUO3P0TUUPTTUPTUT0.35 07540-024 DYN 10% LOAD (100µs/DIV) 07540-013 Figure 11. Typical Isolated Output Supply Current vs. Input Current Figure 14. Typical V Transient Load Response, 3 V Output, ISO in All Supported Power Configurations 10% to 90% Load Step Rev. B | Page 15 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet 25 5 BW = 20MHz 20 4 10% LOAD V) m E (15 PPL V) 3 T RI10 (SO 90% LOAD U VI P T 2 U O 5 V 5 1 0 –5 07540-014 0 07540-028 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 TIME (µs) TIME (ms) Figure 15. Typical Output Voltage Ripple at 90% Load, V = 5 V Figure 18. Typical Output Voltage Start-Up Transient ISO at 10% and 90% Load, V = 3.3 V ISO 16 20 BW = 20MHz 5V INPUT/5V OUTPUT 3.3V INPUT/3.3V OUTPUT 14 5V INPUT/3.3V OUTPUT 16 mV)12 A) RIPPLE (10 RENT (m 12 OUTPUT 86 PLY CUR 8 3.3V 4 SUP 4 200 0.5 1.0 1.5 TIM2E.0 (µs) 2.5 3.0 3.5 4.007540-015 00 5 DA1T0A RATE (Mb1p5s) 20 25 07540-025 Figure 16. Typical Output Voltage Ripple at 90% Load, V = 3.3 V Figure 19. Typical I Supply Current per Forward Data Channel ISO CHn (15 pF Output Load) 7 20 10% LOAD 5V INPUT/5V OUTPUT 3.3V INPUT/3.3V OUTPUT 6 5V INPUT/3.3V OUTPUT 16 5 A) m T ( N 12 (V)SO 4 90% LOAD URRE VI 3 LY C 8 P P 2 SU 4 1 0–1 0 TIME1 (ms) 2 307540-027 00 5 DA1T0A RATE (M1b5ps) 20 2507540-026 Figure 17. Typical Output Voltage Start-Up Transient Figure 20. Typical I Supply Current per Reverse Data Channel CHn at 10% and 90% Load, V = 5 V (15 pF Output Load) ISO Rev. B | Page 16 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202 5 3.0 5V 2.5 4 5V 3.3V 3.3V 2.0 A) A) m 3 m T ( T ( EN EN1.5 R R R R U 2 U C C 1.0 1 0.5 00 5 DA1T0A RATE (M1b5ps) 20 25 07540-018 00 5 DA1T0A RATE (M1b5ps) 20 25 07540-019 Figure 21. Typical I Dynamic Supply Current per Input Figure 22. Typical I Dynamic Supply Current per Output ISO (D) ISO (D) (15 pF Output Load) Rev. B | Page 17 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet TERMINOLOGY I t Propagation Delay DD1 (Q) PLH I is the minimum operating current drawn at the V t propagation delay is measured from the 50% level of the DD1 (Q) DD1 PLH pin when there is no external load at V and the I/O pins are rising edge of the V signal to the 50% level of the rising edge ISO Ix operating below 2 Mbps, requiring no additional dynamic of the V signal. Ox supply current. I reflects the minimum current operating DD1 (Q) Propagation Delay Skew, t PSK condition. t is the magnitude of the worst-case difference in t and/or t PSK PHL PLH I that is measured between units at the same operating temperature, DD1 (D) I is the typical input supply current with all channels supply voltages, and output load within the recommended DD1 (D) simultaneously driven at a maximum data rate of 25 Mbps with operating conditions. full capacitive load representing the maximum dynamic load Channel-to-Channel Matching, t /t PSKCD PSKOD conditions. Resistive loads on the outputs should be treated Channel-to-channel matching is the absolute value of the separately from the dynamic load. difference in propagation delays between the two channels I when operated with identical loads. DD1 (MAX) I is the input current under full dynamic and V load DD1 (MAX) ISO Minimum Pulse Width conditions. The minimum pulse width is the shortest pulse width at which I the specified pulse width distortion is guaranteed. SO (LOAD) I is the current available to the load. SO (LOAD) Maximum Data Rate t Propagation Delay The maximum data rate is the fastest data rate at which the PHL t propagation delay is measured from the 50% level of the specified pulse width distortion is guaranteed. PHL falling edge of the V signal to the 50% level of the falling edge Ix of the V signal. Ox Rev. B | Page 18 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202 APPLICATIONS INFORMATION The dc-to-dc converter section of the ADuM5200/ADuM5201/ Note that the total lead length between the ends of the low ESR ADuM5202 works on principles that are common to most capacitor and the input power supply pin must not exceed 2 mm. switching power supplies. It has a secondary side controller Installing the bypass capacitor with traces more than 2 mm in architecture with isolated pulse-width modulation (PWM) length may result in data corruption. Consider bypassing between feedback. V power is supplied to an oscillating circuit that Pin 1 and Pin 8 and between Pin 9 and Pin 16 unless both common DD1 switches current into a chip scale air core transformer. Power ground pins are connected together close to the package. transferred to the secondary side is rectified and regulated to BYPASS < 2mm either 3.3 V or 5 V. The secondary (V ) side controller regulates ISO the output by creating a PWM control signal that is sent to the VDD1 VISO GND1 GNDISO primary (V ) side by a dedicated iCoupler data channel. The DD1 VIA/VOA VOA/VIA PWM modulates the oscillator circuit to control the power being VIB/VOB VOB/VIB sent to the secondary side. Feedback allows for significantly RCIN NC higher power and efficiency. RCSEL VSEL Tvohltea AgeD loucMko5u2t0 (0U/AVDLOuM) w5i2th0 1h/yAstDerueMsis5 o2n0 2th iem Vplem peonwtse ru inndpeurt-. VEG1N/NDC1 VGEN2D/NISCO07540-020 DD1 Figure 23. Recommended PCB Layout This feature ensures that the converter does not enter oscillation In applications involving high common-mode transients, ensure due to noisy input power or slow power-on ramp rates. that board coupling across the isolation barrier is minimized. The ADuM5200/ADuM5201/ADuM5202 can accept an external Furthermore, design the board layout such that any coupling regulation control signal (RC ) that can be connected to other IN that does occur affects all pins equally on a given component isoPower devices. This allows a single regulator to control multiple side. Failure to ensure this can cause voltage differentials between power modules without contention. When accepting control from pins exceeding the absolute maximum ratings for the device a master power module, the V pins can be connected together, ISO (specified in Table 19), thereby leading to latch-up and/or adding their power. Because there is only one feedback control permanent damage. path, the supplies work together seamlessly. The ADuM5200/ The ADuM5200/ADuM5201/ADuM5202 is a power device that ADuM5201/ADuM5202 can only regulate themselves or accept dissipates approximately 1 W of power when fully loaded and regulation (as slave devices) from another device in this product running at maximum speed. Because it is not possible to apply a line; they cannot provide a regulation signal to other devices. heat sink to an isolation device, the device primarily depends PCB LAYOUT on heat dissipation into the PCB through the GND pins. If the The ADuM5200/ADuM5201/ADuM5202 digital isolators device is used at high ambient temperatures, provide a thermal with 0.5 W isoPower, integrated dc-to-dc converter require no path from the GND pins to the PCB ground plane. The board external interface circuitry for the logic interfaces. Power supply layout in Figure 23 shows enlarged pads for Pin 2, Pin 8, Pin 9, bypassing is required at the input and output supply pins (see and Pin 15. Multiple vias should be implemented from the pad Figure 23). Note that low ESR bypass capacitors are required to the ground plane to significantly reduce the temperature between Pin 1 and Pin 2 and between Pin 15 and Pin 16, as inside the chip. The dimensions of the expanded pads are at the close to the chip pads as possible. discretion of the designer and depend on the available board space. The power supply section of the ADuM5200/ADuM5201/ START-UP BEHAVIOR ADuM5202 uses a 180 MHz oscillator frequency to pass power The ADuM5200/ADuM5201/ADuM5202 do not contain a soft efficiently through its chip scale transformers. In addition, the start circuit. Take the start-up current and voltage behavior into normal operation of the data section of the iCoupler introduces account when designing with this device. switching transients on the power supply pins. Bypass capacitors When power is applied to V , the input switching circuit begins are required for several operating frequencies. Noise suppression DD1 to operate and draw current when the UVLO minimum voltage requires a low inductance, high frequency capacitor, whereas ripple is reached. The switching circuit drives the maximum available suppression and proper regulation require a large value capacitor. power to the output until it reaches the regulation voltage where These capacitors are most conveniently connected between PWM control begins. The amount of current and time this Pin 1 and Pin 2 for V and between Pin 15 and Pin 16 for V . DD1 ISO takes depends on the load and the V slew rate. DD1 To suppress noise and reduce ripple, a parallel combination of With a fast V slew rate (200 μs or less), the peak current at least two capacitors is required. The recommended capacitor DD1 draws up to 100 mA/V of V . The input voltage goes high values are 0.1 μF and 10 μF for V . The smaller capacitor must DD1 DD1 faster than the output can turn on; therefore, the peak current have a low ESR; for example, use of a ceramic capacitor is advised. is proportional to the maximum input voltage. Rev. B | Page 19 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet With a slow V slew rate (in the millisecond range), the input DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY DD1 voltage is not changing quickly when V reaches the UVLO DD1 Positive and negative logic transitions at the isolator input cause minimum voltage. The current surge is approximately 300 mA narrow (~1 ns) pulses to be sent to the decoder via the transformer. because V is nearly constant at the 2.7 V UVLO voltage. The DD1 The decoder is bistable and is, therefore, either set or reset by behavior during startup is similar to when the device load is a the pulses, indicating input logic transitions. In the absence of short circuit; these values are consistent with the short-circuit logic transitions at the input for more than 1 μs, a periodic set current shown in Figure 12. of refresh pulses indicative of the correct input state are sent to When starting the device for VISO = 5 V operation, do not limit ensure dc correctness at the output. If the decoder receives no the current available to the VDD1 power pin to less than 300 mA. internal pulses of more than about 5 μs, the input side is assumed The ADuM5200/ADuM5201/ADuM5202 devices may not be able to be unpowered or nonfunctional, in which case the isolator to drive the output to the regulation point if a current-limiting output is forced to a default state (see Table 24) by the watchdog device clamps the V voltage during startup. As a result, the timer circuit. DD1 ADuM5200/ADuM5201/ADuM5202 devices can draw large The limitation on the magnetic field immunity of the ADuM5200/ amounts of current at low voltage for extended periods of time. ADuM5201/ADuM5202 is set by the condition in which induced The output voltage of the ADuM5200/ADuM5201/ADuM5202 voltage in the receiving coil of the transformer is sufficiently exhibits VISO overshoot during startup. If this could potentially large to either falsely set or reset the decoder. The following analysis damage components attached to VISO, then a voltage-limiting defines the conditions under which this may occur. The 3 V device, such as a Zener diode, can be used to clamp the voltage. operating condition of the ADuM5200/ADuM5201/ADuM5202 Typical behavior is shown in Figure 17 and Figure 18. is examined because it represents the most susceptible mode of operation. EMI CONSIDERATIONS The pulses at the transformer output have an amplitude greater The dc-to-dc converter section of the ADuM5200/ADuM5201/ than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus ADuM5202 devices must operate at 180 MHz to allow efficient establishing a 0.5 V margin in which induced voltages can be power transfer through the small transformers. This creates tolerated. The voltage induced across the receiving coil is given by high frequency currents that can propagate in circuit board ground and power planes, causing edge emissions and dipole V = (−dβ/dt)∑πr2; n = 1, 2, … , N n radiation between the primary and secondary ground planes. where: Grounded enclosures are recommended for applications that use β is the magnetic flux density (gauss). these devices. If grounded enclosures are not possible, follow N is the number of turns in the receiving coil. good RF design practices in the layout of the PCB. See the r is the radius of the nth turn in the receiving coil (cm). n AN-0971 Application Note for board layout recommendations. Given the geometry of the receiving coil in the ADuM5200/ PROPAGATION DELAY PARAMETERS ADuM5201/ADuM5202 and an imposed requirement that the Propagation delay is a parameter that describes the time it takes induced voltage be, at most, 50% of the 0.5 V margin at the a logic signal to propagate through a component. The propagation decoder, a maximum allowable magnetic field is calculated as delay to a logic low output may differ from the propagation delay shown in Figure 25. to a logic high. 100 X INPUT (VIX) 50% LU F C 10 tPLH tPHL ETI OUTPUT (VOX) 50% 07540-118 E MAGNgauss) 1 Figure 24. Propagation Delay Parameters ABLY (k Pthuelssee twwiod tphr odpisatgoarttiioonn dise tlhaye vmaaluxeims aunmd idsi fafner ienndciec abteiotwne oefn ALLOWDENSIT0.1 M how accurately timing of the input signal is preserved. U XIM 0.01 Channel-to-channel matching refers to the maximum amount MA the propagation delay differs between channels within a single PArDoupMag5a2ti0o0n/ AdDelauyM s5k2e0w1 /rAefDerusM to5 2th0e2 mcoamxipmounmen ta.m ount the 0.0011k 10kMAGNETI1C0 0FkIELD FREQ1MUENCY (Hz1)0M 100M 07540-119 Figure 25. Maximum Allowable External Magnetic Flux Density propagation delay differs between multiple ADuM5200/ ADuM5201/ADuM5202 components operating under the same conditions. Rev. B | Page 20 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202 For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a IDD1(Q) IISO voltage of 0.25 V at the receiving coil. This is about 50% of the CONVERTER CONVERTER IDD1(D) PRIMARY SECONDARY sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse IDDP(D) IISO(D) (and is of the worst-case polarity), it reduces the received pulse PRIMARY SECONDARY from >1.0 V to 0.75 V—still well above the 0.5 V sensing DATA I/O DATA I/O tThhree sphroeclded oifn gth me adgenceotdice rf.l ux density values correspond to specific 2-CHANNEL 2-CHANNEL 07540-021 Figure 27. Power Consumption Within the ADuM5200/ADuM5201/ADuM5202 current magnitudes at given distances from the ADuM5200/ Both dynamic input and output current is consumed only when ADuM5201/ADuM5202 transformers. Figure 26 expresses operating at channel speeds higher than the rate of f. Because these allowable current magnitudes as a function of frequency r each channel has a dynamic current determined by its data rate, for selected distances. As shown, the ADuM5200/ADuM5201/ Figure 19 shows the current for a channel in the forward direction, ADuM5202 are extremely immune and can be affected only by which means that the input is on the primary side of the part. extremely large currents operated at high frequency very close Figure 20 shows the current for a channel in the reverse direction, to the component. For the 1 MHz example noted, a 0.5 kA current which means that the input is on the secondary side of the part. placed 5 mm away from the ADuM5200/ADuM5201/ADuM5202 Both figures assume a typical 15 pF load. The following is required to affect the operation of the component. relationship allows the total I current to be calculated: DD1 1000 I = (I × V )/(E × V ) + ∑ I ; n = 1 to 4 (1) A) DISTANCE = 1m DD1 ISO ISO DD1 CHn k T ( 100 where: N E I is the total supply input current. R DD1 R U I is the current drawn by a single channel determined from C CHn LE 10 Figure 19 or Figure 20, depending on channel direction. B WA DISTANCE = 100mm IISO is the current drawn by the secondary side external loads. O L 1 E is the power supply efficiency at 100 mA load from Figure 9 L A M DISTANCE = 5mm at the VISO and VDD1 condition of interest. U M XI 0.1 Calculate the maximum external load by subtracting the dynamic A M output load from the maximum allowable load. 0.011k 10MkAGNET1IC0 0FkIELD FRE1QMUENCY (H1z0)M 100M 07540-120 wherIeIS: O (LOAD) = IISO (MAX) − ∑ IISO (D)n; n = 1 to 4 (2) Figure 26. Maximum Allowable Current for Various Current-to- IISO (LOAD) is the current available to supply an external secondary ADuM5200/ADuM5201/ADuM5202 Spacings side load. Note that at combinations of strong magnetic field and high IISO (MAX) is the maximum external secondary side load current frequency, any loops formed by PCB traces can induce error available at VISO. voltages sufficiently large enough to trigger the thresholds of IISO (D)n is the dynamic load current drawn from VISO by an input succeeding circuitry. Exercise care in the layout of such traces or output channel, as shown in Figure 19 and Figure 20. Data is to avoid this possibility. presented assuming a typical 15 pF load. POWER CONSUMPTION The preceding analysis assumes a 15 pF capacitive load on each data output. If the capacitive load is larger than 15 pF, the addi- The V power supply input provides power to the iCoupler data DD1 tional current must be included in the analysis of I and I . channels as well as to the power converter. For this reason, the DD1 ISO (LOAD) quiescent currents drawn by the data converter and the primary To determine IDD1 in Equation 1, additional primary side and secondary input/output channels cannot be determined sepa- dynamic output current (IAOD) is added directly to IDD1. rately. All of these quiescent power demands have been combined Additional secondary side dynamic output current (IAOD) is into the IDD1 (Q) current shown in Figure 27. The total IDD1 supply added to IISO on a per-channel basis. current is the sum of the quiescent operating current, dynamic To determine I in Equation 2, additional secondary ISO (LOAD) current IDD1 (D) demanded by the I/O channels, and any external side output current (IAOD) is subtracted from IISO (MAX) on a IISO load. per-channel basis. Rev. B | Page 21 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet For each output channel with C greater than 15 pF, the additional During application of power to V , the primary side circuitry L DD1 capacitive supply current is given by is held idle until the UVLO preset voltage is reached. At that time, the data channels initialize to their default low output I = 0.5 × 10−3 × ((C − 15) × V ) × (2f − f); f > 0.5 f (3) AOD L ISO r r state until they receive data pulses from the secondary side. where: When the primary side is above the UVLO threshold, the data C is the output load capacitance (pF). L input channels sample their inputs and begin sending encoded V is the output supply voltage (V). ISO pulses to the inactive secondary output channels. The outputs f is the input logic signal frequency (MHz); it is half of the input on the primary side remain in their default low state because data rate expressed in units of Mbps. no data comes from the secondary side inputs until secondary f is the input channel refresh rate (Mbps). r power is established. The primary side oscillator also begins to CURRENT LIMIT AND THERMAL OVERLOAD operate, transferring power to the secondary power circuits. PROTECTION The secondary V voltage is below its UVLO limit at this point; ISO The ADuM5200/ADuM5201/ADuM5202 are protected against the regulation control signal from the secondary is not being damage due to excessive power dissipation by thermal overload generated. The primary side power oscillator is allowed to free run protection circuits. Thermal overload protection limits the in this circumstance, supplying the maximum amount of power to junction temperature to a maximum of 150°C (typical). Under the secondary, until the secondary voltage rises to its regulation extreme conditions (that is, high ambient temperature and setpoint. This creates a large inrush current transient at V . DD1 power dissipation), when the junction temperature starts to rise When the regulation point is reached, the regulation control above 150°C, the PWM is turned off, reducing the output circuit produces the regulation control signal that modulates current to zero. When the junction temperature drops below the oscillator on the primary side. The V current is reduced 130°C (typical), the PWM turns on again, restoring the output DD1 and is then proportional to the load current. The inrush current current to its nominal value. is less than the short-circuit current shown in Figure 12. The Consider the case where a hard short from V to ground occurs. ISO duration of the inrush current depends on the V loading ISO At first, the ADuM5200/ADuM5201/ADuM5202 reach their conditions and the current available at the V pin. DD1 maximum current, which is proportional to the voltage applied As the secondary side converter begins to accept power from at V . Power dissipates on the primary side of the converter DD1 the primary, the V voltage starts to rise. When the secondary (see Figure 12). If self-heating of the junction becomes great ISO side UVLO is reached, the secondary side outputs are initialized enough to cause its temperature to rise above 150°C, thermal to their default low state until data is received from the correspond- shutdown activates, turning off the PWM, and reducing the ing primary side input. It can take up to 1 μs after the secondary output current to zero. As the junction temperature cools and side is initialized for the state of the output to correlate with the drops below 130°C, the PWM turns on, and power dissipates primary side input. again on the primary side of the converter, causing the junction temperature to rise to 150°C again. This thermal oscillation Secondary side inputs sample their state and transmit it to the between 130°C and 150°C causes the part to cycle on and off as primary side. Outputs are valid about 1 μs after the secondary long as the short remains at the output. side becomes active. Thermal limit protections are intended to protect the device Because the rate of charge of the secondary side power supply against accidental overload conditions. For reliable operation, is dependent on loading conditions and the input voltage level externally limit device power dissipation to prevent junction and the output voltage level selected, take care with the design temperatures from exceeding 130°C. to allow the converter sufficient time to stabilize before valid data is required. POWER CONSIDERATIONS When power is removed from V , the primary side converter and The ADuM5200/ADuM5201/ADuM5202 power input, data DD1 coupler shut down when the UVLO level is reached. The secondary input channels on the primary side and data input channels on side stops receiving power and starts to discharge. The outputs on the secondary side are all protected from premature operation the secondary side hold the last state that they received from the by UVLO circuitry. Below the minimum operating voltage, the primary side. Either the UVLO level is reached and the outputs are power converter holds its oscillator inactive and all input channel placed in their high impedance state, or the outputs detect a lack of drivers and refresh circuits are idle. Outputs remain in a high activity from the primary side inputs and the outputs are set to impedance state to prevent transmission of undefined states their default low value before the secondary power reaches UVLO. during power-up and power-down operations. Rev. B | Page 22 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202 THERMAL ANALYSIS The ADuM5000 can act as a master or a slave device, the ADuM5401, ADuM5402, ADuM5403, and ADuM5404 can The ADuM5200/ADuM5201/ADuM5202 consist of four internal only be master/standalone, and the ADuM520x can only be die, attached to a split lead frame with two die attach paddles. For a slave/standalone device. This means that the ADuM5000, the purposes of thermal analysis, it is treated as a thermal unit ADuM520x, and ADuM5401 to ADuM5404 can only be used with the highest junction temperature reflected in the θ value in JA in certain master/slave combinations as listed in Table 25. Table 14. The value of θ is based on measurements taken with JA the part mounted on a JEDEC standard 4-layer board with fine Table 25. Allowed Combinations of isoPower Parts width traces and still air. Under normal operating conditions, the Slave ADuM5200/ADuM5201/ADuM5202 operate at full load across ADuM5401 to the full temperature range without derating the output current. Master ADuM5000 ADuM520x ADuM5404 However, following the recommendations in the PCB Layout ADuM5000 Yes Yes No section decreases the thermal resistance to the PCB, allowing ADuM520x No No No increased thermal margin at high ambient temperatures. ADuM5401 to Yes Yes No INCREASING AVAILABLE POWER ADuM5404 The ADuM5200/ADuM5201/ADuM5202 are designed with the The allowed combinations of master and slave configured parts capability of running in combination with other compatible listed in Table 25 is sufficient to make any combination of power isoPower devices. The RC and RC pins allow the ADuM5200/ and channel count. IN SEL ADuM5201/ADuM5202 to receive a PWM signal from another Table 26 illustrates how isoPower devices can provide many device through the RC pin and act as a slave to that control IN combinations of data channel count and multiples of the single signal. The RC pin chooses whether the part acts as a stand- SEL unit power. alone self-regulated device or a slave device. When the ADuM5200/ADuM5201/ADuM5202 act as a slave, their power is regulated by a PWM signal coming from a master device. This allows multiple isoPower parts to be combined in parallel while sharing the load equally. When the ADuM5200/ADuM5201/ ADuM5202 are configured as standalone units, they generate their own PWM feedback signal to regulate themselves. Table 26. Configurations for Power and Data Channels Number of Data Channels Power Units 0 Channels 2 Channels 4 Channels 6 Channels 1-Unit Power ADuM5000 master ADuM520x master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master ADuM121x 2-Unit Power ADuM5000 master ADuM5000 master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master ADuM5000 slave ADuM520x slave ADuM520x slave ADuM520x slave 3-Unit Power ADuM5000 master ADuM5000 master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master ADuM5000 slave ADuM5000 slave ADuM5000 slave ADuM520x slave ADuM5000 slave ADuM520x slave ADuM5000 slave ADuM5000 slave Rev. B | Page 23 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet INSULATION LIFETIME In the case of unipolar ac or dc voltage, the stress on the insula- tion is significantly lower. This allows operation at higher working All insulation structures eventually break down when subjected voltages while still achieving a 50-year service life. The working to voltage stress over a sufficiently long period. The rate of voltages listed in Table 20 can be applied while maintaining the insulation degradation is dependent on the characteristics of the 50-year minimum lifetime, provided the voltage conforms to voltage waveform applied across the insulation. In addition to the either the unipolar ac or dc voltage cases. testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the Any cross-insulation voltage waveform that does not conform to lifetime of the insulation structure within the ADuM5200/ Figure 29 or Figure 30 should be treated as a bipolar ac waveform ADuM5201/ADuM5202. and its peak voltage limited to the 50-year lifetime voltage value listed in Table 20. The voltage presented in Figure 29 is shown as Analog Devices performs accelerated life testing using voltage levels sinusoidal for illustration purposes only. It is meant to represent higher than the rated continuous working voltage. Acceleration any voltage waveform varying between 0 V and some limiting factors for several operating conditions are determined. These value. The limiting value can be positive or negative, but the factors allow calculation of the time to failure at the actual working voltage cannot cross 0 V. voltage. The values shown in Table 20 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, RATED PEAK VOLTAGE acansde st,h teh me aapxpimrouvmed C wSoArk/VinDg Ev oalptapgreo vise dh iwghoerrk itnhga nv oal t5a0g-eyse. aIrn s meravnicye 0V 07540-121 life voltage. Operation at these high working voltages can lead to Figure 28. Bipolar AC Waveform shortened insulation life in some cases. The insulation lifetime of the ADuM5200/ADuM5201/ RATED PEAK VOLTAGE AacDrousMs t5h2e0 i2so dlaetpioenn dbsa rornie rt.h Te hveo ilCtaogue pwlearv einfosurmla ttiyopne sitmrupcotsuerde 0V 07540-122 degrades at different rates depending on whether the waveform Figure 29. Unipolar AC Waveform is bipolar ac, unipolar ac, or dc. Figure 28, Figure 29, and Figure 30 illustrate these different isolation voltage waveforms. RATED PEAK VOLTAGE Bipolar ac voltage is the most stringent environment. The goal odfe tae r5m0-iyneeasr tohpee mraatxinimg luifmet iwmoer kuinndge vro tlhtaeg aec r beicpoomlamr ecnonddedit iboyn 0V 07540-123 Analog Devices. Figure 30. DC Waveform Rev. B | Page 24 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202 OUTLINE DIMENSIONS 10.50(0.4134) 10.10(0.3976) 16 9 7.60(0.2992) 7.40(0.2913) 1 8 10.65(0.4193) 10.00(0.3937) 1.27(0.0500) 0.75(0.0295) BSC 2.65(0.1043) 0.25(0.0098) 45° 0.30(0.0118) 2.35(0.0925) 8° 0.10(0.0039) 0° COPLANARITY 0.10 0.51(0.0201) SPELAATNIENG 0.33(0.0130) 1.27(0.0500) 0.31(0.0122) 0.20(0.0079) 0.40(0.0157) C(RINOEFNPEATRRREOENNLCLTEIHNCEOGOSNDMELISPYM)LAEAIANNRNDSETIAORTRNOOESUJNANEORDDETEEDAICN-POSMPFTRIFALONLMPIDMIRLAELIRATIMTDEEESRTFSMEO;SRIRN-0ECU1QH3SU-EADIVAIINMAELDENENSSTIIOGSNNFS.OR 03-27-2007-B Figure 31. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Number of Number of Maximum Maximum Maximum Inputs, Inputs, Data Rate Propagation Pulse Width Temperature Package Package Model1, 2 V Side V Side (Mbps) Delay, 5 V (ns) Distortion (ns) Range Description Option DD1 DD2 ADuM5200ARWZ 2 0 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM5200CRWZ 2 0 25 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM5201ARWZ 1 1 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM5201CRWZ 1 1 25 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM5202ARWZ 0 2 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM5202CRWZ 0 2 25 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16 1 Z = RoHS Compliant Part. 2 Tape and reel are available. The additional -RL suffix designates a 13-inch (1,000 units) tape and reel option. Rev. B | Page 25 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet NOTES Rev. B | Page 26 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202 NOTES Rev. B | Page 27 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet NOTES ©2009-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07540-0-5/12(B) Rev. B | Page 28 of 28