Full/Low Speed 5 kV USB Digital Isolator Data Sheet ADuM4160 FEATURES FUNCTIONAL BLOCK DIAGRAM USB 2.0 compatible Low and full speed data rate: 1.5 Mbps and 12 Mbps VBUS1 1 REG REG 16 VBUS2 Bidirectional communication GND1 2 15 GND2 4.5 V to 5.5 V V operation VDD1 3 14 VDD2 BUS 7 mA maximum upstream supply current @ 1.5 Mbps PDEN 4 13 SPD 8 mA maximum upstream supply current @ 12 Mbps SPU 5 12 PIN 2.3 mA maximum upstream idle current UD– 6 11 DD– Upstream short-circuit protection UD+ 7 10 DD+ CHliagshs t3eAm cpoenrtaatcut rEeS oDp peerarftoiormn:a 1n0c5e° pCe r ANSI/ESD STM5.1-2007 GND1 8 PU LOGIC PD LOGIC 9 GND2 08171-001 High common-mode transient immunity: >25 kV/μs Figure 1. 16-lead SOIC wide-body package version Many microcontrollers implement USB so that it presents only 16-lead SOIC wide body enhanced creepage version the D+ and D− lines to external pins. This is desirable in many RoHS compliant cases because it minimizes external components and simplifies Safety and regulatory approvals (RI-16 package) the design; however, this presents particular challenges when UL recognition: 5000 V rms for 1 minute per isolation is required. USB lines must automatically switch between UL 1577 actively driving D+/D−, receiving data, and allowing external CSA Component Acceptance Notice #5A resistors to set the idle state of the bus. The ADuM4160 provides IEC 60601-1: 250 V rms (reinforced) mechanisms for detecting the direction of data flow and control IEC 60950-1: 400 V rms (reinforced) over the state of the output buffers. Data direction is determined VDE Certificate of Conformity on a packet-by-packet basis. DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 The ADuM4160 uses the edge detection based iCoupler tech- V = 846 V peak IORM nology in conjunction with internal logic to implement a APPLICATIONS transparent, easily configured, upstream facing port isolator. USB peripheral isolation Isolating an upstream facing port provides several advantages Isolated USB hub in simplicity, power management, and robust operation. Medical applications The isolator has propagation delay comparable to that of a GENERAL DESCRIPTION standard hub and cable. It operates with the bus voltage on either side ranging from 4.5 V to 5.5 V, allowing connection The ADuM41601 is a USB port isolator, based on Analog Devices, directly to V by internally regulating the voltage to the signaling BUS Inc., iCoupler® technology. Combining high speed CMOS and level. The ADuM4160 provides isolated control of the pull-up monolithic air core transformer technology, these isolation resistor to allow the peripheral to control connection timing. components provide outstanding performance characteristics The device has a low idle current; so a suspend mode is not and are easily integrated with low and full speed USB-compatible required. A 2.5 kV version, the ADuM3160, is also available. peripheral devices. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009–2012 Analog Devices, Inc. All rights reserved.

ADuM4160 Data Sheet TABLE OF CONTENTS Features..............................................................................................1  Absolute Maximum Ratings............................................................7  Applications.......................................................................................1  ESD Caution...................................................................................7  General Description.........................................................................1  Pin Configuration and Function Descriptions..............................8  Functional Block Diagram..............................................................1  Applications Information..............................................................10  Revision History...............................................................................2  Functional Description..............................................................10  Specifications.....................................................................................3  Product Usage.............................................................................10  Electrical Characteristics.............................................................3  Compatibility of Upstream Applications................................11  Package Characteristics...............................................................4  Power Supply Options...............................................................11  Regulatory Information...............................................................4  Printed Circuit Board (PCB) Layout.......................................11  Insulation and Safety-Related Specifications............................5  DC Correctness and Magnetic Field Immunity.....................11  DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Insulation Lifetime.....................................................................12  Characteristics..............................................................................5  Outline Dimensions.......................................................................14  Recommended Operating Conditions......................................6  Ordering Guide..........................................................................14  REVISION HISTORY 2/12—Rev. C to Rev. D 8/10—Rev. A to Rev. B Created Hyperlink for Safety and Regulatory Approvals Change to Data Sheet Title...............................................................1 Entry in Features Section.................................................................1 Changes to Features Section............................................................1 Changes to Table 3............................................................................4 Changes to Applications Section.....................................................1 Change to Table 4.............................................................................5 Changes to General Description Section.......................................1 Updated Outline Dimensions.......................................................14 Changes to Table 3.............................................................................4 Changes to Ordering Guide..........................................................14 9/09—Rev. 0 to Rev. A 10/10—Rev. B to Rev. C Added USB Logo, Reformatted Page 1...........................................1 Changes to Features and General Description Section...............1 7/09—Revision 0: Initial Version Changes to Endnote 3 in Table 1 and Table 3...............................4 Changes to Table 4............................................................................5 Changes to Table 7 and Table 8.......................................................7 Updated Outline Dimensions.......................................................14 Changes to Ordering Guide..........................................................14 Rev. D | Page 2 of 16

Data Sheet ADuM4160 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 4.5 V ≤ V ≤ 5.5 V, 4.5 V ≤ V ≤ 5.5 V; 3.1 V ≤ V ≤ 3.6 V, 3.1 V ≤ V ≤ 3.6 V; all minimum/maximum specifications apply over BUS1 BUS2 DD1 DD2 the entire recommended operation range, unless otherwise noted; all typical specifications are at T = 25°C, V = V = 3.3 V. Each A DD1 DD2 voltage is relative to its respective ground. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Total Supply Current1 1.5 Mbps V or V Supply Current I 5 7 mA 750 kHz logic signal rate C = 450 pF DD1 BUS1 DD1 (L) L V or V Supply Current I 5 7 mA 750 kHz logic signal rate C = 450 pF DD2 BUS2 DD2 (L) L 12 Mbps V or V Supply Current I 6 8 mA 6 MHz logic signal rate C = 50 pF DD1 BUS1 DD1 (F) L V or V Supply Current I 6 8 mA 6 MHz logic signal rate C = 50 pF DD2 BUS2 DD2 (F) L Idle Current V or V Idle Current I 1.7 2.3 mA DD1 BUS1 DD1 (I) Input Currents I , I , −1 +0.1 +1 μA 0 V ≤ V , V , V , V , V , V , DD− DD+ DD− DD+ UD+ UD− SPD PIN I , I , V , V ≤ 3.0 UD+ UD− SPU PDEN I , I , SPD PIN I , I SPU PDEN Single-Ended Logic High Input Threshold V 2.0 V IH Single-Ended Logic Low Input Threshold V 0.8 V IL Single-Ended Input Hysteresis V 0.4 V HST Differential Input Sensitivity V 0.2 V |V − V | DI XD+ XD− Logic High Output Voltages V 2.8 3.6 V R = 15 kΩ, V = 0 V OH L L Logic Low Output Voltages V 0 0.3 V R = 1.5 kΩ, V = 3.6 V OL L L V and V Supply Undervoltage Lockout V 2.4 3.1 V DD1 DD2 UVLO V Supply Undervoltage Lockout V 3.5 4.35 V BUS1 UVLOB1 V Supply Undervoltage Lockout V 3.5 4.4 V BUS2 UVLOB2 Transceiver Capacitance C 10 pF UD+, UD−, DD+, DD− to ground IN Capacitance Matching 10 % Full Speed Driver Impedance Z 4 20 Ω OUTH Impedance Matching 10 % SWITCHING SPECIFICATIONS, I/O PINS LOW SPEED Low Speed Data Rate 1.5 Mbps C = 50 pF L Propagation Delay2 t , t 325 ns C = 50 pF, SPD = SPU = low, PHLL PLHL L V , V = 3.3 V DD1 DD2 Side 1 Output Rise/Fall Time (10% to 90%) Low t /t 75 300 ns C = 450 pF, SPD = SPU = low, RL FL L Speed V , V = 3.3 V DD1 DD2 Low Speed Differential Jitter, Next Transition |t | 45 ns C = 50 pF LJN L Low Speed Differential Jitter, Paired Transition |t | 15 ns C = 50 pF LJP L SWITCHING SPECIFICATIONS, I/O PINS FULL SPEED Full Speed Data Rate 12 Mbps C = 50 pF L Propagation Delay2 t , t 20 60 70 ns C = 50 pF, SPD = SPU = high, PHLF PLHF L V , V = 3.3 V DD1 DD2 Output Rise/Fall Time (10% to 90%) Full Speed t /t 4 20 ns C = 50 pF, SPD = SPU = high, RF FF L V , V = 3.3 V DD1 DD2 Full Speed Differential Jitter, Next Transition |t | 3 ns C = 50 pF FJN L Full Speed Differential Jitter, Paired Transition |t | 1 ns C = 50 pF FJP L Rev. D | Page 3 of 16

ADuM4160 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions For All Operating Modes Common-Mode Transient Immunity At Logic High Output3 |CM | 25 35 kV/μs V , V , V , V = V or V , H UD+ UD− DD+ DD− DD1 DD2 V = 1000 V, transient magnitude = CM 800 V At Logic Low Output3 |CM| 25 35 kV/μs V , V , V , V = 0 V, V = L UD+ UD− DD+ DD− CM 1000 V, transient magnitude = 800 V 1 The supply current values for the device running at a fixed continuous data rate at 50% duty cycle alternating J and K states. Supply current values are specified with USB-compliant load present. 2 Propagation delay of the low speed DD+ to UD+ or DD− to UD− in either signal direction is measured from the 50% level of the rising or falling edge to the 50% level of the rising or falling edge of the corresponding output signal. 3 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDx. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. PACKAGE CHARACTERISTICS Table 2. Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input to Output)1 R 1012 Ω I-O Capacitance (Input to Output)1 C 2.2 pF f = 1 MHz I-O Input Capacitance2 C 4.0 pF I IC Junction-to-Ambient Thermal Resistance θ 45 °C/W Thermocouple located at center JA of package underside 1 Device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, and Pin 16 are shorted together. 2 Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM4160 is approved by the organizations listed in Table 3. Refer to Table 8 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 3. UL CSA VDE Recognized under 1577 component Approved under CSA Component Certified according to DIN V VDE V recognition program1 Acceptance Notice #5A 0884-10 (VDE V 0884-10):2006-122 Single Protection Basic insulation per CSA 60950-1-07 and IEC 60950-1, Reinforced insulation, 846 V peak 5000 V rms Isolation Voltage 600 V rms (848 V peak) maximum working voltage. Reinforced insulation per CSA 60950-1-07 and IEC 60950-1, 380 V rms (537 V peak) maximum working voltage, RW-16 package. Reinforced insulation per CSA 60950-1-07 and IEC 60950-1, 400 V rms (565 V peak) maximum working voltage, RI-16 package. Reinforced insulation per IEC 60601-1 125 V rms (176 V peak) maximum working voltage, RW-16 package. Reinforced insulation per IEC 60601-1 250 V rms (353 V peak) maximum working voltage, RI-16 package. File E214100 File 205078 File 2471900-4880-0001 1 In accordance with UL 1577, each ADuM4160 is proof tested by applying an insulation test voltage ≥6000 V rms for 1 sec (current leakage detection limit = 10 μA). 2 In accordance with DIN V VDE V 0884-10, each ADuM4160 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval. Rev. D | Page 4 of 16

Data Sheet ADuM4160 INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 4. Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 5000 V rms 1 minute duration Minimum External Air Gap (Clearance) L(I01) 8.0 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) RW-16 Package L(I02) 7.7 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum External Tracking (Creepage) RI-16 Package L(I02) 8.3 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The * marking on packages denotes DIN V VDE V 0884-10 approval. Table 5. Description Conditions Symbol Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V 846 V peak IORM Input-to-Output Test Voltage, Method b1 V × 1.875 = V , 100% production test, t = 1 sec, V 1590 V peak IORM PR m PR partial discharge < 5 pC Input-to-Output Test Voltage, Method a V × 1.6 = V , t = 60 sec, partial discharge < 5 pC V IORM PR m PR After Environmental Tests Subgroup 1 1375 V peak After Input and/or Safety Test Subgroup 2 V × 1.2 = V , t = 60 sec, partial discharge < 5 pC 1018 V peak IORM PR m and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, t = 10 seconds V 6000 V peak TR TR Safety-Limiting Values Maximum value allowed in the event of a failure (see Figure 2) Case Temperature T 150 °C S Side 1 + Side 2 Current I 550 mA S1 Insulation Resistance at T V = 500 V R >109 Ω S IO S 600 A) m500 T ( N E RR400 U C D1 VD300 G N TI RA200 E P O FE 100 A S 00 50AMBIENT TEM1P00ERATURE (°C1)50 200 08171-002 Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. D | Page 5 of 16

ADuM4160 Data Sheet RECOMMENDED OPERATING CONDITIONS Table 6. Parameter Symbol Min Max Unit Operating Temperature T −40 +105 °C A Supply Voltages1 V , V 3.1 5.5 V BUS1 BUS2 Input Signal Rise and Fall Times 1.0 ms 1 All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields. Rev. D | Page 6 of 16

Data Sheet ADuM4160 ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 7. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational Storage Temperature (T ) −65°C to +150°C ST section of this specification is not implied. Exposure to absolute Ambient Operating Temperature (T) −40°C to +105°C A maximum rating conditions for extended periods may affect Supply Voltages (V , V , V , −0.5 V to +6.5 V BUS1 BUS2 DD1 device reliability. V )1 DD2 Upstream Input Voltage −0.5 V to V + 0.5 V DD1 Table 8. Maximum Continuous Working Voltage1 (V ,V , V )1, 2 UD+ UD− SPU Parameter Max Unit Constraint Downstream Input Voltage −0.5 V to V + 0.5 V DD2 (VDD+, VDD−, VSPD, VPIN)1, 2 AC Voltage, Bipolar 565 V peak 50-year minimum Waveform lifetime Average Output Current per Pin3 AC Voltage, Unipolar Side 1 (I ) −10 mA to +10 mA O1 Waveform Side 2 (I ) −10 mA to +10 mA O2 Basic Insulation 848 V peak Maximum approved Common-Mode Transients4 −100 kV/μs to +100 kV/μs working voltage per IEC 60950-1 1 All voltages are relative to their respective ground. 2 VDDI, VBUS1, and VDD2, VBUS2 refer to the supply voltages on the upstream and Reinforced Insulation 846 V peak Maximum approved downstream sides of the coupler, respectively. working voltage per 3 See Figure 2 for maximum rated current values for various temperatures. VDE 0884-10 4 Refers to common-mode transients across the insulation barrier. Common- DC Voltage mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. Basic Insulation 848 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 846 V peak Maximum approved working voltage per VDE 0884-10 1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information. ESD CAUTION Rev. D | Page 7 of 16

ADuM4160 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VBUS1 1 16 VBUS2 GND1* 2 15 GND2* VDD1 3 ADuM4160 14 VDD2 PDEN 4 TOP VIEW 13 SPD SPU 5 (Not to Scale) 12 PIN UD– 6 11 DD– UD+ 7 10 DD+ GND1* 8 9 GND2* NC = NO CONNECT *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING CBOONTHN ETCOT GEDN,D A1 NISD RCEOCNONMEMCETINNDGE BDO. PTIHN T9O A NGDN DP2IN IS 1 5R EACROEM INMTEENRDNEADL.LY 08171-003 Figure 3. Pin Configuration Table 9. Pin Function Descriptions Pin No. Mnemonic Direction Description 1 V Power Input Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, BUS1 connect V to the USB power bus. Where the isolator is powered from a 3.3 V power supply, connect BUS1 V to V and to the external 3.3 V power supply. Bypass to GND is required. BUS1 DD1 1 2 GND Return Ground 1. Ground reference for Isolator Side 1. 1 3 V Power Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, the V pin DD1 DDI should be used for a bypass capacitor to GND. Signal lines that may require pull up, such as PDEN and 1 SPU, should be tied to this pin. Where the isolator is powered from a 3.3 V power supply, connect V to BUS1 V and to the external 3.3 V power supply. Bypass to GND is required. DD1 1 4 PDEN Input Pull-Down Enable. This pin is read when exiting reset. For standard operation, connect this pin to V . DD1 When connected to GND while exiting from reset, the downstream pull-down resistors are 1 disconnected, allowing buffer impedance measurements. 5 SPU Input Speed Select Upstream Buffer. Active high logic input. Selects full speed slew rate, timing, and logic conventions when SPU is high, and low speed slew rate, timing, and logic conventions when SPU is tied low. This input must be set high via connection to V or set low via connection to GND and must DD1 1 match Pin 13. 6 UD− I/O Upstream D−. 7 UD+ I/O Upstream D+. 8 GND Return Ground 1. Ground reference for Isolator Side 1. 1 9 GND Return Ground 2. Ground reference for Isolator Side 2. 2 10 DD+ I/O Downstream D+. 11 DD− I/O Downstream D−. 12 PIN Input Upstream Pull-Up Enable. PIN controls the power connection to the pull-up for the upstream port. It can be tied to V for operation on power-up, or tied to an external control signal for applications requiring DD2 delayed enumeration. 13 SPD Input Speed Select Downstream Buffer. Active high logic input. Selects full speed slew rate, timing, and logic conventions when SPD is high, and low speed slew rate, timing, and logic conventions when SPD is tied low. This input must be set high via connection to V or low via connection to GND, and must match DD2 2 Pin 5. 14 V Power Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, the V pin DD2 DD2 should be used for a bypass capacitor to GND. Signal lines that may require pull-up, such as SPD, can be 2 tied to this pin. Where the isolator is powered from a 3.3 V power supply, connect V to V and to the BUS2 DD2 external 3.3 V power supply. Bypass to GND is required. 2 15 GND Return Ground 2. Ground reference for Isolator Side 2. 2 16 V Power Input Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, BUS2 connect V to the USB power bus. Where the isolator is powered from a 3.3 V power supply, connect BUS2 V to V and to the external 3.3 V power supply. Bypass to GND is required. BUS2 DD2 2 Rev. D | Page 8 of 16

Data Sheet ADuM4160 Table 10. Truth Table, Control Signals, and Power (Positive Logic)1 V , V , UD+ DD+ V V , V V V V , V V V SPU BUS1 DD1 UD− SPD BUS2 DD2 DD− PIN Input State State Input State State Input Notes H Powered Active H Powered Active H Input and output logic set for full speed logic convention and timing. L Powered Active L Powered Active H Input and output logic set for low speed logic convention and timing. L Powered Active H Powered Active H Not allowed: V and V must be set to the same value. SPU SPD USB host detects communications error. H Powered Active L Powered Active H Not allowed: V and V must be set to the same value. SPU SPD USB host detects communications error. X Powered Z X Powered Z L Upstream Side 1 presents a disconnected state to the USB cable. X Unpowered X X Powered Z X When power is not present on V , the downstream data DD1 output drivers revert to high-Z within 32 bit times. The downstream side initializes in high-Z state. X Powered Z X Unpowered X X When power is not present on V , the upstream side DD2 disconnects the pull-up and disables the upstream drivers within 32 bit times. 1 H represents logic high input or output, L represents logic low input or output, X represents the don’t care logic input or output, and Z represents the high impedance output state. Rev. D | Page 9 of 16

ADuM4160 Data Sheet APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION PRODUCT USAGE USB isolation in the D+/D− lines is challenging for several The ADuM4160 is designed to be integrated into a USB reasons. First, access to the output enable signals is normally peripheral with an upstream facing USB port as shown in required to control a transceiver. Some level of intelligence must Figure 4. The key design points are: be built into the isolator to interpret the data stream and 1. The USB host provides power for the upstream side of the determine when to enable and disable its upstream and down- ADuM4160 through the cable. stream output buffers. Second, the signal must be faithfully 2. The peripheral supply provides power to the downstream reconstructed on the output side of the coupler while retaining side of the ADuM4160. precise timing and not passing transient states such as invalid 3. The DD+/DD− lines of the isolator interface with the SE0 and SE1 states. In addition, the part must meet the low peripheral controller, and the UD+/UD− lines of the power requirements of the suspend mode. isolator connect to the cable or host. The iCoupler technology is based on edge detection, and, 4. Peripheral devices have a fixed data rate that is set at design therefore, lends itself well to the USB application. The flow of time. The ADuM4160 has configuration pins, SPU and data through the device is accomplished by monitoring the SPD, that determine the buffer speed and logic convention inputs for activity and setting the direction for data transfer for each side. These must be set identically and match the based on a transition from the idle (J) state. When data desired peripheral speed. direction is established, data is transferred until either an end- 5. USB enumeration begins when either the UD+ or UD− of-packet (EOP) or a sufficiently long idle state is encountered. line is pulled high at the peripheral end of the USB cable, At this point, the coupler disables its output buffers and which is the upstream side of the ADuM4160. Control of monitors its inputs for the next activity the timing of this event is provided by the PIN input on the downstream side of the coupler. During the data transfers, the input side of the coupler holds its 6. Pull-up and pull-down resistors are implemented inside output buffers disabled. The output side enables its output buffers the coupler. Only external series resistors and bypass and disables edge detection from the input buffers. This allows capacitors are required for operation. the data to flow in one direction without wrapping back through the coupler making the iCoupler latch. Logic is included to PERIPHERAL eliminate any artifacts due to different input thresholds of the VDD2 3.3V differential and single-ended buffers. The input state is transferred VBUS1 VBUS2 across the isolation barrier as one of three valid states, J, K, or DD+ DD+ USB DD– ADuM4160 DD– MICRO- POWER SE0. The signal is reconstructed at the output side with a fixed HOST GND1 PIN CONTROLLER SUPPLY time delay from the input side differential input. The iCoupler does not have a special suspend mode, nor does it 08171-004 need one because its power supply current is below the suspend Figure 4. Typical Application current limit of 2.5 mA when the USB bus is idle. Other than the delayed application of pull-up resistors, the The ADuM4160 is designed to interface with an upstream ADuM4160 is transparent to USB traffic, and no modifications facing low/full speed USB port by isolating the D+/D− lines. to the peripheral design are required to provide isolation. The An upstream facing port supports only one speed of operation, isolator adds propagation delay to the signals comparable to a thus, the speed related parameters, J/K logic levels, and D+/D− hub and cable. Isolated peripherals must be treated as if there slew rate are set to match the speed of the upstream facing were a built-in hub when determining the maximum number of peripheral port (see Table 10). hubs in a data chain. A control line on the downstream side of the ADuM4160 activates Hubs can be isolated like any other peripheral. Isolated hubs a pull-up resistor integrated into the upstream side. This allows can be created by placing an ADuM4160 on the upstream port the downstream port to control when the upstream port attaches of a hub chip. This configuration can be made compliant if to the USB bus. The pin can be tied to the peripheral pull-up, a counted as two hub delays. The hub chip allows the ADuM4160 control line, or the VDD2 pin, depending on when the initial bus to operate at full speed yet maintains compatibility with low connect is to be performed. speed devices. Rev. D | Page 10 of 16

Data Sheet ADuM4160 COMPATIBILITY OF UPSTREAM APPLICATIONS PRINTED CIRCUIT BOARD (PCB) LAYOUT The ADuM4160 digital isolator requires no external interface The ADuM4160 is designed specifically for isolating a USB circuitry for the logic interfaces. For full speed operation, the peripheral. However, the chip does have two USB interfaces that D+ and D− line on each side of the device requires a 24 Ω ± 1% meet the electrical requirements for driving USB cables. This series termination resistor. These resistors are not required for opens the possibility of implementing isolation in downstream low speed applications. Power supply bypassing is required at USB ports such as isolated cables, which have generic connections the input and output supply pins (see Figure 5). Install bypass to both upstream and downstream devices, as well as isolating capacitors between V and V on each side of the chip. The host ports. BUSx DDx capacitor value should have a value of 0.1 μF and be of a low In a fully compliant application, a downstream facing port must ESR type. The total lead length between both ends of the be able to detect whether a peripheral is low speed or full speed capacitor and the power supply pin should not exceed 10 mm. based on the application of the upstream pull-up. The buffers and Bypassing between Pin 2 and Pin 8 and between Pin 9 and logic conventions must adjust to match the requested speed. Pin 15 should also be considered, unless the ground pair on Because the ADuM4160 sets its speed by hard wiring pins, the each package side is connected close to the package. part cannot adjust to different peripherals on the fly. VBUS1= 5.0V INPUT VBUS2= 3.3V INPUT The practical result of using the ADuM4160 in a host port is VDD1 = 3.3V OUTPUT VDD2 = 3.3V INPUT VBUS1 VBUS2 that the port works at a single speed. This behavior is acceptable GND1 GND2 in embedded host applications; however, this type of interface is VDD1 ADuM4160 VDD2 PDEN SPD not fully compliant as a general-purpose USB port. SPU PIN UD– DD– Iasto tlhatee pdr ceasbelte s appepeldic oatniolyn;s t hhaevree fao sriem, tirlaera ti scsaubel. eT ahses ecmabbleli oesp earsa tes GUNDD+1 DGDN+D2 08171-005 custom applications, not general-purpose isolated cables. Figure 5. Recommended Printed Circuit Board Layout POWER SUPPLY OPTIONS In applications involving high common-mode transients, it is important to minimize board coupling across the isolation In most USB transceivers, 3.3 V is derived from the 5 V USB bus barrier. Furthermore, design the board layout such that any through an LDO regulator. The ADuM4160 includes internal coupling that does occur equally affects all pins on a given LDO regulators on both the upstream and downstream sides. component side. Failure to ensure this can cause voltage The output of the LDO is available on the V and V pins. DD1 DD2 differentials between pins exceeding the absolute maximum In some cases, especially on the peripheral side of the isolation, ratings of the device, thereby leading to latch-up or permanent there may not be a 5 V power supply available. The ADuM4160 damage. has the ability to bypass the regulator and run on a 3.3 V supply directly. DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Two power pins are present on each side, V and V . If 5 V BUSx DDx is supplied to VBUSx, an internal regulator creates 3.3 V to power Positive and negative logic transitions at the isolator input the xD+ and xD− drivers. VDDx provides external access to the cause narrow (~1 ns) pulses to be sent to the decoder via the 3.3 V supply to allow external bypass as well as bias for external transformer. The decoder is bistable and is, therefore, either set pull-ups. If only 3.3 V is available, it can be supplied to both or reset by the pulses, indicating input logic transitions. In the VBUSx and VDDx. This disables the regulator and powers the absence of logic transitions at the input for more than about coupler directly from the 3.3 V supply. 12 USB bit times, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the Figure 5 shows how to configure a typical application when the output. If the decoder receives no internal pulses for more than upstream side of the coupler receives power directly from the about 36 USB bit times, the input side is assumed to be unpowered USB bus and the downstream side is receiving 3.3 V from the or nonfunctional, in which case the isolator output is forced to a peripheral power supply. The downstream side can run from a default state (see Table 10) by the watchdog timer circuit. 5 V V power supply as well. It can be connected in the same BUS2 manner as VBUS1 as shown in Figure 5, if needed. Rev. D | Page 11 of 16

ADuM4160 Data Sheet The limitation on the magnetic field immunity of the ADuM4160 1000 is set by the condition in which induced voltage in the receiving A) DISTANCE = 1m k coil of the transformer is sufficiently large to either falsely set or T ( 100 N reset the decoder. The following analysis defines the conditions E R R under which this may occur. The 3 V operating condition of the U C ADuM4160 is examined because it represents the most susceptible LE 10 B mode of operation. WA DISTANCE = 100mm O L 1 The pulses at the transformer output have an amplitude greater L A than 1.0 V. The decoder has a sensing threshold of about 0.5 V, thus UM DISTANCE = 5mm M establishing a 0.5 V margin in which induced voltages are tolerated. XI 0.1 A The voltage induced across the receiving coil is given by M V = (−dβ/dt)∑∏r2; n = 1, 2, … , N 0.01 where: n 1k 10MkAGNET1IC0 0FkIELD FRE1QMUENCY (H1z0)M 100M 08171-007 β is magnetic flux density (gauss). Figure 7. Maximum Allowable Current for Various Current-to-ADuM4160 Spacings N is the number of turns in the receiving coil. r is the radius of the nth turn in the receiving coil (cm). As shown, the ADuM4160 is extremely immune and can be n affected only by extremely large currents operated at high Given the geometry of the receiving coil in the ADuM4160 and frequency very close to the component. For the 1 MHz example an imposed requirement that the induced voltage is, at most, noted, a 0.5 kA current would need to be placed 5 mm away 50% of the 0.5 V margin at the decoder, a maximum allowable from the ADuM4160 to affect the operation of the component. magnetic field is calculated, as shown in Figure 6. 100 Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces can X U induce error voltages sufficiently large enough to trigger the L F 10 C thresholds of succeeding circuitry. Take care in the layout of TI E such traces to avoid this possibility. N Gs) MAuas 1 INSULATION LIFETIME OWABLE NSITY (kg0.1 Atol lv ionlstauglaet siotrne ssst rouvcetru are ssu efvfiecnietunatllyly l obnrega pke drioowdn. T whhee rna tseu objfe cted LE ALD insulation degradation is dependent on the characteristics of the M MU 0.01 voltage waveform applied across the insulation. In addition to AXI the testing performed by the regulatory agencies, Analog M Devices carries out an extensive set of evaluations to determine 0.0011k 10kMAGNETIC10 F0kIELD FREQ1MUENCY (Hz1)0M 100M 08171-006 the lifetime of the insulation structure within the ADuM4160. Figure 6. Maximum Allowable External Magnetic Flux Density Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Accele- For example, at a magnetic field frequency of 1 MHz, the max- ration factors for several operating conditions are determined. imum allowable magnetic field of 0.2 kgauss induces a voltage These factors allow calculation of the time to failure at the actual of 0.25 V at the receiving coil. This is about 50% of the sensing working voltage. The values shown in Table 8 summarize the threshold and does not cause a faulty output transition. Similarly, peak voltage for 50 years of service life for a bipolar ac operating if such an event occurs during a transmitted pulse (and is of the condition, and the maximum CSA/VDE approved working worst-case polarity), it reduces the received pulse from >1.0 V to voltages. In many cases, the approved working voltage is higher 0.75 V—still well above the 0.5 V sensing threshold of the decoder. than 50-year service life voltage. Operation at these high work- The preceding magnetic flux density values correspond to specific ing voltages can lead to shortened insulation life in some cases. current magnitudes at given distances from the ADuM4160 transformers. Figure 7 expresses these allowable current magnitudes as a function of frequency for selected distances. Rev. D | Page 12 of 16

Data Sheet ADuM4160 The insulation lifetime of the ADuM4160 depends on the voltage RATED PEAK VOLTAGE winasvuelfaotiromn tsytprue citmupreo sdeedg raacdroesss a tth dei fisfeorleatnito nra bteasr rdieepr. eTnhdei niCg oounp ler 0V 08171-008 whether the waveform is bipolar ac, unipolar ac, or dc. Figure 8, Figure 8. Bipolar AC Waveform Figure 9, and Figure 10 illustrate these different isolation voltage waveforms. RATED PEAK VOLTAGE Bipolar ac voltage is the most stringent environment. The goal odfe tae r5m0-iyneeasr tohpee Arantainlogg l iDfeetvimicee su rnedceorm thmee ancd bedip molaarx icmonudmit ion 0V 08171-009 Figure 9. Unipolar AC Waveform working voltage. In the case of unipolar ac or dc voltage, the stress on the insula- tion is significantly lower. This allows operation at higher working RATED PEAK VOLTAGE voltages and still achieves a 50-year service life. The working v5o0-ltyaegaers mlisitneidm iunm T alibfleet i8m cea,n p rboev aidppedli etdh awt hthilee vmolatiangtea icnoinnfgo trhmes 0V 08171-010 Figure 10. DC Waveform to either the unipolar ac or dc voltage cases. Treat any cross- insulation voltage waveform that does not conform to Figure 9 or Figure 10 as a bipolar ac waveform and limit its peak voltage to the 50-year lifetime voltage value listed in Table 8. Note that the voltage presented in Figure 9 is shown as sinu- soidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. Rev. D | Page 13 of 16

ADuM4160 Data Sheet OUTLINE DIMENSIONS 10.50(0.4134) 10.10(0.3976) 16 9 7.60(0.2992) 7.40(0.2913) 1 8 10.65(0.4193) 10.00(0.3937) 1.27(0.0500) 0.75(0.0295) BSC 2.65(0.1043) 0.25(0.0098) 45° 0.30(0.0118) 2.35(0.0925) 8° 0.10(0.0039) 0° COPLANARITY 0.10 0.51(0.0201) SPELAATNIENG 0.33(0.0130) 1.27(0.0500) 0.31(0.0122) 0.20(0.0079) 0.40(0.0157) C(RINOEFNPEATRRREOENNLCLTEIHNCEOGOSNDMELISPYM)LAEAIANNRNDSETIAORTRNOOESUJNANEORDDETEEDAICN-POSMPFTRIFALONLMPIDMIRLAELIRATIMTDEEESRTFSMEO;SRIRN-0ECU1QH3SU-EADIVAIINMAELDENENSSTIIOGSNNFS.OR 03-27-2007-B Figure 11. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) 13.00(0.5118) 12.60(0.4961) 16 9 7.60(0.2992) 7.40(0.2913) 1 8 10.65(0.4193) 10.00(0.3937) 0.75(0.0295) 2.65(0.1043) 0.25(0.0098) 45° 0.30(0.0118) 2.35(0.0925) 8° 0.10(0.0039) 0° COPLANARITY 0.10 SEATING (0.10.25700) 0.51(0.0201) PLANE 0.33(0.0130) 1.27(0.0500) BSC 0.31(0.0122) 0.20(0.0079) 0.40(0.0157) C(RINEOFNPEATRRREOENNLCLTEIHNCEOGOSNDMELISPYM)LAEAIANNRNDSETIAORTRNOOESUJNANEORDDETEEDAICN-POSMPFTRIFALONLMPIDMIRLAELIRATIMTDEEESRTFSMEO;SRIRN-0ECU1QH3SU-EADIVCIINMAELDENENSSTIIOGSNNFS.OR 10-12-2010-A Figure 12. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] Wide Body (RI-16-1) Dimensions shown in millimeters and (inches) ORDERING GUIDE Number Number Maximum Maximum of Inputs, of Inputs, Data Rate Propagation Maximum Package Model1, 2 VDD1 Side VDD2 Side (Mbps) Delay, 5 V (ns) Jitter (ns) Temperature Range Package Description Option ADuM4160BRWZ 2 2 12 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM4160BRWZ-RL 2 2 12 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM4160BRIZ 2 2 12 70 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-1 ADuM4160BRIZ-RL 2 2 12 70 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-1 EVAL-ADUM4160EBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 For all devices listed, specifications represent full speed buffer configuration. Rev. D | Page 14 of 16

Data Sheet ADuM4160 NOTES Rev. D | Page 15 of 16

ADuM4160 Data Sheet NOTES ©2009–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08171-0-2/12(D) Rev. D | Page 16 of 16

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