PWM Controller and Transformer Driver with Quad-Channel Isolators Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 FEATURES FUNCTIONAL BLOCK DIAGRAMS Isolated PWM controller T1 Integrated transformer driver VDD1 RECT VISO Regulated adjustable output: 3.3 V to 24 V X1 X2 VREG 2 W output power ADuM3470/ADuM3471/ ADuM3472/ADuM3473/ 70% efficiency at guaranteed load of 400 mA at 5.0 V output VDDA DRIVER ADuM3474 REG VDD2 Quad dc-to-25 Mbps (NRZ) signal isolation channels FB 5V PRIMARY 20-lead SSOP package CONVERTER SECONDARY FB CONTROLLER High temperature operation: 105°C maximum OC CH A High common-mode transient immunity: >25 kV/µs 200 kHz to 1 MHz adjustable oscillator frequency VIA/VOA PRIMARY CH B SECONDARY VIA/VOA Soft start function at power-up DATA DATA Pulse-by-pulse overcurrent protection VIB/VOB 4IC/OH CH C 4IC/OH VIB/VOB Thermal shutdown VIC/VOC CH D VIC/VOC SaUfeLt yre acnodg nreitgiuolna:t 2o5ry0 0a pVp rrmosv afolsr 1 minute per UL 1577 VID/VOD GND1 GND2 VID/VOD 09369-001 CSA Component Acceptance Notice #5A Figure 1. Functional Block Diagram VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 ADuM3470 ADuM3471 V = 560 V peak IORM Qualified for automotive applications APPLICATIONS RS-232/RS-422/RS-485 transceivers Industrial field bus isolation Power supply start-up bias and gate drives Isolated sensor interfaces Process controls ADuM3472 Automotive GENERAL DESCRIPTION The ADuM3470/ADuM3471/ADuM3472/ADuM3473/ ADuM3474 devices1 are quad-channel digital isolators with an integrated PWM controller and transformer driver for an isolated dc-to-dc converter. Based on the Analog Devices, Inc., iCoupler® technology, the dc-to-dc converter provides up to 2 W of regulated, isolated power at 3.3 V to 24 V from a 5.0 V input supply or from ADuM3473 ADuM3474 a 3.3 V supply. This eliminates the need for a separate, isolated dc-to-dc converter in 2 W isolated designs. The iCoupler chip scale transformer technology is used to isolate the logic signals, and the integrated transformer driver with isolated secondary side control provides higher efficiency for the isolated dc-to-dc converter. The result is a small form factor, total isolation solution. The ADuM347x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). 09369-003 Figure 2. Block Diagrams of I/O Channels 1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 19 Applications ....................................................................................... 1 Terminology .................................................................................... 24 General Description ......................................................................... 1 Applications Information .............................................................. 25 Functional Block Diagrams ............................................................. 1 Application Schematics ............................................................. 25 Revision History ............................................................................... 2 Transformer Design ................................................................... 26 Specifications ..................................................................................... 3 Transformer Turns Ratio ........................................................... 26 Electrical Characteristics—5 V Primary Input Supply/ Transformer ET Constant ......................................................... 27 5 V Secondary Isolated Supply ................................................... 3 Transformer Primary Inductance and Resistance ................. 27 Electrical Characteristics—3.3 V Primary Input Supply/ Transformer Isolation Voltage .................................................. 27 3.3 V Secondary Isolated Supply ................................................ 5 Switching Frequency .................................................................. 27 Electrical Characteristics—5 V Primary Input Supply/ 3.3 V Secondary Isolated Supply ................................................ 7 Transient Response .................................................................... 27 Component Selection ................................................................ 27 Electrical Characteristics—5 V Primary Input Supply/ 15 V Secondary Isolated Supply ................................................. 9 Printed Circuit Board (PCB) Layout ....................................... 28 Package Characteristics ............................................................. 11 Thermal Analysis ....................................................................... 28 Regulatory Approvals ................................................................. 11 Propagation Delay-Related Parameters ................................... 28 Insulation and Safety-Related Specifications .......................... 11 DC Correctness and Magnetic Field Immunity ..................... 29 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Power Consumption .................................................................. 30 Insulation Characteristics .......................................................... 12 Power Considerations ................................................................ 30 Recommended Operating Conditions .................................... 12 Insulation Lifetime ..................................................................... 31 Absolute Maximum Ratings .......................................................... 13 Outline Dimensions ....................................................................... 32 ESD Caution ................................................................................ 13 Ordering Guide .......................................................................... 33 Pin Configurations and Function Descriptions ......................... 14 Automotive Products ................................................................. 33 REVISION HISTORY 5/14—Rev. A to Rev. B Changes to Figure 6 and Table 14................................................. 16 Change to Table 4 ............................................................................. 9 Changes to Figure 7 and Table 15................................................. 17 Changes to Figure 8, Table 16, and Table 17 ............................... 18 7/13—Rev. 0 to Rev. A Change to Figure 9 ......................................................................... 19 Changed V Pin to NC Pin ....................................... Throughout Changes to Terminology Section ................................................. 24 DD1 Changes to Features Section, Applications Section, Changes to Applications Information Section, Application General Description Section, and Figure 1 ................................... 1 Schematics Section, Figure 38, Figure 39, and Figure 40 .......... 25 Created Hyperlink for Safety and Regulatory Approvals Changes to Transformer Turns Ratio Section ............................ 26 Entry in Features Section ................................................................. 1 Changes to Transformer ET Constant Section, Changes to Table 1 ............................................................................ 3 Transient Response Section, and Table 19 .................................. 27 Changes to Table 2 ............................................................................ 5 Changes to Figure 41 ...................................................................... 28 Changes to Table 3 ............................................................................ 7 Changes to Power Consumption Section and Figure 45 ........... 30 Changes to Table 4 ............................................................................ 9 Changes to Insulation Lifetime Section and Figure 48 ............. 31 Changes to Regulatory Approvals Section .................................. 11 Changes to Ordering Guide .......................................................... 33 Changes to Figure 3 and Table 9 ................................................... 12 Added Automotive Products Section .......................................... 33 Changes to Figure 4 and Table 12 ................................................. 14 Changes to Figure 5 and Table 13 ................................................. 15 10/10—Revision 0: Initial Version Rev. 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Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY 4.5 V ≤ V = V ≤ 5.5 V; V = V = V = 5.0 V; f = 500 kHz; all voltages are relative to their respective grounds (see the DD1 DDA DD2 REG ISO SW application schematic in Figure 38). All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at T = 25°C, V = V = 5.0 V, V = V = V = 5.0 V. A DD1 DDA DD2 REG ISO Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC-TO-DC CONVERTER POWER SUPPLY Isolated Output Voltage V 4.5 5.0 5.5 V I = 0 mA, V = V × (R1 + R2)/R2 ISO ISO ISO FB Feedback Voltage Setpoint V 1.125 1.25 1.375 V I = 0 mA FB ISO Line Regulation V 1 10 mV/V I = 50 mA, V = 4.5 V to 5.5 V ISO (LINE) ISO DD1 Load Regulation V 1 2 % I = 50 mA to 200 mA ISO (LOAD) ISO Output Ripple V 50 mV p-p 20 MHz bandwidth, ISO (RIP) C = 0.1 µF||47 µF, I = 100 mA OUT ISO Output Noise V 100 mV p-p 20 MHz bandwidth, ISO (N) C = 0.1 µF||47 µF, I = 100 mA OUT ISO Switching Frequency f 1000 kHz R = 50 kΩ SW OC 200 kHz R = 270 kΩ OC 192 318 515 kHz V = V (open loop) OC DD2 Switch On Resistance R 0.5 Ω ON Undervoltage Lockout, V , V DD1 DD2 Supplies Positive Going Threshold V 2.8 V UV+ Negative Going Threshold V 2.6 V UV− Hysteresis V 0.2 V UVH DC to 2 Mbps Data Rate1 f ≤ 1 MHz Maximum Output Supply Current2 I 400 mA V = 5.0 V ISO (MAX) ISO Efficiency at Maximum Output 70 % I = I ISO ISO(MAX) Supply Current3 iCOUPLER DATA CHANNELS DC to 2 Mbps Data Rate1 I Supply Current, No V Load I I = 0 mA, f ≤ 1 MHz DD1 ISO DD1 (Q) ISO ADuM3470 14 30 mA ADuM3471 15 30 mA ADuM3472 16 30 mA ADuM3473 17 30 mA ADuM3474 18 30 mA 25 Mbps Data Rate (C Grade Only) I Supply Current, No V Load I I = 0 mA, C = 15 pF, f = 12.5 MHz DD1 ISO DD1 (D) ISO L ADuM3470 44 mA ADuM3471 46 mA ADuM3472 48 mA ADuM3473 50 mA ADuM3474 52 mA Available V Supply Current4 I C = 15 pF, f = 12.5 MHz ISO ISO (LOAD) L ADuM3470 390 mA ADuM3471 388 mA ADuM3472 386 mA ADuM3473 384 mA ADuM3474 382 mA I Supply Current, Full V Load I 550 mA C = 0 pF, f = 0 MHz, V = 5 V, DD1 ISO DD1 (MAX) L DD1 I = 400 mA ISO Rev. B | Page 3 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments I/O Input Currents I , I , I , I −20 +0.01 +20 µA IA IB IC ID Logic High Input Threshold V 2.0 V IH Logic Low Input Threshold V 0.8 V IL Logic High Output Voltages V , V , V − 0.3, 5.0 V I = −20 µA, V = V OAH OBH DD1 Ox Ix IxH V , V V − 0.3 OCH ODH ISO V − 0.5, 4.8 V I = −4 mA, V = V DD1 Ox Ix IxH V − 0.5 ISO Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL V , V OCL ODL 0.0 0.4 V I = 4 mA, V = V Ox Ix IxL AC SPECIFICATIONS A Grade C = 15 pF, CMOS signal levels L Minimum Pulse Width PW 1000 ns Maximum Data Rate 1 Mbps Propagation Delay t , t 55 100 ns PHL PLH Pulse Width Distortion, |t − t | PWD 40 ns PLH PHL Propagation Delay Skew t 50 ns PSK Channel-to-Channel Matching t /t 50 ns PSKCD PSKOD C Grade C = 15 pF, CMOS signal levels L Minimum Pulse Width PW 40 ns Maximum Data Rate 25 Mbps Propagation Delay t , t 30 45 60 ns PHL PLH Pulse Width Distortion, |t − t | PWD 8 ns PLH PHL Change vs. Temperature 5 ps/°C Propagation Delay Skew t 15 ns PSK Channel-to-Channel Matching Codirectional Channels t 8 ns PSKCD Opposing Directional Channels t 15 ns PSKOD Output Rise/Fall Time (10% to 90%) t/t 2.5 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity V = 1000 V, transient CM magnitude = 800 V At Logic High Output |CM | 25 35 kV/µs V = V or V H Ix DD1 ISO At Logic Low Output |CM| 25 35 kV/µs V = 0 V L Ix Refresh Rate f 1.0 Mbps r 1 The contributions of supply current values for all four channels are combined at identical data rates. 2 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget. 3 The power demands of the quiescent operation of the data channels is not separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of the internal power consumption. 4 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of the available current at less than the maximum data rate. Rev. B | Page 4 of 36

Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY 3.0 V ≤ V = V ≤ 3.6 V; V = V = V = 3.3 V; f = 500 kHz; all voltages are relative to their respective grounds (see the DD1 DDA DD2 REG ISO SW application schematic in Figure 38). All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at T = 25°C, V = V = 3.3 V, V = V = V = 3.3 V. A DD1 DDA DD2 REG ISO Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC-TO-DC CONVERTER POWER SUPPLY Isolated Output Voltage V 3.0 3.3 3.6 V I = 0 mA, V = V × (R1 + R2)/R2 ISO ISO ISO FB Feedback Voltage Setpoint V 1.125 1.25 1.375 V I = 0 mA FB ISO Line Regulation V 1 10 mV/V I = 50 mA, V = 3.0 V to 3.6 V ISO (LINE) ISO DD1 Load Regulation V 1 2 % I = 20 mA to 100 mA ISO (LOAD) ISO Output Ripple V 50 mV p-p 20 MHz bandwidth, ISO (RIP) C = 0.1 µF||47 µF, I = 100 mA OUT ISO Output Noise V 100 mV p-p 20 MHz bandwidth, ISO (N) C = 0.1 µF||47 µF, I = 100 mA OUT ISO Switching Frequency f 1000 kHz R = 50 kΩ SW OC 200 kHz R = 270 kΩ OC 192 318 515 kHz V = V (open loop) OC DD2 Switch On Resistance R 0.6 Ω ON Undervoltage Lockout, V , V DD1 DD2 Supplies Positive Going Threshold V 2.8 V UV+ Negative Going Threshold V 2.6 V UV− Hysteresis V 0.2 V UVH DC to 2 Mbps Data Rate1 f ≤ 1 MHz, Maximum Output Supply Current2 I 250 mA V = 3.3 V ISO (MAX) ISO Efficiency at Maximum Output 70 % I = I ISO ISO(MAX) Supply Current3 iCOUPLER DATA CHANNELS DC to 2 Mbps Data Rate1 I Supply Current, No V Load I I = 0 mA, f ≤ 1 MHz DD1 ISO DD1 (Q) ISO ADuM3470 9 20 mA ADuM3471 10 20 mA ADuM3472 11 20 mA ADuM3473 11 20 mA ADuM3474 12 20 mA 25 Mbps Data Rate (C Grade Only) I Supply Current, No V Load I I = 0 mA, C = 15 pF, f = 12.5 MHz DD1 ISO DD1 (D) ISO L ADuM3470 28 mA ADuM3471 29 mA ADuM3472 31 mA ADuM3473 32 mA ADuM3474 34 mA Available V Supply Current4 I C = 15 pF, f = 12.5 MHz ISO ISO (LOAD) L ADuM3470 244 mA ADuM3471 243 mA ADuM3472 241 mA ADuM3473 240 mA ADuM3474 238 mA I Supply Current, Full V Load I 350 mA C = 0 pF, f = 0 MHz, V = 3.3 V, DD1 ISO DD1 (MAX) L DD1 I = 250 mA ISO I/O Input Currents I , I , I , I −10 +0.01 +10 µA IA IB IC ID Rev. B | Page 5 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments Logic High Input Threshold V 1.6 V IH Logic Low Input Threshold V 0.4 V IL Logic High Output Voltages V , V , V − 0.3, 5.0 V I = −20 µA, V = V OAH OBH DD1 Ox Ix IxH V , V V − 0.3 OCH ODH ISO V − 0.5, 4.8 V I = −4 mA, V = V DD1 Ox Ix IxH V − 0.5 ISO Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL V , V OCL ODL 0.0 0.4 V I = 4 mA, V = V Ox Ix IxL AC SPECIFICATIONS A Grade C = 15 pF, CMOS signal levels L Minimum Pulse Width PW 1000 ns Maximum Data Rate 1 Mbps Propagation Delay t , t 60 100 ns PHL PLH Pulse Width Distortion, |t − t | PWD 40 ns PLH PHL Propagation Delay Skew t 50 ns PSK Channel-to-Channel Matching t /t 50 ns PSKCD PSKOD C Grade C = 15 pF, CMOS signal levels L Minimum Pulse Width PW 40 ns Maximum Data Rate 25 Mbps Propagation Delay t , t 30 60 75 ns PHL PLH Pulse Width Distortion, |t − t | PWD 8 ns PLH PHL Change vs. Temperature 5 ps/°C Propagation Delay Skew t 45 ns PSK Channel-to-Channel Matching Codirectional Channels t 8 ns PSKCD Opposing Directional Channels t 15 ns PSKOD Output Rise/Fall Time (10% to 90%) t/t 2.5 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity V = 1000 V, transient CM magnitude = 800 V At Logic High Output |CM | 25 35 kV/µs V = V or V H Ix DD1 ISO At Logic Low Output |CM| 25 35 kV/µs V = 0 V L Ix Refresh Rate f 1.0 Mbps r 1 The contributions of supply current values for all four channels are combined at identical data rates. 2 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget. 3 The power demands of the quiescent operation of the data channels is not separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of the internal power consumption. 4 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of the available current at less than the maximum data rate. Rev. B | Page 6 of 36

Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY 4.5 V ≤ V = V ≤ 5.5 V; V = V = V = 3.3 V; f = 500 kHz; all voltages are relative to their respective grounds (see the DD1 DDA DD2 REG ISO SW application schematic in Figure 38). All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at T = 25°C, V = V = 5.0 V, V = V = V = 3.3 V. A DD1 DDA DD2 REG ISO Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC-TO-DC CONVERTER POWER SUPPLY Isolated Output Voltage V 3.0 3.3 3.6 V I = 0 mA, V = V × (R1 + R2)/R2 ISO ISO ISO FB Feedback Voltage Setpoint V 1.125 1.25 1.375 V I = 0 mA FB ISO Line Regulation V 1 10 mV/V I = 50 mA, V = 4.5 V to 5.5 V ISO (LINE) ISO DD1 Load Regulation V 1 2 % I = 50 mA to 200 mA ISO (LOAD) ISO Output Ripple V 50 mV p-p 20 MHz bandwidth, ISO (RIP) C = 0.1 µF||47 µF, I = 100 mA OUT ISO Output Noise V 100 mV p-p 20 MHz bandwidth, ISO (N) C = 0.1 µF||47 µF, I = 100 mA OUT ISO Switching Frequency f 1000 kHz R = 50 kΩ SW OC 200 kHz R = 270 kΩ OC 192 318 515 kHz V = V (open loop) OC DD2 Switch On Resistance R 0.5 Ω ON Undervoltage Lockout, V , V DD1 DD2 Supplies Positive Going Threshold V 2.8 V UV+ Negative Going Threshold V 2.6 V UV− Hysteresis V 0.2 V UVH DC to 2 Mbps Data Rate1 f ≤ 1 MHz Maximum Output Supply Current2 I 400 mA V = 3.3 V ISO (MAX) ISO Efficiency at Maximum Output 70 % I = I ISO ISO(MAX) Supply Current3 iCOUPLER DATA CHANNELS DC to 2 Mbps Data Rate1 I Supply Current, No V Load I I = 0 mA, f ≤ 1 MHz DD1 ISO DD1 (Q) ISO ADuM3470 9 30 mA ADuM3471 9 30 mA ADuM3472 10 30 mA ADuM3473 10 30 mA ADuM3474 10 30 mA 25 Mbps Data Rate (C Grade Only) I Supply Current, No V Load I I = 0 mA, C = 15 pF, f = 12.5 MHz DD1 ISO DD1 (D) ISO L ADuM3470 33 mA ADuM3471 33 mA ADuM3472 33 mA ADuM3473 33 mA ADuM3474 33 mA Available V Supply Current4 I C = 15 pF, f = 12.5 MHz ISO ISO (LOAD) L ADuM3470 393 mA ADuM3471 392 mA ADuM3472 390 mA ADuM3473 389 mA ADuM3474 388 mA I Supply Current, Full V Load I 375 mA C = 0 pF, f = 0 MHz, V = 5 V, DD1 ISO DD1 (MAX) L DD1 I = 400 mA ISO I/O Input Currents I , I , I , I −20 +0.01 +20 µA IA IB IC ID Rev. B | Page 7 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments Logic High Input Threshold V 2.0 V IH Logic Low Input Threshold V 0.8 V IL Logic High Output Voltages V , V , V − 0.3, 5.0 V I = −20 µA, V = V OAH OBH DD1 Ox Ix IxH V , V V − 0.3 OCH ODH ISO V − 0.5, 4.8 V I = −4 mA, V = V DD1 Ox Ix IxH V − 0.5 ISO Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL V , V OCL ODL 0.0 0.4 V I = 4 mA, V = V Ox Ix IxL AC SPECIFICATIONS A Grade C = 15 pF, CMOS signal levels L Minimum Pulse Width PW 1000 ns Maximum Data Rate 1 Mbps Propagation Delay t , t 55 100 ns PHL PLH Pulse Width Distortion, |t − t | PWD 40 ns PLH PHL Propagation Delay Skew t 50 ns PSK Channel-to-Channel Matching t /t 50 ns PSKCD PSKOD C Grade C = 15 pF, CMOS signal levels L Minimum Pulse Width PW 40 ns Maximum Data Rate 25 Mbps Propagation Delay t , t 30 50 70 ns PHL PLH Pulse Width Distortion, |t − t | PWD 8 ns PLH PHL Change vs. Temperature 5 ps/°C Propagation Delay Skew t 15 ns PSK Channel-to-Channel Matching Codirectional Channels t 8 ns PSKCD Opposing Directional Channels t 15 ns PSKOD Output Rise/Fall Time (10% to 90%) t/t 2.5 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity V = 1000 V, transient CM magnitude = 800 V At Logic High Output |CM | 25 35 kV/µs V = V or V H Ix DD1 ISO At Logic Low Output |CM| 25 35 kV/µs V = 0 V L Ix Refresh Rate f 1.0 Mbps r 1 The contributions of supply current values for all four channels are combined at identical data rates. 2 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget. 3 The power demands of the quiescent operation of the data channels is not separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of the internal power consumption. 4 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of the available current at less than the maximum data rate. Rev. B | Page 8 of 36

Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/15 V SECONDARY ISOLATED SUPPLY 4.5 V ≤ V = V ≤ 5.5 V; V = V = 15 V; V = 5.0 V; f = 500 kHz; all voltages are relative to their respective grounds (see the DD1 DDA REG ISO DD2 SW application schematic in Figure 39). All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at T = 25°C, V = V = 5.0 V, V = V = 15 V, V = 5.0 V. A DD1 DDA REG ISO DD2 Table 4. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC-TO-DC CONVERTER POWER SUPPLY Isolated Output Voltage V 13.5 15 16.5 V I = 0 mA, V = V × (R1 + R2)/R2 ISO ISO ISO FB Feedback Voltage Setpoint V 1.125 1.25 1.375 V I = 0 mA FB ISO V Linear Regulator DD2 Regulator Voltage V 4.6 5.0 5.7 V V = 7 V to 15 V, I = 0 mA DD2 REG DD2 to 50 mA Dropout Voltage V 0.5 1.5 V I = 50 mA DD2 (DO) DD2 Line Regulation V 1 20 mV/V I = 50 mA, V = 4.5 V to 5.5 V ISO (LINE) ISO DD1 Load Regulation V 1 3 % I = 20 mA to 100 mA ISO (LOAD) ISO Output Ripple V 200 mV p-p 20 MHz bandwidth, ISO (RIP) C = 0.1 µF||47 µF, I = 100 mA OUT ISO Output Noise V 500 mV p-p 20 MHz bandwidth, ISO (N) C = 0.1 µF||47 µF, I = 100 mA OUT ISO Switching Frequency f 1000 kHz R = 50 kΩ SW OC 200 kHz R = 270 kΩ OC 192 318 515 kHz V = V (open loop) OC DD2 Switch On Resistance R 0.5 Ω ON Undervoltage Lockout, V , V Supplies DD1 DD2 Positive Going Threshold V 2.8 V UV+ Negative Going Threshold V 2.6 V UV− Hysteresis V 0.2 V UVH DC to 2 Mbps Data Rate1 f ≤ 1 MHz Maximum Output Supply Current2 I 100 mA V = 5.0 V ISO (MAX) ISO Efficiency at Maximum Output 70 % I = I ISO ISO(MAX) Supply Current3 iCOUPLER DATA CHANNELS DC to 2 Mbps Data Rate1 I Supply Current, No V Load I I = 0 mA, f ≤ 1 MHz DD1 ISO DD1 (Q) ISO ADuM3470 25 45 mA ADuM3471 27 45 mA ADuM3472 29 45 mA ADuM3473 31 45 mA ADuM3474 33 45 mA 25 Mbps Data Rate (C Grade Only) I Supply Current, No V Load I I = 0 mA, C = 15 pF, f = 12.5 MHz DD1 ISO DD1 (D) ISO L ADuM3470 73 mA ADuM3471 83 mA ADuM3472 93 mA ADuM3473 102 mA ADuM3474 112 mA Available V Supply Current4 I C = 15 pF, f = 12.5 MHz ISO ISO (LOAD) L ADuM3470 91 mA ADuM3471 89 mA ADuM3472 86 mA ADuM3473 83 mA ADuM3474 80 mA I Supply Current, Full V Load I 425 mA C = 0 pF, f = 0 MHz, V = 5 V, DD1 ISO DD1 (MAX) L DD1 I = 100 mA ISO Rev. B | Page 9 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments I/O Input Currents I , I , I , I −20 +0.01 +20 µA IA IB IC ID Logic High Input Threshold V 2.0 V IH Logic Low Input Threshold V 0.8 V IL Logic High Output Voltages V , V , V − 0.3, 5.0 V I = −20 µA, V = V OAH OBH DD1 Ox Ix IxH V , V V − 0.3 OCH ODH ISO V − 0.5, 4.8 V I = −4 mA, V = V DD1 Ox Ix IxH V − 0.5 ISO Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL V , V OCL ODL 0.0 0.4 V I = 4 mA, V = V Ox Ix IxL AC SPECIFICATIONS A Grade C = 15 pF, CMOS signal levels L Minimum Pulse Width PW 1000 ns Maximum Data Rate 1 Mbps Propagation Delay t , t 55 100 ns PHL PLH Pulse Width Distortion, |t − t | PWD 40 ns PLH PHL Propagation Delay Skew t 50 ns PSK Channel-to-Channel Matching t /t 50 ns PSKCD PSKOD C Grade C = 15 pF, CMOS signal levels L Minimum Pulse Width PW 40 ns Maximum Data Rate 25 Mbps Propagation Delay t , t 30 45 60 ns PHL PLH Pulse Width Distortion, |t − t | PWD 8 ns PLH PHL Change vs. Temperature 5 ps/°C Propagation Delay Skew t 15 ns PSK Channel-to-Channel Matching Codirectional Channels t 8 ns PSKCD Opposing Directional Channels t 15 ns PSKOD Output Rise/Fall Time (10% to 90%) t/t 2.5 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity V = 1000 V, transient CM magnitude = 800 V At Logic High Output |CM | 25 35 kV/µs V = V or V H Ix DD1 ISO At Logic Low Output |CM| 25 35 kV/µs V = 0 V L Ix Refresh Rate f 1.0 Mbps r 1 The contributions of supply current values for all four channels are combined at identical data rates. 2 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget. 3 The power demands of the quiescent operation of the data channels is not separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of the internal power consumption. 4 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of the available current at less than the maximum data rate. Rev. B | Page 10 of 36

Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 PACKAGE CHARACTERISTICS Table 5. Parameter Symbol Min Typ Max Unit Test Conditions/Comments RESISTANCE AND CAPACITANCE Resistance (Input to Output)1 R 1012 Ω I-O Capacitance (Input to Output)1 C 2.2 pF f = 1 MHz I-O Input Capacitance2 C 4.0 pF I IC Junction to Ambient Thermal θ 50.5 °C/W Thermocouple is located at the center of JA Resistance the package underside; test conducted on a 4-layer board with thin traces3 THERMAL SHUTDOWN Thermal Shutdown Threshold TS 150 °C T rising SD J Thermal Shutdown Hysteresis TS 20 °C SD-HYS 1 The device is considered a 2-terminal device: Pin 1 to Pin 10 are shorted together, and Pin 11 to Pin 20 are shorted together. 2 Input capacitance is from any input data pin to ground. 3 See the Thermal Analysis section for thermal model definitions. REGULATORY APPROVALS The ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 are approved by the organizations listed in Table 6. Refer to Table 11 and the Insulation Lifetime section for more information about the recommended maximum working voltages for specific cross-insulation waveforms and insulation levels. Table 6. UL CSA VDE Recognized under the UL 1577 component Approved under CSA Component Acceptance Certified according to DIN V VDE V 0884-10 recognition program1 Notice #5A (VDE V 0884-10):2006-122 Single protection, 2500 V rms isolation Basic insulation per CSA 60950-1-03 and Reinforced insulation, 560 V peak voltage IEC 60950-1, 600 V rms (848 V peak) maximum working voltage File E214100 File 205078 File 2471900-4880-0001 1 In accordance with UL 1577, each ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 is proof tested by applying an insulation test voltage of ≥3000 V rms for 1 sec (current leakage detection limit = 10 µA). 2 In accordance with DIN V VDE V 0884-10 (VDE V 0884-10):2006-12, each ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 is proof tested by applying an insulation test voltage of ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 7. Parameter Symbol Value Unit Test Conditions/Comments Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) >5.1 mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) >5.1 mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Distance (Internal Clearance) 0.017 min mm Distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303, Part 1 Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1) Rev. B | Page 11 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking branded on the component denotes DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 approval. Table 8. Description Test Conditions/Comments Symbol Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V 560 V peak IORM Input-to-Output Test Voltage, Method B1 V × 1.875 = V , 100% production test, t = 1 sec, V 1050 V peak IORM PR m PR partial discharge < 5 pC Input-to-Output Test Voltage, Method A V PR After Environmental Tests Subgroup 1 V × 1.6 = V , t = 60 sec, partial discharge < 5 pC 896 V peak IORM PR m After Input and/or Safety Tests Subgroup 2 V × 1.2 = V , t = 60 sec, partial discharge < 5 pC 672 V peak IORM PR m and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, t = 10 sec V 4000 V peak TR TR Safety Limiting Values Maximum value allowed in the event of a failure (see Figure 3) Case Temperature T 150 °C S Side 1 Current I 1.25 A S1 Insulation Resistance at T V = 500 V R >109 Ω S IO S 1.50 A)1.25 T ( N E R R1.00 U C D1 VD0.75 G N TI RA0.50 E P O E F0.25 A S 00 50 CASE TEMP1E0R0ATURE (°C)150 200 09369-002 Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2 RECOMMENDED OPERATING CONDITIONS Table 9. Parameter Symbol Min Max Unit Operating Temperature T −40 +105 °C A Supply Voltages1 V at V = 3.3 V V 3.0 3.6 V DD1 ISO DD1 V at V = 5.0 V V 3.0 3.6 V DD1 ISO DD1 V at V = 5.0 V V 4.5 5.5 V DD1 ISO DD1 Minimum Load I 10 mA ISO (MIN) 1 All voltages are relative to their respective grounds. Rev. B | Page 12 of 36

Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Table 11. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime1 Table 10. Applicable Parameter Rating Parameter Max Unit Certification Storage Temperature Range (TST) −55°C to +150°C AC Voltage, Bipolar 565 V peak All certifications Ambient Operating Temperature −40°C to +105°C Waveform Range (TA) AC Voltage, Unipolar Supply Voltages1 Waveform VDD1,2 VDDA, VDD2 −0.5 V to +7.0 V Basic Insulation 848 V peak Working voltage V , X1, X2 −0.5 V to +20.0 V per IEC 60950-1 REG Input Voltage (V , V , V , V )1, 3 −0.5 V to V + 0.5 V DC Voltage IA IB IC ID DDI Output Voltage (V , V , V , V )1, 3 −0.5 V to V + 0.5 V Basic Insulation 848 V peak Working voltage OA OB OC OD DDO per IEC 60950-1 Average Output Current per Pin4 −10 mA to +10 mA Common-Mode Transients5 −100 kV/µs to +100 kV/µs 1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information. 1 All voltages are relative to their respective grounds. 2 VDD1 is the power supply for the push-pull transformer. ESD CAUTION 3 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the Printed Circuit Board (PCB) Layout section. 4 See Figure 3 for maximum rated current values for various temperatures. 5 Refers to common-mode transients across the insulation barrier. Common- mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 13 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS X1 1 20 VREG *GND1 2 19 GND2* NC 3 18 VDD2 X2 4 ADuM3470 17 FB VIA 5 TOP VIEW 16 VOA VIB 6 (Not to Scale) 15 VOB VIC 7 14 VOC VID 8 13 VOD VDDA 9 12 OC *GND1 10 11 GND2* NOTES 1. NC = NO INTERNAL CONNECTION. 2. PIN 2AND PIN 10ARE INTERNALLY CONNECTEDTO EACH OTHER; IT IS RPRIEENCC1OO1MMAMMNEEDNN PDDINEE DD1 9TTHHAAARTTE BBINOOTTTEHHR PPNIIANNLSSL YBB EEC OCCOONNNNENNCEETCCETTDEEDDTOTTOO E AAA CCCHOO OMMTMMHOOENNR ;GG IRRTOO ISUUNNDD.. 09369-004 Figure 4. ADuM3470 Pin Configuration Table 12. ADuM3470 Pin Function Descriptions Pin No. Mnemonic Description 1 X1 Transformer Driver Output 1. 2, 10 GND Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 10 are internally connected to each other; 1 it is recommended that both pins be connected to a common ground. 3 NC No Internal Connection. 4 X2 Transformer Driver Output 2. 5 V Logic Input A. IA 6 V Logic Input B. IB 7 V Logic Input C. IC 8 V Logic Input D. ID 9 V Supply Voltage for the Primary Side, 3.0 V to 5.5 V. Connect a 0.1 μF bypass capacitor from V to GND. DDA DDA 1 11, 19 GND Ground Reference for the Secondary Side of the Isolator. Pin 11 and Pin 19 are internally connected to each other; 2 it is recommended that both pins be connected to a common ground. 12 OC Oscillator Control Pin. When the OC pin is connected high to the V pin, the secondary controller runs in open- DD2 loop (unregulated) mode. To regulate the output voltage, connect a resistor between the OC pin and GND; the 2 secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value. 13 V Logic Output D. OD 14 V Logic Output C. OC 15 V Logic Output B. OB 16 V Logic Output A. OA 17 FB Feedback Input from the Secondary Output Voltage, V . Use a resistor divider from the V output to the FB pin ISO ISO to set the V voltage equal to the 1.25 V internal reference level using the formula V = V × (R1 + R2)/R2. The FB ISO FB resistor divider is required even in open-loop mode to provide soft start. 18 V Internal Supply Voltage for the Secondary Side Controller and the Side 2 Data Channels. When a sufficient external DD2 voltage is supplied to V , the internal regulator regulates the V pin to 5.0 V. Otherwise, V should be in the REG DD2 DD2 3.0 V to 5.5 V range. Connect a 0.1 μF bypass capacitor from V to GND. DD2 2 20 V Input of the Internal Regulator to Power the Secondary Side Controller and the Side 2 Data Channels. V should REG REG be in the 5.5 V to 15 V range to regulate the V output to 5.0 V. DD2 Rev. B | Page 14 of 36

Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 X1 1 20 VREG *GND1 2 19 GND2* NC 3 18 VDD2 X2 4 ADuM3471 17 FB VIA 5 TOP VIEW 16 VOA VIB 6 (Not to Scale) 15 VOB VIC 7 14 VOC VOD 8 13 VID VDDA 9 12 OC *GND1 10 11 GND2* NOTES 1. NC = NO INTERNAL CONNECTION. 2. PIN 2AND PIN 10ARE INTERNALLY CONNECTEDTO EACH OTHER; IT IS RPRIEENCC1OO1MMAMMNEEDNN PDDINEE DD1 9TTHHAAARTTE BBINOOTTTEHHR PPNIIANNLSSL YBB EEC OCCOONNNNENNCEETCCETTDEEDDTOTTOO E AAA CCCHOO OMMTMMHOOENNR ;GG IRRTOO ISUUNNDD.. 09369-005 Figure 5. ADuM3471 Pin Configuration Table 13. ADuM3471 Pin Function Descriptions Pin No. Mnemonic Description 1 X1 Transformer Driver Output 1. 2, 10 GND Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 10 are internally connected to each other; 1 it is recommended that both pins be connected to a common ground. 3 NC No Internal Connection. 4 X2 Transformer Driver Output 2. 5 V Logic Input A. IA 6 V Logic Input B. IB 7 V Logic Input C. IC 8 V Logic Output D. OD 9 V Supply Voltage for the Primary Side, 3.0 V to 5.5 V. Connect a 0.1 μF bypass capacitor from V to GND. DDA DDA 1 11, 19 GND Ground Reference for the Secondary Side of the Isolator. Pin 11 and Pin 19 are internally connected to each other; 2 it is recommended that both pins be connected to a common ground. 12 OC Oscillator Control Pin. When the OC pin is connected high to the V pin, the secondary controller runs in open- DD2 loop (unregulated) mode. To regulate the output voltage, connect a resistor between the OC pin and GND; the 2 secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value. 13 V Logic Input D. ID 14 V Logic Output C. OC 15 V Logic Output B. OB 16 V Logic Output A. OA 17 FB Feedback Input from the Secondary Output Voltage, V . Use a resistor divider from the V output to the FB pin ISO ISO to set the V voltage equal to the 1.25 V internal reference level using the formula V = V × (R1 + R2)/R2. The FB ISO FB resistor divider is required even in open-loop mode to provide soft start. 18 V Internal Supply Voltage for the Secondary Side Controller and the Side 2 Data Channels. When a sufficient external DD2 voltage is supplied to V , the internal regulator regulates the V pin to 5.0 V. Otherwise, V should be in the REG DD2 DD2 3.0 V to 5.5 V range. Connect a 0.1 μF bypass capacitor from V to GND. DD2 2 20 V Input of the Internal Regulator to Power the Secondary Side Controller and the Side 2 Data Channels. V should REG REG be in the 5.5 V to 15 V range to regulate the V output to 5.0 V. DD2 Rev. B | Page 15 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet X1 1 20 VREG *GND1 2 19 GND2* NC 3 18 VDD2 X2 4 ADuM3472 17 FB VIA 5 TOP VIEW 16 VOA VIB 6 (Not to Scale) 15 VOB VOC 7 14 VIC VOD 8 13 VID VDDA 9 12 OC *GND1 10 11 GND2* NOTES 1. NC = NO INTERNAL CONNECTION. 2. PIN 2AND PIN 10ARE INTERNALLY CONNECTEDTO EACH OTHER; IT IS RPRIEENCC1OO1MMAMMNEEDNN PDDINEE DD1 9TTHHAAARTTE BBINOOTTTEHHR PPNIIANNLSSL YBB EEC OCCOONNNNENNCEETCCETTDEEDDTOTTOO E AAA CCCHOO OMMTMMHOOENNR ;GG IRRTOO ISUUNNDD.. 09369-006 Figure 6. ADuM3472 Pin Configuration Table 14. ADuM3472 Pin Function Descriptions Pin No. Mnemonic Description 1 X1 Transformer Driver Output 1. 2, 10 GND Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 10 are internally connected to each other; 1 it is recommended that both pins be connected to a common ground. 3 NC No Internal Connection. 4 X2 Transformer Driver Output 2. 5 V Logic Input A. IA 6 V Logic Input B. IB 7 V Logic Output C. OC 8 V Logic Output D. OD 9 V Supply Voltage for the Primary Side, 3.0 V to 5.5 V. Connect a 0.1 μF bypass capacitor from V to GND. DDA DDA 1 11, 19 GND Ground Reference for the Secondary Side of the Isolator. Pin 11 and Pin 19 are internally connected to each other; 2 it is recommended that both pins be connected to a common ground. 12 OC Oscillator Control Pin. When the OC pin is connected high to the V pin, the secondary controller runs in open- DD2 loop (unregulated) mode. To regulate the output voltage, connect a resistor between the OC pin and GND; the 2 secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value. 13 V Logic Input D. ID 14 V Logic Input C. IC 15 V Logic Output B. OB 16 V Logic Output A. OA 17 FB Feedback Input from the Secondary Output Voltage, V . Use a resistor divider from the V output to the FB pin ISO ISO to set the V voltage equal to the 1.25 V internal reference level using the formula V = V × (R1 + R2)/R2. The FB ISO FB resistor divider is required even in open-loop mode to provide soft start. 18 V Internal Supply Voltage for the Secondary Side Controller and the Side 2 Data Channels. When a sufficient external DD2 voltage is supplied to V , the internal regulator regulates the V pin to 5.0 V. Otherwise, V should be in the REG DD2 DD2 3.0 V to 5.5 V range. Connect a 0.1 μF bypass capacitor from V to GND. DD2 2 20 V Input of the Internal Regulator to Power the Secondary Side Controller and the Side 2 Data Channels. V should REG REG be in the 5.5 V to 15 V range to regulate the V output to 5.0 V. DD2 Rev. B | Page 16 of 36

Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 X1 1 20 VREG *GND1 2 19 GND2* NC 3 18 VDD2 X2 4 ADuM3473 17 FB VIA 5 TOP VIEW 16 VOA VOB 6 (Not to Scale) 15 VIB VOC 7 14 VIC VOD 8 13 VID VDDA 9 12 OC *GND1 10 11 GND2* NOTES 1. NC = NO INTERNAL CONNECTION. 2. PIN 2AND PIN 10ARE INTERNALLY CONNECTEDTO EACH OTHER; IT IS RPRIEENCC1OO1MMAMMNEEDNN PDDINEE DD1 9TTHHAAARTTE BBINOOTTTEHHR PPNIIANNLSSL YBB EEC OCCOONNNNENNCEETCCETTDEEDDTOTTOO E AAA CCCHOO OMMTMMHOOENNR ;GG IRRTOO ISUUNNDD.. 09369-007 Figure 7. ADuM3473 Pin Configuration Table 15. ADuM3473 Pin Function Descriptions Pin No. Mnemonic Description 1 X1 Transformer Driver Output 1. 2, 10 GND Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 10 are internally connected to each other; 1 it is recommended that both pins be connected to a common ground. 3 NC No Internal Connection. 4 X2 Transformer Driver Output 2. 5 V Logic Input A. IA 6 V Logic Output B. OB 7 V Logic Output C. OC 8 V Logic Output D. OD 9 V Supply Voltage for the Primary Side, 3.0 V to 5.5 V. Connect a 0.1 μF bypass capacitor from V to GND. DDA DDA 1 11, 19 GND Ground Reference for the Secondary Side of the Isolator. Pin 11 and Pin 19 are internally connected to each other; 2 it is recommended that both pins be connected to a common ground. 12 OC Oscillator Control Pin. When the OC pin is connected high to the V pin, the secondary controller runs in open- DD2 loop (unregulated) mode. To regulate the output voltage, connect a resistor between the OC pin and GND; the 2 secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value. 13 V Logic Input D. ID 14 V Logic Input C. IC 15 V Logic Input B. IB 16 V Logic Output A. OA 17 FB Feedback Input from the Secondary Output Voltage, V . Use a resistor divider from the V output to the FB pin ISO ISO to set the V voltage equal to the 1.25 V internal reference level using the formula V = V × (R1 + R2)/R2. The FB ISO FB resistor divider is required even in open-loop mode to provide soft start. 18 V Internal Supply Voltage for the Secondary Side Controller and the Side 2 Data Channels. When a sufficient external DD2 voltage is supplied to V , the internal regulator regulates the V pin to 5.0 V. Otherwise, V should be in the REG DD2 DD2 3.0 V to 5.5 V range. Connect a 0.1 μF bypass capacitor from V to GND. DD2 2 20 V Input of the Internal Regulator to Power the Secondary Side Controller and the Side 2 Data Channels. V should REG REG be in the 5.5 V to 15 V range to regulate the V output to 5.0 V. DD2 Rev. B | Page 17 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet X1 1 20 VREG *GND1 2 19 GND2* NC 3 18 VDD2 X2 4 ADuM3474 17 FB VOA 5 TOP VIEW 16 VIA VOB 6 (Not to Scale) 15 VIB VOC 7 14 VIC VOD 8 13 VID VDDA 9 12 OC *GND1 10 11 GND2* NOTES 1. NC = NO INTERNAL CONNECTION. 2. PIN 2AND PIN 10ARE INTERNALLY CONNECTEDTO EACH OTHER; IT IS RPRIEENCC1OO1MMAMMNEEDNN PDDINEE DD1 9TTHHAAARTTE BBINOOTTTEHHR PPNIIANNLSSL YBB EEC OCCOONNNNENNCEETCCETTDEEDDTOTTOO E AAA CCCHOO OMMTMMHOOENNR ;GG IRRTOO ISUUNNDD.. 09369-008 Figure 8. ADuM3474 Pin Configuration Table 16. ADuM3474 Pin Function Descriptions Pin No. Mnemonic Description 1 X1 Transformer Driver Output 1. 2, 10 GND Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 10 are internally connected to each other; 1 it is recommended that both pins be connected to a common ground. 3 NC No Internal Connection. 4 X2 Transformer Driver Output 2. 5 V Logic Output A. OA 6 V Logic Output B. OB 7 V Logic Output C. OC 8 V Logic Output D. OD 9 V Supply Voltage for the Primary Side, 3.0 V to 5.5 V. Connect a 0.1 μF bypass capacitor from V to GND. DDA DDA 1 11, 19 GND Ground Reference for the Secondary Side of the Isolator. Pin 11 and Pin 19 are internally connected to each other; 2 it is recommended that both pins be connected to a common ground. 12 OC Oscillator Control Pin. When the OC pin is connected high to the V pin, the secondary controller runs in open- DD2 loop (unregulated) mode. To regulate the output voltage, connect a resistor between the OC pin and GND; the 2 secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value. 13 V Logic Input D. ID 14 V Logic Input C. IC 15 V Logic Input B. IB 16 V Logic Input A. IA 17 FB Feedback Input from the Secondary Output Voltage, V . Use a resistor divider from the V output to the FB pin ISO ISO to set the V voltage equal to the 1.25 V internal reference level using the formula V = V × (R1 + R2)/R2. The FB ISO FB resistor divider is required even in open-loop mode to provide soft start. 18 V Internal Supply Voltage for the Secondary Side Controller and the Side 2 Data Channels. When a sufficient external DD2 voltage is supplied to V , the internal regulator regulates the V pin to 5.0 V. Otherwise, V should be in the REG DD2 DD2 3.0 V to 5.5 V range. Connect a 0.1 μF bypass capacitor from V to GND. DD2 2 20 V Input of the Internal Regulator to Power the Secondary Side Controller and the Side 2 Data Channels. V should REG REG be in the 5.5 V to 15 V range to regulate the V output to 5.0 V. DD2 Table 17. Truth Table (Positive Logic) V Input1 V State V State V Output1 Notes Ix DD1 DD2 Ox High Powered Powered High Normal operation, data is high Low Powered Powered Low Normal operation, data is low 1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). Rev. B | Page 18 of 36

Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 TYPICAL PERFORMANCE CHARACTERISTICS 1500 80 1400 1300 70 1200 1100 60 1000 f (kHz)SW 987600000000 FICIENCY (%) 5400 F 30 500 E 400 20 300 200 10 –40°C +25°C 100 +105°C 00 50 100 150 200RO2C5 (0kΩ)300 350 400 450 500 09369-009 00 50 100 150LOA20D0 CU2R5R0ENT3 0(0mA)350 400 450 500 09369-012 Figure 9. Switching Frequency (fSW) vs. ROC Resistance Figure 12. Typical Efficiency over Temperature with Coilcraft Transformer, fSW = 500 kHz, 5 V Input to 5 V Output 80 80 70 70 60 60 %) 50 %) 50 Y ( Y ( C C EN 40 EN 40 CI CI EFFI 30 EFFI 30 20 1MHz 20 700kHz 10 500kHz 10 VDD1 = 5V, VISO = 5V 200kHz VDD1 = 5V, VISO = 3.3V 00 50 100 150LOA20D0 CU2R5R0ENT3 0(0mA)350 400 450 500 09369-010 00 50 100 150LOA20D0 CU2R5R0ENT3 0(0VmDAD)13 5=0 3.3V40, 0VISO4 5=0 3.3V500 09369-013 Figure 10. Typical Efficiency at Various Switching Frequencies with Figure 13. Single-Supply Efficiency with Coilcraft Transformer, fSW = 500 kHz Coilcraft Transformer, 5 V Input to 5 V Output 80 80 70 70 60 60 %) 50 %) 50 Y ( Y ( C C EN 40 EN 40 CI CI FI FI F 30 F 30 E E 20 1MHz 20 1MHz 700kHz 700kHz 10 500kHz 10 500kHz 200kHz 200kHz 00 50 100 150LOA20D0 CU2R5R0ENT3 0(0mA)350 400 450 500 09369-011 00 10 20 30 40 L5O0AD60CUR70REN8T0(m9A0)100 110 120 130 140 09369-014 Figure 11. Typical Efficiency at Various Switching Frequencies with Figure 14. Typical Efficiency at Various Switching Frequencies with Halo Transformer, 5 V Input to 5 V Output Coilcraft Transformer, 5 V Input to 15 V Output Rev. B | Page 19 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet 80 15 70 60 %) 50 10 FICIENCY ( 40 I (mA)CH F 30 E 5 20 1MHz 700kHz VDD1 = 5V, VISO = 5V 10 500kHz VDD1 = 5V, VISO = 3.3V 200kHz VDD1 = 3.3V, VISO = 3.3V 00 10 20 30 40 L5O0AD60CUR70REN8T0(m9A0)100 110 120 130 140 09369-026 00 5 DA1T0ARATE(M1b5ps) 20 25 09369-029 Figure 15. Typical Efficiency at Various Switching Frequencies with Figure 18. Typical Single-Supply ICH Supply Current per Forward Data Channel Halo Transformer, 5 V Input to 15 V Output (15 pF Output Load) 80 15 70 60 %) 50 10 CIENCY ( 40 (mA)CH FI I F 30 E 5 20 VDD1 = 5V, VISO = 5V 10 –40°C VDD1 = 5V, VISO = 3.3V ++2150°5C°C VDD1 = 3.3V, VISO = 3.3V 00 10 20 30 40 L5O0AD6 0CUR7R0EN8T0 (m9A0)100 110 120 130 140 09369-027 00 5 DA1T0ARATE(M1b5ps) 20 25 09369-030 Figure 16. Typical Efficiency over Temperature with Coilcraft Transformer, Figure 19. Typical Single-Supply ICH Supply Current per Reverse Data Channel fSW = 500 kHz, 5 V Input to 15 V Output (15 pF Output Load) 80 5 70 VDD1 = 5V, VISO = 5V 4 VDD1 = 5V, VISO = 3.3V 60 VDD1 = 3.3V, VISO = 3.3V %) 50 CY ( mA) 3 EN 40 (D) EFFICI 30 IISO ( 2 20 1 10 VDD1 = 5V, VISO = 15V VDD1 = 5V, VISO = 12V 00 10 20 30 40 50LO6A0DC70URR80ENT90(m1A0)0 110 120 130140 09369-028 00 5 DA1T0A RATE (Mb1p5s) 20 25 09369-031 Figure 17. Double-Supply Efficiency with Coilcraft Transformer, fSW = 500 kHz Figure 20. Typical Single-Supply IISO (D) Dynamic Supply Current per Output Channel (15 pF Output Load) Rev. B | Page 20 of 36

Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 5 5 VVDDDD11 == 55VV,, VVIISSOO == 53V.3V VVDDDD11 == 55VV,, VVIISSOO == 1152VV 4 VDD1 = 3.3V, VISO = 3.3V 4 A) 3 A) 3 m m (D) (D) O ( O ( IIS 2 IIS 2 1 1 00 5 DA1T0A RATE (Mb1p5s) 20 25 09369-032 00 5 DA1T0A RATE (M1b5ps) 20 25 09369-035 Figure 21. Typical Single-Supply IISO (D) Dynamic Supply Current Figure 24. Typical Double-Supply IISO (D) Dynamic Supply Current per Input Channel per Output Channel (15 pF Output Load) 30 5 VDD1 = 5V, VISO = 15V VDD1 = 5V, VISO = 15V VDD1 = 5V, VISO = 12V VDD1 = 5V, VISO = 12V 25 4 20 A) 3 A) m (mCH 15 (O (D) I IIS 2 10 1 5 00 5 DA1T0A RATE (Mb1p5s) 20 25 09369-033 00 5 DA1T0A RATE (M1b5ps) 20 25 09369-036 Figure 22. Typical Double-Supply ICH Supply Current per Forward Data Figure 25. Typical Double-Supply IISO (D) Dynamic Supply Current Channel (15 pF Output Load) per Input Channel 30 6 VDD1 = 5V, VISO = 15V 25 VDD1 = 5V, VISO = 12V 5 20 4 A) V) (mCH 15 V (ISO 3 I 10 2 5 1 VISO AT 10mA VISO AT 50mA VISO AT 400mA 00 5 DA1T0A RATE (M1b5ps) 20 25 09369-034 00 5 10 TIME15 (ms) 20 25 30 09369-037 Figure 23. Typical Double-Supply ICH Supply Current per Reverse Data Figure 26. Typical VISO Startup with 10 mA, 50 mA, and 400 mA Output Load, Channel (15 pF Output Load) 5 V Input to 5 V Output Rev. B | Page 21 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet 5 6.0 COUT = 47µF, L1 = 47µH 5.5 5.0 4 4.5 V) (O S 3 VI 6.0 V) (O 5.5 COUT = 47µF, L1 = 100µH S VI 2 5.0 4.5 1 VISO AT 10mA A) 1.0 VVIISSOO AATT 5400m0mAA (OAD 0.5 90% LOAD 10% LOAD 00 5 10 TIME15 (ms) 20 25 30 09369-038 IL 0–2 0 2 4 TIME6 (ms) 8 10 12 14 09369-041 Figure 27. Typical VISO Startup with 10 mA, 50 mA, and 400 mA Output Load, Figure 30. Typical VISO Load Transient Response at 10% to 90% of 400 mA Load, 5 V Input to 3.3 V Output fSW = 500 kHz, 5 V Input to 5 V Output 5 4.0 COUT = 47µF, L1 = 47µH 3.5 4 3.0 V) (O S 3 VI 4.0 (V)O 3.5 COUT = 47µF, L1 = 100µH S VI 2 3.0 1 1.0 VVIISSOO AATT 1500mmAA (A)AD 0.5 90% LOAD 10% LOAD VISO AT 250mA LO 00 5 10 TIME15 (ms) 20 25 30 09369-039 I 0–2 0 2 4 TIME6 (ms) 8 10 12 14 09369-042 Figure 28. Typical VISO Startup with 10 mA, 50 mA, and 250 mA Output Load, Figure 31. Typical VISO Load Transient Response at 10% to 90% of 400 mA Load, 3.3 V Input to 3.3 V Output fSW = 500 kHz, 5 V Input to 3.3 V Output 18 4.0 COUT = 47µF, L1 = 47µH 16 3.5 3.0 14 V) 12 (O S VI 4.0 (V)O 10 3.5 COUT = 47µF, L1 = 100µH S VI 8 3.0 6 4 1.0 2 VVIISSOO AATT 1200mmAA (A)AD 0.5 90% LOAD 10% LOAD VISO AT 100mA LO 00 5 10 TIME15 (ms) 20 25 30 09369-040 I 0–2 0 2 4 TIME6 (ms) 8 10 12 14 09369-044 Figure 29. Typical VISO Startup with 10 mA, 20 mA, and 100 mA Output Load, Figure 32. Typical VISO Load Transient Response at 10% to 90% of 250 mA Load, 5 V Input to 15 V Output fSW = 500 kHz, 3.3 V Input to 3.3 V Output Rev. B | Page 22 of 36

Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 18 3.34 COUT = 47µF, L1 = 47µH, L2 = 47µH 16 14 3.32 V) (V)SO 12 V (ISO VI 18 3.30 COUT = 47µF, L1 = 100µH, L2 = 100µH 16 14 3.28 12 20 (A)D 210000 10% LOAD 90% LOAD X1 (V) 10 X1 ON X2 ON A O IL 0–2 2 6 10 14TIME 1(m8s) 22 26 30 34 09369-043 0–2 –1 TIME0 (µs) 1 2 09369-047 Figure 33. Typical VISO Load Transient Response at 10% to 90% of 100 mA Load, Figure 36. Typical VISO Output Voltage Ripple at 250 mA Load, fSW = 500 kHz, 5 V Input to 15 V Output fSW = 500 kHz, 3.3 V Input to 3.3 V Output 5.04 15.4 15.2 5.02 V) V (ISO 5.00 (V)SO 15.0 VI 14.8 4.98 14.6 20 20 X2 ON X2 ON V) V) X1 ( 10 X1 ON X1 ( 10 X1 ON 0–2 –1 TIME0 (µs) 1 2 09369-045 0–2 –1 TIME0 (µs) 1 2 09369-048 Figure 34. Typical VISO Output Voltage Ripple at 400 mA Load, Figure 37. Typical VISO Output Voltage Ripple at 100 mA Load, fSW = 500 kHz, 5 V Input to 5 V Output fSW = 500 kHz, 5 V Input to 15 V Output 3.34 3.32 V) (O S VI 3.30 3.28 20 X2 ON V) 1 ( 10 X1 ON X 0–2 –1 TIME0 (µs) 1 2 09369-046 Figure 35. Typical VISO Output Voltage Ripple at 400 mA Load, fSW = 500 kHz, 5 V Input to 3.3 V Output Rev. B | Page 23 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet TERMINOLOGY I t Propagation Delay DD1 (Q) PLH I is the minimum operating current drawn at the V power The t propagation delay is measured from the 50% level of DD1 (Q) DD1 PLH input when there is no external load at V and the I/O pins are the rising edge of the V signal to the 50% level of the rising ISO Ix operating below 2 Mbps, requiring no additional dynamic supply edge of the VOx signal. current. Propagation Delay Skew (t ) PSK I t is the magnitude of the worst-case difference in t and/or DD1 (D) PSK PHL I is the typical input supply current with all channels t that is measured between units at the same operating temper- DD1 (D) PLH simultaneously driven at a maximum data rate of 25 Mbps with ature, supply voltages, and output load within the recommended the full capacitive load representing the maximum dynamic operating conditions. load conditions. Treat resistive loads on the outputs separately Channel-to-Channel Matching from the dynamic load. Channel-to-channel matching is the absolute value of the differ- I ence in propagation delays between two channels when operated DD1 (MAX) I is the input current under full dynamic and V load with identical loads. DD1 (MAX) ISO conditions. Minimum Pulse Width t Propagation Delay The minimum pulse width is the shortest pulse width at which PHL The t propagation delay is measured from the 50% level of the specified pulse width distortion is guaranteed. PHL the falling edge of the V signal to the 50% level of the falling Ix Maximum Data Rate edge of the V signal. Ox The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. Rev. B | Page 24 of 36

Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 APPLICATIONS INFORMATION T1 D1 L1 VISO = +3.3V 47µH COUT TO +15V The dc-to-dc converter section of the ADuM347x uses a 47µF VDD1 R1 secondary side controller architecture with isolated pulse-width CIN D2 modulation (PWM) feedback. V power is supplied to an oscillat- DD1 ing circuit that switches current to the primary side of an external power transformer using internal push-pull switches at the X1 1 X1 20 VREG 0.1µF 2 GND1 19 GND2 and X2 pins. Power transferred to the secondary side of the trans- 3 NC ADuM3470/ 18 VDD2 +5V former is full wave rectified with external Schottky diodes (D1 4 X2 ADuM3471/ 17 FB VFB and D2), filtered with the L1 inductor and COUT capacitor, and 56 VVIIAB//VVOOAB AADDuuMM33447723// 1165 VVIIAB//VVOOAB R2 regulated to the isolated power supply voltage from 3.3 V to 15 V. 7 VIC/VOC ADuM3474 14 VIC/VOC The secondary (V ) side controller regulates the output using 8 VID/VOD 13 VID/VOD a feedback voltageI,S OVFB, from a resistor divider on the output to VD0D.11µF 91 0V GDDNAD1 1112 GONCD2 ROC 100kΩ cbrye aa tde ead PicWateMd ciConoutrpolle sri gdnataal tchhaatn ins esle lnatb teole tdh eV pFBr.i mThaery p (rVimDDa1r)y s sididee FOR VISO = 3.3V VOISRO 5 =V ,V CFBO N× N(RE1C T+ RV2R)E/RG,2 VDD2,AND VISO. 09369-015 PWM converter varies the duty cycle of the X1 and X2 switches Figure 38. Single Power Supply to modulate the oscillator circuit and control the power being D1 L1 T1 VISO = sent to the secondary side. This feedback allows for significantly +12VTO 47µH 47µF +24V higher power and efficiency. COUT1 UNREGULATED VDD1 +6VTO The ADuM347x devices implement undervoltage lockout +12V CIN D2 L2 COUT2 (UVLO) with hysteresis on the V power input. This feature DDA 47µF ensures that the converter does not go into oscillation due to D3 47µH R1 noisy input power or slow power-on ramp rates. D4 A minimum load current of 10 mA is recommended to ensure optimum load regulation. Smaller loads can generate excess noise 1 X1 20 VREG on the output due to short or erratic PWM pulses. Excess noise 2 GND1 19 GND2 generated in this way can cause regulation problems in some 3 NC ADuM3470/ 18 VDD2 0.1µ+F5V circumstances. 4 X2 ADuM3471/ 17 FB VFB 5 VIA/VOA ADuM3472/ 16 VIA/VOA APPLICATION SCHEMATICS 6 VIB/VOB ADuM3473/ 15 VIB/VOB R2 7 VIC/VOC ADuM3474 14 VIC/VOC The ADuM347x devices have three main application schematics, 8 VID/VOD 13 VID/VOD as shown in Figure 38 to Figure 40. Figure 38 has a center-tapped VDD1 9 VDDA 12 OC ROC100kΩ secondary and two Schottky diodes that provide full wave 0.1µF 10 GND1 11 GND2 r3e.3c tVif,i c5a Vti,o 1n2 f Vor, aan sdin 1g5le V o. uFtopru sti,n tgylpei csaulplyp lfioers pwohweenr VsuISpOp =li e3s.3 o Vf FOR VISO = 15V VOISRO L =E VSFSB, V×R (ERG1 C+A RN2 )C/RO2NNECTTO VISO. 09369-016 or 5 V, V , V , and V can be connected together. Figure 39. Doubling Power Supply REG DD2 ISO D1 L1 Figure 39 shows a voltage doubling circuit that can be used for a T1 VISO = COARSELY single supply with an output that exceeds 15 V; 15 V is the largest 47µH C47OµUFT1 R+5EVGTUOL A+T1E5DV supply that can be connected to the regulator input, VREG (Pin 20). VDD1 In the circuit shown in Figure 39, the output voltage can be as high CIN D2 L2 COUT2 47µF UNREGULATED as 24 V, and the voltage at the V pin can be as high as 12 V. –5VTO –15V REG 47µH When using the circuit shown in Figure 39 to obtain an output D3 R1 voltage lower than 10 V (for example, V = 3.3 V, V = 5 V), DD1 ISO D4 connect V to V directly. REG ISO Figure 40, which also uses a voltage doubling secondary circuit, 1 X1 20 VREG is an example of a coarsely regulated, positive power supply and 2 GND1 19 GND2 an unregulated, negative power supply for outputs of approxi- 3 NC ADuM3470/ 18 VDD2 0.1µ+F5V 4 X2 ADuM3471/ 17 FB mFoart eallyl t±h5e Vci, rc±u1i2ts V s,h aonwdn ± i1n5 F Vig. ure 38 to Figure 40, the isolated 56 VVIIAB//VVOOAB AAADDDuuuMMM333444777234// 1165 VVIIAB//VVOOAB RVF2B 7 VIC/VOC 14 VIC/VOC output voltage (VISO) can be set with the voltage dividers, R1 8 VID/VOD 13 VID/VOD and R2 (values 1 kΩ to 100 kΩ) using the following equation: VDD1 9 VDDA 12 OC ROC100kΩ VISO = VFB × (R1 + R2)/R2 0.1µF 10 GNDV1ISO = VFB × (R1 + R2)/R121 GND2 09369-017 where V is the internal feedback voltage (approximately 1.25 V). FB Figure 40. Positive Supply and Unregulated Negative Supply Rev. B | Page 25 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet TRANSFORMER DESIGN V ISO +V Custom transformers were designed for use in the circuits shown NS = 2 D (2) in Figure 38, Figure 39, and Figure 40 (see Table 18). The trans- N V ×D×2 P DD1(MIN) formers designed for use with the ADuM347x differ from other where: transformers used with isolated dc-to-dc converters that do not N/N is the primary to secondary turns ratio. regulate the output voltage. The output voltage is regulated by a S P V is the isolated output supply voltage. V /2 is used because PWM controller in the ADuM347x that varies the duty cycle of ISO ISO the circuit uses two pairs of diodes, creating a doubler circuit. the primary side switches in response to a secondary side feed- V is the Schottky diode voltage drop (0.5 V maximum). back voltage, V , received through an isolated digital channel. D FB V is the minimum input supply voltage. The internal controller has a maximum duty cycle of 40%. DD1 (MIN) D is the duty cycle = 0.30 for a 30% typical duty cycle (40% is TRANSFORMER TURNS RATIO the maximum duty cycle). To determine the transformer turns ratio—taking into account 2 is a multiplier factor used for the push-pull switching cycle. the losses for the primary switches and the losses for the secondary For the circuit shown in Figure 39 using the 5 V to 15 V reference diodes and inductors—the external transformer turns ratio for design in Table 18 and with V = 4.5 V, the turns ratio is DD1 (MIN) the ADuM347x can be calculated using Equation 1. N/N = 3. S P N V +V S = ISO D (1) The circuit shown in Figure 40 also uses double windings and N V ×D×2 diode pairs to create a doubler circuit. However, because a P DD1(MIN) positive and negative output voltage are created, V is used, ISO where: and the external transformer turns ratio can be calculated using N/N is the primary to secondary turns ratio. S P Equation 3. V is the isolated output supply voltage. ISO N V +V VD is the Schottky diode voltage drop (0.5 V maximum). S = ISO D (3) VDD1 (MIN) is the minimum input supply voltage. NP VDD1(MIN)×D×2 D is the duty cycle = 0.30 for a 30% typical duty cycle (40% is where: the maximum duty cycle). N/N is the primary to secondary turns ratio. 2 is a multiplier factor used for the push-pull switching cycle. S P V is the isolated output supply voltage. ISO For the circuit shown in Figure 38 using the 5 V to 5 V reference V is the Schottky diode voltage drop (0.5 V maximum). D design in Table 18 and with V = 4.5 V, the turns ratio is DD1 (MIN) V is the minimum input supply voltage. DD1 (MIN) N/N = 2. S P D is the duty cycle = 0.35 for a 35% typical duty cycle (40% is For a 3.3 V input to 3.3 V output isolated single power supply the maximum duty cycle). and with VDD1 (MIN) = 3.0 V, the turns ratio is also NS/NP = 2. 2 is a multiplier factor used for the push-pull switching cycle. Therefore, the same transformer turns ratio, N/N = 2, can be S P For the circuit shown in Figure 40, the duty cycle, D, is set to 0.35 used for the three single power applications: 5 V to 5 V, 5 V to for a 35% typical duty cycle to reduce the maximum voltages seen 3.3 V, and 3.3 V to 3.3 V. by the diodes for a ±15 V supply. The circuit shown in Figure 39 uses double windings and diode For the circuit shown in Figure 40 using the +5 V to ±15 V refer- pairs to create a doubler circuit; therefore, half the output voltage, ence design in Table 18 and with V = 4.5 V, the turns DD1 (MIN) V /2, is used, as shown in Equation 2. ISO ratio is N/N = 5. S P Table 18. Transformer Reference Designs Turns Ratio, ET Constant Total Primary Total Primary Isolation Isolation Part No. Manufacturer PRI:SEC (V × µs Min) Inductance (µH) Resistance (Ω) Voltage (rms) Type Reference JA4631-BL Coilcraft 1CT:2CT 18 255 0.2 2500 Basic Figure 38 JA4650-BL Coilcraft 1CT:3CT 18 255 0.2 2500 Basic Figure 39 KA4976-AL Coilcraft 1CT:5CT 18 255 0.2 2500 Basic Figure 40 TGSAD-260V6LF Halo Electronics 1CT:2CT 14 389 0.8 2500 Supplemental Figure 38 TGSAD-290V6LF Halo Electronics 1CT:3CT 14 389 0.8 2500 Supplemental Figure 39 TGSAD-292V6LF Halo Electronics 1CT:5CT 14 389 0.8 2500 Supplemental Figure 40 TGAD-260NARL Halo Electronics 1CT:2CT 14 389 0.8 1500 Functional Figure 38 TGAD-290NARL Halo Electronics 1CT:3CT 14 389 0.8 1500 Functional Figure 39 TGAD-292NARL Halo Electronics 1CT:5CT 14 389 0.8 1500 Functional Figure 40 Rev. B | Page 26 of 36

Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 TRANSFORMER ET CONSTANT The ADuM347x devices also have an open-loop mode where the output voltage is not regulated and is dependent on the The next transformer design factor to consider is the ET constant. transformer turns ratio, N/N , and the conditions of the output This constant determines the minimum V × µs constant of the S P including output load current and the losses in the dc-to-dc transformer over the operating temperature. ET values of 14 V × µs converter circuit. This open-loop mode is selected when the OC and 18 V × µs were selected for the ADuM347x transformer pin is connected high to the V pin. In open-loop mode, the designs listed in Table 18 using the following equation: DD2 switching frequency is 318 kHz. V ET(MIN)= DD1(MAX) TRANSIENT RESPONSE f ×2 SW(MIN) The load transient response of the ADuM347x output voltage for where: 10% to 90% of the full load is shown in Figure 30 to Figure 33 VDD1 (MAX) is the maximum input supply voltage. for the application schematics in Figure 38 and Figure 39. The f is the minimum primary switching frequency = 300 kHz response shown is slow but stable and can have more output SW (MIN) in startup. change than desired for some applications. The output voltage 2 is a multiplier factor used for the push-pull switching cycle. change with load transient is reduced, and the output is shown TRANSFORMER PRIMARY INDUCTANCE AND to remain stable by adding more inductance to the output circuits, as shown in the second V output waveform in Figure 30 to RESISTANCE ISO Figure 33. For additional improvement in transient response, Another important characteristic of the transformer for designs add a 0.1 µF ceramic capacitor (C ) in parallel with the high FB with the ADuM347x is the primary inductance. Transformers feedback resistor. This value helps to reduce the overshoot and for the ADuM347x are recommended to have between 60 µH to undershoot during load transients. 100 µH of inductance per primary winding. Values of primary COMPONENT SELECTION inductance in this range are needed for smooth operation of the ADuM347x pulse-by-pulse current-limit circuit, which can help The ADuM347x digital isolators with 2 W dc-to-dc converters protect against a build-up of saturation currents in the transformer. require no external interface circuitry for the logic interfaces. If the inductance is specified for the total of both primary wind- Power supply bypassing is required at the input and output supply ings, for example, as 400 µH, the inductance of one winding is pins. Note that a low ESR ceramic bypass capacitor of 0.1 µF is one-fourth of two equal windings, or 100 µH. required on Side 1 between Pin 9 and Pin 10, and on Side 2 between Pin 18 and Pin 19, as close to the chip pads as possible. Another important characteristic of the transformer for designs with the ADuM347x is primary resistance. Primary resistance as The power supply section of the ADuM347x uses a high oscillator low as is practical (less than 1 Ω) helps to reduce losses and frequency to efficiently pass power through the external power improves efficiency. The dc primary resistance can be measured transformer. In addition, normal operation of the data section of and specified, and is shown for the transformers in Table 18. the iCoupler introduces switching transients on the power supply pins. Bypass capacitors are required for several operating frequen- TRANSFORMER ISOLATION VOLTAGE cies. Noise suppression requires a low inductance, high frequency Isolation voltage and isolation type should be determined for capacitor; ripple suppression and proper regulation require a large the requirements of the application and then specified. The value capacitor. To suppress noise and reduce ripple, large value transformers in Table 18 have been specified for 2500 V rms ceramic capacitors of X5R or X7R dielectric type are recom- for supplemental or basic isolation and for 1500 V rms functional mended. The recommended capacitor value is 10 µF for V and DD1 isolation. Other isolation levels and isolation voltages can be 47 µF for V . These capacitors have a low ESR and are available ISO specified and requested from the transformer manufacturers in moderate 1206 or 1210 sizes for voltages up to 10 V. For output listed in Table 18 or from other manufacturers. voltages larger than 10 V, two 22 µF ceramic capacitors can be SWITCHING FREQUENCY used in parallel. See Table 19 for recommended components. The ADuM347x switching frequency can be adjusted from Table 19. Recommended Components 200 kHz to 1 MHz by changing the value of the ROC resistor Part No. Manufacturer Value shown in Figure 38, Figure 39, and Figure 40. The value of the GRM32ER71A476KE15L Murata 47 µF, 10 V, X7R, 1210 ROC resistor needed for the desired switching frequency can be GRM32ER71C226KEA8L Murata 22 µF, 16 V, X7R, 1210 determined from the switching frequency vs. R resistance curve GRM31CR71A106KA01L Murata 10 µF, 10 V, X7R, 1206 OC shown in Figure 9. The output filter inductor value and output MBR0540T1G ON Semiconductor Schottky, 0.5 A, 40 V, SOD-123 capacitor value for the ADuM347x application schematics have LQH3NPN470MM0 Murata 47 µH, 0.41 A, 1212 been designed to be stable over the switching frequency range of ME3220-104KL Coilcraft 100 µH, 0.34 A, 1210 500 kHz to 1 MHz, when loaded from 10% to 90% of the maxi- LQH6PPN470M43 Murata 47 µH, 1.10 A, 2424 mum load. LQH6PPN101M43 Murata 100 µH, 0.80 A, 2424 Rev. B | Page 27 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet Inductors must be selected based on the value and supply The board layout in Figure 41 shows enlarged pads for Pin 2 current needed. Most applications with switching frequencies and Pin 10 (GND) on Side 1 and Pin 11 and Pin 19 (GND) 1 2 between 500 kHz and 1 MHz and load transients between 10% on Side 2. Large diameter vias should be implemented from the and 90% of full load are stable with the 47 μH inductor value pad to the ground planes and power planes to increase thermal listed in Table 19. Values as large as 200 μH can be used for power conductivity and to reduce inductance. Multiple vias in the supply applications with a switching frequency as low as 200 kHz thermal pads can significantly reduce temperatures inside the to help stabilize the output voltage or for improved load transient chip. The dimensions of the expanded pads are left to the discre- response (see Figure 30 to Figure 33). Inductors in a small 1212 tion of the designer and depend on the available board space. or 1210 size are listed in Table 19 with a 47 μH value and a 0.41 A THERMAL ANALYSIS current rating to handle the majority of applications below a The ADuM347x parts consist of two internal die attached to a 400 mA load, and with a 100 μH value and a 0.34 A current split lead frame with two die attach paddles. For the purposes rating to handle a load up to 300 mA. of thermal analysis, the die are treated as a thermal unit, with Recommended Schottky diodes have low forward voltage to the highest junction temperature reflected in the θ value from JA reduce losses and high reverse voltage of up to 40 V to withstand Table 5. The value of θ is based on measurements taken with JA the peak voltages available in the doubling circuits shown in the parts mounted on a JEDEC standard, 4-layer board with Figure 39 and Figure 40. fine width traces and still air. PRINTED CIRCUIT BOARD (PCB) LAYOUT Under normal operating conditions, the ADuM347x devices Figure 41 shows the recommended PCB layout for the operate at full load across the full temperature range without ADuM347x. Note that the total lead length between the ends derating the output current. However, following the recom- of the low ESR capacitor and the V and GND pins must not mendations in the Printed Circuit Board (PCB) Layout section DDx x exceed 2 mm. Installing a bypass capacitor with traces more decreases thermal resistance to the PCB, allowing increased than 2 mm in length can result in data corruption. thermal margins at high ambient temperatures. The ADuM347x devices have a thermal shutdown circuit X1 VREG that shuts down the dc-to-dc converter and the outputs of the GND1 GND2 NC VDD2 ADuM347x when a die temperature of approximately 160°C X2 FB is reached. When the die cools below approximately 140°C, the VIA/VOA VIA/VOA ADuM347x dc-to-dc converter and outputs turn on again. VIB/VOB VIB/VOB VIC/VOC VIC/VOC PROPAGATION DELAY-RELATED PARAMETERS VID/VOD VID/VOD Propagation delay is a parameter that describes the length of VDDA OC GND1 GND2 09369-025 tniemnet (its etea kFeigs uforer 4a2 l)o.g Tich esi pgnroapl atoga ptiroonp adgealatey ttho rao luogghic a l ocwom oputop-ut Figure 41. Recommended PCB Layout can differ from the propagation delay to a logic high output. In applications that involve high common-mode transients, ensure that board coupling across the isolation barrier is minimized. INPUT (VIx) 50% Furthermore, design the board layout such that any coupling that tPLH tPHL dFaoielus roec tcou ern asfufercet tsh aisll cpainn sc aeuqsuea vlloyl toang ea dgiifvfeerne ncotimalsp boentewnete snid pei.n s OUTPUT (VOx) 50% 09369-018 Figure 42. Propagation Delay Parameters that exceed the absolute maximum ratings specified in Table 10, thereby leading to latch-up and/or permanent damage. Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how The ADuM3470/ADuM3471/ADuM3472/ADuM3473/ accurately the timing of the input signal is preserved. ADuM3474 are power devices that dissipate approximately 1 W of power when fully loaded and running at maximum speed. Channel-to-channel matching refers to the maximum amount Because it is not possible to apply a heat sink to an isolation device, that the propagation delay differs between channels within a the devices primarily depend on heat dissipation into the PCB single ADuM347x component. through the GND pins. If the devices are used at high ambient x Propagation delay skew refers to the maximum amount that the temperatures, provide a thermal path from the GND pins to the x propagation delay differs between multiple ADuM347x compo- PCB ground plane. nents operating under the same conditions. Rev. B | Page 28 of 36

Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 DC CORRECTNESS AND MAGNETIC FIELD For example, at a magnetic field frequency of 1 MHz, the IMMUNITY maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This voltage is approxi- Positive and negative logic transitions at the isolator input cause mately 50% of the sensing threshold and does not cause a faulty narrow (~1 ns) pulses to be sent to the decoder via the transformer. output transition. Similarly, if such an event occurs during a The decoder is bistable and is, therefore, either set or reset by transmitted pulse (and is of the worst-case polarity), it reduces the pulses, indicating input logic transitions. In the absence of the received pulse from >1.0 V to 0.75 V—still well above the logic transitions at the input for more than 1 µs, periodic sets of 0.5 V sensing threshold of the decoder. refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal The preceding magnetic flux density values correspond to pulses for more than approximately 5 µs, the input side is assumed specific current magnitudes at given distances from the to be unpowered or nonfunctional, and the isolator output is forced ADuM347x transformers. Figure 44 expresses these allowable to a default state by the watchdog timer circuit (see Table 17). current magnitudes as a function of frequency for selected This situation should occur in the ADuM347x devices only distances. As shown in Figure 44, the ADuM347x is extremely during power-up and power-down operations. immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the The limitation on the magnetic field immunity of the ADuM347x 1 MHz example, a 0.5 kA current must be placed 5 mm away is set by the condition in which induced voltage in the transformer from the ADuM347x to affect the operation of the component. receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under 1k which this can occur. A) DISTANCE = 1m k The 3.3 V operating condition of the ADuM347x is examined NT ( 100 E because it represents the most susceptible mode of operation. RR U The pulses at the transformer output have an amplitude of >1.0 V. E C 10 L The decoder has a sensing threshold of approximately 0.5 V, thus AB DISTANCE = 100mm W establishing a 0.5 V margin in which induced voltages can be LO 1 L tolerated. The voltage induced across the receiving coil is given by M A DISTANCE = 5mm U V = (−dβ/dt) ∑ πrn2; n = 1, 2, …, N XIM 0.1 A M where: β is the magnetic flux density (gauss). 0.01 Nrn iiss tthhee rnaudmiubse or fo tfh teu nrnths t uinr nth ien rtehcee irveicnegiv cionigl. coil (cm). 1k 10kMAGNET1IC00 FkIELD FRE1QMUENCY (H1z0)M 100M 09369-020 Figure 44. Maximum Allowable Current Given the geometry of the receiving coil in the ADuM347x and for Various Current-to-ADuM347x Spacings an imposed requirement that the induced voltage be, at most, At combinations of strong magnetic field and high frequency, any 50% of the 0.5 V margin at the decoder, a maximum allowable loops formed by PCB traces can induce error voltages sufficiently magnetic field is calculated as shown in Figure 43. large to trigger the thresholds of succeeding circuitry. Care should 100 be taken in the layout of such traces to avoid this possibility. X U FL C 10 ETI N AGss) E Mgau 1 ABLY (k ALLOWDENSIT0.1 M U XIM 0.01 A M 0.0011k 10kMAGNETI1C0 0FkIELD FREQ1MUENCY (Hz1)0M 100M 09369-019 Figure 43. Maximum Allowable External Magnetic Flux Density Rev. B | Page 29 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet POWER CONSUMPTION The preceding analysis assumes a 15 pF capacitive load on each data output. If the capacitive load is larger than 15 pF, the additional The V power supply provides power to the iCoupler data DD1 current must be included in the analysis of I and I . channels, as well as to the power converter. For this reason, DD1 ISO (LOAD) the quiescent currents drawn by the power converter and the POWER CONSIDERATIONS primary and secondary I/O channels cannot be determined Soft Start Mode and Current-Limit Protection separately. All of these quiescent power demands are combined When the ADuM347x device first receives power from V , it is in the I current (see the simplified diagram in Figure 45). DD1 DD1 (Q) in soft start mode, and the output voltage, V , is increased The total I supply current is equal to the sum of the quiescent ISO DD1 gradually while it is below the start-up threshold. In soft start operating current; the dynamic current, I , demanded by DD1 (D) mode, the width of the PWM signal is increased gradually by the I/O channels; and any external I load. ISO the primary converter to limit the peak current during V ISO IDD1 (Q) FB IISO power-up. When the output voltage is larger than the start-up PRIMARY SECONDARY threshold, the PWM signal can be transferred from the second- IDD1 (D) CONVERTER CONTROLLER ary controller to the primary converter, and the dc-to-dc converter switches from soft start mode to the normal PWM control mode. IDDP (D) IISO (D) If a short circuit occurs, the push-pull converter shuts down for approximately 2 ms and then enters soft start mode. If, at the end PRIMARY SECONDARY DATA DATA of soft start, a short circuit still exists, the process is repeated, I/O I/O which is called hiccup mode. If the short circuit is cleared, the 4CH 4CH 09369-024 AThDeu AMD3u47Mx3 d4e7vxi cdee venicteesr sa lnsoor hmaavle o ap peuralstieo-nby. -pulse current Figure 45. Power Consumption Within the ADuM347x limit, which is active in startup and normal operation. This Dynamic I/O current is consumed only when operating a channel current limit protects the primary switches, X1 and X2, from at speeds higher than the refresh rate of fr. The dynamic current exceeding approximately 1.2 A peak and also protects the of each channel is determined by its data rate. Figure 18 and transformer windings. Figure 22 show the current for a channel in the forward direction, Data Channel Power Cycle meaning that the input is on the primary side of the part. Figure 19 The ADuM347x data input channels on the primary side and and Figure 23 show the current for a channel in the reverse direc- the data input channels on the secondary side are protected from tion, meaning that the input is on the secondary side of the part. premature operation by UVLO circuitry. Below the minimum Figure 18, Figure 19, Figure 22, and Figure 23 assume a typical operating voltage, the power converter holds its oscillator inactive, 15 pF output load. and all input channel drivers and refresh circuits are idle. Outputs The following relationship allows the total I current to be DD1 are held in a low state to prevent transmission of undefined states IDD1 = (IISO × VISO)/(E × VDD1) + Σ ICHn; n = 1 to 4 (1) during power-up and power-down operations. where: During application of power to V , the primary side circuitry DD1 IDD1 is the total supply input current. is held idle until the UVLO preset voltage is reached. At that time, IISO is the current drawn by the secondary side external load. the data channels are initialized to their default low output state E is the power supply efficiency at the given output load from until they receive data pulses from the secondary side. Figure 13 or Figure 17 at the V and V condition of interest. ISO DD1 The primary side input channels sample the input and send a I is the current drawn by a single channel, determined from CHn pulse to the inactive secondary output. The secondary side Figure 18, Figure 19, Figure 22, or Figure 23, depending on converter begins to accept power from the primary, and the V ISO channel direction. voltage starts to rise. When the secondary side UVLO is reached, The maximum external load can be calculated by subtracting the secondary side outputs are initialized to their default low state the dynamic output load from the maximum allowable load. until data, either a transition or a dc refresh pulse, is received from the corresponding primary side input. It can take up to 1 μs after I = I − Σ I ; n = 1 to 4 (2) ISO (LOAD) ISO (MAX) ISO (D)n the secondary side is initialized for the state of the output to where: correlate with the primary side input. I is the current available to supply an external secondary ISO (LOAD) Secondary side inputs sample their state and transmit it to the side load. primary side. Outputs are valid one propagation delay after the I is the maximum external secondary side load current ISO (MAX) secondary side becomes active. available at V . ISO IISO (D)n is the dynamic load current drawn from VISO by an output or input channel, as shown for a single supply in Figure 20 or Figure 21 or for a double supply in Figure 24 or Figure 25. Rev. B | Page 30 of 36

Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Because the rate of charge of the secondary side is dependent Bipolar ac voltage is the most stringent environment. A 50-year on the soft start cycle, loading conditions, input voltage, and operating lifetime under the bipolar ac condition determines the output voltage level selected, care should be taken in the design maximum working voltage recommended by Analog Devices. to allow the converter to stabilize before valid data is required. In the case of unipolar ac or dc voltage, the stress on the insulation When power is removed from V , the primary side converter is significantly lower. This allows operation at higher working DD1 and coupler shut down when the UVLO level is reached. The voltages while still achieving a 50-year service life. The working secondary side stops receiving power and starts to discharge. voltages listed in Table 11 can be applied while maintaining the The outputs on the secondary side hold the last state that they 50-year minimum lifetime, provided that the voltage conforms received from the primary side until either the UVLO level is to either the unipolar ac or dc voltage cases. Treat any cross- reached and the outputs are placed in their default low state, insulation voltage waveform that does not conform to Figure 47 or the outputs detect a lack of activity from the inputs and the or Figure 48 as a bipolar ac waveform, and limit its peak voltage outputs are set to their default value before the secondary power to the 50-year lifetime voltage value listed in Table 11. reaches UVLO. The voltage presented in Figure 48 is shown as sinusoidal for INSULATION LIFETIME illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The All insulation structures eventually break down when subjected limiting value can be positive or negative, but the voltage cannot to voltage stress over a sufficiently long period. The rate of insu- cross 0 V. lation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. Analog Devices conducts RATED PEAK VOLTAGE ainns uexlatteinosniv set rsuect toufr ee vwailtuhaitnio tnhse tAo DdeutMer3m47inxe d tehvei cleifse.t ime of the 0V 09369-021 Figure 46. Bipolar AC Waveform Accelerated life testing is performed using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined, allowing calcu- RATED PEAK VOLTAGE lTahtieo nva oluf eths es htiomwen t ion f Taialbulree 1a1t tshuem wmoarrkiizneg t vhoel tpaegaek o vfo ilntategreess tf.o r 0V 09369-023 50 years of service life in several operating conditions. In many Figure 47. DC Waveform cases, the working voltage approved by agency testing is higher than the 50-year service life voltage. Operation at working RATED PEAK VOLTAGE voltages higher than the service life voltage listed in Table 11 lTehade sin tosu plarteimona tluifreeti minesu olfa ttihoen A fDaiuluMre3. 47x depends on the voltage 0V 09369-022 waveform type imposed across the isolation barrier. The iCoupler Figure 48. Unipolar AC Waveform insulation structure degrades at different rates, depending on whether the waveform is bipolar ac, dc, or unipolar ac. Figure 46, Figure 47, and Figure 48 illustrate these different isolation voltage waveforms. Rev. B | Page 31 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet OUTLINE DIMENSIONS 7.50 7.20 6.90 20 11 5.60 5.30 5.00 8.20 7.80 1 7.40 10 1.85 0.25 2.00 MAX 1.75 0.09 1.65 COPLA0N.0A5R MITIYN 0.65 BSC 00..3282 PSLEAATNIENG 840°°° 000...975555 0.10 COMPLIANTTO JEDEC STANDARDS MO-150-AE 060106-A Figure 49. 20-Lead Shrink Small Outline Package [SSOP] (RS-20) Dimensions shown in millimeters Rev. B | Page 32 of 36

Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 ORDERING GUIDE Number Number Maximum Maximum Maximum of Inputs, of Inputs, Data Rate Propagation Pulse Width Temperature Package Package Model1, 2, 3 V Side V Side (Mbps) Delay, 5 V (ns) Distortion (ns) Range (°C) Description Option DD1 ISO ADuM3470ARSZ 4 0 1 100 40 −40 to +105 20-Lead SSOP RS-20 ADuM3470CRSZ 4 0 25 60 8 −40 to +105 20-Lead SSOP RS-20 ADuM3470WARSZ 4 0 1 100 40 −40 to +105 20-Lead SSOP RS-20 ADuM3470WCRSZ 4 0 25 60 8 −40 to +105 20-Lead SSOP RS-20 ADuM3471ARSZ 3 1 1 100 40 −40 to +105 20-Lead SSOP RS-20 ADuM3471CRSZ 3 1 25 60 8 −40 to +105 20-Lead SSOP RS-20 ADuM3471WARSZ 3 1 1 100 40 −40 to +105 20-Lead SSOP RS-20 ADuM3471WCRSZ 3 1 25 60 8 −40 to +105 20-Lead SSOP RS-20 ADuM3472ARSZ 2 2 1 100 40 −40 to +105 20-Lead SSOP RS-20 ADuM3472CRSZ 2 2 25 60 8 −40 to +105 20-Lead SSOP RS-20 ADuM3472WARSZ 2 2 1 100 40 −40 to +105 20-Lead SSOP RS-20 ADuM3472WCRSZ 2 2 25 60 8 −40 to +105 20-Lead SSOP RS-20 ADuM3473ARSZ 1 3 1 100 40 −40 to +105 20-Lead SSOP RS-20 ADuM3473CRSZ 1 3 25 60 8 −40 to +105 20-Lead SSOP RS-20 ADuM3473WARSZ 1 3 1 100 40 −40 to +105 20-Lead SSOP RS-20 ADuM3473WCRSZ 1 3 25 60 8 −40 to +105 20-Lead SSOP RS-20 ADuM3474ARSZ 0 4 1 100 40 −40 to +105 20-Lead SSOP RS-20 ADuM3474CRSZ 0 4 25 60 8 −40 to +105 20-Lead SSOP RS-20 ADuM3474WARSZ 0 4 1 100 40 −40 to +105 20-Lead SSOP RS-20 ADuM3474WCRSZ 0 4 25 60 8 −40 to +105 20-Lead SSOP RS-20 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. 3 Tape and reel are available. The addition of an RL7 suffix designates a 7” (500 units) tape and reel option. AUTOMOTIVE PRODUCTS The ADuM3470W, ADuM3471W, ADuM3472W, ADuM3473W, and ADuM3474W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. B | Page 33 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet NOTES Rev. B | Page 34 of 36

Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 NOTES Rev. B | Page 35 of 36

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet NOTES ©2010–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09369-0-5/14(B) Rev. B | Page 36 of 36