Quad-Channel, Digital Isolators, Enhanced System-Level ESD Reliability Data Sheet ADuM3400/ADuM3401/ADuM3402 FEATURES GENERAL DESCRIPTION Enhanced system-level ESD performance per IEC 61000-4-x The ADuM3400/ADuM3401/ADuM34021 are 4-channel digital Low power operation isolators based on the Analog Devices, Inc., iCoupler® technol- 5 V operation ogy. Combining high speed CMOS and monolithic air core 1.4 mA per channel maximum at 0 Mbps to 2 Mbps transformer technology, these isolation components provide 4.3 mA per channel maximum at 10 Mbps outstanding performance characteristics superior to alternatives 34 mA per channel maximum at 90 Mbps such as optocoupler devices. 3.3 V operation iCoupler devices remove the design difficulties commonly 0.9 mA per channel maximum at 0 Mbps to 2 Mbps associated with optocouplers. Typical optocoupler concerns 2.4 mA per channel maximum at 10 Mbps regarding uncertain current transfer ratios, nonlinear transfer 20 mA per channel maximum at 90 Mbps functions, and temperature and lifetime effects are eliminated Bidirectional communication with the simple iCoupler digital interfaces and stable performance 3.3 V/5 V level translation characteristics. The need for external drivers and other discrete High temperature operation: 105°C components is eliminated with these iCoupler products. Further- High data rate: dc to 90 Mbps (NRZ) more, iCoupler devices consume one-tenth to one-sixth the Precise timing characteristics power of optocouplers at comparable signal data rates. 2 ns maximum pulse width distortion 2 ns maximum channel-to-channel matching The isolators provide four independent isolation channels in a High common-mode transient immunity: >25 kV/μs variety of channel configurations and data rates (see the Ordering Output enable function Guide). All models operate with the supply voltage on either 16-lead SOIC wide body, RoHS-compliant package side ranging from 3.0 V to 5.5 V, providing compatibility with Safety and regulatory approvals lower voltage systems as well as enabling a voltage translation UL recognition: 2500 V rms for 1 minute per UL 1577 functionality across the isolation barrier. The isolators have a CSA Component Acceptance Notice 5A patented refresh feature that ensures dc correctness in the absence VDE Certificate of Conformity of input logic transitions and during power-up/power-down DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 conditions. V = 560 V peak IORM In comparison to the ADuM1400/ADuM1401/ADuM1402 APPLICATIONS isolators, the ADuM3400/ADuM3401/ADuM3402 isolators contain various circuit and layout changes to provide increased General-purpose multichannel isolation capability relative to system-level IEC 61000-4-x testing (ESD/ SPI/data converter isolation burst/surge). The precise capability in these tests for either set of RS-232/RS-422/RS-485 transceivers isolators is strongly determined by the design and layout of the Industrial field bus isolation user board or module. For more information, see the AN-793 Application Note, ESD/Latch-Up Considerations with iCoupler Isolation Products. FUNCTIONAL BLOCK DIAGRAMS VDD1 1 16VDD2 VDD1 1 16VDD2 VDD1 1 16VDD2 GND1 2 15GND2 GND1 2 15GND2 GND1 2 15GND2 VIA 3 ENCODE DECODE 14VOA VIA 3 ENCODE DECODE 14VOA VIA 3 ENCODE DECODE 14VOA VIB 4 ENCODE DECODE 13VOB VIB 4 ENCODE DECODE 13VOB VIB 4 ENCODE DECODE 13VOB VIC 5 ENCODE DECODE 12VOC VIC 5 ENCODE DECODE 12VOC VOC 5 DECODE ENCODE 12VIC VID 6 ENCODE DECODE 11VOD VOD 6 DECODE ENCODE 11VID VOD 6 DECODE ENCODE 11VID GNNDC1 87 190VGEN2D2 05985-001 GNVDE11 87 190VGEN2D2 05985-002 GNVDE11 87 190VGEN2D2 05985-003 Figure 1. ADuM3400 Functional Block Diagram Figure 2. ADuM3401 Functional Block Diagram Figure 3. ADuM3402 Functional Block Diagram 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADuM3400/ADuM3401/ADuM3402 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ......................................................... 14 Applications ....................................................................................... 1 ESD Caution................................................................................ 14 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ......................... 15 Functional Block Diagrams ............................................................. 1 Typical Performance Characteristics) .......................................... 18 Revision History ............................................................................... 2 Application Information ................................................................ 20 Specifications ..................................................................................... 3 PC Board Layout ........................................................................ 20 Electrical Characteristics—5 V Operation................................ 3 System-Level ESD Considerations and Enhancements ........ 20 Electrical Characteristics—3.3 V Operation ............................ 6 Propagation Delay-Related Parameters ................................... 20 Electrical Characteristics—Mixed 5 V/3.3 V or 3.3 V/5 V DC Correctness and Magnetic Field Immunity........................... 20 Operation ....................................................................................... 8 Power Consumption .................................................................. 21 Package Characteristics ............................................................. 12 Insulation Lifetime ..................................................................... 22 Regulatory Information ............................................................. 12 Outline Dimensions ....................................................................... 23 Insulation and Safety-Related Specifications .......................... 12 Ordering Guide .......................................................................... 23 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics ............................................................................ 13 Recommended Operating Conditions .................................... 13 REVISION HISTORY 7/2017—Rev. E to Rev. F 4/2014—Rev. B to Rev. C Changes to Logic High Output Voltages Parameter and Logic Changes to Table 5 .......................................................................... 12 Low Output Voltages Parameter, Table 1....................................... 3 Changes to Logic High Output Voltages Parameter and Logic 2/2012—Rev. A to Rev. B Low Output Voltages Parameter, Table 2....................................... 6 Created Hyperlink for Safety and Regulatory Approvals Changes to Logic High Output Voltages Parameter and Logic Entry in Features Section ................................................................. 1 Low Output Voltages Parameter, Table 3....................................... 9 Change to PC Board Layout Section ........................................... 20 7/2016—Rev. D to Rev. E 6/2007—Rev. 0 to Rev. A Changes to Features Section and General Description Section ....... 1 Updated VDE Certification Throughout ....................................... 1 Changes to Electrical Characteristics—3.3 V Operation Section .... 6 Changes to Features, General Description, Note 1, Figure 1, Changes to Electrical Characteristics—Mixed 5 V/3.3 V or 3.3 V/ Figure 2, and Figure 3 ....................................................................... 1 5 V Operation Section and Table 3 .......................................................... 8 Changes to Regulatory Information Section .............................. 12 Changes to Table 12 ................................................................................... 15 Changes to Table 7 and Figure 4 Caption ................................... 13 Changes to Table 13 ................................................................................... 16 Added Table 10; Renumbered Sequentially ................................ 14 Changes to Table 13 ................................................................................... 17 Added Insulation Lifetime Section .............................................. 22 Changes to Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Inserted Figure 21, Figure 22, and Figure 23 .............................. 22 Figure 13, Figure 14, Figure 15, Figure 16 ............................................ 18 Changes to Ordering Guide .......................................................... 23 7/2015—Rev. C to Rev. D 3/2006—Revision 0: Initial Version Changes to Table 5 and Table 6 ..................................................... 12 Rev. F | Page 2 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION All voltages are relative to their respective ground. 4.5 V ≤ V ≤ 5.5 V, 4.5 V ≤ V ≤ 5.5 V; all minimum/maximum specifications apply DD1 DD2 over the entire recommended operation range, unless otherwise noted; all typical specifications are at T = 25°C, V = V = 5 V. A DD1 DD2 Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I 0.57 0.83 mA DDI (Q) Output Supply Current per Channel, Quiescent I 0.29 0.35 mA DDO (Q) ADuM3400, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I 2.9 3.5 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 1.2 1.9 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V Supply Current I 9.0 11.6 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 3.0 5.5 mA 5 MHz logic signal freq. DD2 DD2 (10) 90 Mbps (CRW Grade Only) V Supply Current I 72 100 mA 45 MHz logic signal freq. DD1 DD1 (90) V Supply Current I 19 36 mA 45 MHz logic signal freq. DD2 DD2 (90) ADuM3401, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I 2.5 3.2 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 1.6 2.4 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V Supply Current I 7.4 10.6 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 4.4 6.5 mA 5 MHz logic signal freq. DD2 DD2 (10) 90 Mbps (CRW Grade Only) V Supply Current I 59 82 mA 45 MHz logic signal freq. DD1 DD1 (90) V Supply Current I 32 46 mA 45 MHz logic signal freq. DD2 DD2 (90) ADuM3402, Total Supply Current, Four Channels1 DC to 2 Mbps V or V Supply Current I , I 2.0 2.8 mA DC to 1 MHz logic signal freq. DD1 DD2 DD1 (Q) DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V or V Supply Current I , I 6.0 7.5 mA 5 MHz logic signal freq. DD1 DD2 DD1 (10) DD2 (10) 90 Mbps (CRW Grade Only) V or V Supply Current I , I 51 62 mA 45 MHz logic signal freq. DD1 DD2 DD1 (90) DD2 (90) For All Models Input Currents I , I , I , −10 +0.01 +10 µA 0 V ≤ V , V , V , V ≤ V or V , IA IB IC IA IB IC ID DD1 DD2 I , I , I 0 V ≤ V , V ≤ V or V ID E1 E2 E1 E2 DD1 DD2 Logic High Input Threshold V , V 2.0 V IH EH Logic Low Input Threshold V , V 0.8 V IL EL Logic High Output Voltages V , V , (V or V ) − 0.1 5.0 V I = −20 µA, V = V OAH OBH DD1 DD2 Ox Ix IxH V , V (V or V ) − 0.4 4.8 V I = −3.2 mA, V = V OCH ODH DD1 DD2 Ox Ix IxH Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL V , V 0.04 0.1 V I = 400 µA, V = V OCL ODL Ox Ix IxL 0.2 0.4 V I = 3.2 mA, V = V Ox Ix IxL Rev. F | Page 3 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS ARW Package Minimum Pulse Width2 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 50 65 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 40 ns C = 15 pF, CMOS signal levels PLH PHL L Propagation Delay Skew5 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching6 t 50 ns C = 15 pF, CMOS signal levels PSKCD/OD L BRW Package Minimum Pulse Width2 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 20 32 50 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 15 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 3 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 6 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 CRW Package Minimum Pulse Width2 PW 8.3 11.1 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 90 120 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 18 27 32 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 0.5 2 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 3 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 10 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 2 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 5 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 Rev. F | Page 4 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402 Parameter Symbol Min Typ Max Unit Test Conditions/Comments For All Models Output Disable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L (High/Low-to-High Impedance) Output Enable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L (High Impedance-to-High/Low) Output Rise/Fall Time (10% to 90%) t /t 2.5 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity |CM | 25 35 kV/µs V = V /V , V = 1000 V, H Ix DD1 DD2 CM at Logic High Output7 transient magnitude = 800 V Common-Mode Transient Immunity |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM at Logic Low Output7 transient magnitude = 800 V Refresh Rate f 1.2 Mbps r Input Dynamic Supply Current per Channel8 I 0.20 mA/Mbps DDI (D) Output Dynamic Supply Current per Channel8 I 0.05 mA/Mbps DDO (D) 1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. F | Page 5 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet ELECTRICAL CHARACTERISTICS—3.3 V OPERATION All voltages are relative to their respective ground. 3.0 V ≤ V ≤ 3.6 V, 3.0 V ≤ V ≤ 3.6 V; all minimum/maximum specifications apply DD1 DD2 over the entire recommended operation range, unless otherwise noted; all typical specifications are at T = 25°C, V = V = 3.3 V. A DD1 DD2 Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I 0.31 0.49 mA DDI (Q) Output Supply Current per Channel, Quiescent I 0.19 0.27 mA DDO (Q) ADuM3400, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I 1.6 2.1 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.7 1.2 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V Supply Current I 4.8 7.1 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 1.8 2.3 mA 5 MHz logic signal freq. DD2 DD2 (10) 90 Mbps (CRW Grade Only) V Supply Current I 37 54 mA 45 MHz logic signal freq. DD1 DD1 (90) V Supply Current I 11 15 mA 45 MHz logic signal freq. DD2 DD2 (90) ADuM3401, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I 1.4 1.9 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.9 1.5 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V Supply Current I 4.1 5.6 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 2.5 3.3 mA 5 MHz logic signal freq. DD2 DD2 (10) 90 Mbps (CRW Grade Only) V Supply Current I 31 44 mA 45 MHz logic signal freq. DD1 DD1 (90) V Supply Current I 17 24 mA 45 MHz logic signal freq. DD2 DD2 (90) ADuM3402, Total Supply Current, Four Channels1 DC to 2 Mbps V or V Supply Current I , I 1.2 1.7 mA DC to 1 MHz logic signal freq. DD1 DD2 DD1 (Q) DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V or V Supply Current I , I 3.3 4.4 mA 5 MHz logic signal freq. DD1 DD2 DD1 (10) DD2 (10) 90 Mbps (CRW Grade Only) V or V Supply Current I , I 24 39 mA 45 MHz logic signal freq. DD1 DD2 DD1 (90) DD2 (90) For All Models Input Currents I , I , I , −10 +0.01 +10 µA 0 V ≤ V , V , V , V ≤ V or V , IA IB IC IA IB IC ID DD1 DD2 I , I , I 0 V ≤ V , V ≤ V or V ID E1 E2 E1 E2 DD1 DD2 Logic High Input Threshold V , V 1.6 V IH EH Logic Low Input Threshold V , V 0.4 V IL EL Logic High Output Voltages V , V , (V or V ) − 0.1 3.0 V I = −20 µA, V = V OAH OBH DD1 DD2 Ox Ix IxH V , V (V or V ) − 0.4 2.8 V I = −3.2 mA, V = V OCH ODH DD1 DD2 Ox Ix IxH Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL V , V 0.04 0.1 V I = 400 µA, V = V OCL ODL Ox Ix IxL 0.2 0.4 V I = 3.2 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ARW Package Minimum Pulse Width2 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 50 75 100 ns C = 15 pF, CMOS signal levels PHL PLH L Rev. F | Page 6 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Pulse Width Distortion, |t − t |4 PWD 40 ns C = 15 pF, CMOS signal levels PLH PHL L Propagation Delay Skew5 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching6 t 50 ns C = 15 pF, CMOS signal levels PSKCD/OD L BRW Package Minimum Pulse Width2 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 20 38 50 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 22 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 3 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 6 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 CRW Package Minimum Pulse Width2 PW 8.3 11.1 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 90 120 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 20 34 45 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 0.5 2 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 3 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 16 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 2 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 5 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 For All Models Output Disable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L (High/Low-to-High Impedance) Output Enable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L (High Impedance-to-High/Low) Output Rise/Fall Time (10% to 90%) t /t 3 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity |CM | 25 35 kV/µs V = V /V , V = 1000 V, H Ix DD1 DD2 CM at Logic High Output7 transient magnitude = 800 V Common-Mode Transient Immunity |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM at Logic Low Output7 transient magnitude = 800 V Refresh Rate f 1.1 Mbps r Input Dynamic Supply Current per Channel8 I 0.10 mA/Mbps DDI (D) Output Dynamic Supply Current per Channel8 I 0.03 mA/Mbps DDO (D) 1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. F | Page 7 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OR 3.3 V/5 V OPERATION All voltages are relative to their respective ground. 5 V/3.3 V operation: 4.5 V ≤ V ≤ 5.5 V, 3.0 V ≤ V ≤ 3.6 V; 3.3 V/5 V operation: DD1 DD2 3.0 V ≤ V ≤ 3.6 V, 4.5 V ≤ V ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, DD1 DD2 unless otherwise noted; all typical specifications are at T = 25°C; V = 3.3 V, V = 5 V or V = 5 V, V = 3.3 V. A DD1 DD2 DD1 DD2 Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I DDI (Q) 5 V/3.3 V Operation 0.57 0.83 mA 3.3 V/5 V Operation 0.31 0.49 mA Output Supply Current per Channel, Quiescent I DDO (Q) 5 V/3.3 V Operation 0.29 0.27 mA 3.3 V/5 V Operation 0.19 0.35 mA ADuM3400, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I DD1 DD1 (Q) 5 V/3.3 V Operation 2.9 3.5 mA DC to 1 MHz logic signal freq. 3.3 V/5 V Operation 1.6 2.1 mA DC to 1 MHz logic signal freq. V Supply Current I DD2 DD2 (Q) 5 V/3.3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq. 3.3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) V Supply Current I DD1 DD1 (10) 5 V/3.3 V Operation 9.0 11.6 mA 5 MHz logic signal freq. 3.3 V/5 V Operation 4.8 7.1 mA 5 MHz logic signal freq. V Supply Current I DD2 DD2 (10) 5 V/3.3 V Operation 1.8 2.3 mA 5 MHz logic signal freq. 3.3 V/5 V Operation 3.0 5.5 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) V Supply Current I DD1 DD1 (90) 5 V/3.3 V Operation 72 100 mA 45 MHz logic signal freq. 3.3 V/5 V Operation 37 54 mA 45 MHz logic signal freq. V Supply Current I DD2 DD2 (90) 5 V/3.3 V Operation 11 15 mA 45 MHz logic signal freq. 3.3 V/5 V Operation 19 36 mA 45 MHz logic signal freq. ADuM3401, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I DD1 DD1 (Q) 5 V/3.3 V Operation 2.5 3.2 mA DC to 1 MHz logic signal freq. 3.3 V/5 V Operation 1.4 1.9 mA DC to 1 MHz logic signal freq. V Supply Current I DD2 DD2 (Q) 5 V/3.3 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq. 3.3 V/5 V Operation 1.6 2.4 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) V Supply Current I DD1 DD1 (10) 5 V/3.3 V Operation 7.4 10.6 mA 5 MHz logic signal freq. 3.3 V/5 V Operation 4.1 5.6 mA 5 MHz logic signal freq. V Supply Current I DD2 DD2 (10) 5 V/3.3 V Operation 2.5 3.3 mA 5 MHz logic signal freq. 3.3 V/5 V Operation 4.4 6.5 mA 5 MHz logic signal freq. Rev. F | Page 8 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402 Parameter Symbol Min Typ Max Unit Test Conditions/Comments 90 Mbps (CRW Grade Only) V Supply Current I DD1 DD1 (90) 5 V/3.3 V Operation 59 82 mA 45 MHz logic signal freq. 3.3 V/5 V Operation 31 44 mA 45 MHz logic signal freq. V Supply Current I DD2 DD2 (90) 5 V/3.3 V Operation 17 24 mA 45 MHz logic signal freq. 3.3 V/5 V Operation 32 46 mA 45 MHz logic signal freq. ADuM3402, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I DD1 DD1 (Q) 5 V/3.3 V Operation 2.0 2.8 mA DC to 1 MHz logic signal freq. 3.3 V/5 V Operation 1.2 1.7 mA DC to 1 MHz logic signal freq. V Supply Current I DD2 DD2 (Q) 5 V/3.3 V Operation 1.2 1.7 mA DC to 1 MHz logic signal freq. 3.3 V/5 V Operation 2.0 2.8 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) V Supply Current I DD1 DD1 (10) 5 V/3.3 V Operation 6.0 7.5 mA 5 MHz logic signal freq. 3.3 V/5 V Operation 3.3 4.4 mA 5 MHz logic signal freq. V Supply Current I DD2 DD2 (10) 5 V/3.3 V Operation 3.3 4.4 mA 5 MHz logic signal freq. 3.3 V/5 V Operation 6.0 7.5 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) V Supply Current I DD1 DD1 (90) 5 V/3.3 V Operation 46 62 mA 45 MHz logic signal freq. 3.3 V/5 V Operation 24 39 mA 45 MHz logic signal freq. V Supply Current I DD2 DD2 (90) 5 V/3.3 V Operation 24 39 mA 45 MHz logic signal freq. 3.3 V/5 V Operation 46 62 mA 45 MHz logic signal freq. For All Models Input Currents I , I , I , −10 +0.01 +10 µA 0 V ≤ V ,V , V ,V ≤ V or V , IA IB IC IA IB IC ID DD1 DD2 I , I , I 0 V ≤ V ,V ≤ V or V ID E1 E2 E1 E2 DD1 DD2 Logic High Input Threshold V , V IH EH 5 V/3.3 V Operation 2.0 V 3.3 V/5 V Operation 1.6 V Logic Low Input Threshold V , V IL EL 5 V/3.3 V Operation 0.8 V 3.3 V/5 V Operation 0.4 V Logic High Output Voltages V , V , (V or V ) − (V or V ) V I = −20 µA, V = V OAH OBH DD1 DD2 DD1 DD2 Ox Ix IxH 0.1 V , V (V or V ) − (V or V ) − V I = −3.2 mA, V = V OCH ODH DD1 DD2 DD1 DD2 Ox Ix IxH 0.4 0.2 Logic Low Output Voltages V ,V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL V , V 0.04 0.1 V I = 400 µA, V = V OCL ODL Ox Ix IxL 0.2 0.4 V I = 3.2 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ARW Package Minimum Pulse Width2 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 50 70 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 40 ns C = 15 pF, CMOS signal levels PLH PHL L Propagation Delay Skew5 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching6 t 50 ns C = 15 pF, CMOS signal levels PSKCD/OD L Rev. F | Page 9 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments BRW Package Minimum Pulse Width2 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 15 35 50 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 22 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 3 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 6 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 CRW Package Minimum Pulse Width2 PW 8.3 11.1 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 90 120 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 20 30 40 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 0.5 2 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 3 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 14 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 2 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 5 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 For All Models Output Disable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L (High/Low-to-High Impedance) Output Enable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L (High Impedance-to-High/Low) Output Rise/Fall Time (10% to 90%) t /t C = 15 pF, CMOS signal levels R f L 5 V/3.3 V Operation 3.0 ns 3.3 V/5 V Operation 2.5 ns Common-Mode Transient Immunity |CM | 25 35 kV/µs V = V /V , V = 1000 V, H Ix DD1 DD2 CM at Logic High Output7 transient magnitude = 800 V Common-Mode Transient Immunity |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM at Logic Low Output7 transient magnitude = 800 V Rev. F | Page 10 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Refresh Rate f r 5 V/3.3 V Operation 1.2 Mbps 3.3 V/5 V Operation 1.1 Mbps Input Dynamic Supply Current per Channel8 I DDI (D) 5 V/3.3 V Operation 0.20 mA/Mbps 3.3 V/5 V Operation 0.10 mA/Mbps Output Dynamic Supply Current per Channel8 I DDO (D) 5 V/3.3 V Operation 0.03 mA/Mbps 3.3 V/5 V Operation 0.05 mA/Mbps 1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. F | Page 11 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet PACKAGE CHARACTERISTICS Table 4. Parameter Symbol Min Typ Max Unit Test Conditions/Comments Resistance (Input-to-Output)1 R 1012 Ω I-O Capacitance (Input-to-Output)1 C 2.2 pF f = 1 MHz I-O Input Capacitance2 C 4.0 pF I IC Junction-to-Case Thermal Resistance, Side 1 θ 33 °C/W Thermocouple located at JCI IC Junction-to-Case Thermal Resistance, Side 2 θ 28 °C/W center of package underside JCO 1 Device considered a 2-terminal device; Pin 1 to Pin 8 are shorted together and Pin 9 to Pin 16 are shorted together. 2 Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM3400/ADuM3401/ADuM3402 are approved by the organizations listed in Table 5. Refer to Table 10 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 5. UL CSA CQC VDE Recognized Approved under CSA Component Approved under Certified according to Under 1577 Acceptance Notice 5A CQC11-471543-2012 DIN V VDE V 0884-10 (VDE V 0884-10): 2006-122 Component Recognition Program1 Single Protection, Basic insulation per Basic insulation per Reinforced insulation, 560 V peak 2500 V rms Isolation CSA 60950-1-03 and IEC 60950-1, GB4943.1-2011 400 V rms Voltage 800 V rms (1131 V peak) (588 V peak) maximum maximum working voltage working voltage, tropical climate, altitude ≤ 5000 meters Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage File E214100 File 205078 File CQC14001117249 File 2471900-4880-0001 1 In accordance with UL 1577, each ADuM3400/ADuM3401/ADuM3402 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA). 2 In accordance with DIN V VDE V 0884-10, each ADuM3400/ADuM3401/ADuM3402 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 7.7 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 8.1 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1 Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1) Rev. F | Page 12 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402 DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The * marking on packages denotes DIN V VDE V 0884-10 approval. Table 7. Description Conditions Symbol Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V 560 V peak IORM Input-to-Output Test Voltage, Method B1 V × 1.875 = V , 100% production test, V 1050 V peak IORM PR PR t = 1 sec, partial discharge < 5 pC m Input-to-Output Test Voltage, Method A V × 1.6 = V , t = 60 sec, V IORM PR m PR partial discharge < 5 pC After Environmental Tests Subgroup 1 896 V peak After Input and/or Safety Test Subgroup 2 and Subgroup 3 V × 1.2 = V , t = 60 sec, 672 V peak IORM PR m partial discharge < 5 pC Highest Allowable Overvoltage Transient overvoltage, t = 10 seconds V 4000 V peak TR TR Safety-Limiting Values Maximum value allowed in the event of a failure (see Figure 4) Case Temperature T 150 °C S Side 1 Current I 265 mA S1 Side 2 Current I 335 mA S2 Insulation Resistance at T V = 500 V R >109 Ω S IO S 350 RECOMMENDED OPERATING CONDITIONS 300 Table 8. A) m Parameter Rating T ( 250 EN SIDE #2 Operating Temperature Range (TA) −40°C to +105°C R UR 200 Supply Voltages (VDD1, VDD2)1 3.0 V to 5.5 V C G Input Signal Rise and Fall Times 1.0 ms N TI 150 LIMI SIDE #1 1 All voltages are relative to their respective ground. See the DC Correctness Y- 100 and Magnetic Field Immunity section for information on immunity to T E external magnetic fields. F A S 50 00 50CASE TEMP1E0R0ATURE (°C)150 200 05985-004 Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. F | Page 13 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 9. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational Storage Temperature Range (T ) −65°C to +150°C ST section of this specification is not implied. Operation beyond Ambient Operating Temperature Range (T) −40°C to +105°C A the maximum operating conditions for extended periods may Supply Voltages (V , V )1 −0.5 V to +7.0 V DD1 DD2 affect product reliability. Input Voltage (V , V , V , V , V , V )1, 2 −0.5 V to V + 0.5 V IA IB IC ID E1 E2 DD1 Output Voltage (V , V , V , V )1, 2 −0.5 V to V + 0.5 V ESD CAUTION OA OB OC OD DDO Average Output Current per Pin3 Side 1 (I ) −18 mA to +18 mA O1 Side 2 (I ) −22 mA to +22 mA O2 Common-Mode Transients (CM , CM)4 −100 kV/µs to H L +100 kV/µs 1 All voltages are relative to their respective ground. 2 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section. 3 See Figure 4 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Common- mode transients exceeding the Absolute Maximum Ratings can cause latch- up or permanent damage. Table 10. Maximum Continuous Working Voltage1 Parameter Max Unit Constraint AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime AC Voltage, Unipolar Waveform Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 DC Voltage Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Table 11. Truth Table (Positive Logic) V Input1 V Input2 V State1 V State1 V Output1 Notes Ix Ex DDI DDO OX H H or NC Powered Powered H L H or NC Powered Powered L x L Powered Powered Z x H or NC Unpowered Powered H Outputs return to the input state within 1 µs of V power restoration. DDI x L Unpowered Powered Z x x Powered Unpowered Indeterminate Outputs return to the input state within 1 µs of V power restoration DDO if V state is H or NC. Outputs return to high impedance state within Ex 8 ns of V power restoration if V state is L. DDO Ex 1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively. 2 In noisy environments, connecting VEx to an external logic high or low is recommended. Rev. F | Page 14 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1 1 16 VDD2 *GND1 2 15 GND2* VIA 3 ADuM3400 14 VOA VIB 4 TOP VIEW 13 VOB VIC 5 (Not to Scale) 12 VOC VID 6 11 VOD NC 7 10 VE2 *GND1 8NC = NO CONNECT9 GND2* 05985-005 *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND2 IS RECOMMENDED. IN NOISY ENVIRONMENTS, CONNECTING OUTPUT ENABLES (PIN 7 FOR ADuM3401/ADuM3402 AND PIN 10 FOR ALL MODELS) TO AN EXTERNAL LOGIC HIGH OR LOW IS RECOMMENDED. Figure 5. ADuM3400 Pin Configuration Table 12. ADuM3400 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V. DD1 2, 8 GND Ground 1. Ground reference for Isolator Side 1. 1 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Input C. IC 6 V Logic Input D. ID 7 NC No Connect. 9, 15 GND Ground 2. Ground reference for Isolator Side 2. 2 10 V Output Enable 2. Active high logic input. V , V , V , and V outputs are enabled when V is high or disconnected. E2 OA OB OC OD E2 V , V , V , and V outputs are disabled when V is low. In noisy environments, connecting V to an external logic OA OB OC OD E2 E2 high or low is recommended. 11 V Logic Output D. OD 12 V Logic Output C. OC 13 V Logic Output B. OB 14 V Logic Output A. OA 16 V Supply Voltage for Isolator Side 2, 3.0 V to 5.5 V. DD2 Rev. F | Page 15 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet VDD1 1 16 VDD2 *GND1 2 15 GND2* VIA 3 ADuM3401 14 VOA VIB 4 TOP VIEW 13 VOB VIC 5 (Not to Scale) 12 VOC VOD 6 11 VID VE1 7 10 VE2 *GND1 8 9 GND2* 05985-006 *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND2 IS RECOMMENDED. IN NOISY ENVIRONMENTS, CONNECTING OUTPUT ENABLES (PIN 7 FOR ADuM3401/ADuM3402 AND PIN 10 FOR ALL MODELS) TO AN EXTERNAL LOGIC HIGH OR LOW IS RECOMMENDED. Figure 6. ADuM3401 Pin Configuration Table 13. ADuM3401 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V. DD1 2, 8 GND Ground 1. Ground reference for Isolator Side 1. 1 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Input C. IC 6 V Logic Output D. OD 7 V Output Enable 1. Active high logic input. V output is enabled when V is high or disconnected. V is disabled when E1 OD E1 OD V is low. In noisy environments, connecting V to an external logic high or low is recommended. E1 E1 9, 15 GND Ground 2. Ground reference for Isolator Side 2. 2 10 V Output Enable 2. Active high logic input. V , V , and V outputs are enabled when V is high or disconnected. E2 OA OB OC E2 V , V , and V outputs are disabled when V is low. In noisy environments, connecting V to an external logic high OA OB OC E2 E2 or low is recommended. 11 V Logic Input D. ID 12 V Logic Output C. OC 13 V Logic Output B. OB 14 V Logic Output A. OA 16 V Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V. DD2 Rev. F | Page 16 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402 VDD1 1 16 VDD2 *GND1 2 15 GND2* VIA 3 ADuM3402 14 VOA VIB 4 TOP VIEW 13 VOB VOC 5 (Not to Scale) 12 VIC VOD 6 11 VID VE1 7 10 VE2 *GND1 8 9 GND2* 05985-007 *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND2 IS RECOMMENDED. IN NOISY ENVIRONMENTS, CONNECTING OUTPUT ENABLES (PIN 7 FOR ADuM3401/ADuM3402 AND PIN 10 FOR ALL MODELS) TO AN EXTERNAL LOGIC HIGH OR LOW IS RECOMMENDED. Figure 7. ADuM3402 Pin Configuration Table 14. ADuM3402 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V. DD1 2, 8 GND Ground 1. Ground reference for Isolator Side 1. 1 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Output C. OC 6 V Logic Output D. OD 7 V Output Enable 1. Active high logic input. V and V outputs are enabled when V is high or disconnected. E1 OC OD E1 V and V outputs are disabled when V is low. In noisy environments, connecting V to an external logic high or OC OD E1 E1 low is recommended. 9, 15 GND Ground 2. Ground reference for Isolator Side 2. 2 10 V Output Enable 2. Active high logic input. V and V outputs are enabled when V is high or disconnected. E2 OA OB E2 V and V outputs are disabled when V is low. In noisy environments, connecting V to an external logic high or OA OB E2 E2 low is recommended. 11 V Logic Input D. ID 12 V Logic Input C. IC 13 V Logic Output B. OB 14 V Logic Output A. OA 16 V Supply Voltage for Isolator Side 2, 3.0 V to 5.5 V. DD2 Rev. F | Page 17 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 20 80 15 60 A) m NEL ( 5V mA) T/CHAN 10 RRENT ( 40 5V N U RRE 3.3V C 3.3V CU 5 20 00 20 DA4T0A RATE (Mb60ps) 80 100 05985-008 00 20 DA4T0A RATE (Mb60ps) 80 100 05985-011 Figure 8. Typical Input Supply Current per Channel vs. Data Rate (No Load) Figure 11. Typical ADuM3400 VDD1 Supply Current vs. Data Rate for 5 V and 3.3 V Operation 20 80 15 60 A) m NEL ( mA) T/CHAN 10 RRENT ( 40 N U RE C R CU 5 20 5V 5V 3.3V 3.3V 00 20 DA4T0A RATE (Mb60ps) 80 100 05985-009 00 20 DA4T0A RATE (Mb60ps) 80 100 05985-012 Figure 9. Typical Output Supply Current per Channel vs. Data Rate (No Load) Figure 12. Typical ADuM3400 VDD2 Supply Current vs. Data Rate for 5 V and 3.3 V Operation 20 80 15 60 A) m NEL ( mA) T/CHAN 10 RRENT ( 40 5V REN 5V CU R CU 5 20 3.3V 3.3V 00 20 DA4T0A RATE (Mb60ps) 80 100 05985-010 00 20 DA4T0A RATE (Mb60ps) 80 100 05985-013 Figure 10. Typical Output Supply Current per Channel vs. Data Rate Figure 13. Typical ADuM3401 VDD1 Supply Current vs. Data Rate (15 pF Output Load) for 5 V and 3.3 V Operation Rev. F | Page 18 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402 80 40 60 s) 3.3V n Y ( 35 A) LA m E RENT ( 40 TION D R A CU 5V AG 30 P O 20 R P 5V 3.3V 00 20 DA4T0A RATE (Mb60ps) 80 100 05985-014 25–50 –25 0TEMPERA2T5URE (°C)50 75 100 05985-016 Figure 14. Typical ADuM3401 VDD2 Supply Current vs. Data Rate Figure 16. Propagation Delay vs. Temperature, C Grade for 5 V and 3.3 V Operation 80 60 A) m NT ( 40 E R R U 5V C 20 3.3V 00 20 DA4T0A RATE (Mb60ps) 80 100 05985-015 Figure 15. Typical ADuM3402 VDD1 or VDD2 Supply Current vs. Data Rate for 5 V and 3.3 V Operation Rev. F | Page 19 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet APPLICATION INFORMATION PC BOARD LAYOUT While the ADuM3400/ADuM3401/ADuM3402 improve system- level ESD reliability, they are no substitute for a robust system- The ADuM3400/ADuM3401/ADuM3402 digital isolators level design. See the AN-793 Application Note, ESD/Latch-Up require no external interface circuitry for the logic interfaces. Considerations with iCoupler Isolation Products for detailed Power supply bypassing is strongly recommended at the input recommendations on board layout and system-level design. and output supply pins (see Figure 17). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for V PROPAGATION DELAY-RELATED PARAMETERS DD1 and between Pin 15 and Pin 16 for V . The capacitor value must DD2 Propagation delay is a parameter that describes the time it takes be between 0.01 µF and 0.1 µF. The total lead length between both a logic signal to propagate through a component. The propagation ends of the capacitor and the input power supply pin must not delay to a logic low output can differ from the propagation exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between delay to a logic high. Pin 9 and Pin 16 must also be considered unless the ground pair on each package side is connected close to the package. INPUT (VIx) 50% VDD1 VDD2 tPLH tPHL GNVVDIIAB1 GVVOONABD2 OUTPUT (VOx) 50% 05985-018 VIC/OC VOC/IC Figure 18. Propagation Delay Parameters VGIDNV/ODED11 VVGOEN2DD/I2D 05985-017 Pthuelssee twwiod tphr odpisatgoarttiioonn dise tlhaye vmaaluxeims aunmd disi fafner ienndciec abteiotwn eoefn h ow Figure 17. Recommended Printed Circuit Board Layout accurately the input signal timing is preserved. In applications involving high common-mode transients, care Channel-to-channel matching refers to the maximum amount must be taken to ensure that board coupling across the isolation the propagation delay differs between channels within a single barrier is minimized. Furthermore, the board layout must be ADuM3400/ADuM3401/ADuM3402 component. designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can Propagation delay skew refers to the maximum amount the prop- cause voltage differentials between pins exceeding the Absolute agation delay differs between multiple ADuM3400/ADuM3401/ Maximum Ratings of the device, thereby leading to latch-up or ADuM3402 components operating under the same conditions. permanent damage. DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY See the AN-1109 Application Note for board layout guidelines. Positive and negative logic transitions at the isolator input cause SYSTEM-LEVEL ESD CONSIDERATIONS AND narrow (~1 ns) pulses to be sent to the decoder via the transformer. ENHANCEMENTS The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of System-level ESD reliability (for example, per IEC 61000-4-x) logic transitions at the input for more than ~1 µs, a periodic set is highly dependent on system design, which varies widely of refresh pulses indicative of the correct input state are sent to by application. The ADuM3400/ADuM3401/ADuM3402 ensure dc correctness at the output. If the decoder receives no incorporate many enhancements to make ESD reliability less internal pulses of more than about 5 µs, the input side is assumed dependent on system design. The enhancements include: to be unpowered or nonfunctional, in which case the isolator • ESD protection cells added to all input/output interfaces. output is forced to a default state (see Table 11) by the watchdog • Key metal trace resistances reduced using wider geometry timer circuit. and paralleling of lines with vias. The limitation on the magnetic field immunity of the ADuM3400/ • The SCR effect inherent in CMOS devices minimized by ADuM3401/ADuM3402 is set by the condition in which induced use of guarding and isolation technique between PMOS voltage in the receiving coil of the transformer is sufficiently large and NMOS devices. to either falsely set or reset the decoder. The following analysis • Areas of high electric field concentration eliminated using defines the conditions under which this can occur. The 3.3 V 45° corners on metal traces. operating condition of the ADuM3400/ADuM3401/ADuM3402 • Supply pin overvoltage prevented with larger ESD clamps is examined because it represents the most susceptible mode of between each supply pin and respective ground. operation. Rev. F | Page 20 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402 The pulses at the transformer output have an amplitude greater 1000 than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus A) DISTANCE = 1m k establishing a 0.5 V margin in which induced voltages can be T ( 100 N tolerated. The voltage induced across the receiving coil is given by RE R U V = (−dβ/dt)∑∏rn2; N = 1, 2, … , N E C 10 L B where: A DISTANCE = 100mm W O β is magnetic flux density (gauss). LL 1 A N is the number of turns in the receiving coil. M DISTANCE = 5mm U rn is the radius of the nth turn in the receiving coil (cm). XIM 0.1 A M Given the geometry of the receiving coil in the ADuM3400/ ADuM3401/ADuM3402 and an imposed requirement that 0.01 tdheec oinddeur,c ae dm vaoxlitmaguem b ea lalto wmaobslte 5 m0%ag onfe tthice f 0ie.5ld V is m caalrcguilna taetd t haes 1k 10MkAGNET1IC0 0FkIELD FRE1QMUENCY (H1z0)M 100M 05985-020 Figure 20. Maximum Allowable Current for Various Current-to- shown in Figure 19. ADuM3400/ADuM3401/ADuM3402 Spacings 100 Note that at combinations of strong magnetic field and high X U L frequency, any loops formed by printed circuit board traces F C 10 TI can induce error voltages sufficiently large enough to trigger E AGNss) the thresholds of succeeding circuitry. Care must be taken in E Mgau 1 the layout of such traces to avoid this possibility. Lk ABY ( POWER CONSUMPTION ALLOWDENSIT0.1 The supply current at a given channel of the ADuM3400/ M ADuM3401/ADuM3402 isolator is a function of the supply U XIM 0.01 voltage, the channel data rate, and the channel output load. A M For each input channel, the supply current is given by 0.0011k 10kMAGNETI1C0 0FkIELD FREQ1MUENCY (Hz1)0M 100M 05985-019 IIDDI == IIDDI (Q) × (2f − f) + I ff ≤> 00..55 ffr DDI DDI (D) r DDI (Q) r Figure 19. Maximum Allowable External Magnetic Flux Density For each output channel, the supply current is given by For example, at a magnetic field frequency of 1 MHz, the max- I = I f ≤ 0.5 f imum allowable magnetic field of 0.2 kgauss induces a voltage DDO DDO (Q) r of 0.25 V at the receiving coil, which is about 50% of the sensing I = (I + (0.5 × 10−3) × C × V ) × (2f − f) + I DDO DDO (D) L DDO r DDO (Q) threshold and does not cause a faulty output transition. Similarly, if f > 0.5 f r such an event occurs during a transmitted pulse (and is of the where: worst-case polarity), it reduces the received pulse from >1.0 V to I , I are the input and output dynamic supply currents 0.75 V—still well above the 0.5 V sensing threshold of the decoder. DDI (D) DDO (D) per channel (mA/Mbps). The preceding magnetic flux density values correspond to specific C is the output load capacitance (pF). L current magnitudes at given distances from the ADuM3400/ V is the output supply voltage (V). DDO ADuM3401/ADuM3402 transformers. Figure 20 expresses f is the input logic signal frequency (MHz); it is half of the input these allowable current magnitudes as a function of frequency data rate expressed in units of Mbps. for selected distances. As shown, the ADuM3400/ADuM3401/ f is the input stage refresh rate (Mbps). r ADuM3402 are extremely immune and can be affected only by I , I are the specified input and output quiescent DDI (Q) DDO (Q) extremely large currents operated at high frequency very close supply currents (mA). to the component. For the 1 MHz example noted, place a 0.5 kA current 5 mm away from the ADuM3400/ADuM3401/ADuM3402 to affect the operation of the component. Rev. F | Page 21 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet To calculate the total I and I supply current, the supply In the case of unipolar ac or dc voltage, the stress on the insulation DD1 DD2 currents for each input and output channel corresponding to is significantly lower, which allows operation at higher working V and V are calculated and totaled. Figure 8 provides the voltages while still achieving a 50-year service life. The working DD1 DD2 per-channel input supply current as a function of the data rate. voltages listed in Table 10 can be applied while maintaining the Figure 9 and Figure 10 provide the per-channel supply output 50-year minimum lifetime provided the voltage conforms to either current as a function of the data rate for an unloaded output the unipolar ac or dc voltage cases. Any cross insulation voltage condition and for a 15 pF output condition, respectively. Figure 11 waveform that does not conform to Figure 22 or Figure 23 must through Figure 15 provide the total V and V supply current be treated as a bipolar ac waveform and the peak voltage must DD1 DD2 as a function of the data rate for the ADuM3400/ADuM3401/ be limited to the 50-year lifetime voltage value listed in Table 10. ADuM3402 channel configurations. Note that the voltage presented in Figure 22 is shown as sinusoidal INSULATION LIFETIME for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The All insulation structures eventually break down when subjected limiting value can be positive or negative, but the voltage cannot to voltage stress over a sufficiently long period. The rate of cross 0 V. insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition RATED PEAK VOLTAGE tDoe tvhiec etse sctainrrgi epse orufotr amne edx tbeyn tshivee r seegtu olaf teovrayl uaagteinocnise st,o A dneatelormg ine 0V 05985-021 the lifetime of the insulation structure within the ADuM3400/ Figure 21. Bipolar AC Waveform ADuM3401/ADuM3402. RATED PEAK VOLTAGE Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration 0V 05985-022 factors for several operating conditions are determined. These Figure 22. Unipolar AC Waveform factors allow calculation of the time to failure at the actual working RATED PEAK VOLTAGE voltage. The values shown in Figure 21 summarize the peak voltage faonrd 5 t0h ey emaarsx iomf usemr vCicSeA l/iVfeD foEr aap bpripooveladr waoc rokpinegra vtoinltga gceosn. Idnit mioann, y 0V 05985-023 cases, the approved working voltage is higher than the 50-year Figure 23. DC Waveform service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. The insulation lifetime of the ADuM3400/ADuM3401/ ADuM3402 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 21, Figure 22, and Figure 23 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the recommended maximum working voltage of Analog Devices. Rev. F | Page 22 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402 OUTLINE DIMENSIONS 10.50(0.4134) 10.10(0.3976) 16 9 7.60(0.2992) 7.40(0.2913) 1 8 10.65(0.4193) 10.00(0.3937) 1.27(0.0500) 0.75(0.0295) BSC 2.65(0.1043) 0.25(0.0098) 45° 0.30(0.0118) 2.35(0.0925) 8° 0.10(0.0039) 0° COPLANARITY 0.10 0.51(0.0201) SPELAATNIENG 0.33(0.0130) 1.27(0.0500) 0.31(0.0122) 0.20(0.0079) 0.40(0.0157) (RCINEOFNPEATRRREOENNLCLTEIHNCEOGOSNDMELISPYM)LAEAIANNRNDSETIAORTRNOOESUJNANEORDDETEEDAICN-POSMPFTRIFALONLMPIDMIRLAELIRATIMTDEEESRTFSMEO;SRIRN-0ECU1QH3SU-EADIVAIINMAELDENENSSTIIOGSNNFS.OR 03-27-2007-B Figure 24. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Number Number Maximum Maximum Maximum of Inputs, of Inputs, Data Rate Propagation Pulse Width Temperature Package Model1, 2 V Side V Side (Mbps) Delay, 5 V (ns) Distortion (ns) Range Package Description Option DD1 DD2 ADuM3400ARWZ 4 0 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM3400BRWZ 4 0 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM3400CRWZ 4 0 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM3401ARWZ 3 1 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM3401BRWZ 3 1 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM3401CRWZ 3 1 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM3402ARWZ 2 2 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM3402BRWZ 2 2 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM3402CRWZ 2 2 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16 1 Z = RoHS Compliant Part. 2 Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape-and-reel option. Rev. F | Page 23 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet NOTES ©2006–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05985-0-7/17(F) Rev. F | Page 24 of 24

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