Triple-Channel, Digital Isolators, Enhanced System-Level ESD Reliability Data Sheet ADuM3300/ADuM3301 FEATURES GENERAL DESCRIPTION Enhanced system-level ESD performance per IEC 61000-4-x The ADuM3300/ADuM33011 are 3-channel digital isolators based Low power operation on the Analog Devices, Inc., iCoupler® technology. Combining 5 V operation high speed CMOS and monolithic air core transformer technology, 2.0 mA per channel maximum at 0 Mbps to 2 Mbps these isolation components provide outstanding performance 4.1 mA per channel maximum at 10 Mbps characteristics superior to alternatives, such as optocoupler devices. 36 mA per channel maximum at 90 Mbps iCoupler devices remove the design difficulties commonly 3.3 V operation associated with optocouplers. Typical optocoupler concerns 1.0 mA per channel maximum at 0 Mbps to 2 Mbps regarding uncertain current transfer ratios, nonlinear transfer 2.8 mA per channel maximum at 10 Mbps functions, and temperature and lifetime effects are eliminated 17 mA per channel maximum at 90 Mbps with the simple iCoupler digital interfaces and stable performance Bidirectional communication characteristics. The need for external drivers and other discrete 3.3 V/5 V level translation components is eliminated with these iCoupler products. High temperature operation: 105°C Furthermore, iCoupler devices consume one-tenth to one-sixth High data rate: dc to 90 Mbps (NRZ) the power of optocouplers at comparable signal data rates. Precise timing characteristics 2 ns maximum pulse width distortion The ADuM3300/ADuM3301 isolators provide three independent 2 ns maximum channel-to-channel matching isolation channels in a variety of channel configurations and High common-mode transient immunity: >25 kV/μs data rates (see the Ordering Guide). All models operate with the Output enable function supply voltage on either side ranging from 3.3 V to 5.5 V, providing 16-lead SOIC wide body, RoHS-compliant package compatibility with lower voltage systems as well as enabling a Safety and regulatory approvals voltage translation functionality across the isolation barrier. The UL recognition: 2500 V rms for 1 minute per UL 1577 ADuM3300/ADuM3301 isolators have a patented refresh feature CSA Component Acceptance Notice 5A that ensures dc correctness in the absence of input logic VDE Certificate of Conformity transitions and during power-up/power-down conditions. DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 In comparison to ADuM1300/ADuM1301 isolators, ADuM3300/ VIORM = 560 V peak ADuM3301 isolators contain various circuit and layout changes CQC Certification per GB4943.1-2011 to provide increased capability relative to system-level IEC APPLICATIONS 61000-4-x testing (ESD, burst, and surge). The precise capability General-purpose multichannel isolation in these tests for either the ADuM1300/ADuM1301 or SPI interface/data converter isolation ADuM3300/ADuM3301 products is strongly determined by the RS-232/RS-422/RS-485 transceivers design and layout of the user’s system. Industrial field bus isolation FUNCTIONAL BLOCK DIAGRAMS VDD1 1 16 VDD2 VDD1 1 16 VDD2 GND1 2 15 GND2 GND1 2 15 GND2 VIA 3 ENCODE DECODE 14 VOA VIA 3 ENCODE DECODE 14 VOA VIB 4 ENCODE DECODE 13 VOB VIB 4 ENCODE DECODE 13 VOB VIC 5 ENCODE DECODE 12 VOC VOC 5 DECODE ENCODE 12 VIC NC 6 11 NC NC 6 11 NC NC 7 10 VE2 VE1 7 10 VE2 GND1 8 9 GND2 05984-001 GND1 8 9 GND205984-002 Figure 1. ADuM3300 Functional Block Diagram Figure 2. ADuM3301 Functional Block Diagram 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADuM3300/ADuM3301 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Recommended Operating Conditions .................................... 11 Applications ....................................................................................... 1 Absolute Maximum Ratings ......................................................... 12 General Description ......................................................................... 1 ESD Caution................................................................................ 12 Functional Block Diagrams ............................................................. 1 Pin Configurations and Function Descriptions ......................... 13 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 15 Specifications ..................................................................................... 3 Application Information ................................................................ 17 Electrical Characteristics—5 V Operation................................ 3 PC Board Layout ........................................................................ 17 Electrical Characteristics—3.3 V Operation ............................ 5 System-Level ESD Considerations and Enhancements ........ 17 Electrical Characteristics—Mixed 5 V/3.3 V or 3.3 V/5 V Propagation Delay-Related Parameters ................................... 17 Operation ....................................................................................... 7 DC Correctness and Magnetic Field Immunity........................... 17 Package Characteristics ............................................................. 10 Power Consumption .................................................................. 18 Regulatory Information ............................................................. 10 Insulation Lifetime ..................................................................... 19 Insulation and Safety-Related Specifications .......................... 10 Outline Dimensions ....................................................................... 20 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Ordering Guide .......................................................................... 20 Characteristics ............................................................................ 11 REVISION HISTORY 7/2017—Rev. D to Rev. E 4/2014—Rev. B to Rev. C Changes to Features Section............................................................ 1 Change to Table 5 ........................................................................... 10 Change to Logic High Output Voltages Parameter and Logic Low Output Voltages Parameter, Table 1....................................... 3 2/2012—Rev. A to Rev. B Change to Logic High Output Voltages Parameter and Logic Created Hyperlink for Safety and Regulatory Approvals Low Output Voltages Parameter, Table 2....................................... 5 Entry in Features Section ................................................................. 1 Change to Logic High Output Voltages Parameter and Logic Change to PC Board Layout Section ........................................... 17 Low Output Voltages Parameter, Table 3....................................... 8 Updated Outline Dimensions ....................................................... 20 Changes to Table 5 .......................................................................... 10 6/2007—Rev. 0 to Rev. A 8/2016—Rev. C to Rev. D Updated VDE Certification Throughout ....................................... 1 Changed ADuM330x to ADuM3300/ADuM3301 ... Throughout Changes to Features, General Description, and Note 1 ............... 1 Changed 3 V to 3.3 V and 2.7 to 3.0 V ....................... Throughout Changes to Regulatory Information Section .............................. 10 Changes to Table 3 ............................................................................ 7 Changes to DIN V VDE V 0884-10 (VDE V 0884-10) Changed Supply Voltages Parameter, Table 8 ............................. 11 Insulation Characteristics .............................................................. 11 Changes to Table 12 ........................................................................ 13 Added Table 10 ............................................................................... 12 Changes to Table 13 ........................................................................ 14 Added Insulation Lifetime Section .............................................. 19 Changes to Figure 6 to Figure 11 .................................................. 15 Changes to Figure 12 and Figure 13 ............................................. 16 3/2006—Revision 0: Initial Version Changes to Ordering Guide .......................................................... 20 Rev. E | Page 2 of 20

Data Sheet ADuM3300/ADuM3301 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION All voltages are relative to their respective ground. 4.5 V ≤ V ≤ 5.5 V, 4.5 V ≤ V ≤ 5.5 V; all minimum/maximum specifications apply DD1 DD2 over the entire recommended operation range, unless otherwise noted; all typical specifications are at T = 25°C, V = V = 5 V. A DD1 DD2 Table 1. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I 0.66 0.97 mA DDI (Q) Output Supply Current per Channel, Quiescent I 0.39 0.55 mA DDO (Q) ADuM3300, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I 2.4 3.3 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 1.1 2.1 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V Supply Current I 7.0 8.1 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 2.7 3.6 mA 5 MHz logic signal freq. DD2 DD2 (10) 90 Mbps (CRW Grade Only) V Supply Current I 54 77 mA 45 MHz logic signal freq. DD1 DD1 (90) V Supply Current I 15 31 mA 45 MHz logic signal freq. DD2 DD2 (90) ADuM3301, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I 2.0 3.1 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 1.6 2.3 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V Supply Current I 5.5 6.9 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 3.9 5.4 mA 5 MHz logic signal freq. DD2 DD2 (10) 90 Mbps (CRW Grade Only) V Supply Current I 41 57 mA 45 MHz logic signal freq. DD1 DD1 (90) V Supply Current I 28 41 mA 45 MHz logic signal freq. DD2 DD2 (90) For All Models Input Currents I , I , I , −10 +0.01 +10 µA 0 V ≤ V , V , V , V ≤ V or V , IA IB IC IA IB IC ID DD1 DD2 I , I , I 0 V ≤ V , V ≤ V or V ID E1 E2 E1 E2 DD1 DD2 Logic High Input Threshold V , V 2.0 V IH EH Logic Low Input Threshold V , V 0.8 V IL EL Logic High Output Voltages V , V , (V or 5.0 V I = −20 µA, V = V OAH OBH DD1 Ox Ix IxH V , V V ) − 0.1 OCH ODH DD2 (V or 4.8 V I = −3.2 mA, V = V DD1 Ox Ix IxH V ) − 0.4 DD2 Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 0.2 0.4 V I = 3.2 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ADuM3300ARWZ/ADuM3301ARWZ Minimum Pulse Width2 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 50 65 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 40 ns C = 15 pF, CMOS signal levels PLH PHL L Propagation Delay Skew5 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching6 t 50 ns C = 15 pF, CMOS signal levels PSKCD/OD L Rev. E | Page 3 of 20

ADuM3300/ADuM3301 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions ADuM3300BRWZ/ADuM3301BRWZ Minimum Pulse Width2 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 20 32 50 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 15 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 3 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 6 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 ADuM3300CRWZ/ADuM3301CRWZ Minimum Pulse Width2 PW 8.3 11.1 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 90 120 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 18 27 32 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 0.5 2 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 3 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 10 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 2 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 5 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 For All Models Output Disable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L (High/Low-to-High Impedance) Output Enable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L (High Impedance-to-High/Low) Output Rise/Fall Time (10% to 90%) t /t 2.5 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity |CM | 25 35 kV/µs V = V or V , V = 1000 V, H Ix DD1 DD2 CM at Logic High Output7 transient magnitude = 800 V Common-Mode Transient Immunity |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM at Logic Low Output7 transient magnitude = 800 V Refresh Rate f 1.2 Mbps r Input Dynamic Supply Current per Channel8 I 0.20 mA/Mbps DDI (D) Output Dynamic Supply Current per Channel8 I 0.05 mA/Mbps DDO (D) 1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3300/ADuM3301 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. E | Page 4 of 20

Data Sheet ADuM3300/ADuM3301 ELECTRICAL CHARACTERISTICS—3.3 V OPERATION All voltages are relative to their respective ground. 3.0 V ≤ V ≤ 3.6 V, 3.0 V ≤ V ≤ 3.6 V; all minimum/maximum specifications apply DD1 DD2 over the entire recommended operation range, unless otherwise noted; all typical specifications are at T = 25°C, V = V = 3.3 V. A DD1 DD2 Table 2. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I 0.37 0.57 mA DDI (Q) Output Supply Current per Channel, Quiescent I 0.25 0.37 mA DDO (Q) ADuM3300, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I 1.4 1.9 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.7 1.2 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V Supply Current I 3.8 5.3 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 1.5 2.1 mA 5 MHz logic signal freq. DD2 DD2 (10) 90 Mbps (CRW Grade Only) V Supply Current I 28 41 mA 45 MHz logic signal freq. DD1 DD1 (90) V Supply Current I 8.2 11 mA 45 MHz logic signal freq. DD2 DD2 (90) ADuM3301, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I 1.1 1.6 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.9 1.4 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V Supply Current I 3.0 4.1 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 2.2 2.9 mA 5 MHz logic signal freq. DD2 DD2 (10) 90 Mbps (CRW Grade Only) V Supply Current I 22 31 mA 45 MHz logic signal freq. DD1 DD1 (90) V Supply Current I 15 21 mA 45 MHz logic signal freq. DD2 DD2 (90) For All Models Input Currents I , I , I , −10 +0.01 +10 µA 0 V ≤ V , V , V , V ≤ V or V , IA IB IC IA IB IC ID DD1 DD2 I , I , I 0 V ≤ V ,V ≤ V or V ID E1 E2 E1 E2 DD1 DD2 Logic High Input Threshold V , V 1.6 V IH EH Logic Low Input Threshold V , V 0.4 V IL EL Logic High Output Voltages V , V , (V or 3.0 V I = −20 µA, V = V OAH OBH DD1 Ox Ix IxH V , V V ) − 0.1 OCH ODH DD2 (V or 2.8 V I = −3.2 mA, V = V DD1 Ox Ix IxH V ) − 0.4 DD2 Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 0.2 0.4 V I = 3.2 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ADuM3300ARWZ/ADuM3301ARWZ Minimum Pulse Width2 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 50 75 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 40 ns C = 15 pF, CMOS signal levels PLH PHL L Propagation Delay Skew5 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching6 t 50 ns C = 15 pF, CMOS signal levels PSKCD/OD L Rev. E | Page 5 of 20

ADuM3300/ADuM3301 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions ADuM3300BRWZ/ADuM3301BRWZ Minimum Pulse Width2 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 20 38 50 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 22 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 3 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 6 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 ADuM3300CRWZ/ADuM3301CRWZ Minimum Pulse Width2 PW 8.3 11.1 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 90 120 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 20 34 45 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 0.5 2 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 3 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 16 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 2 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 5 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 For All Models Output Disable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L (High/Low-to-High Impedance) Output Enable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L (High Impedance-to-High/Low) Output Rise/Fall Time (10% to 90%) t /t 3 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity |CM | 25 35 kV/µs V = V or V , V = 1000 V, H Ix DD1 DD2 CM at Logic High Output7 transient magnitude = 800 V Common-Mode Transient Immunity |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM at Logic Low Output7 transient magnitude = 800 V Refresh Rate f 1.1 Mbps r Input Dynamic Supply Current per Channel8 I 0.10 mA/Mbps DDI (D) Output Dynamic Supply Current per Channel8 I 0.03 mA/Mbps DDO (D) 1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3300/ADuM3301 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. E | Page 6 of 20

Data Sheet ADuM3300/ADuM3301 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OR 3.3 V/5 V OPERATION All voltages are relative to their respective ground. 5 V/3.3 V operation: 4.5 V ≤ V ≤ 5.5 V, 3.0 V ≤ V ≤ 3.6 V. 3.3 V/5 V operation: DD1 DD2 3.0 V ≤ V ≤ 3.6 V, 4.5 V ≤ V ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range, DD1 DD2 unless otherwise noted. All typical specifications are at T = 25°C; V = 3.3 V, V = 5 V or V = 5 V, V = 3.3 V. A DD1 DD2 DD1 DD2 Table 3. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I DDI (Q) 5 V/3 V Operation 0.66 0.97 mA 3 V/5 V Operation 0.37 0.57 mA Output Supply Current per Channel, Quiescent I DDO (Q) 5 V/3 V Operation 0.25 0.37 mA 3 V/5 V Operation 0.39 0.55 mA ADuM3300, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I DD1 DD1 (Q) 5 V/3 V Operation 2.4 3.3 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.4 1.9 mA DC to 1 MHz logic signal freq. V Supply Current I DD2 DD2 (Q) 5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.1 2.1 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) V Supply Current I DD1 DD1 (10) 5 V/3 V Operation 7.0 8.1 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.8 5.3 mA 5 MHz logic signal freq. V Supply Current I DD2 DD2 (10) 5 V/3 V Operation 1.5 2.1 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.7 3.6 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) V Supply Current I DD1 DD1 (90) 5 V/3 V Operation 54 77 mA 45 MHz logic signal freq. 3 V/5 V Operation 28 41 mA 45 MHz logic signal freq. V Supply Current I DD2 DD2 (90) 5 V/3 V Operation 8.2 11 mA 45 MHz logic signal freq. 3 V/5 V Operation 15 31 mA 45 MHz logic signal freq. ADuM3301, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I DD1 DD1 (Q) 5 V/3 V Operation 2.0 3.1 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.1 1.6 mA DC to 1 MHz logic signal freq. V Supply Current I DD2 DD2 (Q) 5 V/3 V Operation 0.9 1.4 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.6 2.3 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) V Supply Current I DD1 DD1 (10) 5 V/3 V Operation 5.5 6.9 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.0 4.1 mA 5 MHz logic signal freq. V Supply Current I DD2 DD2 (10) 5 V/3 V Operation 2.2 2.9 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.9 5.4 mA 5 MHz logic signal freq. Rev. E | Page 7 of 20

ADuM3300/ADuM3301 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions 90 Mbps (CRW Grade Only) V Supply Current I DD1 DD1 (90) 5 V/3 V Operation 41 57 mA 45 MHz logic signal freq. 3 V/5 V Operation 22 31 mA 45 MHz logic signal freq. V Supply Current I DD2 DD2 (90) 5 V/3 V Operation 15 21 mA 45 MHz logic signal freq. 3 V/5 V Operation 28 41 mA 45 MHz logic signal freq. For All Models Input Currents I , I , I , −10 +0.01 +10 µA 0 V ≤ V , V , V , V ≤ V or V , IA IB IC IA IB IC ID DD1 DD2 I , I , I 0 V ≤ V , V ≤ V or V ID E1 E2 E1 E2 DD1 DD2 Logic High Input Threshold V , V IH EH 5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V Logic Low Input Threshold V , V IL EL 5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V Logic High Output Voltages V , V , (V or (V or V ) V I = −20 µA, V = V OAH OBH DD1 DD1 DD2 Ox Ix IxH V , V V ) − 0.1 OCH ODH DD2 (V or (V or V I = −3.2 mA, V = V DD1 DD1 Ox Ix IxH V ) − 0.4 V ) − 0.2 DD2 DD2 Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 0.2 0.4 V I = 3.2 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ADuM3300ARWZ/ADuM3301ARWZ Minimum Pulse Width2 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 50 70 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 40 ns C = 15 pF, CMOS signal levels PLH PHL L Propagation Delay Skew5 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching6 t 50 ns C = 15 pF, CMOS signal levels PSKCD/OD L ADuM3300BRWZ/ADuM3301BRWZ Minimum Pulse Width2 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 15 35 50 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 22 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 3 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 6 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 ADuM3300CRWZ/ADuM3301CRWZ Minimum Pulse Width2 PW 8.3 11.1 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 90 120 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 20 30 40 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 0.5 2 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 3 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 14 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 2 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 5 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 Rev. E | Page 8 of 20

Data Sheet ADuM3300/ADuM3301 Parameter Symbol Min Typ Max Unit Test Conditions For All Models Output Disable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L (High/Low-to-High Impedance) Output Enable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L (High Impedance-to-High/Low) Output Rise/Fall Time (10% to 90%) t /t C = 15 pF, CMOS signal levels R F L 5 V/3.3 V Operation 3.0 ns 3.3 V/5 V Operation 2.5 ns Common-Mode Transient Immunity |CM | 25 35 kV/µs V = V or V , V = 1000 V, H Ix DD1 DD2 CM at Logic High Output7 transient magnitude = 800 V Common-Mode Transient Immunity |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM at Logic Low Output7 transient magnitude = 800 V Refresh Rate f r 5 V/3.3 V Operation 1.2 Mbps 3.3 V/5 V Operation 1.1 Mbps Input Dynamic Supply Current per Channel8 I DDI (D) 5 V/3.3 V Operation 0.20 mA/Mbps 3.3 V/5 V Operation 0.10 mA/Mbps Output Dynamic Supply Current per Channel8 I DDO (D) 5 V/3.3 V Operation 0.05 mA/Mbps 3.3 V/5 V Operation 0.03 mA/Mbps 1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3300/ADuM3301 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. E | Page 9 of 20

ADuM3300/ADuM3301 Data Sheet PACKAGE CHARACTERISTICS Table 4. Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input to Output)1 R 1012 Ω I-O Capacitance (Input to Output)1 C 2.2 pF f = 1 MHz I-O Input Capacitance2 C 4.0 pF I IC Junction-to-Case Thermal Resistance, Side 1 θ 33 °C/W Thermocouple located at JCI IC Junction-to-Case Thermal Resistance, Side 2 θ 28 °C/W center of package underside JCO 1 The device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. 2 Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM3300/ADuM3301 is approved by the organizations listed in Table 5. See Table 10 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 5. UL CSA VDE CQC Recognized under Approved under CSA Component Certified according to Approved under CQC11-471543-2015 UL 1577 Component Acceptance Notice 5A DIN V VDE V 0884-10 Recognition Program1 (VDE V 0884-10): 2006-122 Single protection, Basic insulation per CSA 60950-1-03 Reinforced insulation, Basic insulation per GB4943.1-2011, 2500 V rms isolation and IEC 60950-1, 800 V rms (1131 V peak) 560 V peak 760 V rms (1075 V peak) maximum voltage maximum working voltage working voltage, tropical climate, Reinforced insulation per altitude ≤ 5000 meters CSA 60950-1-03 and IEC 60950-1, Reinforced insulation per GB4943.1-2011, 400 V rms (566 V peak) maximum 380 V rms (537 V peak) maximum working voltage working voltage, tropical climate, altitude ≤ 5000 meters File E214100 File 205078 File 2471900-4880-0001 File CQC16001160843 1 In accordance with UL1577, the ADuM3300/ADuM3301 are proof tested by applying an insulation test voltage ≥3000 V rms for 1 second (current leakage detection limit = 5 μA). 2 In accordance with DIN V VDE V 0884-10, the ADuM3300/ADuM3301 are proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 7.7 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 8.1 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Rev. E | Page 10 of 20

Data Sheet ADuM3300/ADuM3301 DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage. Table 7. Description Conditions Symbol Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V 560 V peak IORM Input-to-Output Test Voltage, Method B1 V × 1.875 = V , 100% production test, t = 1 sec, V 1050 V peak IORM PR m PR partial discharge < 5 pC Input-to-Output Test Voltage, Method A V × 1.6 = V , t = 60 sec, partial discharge < 5 pC V IORM PR m PR After Environmental Tests Subgroup 1 896 V peak After Input and/or Safety Test Subgroup 2 V × 1.2 = V , t = 60 sec, partial discharge < 5 pC 672 V peak IORM PR m and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, t = 10 seconds V 4000 V peak TR TR Safety-Limiting Values Maximum value allowed in the event of a failure (see Figure 3) Case Temperature T 150 °C S Side 1 Current I 265 mA S1 Side 2 Current I 335 mA S2 Insulation Resistance at T V = 500 V R >109 Ω S IO S 350 RECOMMENDED OPERATING CONDITIONS 300 Table 8. A) m Parameter Symbol Min Max Unit T ( 250 EN SIDE #2 Operating Temperature TA −40 +105 °C R UR 200 Supply Voltages1 VDD1, VDD2 3.0 5.5 V C G Input Signal Rise and Fall Times 1.0 ms N TI 150 LIMI SIDE #1 1 All voltages are relative to their respective ground. See the DC Correctness Y- 100 and Magnetic Field Immunity section for information on immunity to external ET magnetic fields. F A S 50 00 50CASE TEMP1E0R0ATURE (°C)150 200 05984-003 Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. E | Page 11 of 20

ADuM3300/ADuM3301 Data Sheet ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 9. stress rating only; functional operation of the product at these Parameter Symbol Min Max Unit or any other conditions above those indicated in the operational Storage Temperature T −65 +150 °C ST section of this specification is not implied. Operation beyond Ambient Operating T −40 +105 °C A the maximum operating conditions for extended periods may Temperature affect product reliability. Supply Voltages1 V , V −0.5 +7.0 V DD1 DD2 Input Voltage1, 2 V , V , V , −0.5 V + 0.5 V ESD CAUTION IA IB IC DDI V , V , V ID E1 E2 Output Voltage1, 2 V , V , V , −0.5 V + 0.5 V OA OB OC DDO V OD Average Output Current per Pin3 Side 1 I −23 +23 mA O1 Side 2 I −30 +30 mA O2 Common-Mode CM , CM −100 +100 kV/µs H L Transients4 1 All voltages are relative to their respective ground. 2 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. 3 See Figure 3 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Common- mode transients exceeding the Absolute Maximum Rating can cause latch-up or permanent damage. Table 10. Maximum Continuous Working Voltage1 Parameter Max Unit Constraint AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime AC Voltage, Unipolar Waveform Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 DC Voltage Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Table 11. Truth Table (Positive Logic) V Input1 V Input2 V State1 V State1 V Output1 Notes IX EX DDI DDO OX H H or NC Powered Powered H L H or NC Powered Powered L X L Powered Powered Z X H or NC Unpowered Powered H Outputs return to the input state within 1 µs of V power DDI restoration X L Unpowered Powered Z X X Powered Unpowered Indeterminate Outputs return to the input state within 1 µs of V power DDO restoration if V state is H or NC EX Outputs return to high impedance state within 8 ns of V DDO power restoration if V state is L EX 1 VIX and VOX refer to the input and output signals of a given channel (A, B, or C). VEX refers to the output enable signal on the same side as the VOX outputs. VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively. 2 In noisy environments, connecting VEX to an external logic high or low is recommended. Rev. E | Page 12 of 20

Data Sheet ADuM3300/ADuM3301 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1 1 16 VDD2 GND1* 2 15 GND2** VIA 3 ADuM3300 14 VOA VIB 4 TOP VIEW 13 VOB VIC 5 (Not to Scale) 12 VOC NC 6 11 NC NC 7 10 VE2 GND1* 8 9 GND2** NC = NO CONNECT *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. **PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED, AND CONNECTING BCAOOLLNT HNM EOTCODT EGINLNSGD) O2T IUOST ARPNEU CTEO XEMTNEMARBENLNAEDLSE LD(PO. IIGNN I 7CN FOHOIISGRYH A EODNRuVM LIR3OO3W0N1 MI SAE NRNDET CSPO,INM 1M0 EFNODRED. 05984-004 Figure 4. ADuM3300 Pin Configuration Table 12. ADuM3300 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V. DD1 2, 8 GND Ground 1. Ground Reference for Isolator Side 1. 1 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Input C. IC 6, 7, 11 NC No Connect. 9, 15 GND Ground 2. Ground Reference for Isolator Side 2. 2 10 V Output Enable 2. Active high logic input. V , V , and V outputs are enabled when V is high or disconnected. E2 OA OB OC E2 V , V , and V outputs are disabled when V is low. In noisy environments, connecting V to an external logic OA OB OC E2 E2 high or low is recommended. 12 V Logic Output C. OC 13 V Logic Output B. OB 14 V Logic Output A. OA 16 V Supply Voltage for Isolator Side 2, 3.0 V to 5.5 V. DD2 Rev. E | Page 13 of 20

ADuM3300/ADuM3301 Data Sheet VDD1 1 16 VDD2 *GND1 2 15 GND2** VIA 3 ADuM3301 14 VOA VIB 4 TOP VIEW 13 VOB VOC 5 (Not to Scale) 12 VIC NC 6 11 NC VE1 7 10 VE2 *GND1 8 9 GND2** NC = NO CONNECT *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, **APAINNNDD 9 CC AOONNNDNN PEEICCNTT 1IINN5 GGA RBBEOO TITNHHT TETOORN GGANNLDDL12Y II SSC ORRNEENCCEOOCMMTMMEEEDNN,DDEEDD.. 05984-005 Figure 5. ADuM3301 Pin Configuration Table 13. ADuM3301 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V. DD1 2, 8 GND Ground 1. Ground reference for Isolator Side 1. 1 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Output C. OC 6, 11 NC No Connect. 7 V Output Enable 1. Active high logic input. V output is enabled when V is high or disconnected. V is E1 OC E1 OC disabled when V is low. In noisy environments, connecting V to an external logic high or low is E1 E1 recommended. 9, 15 GND Ground 2. Ground reference for Isolator Side 2. 2 10 V Output Enable 2. Active high logic input. V and V outputs are enabled when V is high or disconnected. E2 OA OB E2 V and V outputs are disabled when V is low. In noisy environments, connecting V to an external logic OA OB E2 E2 high or low is recommended. 12 V Logic Input C. IC 13 V Logic Output B. OB 14 V Logic Output A. OA 16 V Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V. DD2 Rev. E | Page 14 of 20

Data Sheet ADuM3300/ADuM3301 TYPICAL PERFORMANCE CHARACTERISTICS 20 80 15 60 A) m NEL ( 5V mA) RENT/CHAN 10 3.3V CURRENT ( 40 5V R CU 5 20 3.3V 00 20 DA4T0A RATE (Mb60ps) 80 100 05984-006 00 20 DA4T0A RATE (Mb60ps) 80 100 05984-009 Figure 6. Typical Input Supply Current per Channel vs. Data Rate (No Load) Figure 9. Typical ADuM3300 VDD1 Supply Current vs. Data Rate for 5 V and 3.3 V Operation 20 80 15 60 A) m NEL ( mA) HAN 10 NT ( 40 C E RENT/ CURR R CU 5 20 5V 5V 3.3V 3.3V 00 20 DA4T0A RATE (Mb60ps) 80 100 05984-007 00 20 DA4T0A RATE (Mb60ps) 80 100 05984-010 Figure 7. Typical Output Supply Current per Channel vs. Data Rate (No Load) Figure 10. Typical ADuM3300 VDD2 Supply Current vs. Data Rate for 5 V and 3.3 V Operation 20 80 A) 15 60 m EL ( A) N m HAN 10 NT ( 40 C E RENT/ 5V CURR 5V R CU 5 20 3.3V 3.3V 00 20 DA4T0A RATE (Mb60ps) 80 100 05984-008 00 20 DA4T0A RATE (Mb60ps) 80 100 05984-011 Figure 8. Typical Output Supply Current per Channel vs. Data Rate Figure 11. Typical ADuM3301 VDD1 Supply Current vs. Data Rate (15 pF Output Load) for 5 V and 3.3 V Operation Rev. E | Page 15 of 20

ADuM3300/ADuM3301 Data Sheet 80 40 60 s) 3.3V n Y ( 35 mA) ELA RENT ( 40 TION D R A U G C 5V PA 30 O 20 R P 5V 3.3V 00 20 DA4T0A RATE (Mb60ps) 80 100 05984-012 25–50 –25 0TEMPERA2T5URE (°C)50 75 100 05984-019 Figure 12. Typical ADuM3301 VDD2 Supply Current vs. Data Rate Figure 13. Propagation Delay vs. Temperature, C Grade for 5 V and 3.3 V Operation Rev. E | Page 16 of 20

Data Sheet ADuM3300/ADuM3301 APPLICATION INFORMATION PC BOARD LAYOUT While the ADuM3300/ADuM3301 improve system-level ESD reliability, they are no substitute for a robust system-level The ADuM3300/ADuM3301 digital isolator requires no external design. See Application Note AN-793 ESD/Latch-Up interface circuitry for the logic interfaces. Power supply Considerations with iCoupler Isolation Products for detailed bypassing is strongly recommended at the input and output recommendations on board layout and system-level design. supply pins (see Figure 14). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for V and PROPAGATION DELAY-RELATED PARAMETERS DD1 between Pin 15 and Pin 16 for V . The capacitor value should DD2 Propagation delay is a parameter that describes the time it takes be between 0.01 µF and 0.1 µF. The total lead length between a logic signal to propagate through a component. The propagation both ends of the capacitor and the input power supply pin delay to a logic low output can differ from the propagation should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 delay to a logic high. and between Pin 9 and Pin 16 should be considered unless the ground pair on each package side is connected close to the INPUT (VIX) 50% package. tPLH tPHL GVNDVDDIA11 VGVDONDAD22 OUTPUT (VOX) 50% 05984-016 VIB VOB Figure 15. Propagation Delay Parameters VIC/OC VOC/IC NC NC Pulse width distortion is the maximum difference between GNVDE11 GVEN2D2 05984-015 tahcecsuer attweoly p trhoep iangpautito snig dnealla’sy t vimaliunegs iasn pdr eiss earnv eindd. i cation of how Figure 14. Recommended Printed Circuit Board Layout Channel-to-channel matching refers to the maximum amount In applications involving high common-mode transients, care the propagation delay differs between channels within a single should be taken to ensure that board coupling across the ADuM3300/ADuM3301 component. isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur Propagation delay skew refers to the maximum amount the equally affects all pins on a given component side. Failure to propagation delay differs between multiple ADuM3300/ ensure this could cause voltage differentials between pins ADuM3301 components operating under the same conditions. exceeding the device’s absolute maximum ratings, thereby DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY leading to latch-up or permanent damage. Positive and negative logic transitions at the isolator input cause See the AN-1109 Application Note for board layout guidelines. narrow (~1 ns) pulses to be sent to the decoder via the transformer. SYSTEM-LEVEL ESD CONSIDERATIONS AND The decoder is bistable and is, therefore, either set or reset by ENHANCEMENTS the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 µs, a periodic set System-level ESD reliability (for example, per IEC 61000-4-x) is of refresh pulses indicative of the correct input state is sent to highly dependent on system design, which varies widely by ensure dc correctness at the output. If the decoder receives no application. The ADuM3300/ADuM3301 incorporate many internal pulses of more than about 5 µs, the input side is enhancements to make ESD reliability less dependent on system assumed to be unpowered or nonfunctional, in which case the design. The enhancements include isolator output is forced to a default state (see Table 11) by the • ESD protection cells added to all input/output interfaces. watchdog timer circuit. • Key metal trace resistances reduced using wider geometry The limitation on the ADuM3300/ADuM3301 magnetic field and paralleling of lines with vias. immunity is set by the condition in which induced voltage in the • The SCR effect inherent in CMOS devices minimized by transformer’s receiving coil is sufficiently large to either falsely use of guarding and isolation technique between PMOS set or reset the decoder. The following analysis defines the and NMOS devices. conditions under which this can occur. The 3 V operating • Areas of high electric field concentration eliminated using condition of the ADuM3300/ADuM3301 are examined because 45° corners on metal traces. it represents the most susceptible mode of operation. • Supply pin overvoltage prevented with larger ESD clamps between each supply pin and its respective ground. Rev. E | Page 17 of 20

ADuM3300/ADuM3301 Data Sheet The pulses at the transformer output have an amplitude greater 1000 than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus A) DISTANCE = 1m k establishing a 0.5 V margin in which induced voltages can be T ( 100 N tolerated. The voltage induced across the receiving coil is given by RE R U V = (−dβ/dt) ∑π rn2; n = 1, 2, … , N E C 10 L B where: A DISTANCE = 100mm W O β is magnetic flux density (gauss). L 1 L A rn is the radius of the nth turn in the receiving coil (cm). UM DISTANCE = 5mm M N is the number of turns in the receiving coil. XI 0.1 A M Given the geometry of the receiving coil in the ADuM330x and a5n0% im opf othseed 0 r.5e qVu imreamrgeinnt atth atht eth dee cinodduecr,e ad mvoalxtaimgeu ims a at lmlowosatb le 0.011k 10MkAGNET1IC0 0FkIELD FRE1QMUENCY (H1z0)M 100M 05984-018 magnetic field is calculated as shown in Figure 16. Figure 17. Maximum Allowable Current 100 for Various Current-to-ADuM3300/ADuM3301 Spacings X U L Note that at combinations of strong magnetic field and high F TIC 10 frequency, any loops formed by printed circuit board traces E N could induce error voltages sufficiently large enough to trigger E MAGgauss) 1 the thresholds of succeeding circuitry. Care should be taken in Lk the layout of such traces to avoid this possibility. ABY ( ALLOWDENSIT0.1 POWER CONSUMPTION M The supply current at a given channel of the ADuM3300/ U XIM 0.01 ADuM3301 isolator is a function of the supply voltage, the MA channel’s data rate, and the channel’s output load. For each input channel, the supply current is given by 0.0011k 10kMAGNETI1C0 0FkIELD FREQ1MUENCY (Hz1)0M 100M 05984-017 IDDI = IDDI (Q) f ≤ 0.5 fr Figure 16. Maximum Allowable External Magnetic Flux Density I = I × (2f − f) + I f > 0.5 f DDI DDI (D) r DDI (Q) r For example, at a magnetic field frequency of 1 MHz, the For each output channel, the supply current is given by maximum allowable magnetic field of 0.2 kgauss induces a I = I f ≤ 0.5 f voltage of 0.25 V at the receiving coil. This is about 50% of the DDO DDO (Q) r sensing threshold and does not cause a faulty output transition. IDDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q) Similarly, if such an event were to occur during a transmitted f > 0.5 fr pulse (and was of the worst-case polarity), it would reduce the where: received pulse from >1.0 V to 0.75 V—still well above the 0.5 V I , I are the input and output dynamic supply currents DDI (D) DDO (D) sensing threshold of the decoder. per channel (mA/Mbps). The preceding magnetic flux density values correspond to CL is the output load capacitance (pF). specific current magnitudes at given distances from the VDDO is the output supply voltage (V). ADuM3300/ADuM3301 transformers. Figure 17 expresses these f is the input logic signal frequency (MHz); it is half of the input allowable current magnitudes as a function of frequency for data rate expressed in units of Mbps. selected distances. The ADuM3300/ADuM3301 are extremely fr is the input stage refresh rate (Mbps). immune and can be affected only by extremely large currents IDDI (Q), IDDO (Q) are the specified input and output quiescent operated at high frequency very close to the component (see supply currents (mA). Figure 17). For the 1 MHz example noted, a 0.5 kA current To calculate the total I and I supply current, the supply DD1 DD2 would have to be placed 5 mm away from the ADuM3300/ currents for each input and output channel corresponding to ADuM3301 to affect the component’s operation. V and V are calculated and totaled. Figure 6 provides per- DD1 DD2 channel input supply current as a function of data rate. Figure 7 and Figure 8 provide per-channel output supply current as a function of data rate for an unloaded output condition and for a 15 pF output condition, respectively. Figure 9 through Figure 12 provide total V and V supply current as a function of data DD1 DD2 rate for ADuM3300/ADuM3301 channel configurations. Rev. E | Page 18 of 20

Data Sheet ADuM3300/ADuM3301 INSULATION LIFETIME In the case of unipolar ac or dc voltage, the stress on the insula- tion is significantly lower. This allows operation at higher working All insulation structures eventually break down when subjected voltages while still achieving a 50-year service life. The working to voltage stress over a sufficiently long period. The rate of voltages listed in Table 10 can be applied while maintaining the insulation degradation is dependent on the characteristics of the 50-year minimum lifetime, provided that the voltage conforms voltage waveform applied across the insulation. In addition to to either the unipolar ac or dc voltage cases. Any cross-insulation the testing performed by the regulatory agencies, Analog voltage waveform that does not conform to Figure 19 or Figure 20 Devices executes an extensive set of evaluations to determine should be treated as a bipolar ac waveform, and its peak voltage the lifetime of the insulation structure within the ADuM3300/ should be limited to the 50-year lifetime voltage value listed in ADuM3301. Table 10. Analog Devices performs accelerated life testing using voltage Note that the voltage presented in Figure 19 is shown as levels higher than the rated continuous working voltage. sinusoidal for illustration purposes only. It is meant to represent Acceleration factors for several operating conditions are any voltage waveform varying between 0 V and some limiting determined. These factors allow calculation of the time to value. The limiting value can be positive or negative, but the failure at the actual working voltage. voltage cannot cross 0 V. The values shown in Table 10 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum CSA/VDE approved working voltages. In many RATED PEAK VOLTAGE csearsveisc, et hlief ea pvporltoavgeed. Owpoerrkaintigo nv oaltt athgee sies hhiigghh ewr othrkainn g5 0v-oyletaagr es 0V 05984-020 can lead to shortened insulation life. Figure 18. Bipolar AC Waveform The insulation lifetime of the ADuM3300/ADuM3301 depends on the voltage waveform type imposed across the isolation RATED PEAK VOLTAGE braatrersi edre. pTehned iiCnog uopnl ewr hinesthuelart tiohne wstarvuecftourrme d ise gbriapdoelas ra at cd,i fferent 0V 05984-021 unipolar ac, or dc. Figure 18, Figure 19, and Figure 20 illustrate Figure 19. Unipolar AC Waveform these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition RATED PEAK VOLTAGE dweotrekrimngin veos ltthagee A. nalog Devices recommended maximum 0V 05984-022 Figure 20. DC Waveform Rev. E | Page 19 of 20

ADuM3300/ADuM3301 Data Sheet OUTLINE DIMENSIONS 10.50(0.4134) 10.10(0.3976) 16 9 7.60(0.2992) 7.40(0.2913) 1 8 10.65(0.4193) 10.00(0.3937) 1.27(0.0500) 0.75(0.0295) BSC 2.65(0.1043) 0.25(0.0098) 45° 0.30(0.0118) 2.35(0.0925) 8° 0.10(0.0039) 0° COPLANARITY 0.10 0.51(0.0201) SPELAATNIENG 0.33(0.0130) 1.27(0.0500) 0.31(0.0122) 0.20(0.0079) 0.40(0.0157) (RCINEOFNPEATRRREOENNLCLTEIHNCEOGOSNDMELISPYM)LAEAIANNRNDSETIAORTRNOOESUJNANEORDDETEEDAICN-POSMPFTRIFALONLMPIDMIRLAELIRATIMTDEEESRTFSMEO;SRIRN-0ECU1QH3SU-EADIVAIINMAELDENENSSTIIOGSNNFS.OR 03-27-2007-B Figure 21. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Number of Number of Maximum Maximum Maximum Temperature Inputs, Inputs, Data Rate Propagation Pulse Width Package Model1, 2 Range (°C) V Side V Side (Mbps) Delay, 5 V (ns) Distortion (ns) Option3 DD1 DD2 ADuM3300ARWZ −40 to +105 3 0 1 100 40 RW-16 ADuM3300ARWZ-RL −40 to +105 3 0 1 100 40 RW-16 ADuM3300BRWZ −40 to +105 3 0 10 50 3 RW-16 ADuM3300BRWZ-RL −40 to +105 3 0 10 50 3 RW-16 ADuM3300CRWZ −40 to +105 3 0 90 32 2 RW-16 ADuM3300CRWZ-RL −40 to +105 3 0 90 32 2 RW-16 ADuM3301ARWZ −40 to +105 2 1 1 100 40 RW-16 ADuM3301ARWZ-RL −40 to +105 2 1 1 100 40 RW-16 ADuM3301BRWZ −40 to +105 2 1 10 50 3 RW-16 ADuM3301BRWZ-RL −40 to +105 2 1 10 50 3 RW-16 ADuM3301CRWZ −40 to +105 2 1 90 32 2 RW-16 ADuM3301CRWZ-RL −40 to +105 2 1 90 32 2 RW-16 1 Z = RoHS Compliant Part. 2 Tape and reel are available. The addition of an “-RL” suffix designates a 13” (1,000 units) tape and reel option. 3 RW-16 = 16-lead wide body SOIC. ©2006–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05984-0-7/17(E) Rev. E | Page 20 of 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADUM3300CRWZ-RL ADUM3300BRWZ ADUM3300ARWZ ADUM3300BRWZ-RL ADUM3301ARWZ-RL ADUM3300CRWZ ADUM3301BRWZ ADUM3301ARWZ ADUM3301BRWZ-RL ADUM3301CRWZ ADUM3301CRWZ-RL ADUM3300ARWZ-RL ADUM3300WARWZ-RL ADUM3301WBRWZ-RL ADUM3300WARWZ ADUM3301WARWZ ADUM3301WBRWZ ADUM3300WBRWZ ADUM3300WBRWZ-RL ADUM3301WARWZ-RL