Quad-Channel Digital Isolators Data Sheet ADuM1410/ADuM1411/ADuM1412 FEATURES FUNCTIONAL BLOCK DIAGRAMS Low power operation VDD1 1 ADuM1410 16VDD2 5 V operation GND1 2 15 GND2 1.3 mA per channel maximum at 0 Mbps to 2 Mbps VIA 3 ENCODE DECODE 14 VOA 4.0 mA per channel maximum at 10 Mbps VIB 4 ENCODE DECODE 13 VOB 3 V operation VIC 5 ENCODE DECODE 12 VOC 0.8 mA per channel maximum at 0 Mbps to 2 Mbps 1.8 mA per channel maximum at 10 Mbps VID 6 ENCODE DECODE 11 VOD B3 iVd/i5re Vc tlieovneal lt craonmsmlatuinoinc ation DISAGBNLDE1 87 190 CGTNRDL22 06580-001 Figure 1. ADuM1410 High temperature operation: 105°C Up to 10 Mbps data rate (NRZ) VDD1 1 ADuM1411 16VDD2 Programmable default output state GND1 2 15 GND2 High common-mode transient immunity: >25 kV/µs VIA 3 ENCODE DECODE 14 VOA 16-lead, RoHS compliant, SOIC wide body package VIB 4 ENCODE DECODE 13 VOB Safety and regulatory approvals VIC 5 ENCODE DECODE 12 VOC UL recognition: 3750 V rms for 1 minute per UL 1577 VOD 6 DECODE ENCODE 11 VID CSA Component Acceptance Notice 5A VDDEI cNe Vrt VifiDcEa tVe 0o8f 8co4n-1f0o r(mVDitEy V 0884-10): 2006-12 CGTNRDL11 87 190 CGTNRDL22 06580-002 Figure 2. ADuM1411 V = 560 V peak IORM TÜV approval: IEC/EN 60950-1 VDD1 1 ADuM1412 16VDD2 APPLICATIONS GND1 2 15 GND2 VIA 3 ENCODE DECODE 14 VOA General-purpose multichannel isolation VIB 4 ENCODE DECODE 13 VOB SPI interface/data converter isolation RS-232/RS-422/RS-485 transceivers VOC 5 DECODE ENCODE 12 VIC Industrial field bus isolation VOD 6 DECODE ENCODE 11 VID CGTNRDL11 87 190 CGTNRDL22 06580-003 Figure 3. ADuM1412 GENERAL DESCRIPTION devices consume one-tenth to one-sixth the power of optocou- The ADuM1410/ADuM1411/ADuM14121 are four-channel plers at comparable signal data rates. digital isolators based on Analog Devices, Inc., iCoupler® The ADuM1410/ADuM1411/ADuM1412 isolators provide four technology. Combining high speed CMOS and monolithic air independent isolation channels in a variety of channel configu- core transformer technologies, these isolation components provide rations and data rates (see the Ordering Guide) up to 10 Mbps. outstanding performance characteristics superior to alternatives All models operate with the supply voltage on either side ranging such as optocoupler devices. from 2.7 V to 5.5 V, providing compatibility with lower voltage By avoiding the use of LEDs and photodiodes, iCoupler devices systems as well as enabling voltage translation functionality across remove the design difficulties commonly associated with opto- the isolation barrier. All products also have a default output couplers. The usual concerns that arise with optocouplers, such control pin. This allows the user to define the logic state the as uncertain current transfer ratios, nonlinear transfer functions, outputs are to adopt in the absence of the input power. Unlike and temperature and lifetime effects, are eliminated with the simple other optocoupler alternatives, the ADuM1410/ADuM1411/ iCoupler digital interfaces and stable performance characteristics. ADuM1412 isolators have a patented refresh feature that ensures The need for external drivers and other discrete components is dc correctness in the absence of input logic transitions and eliminated with these iCoupler products. Furthermore, iCoupler during power-up/power-down conditions. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Rev. M Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2005–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADuM1410/ADuM1411/ADuM1412 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Recommended Operating Conditions .................................... 11 Applications ....................................................................................... 1 Absolute Maximum Ratings ......................................................... 12 Functional Block Diagrams ............................................................. 1 ESD Caution................................................................................ 12 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ......................... 13 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 17 Specifications ..................................................................................... 3 Applications Information .............................................................. 19 Electrical Characteristics—5 V Operation................................ 3 PC Board Layout ........................................................................ 19 Electrical Characteristics—3 V Operation................................ 5 Propagation Delay-Related Parameters ................................... 19 Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V DC Correctness and Magnetic Field Immunity ........................... 19 Operation ....................................................................................... 7 Power Consumption .................................................................. 20 Package Characteristics ............................................................. 10 Insulation Lifetime ..................................................................... 20 Regulatory Information ............................................................. 10 Outline Dimensions ....................................................................... 22 Insulation and Safety-Related Specifications .......................... 10 Ordering Guide .......................................................................... 22 DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 Insulation Characteristics .......................................................... 11 REVISION HISTORY 8/15—Rev. L to Rev. M Changes to Features and Applications ............................................ 1 Changes to Table 5 and Table 6 ..................................................... 10 Changes to DC Specifications in Table 1 ........................................ 3 Changes to DC Specifications in Table 2 ........................................ 5 7/15—Rev. K to Rev. L Changes to DC Specifications in Table 3 ........................................ 7 Changes to Table 5 and Table 6 ..................................................... 10 Changes to Regulatory Information Section .............................. 10 Added Table 10 ............................................................................... 12 4/15—Rev. J to Rev. K Added Insulation Lifetime Section .............................................. 21 Changed ADuM141x to ADuM1410/ADuM1411/ ADuM1412 ..................................................................... Throughout 2/07—Rev. E to Rev. F Change to Features Section ............................................................. 1 Added ADuM1410ARWZ ................................................ Universal Changes to Table 5 and Table 6 ..................................................... 10 Updated Pin Name CTRL to CTRL Throughout ........................ 1 2 Changes to Ordering Guide .......................................................... 21 4/14—Rev. I to Rev. J Change to Table 5 ........................................................................... 10 10/06—Rev. D to Rev. E Added ADuM1411 and ADuM1412 ............................... Universal 3/12—Rev. H to Rev. I Deleted ADuM1310 ........................................................... Universal Created Hyperlink for Safety and Regulatory Approvals Changes to Features .......................................................................... 1 Entry in Features Section ................................................................. 1 Changes to Specifications Section ................................................... 3 Change to PC Board Layout Section ............................................ 19 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 20 11/10—Rev. G to Rev. H Added TÜV Approval to Features Section .................................... 1 3/06—Rev. C to Rev. D Added TÜV Column, Table 5 ....................................................... 10 Added Note 1 and Changes to Figure 2 .......................................... 1 Changes to Absolute Maximum Ratings ..................................... 11 6/07—Rev. F to Rev. G Updated VDE Certification Throughout ...................................... 1 11/05—Revision C: Initial Version Rev. M | Page 2 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION 4.5 V ≤ V ≤ 5.5 V, 4.5 V ≤ V ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, DD1 DD2 unless otherwise noted; all typical specifications are at T = 25°C, V = V = 5 V. All voltages are relative to their respective ground. A DD1 DD2 Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Input Supply Current per Channel, I 0.50 0.73 mA DDI (Q) Quiescent Output Supply Current per Channel, I 0.38 0.53 mA DDO (Q) Quiescent ADuM1410, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I 2.4 3.2 mA DC to 1 MHz logic signal frequency DD1 DD1 (Q) V Supply Current I 1.2 1.6 mA DC to 1 MHz logic signal frequency DD2 DD2 (Q) 10 Mbps (BRWZ Version Only) V Supply Current I 8.8 12 mA 5 MHz logic signal frequency DD1 DD1 (10) V Supply Current I 2.8 4.0 mA 5 MHz logic signal frequency DD2 DD2 (10) ADuM1411, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I 2.2 2.8 mA DC to 1 MHz logic signal frequency DD1 DD1 (Q) V Supply Current I 1.8 2.4 mA DC to 1 MHz logic signal frequency DD2 DD2 (Q) 10 Mbps (BRWZ Version Only) V Supply Current I 5.4 7.6 mA 5 MHz logic signal frequency DD1 DD1 (10) V Supply Current I 3.8 5.3 mA 5 MHz logic signal frequency DD2 DD2 (10) ADuM1412, Total Supply Current, Four Channels1 DC to 2 Mbps V or V Supply Current I , I 2.0 2.6 mA DC to 1 MHz logic signal frequency DD1 DD2 DD1 (Q) DD2 (Q) 10 Mbps (BRWZ Version Only) V or V Supply Current I , I 4.6 6.5 mA 5 MHz logic signal frequency DD1 DD2 DD1 (10) DD2 (10) All Models Input Currents I , I , I , −10 +0.01 +10 µA 0 V ≤ V , V , V , V ≤ V or V , IA IB IC IA IB IC ID DD1 DD2 I , I , 0 V ≤ V , V ≤ V or V , ID CTRL1 CTRL1 CTRL2 DD1 DD2 I , I 0 V ≤ V ≤ V CTRL2 DISABLE DISABLE DD1 Logic High Input Threshold V 2.0 V IH Logic Low Input Threshold V 0.8 V IL Logic High Output Voltages V , V , (V or V ) − 0.1 5.0 V I = −20 µA, V = V OAH OBH DD1 DD2 Ox Ix IxH VOCH, VODH (VDD1 or VDD2) − 0.4 4.8 V IOx = −4 mA, VIx = VIxH Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL Rev. M | Page 3 of 22

ADuM1410/ADuM1411/ADuM1412 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS ADuM1410ARWZ/ADuM1411ARWZ/ ADuM1412ARWZ Minimum Pulse Width2 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 20 65 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 40 ns C = 15 pF, CMOS signal levels PLH PHL L Propagation Delay Skew5 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching6 t 50 ns C = 15 pF, CMOS signal levels PSKCD/OD L ADuM1410BRWZ/ADuM1411BRWZ/ ADuM1412BRWZ Minimum Pulse Width2 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 20 30 50 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 5 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 30 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 5 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 6 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 All Models Output Rise/Fall Time (10% to 90%) t/t 2.5 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity |CM | 25 35 kV/µs V = V or V , V = 1000 V, H Ix DD1 DD2 CM at Logic High Output7 transient magnitude = 800 V Common-Mode Transient Immunity |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM at Logic Low Output7 transient magnitude = 800 V Refresh Rate f 1.2 Mbps r Input Enable Time8 t 2.0 µs V , V , V , V = 0 V or V ENABLE IA IB IC ID DD1 Input Disable Time8 t 5.0 µs V , V , V , V = 0 V or V DISABLE IA IB IC ID DD1 Input Dynamic Supply Current I 0.12 mA/ DDI (D) per Channel9 Mbps Output Dynamic Supply Current I 0.04 mA/ DDO (D) per Channel9 Mbps 1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. |CML| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14). 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. M | Page 4 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412 ELECTRICAL CHARACTERISTICS—3 V OPERATION 2.7 V ≤ V ≤ 3.6 V, 2.7 V ≤ V ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, DD1 DD2 unless otherwise noted; all typical specifications are at T = 25°C, V = V = 3.0 V. All voltages are relative to their respective ground. A DD1 DD2 Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Input Supply Current per Channel, I 0.25 0.38 mA DDI (Q) Quiescent Output Supply Current per Channel, I 0.19 0.33 mA DDO (Q) Quiescent ADuM1410, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I 1.2 1.6 mA DC to 1 MHz logic signal DD1 DD1 (Q) frequency V Supply Current I 0.8 1.0 mA DC to 1 MHz logic signal DD2 DD2 (Q) frequency 10 Mbps (BRWZ Version Only) V Supply Current I 4.5 6.5 mA 5 MHz logic signal frequency DD1 DD1 (10) V Supply Current I 1.4 1.8 mA 5 MHz logic signal frequency DD2 DD2 (10) ADuM1411, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I 1.0 1.9 mA DC to 1 MHz logic signal frequency DD1 DD1 (Q) V Supply Current I 0.9 1.7 mA DC to 1 MHz logic signal frequency DD2 DD2 (Q) 10 Mbps (BRWZ Version Only) V Supply Current I 3.1 4.5 mA 5 MHz logic signal frequency DD1 DD1 (10) V Supply Current I 2.1 3.0 mA 5 MHz logic signal frequency DD2 DD2 (10) ADuM1412, Total Supply Current, Four Channels1 DC to 2 Mbps V or V Supply Current I , I 1.0 1.8 mA DC to 1 MHz logic signal frequency DD1 DD2 DD1 (Q) DD2 (Q) 10 Mbps (BRWZ Version Only) V or V Supply Current I , I 2.6 3.8 mA 5 MHz logic signal frequency DD1 DD2 DD1 (10) DD2 (10) All Models Input Currents I , I , I , I , −10 +0.01 +10 µA 0 V ≤ V , V , V , V ≤ V or V , IA IB IC ID IA IB IC ID DD1 DD2 I ,I , I 0 V ≤ V , V ≤ V or V , CTRL1 CTRL2 DISABLE CTRL1 CTRL2 DD1 DD2 0 V ≤ V ≤ V DISABLE DD1 Logic High Input Threshold V 1.6 V IH Logic Low Input Threshold V 0.4 V IL Logic High Output Voltages V , V , (V or V ) − 0.1 3.0 V I = −20 µA, V = V OAH OBH DD1 DD2 Ox Ix IxH VOCH, VODH (VDD1 or VDD2) − 0.4 2.8 V IOx = −4 mA, VIx = VIxH Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL Rev. M | Page 5 of 22

ADuM1410/ADuM1411/ADuM1412 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS ADuM1410ARWZ/ADuM1411ARWZ/ ADuM1412ARWZ Minimum Pulse Width2 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 20 75 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 40 ns C = 15 pF, CMOS signal levels PLH PHL L Propagation Delay Skew5 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching6 t 50 ns C = 15 pF, CMOS signal levels PSKCD/OD L ADuM1410BRWZ/ADuM1411BRWZ/ ADuM1412BRWZ Minimum Pulse Width2 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 20 40 60 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 5 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 30 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 5 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 6 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 All Models Output Rise/Fall Time (10% to 90%) t/t 2.5 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity |CM | 25 35 kV/µs V = V or V , V = 1000 V, H Ix DD1 DD2 CM at Logic High Output7 transient magnitude = 800 V Common-Mode Transient Immunity |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM at Logic Low Output7 transient magnitude = 800 V Refresh Rate f 1.1 Mbps r Input Enable Time8 t 2.0 µs V , V , V , V = 0 V or V ENABLE IA IB IC ID DD1 Input Disable Time8 t 5.0 µs V , V , V , V = 0 V or V DISABLE IA IB IC ID DD1 Input Dynamic Supply Current I 0.07 mA/ DDI (D) per Channel9 Mbps Output Dynamic Supply Current I 0.02 mA/ DDO (D) per Channel9 Mbps 1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. |CML| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14). 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. M | Page 6 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION 5 V/3 V operation: 4.5 V ≤ V ≤ 5.5 V, 2.7 V ≤ V ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ V ≤ 3.6 V, 4.5 V ≤ V ≤ 5.5 V; all DD1 DD2 DD1 DD2 minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at T = 25°C; V = 3.0 V, V = 5 V; or V = 5 V, V = 3.0 V. All voltages are relative to their respective ground. A DD1 DD2 DD1 DD2 Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I DDI (Q) 5 V/3 V Operation 0.50 0.73 mA 3 V/5 V Operation 0.25 0.38 mA Output Supply Current per Channel, Quiescent I DDO (Q) 5 V/3 V Operation 0.19 0.33 mA 3 V/5 V Operation 0.38 0.53 mA ADuM1410, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I DD1 DD1 (Q) 5 V/3 V Operation DC to 1 MHz logic signal 2.4 3.2 mA frequency 3 V/5 V Operation DC to 1 MHz logic signal 1.2 1.6 mA frequency V Supply Current I DD2 DD2 (Q) 5 V/3 V Operation DC to 1 MHz logic signal 0.8 1.0 mA frequency 3 V/5 V Operation DC to 1 MHz logic signal 1.2 1.6 mA frequency 10 Mbps (BRWZ Version Only) V Supply Current I DD1 DD1 (10) 5 V/3 V Operation 8.6 11 mA 5 MHz logic signal frequency 3 V/5 V Operation 3.4 6.5 mA 5 MHz logic signal frequency V Supply Current I DD2 DD2 (10) 5 V/3 V Operation 1.4 1.8 mA 5 MHz logic signal frequency 3 V/5 V Operation 2.6 3.0 mA 5 MHz logic signal frequency ADuM1411, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I DD1 DD1 (Q) 5 V/3 V Operation DC to 1 MHz logic signal 2.2 2.8 mA frequency 3 V/5 V Operation DC to 1 MHz logic signal 1.0 1.9 mA frequency V Supply Current I DD2 DD2 (Q) 5 V/3 V Operation DC to 1 MHz logic signal 0.9 1.7 mA frequency 3 V/5 V Operation DC to 1 MHz logic signal 1.7 2.4 mA frequency 10 Mbps (BRWZ Version Only) V Supply Current I DD1 DD1 (10) 5 V/3 V Operation 5.4 7.6 mA 5 MHz logic signal frequency 3 V/5 V Operation 3.1 4.5 mA 5 MHz logic signal frequency V Supply Current I DD2 DD2 (10) 5 V/3 V Operation 2.1 3.0 mA 5 MHz logic signal frequency 3 V/5 V Operation 3.8 5.3 mA 5 MHz logic signal frequency Rev. M | Page 7 of 22

ADuM1410/ADuM1411/ADuM1412 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments ADuM1412, Total Supply Current, Four Channels1 DC to 2 Mbps V Supply Current I DD1 DD1 (Q) 5 V/3 V Operation DC to 1 MHz logic signal 2.0 2.6 mA frequency 3 V/5 V Operation DC to 1 MHz logic signal 1.0 1.8 mA frequency V Supply Current I DD2 DD2 (Q) 5 V/3 V Operation DC to 1 MHz logic signal 1.0 1.8 mA frequency 3 V/5 V Operation DC to 1 MHz logic signal 2.0 2.6 mA frequency 10 Mbps (BRWZ Version Only) V Supply Current I DD1 DD1 (10) 5 V/3 V Operation 4.6 6.5 mA 5 MHz logic signal frequency 3 V/5 V Operation 2.6 3.8 mA 5 MHz logic signal frequency V Supply Current I DD2 DD2 (10) 5 V/3 V Operation 2.6 3.8 mA 5 MHz logic signal frequency 3 V/5 V Operation 4.6 6.5 mA 5 MHz logic signal frequency All Models Input Currents I , I , I , 0 V ≤ V , V , V , V ≤ V or V , IA IB IC IA IB IC ID DD1 DD2 I ,I , I , 0 V ≤ V , V ≤ V or V , ID CTRL1 CTRL2 CTRL1 CTRL2 DD1 DD2 I −10 +0.01 +10 μA 0 V ≤ V ≤ V DISABLE DISABLE DD1 Logic High Input Threshold V IH 5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V Logic Low Input Threshold V IL 5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V Logic High Output Voltages (V or (V or DD1 DD1 V ) − 0.1 V V I = −20 μA, V = V DD2 DD2) Ox Ix IxH V , V , (V or (V or OAH OBH DD1 DD1 V , V V ) − 0.4 V ) − 0.2 V I = −4 mA, V = V OCH ODH DD2 DD2 Ox Ix IxH Logic Low Output Voltages 0.0 0.1 V I = 20 μA, V = V Ox Ix IxL VOAL, VOBL, 0.04 0.1 V IOx = 400 μA, VIx = VIxL V , V 0.2 0.4 V I = 4 mA, V = V OCL ODL Ox Ix IxL SWITCHING SPECIFICATIONS ADuM1410ARWZ/ADuM1411ARWZ/ ADuM1412ARWZ Minimum Pulse Width2 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 25 70 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 40 ns C = 15 pF, CMOS signal levels PLH PHL L Propagation Delay Skew5 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching6 t 50 ns C = 15 pF, CMOS signal levels PSKCD/OD L Rev. M | Page 8 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412 Parameter Symbol Min Typ Max Unit Test Conditions/Comments ADuM1410BRWZ/ADuM1411BRWZ/ ADuM1412BRWZ Minimum Pulse Width2 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 25 35 60 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 5 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 30 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, Codirectional Channels6 t 5 ns C = 15 pF, CMOS signal levels PSKCD L Channel-to-Channel Matching, Opposing-Directional Channels6 t 6 ns C = 15 pF, CMOS signal levels PSKOD L All Models Output Rise/Fall Time (10% to 90%) t/t C = 15 pF, CMOS signal levels R F L 5 V/3 V Operation 2.5 ns 3 V/5 V Operation 2.5 ns Common-Mode Transient Immunity at V = V or V , V = 1000 V, Ix DD1 DD2 CM Logic High Output7 |CM | 25 35 kV/µs transient magnitude = 800 V H Common-Mode Transient Immunity at V = 0 V, V = 1000 V, transient Ix CM Logic Low Output7 |CM| 25 35 kV/µs magnitude = 800 V L Refresh Rate f r 5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps Input Enable Time8 t 2.0 µs V , V , V , V = 0 V or V ENABLE IA IB IC ID DD1 Input Disable Time8 t 5.0 µs V , V , V , V = 0 V or V DISABLE IA IB IC ID DD1 Input Dynamic Supply Current per Channel9 I DDI (D) 5 V Operation mA/ 0.12 Mbps 3 V Operation mA/ 0.07 Mbps Output Dynamic Supply Current per Channel9 I DDO (D) 5 V Operation mA/ 0.04 Mbps 3 V Operation mA/ 0.02 Mbps 1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. |CML| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14). 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. M | Page 9 of 22

ADuM1410/ADuM1411/ADuM1412 Data Sheet PACKAGE CHARACTERISTICS Table 4. Parameter Symbol Min Typ Max Unit Test Conditions/Comments Resistance (Input to Output)1 R 1012 Ω I-O Capacitance (Input to Output)1 C 2.2 pF f = 1 MHz I-O Input Capacitance2 C 4.0 pF I IC Junction to Case Thermal Resistance Side 1 θ 33 °C/W Thermocouple located at center of package underside JCI Side 2 θ 28 °C/W JCO 1 The device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. 2 Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM1410/ADuM1411/ADuM1412 have been approved by the organizations listed in Table 5. See Table 10 and the Insulation Lifetime section for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 5. UL CSA CQC VDE TÜV Recognized Under Approved under CSA Approved under Certified according to Approved according to 1577 Component Component Acceptance CQC11-471543-2012 DIN V VDE V 0884-10 IEC 60950-1:2005 and Recognition Notice 5A (VDE V 0884-10): 2006-122 EN 60950-1:2006 Program1 Single Protection, Basic insulation per Basic insulation per Reinforced insulation, 3000 V rms reinforced isolation 3750 V rms CSA 60950-1-03 and GB4943.1-2011, 600 V rms 560 V peak at a 400 V rms working voltage, Isolation IEC 60950-1, 800 V rms (848 V peak) maximum 3000 V rms basic isolation at a Voltage (1131 V peak) maximum working voltage, tropical 600 V rms working voltage working voltage climate, altitude ≤ 5000 m Reinforced insulation Reinforced insulation per per CSA 60950-1-03 and GB4943.1-2011, 380 V rms IEC 60950-1, 400 V rms (537 V peak) maximum (566 V peak) maximum working voltage, tropical working voltage climate, altitude ≤ 5000 m File E214100 File 205078 File CQC14001108689 File 2471900-4880-0001 Certificate B 10 03 56232 006 1 In accordance with UL 1577, each ADuM1410/ADuM1411/ADuM1412 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA). 2 In accordance with DIN V VDE V 0884-10, each ADuM1410/ADuM1411/ADuM1412 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY RELATED SPECIFICATIONS Table 6. Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 3750 V rms 1-minute duration Minimum External Tracking (Creepage) L(I02) 7.71 mm min Measured from input terminals to output terminals, shortest distance path along package body Minimum External Air Gap (Clearance) L(I01) 7.7 mm min Measured from input terminals to output terminals, shortest distance through air Minimum Clearance in the Plane of the L(PCB) 8.12 mm min Measured from input terminals to output terminals, shortest Printed Circuit Board (PCB Clearance) distance through air, line of sight, in the PCB mounting plane Minimum Internal Gap (Internal Clearance) 0.017 mm min Insulation distance through insulation Tracking Resistance (Comparative Tracking CTI >400 V DIN IEC 112/VDE 0303 Part 1 Index) Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1) 1 Clearance and creepage measured by VDE is >8 mm for SOIC wide packages. 2 This value is for information only, to aid in PCB design. Package clearance is identical to creepage as specified in L(I02). Rev. M | Page 10 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412 DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation within the safety limit data only. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval. Table 7. Description Conditions Symbol Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V 560 V peak IORM Input-to-Output Test Voltage, Method B1 V × 1.875 = V , 100% production test, t = 1 sec, V 1050 V peak IORM PR m PR partial discharge < 5 pC Input-to-Output Test Voltage, Method A V × 1.6 = V , t = 60 sec, partial discharge < 5 pC V IORM PR m PR After Environmental Tests Subgroup 1 896 V peak After Input and/or Safety Test Subgroup 2 V × 1.2 = V , t = 60 sec, partial discharge < 5 pC 672 V peak IORM PR m and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, t = 10 seconds V 4000 V peak TR TR Safety Limiting Values Maximum value allowed in the event of a failure; see Figure 4 Case Temperature T 150 °C S Side 1 Current I 265 mA S1 Side 2 Current I 335 mA S2 Insulation Resistance at T V = 500 V R >109 Ω S IO S RECOMMENDED OPERATING CONDITIONS 350 Table 8. 300 Parameter Symbol Min Max Unit A) m T ( 250 Operating Temperature TA −40 +105 °C REN SIDE #2 Supply Voltages1 VDD1, VDD2 2.7 5.5 V UR 200 Input Signal Rise and Fall Times 1.0 ms C G TIN 150 1 All voltages are relative to their respective ground. See the DC Correctness MI SIDE #1 and Magnetic Field Immunity section for information on immunity to external Y-LI 100 magnetic fields. T E F A S 50 00 50CASE TEMP1E0R0ATURE (°C)150 200 06580-007 Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. M | Page 11 of 22

ADuM1410/ADuM1411/ADuM1412 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum A Ratings may cause permanent damage to the product. This is a Table 9. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational Storage Temperature (T ) Range −65°C to +150°C ST section of this specification is not implied. Operation beyond Ambient Operating Temperature −40°C to +105°C (T ) Range the maximum operating conditions for extended periods may A Supply Voltages (V , V )1 −0.5 V to +7.0 V affect product reliability. DD1 DD2 Input Voltages (V , V , V , V , V , −0.5 V to V + 0.5 V IA IB IC ID CTRL1 DDI ESD CAUTION V , V )1, 2 CTRL2 DISABLE Output Voltages (V , V , V , V )1, 2 −0.5 V to V + 0.5 V OA OB OC OD DDO Average Output Current per Pin3 Side 1 (I ) −18 mA to +18 mA O1 Side 2 (I ) −22 mA to +22 mA O2 Common-Mode Transients4 −100 kV/μs to +100 kV/μs 1 All voltages are relative to their respective ground. 2 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section. 3 See Figure 4 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Common- mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. Table 10. Maximum Continuous Working Voltage1 Parameter Max Unit Constraint AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime AC Voltage, Unipolar Waveform Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 DC Voltage Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Rev. M | Page 12 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1 1 16 VDD2 GND1* 2 15 GND2* VIA 3 ADuM1410 14 VOA VIB 4 TOP VIEW 13 VOB VIC 5 (Not to Scale) 12 VOC VID 6 11 VOD DISABLE 7 10 CTRL2 GND1* 8 9 GND2* *PTCIOON N G2N NAEDNC1DT I ESPD IRN. E C8CO AONRMNEME IECNNTTIDENERGDN B.A POLILTNYH 9 C TAOON NDGN NPEDICN2T 1IES5D RA. ERCCEOO NINMNTMEECERNTNIDNAEGLDL B.YOTH 06580-004 Figure 5. ADuM1410 Pin Configuration Table 11. ADuM1410 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V). DD1 2 GND Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND is 1 1 recommended. 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Input C. IC 6 V Logic Input D. ID 7 DISABLE Input Disable. Disables the isolator inputs and halts the dc refresh circuits. Outputs take on the logic state determined by CTRL. 2 8 GND Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND is 1 1 recommended. 9 GND Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND is 2 2 recommended. 10 CTRL Default Output Control. Controls the logic state the outputs assume when the input power is off. V , V , V , and 2 OA OB OC V outputs are high when CTRL is high or disconnected and V is off. V , V , V , and V outputs are low when OD 2 DD1 OA OB OC OD CTRL is low and V is off. When V power is on, this pin has no effect. 2 DD1 DD1 11 V Logic Output D. OD 12 V Logic Output C. OC 13 V Logic Output B. OB 14 V Logic Output A. OA 15 GND Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND is 2 2 recommended. 16 V Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V). DD2 Rev. M | Page 13 of 22

ADuM1410/ADuM1411/ADuM1412 Data Sheet VDD1 1 16 VDD2 GND1* 2 15 GND2* VIA 3 ADuM1411 14 VOA VIB 4 TOP VIEW 13 VOB VIC 5 (Not to Scale) 12 VOC VOD 6 11 VID CTRL1 7 10 CTRL2 GND1* 8 9 GND2* *PTCIOON N G2N NAEDNC1DT I ESPD IRN. E C8CO AONRMNEME IECNNTTIDENERGDN B.A POLILTNYH 9 C TAOON NDGN NPEDICN2T 1IES5D RA. ERCCEOO NINMNTMEECERNTNIDNAEGLDL B.YOTH 06580-005 Figure 6. ADuM1411 Pin Configuration Table 12. ADuM1411 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V). DD1 2 GND Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND is 1 1 recommended. 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Input C. IC 6 V Logic Output D. OD 7 CTRL Default Output Control. Controls the logic state the outputs assume when the input power is off. V output is high 1 OD when CTRL is high or disconnected and V is off. V output is low when CTRL is low and V is off. When V 1 DD2 OD 1 DD2 DD2 power is on, this pin has no effect. 8 GND Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND is 1 1 recommended. 9 GND Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND is 2 2 recommended. 10 CTRL Default Output Control. Controls the logic state the outputs assume when the input power is off. V , V , and V 2 OA OB OC outputs are high when CTRL is high or disconnected and V is off. V , V , and V outputs are low when CTRL is 2 DD1 OA OB OC 2 low and V is off. When V power is on, this pin has no effect. DD1 DD1 11 V Logic Input D. ID 12 V Logic Output C. OC 13 V Logic Output B. OB 14 V Logic Output A. OA 15 GND Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND is 2 2 recommended. 16 V Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V). DD2 Rev. M | Page 14 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412 VDD1 1 16 VDD2 GND1* 2 15 GND2* VIA 3 ADuM1412 14 VOA VIB 4 TOP VIEW 13 VOB VOC 5 (Not to Scale) 12 VIC VOD 6 11 VID CTRL1 7 10 CTRL2 GND1* 8 9 GND2* *PTCIOON N G2N NAEDNC1DT I ESPD IRN. E C8CO AONRMNEME IECNNTTIDENERGDN B.A POLILTNYH 9 C TAOON NDGN NPEDICN2T 1IES5D RA. ERCCEOO NINMNTMEECERNTNIDNAEGLDL B.YOTH 06580-006 Figure 7. ADuM1412 Pin Configuration Table 13. ADuM1412 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V). DD1 2 GND Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND is 1 1 recommended. 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Output C. OC 6 V Logic Output D. OD 7 CTRL Default Output Control. Controls the logic state the outputs assume when the input power is off. V and V 1 OC OD outputs are high when CTRL is high or disconnected and V is off. V and V outputs are low when CTRL is low 1 DD2 OC OD 1 and V is off. When V power is on, this pin has no effect. DD2 DD2 8 GND Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND is 1 1 recommended. 9 GND Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND is 2 2 recommended. 10 CTRL Default Output Control. Controls the logic state the outputs assume when the input power is off. V and V 2 OA OB outputs are high when CTRL is high or disconnected and V is off. V and V outputs are low when CTRL is low 2 DD1 OA OB 2 and V is off. When V power is on, this pin has no effect. DD1 DD1 11 V Logic Input D. ID 12 V Logic Input C. IC 13 V Logic Output B. OB 14 V Logic Output A. OA 15 GND Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND is 2 2 recommended. 16 V Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V). DD2 Rev. M | Page 15 of 22

ADuM1410/ADuM1411/ADuM1412 Data Sheet Table 14. Truth Table (Positive Logic) V CTRL V V V V Ix X DISABLE DDI DDO Ox Input1 Input2 State3 State4 State5 Output1 Description H X L or Powered Powered H Normal operation, data is high. NC L X L or Powered Powered L Normal operation, data is low. NC X H or H X Powered H Inputs disabled. Outputs are in the default state as determined NC by CTRL . X X L H X Powered L Inputs disabled. Outputs are in the default state as determined by CTRL . X X H or X Unpowered Powered H Input unpowered. Outputs are in the default state as determined NC by CTRL . X Outputs return to input state within 1 µs of V power restoration. DDI See the pin function descriptions (Table 11, Table 12, and Table 13) for more details. X L X Unpowered Powered L Input unpowered. Outputs are in the default state as determined by CTRL . X Outputs return to input state within 1 µs of V power restoration. DDI See the pin function descriptions (Table 11, Table 12, and Table 13) for more details. X X X Powered Unpowered Z Output unpowered. Output pins are in high impedance state. Outputs return to input state within 1 µs of V power restoration. DDO See the pin function descriptions (Table 11, Table 12, and Table 13) for more details. 1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). 2 CTRLX refers to the default output control signal on the input side of a given channel (A, B, C, or D). 3 Available only on the ADuM1410. 4 VDDI refers to the power supply on the input side of a given channel (A, B, C, or D). 5 VDDO refers to the power supply on the output side of a given channel (A, B, C, or D). Rev. M | Page 16 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 10 8 1.5 A) m NEL ( mA) 6 T/CHAN 1.0 5V RRENT ( 4 5V N U RE 3V C R U 0.5 C 2 3V 00 2 DAT4A RATE (Mb6ps) 8 10 06580-008 00 2 DAT4A RATE (Mb6ps) 8 10 06580-011 Figure 8. Typical Supply Current per Input Channel vs. Data Rate Figure 11. Typical ADuM1410 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation for 5 V and 3 V Operation 1.0 10 0.9 0.8 8 A) 0.7 m NEL ( 0.6 5V mA) 6 T/CHAN 00..54 RRENT ( 4 N U RRE 0.3 C CU 3V 5V 0.2 2 0.1 3V 00 2 DAT4A RATE (Mb6ps) 8 10 06580-009 00 2 DAT4A RATE (Mb6ps) 8 10 06580-012 Figure 9. Typical Supply Current per Output Channel vs. Data Rate Figure 12. Typical ADuM1410 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation (No Output Load) for 5 V and 3 V Operation 1.4 10 1.2 8 A) 1.0 m NEL ( 0.8 mA) 6 T/CHAN 0.6 5V RRENT ( 4 N U RE C R 0.4 5V U C 3V 2 0.2 3V 00 2 DAT4A RATE (Mb6ps) 8 10 06580-010 00 2 DAT4A RATE (Mb6ps) 8 10 06580-013 Figure 10. Typical Supply Current per Output Channel vs. Data Rate Figure 13. Typical ADuM1411 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load) for 5 V and 3 V Operation Rev. M | Page 17 of 22

ADuM1410/ADuM1411/ADuM1412 Data Sheet 10 10 8 8 A) 6 A) 6 m m T ( T ( N N E E R R R 4 R 4 U U C C 5V 5V 2 2 3V 3V 00 2 DAT4A RATE (Mb6ps) 8 10 06580-014 00 2 DAT4A RATE (Mb6ps) 8 10 06580-015 Figure 14. Typical ADuM1411 VDD2 Supply Current vs. Data Rate Figure 15. Typical ADuM1412 VDD1 or VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation for 5 V and 3 V Operation Rev. M | Page 18 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412 APPLICATIONS INFORMATION PC BOARD LAYOUT DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY The ADuM1410/ADuM1411/ADuM1412 digital isolators Positive and negative logic transitions at the isolator input require no external interface circuitry for the logic interfaces. cause narrow (~1 ns) pulses to be sent to the decoder using the Power supply bypassing is strongly recommended at the input transformer. The decoder is bistable and is, therefore, either set and output supply pins (see Figure 16). Bypass capacitors are or reset by the pulses, indicating input logic transitions. In the most conveniently connected between Pin 1 and Pin 2 for V , absence of logic transitions at the input for more than ~1 µs, a DD1 and between Pin 15 and Pin 16 for V . The capacitor value periodic set of refresh pulses indicative of the correct input state DD2 should be between 0.01 µF and 0.1 µF. The total lead length is sent to ensure dc correctness at the output. If the decoder between both ends of the capacitor and the input power supply receives no internal pulses of more than approximately 5 µs, the pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 input side is assumed to be unpowered or nonfunctional, in and between Pin 9 and Pin 16 should also be considered unless which case the isolator output is forced to a default state (see both ground pins on each package are connected together close to Table 14) by the watchdog timer circuit. the package. The magnetic field immunity of the ADuM1410/ADuM1411/ VDD1 VDD2 ADuM1412 is determined by the changing magnetic field, which GND1 GND2 VIA VOA induces a voltage in the transformer’s receiving coil large enough VIB ADuM1410 VOB to either falsely set or reset the decoder. The following analysis VIC VOC DISAGBNVLDIED1 VCGOTNRDDL22 06580-016 doispe efeixrnaaetmisn itgnh ecedo cn bodneictdiaoiutniso eon fis tt hureen pdAreeDrs uewnMhtsi1c t4hh1 et0h /miAso Dcsatun sM uos1cc4ce1up1rt./i ATblhDee um 3Mo Vd1 e4 1o2f Figure 16. Recommended Printed Circuit Board Layout operation. In applications involving high common-mode transients, it is The pulses at the transformer output have an amplitude greater important to minimize board coupling across the isolation barrier. than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus Furthermore, users should design the board layout so that any establishing a 0.5 V margin in which induced voltages can be coupling that does occur equally affects all pins on a given tolerated. The voltage induced across the receiving coil is given by component side. Failure to ensure this can cause voltage V = (−dβ/dt) ∑ π r2; n = 1, 2, … , N differentials between pins exceeding the absolute maximum n ratings of the device, thereby leading to latch-up or permanent where: damage. See the AN-1109 Application Note for board layout β is magnetic flux density (gauss). guidelines. r is the radius of the nth turn in the receiving coil (cm). n PROPAGATION DELAY-RELATED PARAMETERS N is the number of turns in the receiving coil. Propagation delay is a parameter that describes the time it takes Given the geometry of the receiving coil in the ADuM1410/ a logic signal to propagate through a component. The input-to- ADuM1411/ADuM1412 and an imposed requirement that the output propagation delay time for a high-to-low transition may induced voltage be, at most, 50% of the 0.5 V margin at the differ from the propagation delay time of a low-to-high transition. decoder, a maximum allowable magnetic field at a given frequency can be calculated. The result is shown in Figure 18. INPUT (VIx) 50% 100 tPLH tPHL X U OUTPUT (VOx) 50% 06580-017 ETIC FL 10 Figure 17. Propagation Delay Parameters N AGss) Pulse width distortion is the maximum difference between these E Mgau 1 Lk two propagation delay values and an indication of how accurately ABY ( tChhea tnimneiln-gto o-fc hthaen ninepl umt asticghnianlg i sr epfreersse trov ethd.e maximum amount M ALLOWDENSIT0.1 U the propagation delay differs between channels within a single XIM 0.01 ADuM1410/ADuM1411/ADuM1412 component. A M Propagation delay skew refers to the maximum amount the pArDopuaMg1at4i1o1n/ AdDelauyM d1i4ff1e2r sc obmetpwoeneenn mts uolptieprlaet iAngD uunMde1r4 t1h0e/ same 0.0011k 10kMAGNETI1C0 0FkIELD FREQ1MUENCY (Hz1)0M 100M 06580-018 Figure 18. Maximum Allowable External Magnetic Flux Density conditions. Rev. M | Page 19 of 22

ADuM1410/ADuM1411/ADuM1412 Data Sheet For example, at a magnetic field frequency of 1 MHz, the POWER CONSUMPTION maximum allowable magnetic field of 0.2 kgauss induces a The supply current at a given channel of the ADuM1410/ voltage of 0.25 V at the receiving coil. This is about 50% of the ADuM1411/ADuM1412 isolators is a function of the supply sensing threshold and does not cause a faulty output transition. voltage, the data rate of the channel, and the output load of the Similarly, if such an event occurred during a transmitted pulse channel. (and had the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing For each input channel, the supply current is given by threshold of the decoder. I = I f ≤ 0.5 f DDI DDI (Q) r The preceding magnetic flux density values correspond to I = I × (2f − f) + I f > 0.5 f DDI DDI (D) r DDI (Q) r specific current magnitudes at given distances from the For each output channel, the supply current is given by ADuM1410/ADuM1411/ADuM1412 transformers. Figure 19 shows these allowable current magnitudes as a function of I = I f ≤ 0.5 f DDO DDO (Q) r frequency for selected distances. As shown, the ADuM1410/ I = (I + (0.5 × 10−3) × C × V ) × (2f − f) + I DDO DDO (D) L DDO r DDO (Q) ADuM1411/ADuM1412 is extremely immune and can be affected f > 0.5 f r only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted previously, a where: 0.5 kA current would have to be placed 5 mm away from the I , I are the input and output dynamic supply currents DDI (D) DDO (D) ADuM1410/ADuM1411/ADuM1412 to affect the operation of per channel (mA/Mbps). the component. C is the output load capacitance (pF). L V is the output supply voltage (V). 1000 DDO f is the input logic signal frequency (MHz); it is half the input kA) DISTANCE = 1m data rate, expressed in units of Mbps. T ( 100 EN fr is the input stage refresh rate (Mbps). R UR IDDI (Q), IDDO (Q) are the specified input and output quiescent E C 10 supply currents (mA). L B A DISTANCE = 100mm W To calculate the total V and V supply current, the supply O DD1 DD2 LL 1 currents for each input and output channel corresponding to A M DISTANCE = 5mm V and V are calculated and totaled. Figure 8 and Figure 9 U DD1 DD2 M XI 0.1 show per-channel supply currents as a function of data rate for A M an unloaded output condition. Figure 10 shows the per-channel supply current as a function of data rate for a 15 pF output 0.01 1k 10MkAGNET1IC0 0FkIELD FRE1QMUENCY (H1z0)M 100M 06580-019 VcoDnDd2 istuiopnp.l yF icguurrree n1t1 atsh aro fuugnhc tFioignu oref d1a5t ash roawte tfhoer AtoDtaul MVD1D411 a0n/d Figure 19. Maximum Allowable Current for Various ADuM1411/ADuM1412 channel configurations. Current-to-ADuM1410/ADuM1411/ADuM1412 Spacings INSULATION LIFETIME Note that at combinations of strong magnetic field and high All insulation structures eventually break down when subjected frequency, any loops formed by printed circuit board traces can to voltage stress over a sufficiently long period. The rate of induce error voltages sufficiently large enough to trigger the insulation degradation is dependent on the characteristics of the thresholds of succeeding circuitry. Care should be taken in the voltage waveform applied across the insulation. In addition to layout of such traces to avoid this possibility. the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM1410/ ADuM1411/ADuM1412. Rev. M | Page 20 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412 Analog Devices performs accelerated life testing using voltage Note that the voltage presented in Figure 21 is shown as sinusoidal levels higher than the rated continuous working voltage. for illustration purposes only. It is meant to represent any voltage Acceleration factors for several operating conditions are waveform varying between 0 V and some limiting value. The determined. These factors allow calculation of the time to limiting value can be positive or negative, but the voltage cannot failure at the actual working voltage. The values shown in cross 0 V. Table 10 summarize the peak voltage for 50 years of service life RATED PEAK VOLTAGE for a bipolar ac operating condition and the maximum CapSpAro/VveDdE w aoprpkrionvge vdo wltaogrke iins gh vigohltearg tehs.a nIn 5 m0-ayneya rc saesrevs,i cteh eli fe 0V 06580-020 Figure 20. Bipolar AC Waveform voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. The insulation lifetime of the ADuM1410/ADuM1411/ RATED PEAK VOLTAGE AacDrousMs t1h4e1 i2s odleaptieonnd bs aornri ethr.e T vhoelt iaCgeo uwpalveer fionrsmul atytipoen i smtrpuocsteudr e 0V 06580-021 degrades at different rates depending on whether the waveform Figure 21. Unipolar AC Waveform is bipolar ac, unipolar ac, or dc. Figure 20, Figure 21, and Figure 22 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal RATED PEAK VOLTAGE odfe tae r5m0-iyneeasr tohpee Arantainlogg l iDfeetvimicee su rnedceorm thmee ancd bedip molaarx icmonudmit ion 0V 06580-022 working voltage. Figure 22. DC Waveform In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 10 can be applied while maintaining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage case. Any cross-insulation voltage waveform that does not conform to Figure 21 or Figure 22 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 10. Rev. M | Page 21 of 22

ADuM1410/ADuM1411/ADuM1412 Data Sheet OUTLINE DIMENSIONS 10.50(0.4134) 10.10(0.3976) 16 9 7.60(0.2992) 7.40(0.2913) 1 8 10.65(0.4193) 10.00(0.3937) 1.27(0.0500) 0.75(0.0295) BSC 2.65(0.1043) 0.25(0.0098) 45° 0.30(0.0118) 2.35(0.0925) 8° 0.10(0.0039) 0° COPLANARITY 0.10 0.51(0.0201) SPELAATNIENG 0.33(0.0130) 1.27(0.0500) 0.31(0.0122) 0.20(0.0079) 0.40(0.0157) R(CINEOFNPEATRRREOENNLCLTEIHNCEOGOSNDMELISPYM)LAEAIANNRNDSETIAORTRNOOESUJNANEORDDETEEDAICN-POSMPFTRIFALONLMPIDMIRLAELIRATIMTDEEESRTFSMEO;SRIRN-0ECU1QH3SU-EADIVAIINMAELDENENSSTIIOGSNNFS.OR 03-27-2007-B Figure 23. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Number Number Maximum Maximum of Inputs, of Inputs, Maximum Propagation Pulse Width Temperature Package Model1 V Side V Side Data Rate Delay, 5 V Distortion Range Package Description Option DD1 DD2 ADuM1410ARWZ 4 0 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1410ARWZ-RL 4 0 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16 ADuM1410BRWZ 4 0 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1410BRWZ-RL 4 0 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16 ADuM1411ARWZ 3 1 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1411ARWZ-RL 3 1 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16 ADuM1411BRWZ 3 1 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1411BRWZ-RL 3 1 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16 ADuM1412ARWZ 2 2 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1412ARWZ-RL 2 2 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16 ADuM1412BRWZ 2 2 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1412BRWZ-RL 2 2 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16 1 Z = RoHS Compliant Part. ©2005–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06580-0-8/15(M) Rev. M | Page 22 of 22

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADUM1410BRWZ ADUM1410ARWZ ADUM1411ARWZ ADUM1410ARWZ-RL ADUM1411ARWZ-RL ADUM1412ARWZ ADUM1411BRWZ ADUM1410BRWZ-RL ADUM1412BRWZ ADUM1411BRWZ-RL ADUM1412BRWZ-RL ADUM1412ARWZ-RL