Quad-Channel Digital Isolators Data Sheet ADuM1400/ADuM1401/ADuM1402 FEATURES GENERAL DESCRIPTION Qualified for automotive applications The ADuM1400/ADuM1401/ADuM14021 are quad-channel Low power operation digital isolators based on Analog Devices, Inc., iCoupler® 5 V operation technology. Combining high speed CMOS and monolithic air 1.0 mA per channel maximum at 0 Mbps to 2 Mbps core transformer technology, these isolation components provide 3.5 mA per channel maximum at 10 Mbps outstanding performance characteristics superior to alternatives, 31 mA per channel maximum at 90 Mbps such as optocoupler devices. 3 V operation By avoiding the use of LEDs and photodiodes, iCoupler devices 0.7 mA per channel maximum at 0 Mbps to 2 Mbps remove the design difficulties commonly associated with opto- 2.1 mA per channel maximum at 10 Mbps couplers. The typical optocoupler concerns regarding uncertain 20 mA per channel maximum at 90 Mbps current transfer ratios, nonlinear transfer functions, and Bidirectional communication temperature and lifetime effects are eliminated with the simple 3 V/5 V level translation iCoupler digital interfaces and stable performance characteristics. High temperature operation: 125°C High data rate: dc to 90 Mbps (NRZ) The need for external drivers and other discrete components is Precise timing characteristics eliminated with these iCoupler products. Furthermore, iCoupler 2 ns maximum pulse width distortion devices consume one tenth to one sixth of the power of 2 ns maximum channel-to-channel matching optocouplers at comparable signal data rates. High common-mode transient immunity: >25 kV/μs The ADuM1400/ADuM1401/ADuM1402 isolators provide four Output enable function independent isolation channels in a variety of channel configu- 16-lead SOIC wide body package rations and data rates (see the Ordering Guide). All models RoHS-compliant models available operate with the supply voltage on either side ranging from Safety and regulatory approvals 2.7 V to 5.5 V, providing compatibility with lower voltage UL recognition: 2500 V rms for 1 minute per UL 1577 systems as well as enabling a voltage translation functionality CSA Component Acceptance Notice 5A across the isolation barrier. In addition, the ADuM1400/ VDE Certificate of Conformity ADuM1401/ADuM1402 provide low pulse width distortion DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 (<2 ns for CRW grade) and tight channel-to-channel matching V = 560 V peak IORM (<2 ns for CRW grade). Unlike other optocoupler alternatives, the TÜV approval: IEC/EN/UL/CSA 61010-1 ADuM1400/ADuM1401/ADuM1402 isolators have a patented APPLICATIONS refresh feature that ensures dc correctness in the absence of input logic transitions and when power is not applied to one of the General-purpose multichannel isolation supplies. SPI interface/data converter isolation RS-232/RS-422/RS-485 transceivers 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Industrial field bus isolation Automotive systems FUNCTIONAL BLOCK DIAGRAMS VDD1 1 16VDD2 VDD1 1 16VDD2 VDD1 1 16VDD2 GND1 2 15GND2 GND1 2 15GND2 GND1 2 15GND2 VIA 3 ENCODE DECODE 14VOA VIA 3 ENCODE DECODE 14VOA VIA 3 ENCODE DECODE 14VOA VIB 4 ENCODE DECODE 13VOB VIB 4 ENCODE DECODE 13VOB VIB 4 ENCODE DECODE 13VOB VIC 5 ENCODE DECODE 12VOC VIC 5 ENCODE DECODE 12VOC VOC 5 DECODE ENCODE 12VIC VID 6 ENCODE DECODE 11VOD VOD 6 DECODE ENCODE 11VID VOD 6 DECODE ENCODE 11VID GNNDC1 87 190VGEN2D2 03786-001 GNVDE11 87 190VGEN2D2 03786-002 GNVDE11 87 190VGEN2D2 03786-003 Figure 1. ADuM1400 Figure 2. ADuM1401 Figure 3. ADuM1402 Rev. L Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADuM1400/ADuM1401/ADuM1402 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Applications ....................................................................................... 1 Characteristics ............................................................................ 20 General Description ......................................................................... 1 Recommended Operating Conditions .................................... 20 Functional Block Diagrams ............................................................. 1 Absolute Maximum Ratings ......................................................... 21 Revision History ............................................................................... 3 ESD Caution................................................................................ 21 Specifications ..................................................................................... 4 Pin Configurations and Function Descriptions ......................... 22 Electrical Characteristics—5 V, 105°C Operation ................... 4 Typical Performance Characteristics ........................................... 25 Electrical Characteristics—3 V, 105°C Operation ................... 6 Applications Information .............................................................. 27 PC Board Layout ........................................................................ 27 Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V, 105°C Operation ....................................................................................... 8 Propagation Delay-Related Parameters ................................... 27 Electrical Characteristics—5 V, 125°C Operation ................. 11 DC Correctness and Magnetic Field Immunity ..................... 27 Electrical Characteristics—3 V, 125°C Operation ................. 13 Power Consumption .................................................................. 28 Electrical Characteristics—Mixed 5 V/3 V, 125°C Operation Insulation Lifetime ..................................................................... 29 ....................................................................................................... 15 Outline Dimensions ....................................................................... 30 Electrical Characteristics—Mixed 3 V/5 V, 125°C Operation Ordering Guide .......................................................................... 30 ....................................................................................................... 17 Automotive Products ................................................................. 31 Package Characteristics ............................................................. 19 Regulatory Information ............................................................. 19 Insulation and Safety Related Specifications .......................... 19 Rev. L | Page 2 of 31

Data Sheet ADuM1400/ADuM1401/ADuM1402 REVISION HISTORY 12/2016—Rev. K to Rev. L 6/2007—Rev. D to Rev. E Changes to Table 1 ............................................................................ 4 Updated VDE Certification Throughout ....................................... 1 Changes to Table 2 ............................................................................ 6 Changes to Features and Note 1 ...................................................... 1 Changes to Table 3 ............................................................................ 9 Changes to Figure 1, Figure 2, and Figure 3 .................................. 1 Changes to Table 4 .......................................................................... 11 Changes to Regulatory Information Section ............................... 10 Changes to Table 5 .......................................................................... 13 Changes to Table 7 .......................................................................... 11 Changes to Table 6 .......................................................................... 15 Added Table 10 ................................................................................ 12 Changes to Table 7 .......................................................................... 17 Added Insulation Lifetime Section ............................................... 20 Changes to Table 9 and Table 10 ................................................... 19 Updated Outline Dimensions........................................................ 21 Changes to Ordering Guide ........................................................... 30 Changes to Ordering Guide ........................................................... 21 7/2015—Rev. J to Rev. K 2/2006—Rev. C to Rev. D Changes to Table 9 and Table 10 ................................................... 19 Updated Format ................................................................. Universal Added TÜV Approval ....................................................... Universal 4/2015—Rev. I to Rev. J Changed ADuM140x to ADuM1400/ADuM1401/ 5/2005—Rev. B to Rev. C ADuM1402..................................................................... Throughout Changes to Format ............................................................. Universal Changes to Table 10 ........................................................................ 19 Changes to Figure 2 .......................................................................... 1 Changes to Table 3 ............................................................................ 8 4/2014—Rev. H to Rev. I Changes to Table 6 .......................................................................... 12 Change to Table 9 ............................................................................ 19 Changes to Ordering Guide ........................................................... 21 3/2012—Rev. G to Rev. H 6/2004—Rev. A to Rev. B Created Hyperlink for Safety and Regulatory Approvals Changes to Format ............................................................. Universal Entry in Features Section ................................................................. 1 Changes to Features .......................................................................... 1 Change to PC Board Layout Section ............................................ 27 Changes to Electrical Characteristics—5 V Operation ................ 3 Updated Outline Dimensions ........................................................ 30 Changes to Electrical Characteristics—3 V Operation ................ 5 Moved Automotive Products Section ........................................... 31 Changes to Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V Operation ............................................................................ 7 5/2008—Rev. F to Rev. G Changes to DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation Added ADuM1400W, ADuM1401W, and ADuM1402W Characteristics Title ........................................................................ 11 Parts ...................................................................................... Universal Changes to the Ordering Guide .................................................... 19 Added Table 4 .................................................................................. 11 Added Table 5 .................................................................................. 13 5/2004—Rev. 0 to Rev. A Added Table 6 .................................................................................. 15 Updated Format ................................................................. Universal Added Table 7 .................................................................................. 17 Changes to the Features.................................................................... 1 Changes to Table 12 ........................................................................ 20 Changes to Table 7 and Table 8 ..................................................... 14 Changes to Table 13 ........................................................................ 21 Changes to Table 9 .......................................................................... 15 Added Automotive Products Section ........................................... 29 Changes to the DC Correctness and Magnetic Field Immunity Changes to Ordering Guide ........................................................... 30 Section .............................................................................................. 20 Changes to the Power Consumption Section .............................. 21 11/2007—Rev. E to Rev. F Changes to the Ordering Guide .................................................... 22 Changes to Note 1 ............................................................................. 1 Added ADuM140xARW Change vs. Temperature Parameter ... 4 9/2003—Revision 0: Initial Version Added ADuM140xARW Change vs. Temperature Parameter ... 5 Added ADuM140xARW Change vs. Temperature Parameter ... 8 Changes to Figure 17 ...................................................................... 18 Rev. L | Page 3 of 31

ADuM1400/ADuM1401/ADuM1402 Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION1 4.5 V ≤ V ≤ 5.5 V, 4.5 V ≤ V ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, DD1 DD2 unless otherwise noted; all typical specifications are at T = 25°C, V = V = 5 V. These specifications do not apply to ADuM1400W, A DD1 DD2 ADuM1401W, and ADuM1402W automotive grade versions. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I 0.50 0.53 mA DDI (Q) Output Supply Current per Channel, Quiescent I 0.19 0.21 mA DDO (Q) ADuM1400 Total Supply Current, Four Channels2 DC to 2 Mbps V Supply Current I 2.2 2.8 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.9 1.4 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V Supply Current I 8.6 10.6 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 2.6 3.5 mA 5 MHz logic signal freq. DD2 DD2 (10) 90 Mbps (CRW Grade Only) V Supply Current I 70 100 mA 45 MHz logic signal freq. DD1 DD1 (90) V Supply Current I 18 25 mA 45 MHz logic signal freq. DD2 DD2 (90) ADuM1401 Total Supply Current, Four Channels2 DC to 2 Mbps V Supply Current I 1.8 2.4 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 1.2 1.8 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V Supply Current I 7.1 9.0 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 4.1 5.0 mA 5 MHz logic signal freq. DD2 DD2 (10) 90 Mbps (CRW Grade Only) V Supply Current I 57 82 mA 45 MHz logic signal freq. DD1 DD1 (90) V Supply Current I 31 43 mA 45 MHz logic signal freq. DD2 DD2 (90) ADuM1402 Total Supply Current, Four Channels2 DC to 2 Mbps V or V Supply Current I , I 1.5 2.1 mA DC to 1 MHz logic signal freq. DD1 DD2 DD1 (Q) DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V or V Supply Current I , I 5.6 7.0 mA 5 MHz logic signal freq. DD1 DD2 DD1 (10) DD2 (10) 90 Mbps (CRW Grade Only) V or V Supply Current I , I 44 62 mA 45 MHz logic signal freq. DD1 DD2 DD1 (90) DD2 (90) For All Models Input Currents I , I , I , −10 +0.01 +10 µA 0 V ≤ V , V , V , V ≤ V or V , IA IB IC IA IB IC ID DD1 DD2 I , I , I 0 V ≤ V , V ≤ V or V ID E1 E2 E1 E2 DD1 DD2 Logic High Input Threshold V , V 2.0 V IH EH Logic Low Input Threshold V , V 0.8 V IL EL Logic High Output Voltages V , V , (V or V ) − 0.1 5.0 V I = −20 µA, V = V OAH OBH DD1 DD2 Ox Ix IxH VOCH, VODH (VDD1 or VDD2) − 0.4 4.8 V IOx = −3.2 mA, VIx = VIxH Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 0.2 0.4 V I = 3.2 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ADuM1400ARW/ADuM1401ARW/ADuM1402ARW Minimum Pulse Width3 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate4 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay5 t , t 50 65 100 ns C = 15 pF, CMOS signal levels PHL PLH L Rev. L | Page 4 of 31

Data Sheet ADuM1400/ADuM1401/ADuM1402 Parameter Symbol Min Typ Max Unit Test Conditions Pulse Width Distortion, |t − t |5 PWD 40 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 11 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew6 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching7 t /t 50 ns C = 15 pF, CMOS signal levels PSKCD PSKOD L ADuM1400BRW/ADuM1401BRW/ADuM1402BRW Minimum Pulse Width3 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate4 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay5 t , t 20 32 50 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |5 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew6 t 15 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, Codirectional t 3 ns C = 15 pF, CMOS signal levels PSKCD L Channels7 Channel-to-Channel Matching, Opposing- t 6 ns C = 15 pF, CMOS signal levels PSKOD L Directional Channels7 ADuM1400CRW/ADuM1401CRW/ADuM1402CRW Minimum Pulse Width3 PW 8.3 11.1 ns C = 15 pF, CMOS signal levels L Maximum Data Rate4 90 120 Mbps C = 15 pF, CMOS signal levels L Propagation Delay5 t , t 18 27 32 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |5 PWD 0.5 2 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 3 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew6 t 10 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, Codirectional t 2 ns C = 15 pF, CMOS signal levels PSKCD L Channels7 Channel-to-Channel Matching, Opposing- t 5 ns C = 15 pF, CMOS signal levels PSKOD L Directional Channels7 For All Models Output Disable Propagation Delay (High/Low t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L to High Impedance) Output Enable Propagation Delay (High t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L Impedance to High/Low) Output Rise/Fall Time (10% to 90%) t/t 2.5 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity at Logic |CM | 25 35 kV/µs V = V or V , V = 1000 V, H Ix DD1 DD2 CM High Output8 transient magnitude = 800 V Common-Mode Transient Immunity at Logic |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM Low Output8 transient magnitude = 800 V Refresh Rate f 1.2 Mbps r Input Dynamic Supply Current per Channel9 I 0.19 mA/Mbps DDI (D) Output Dynamic Supply Current per Channel9 I 0.05 mA/Mbps DDO (D) 1 All voltages are relative to their respective ground. 2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. L | Page 5 of 31

ADuM1400/ADuM1401/ADuM1402 Data Sheet ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION1 2.7 V ≤ V ≤ 3.6 V, 2.7 V ≤ V ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, DD1 DD2 unless otherwise noted; all typical specifications are at T = 25°C, V = V = 3.0 V. These specifications do not apply to ADuM1400W, A DD1 DD2 ADuM1401W, and ADuM1402W automotive grade versions. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I 0.26 0.31 mA DDI (Q) Output Supply Current per Channel, Quiescent I 0.11 0.14 mA DDO (Q) ADuM1400 Total Supply Current, Four Channels2 DC to 2 Mbps V Supply Current I 1.2 1.9 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.5 0.9 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V Supply Current I 4.5 6.5 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 1.4 2.0 mA 5 MHz logic signal freq. DD2 DD2 (10) 90 Mbps (CRW Grade Only) V Supply Current I 37 65 mA 45 MHz logic signal freq. DD1 DD1 (90) V Supply Current I 11 15 mA 45 MHz logic signal freq. DD2 DD2 (90) ADuM1401 Total Supply Current, Four Channels2 DC to 2 Mbps V Supply Current I 1.0 1.6 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.7 1.2 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V Supply Current I 3.7 5.4 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 2.2 3.0 mA 5 MHz logic signal freq. DD2 DD2 (10) 90 Mbps (CRW Grade Only) V Supply Current I 30 52 mA 45 MHz logic signal freq. DD1 DD1 (90) V Supply Current I 18 27 mA 45 MHz logic signal freq. DD2 DD2 (90) ADuM1402 Total Supply Current, Four Channels2 DC to 2 Mbps V or V Supply Current I , I 0.9 1.5 mA DC to 1 MHz logic signal freq. DD1 DD2 DD1 (Q) DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V or V Supply Current I , I 3.0 4.2 mA 5 MHz logic signal freq. DD1 DD2 DD1 (10) DD2 (10) 90 Mbps (CRW Grade Only) V or V Supply Current I , I 24 39 mA 45 MHz logic signal freq. DD1 DD2 DD1 (90) DD2 (90) For All Models Input Currents I , I , I , −10 +0.01 +10 µA 0 V ≤ V , V , V , V ≤ V or V , IA IB IC IA IB IC ID DD1 DD2 I , I , I 0 V ≤ V , V ≤ V or V ID E1 E2 E1 E2 DD1 DD2 Logic High Input Threshold V , V 1.6 V IH EH Logic Low Input Threshold V , V 0.4 V IL EL Logic High Output Voltages V , V , (V or V ) − 0.1 3.0 V I = −20 µA, V = V OAH OBH DD1 DD2 Ox Ix IxH VOCH, VODH (VDD1 or VDD2) − 0.4 2.8 V IOx = −3.2 mA, VIx = VIxH Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 0.2 0.4 V I = 3.2 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ADuM1400ARW/ADuM1401ARW/ADuM1402ARW Minimum Pulse Width3 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate4 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay5 t , t 50 75 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |5 PWD 40 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 11 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew6 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching7 t /t 50 ns C = 15 pF, CMOS signal levels PSKCD PSKOD L Rev. L | Page 6 of 31

Data Sheet ADuM1400/ADuM1401/ADuM1402 Parameter Symbol Min Typ Max Unit Test Conditions ADuM1400BRW/ADuM1401BRW/ADuM1402BRW Minimum Pulse Width3 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate4 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay5 t , t 20 38 50 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |5 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew6 t 22 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, Codirectional t 3 ns C = 15 pF, CMOS signal levels PSKCD L Channels7 Channel-to-Channel Matching, Opposing- t 6 ns C = 15 pF, CMOS signal levels PSKOD L Directional Channels7 ADuM1400CRW/ADuM1401CRW/ADuM1402CRW Minimum Pulse Width3 PW 8.3 11.1 ns C = 15 pF, CMOS signal levels L Maximum Data Rate4 90 120 Mbps C = 15 pF, CMOS signal levels L Propagation Delay5 t , t 20 34 45 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |5 PWD 0.5 2 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 3 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew6 t 16 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, Codirectional t 2 ns C = 15 pF, CMOS signal levels PSKCD L Channels7 Channel-to-Channel Matching, Opposing- t 5 ns C = 15 pF, CMOS signal levels PSKOD L Directional Channels7 For All Models Output Disable Propagation Delay (High/Low to t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L High Impedance) Output Enable Propagation Delay (High t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L Impedance to High/Low) Output Rise/Fall Time (10% to 90%) t/t 3 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity at Logic |CM | 25 35 kV/µs V = V or V , V = 1000 V, H Ix DD1 DD2 CM High Output8 transient magnitude = 800 V Common-Mode Transient Immunity at Logic |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM Low Output8 transient magnitude = 800 V Refresh Rate f 1.1 Mbps r Input Dynamic Supply Current per Channel9 I 0.10 mA/ DDI (D) Mbps Output Dynamic Supply Current per Channel9 I 0.03 mA/ DDO (D) Mbps 1 All voltages are relative to their respective ground. 2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. L | Page 7 of 31

ADuM1400/ADuM1401/ADuM1402 Data Sheet ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION1 5 V/3 V operation: 4.5 V ≤ V ≤ 5.5 V, 2.7 V ≤ V ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ V ≤ 3.6 V, 4.5 V ≤ V ≤ 5.5 V; all DD1 DD2 DD1 DD2 minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at T = 25°C; V = 3.0 V, V = 5 V or V = 5 V, V = 3.0 V. These specifications do not apply to ADuM1400W, ADuM1401W, A DD1 DD2 DD1 DD2 and ADuM1402W automotive grade versions. Table 3. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent IDDI (Q) 5 V/3 V Operation 0.50 0.53 mA 3 V/5 V Operation 0.26 0.31 mA Output Supply Current per Channel, Quiescent IDDO (Q) 5 V/3 V Operation 0.11 0.14 mA 3 V/5 V Operation 0.19 0.21 mA ADuM1400 Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 5 V/3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 5 V/3 V Operation 0.5 0.9 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.9 1.4 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current IDD1 (10) 5 V/3 V Operation 8.6 10.6 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.5 6.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 5 V/3 V Operation 1.4 2.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.6 3.5 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) VDD1 Supply Current IDD1 (90) 5 V/3 V Operation 70 100 mA 45 MHz logic signal freq. 3 V/5 V Operation 37 65 mA 45 MHz logic signal freq. VDD2 Supply Current IDD2 (90) 5 V/3 V Operation 11 15 mA 45 MHz logic signal freq. 3 V/5 V Operation 18 25 mA 45 MHz logic signal freq. ADuM1401 Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 5 V/3 V Operation 1.8 2.4 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.0 1.6 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.8 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current IDD1 (10) 5 V/3 V Operation 7.1 9.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.7 5.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 5 V/3 V Operation 2.2 3.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.1 5.0 mA 5 MHz logic signal freq. Rev. L | Page 8 of 31

Data Sheet ADuM1400/ADuM1401/ADuM1402 Parameter Symbol Min Typ Max Unit Test Conditions 90 Mbps (CRW Grade Only) VDD1 Supply Current IDD1 (90) 5 V/3 V Operation 57 82 mA 45 MHz logic signal freq. 3 V/5 V Operation 30 52 mA 45 MHz logic signal freq. VDD2 Supply Current IDD2 (90) 5 V/3 V Operation 18 27 mA 45 MHz logic signal freq. 3 V/5 V Operation 31 43 mA 45 MHz logic signal freq. ADuM1402 Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 5 V/3 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 5 V/3 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current IDD1 (10) 5 V/3 V Operation 5.6 7.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.0 4.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 5 V/3 V Operation 3.0 4.2 mA 5 MHz logic signal freq. 3 V/5 V Operation 5.6 7.0 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) VDD1 Supply Current IDD1 (90) 5 V/3 V Operation 44 62 mA 45 MHz logic signal freq. 3 V/5 V Operation 24 39 mA 45 MHz logic signal freq. VDD2 Supply Current IDD2 (90) 5 V/3 V Operation 24 39 mA 45 MHz logic signal freq. 3 V/5 V Operation 44 62 mA 45 MHz logic signal freq. For All Models Input Currents IIA, IIB, IIC, −10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, IID, IE1, IE2 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2 Logic High Input Threshold VIH, VEH 5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V Logic Low Input Threshold VIL, VEL 5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V Logic High Output Voltages VOAH, VOBH, (VDD1 or VDD2) − 0.1 (VDD1 or VDD2) V IOx = −20 µA, VIx = VIxH VOCH, VODH (VDD1 or VDD2) − 0.4 (VDD1 or VDD2) − 0.2 V IOx = −3.2 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL, 0.0 0.1 V IOx = 20 µA, VIx = VIxL VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 0.2 0.4 V IOx = 3.2 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM1400ARW/ADuM1401ARW/ADuM1402ARW Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 tPHL, tPLH 50 70 100 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching7 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels ADuM1400BRW/ADuM1401BRW/ADuM1402BRW Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 tPHL, tPLH 15 35 50 ns CL = 15 pF, CMOS signal levels Rev. L | Page 9 of 31

ADuM1400/ADuM1401/ADuM1402 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 tPSK 22 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional tPSKCD 3 ns CL = 15 pF, CMOS signal levels Channels7 Channel-to-Channel Matching, Opposing- tPSKOD 6 ns CL = 15 pF, CMOS signal levels Directional Channels7 ADuM1400CRW/ADuM1401CRW/ADuM1402CRW Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 tPHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 tPSK 14 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional tPSKCD 2 ns CL = 15 pF, CMOS signal levels Channels7 Channel-to-Channel Matching, Opposing- tPSKOD 5 ns CL = 15 pF, CMOS signal levels Directional Channels7 For All Models Output Disable Propagation Delay (High/Low tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels to High Impedance) Output Enable Propagation Delay (High tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/tF CL = 15 pF, CMOS signal levels 5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns Common-Mode Transient Immunity at Logic |CMH| 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V, High Output8 transient magnitude = 800 V Common-Mode Transient Immunity at Logic |CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V, Low Output8 transient magnitude = 800 V Refresh Rate fr 5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps Input Dynamic Supply Current per Channel9 IDDI (D) 5 V/3 V Operation 0.19 mA/Mbps 3 V/5 V Operation 0.10 mA/Mbps Output Dynamic Supply Current per Channel9 IDDO (D) 5 V/3 V Operation 0.03 mA/Mbps 3 V/5 V Operation 0.05 mA/Mbps 1 All voltages are relative to their respective ground. 2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. L | Page 10 of 31

Data Sheet ADuM1400/ADuM1401/ADuM1402 ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION1 4.5 V ≤ V ≤ 5.5 V, 4.5 V ≤ V ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, DD1 DD2 unless otherwise noted; all typical specifications are at T = 25°C, V = V = 5 V. These specifications apply to ADuM1400W, A DD1 DD2 ADuM1401W, and ADuM1402W automotive grade versions. Table 4. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I 0.50 0.53 mA DDI (Q) Output Supply Current per Channel, Quiescent I 0.19 0.21 mA DDO (Q) ADuM1400W, Total Supply Current, Four Channels2 DC to 2 Mbps V Supply Current I 2.2 2.8 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.9 1.4 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 8.6 10.6 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 2.6 3.5 mA 5 MHz logic signal freq. DD2 DD2 (10) ADuM1401W, Total Supply Current, Four Channels2 DC to 2 Mbps V Supply Current I 1.8 2.4 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 1.2 1.8 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 7.1 9.0 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 4.1 5.0 mA 5 MHz logic signal freq. DD2 DD2 (10) ADuM1402W, Total Supply Current, Four Channels2 DC to 2 Mbps V or V Supply Current I , I 1.5 2.1 mA DC to 1 MHz logic signal freq. DD1 DD2 DD1 (Q) DD2 (Q) 10 Mbps (TRWZ Grade Only) V or V Supply Current I , I 5.6 7.0 mA 5 MHz logic signal freq. DD1 DD2 DD1 (10) DD2 (10) For All Models Input Currents I , I , I , −10 +0.01 +10 µA 0 V ≤ V , V , V , V ≤ V or V , IA IB IC IA IB IC ID DD1 DD2 I , I , I 0 V ≤ V , V ≤ V or V ID E1 E2 E1 E2 DD1 DD2 Logic High Input Threshold V , V 2.0 V IH EH Logic Low Input Threshold V , V 0.8 V IL EL Logic High Output Voltages V , V , (V or V ) − 0.1 5.0 V I = −20 µA, V = V OAH OBH DD1 DD2 Ox Ix IxH VOCH, VODH (VDD1 or VDD2) − 0.4 4.8 V IOx = −3.2 mA, VIx = VIxH Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 0.2 0.4 V I = 3.2 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ADuM1400WSRWZ/ADuM1401WSRWZ/ ADuM1402WSRWZ Minimum Pulse Width3 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate4 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay5 t , t 50 65 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |5 PWD 40 ns C = 15 pF, CMOS signal levels PLH PHL L Propagation Delay Skew6 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching7 t /t 50 ns C = 15 pF, CMOS signal levels PSKCD PSKOD L Rev. L | Page 11 of 31

ADuM1400/ADuM1401/ADuM1402 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions ADuM1400WTRWZ/ADuM1401WTRWZ/ ADuM1402WTRWZ Minimum Pulse Width3 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate4 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay5 t , t 18 27 34 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |5 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew6 t 15 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, Codirectional t 3 ns C = 15 pF, CMOS signal levels PSKCD L Channels7 Channel-to-Channel Matching, Opposing- t 6 ns C = 15 pF, CMOS signal levels PSKOD L Directional Channels7 For All Models Output Disable Propagation Delay (High/Low t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L to High Impedance) Output Enable Propagation Delay (High t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L Impedance to High/Low) Output Rise/Fall Time (10% to 90%) t/t 2.5 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity at Logic |CM | 25 35 kV/µs V = V /V , V = 1000 V, H Ix DD1 DD2 CM High Output8 transient magnitude = 800 V Common-Mode Transient Immunity at Logic |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM Low Output8 transient magnitude = 800 V Refresh Rate f 1.2 Mbps r Input Dynamic Supply Current per Channel9 I 0.19 mA/Mbps DDI (D) Output Dynamic Supply Current per Channel9 I 0.05 mA/Mbps DDO (D) 1 All voltages are relative to their respective ground. 2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. L | Page 12 of 31

Data Sheet ADuM1400/ADuM1401/ADuM1402 ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION1 3.0 V ≤ V ≤ 3.6 V, 3.0 V ≤ V ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, DD1 DD2 unless otherwise noted; all typical specifications are at T = 25°C, V = V = 3.0 V. These specifications apply to ADuM1400W, A DD1 DD2 ADuM1401W, and ADuM1402W automotive grade versions. Table 5. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, I 0.26 0.31 mA DDI (Q) Quiescent Output Supply Current per Channel, I 0.11 0.14 mA DDO (Q) Quiescent ADuM1400W, Total Supply Current, Four Channels2 DC to 2 Mbps V Supply Current I 1.2 1.9 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.5 0.9 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 4.5 6.5 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 1.4 2.0 mA 5 MHz logic signal freq. DD2 DD2 (10) ADuM1401W, Total Supply Current, Four Channels2 DC to 2 Mbps V Supply Current I 1.0 1.6 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.7 1.2 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 3.7 5.4 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 2.2 3.0 mA 5 MHz logic signal freq. DD2 DD2 (10) ADuM1402W, Total Supply Current, Four Channels2 DC to 2 Mbps V or V Supply Current I , I 0.9 1.5 mA DC to 1 MHz logic signal freq. DD1 DD2 DD1 (Q) DD2 (Q) 10 Mbps (TRWZ Grade Only) V or V Supply Current I , I 3.0 4.2 mA 5 MHz logic signal freq. DD1 DD2 DD1 (10) DD2 (10) For All Models Input Currents I , I , I , −10 +0.01 +10 µA 0 V ≤ V , V , V , V ≤ V or V , IA IB IC IA IB IC ID DD1 DD2 I , I , I 0 V ≤ V , V ≤ V or V ID E1 E2 E1 E2 DD1 DD2 Logic High Input Threshold V , V 1.6 V IH EH Logic Low Input Threshold V , V 0.4 V IL EL Logic High Output Voltages V , V , (V or V ) − 0.1 3.0 V I = −20 µA, V = V OAH OBH DD1 DD2 Ox Ix IxH VOCH, VODH (VDD1 or VDD2) − 0.4 2.8 V IOx = −3.2 mA, VIx = VIxH Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 0.2 0.4 V I = 3.2 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ADuM1400WSRWZ/ADuM1401WSRWZ/ ADuM1402WSRWZ Minimum Pulse Width3 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate4 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay5 t , t 50 75 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |5 PWD 40 ns C = 15 pF, CMOS signal levels PLH PHL L Propagation Delay Skew6 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching7 t /t 50 ns C = 15 pF, CMOS signal levels PSKCD PSKOD L Rev. L | Page 13 of 31

ADuM1400/ADuM1401/ADuM1402 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions ADuM1400WTRWZ/ADuM1401WTRWZ/ ADuM1402WTRWZ Minimum Pulse Width3 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate4 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay5 t , t 20 34 45 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |5 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew6 t 22 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 3 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels7 Channel-to-Channel Matching, t 6 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels7 For All Models Output Disable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L (High/Low to High Impedance) Output Enable Propagation Delay (High t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L Impedance to High/Low) Output Rise/Fall Time (10% to 90%) t/t 3 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity at |CM | 25 35 kV/µs V = V /V , V = 1000 V, H Ix DD1 DD2 CM Logic High Output8 transient magnitude = 800 V Common-Mode Transient Immunity at |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM Logic Low Output8 transient magnitude = 800 V Refresh Rate f 1.1 Mbps r Input Dynamic Supply Current per I 0.10 mA/Mbps DDI (D) Channel9 Output Dynamic Supply Current per I 0.03 mA/Mbps DDO (D) Channel9 1 All voltages are relative to their respective ground. 2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. L | Page 14 of 31

Data Sheet ADuM1400/ADuM1401/ADuM1402 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION1 4.5 V ≤ V ≤ 5.5 V, 3.0 V ≤ V ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, DD1 DD2 unless otherwise noted; all typical specifications are at T = 25°C; V = 5 V, V = 3.0 V. These specifications apply to ADuM1400W, A DD1 DD2 ADuM1401W, and ADuM1402W automotive grade versions. Table 6. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I 0.50 0.53 mA DDI (Q) Output Supply Current per Channel, Quiescent I 0.11 0.14 mA DDO (Q) ADuM1400W, Total Supply Current, Four Channels2 DC to 2 Mbps V Supply Current I 2.2 2.8 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.5 0.9 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 8.6 10.6 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 1.4 2.0 mA 5 MHz logic signal freq. DD2 DD2 (10) ADuM1401W, Total Supply Current, Four Channels2 DC to 2 Mbps V Supply Current I 1.8 2.4 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.7 1.2 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 7.1 9.0 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 2.2 3.0 mA 5 MHz logic signal freq. DD2 DD2 (10) ADuM1402W, Total Supply Current, Four Channels2 DC to 2 Mbps V Supply Current I 1.5 2.1 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.9 1.5 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 5.6 7.0 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 3.0 4.2 mA 5 MHz logic signal freq. DD2 DD2 (10) For All Models Input Currents I , I , I , −10 +0.01 +10 µA 0 V ≤ V , V , V , V ≤ V IA IB IC IA IB IC ID DD1 I , I , I or V , 0 V ≤ V , V ≤ V ID E1 E2 DD2 E1 E2 DD1 or V DD2 Logic High Input Threshold V , V IH EH 5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V Logic Low Input Threshold V , V IL EL 5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V Logic High Output Voltages V , V , (V or V ) − 0.1 V or V V I = −20 µA, V = V OAH OBH DD1 DD2 DD1 DD2 Ox Ix IxH VOCH, VODH (VDD1 or VDD2) − 0.4 VDD1, VDD2 − 0.2 V IOx = −3.2 mA, VIx = VIxH Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 0.2 0.4 V I = 3.2 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ADuM1400WSRWZ/ADuM1401WSRWZ/ ADuM1402WSRWZ Minimum Pulse Width3 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate4 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay5 t , t 50 70 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |5 PWD 40 ns C = 15 pF, CMOS signal levels PLH PHL L Propagation Delay Skew6 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching7 t /t 50 ns C = 15 pF, CMOS signal levels PSKCD PSKOD L Rev. L | Page 15 of 31

ADuM1400/ADuM1401/ADuM1402 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions ADuM1400WTRWZ/ADuM1401WTRWZ/ ADuM1402WTRWZ Minimum Pulse Width3 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate4 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay5 t , t 20 30 40 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |5 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew6 t 22 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, Codirectional t 3 ns C = 15 pF, CMOS signal levels PSKCD L Channels7 Channel-to-Channel Matching, Opposing- t 6 ns C = 15 pF, CMOS signal levels PSKOD L Directional Channels7 For All Models Output Disable Propagation Delay (High/Low t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L to High Impedance) Output Enable Propagation Delay (High t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L Impedance to High/Low) Output Rise/Fall Time (10% to 90%) t/t 3.0 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity at Logic |CM | 25 35 kV/µs V = V /V , V = 1000 V, H Ix DD1 DD2 CM High Output8 transient magnitude = 800 V Common-Mode Transient Immunity at Logic |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM Low Output8 transient magnitude = 800 V Refresh Rate f 1.2 Mbps r Input Dynamic Supply Current per Channel9 I 0.19 mA/Mbps DDI (D) Output Dynamic Supply Current per Channel9 I 0.03 mA/Mbps DDO (D) 1 All voltages are relative to their respective ground. 2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. L | Page 16 of 31

Data Sheet ADuM1400/ADuM1401/ADuM1402 ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION1 3.0 V ≤ V ≤ 3.6 V, 4.5 V ≤ V ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, DD1 DD2 unless otherwise noted; all typical specifications are at T = 25°C; V = 3.0 V, V = 5 V. These specifications apply to ADuM1400W, A DD1 DD2 ADuM1401W, and ADuM1402W automotive grade versions. Table 7. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I 0.26 0.31 mA DDI (Q) Output Supply Current per Channel, Quiescent I 0.19 0.21 mA DDO (Q) ADuM1400W, Total Supply Current, Four Channels2 DC to 2 Mbps V Supply Current I 1.2 1.9 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.9 1.4 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 4.5 6.5 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 2.6 3.5 mA 5 MHz logic signal freq. DD2 DD2 (10) ADuM1401W, Total Supply Current, Four Channels2 DC to 2 Mbps V Supply Current I 1.0 1.6 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 1.2 1.8 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 3.7 5.4 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 4.1 5.0 mA 5 MHz logic signal freq. DD2 DD2 (10) ADuM1402W, Total Supply Current, Four Channels2 DC to 2 Mbps V Supply Current I 0.9 1.5 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 1.5 2.1 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 3.0 4.2 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 5.6 7.0 mA 5 MHz logic signal freq. DD2 DD2 (10) For All Models Input Currents I , I , I , −10 +0.01 +10 µA 0 V ≤ V , V , V , V ≤ V or IA IB IC IA IB IC ID DD1 I , I , I V , 0 V ≤ V , V ≤ V or V ID E1 E2 DD2 E1 E2 DD1 DD2 Logic High Input Threshold V , V 1.6 V IH EH Logic Low Input Threshold V , V 0.4 V IL EL Logic High Output Voltages V , V , (V or V ) − 0.1 V , V V I = −20 µA, V = V OAH OBH DD1 DD2 DD1 DD2 Ox Ix IxH VOCH, VODH (VDD1 or VDD2) − 0.4 VDD1, VDD2 − 0.2 V IOx = −3.2 mA, VIx = VIxH Logic Low Output Voltages V , V , 0.0 0.1 V I = 20 µA, V = V OAL OBL Ox Ix IxL VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 0.2 0.4 V I = 3.2 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ADuM1400WSRWZ/ADuM1401WSRWZ/ ADuM1402WSRWZ Minimum Pulse Width3 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate4 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay5 t , t 50 70 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |5 PWD 40 ns C = 15 pF, CMOS signal levels PLH PHL L Propagation Delay Skew6 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching7 t /t 50 ns C = 15 pF, CMOS signal levels PSKCD PSKOD L Rev. L | Page 17 of 31

ADuM1400/ADuM1401/ADuM1402 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions ADuM1400WTRWZ/ADuM1401WTRWZ/ ADuM1402WTRWZ Minimum Pulse Width3 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate4 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay5 t , t 20 30 40 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |5 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew6 t 22 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 3 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels7 Channel-to-Channel Matching, Opposing- t 6 ns C = 15 pF, CMOS signal levels PSKOD L Directional Channels7 For All Models Output Disable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L (High/Low to High Impedance) Output Enable Propagation Delay (High t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L Impedance to High/Low) Output Rise/Fall Time (10% to 90%) t/t 2.5 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity at |CM | 25 35 kV/µs V = V /V , V = 1000 V, H Ix DD1 DD2 CM Logic High Output8 transient magnitude = 800 V Common-Mode Transient Immunity at |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM Logic Low Output8 transient magnitude = 800 V Refresh Rate f 1.1 Mbps r Input Dynamic Supply Current per Channel9 I 0.10 mA/Mbps DDI (D) Output Dynamic Supply Current per Channel9 I 0.05 mA/Mbps DDO (D) 1 All voltages are relative to their respective ground. 2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. L | Page 18 of 31

Data Sheet ADuM1400/ADuM1401/ADuM1402 PACKAGE CHARACTERISTICS Table 8. Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input to Output)1 R 1012 Ω I-O Capacitance (Input to Output)1 C 2.2 pF f = 1 MHz I-O Input Capacitance2 C 4.0 pF I IC Junction to Case Thermal Resistance, Side 1 θ 33 °C/W Thermocouple located at JCI IC Junction to Case Thermal Resistance, Side 2 θ 28 °C/W center of package underside JCO 1 Device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, and Pin 16 are shorted together. 2 Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM1400/ADuM1401/ADuM1402 are approved by the organizations listed in Table 9. Refer to Table 14 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 9. UL CSA VDE CQC TÜV Recognized Under Approved under Certified according to Approved under Approved according to UL 1577 Component CSA Component DIN V VDE V 0884-10 CQC11-471543-2012 IEC 61010-1:2001 (2nd Edition), Recognition Acceptance Notice 5A (VDE V 0884-10):2006-122 EN 61010-1:2001 (2nd Edition), Program1 UL 61010-1:2004, and CSA C22.2.61010.1:2005 Single Protection, Basic insulation per Reinforced insulation, Basic Insulation per Reinforced insulation, 400 V rms 2500 V rms Isolation CSA 60950-1-03 and 560 V peak GB4943.1-2011, 415 V rms maximum working voltage Voltage IEC 60950-1, 780 V rms (588 V peak) maximum (1103 V peak) maximum working voltage, tropical working voltage climate, altitude ≤ 5000 m Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 390 V rms (551 V peak) maximum working voltage File E214100 File 205078 File 2471900-4880-0001 File CQC14001114900 Certificate U8V 05 06 56232 002 1 In accordance with UL 1577, each ADuM1400/ADuM1401/ADuM1402 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA). 2 In accordance with DIN V VDE V 0884-10, each ADuM1400/ADuM1401/ADuM1402 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY RELATED SPECIFICATIONS Table 10. Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 7.8 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 7.8 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Clearance in the Plane of the Printed L(PCB) 8.3 min mm Measured from input terminals to output terminals, Circuit Board (PCB Clearance) shortest distance through air, and line of sight, in the PCB mounting plane Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1 Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1) Rev. L | Page 19 of 31

ADuM1400/ADuM1401/ADuM1402 Data Sheet DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval. Table 11. Description Conditions Symbol Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V 560 V peak IORM Input to Output Test Voltage, Method B1 V × 1.875 = V , 100% production test, t = 1 sec, V 1050 V peak IORM PR m PR partial discharge < 5 pC Input to Output Test Voltage, Method A V × 1.6 = V , t = 60 sec, partial discharge < 5 pC V IORM PR m PR After Environmental Tests Subgroup 1 896 V peak After Input and/or Safety Test Subgroup 2 V × 1.2 = V , t = 60 sec, partial discharge < 5 pC 672 V peak IORM PR m and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, t = 10 seconds V 4000 V peak TR TR Safety Limiting Values Maximum value allowed in the event of a failure (see Figure 4) Case Temperature T 150 °C S Side 1 Current I 265 mA S1 Side 2 Current I 335 mA S2 Insulation Resistance at T V = 500 V R >109 Ω S IO S 350 RECOMMENDED OPERATING CONDITIONS 300 Table 12. A) m Parameter Rating T ( 250 EN SIDE #2 Operating Temperature (TA)1 −40°C to +105°C R UR 200 Operating Temperature (TA)2 −40°C to +125°C C G Supply Voltages (VDD1, VDD2)1, 3 2.7 V to 5.5 V N MITI 150 SIDE #1 Supply Voltages (VDD1, VDD2)2, 3 3.0 V to 5.5 V LI Input Signal Rise and Fall Times 1.0 ms Y- 100 ET AF 1 Does not apply to ADuM1400W, ADuM1401W, and ADuM1402W automotive S 50 grade versions. 2 Applies to ADuM1400W, ADuM1401W, and ADuM1402W automotive grade 00 50CASE TEMP1E0R0ATURE (°C)150 200 03786-004 3 Avaenllrd vs ioMolntaasgg.n eest aicr eF ireellda tImivem tuon tihtye isre rcetsipoenc ftoivr ein gforormunadti.o Sne eo nth iem DmCu Cnoitryr etoct ness Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values external magnetic fields. with Case Temperature per DIN V VDE V 0884-10 Rev. L | Page 20 of 31

Data Sheet ADuM1400/ADuM1401/ADuM1402 ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 13. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational Storage Temperature (T ) −65°C to +150°C ST section of this specification is not implied. Operation beyond Ambient Operating Temperature (T)1 −40°C to +105°C A the maximum operating conditions for extended periods may Ambient Operating Temperature (T)2 −40°C to +125°C A affect product reliability. Supply Voltages (V , V )3 −0.5 V to +7.0 V DD1 DD2 Input Voltage (V , V , V , V , V , V )3, 4 −0.5 V to V + 0.5 V ESD CAUTION IA IB IC ID E1 E2 DDI Output Voltage (V , V , V , V )3, 4 −0.5 V to V + 0.5 V OA OB OC OD DDO Average Output Current per Pin5 Side 1 (I ) −18 mA to +18 mA O1 Side 2 (I ) −22 mA to +22 mA O2 Common-Mode Transients6 −100 kV/µs to +100 kV/µs 1 Does not apply to ADuM1400W, ADuM1401W, and ADuM1402W automotive grade versions. 2 Applies to ADuM1400W, ADuM1401W, and ADuM1402W automotive grade versions. 3 All voltages are relative to their respective ground. 4 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section. 5 See Figure 4 for maximum rated current values for various temperatures. 6 This refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Ratings may cause latch-up or permanent damage. Table 14. Maximum Continuous Working Voltage1 Parameter Max Unit Constraint AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime AC Voltage, Unipolar Waveform Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 DC Voltage Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Table 15. Truth Table (Positive Logic) V Input1 V Input1, 2 V State1 V State1 V Output1 Notes Ix Ex DDI DDO Ox H H or NC Powered Powered H L H or NC Powered Powered L X L Powered Powered Z X H or NC Unpowered Powered H Outputs return to the input state within 1 µs of V power restoration. DDI X L Unpowered Powered Z X X Powered Unpowered Indeterminate Outputs return to the input state within 1 µs of V power restoration DDO if the V state is H or NC. Outputs return to a high impedance state Ex within 8 ns of V power restoration if the V state is L. DDO Ex 1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively. 2 In noisy environments, connecting VEx to an external logic high or low is recommended. Rev. L | Page 21 of 31

ADuM1400/ADuM1401/ADuM1402 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1 1 16 VDD2 *GND1 2 15 GND2* VIA 3 ADuM1400 14 VOA VIB 4 TOP VIEW 13 VOB VIC 5 (Not to Scale) 12 VOC VID 6 11 VOD NC 7 10 VE2 *GND1 8NC = NO CONNECT9 GND2* 03786-005 *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED. Figure 5. ADuM1400 Pin Configuration Table 16. ADuM1400 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage for Isolator Side 1. DD1 2 GND Ground 1. Ground reference for Isolator Side 1. 1 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Input C. IC 6 V Logic Input D. ID 7 NC No Connect. 8 GND Ground 1. Ground reference for Isolator Side 1. 1 9 GND Ground 2. Ground reference for Isolator Side 2. 2 10 V Output Enable 2. Active high logic input. V , V , V , and V outputs are enabled when V is high or disconnected. E2 OA OB OC OD E2 V , V , V , and V outputs are disabled when V is low. In noisy environments, connecting V to an external logic OA OB OC OD E2 E2 high or low is recommended. 11 V Logic Output D. OD 12 V Logic Output C. OC 13 V Logic Output B. OB 14 V Logic Output A. OA 15 GND Ground 2. Ground reference for Isolator Side 2. 2 16 V Supply Voltage for Isolator Side 2. DD2 Rev. L | Page 22 of 31

Data Sheet ADuM1400/ADuM1401/ADuM1402 VDD1 1 16 VDD2 *GND1 2 15 GND2* VIA 3 ADuM1401 14 VOA VIB 4 TOP VIEW 13 VOB VIC 5 (Not to Scale) 12 VOC VOD 6 11 VID VE1 7 10 VE2 *GND1 8 9 GND2* 03786-006 *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED. Figure 6. ADuM1401 Pin Configuration Table 17. ADuM1401 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage for Isolator Side 1. DD1 2 GND Ground 1. Ground reference for Isolator Side 1. 1 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Input C. IC 6 V Logic Output D. OD 7 V Output Enable 1. Active high logic input. V output is enabled when V is high or disconnected. V is disabled E1 OD E1 OD when V is low. In noisy environments, connecting V to an external logic high or low is recommended. E1 E1 8 GND Ground 1. Ground reference for Isolator Side 1. 1 9 GND Ground 2. Ground reference for Isolator Side 2. 2 10 V Output Enable 2. Active high logic input. V , V , and V outputs are enabled when V is high or disconnected. V , E2 OA OB OC E2 OA V , and V outputs are disabled when V is low. In noisy environments, connecting V to an external logic high or OB OC E2 E2 low is recommended. 11 V Logic Input D. ID 12 V Logic Output C. OC 13 V Logic Output B. OB 14 V Logic Output A. OA 15 GND Ground 2. Ground reference for Isolator Side 2. 2 16 V Supply Voltage for Isolator Side 2. DD2 Rev. L | Page 23 of 31

ADuM1400/ADuM1401/ADuM1402 Data Sheet VDD1 1 16 VDD2 *GND1 2 15 GND2* VIA 3 ADuM1402 14 VOA VIB 4 TOP VIEW 13 VOB VOC 5 (Not to Scale) 12 VIC VOD 6 11 VID VE1 7 10 VE2 *GND1 8 9 GND2* 03786-007 *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED. Figure 7. ADuM1402 Pin Configuration Table 18. ADuM1402 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage for Isolator Side 1. DD1 2 GND Ground 1. Ground reference for Isolator Side 1. 1 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Output C. OC 6 V Logic Output D. OD 7 V Output Enable 1. Active high logic input. V and V outputs are enabled when V is high or disconnected. V and E1 OC OD E1 OC V outputs are disabled when V is low. In noisy environments, connecting V to an external logic high or low is OD E1 E1 recommended. 8 GND Ground 1. Ground reference for Isolator Side 1. 1 9 GND Ground 2. Ground reference for Isolator Side 2. 2 10 V Output Enable 2. Active high logic input. V and V outputs are enabled when V is high or disconnected. V and E2 OA OB E2 OA V outputs are disabled when V is low. In noisy environments, connecting V to an external logic high or low is OB E2 E2 recommended. 11 V Logic Input D. ID 12 V Logic Input C. IC 13 V Logic Output B. OB 14 V Logic Output A. OA 15 GND Ground 2. Ground reference for Isolator Side 2. 2 16 V Supply Voltage for Isolator Side 2. DD2 Rev. L | Page 24 of 31

Data Sheet ADuM1400/ADuM1401/ADuM1402 TYPICAL PERFORMANCE CHARACTERISTICS 20 80 70 15 60 A) m NEL ( mA) 50 NT/CHAN 10 5V URRENT ( 4300 5V RE C R 3V 3V U 5 20 C 10 00 20 DA4T0A RATE (M6b0ps) 80 100 03786-008 00 20 DA4T0A RATE (M6b0ps) 80 100 03786-011 Figure 8. Typical Input Supply Current per Channel vs. Data Rate Figure 11. Typical ADuM1400 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation for 5 V and 3 V Operation 6 25 5 20 A) m 4 NEL ( mA) 15 NT/CHAN 3 5V URRENT ( 10 RE 2 C 5V R CU 3V 3V 5 1 00 20 DA4T0A RATE (M6b0ps) 80 100 03786-009 00 20 DA4T0A RATE (M6b0ps) 80 100 03786-012 Figure 9. Typical Output Supply Current per Channel vs. Data Rate Figure 12. Typical ADuM1400 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation (No Output Load) for 5 V and 3 V Operation 10 35 30 8 A) 25 m NEL ( 6 mA) 20 T/CHAN 4 RRENT ( 15 REN 5V CU 5V R 10 CU 3V 2 3V 5 00 20 DA4T0A RATE (M6b0ps) 80 100 03786-010 00 20 DA4T0A RATE (M6b0ps) 80 100 03786-013 Figure 10. Typical Output Supply Current per Channel vs. Data Rate Figure 13. Typical ADuM1401 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load) for 5 V and 3 V Operation Rev. L | Page 25 of 31

ADuM1400/ADuM1401/ADuM1402 Data Sheet 40 40 35 30 s) 3V n Y ( 35 mA) 25 ELA RENT ( 20 5V TION D UR 15 GA C A 30 3V OP 10 R P 5V 5 00 20 DA4T0A RATE (M6b0ps) 80 100 03786-014 25–50 –25 0TEMPERA2T5URE (°C)50 75 100 03786-016 Figure 14. Typical ADuM1401 VDD2 Supply Current vs. Data Rate Figure 16. Propagation Delay vs. Temperature, C Grade for 5 V and 3 V Operation 50 45 40 35 A) 30 m NT ( 25 E R R 20 CU 5V 15 3V 10 5 00 20 DA4T0A RATE (M6b0ps) 80 100 03786-015 Figure 15. Typical ADuM1402 VDD1 or VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation Rev. L | Page 26 of 31

Data Sheet ADuM1400/ADuM1401/ADuM1402 APPLICATIONS INFORMATION PC BOARD LAYOUT DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY The ADuM1400/ADuM1401/ADuM1402 digital isolators require no external interface circuitry for the logic interfaces. Positive and negative logic transitions at the isolator input Power supply bypassing is strongly recommended at the input cause narrow (~1 ns) pulses to be sent to the decoder via the and output supply pins (see Figure 17). Bypass capacitors are transformer. The decoder is bistable and is, therefore, either set most conveniently connected between Pin 1 and Pin 2 for VDD1 or reset by the pulses, indicating input logic transitions. In the and between Pin 15 and Pin 16 for VDD2. The capacitor value absence of logic transitions at the input for more than ~1 µs, a should be between 0.01 µF and 0.1 µF. The total lead length periodic set of refresh pulses indicative of the correct input state between both ends of the capacitor and the input power supply are sent to ensure dc correctness at the output. If the decoder pin should not exceed 20 mm. Bypassing between Pin 1 and Pin receives no internal pulses of more than about 5 µs, the input 8 and between Pin 9 and Pin 16 should also be considered, side is assumed to be unpowered or nonfunctional, in which unless the ground pair on each package side is connected close case the isolator output is forced to a default state (see Table 15) to the package. by the watchdog timer circuit. VDD1 VDD2 The limitation on the magnetic field immunity of the ADuM1400/ GND1 GND2 VIA VOA ADuM1401/ADuM1402 is set by the condition in which induced VIB VOB voltage in the receiving coil of the transformer is sufficiently large VIC/VOC VOC/VIC VNIDCG//VNVODED11 VVGOEN2DD/V2ID 03786-017 ea3nn Voal uoygspihes r tdaoet iefniintghe ceso rt nhfadeli scteioolnyn ds oeitfti otohnre sr eAusnDedtu etMhr ew1 d4he0icc0ho/A dtheDri.su TMmha1ey4 f 0oo1lcl/co uwri. nTgh e Figure 17. Recommended Printed Circuit Board Layout ADuM1402 is examined because it represents the most susceptible In applications involving high common-mode transients, care mode of operation. should be taken to ensure that board coupling across the isolation The pulses at the transformer output have an amplitude greater barrier is minimized. Furthermore, the board layout should be than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus designed such that any coupling that does occur equally affects establishing a 0.5 V margin in which induced voltages can be all pins on a given component side. Failure to ensure this could tolerated. The voltage induced across the receiving coil is given by cause voltage differentials between pins exceeding the Absolute Maximum Ratings of the device, thereby leading to latch-up or V = (−dβ/dt)∑∏rn2; n = 1, 2, … , N permanent damage. where: See the AN-1109 Application Note for board layout guidelines. β is magnetic flux density (gauss). N is the number of turns in the receiving coil. PROPAGATION DELAY-RELATED PARAMETERS r is the radius of the nth turn in the receiving coil (cm). n Propagation delay is a parameter that describes the time it takes Given the geometry of the receiving coil in the ADuM1400/ a logic signal to propagate through a component. The propagation ADuM1401/ADuM1402 and an imposed requirement that the delay to a Logic 0 output may differ from the propagation delay induced voltage be 50% at most of the 0.5 V margin at the to a Logic 1 output. decoder, a maximum allowable magnetic field is calculated as INPUT (VIx) 50% shown in Figure 19. tPLH tPHL 100 OUTPUT (VOx) 50% 03786-018 C FLUX 10 Figure 18. Propagation Delay Parameters ETI N Pulse width distortion is the maximum difference between AGss) these two propagation delay values and is an indication of how LE Mkgau 1 aCchcaunrnateell-yt ot-hceh tainmnienlg m oaf ttchhei ningp ruetf esrisg ntoa lt hise p mreasxeirmveudm. amount ALLOWABDENSITY (0.1 the propagation delay differs between channels within a single UM ADuM1400/ADuM1401/ADuM1402 component. XIM 0.01 A M Propagation delay skew refers to the maximum amount the pArDopuaMga1t4io0n1/ dAeDlauyM di1f4fe0r2s cboemtwpeoenne mntus lotippeler aAtiDngu Mun1d4e0r0 t/h e same 0.0011k 10kMAGNETI1C0 0FkIELD FREQ1MUENCY (Hz1)0M 100M 03786-019 conditions. Figure 19. Maximum Allowable External Magnetic Flux Density Rev. L | Page 27 of 31

ADuM1400/ADuM1401/ADuM1402 Data Sheet For example, at a magnetic field frequency of 1 MHz, the POWER CONSUMPTION maximum allowable magnetic field of 0.2 kgauss induces a The supply current at a given channel of the ADuM1400/ voltage of 0.25 V at the receiving coil. This is about 50% of the ADuM1401/ADuM1402 isolator is a function of the supply sensing threshold and does not cause a faulty output transition. voltage, the data rate of the channel, and the output load of the Similarly, if such an event occurs during a transmitted pulse channel. (and has the worst-case polarity), it reduces the received pulse For each input channel, the supply current is given by from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder. I = I f ≤ 0.5 f DDI DDI (Q) r The preceding magnetic flux density values correspond to I = I × (2f − f) + I f > 0.5 f DDI DDI (D) r DDI (Q) r specific current magnitudes at given distances from the For each output channel, the supply current is given by ADuM1400/ADuM1401/ADuM1402 transformers. Figure 20 I = I f ≤ 0.5 f expresses these allowable current magnitudes as a function of DDO DDO (Q) r frequency for selected distances. As shown, the ADuM1400/ I = (I + (0.5 × 10−3) × C × V ) × (2f − f) + I DDO DDO (D) L DDO r DDO (Q) ADuM1401/ADuM1402 are extremely immune and can be f > 0.5 f r affected only by extremely large currents operated at high where: frequency very close to the component. For the 1 MHz example I , I are the input and output dynamic supply currents DDI (D) DDO (D) noted, one would have to place a 0.5 kA current 5 mm away per channel (mA/Mbps). from the ADuM1400/ADuM1401/ADuM1402 to affect the C is the output load capacitance (pF). L operation of the component. V is the output supply voltage (V). DDO 1000 f is the input logic signal frequency (MHz); it is half of the input A) DISTANCE = 1m data rate expressed in units of Mbps. k NT ( 100 fr is the input stage refresh rate (Mbps). E RR IDDI (Q), IDDO (Q) are the specified input and output quiescent U C supply currents (mA). E 10 L AB DISTANCE = 100mm To calculate the total VDD1 and VDD2 supply current, the supply W O currents for each input and output channel corresponding to L 1 L A V and V are calculated and totaled. Figure 8 and Figure 9 M DISTANCE = 5mm DD1 DD2 MU provide per-channel supply currents as a function of data rate AXI 0.1 for an unloaded output condition. Figure 10 provides per- M channel supply current as a function of data rate for a 15 pF 0.01 output condition. Figure 11 through Figure 15 provide total 1k 10MkAGNET1IC0 0FkIELD FRE1QMUENCY (H1z0)M 100M 03786-020 VADDDu1 Man1d4 V00D/DA2 DsuupMpl1y4 c0u1r/rAenDt uaMs a1 4fu0n2c cthioann noef ld caotan friagtuer faotrio ns. Figure 20. Maximum Allowable Current for Various Current-to-ADuM1400/ADuM1401/ADuM1402 Spacings Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. Rev. L | Page 28 of 31

Data Sheet ADuM1400/ADuM1401/ADuM1402 INSULATION LIFETIME In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower, which allows operation at higher working All insulation structures eventually break down when subjected voltages while still achieving a 50-year service life. The working to voltage stress over a sufficiently long period. The rate of voltages listed in Table 14 can be applied while maintaining the insulation degradation is dependent on the characteristics of 50-year minimum lifetime, provided the voltage conforms to either the voltage waveform applied across the insulation. In addition the unipolar ac or dc voltage cases. Any cross-insulation voltage to the testing performed by the regulatory agencies, Analog waveform that does not conform to Figure 22 or Figure 23 should Devices carries out an extensive set of evaluations to determine be treated as a bipolar ac waveform, and its peak voltage should the lifetime of the insulation structure within the ADuM1400/ be limited to the 50-year lifetime voltage value listed in Table 14. ADuM1401/ADuM1402. Note that the voltage presented in Figure 22 is shown as sinusoidal Analog Devices performs accelerated life testing using voltage for illustration purposes only. It is meant to represent any voltage levels higher than the rated continuous working voltage. Accel- waveform varying between 0 V and some limiting value. The eration factors for several operating conditions are determined. limiting value can be positive or negative, but the voltage cannot These factors allow calculation of the time to failure at the actual cross 0 V. working voltage. The values shown in Table 14 summarize the peak voltage for 50 years of service life for a bipolar ac operating RATED PEAK VOLTAGE cvoonltdagiteios.n I nan mda tnhye cmasaexsi,m thuem a pCpSrAov/VedD wEo arpkpinrogv veodl twagoer kisin hgi gher 0V 03786-021 than a 50-year service life voltage. Operation at these high working Figure 21. Bipolar AC Waveform voltages can lead to shortened insulation life in some cases. RATED PEAK VOLTAGE TAhDeu iMns1u4la0t2io dne pliefentdims oen o ft hthe ev oAlDtaugeM w1a4v0e0f/oArmD utyMp1e4 i0m1p/ osed 0V 03786-022 across the isolation barrier. The iCoupler insulation structure Figure 22. Unipolar AC Waveform degrades at different rates depending on whether the waveform RATED PEAK VOLTAGE is bipolar ac, unipolar ac, or dc. Figure 21, Figure 22, and Figure 23 illustrate these different isolation voltage waveforms, respectively. 0V 03786-023 Bipolar ac voltage is the most stringent environment. The goal Figure 23. DC Waveform of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage. Rev. L | Page 29 of 31

ADuM1400/ADuM1401/ADuM1402 Data Sheet OUTLINE DIMENSIONS 10.50(0.4134) 10.10(0.3976) 16 9 7.60(0.2992) 7.40(0.2913) 1 8 10.65(0.4193) 10.00(0.3937) 1.27(0.0500) 0.75(0.0295) BSC 2.65(0.1043) 0.25(0.0098) 45° 0.30(0.0118) 2.35(0.0925) 8° 0.10(0.0039) 0° COPLANARITY 0.10 0.51(0.0201) SPELAATNIENG 0.33(0.0130) 1.27(0.0500) 0.31(0.0122) 0.20(0.0079) 0.40(0.0157) C(RINOEFNPEATRRREOENNLCLTEIHNCEOGOSNDMELISPYM)LAEAIANNRNDSETIAORTRNOOESUJNANEORDDETEEDAICN-POSMPFTRIFALONLMPIDMIRLAELIRATIMTDEEESRTFSMEO;SRIRN-0ECU1QH3SU-EADIVAIINMAELDENENSSTIIOGSNNFS.OR 03-27-2007-B Figure 24. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Number Number Maximum Maximum Maximum of Inputs, of Inputs, Data Rate Propagation Pulse Width Temperature Package Package Model1, 2, 3, 4 V Side V Side (Mbps) Delay, 5 V (ns) Distortion (ns) Range Description Option DD1 DD2 ADuM1400ARW 4 0 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1400BRW 4 0 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1400CRW 4 0 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1400ARWZ 4 0 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1400BRWZ 4 0 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1400CRWZ 4 0 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1400WSRWZ 4 0 1 100 40 −40°C to +125°C 16-Lead SOIC_W RW-16 ADuM1400WTRWZ 4 0 10 34 3 −40°C to +125°C 16-Lead SOIC_W RW-16 ADuM1401ARW 3 1 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1401BRW 3 1 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1401CRW 3 1 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1401ARWZ 3 1 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1401BRWZ 3 1 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1401CRWZ 3 1 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1401WSRWZ 3 1 1 100 40 −40°C to +125°C 16-Lead SOIC_W RW-16 ADuM1401WTRWZ 3 1 10 34 3 −40°C to +125°C 16-Lead SOIC_W RW-16 ADuM1402ARW 2 2 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1402BRW 2 2 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1402CRW 2 2 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1402ARWZ 2 2 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1402BRWZ 2 2 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1402CRWZ 2 2 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1402WSRWZ 2 2 1 100 40 −40°C to +125°C 16-Lead SOIC_W RW-16 ADuM1402WTRWZ 2 2 10 34 3 −40°C to +125°C 16-Lead SOIC_W RW-16 EVAL-ADuMQSEBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. 3 Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape and reel option. 4 No tape and reel option is available for the ADuM1400CRW or ADuM1402BRW models. Rev. L | Page 30 of 31

Data Sheet ADuM1400/ADuM1401/ADuM1402 AUTOMOTIVE PRODUCTS The ADuM1400W/ADuM1401W/ADuM1402W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ©2003–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03786-0-12/16(L) Rev. L | Page 31 of 31

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