Triple-Channel Digital Isolators Data Sheet ADuM1300/ADuM1301 FEATURES GENERAL DESCRIPTION Qualified for automotive applications The ADuM1300/ADuM13011 are triple-channel digital isolators Low power operation based on the Analog Devices, Inc., iCoupler® technology. 5 V operation Combining high speed CMOS and monolithic transformer 1.2 mA per channel maximum at 0 Mbps to 2 Mbps technology, these isolation components provide outstanding 3.5 mA per channel maximum at 10 Mbps performance characteristics superior to alternatives, such as 32 mA per channel maximum at 90 Mbps optocouplers. 3 V operation By avoiding the use of LEDs and photodiodes, iCoupler 0.8 mA per channel maximum at 0 Mbps to 2 Mbps devices remove the design difficulties commonly associated 2.2 mA per channel maximum at 10 Mbps with optocouplers. The typical optocoupler concerns regarding 20 mA per channel maximum at 90 Mbps uncertain current transfer ratios, nonlinear transfer functions, and Bidirectional communication temperature and lifetime effects are eliminated with the simple 3 V/5 V level translation iCoupler digital interfaces and stable performance characteristics. High temperature operation: 125°C The need for external drivers and other discrete components is High data rate: dc to 90 Mbps (NRZ) eliminated with these iCoupler products. Furthermore, iCoupler Precise timing characteristics devices consume one-tenth to one-sixth of the power of 2 ns maximum pulse width distortion optocouplers at comparable signal data rates. 2 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs The ADuM1300/ADuM1301 isolators provide three independent Output enable function isolation channels in a variety of channel configurations and 16-lead SOIC wide body package data rates (see the Ordering Guide). Both models operate with RoHS-compliant models available the supply voltage on either side ranging from 2.7 V to 5.5 V, Safety and regulatory approvals providing compatibility with lower voltage systems as well as UL recognition: 2500 V rms for 1 minute per UL 1577 enabling a voltage translation functionality across the isolation CSA Component Acceptance Notice 5A barrier. In addition, the ADuM1300/ADuM1301 provide low VDE Certificate of Conformity pulse width distortion (<2 ns for CRW grade) and tight channel- DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 to-channel matching (<2 ns for CRW grade). Unlike other V = 560 V peak optocoupler alternatives, the ADuM1300/ADuM1301 isolators IORM TÜV approval: IEC/EN/UL/CSA 61010-1 have a patented refresh feature that ensures dc correctness in the APPLICATIONS absence of input logic transitions and when power is not applied to one of the supplies. General-purpose multichannel isolation SPI interface/data converter isolation 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. RS-232/RS-422/RS-485 transceivers Industrial field bus isolation Automotive systems FUNCTIONAL BLOCK DIAGRAMS VDD1 1 16 VDD2 VDD1 1 16 VDD2 GND1 2 15 GND2 GND1 2 15 GND2 VIA 3 ENCODE DECODE 14 VOA VIA 3 ENCODE DECODE 14 VOA VIB 4 ENCODE DECODE 13 VOB VIB 4 ENCODE DECODE 13 VOB VIC 5 ENCODE DECODE 12 VOC VOC 5 DECODE ENCODE 12 VIC NC 6 11 NC NC 6 11 NC NC 7 10 VE2 VE1 7 10 VE2 GND1 8 9 GND2 03787-001 GND1 8 9 GND2 03787-002 Figure 1. ADuM1300 Functional Block Diagram Figure 2. ADuM1301 Functional Block Diagram Rev. K Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2003–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADuM1300/ADuM1301 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Applications ....................................................................................... 1 Characteristics ............................................................................ 20 General Description ......................................................................... 1 Recommended Operating Conditions .................................... 20 Functional Block Diagrams ............................................................. 1 Absolute Maximum Ratings ......................................................... 21 Revision History ............................................................................... 3 ESD Caution................................................................................ 21 Specifications ..................................................................................... 4 Pin Configurations and Function Descriptions ......................... 22 Electrical Characteristics—5 V, 105°C Operation ................... 4 Typical Performance Characteristics ........................................... 23 Electrical Characteristics—3 V, 105°C Operation ................... 6 Applications Information .............................................................. 25 Printed Circuit Board (PCB) Layout ....................................... 25 Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V, 105°C Operation ........................................................................... 8 Propagation Delay-Related Parameters ................................... 25 Electrical Characteristics—5 V, 125°C Operation ................. 11 DC Correctness and Magnetic Field Immunity .......................... 25 Electrical Characteristics—3 V, 125°C Operation ................. 13 Power Consumption .................................................................. 26 Electrical Characteristics—Mixed 5 V/3 V, 125°C Operation ... 15 Insulation Lifetime ..................................................................... 27 Electrical Characteristics—Mixed 3 V/5 V, 125°C Operation .... 17 Outline Dimensions ....................................................................... 28 Package Characteristics ............................................................. 19 Ordering Guide .......................................................................... 29 Regulatory Information ............................................................. 19 Automotive Products ................................................................. 29 Insulation and Safety-Related Specifications .......................... 19 Rev. K | Page 2 of 32

Data Sheet ADuM1300/ADuM1301 REVISION HISTORY 11/15—Rev. J to Rev. K 2/06—Rev. D to Rev. E Changes to Table 9 and Table 10 ................................................... 19 Updated Format ................................................................. Universal Changes to Ordering Guide ........................................................... 29 Added TÜV Approval ....................................................... Universal Changes to Figure 2 .......................................................................... 1 4/14—Rev. I to Rev. J Change to Table 9 ............................................................................ 19 5/05—Rev. C to Rev. D Changes to Format ............................................................. Universal 3/12—Rev. H to Rev. I Changes to Figure 2 .......................................................................... 1 Created Hyperlink for Safety and Regulatory Approvals Changes to Table 6 .......................................................................... 10 Entry in Features Section ................................................................. 1 Changes to Ordering Guide ........................................................... 18 Change to PC Board Layout Section ............................................ 25 Updated Outline Dimensions ........................................................ 28 6/04—Rev. B to Rev. C Moved Automotive Products Section ........................................... 28 Changes to Format ............................................................. Universal Changes to Features .......................................................................... 1 5/08—Rev. G to Rev. H Changes to Electrical Characteristics—5 V Operation ................ 3 Added ADuM1300W and ADuM1301W Parts ............. Universal Changes to Electrical Characteristics—3 V Operation ................ 5 Changes to Features List ................................................................... 1 Changes to Electrical Characteristics—Mixed 5 V/3 V or Added Table 4 .................................................................................. 11 3 V/5 V Operation ............................................................................ 7 Added Table 5 .................................................................................. 13 Changes to Ordering Guide ........................................................... 18 Added Table 6 .................................................................................. 15 Added Table 7 .................................................................................. 17 5/04—Rev. A to Rev. B Changes to Table 12 ........................................................................ 20 Changes to the Format ...................................................... Universal Changes to Table 13 ........................................................................ 21 Changes to the Features.................................................................... 1 Added Automotive Products Section ........................................... 27 Changes to Table 7 and Table 8 ..................................................... 14 Changes to Ordering Guide ........................................................... 28 Changes to Table 9 .......................................................................... 15 Changes to the DC Correctness and Magnetic Field Immunity 11/07—Rev. F to Rev. G Section .............................................................................................. 19 Changes to Note 1 and Figure 2 ...................................................... 1 Changes to the Power Consumption Section .............................. 20 Added ADuM130xARW Change vs. Temperature Parameter ... 3 Changes to the Ordering Guide .................................................... 21 Added ADuM130xARW Change vs. Temperature Parameter ... 5 Added ADuM130xARW Change vs. Temperature Parameter ... 8 9/03—Rev. 0 to Rev. A Changes to Figure 14 ...................................................................... 16 Edits to Regulatory Information ................................................... 13 Edits to Absolute Maximum Ratings ............................................ 15 6/07—Rev. E to Rev. F Deleted the Package Branding Information ................................ 16 Updated VDE Certification Throughout ....................................... 1 Changes to Features, Note 1, Figure 1, and Figure 2 .................... 1 9/03—Revision 0: Initial Version Changes to Regulatory Information Section ............................... 10 Added Table 10 ................................................................................ 12 Added Insulation Lifetime Section ............................................... 17 Updated Outline Dimensions ........................................................ 19 Changes to Ordering Guide ........................................................... 19 Rev. K | Page 3 of 32

ADuM1300/ADuM1301 Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION All voltages are relative to their respective ground. 4.5 V ≤ V ≤ 5.5 V, 4.5 V ≤ V ≤ 5.5 V; all minimum/maximum specifications apply DD1 DD2 over the entire recommended operation range, unless otherwise noted; all typical specifications are at T = 25°C, V = V = 5 V. These A DD1 DD2 specifications do not apply to ADuM1300W and ADuM1301W automotive grade versions. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I 0.50 0.53 mA DDI (Q) Output Supply Current per Channel, Quiescent I 0.19 0.24 mA DDO (Q) ADuM1300 Total Supply Current, Three Channels1 DC to 2 Mbps V Supply Current I 1.6 2.5 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.7 1.0 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V Supply Current I 6.5 8.1 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 1.9 2.5 mA 5 MHz logic signal freq. DD2 DD2 (10) 90 Mbps (CRW Grade Only) V Supply Current I 57 77 mA 45 MHz logic signal freq. DD1 DD1 (90) V Supply Current I 16 18 mA 45 MHz logic signal freq. DD2 DD2 (90) ADuM1301 Total Supply Current, Three Channels1 DC to 2 Mbps V Supply Current I 1.3 2.1 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 1.0 1.4 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V Supply Current I 5.0 6.2 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 3.4 4.2 mA 5 MHz logic signal freq. DD2 DD2 (10) 90 Mbps (CRW Grade Only) V Supply Current I 43 57 mA 45 MHz logic signal freq. DD1 DD1 (90) V Supply Current I 29 37 mA 45 MHz logic signal freq. DD2 DD2 (90) For All Models Input Currents I , I , I , I , I −10 +0.01 +10 µA 0 V ≤ V , V , V ≤ V or V , IA IB IC E1 E2 IA IB IC DD1 DD2 0 V ≤ V , V ≤ V or V E1 E2 DD1 DD2 Logic High Input Threshold V , V 2.0 V IH EH Logic Low Input Threshold V , V 0.8 V IL EL Logic High Output Voltages V , V , V (V or V ) − 0.1 5.0 V I = −20 µA, V = V OAH OBH OCH DD1 DD2 Ox Ix IxH (V or V ) − 0.4 4.8 V I = −4 mA, V = V DD1 DD2 Ox Ix IxH Logic Low Output Voltages V , V , V 0.0 0.1 V I = 20 µA, V = V OAL OBL OCL Ox Ix IxL 0.04 0.1 V I = 400 µA, V = V Ox Ix IxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ADuM1300ARW/ADuM1301ARW Minimum Pulse Width2 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 50 65 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 11 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching6 t /t 50 ns C = 15 pF, CMOS signal levels PSKCD PSKOD L Rev. K | Page 4 of 32

Data Sheet ADuM1300/ADuM1301 Parameter Symbol Min Typ Max Unit Test Conditions ADuM1300BRW/ADuM1301BRW Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 20 32 50 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 tPSK 15 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional t 3 ns C = 15 pF, CMOS signal levels PSKCD L Channels6 Channel-to-Channel Matching, Opposing- t 6 ns C = 15 pF, CMOS signal levels PSKOD L Directional Channels6 ADuM1300CRW/ADuM1301CRW Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 18 27 32 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 3 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 tPSK 10 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional t 2 ns C = 15 pF, CMOS signal levels PSKCD L Channels6 Channel-to-Channel Matching, Opposing- t 5 ns C = 15 pF, CMOS signal levels PSKOD L Directional Channels6 For All Models Output Disable Propagation Delay (High/Low t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L to High Impedance) Output Enable Propagation Delay (High t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L Impedance to High/Low) Output Rise/Fall Time (10% to 90%) t/t 2.5 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity at Logic |CMH| 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V, High Output7 transient magnitude = 800 V Common-Mode Transient Immunity at Logic |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM Low Output7 transient magnitude = 800 V Refresh Rate f 1.2 Mbps r Input Dynamic Supply Current per Channel8 I 0.19 mA/Mbps DDI (D) Output Dynamic Supply Current per Channel8 IDDO (D) 0.05 mA/Mbps 1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. K | Page 5 of 32

ADuM1300/ADuM1301 Data Sheet ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION All voltages are relative to their respective ground. 2.7 V ≤ V ≤ 3.6 V, 2.7 V ≤ V ≤ 3.6 V; all minimum/maximum specifications apply DD1 DD2 over the entire recommended operation range, unless otherwise noted; all typical specifications are at T = 25°C, V = V = 3.0 V. A DD1 DD2 These specifications do not apply to ADuM1300W and ADuM1301W automotive grade versions. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I 0.26 0.31 mA DDI (Q) Output Supply Current per Channel, Quiescent I 0.11 0.15 mA DDO (Q) ADuM1300 Total Supply Current, Three Channels1 DC to 2 Mbps V Supply Current I 0.9 1.7 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.4 0.7 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V Supply Current I 3.4 4.9 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 1.1 1.6 mA 5 MHz logic signal freq. DD2 DD2 (10) 90 Mbps (CRW Grade Only) V Supply Current I 31 48 mA 45 MHz logic signal freq. DD1 DD1 (90) V Supply Current I 8 13 mA 45 MHz logic signal freq. DD2 DD2 (90) ADuM1301 Total Supply Current, Three Channels1 DC to 2 Mbps V Supply Current I 0.7 1.4 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.6 0.9 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (BRW and CRW Grades Only) V Supply Current I 2.6 3.7 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 1.8 2.5 mA 5 MHz logic signal freq. DD2 DD2 (10) 90 Mbps (CRW Grade Only) V Supply Current I 24 36 mA 45 MHz logic signal freq. DD1 DD1 (90) V Supply Current I 16 23 mA 45 MHz logic signal freq. DD2 DD2 (90) For All Models Input Currents I , I , I , I , I −10 +0.01 +10 µA 0 V ≤ V , V , V ≤ V or V , IA IB IC E1 E2 IA IB IC DD1 DD2 0 V ≤ V , V ≤ V or V E1 E2 DD1 DD2 Logic High Input Threshold V , V 1.6 V IH EH Logic Low Input Threshold V , V 0.4 V IL EL Logic High Output Voltages V , V , V (V or V ) − 0.1 3.0 V I = −20 µA, V = V OAH OBH OCH DD1 DD2 Ox Ix IxH (V or V ) − 0.4 2.8 V I = −4 mA, V = V DD1 DD2 Ox Ix IxH Logic Low Output Voltages V , V , V 0.0 0.1 V I = 20 µA, V = V OAL OBL OCL Ox Ix IxL 0.04 0.1 V I = 400 µA, V = V Ox Ix IxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ADuM1300ARW/ADuM1301ARW Minimum Pulse Width2 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 50 75 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 11 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching6 t /t 50 ns C = 15 pF, CMOS signal levels PSKCD PSKOD L Rev. K | Page 6 of 32

Data Sheet ADuM1300/ADuM1301 Parameter Symbol Min Typ Max Unit Test Conditions ADuM1300BRW/ADuM1301BRW Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 20 38 50 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 tPSK 26 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional t 3 ns C = 15 pF, CMOS signal levels PSKCD L Channels6 Channel-to-Channel Matching, Opposing- t 6 ns C = 15 pF, CMOS signal levels PSKOD L Directional Channels6 ADuM1300CRW/ADuM1301CRW Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 20 34 45 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 3 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 tPSK 16 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional t 2 ns C = 15 pF, CMOS signal levels PSKCD L Channels6 Channel-to-Channel Matching, Opposing- t 5 ns C = 15 pF, CMOS signal levels PSKOD L Directional Channels6 For All Models Output Disable Propagation Delay (High/Low to t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L High Impedance) Output Enable Propagation Delay (High t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L Impedance to High/Low) Output Rise/Fall Time (10% to 90%) t/t 3 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity at |CMH| 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V, Logic High Output7 transient magnitude = 800 V Common-Mode Transient Immunity at |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM Logic Low Output7 transient magnitude = 800 V Refresh Rate f 1.1 Mbps r Input Dynamic Supply Current per Channel8 I 0.10 mA/Mbps DDI (D) Output Dynamic Supply Current per Channel8 IDDO (D) 0.03 mA/Mbps 1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. K | Page 7 of 32

ADuM1300/ADuM1301 Data Sheet ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ V ≤ 5.5 V, 2.7 V ≤ V ≤ 3.6 V; 3 V/5 V operation: DD1 DD2 2.7 V ≤ V ≤ 3.6 V, 4.5 V ≤ V ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, DD1 DD2 unless otherwise noted; all typical specifications are at T = 25°C; V = 3.0 V, V = 5 V or V = 5 V, V = 3.0 V. These specifica- A DD1 DD2 DD1 DD2 tions do not apply to ADuM1300W and ADuM1301W automotive grade versions. Table 3. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I DDI (Q) 5 V/3 V Operation 0.50 0.53 mA 3 V/5 V Operation 0.26 0.31 mA Output Supply Current per Channel, Quiescent I DDO (Q) 5 V/3 V Operation 0.11 0.15 mA 3 V/5 V Operation 0.19 0.24 mA ADuM1300 Total Supply Current, Three Channels1 DC to 2 Mbps V Supply Current I DD1 DD1 (Q) 5 V/3 V Operation 1.6 2.5 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.9 1.7 mA DC to 1 MHz logic signal freq. V Supply Current I DD2 DD2 (Q) 5 V/3 V Operation 0.4 0.7 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.7 1.0 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) V Supply Current I DD1 DD1 (10) 5 V/3 V Operation 6.5 8.1 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.4 4.9 mA 5 MHz logic signal freq. V Supply Current I DD2 DD2 (10) 5 V/3 V Operation 1.1 1.6 mA 5 MHz logic signal freq. 3 V/5 V Operation 1.9 2.5 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) V Supply Current I DD1 DD1 (90) 5 V/3 V Operation 57 77 mA 45 MHz logic signal freq. 3 V/5 V Operation 31 48 mA 45 MHz logic signal freq. V Supply Current I DD2 DD2 (90) 5 V/3 V Operation 8 13 mA 45 MHz logic signal freq. 3 V/5 V Operation 16 18 mA 45 MHz logic signal freq. ADuM1301 Total Supply Current, Three Channels1 DC to 2 Mbps V Supply Current I DD1 DD1 (Q) 5 V/3 V Operation 1.3 2.1 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.7 1.4 mA DC to 1 MHz logic signal freq. V Supply Current I DD2 DD2 (Q) 5 V/3 V Operation 0.6 0.9 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.0 1.4 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) V Supply Current I DD1 DD1 (10) 5 V/3 V Operation 5.0 6.2 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.6 3.7 mA 5 MHz logic signal freq. V Supply Current I DD2 DD2 (10) 5 V/3 V Operation 1.8 2.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.4 4.2 mA 5 MHz logic signal freq. Rev. K | Page 8 of 32

Data Sheet ADuM1300/ADuM1301 Parameter Symbol Min Typ Max Unit Test Conditions 90 Mbps (CRW Grade Only) V Supply Current I DD1 DD1 (90) 5 V/3 V Operation 43 57 mA 45 MHz logic signal freq. 3 V/5 V Operation 24 36 mA 45 MHz logic signal freq. V Supply Current I DD2 DD2 (90) 5 V/3 V Operation 16 23 mA 45 MHz logic signal freq. 3 V/5 V Operation 29 37 mA 45 MHz logic signal freq. For All Models Input Currents I , I , I , I , I −10 +0.01 +10 µA 0 V ≤ V , V , V ≤ V or V , IA IB IC E1 E2 IA IB IC DD1 DD2 0 V ≤ V , V ≤ V or V E1 E2 DD1 DD2 Logic High Input Threshold V , V IH EH 5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V Logic Low Input Threshold V , V IL EL 5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V Logic High Output Voltages V , V , V (V or V ) − 0.1 (V or V ) V I = −20 µA, V = V OAH OBH OCH DD1 DD2 DD1 DD2 Ox Ix IxH (V or V ) − 0.4 (V or V ) − 0.2 V I = −4 mA, V = V DD1 DD2 DD1 DD2 Ox Ix IxH Logic Low Output Voltages V , V , V 0.0 0.1 V I = 20 µA, V = V OAL OBL OCL Ox Ix IxL 0.04 0.1 V I = 400 µA, V = V Ox Ix IxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ADuM1300ARW/ADuM1301ARW Minimum Pulse Width2 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 50 70 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 11 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching6 t /t 50 ns C = 15 pF, CMOS signal levels PSKCD PSKOD L ADuM1300BRW/ADuM1301BRW Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 15 35 50 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 tPSK 6 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional t 3 ns C = 15 pF, CMOS signal levels PSKCD L Channels6 Channel-to-Channel Matching, Opposing- t 22 ns C = 15 pF, CMOS signal levels PSKOD L Directional Channels6 ADuM1300CRW/ADuM1301CRW Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 3 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 tPSK 14 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, t 2 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 5 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 Rev. K | Page 9 of 32

ADuM1300/ADuM1301 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions For All Models Output Disable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L (High/Low to High Impedance) Output Enable Propagation Delay (High t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L Impedance to High/Low) Output Rise/Fall Time (10% to 90%) t/t C = 15 pF, CMOS signal levels R F L 5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns Common-Mode Transient Immunity at |CM | 25 35 kV/µs V = V or V , V = 1000 V, H Ix DD1 DD2 CM Logic High Output7 transient magnitude = 800 V Common-Mode Transient Immunity at |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM Logic Low Output7 transient magnitude = 800 V Refresh Rate f r 5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps Input Dynamic Supply Current per Channel8 I DDI (D) 5 V/3 V Operation 0.19 mA/Mbps 3 V/5 V Operation 0.10 mA/Mbps Output Dynamic Supply Current per Channel8 IDDO (D) 5 V/3 V Operation 0.03 mA/Mbps 3 V/5 V Operation 0.05 mA/Mbps 1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. K | Page 10 of 32

Data Sheet ADuM1300/ADuM1301 ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION All voltages are relative to their respective ground. 4.5 V ≤ V ≤ 5.5 V, 4.5 V ≤ V ≤ 5.5 V; all minimum/maximum specifications apply DD1 DD2 over the entire recommended operation range, unless otherwise noted; all typical specifications are at T = 25°C, V = V = 5 V. These A DD1 DD2 specifications apply to ADuM1300W and ADuM1301W automotive grade versions. Table 4. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I 0.50 0.53 mA DDI (Q) Output Supply Current per Channel, Quiescent I 0.19 0.24 mA DDO (Q) ADuM1300W, Total Supply Current, Three Channels1 DC to 2 Mbps V Supply Current I 1.6 2.5 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.7 1.0 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 6.5 8.1 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 1.9 2.5 mA 5 MHz logic signal freq. DD2 DD2 (10) ADuM1301W, Total Supply Current, Three Channels1 DC to 2 Mbps V Supply Current I 1.3 2.1 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 1.0 1.4 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 5.0 6.2 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 3.4 4.2 mA 5 MHz logic signal freq. DD2 DD2 (10) For All Models Input Currents I , I , I , I , I −10 +0.01 +10 µA 0 V ≤ V , V , V ≤ V or V , IA IB IC E1 E2 IA IB IC DD1 DD2 0 V ≤ V , V ≤ V or V E1 E2 DD1 DD2 Logic High Input Threshold V , V 2.0 V IH EH Logic Low Input Threshold V , V 0.8 V IL EL Logic High Output Voltages V , V , V V , V − 0.1 5.0 V I = −20 µA, V = V OAH OBH OCH DD1 DD2 Ox Ix IxH V , V − 0.4 4.8 V I = −4 mA, V = V DD1 DD2 Ox Ix IxH Logic Low Output Voltages V , V , V 0.0 0.1 V I = 20 µA, V = V OAL OBL OCL Ox Ix IxL 0.04 0.1 V I = 400 µA, V = V Ox Ix IxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ADuM1300WSRWZ/ADuM1301WSRWZ Minimum Pulse Width2 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 50 65 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 40 ns C = 15 pF, CMOS signal levels PLH PHL L Propagation Delay Skew5 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching6 t /t 50 ns C = 15 pF, CMOS signal levels PSKCD PSKOD L ADuM1300WTRWZ/ADuM1301WTRWZ Minimum Pulse Width2 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 18 27 32 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 15 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, Codirectional t 3 ns C = 15 pF, CMOS signal levels PSKCD L Channels6 Channel-to-Channel Matching, Opposing- t 6 ns C = 15 pF, CMOS signal levels PSKOD L Directional Channels6 Rev. K | Page 11 of 32

ADuM1300/ADuM1301 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions For All Models Output Disable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L (High/Low to High Impedance) Output Enable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L (High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) t/t 2.5 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity at Logic |CM | 25 35 kV/µs V = V /V , V = 1000 V, H Ix DD1 DD2 CM High Output7 transient magnitude = 800 V Common-Mode Transient Immunity at Logic |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM Low Output7 transient magnitude = 800 V Refresh Rate f 1.2 Mbps r Input Dynamic Supply Current per Channel8 I 0.19 mA/Mbps DDI (D) Output Dynamic Supply Current per Channel8 I 0.05 mA/Mbps DDO (D) 1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. K | Page 12 of 32

Data Sheet ADuM1300/ADuM1301 ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION All voltages are relative to their respective ground. 3.0 V ≤ V ≤ 3.6 V, 3.0 V ≤ V ≤ 3.6 V; all minimum/maximum specifications apply DD1 DD2 over the entire recommended operation range, unless otherwise noted; all typical specifications are at T = 25°C, V = V = 3.0 V. A DD1 DD2 These specifications apply to ADuM1300W and ADuM1301W automotive grade versions. Table 5. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I 0.26 0.31 mA DDI (Q) Output Supply Current per Channel, Quiescent I 0.11 0.15 mA DDO (Q) ADuM1300W, Total Supply Current, Three Channels1 DC to 2 Mbps V Supply Current I 0.9 1.7 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.4 0.7 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 3.4 4.9 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 1.1 1.6 mA 5 MHz logic signal freq. DD2 DD2 (10) ADuM1301W, Total Supply Current, Three Channels1 DC to 2 Mbps V Supply Current I 0.7 1.4 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.6 0.9 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 2.6 3.7 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 1.8 2.5 mA 5 MHz logic signal freq. DD2 DD2 (10) For All Models Input Currents I , I , I , I , I −10 +0.01 +10 µA 0 V ≤ V , V , V ≤ V or V , IA IB IC E1 E2 IA IB IC DD1 DD2 0 V ≤ V , V ≤ V or V E1 E2 DD1 DD2 Logic High Input Threshold V , V 1.6 V IH EH Logic Low Input Threshold V , V 0.4 V IL EL Logic High Output Voltages V , V , V V , V − 0.1 3.0 V I = −20 µA, V = V OAH OBH OCH DD1 DD2 Ox Ix IxH V , V − 0.4 2.8 V I = −4 mA, V = V DD1 DD2 Ox Ix IxH Logic Low Output Voltages V , V , V 0.0 0.1 V I = 20 µA, V = V OAL OBL OCL Ox Ix IxL 0.04 0.1 V I = 400 µA, V = V Ox Ix IxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ADuM1300WSRWZ/ADuM1301WSRWZ Minimum Pulse Width2 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 50 75 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching6 t /t 50 ns C = 15 pF, CMOS signal levels PSKCD PSKOD L ADuM1300WTRWZ/ADuM1301WTRWZ Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 20 34 45 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 tPSK 26 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, t 3 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 6 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 Rev. K | Page 13 of 32

ADuM1300/ADuM1301 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions For All Models Output Disable Propagation Delay (High/Low to t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L High Impedance) Output Enable Propagation Delay (High Impedance t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L to High/Low) Output Rise/Fall Time (10% to 90%) t/t 3 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity at |CM | 25 35 kV/µs V = V /V , V = 1000 V, H Ix DD1 DD2 CM Logic High Output7 transient magnitude = 800 V Common-Mode Transient Immunity at |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM Logic Low Output7 transient magnitude = 800 V Refresh Rate f 1.1 Mbps r Input Dynamic Supply Current per Channel8 I 0.10 mA/Mbps DDI (D) Output Dynamic Supply Current per Channel8 IDDO (D) 0.03 mA/Mbps 1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. K | Page 14 of 32

Data Sheet ADuM1300/ADuM1301 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION1 All voltages are relative to their respective ground. 4.5 V ≤ V ≤ 5.5 V, 3.0 V ≤ V ≤ 3.6 V; all minimum/maximum specifications apply DD1 DD2 over the entire recommended operation range, unless otherwise noted; all typical specifications are at T = 25°C; V = 5 V, V = 3.0 V. A DD1 DD2 These specifications apply to ADuM1300W and ADuM1301W automotive grade versions. Table 6. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I 0.50 0.53 mA DDI (Q) Output Supply Current per Channel, Quiescent I 0.11 0.15 mA DDO (Q) ADuM1300W, Total Supply Current, Three Channels2 DC to 2 Mbps V Supply Current I 1.6 2.5 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.4 0.7 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 6.5 8.1 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 1.1 1.6 mA 5 MHz logic signal freq. DD2 DD2 (10) ADuM1301W, Total Supply Current, Three Channels1 DC to 2 Mbps V Supply Current I 1.3 2.1 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.6 0.9 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 5.0 6.2 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 1.8 2.5 mA 5 MHz logic signal freq. DD2 DD2 (10) For All Models Input Currents I , I , I , I , I −10 +0.01 +10 μA 0 V ≤ V , V , V ≤ V or V , IA IB IC E1 E2 IA IB IC DD1 DD2 0 V ≤ V , V ≤ V or V E1 E2 DD1 DD2 Logic High Input Threshold V , V 2.0 V IH EH Logic Low Input Threshold V , V 0.8 V IL EL Logic High Output Voltages V , V , V V , V − 0.1 V , V V I = −20 μA, V = V OAH OBH OCH DD1 DD2 DD1 DD2 Ox Ix IxH V , V − 0.4 V , V I = −4 mA, V = V DD1 DD2 DD1 Ox Ix IxH V − 0.2 DD2 Logic Low Output Voltages V , V , V 0.0 0.1 V I = 20 μA, V = V OAL OBL OCL Ox Ix IxL 0.04 0.1 V I = 400 μA, V = V Ox Ix IxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ADuM1300WSRWZ/ADuM1301WSRWZ Minimum Pulse Width3 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate4 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay5 t , t 50 70 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching7 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels ADuM1300WTRWZ/ADuM1301WTRWZ Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 tPSK 6 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional t 3 ns C = 15 pF, CMOS signal levels PSKCD L Channels6 Channel-to-Channel Matching, Opposing- t 22 ns C = 15 pF, CMOS signal levels PSKOD L Directional Channels6 Rev. K | Page 15 of 32

ADuM1300/ADuM1301 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions For All Models Output Disable Propagation Delay (High/Low t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L to High Impedance) Output Enable Propagation Delay (High t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L Impedance to High/Low) Output Rise/Fall Time (10% to 90%) t/t 3.0 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity at |CM | 25 35 kV/µs V = V /V , V = 1000 V, H Ix DD1 DD2 CM Logic High Output8 transient magnitude = 800 V Common-Mode Transient Immunity at |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM Logic Low Output7 transient magnitude = 800 V Refresh Rate f 1.2 Mbps r Input Dynamic Supply Current per Channel9 I 0.19 mA/Mbps DDI (D) Output Dynamic Supply Current per Channel8 IDDO (D) 0.03 mA/Mbps 1 All voltages are relative to their respective ground. 2 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. K | Page 16 of 32

Data Sheet ADuM1300/ADuM1301 ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION All voltages are relative to their respective ground. 3.0 V ≤ V ≤ 3.6 V, 4.5 V ≤ V ≤ 5.5 V; all minimum/maximum specifications apply DD1 DD2 over the entire recommended operation range, unless otherwise noted; all typical specifications are at T = 25°C; V = 3.0 V, V = 5 V. A DD1 DD2 These apply to ADuM1300W and ADuM1301W automotive grade versions. Table 7. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I 0.26 0.31 mA DDI (Q) Output Supply Current per Channel, Quiescent I 0.19 0.24 mA DDO (Q) ADuM1300W, Total Supply Current, Three Channels1 DC to 2 Mbps V Supply Current I 0.9 1.7 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 0.7 1.0 mA DC to 1 MHz logic signal freq. DD2 DD2(Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 3.4 4.9 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 1.9 2.5 mA 5 MHz logic signal freq. DD2 DD2 (10) ADuM1301W, Total Supply Current, Three Channels1 DC to 2 Mbps V Supply Current I 0.7 1.4 mA DC to 1 MHz logic signal freq. DD1 DD1 (Q) V Supply Current I 1.0 1.4 mA DC to 1 MHz logic signal freq. DD2 DD2 (Q) 10 Mbps (TRWZ Grade Only) V Supply Current I 2.6 3.7 mA 5 MHz logic signal freq. DD1 DD1 (10) V Supply Current I 3.4 4.2 mA 5 MHz logic signal freq. DD2 DD2 (10) For All Models Input Currents I , I , I , I , I −10 +0.01 +10 μA 0 V ≤ V , V , V ≤ V or V , IA IB IC E1 E2 IA IB IC DD1 DD2 0 V ≤ V , V ≤ V or V E1 E2 DD1 DD2 Logic High Input Threshold V , V 1.6 V IH EH Logic Low Input Threshold V , V 0.4 V IL EL Logic High Output Voltages V , V , V V , V − 0.1 V , V V I = −20 μA, V = V OAH OBH OCH DD1 DD2 DD1 DD2 Ox Ix IxH V , V − 0.4 V , V I = −4 mA, V = V DD1 DD2 DD1 Ox Ix IxH V − 0.2 DD2 Logic Low Output Voltages V , V , V 0.0 0.1 V I = 20 μA, V = V OAL OBL OCL Ox Ix IxL 0.04 0.1 V I = 400 μA, V = V Ox Ix IxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS ADuM1300WSRWZ/ADuM1301WSRWZ Minimum Pulse Width2 PW 1000 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 50 70 100 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t 50 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching6 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels ADuM1300WTRWZ/ADuM1301WTRWZ Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 tPSK 6 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional t 3 ns C = 15 pF, CMOS signal levels PSKCD L Channels6 Channel-to-Channel Matching, Opposing- t 22 ns C = 15 pF, CMOS signal levels PSKOD L Directional Channels6 Rev. K | Page 17 of 32

ADuM1300/ADuM1301 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions For All Models Output Disable Propagation Delay (High/Low t , t 6 8 ns C = 15 pF, CMOS signal levels PHZ PLH L to High Impedance) Output Enable Propagation Delay t , t 6 8 ns C = 15 pF, CMOS signal levels PZH PZL L (High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) t/t C = 15 pF, CMOS signal levels R F L 5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns Common-Mode Transient Immunity at Logic |CM | 25 35 kV/µs V = V /V , V = 1000 V, H Ix DD1 DD2 CM High Output7 transient magnitude = 800 V Common-Mode Transient Immunity at Logic |CM| 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM Low Output7 transient magnitude = 800 V Refresh Rate f 1.1 Mbps r Input Dynamic Supply Current per Channel8 I 0.10 mA/Mbps DDI (D) Output Dynamic Supply Current per Channel8 IDDO (D) 0.05 mA/Mbps 1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300W/ADuM1301W channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. K | Page 18 of 32

Data Sheet ADuM1300/ADuM1301 PACKAGE CHARACTERISTICS Table 8. Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input-to-Output)1 R 1012 Ω I-O Capacitance (Input-to-Output)1 C 1.7 pF f = 1 MHz I-O Input Capacitance2 C 4.0 pF I IC Junction-to-Case Thermal Resistance, Side 1 θ 33 °C/W Thermocouple located at center of JCI package underside IC Junction-to-Case Thermal Resistance, Side 2 θ 28 °C/W JCO 1 Device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, and Pin 16 are shorted together. 2 Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM1300/ADuM1301 are approved by the organizations listed in Table 9. Refer to Table 14 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels. Table 9. UL CSA CQC VDE TÜV Recognized Approved under Approved under Certified according Approved according to Under 1577 CSA Component CQC11-471543-2012 to DIN V VDE V 0884-10 IEC 61010-1:2001 (2nd Edition), Component Acceptance Notice 5A (VDE V 0884-10):2006-122 EN 61010-1:2001 (2nd Edition), Recognition UL 61010-1:2004 CSA Program1 C22.2.61010.1:2005 Single Protection, Basic insulation per Basic insulation per Reinforced insulation, Reinforced insulation, 400 V rms 2500 V rms CSA 60950-1-03 and GB4943.1-2011 560 V peak maximum working voltage Isolation IEC 60950-1, 800 V rms Voltage (1131 V peak) maximum working voltage Reinforced insulation per Basic insulation, CSA 60950-1-03 and 415 V rms (588 V peak) IEC 60950-1, 400 V rms maximum working (566 V peak) maximum voltage, tropical climate, working voltage altitude ≤ 5000 m File E214100 File 205078 File: CQC14001114900 File 2471900-4880-0001 Certificate U8V 05 06 56232 002 1 In accordance with UL 1577, each ADuM1300/ADuM1301 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA). 2 In accordance with DIN V VDE V 0884-10, each ADuM1300/ADuM1301 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 10. Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 7.7 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 8.1 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1 Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1) Rev. K | Page 19 of 32

ADuM1300/ADuM1301 Data Sheet DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage. Table 11. Description Conditions Symbol Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V 560 V peak IORM Input-to-Output Test Voltage, Method B1 V × 1.875 = V , 100% production test, t = 1 sec, V 1050 V peak IORM PR m PR partial discharge < 5 pC Input-to-Output Test Voltage, Method A V × 1.6 = V , t = 60 sec, partial discharge < 5 pC V IORM PR m PR After Environmental Tests Subgroup 1 896 V peak After Input and/or Safety Test Subgroup 2 V × 1.2 = V , t = 60 sec, partial discharge < 5 pC 672 V peak IORM PR m and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, t = 10 seconds V 4000 V peak TR TR Safety-Limiting Values Maximum value allowed in the event of a failure (see Figure 3) Case Temperature T 150 °C S Side 1 Current I 265 mA S1 Side 2 Current I 335 mA S2 Insulation Resistance at T V = 500 V R >109 Ω S IO S 350 RECOMMENDED OPERATING CONDITIONS 300 Table 12. A) m Parameter Rating T ( 250 EN SIDE #2 Operating Temperature (TA)1 −40°C to +105°C R UR 200 Operating Temperature (TA)2 −40°C to +125°C C G Supply Voltages (VDD1, VDD2)1, 3 2.7 V to 5.5 V N MITI 150 SIDE #1 Supply Voltages (VDD1, VDD2) 2, 3 3.0 V to 5.5 V LI Input Signal Rise and Fall Times 1.0 ms Y- 100 ET AF 1 Does not apply to ADuM1300W and ADuM1301W automotive grade versions. S 50 2 Applies to ADuM1300W and ADuM1301W automotive grade versions. 3 All voltages are relative to their respective ground. See the DC Correctness 00 50CASE TEMP1E0R0ATURE (°C)150 200 03787-003 amnadg Mnaegtince ftiiecl dFise.l d Immunity section for information on immunity to external Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. K | Page 20 of 32

Data Sheet ADuM1300/ADuM1301 ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 13. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational Storage Temperature (T ) −65°C to +150°C ST section of this specification is not implied. Operation beyond Ambient Operating Temperature (T)1 −40°C to +105°C A the maximum operating conditions for extended periods may Ambient Operating Temperature (T)2 −40°C to +125°C A affect product reliability. Supply Voltages (V , V )3 −0.5 V to +7.0 V DD1 DD2 Input Voltage (VIA, VIB, VIC, VE1, VE2)3, 4 −0.5 V to VDDI + 0.5 V ESD CAUTION Output Voltage (V , V , V )3, 4 −0.5 V to V + 0.5 V OA OB OC DDO Average Output Current per Pin5 Side 1 (I ) −23 mA to +23 mA O1 Side 2 (I ) −30 mA to +30 mA O2 Common-Mode Transients6 −100 kV/µs to +100 kV/µs 1 Does not apply to ADuM1300W and ADuM1301W automotive grade versions. 2 Applies to ADuM1300W and ADuM1301W automotive grade versions. 3 All voltages are relative to their respective ground. 4 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the Printed Circuit Board (PCB) Layout section. 5 See Figure 3 for maximum rated current values for various temperatures. 6 This refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Ratings may cause latch-up or permanent damage. Table 14. Maximum Continuous Working Voltage1 Parameter Max Unit Constraint AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime AC Voltage, Unipolar Waveform Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 DC Voltage Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Table 15. Truth Table (Positive Logic) V Input1 V Input1, 2 V State1 V State1 V Output1 Notes Ix Ex DDI DDO Ox H H or NC Powered Powered H L H or NC Powered Powered L X L Powered Powered Z X H or NC Unpowered Powered H Outputs return to the input state within 1 µs of V power restoration. DDI X L Unpowered Powered Z X X Powered Unpowered Indeterminate Outputs return to the input state within 1 µs of V power restoration DDO if the V state is H or NC. Outputs return to a high impedance state Ex within 8 ns of V power restoration if the V state is L. DDO Ex 1 VIx and VOx refer to the input and output signals of a given channel (A, B, or C). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively. 2 In noisy environments, connecting VEx to an external logic high or low is recommended. Rev. K | Page 21 of 32

ADuM1300/ADuM1301 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1 1 16 VDD2 VDD1 1 16 VDD2 *GND1 2 15 GND2* *GND1 2 15 GND2* VIA 3 ADuM1300 14 VOA VIA 3 ADuM1301 14 VOA VIB 4 TOP VIEW 13 VOB VIB 4 TOP VIEW 13 VOB VIC 5 (Not to Scale) 12 VOC VOC 5 (Not to Scale) 12 VIC NC 6 11 NC NC 6 11 NC NC 7 10 VE2 VE1 7 10 VE2 *GND1 8NC = NO CONNEC9T GND2* 03787-004 *GND1 8NC = NO CONNECT9 GND2* 03787-005 *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED. CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED. Figure 4. ADuM1300 Pin Configuration Figure 5. ADuM1301 Pin Configuration Table 16. ADuM1300 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage for Isolator Side 1. DD1 2 GND Ground 1. Ground reference for Isolator Side 1. 1 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Input C. IC 6 NC No Connect. 7 NC No Connect. 8 GND Ground 1. Ground reference for Isolator Side 1. 1 9 GND Ground 2. Ground reference for Isolator Side 2. 2 10 V Output Enable 2. Active high logic input. V , V , and V outputs are enabled when V is high or disconnected. V , V , and V E2 OA OB OC E2 OA OB OC outputs are disabled when V is low. In noisy environments, connecting V to an external logic high or low is recommended. E2 E2 11 NC No Connect. 12 V Logic Output C. OC 13 V Logic Output B. OB 14 V Logic Output A. OA 15 GND Ground 2. Ground reference for Isolator Side 2. 2 16 V Supply Voltage for Isolator Side 2. DD2 Table 17. ADuM1301 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage for Isolator Side 1. DD1 2 GND Ground 1. Ground reference for Isolator Side 1. 1 3 V Logic Input A. IA 4 V Logic Input B. IB 5 V Logic Output C. OC 6 NC No Connect. 7 V Output Enable 1. Active high logic input. V output is enabled when V is high or disconnected. V output is disabled when V is E1 OC E1 OC E1 low. In noisy environments, connecting V to an external logic high or low is recommended. E1 8 GND Ground 1. Ground reference for Isolator Side 1. 1 9 GND Ground 2. Ground reference for Isolator Side 2. 2 10 V Output Enable 2. Active high logic input. V and V outputs are enabled when V is high or disconnected. V and V outputs are E2 OA OB E2 OA OB disabled when V is low. In noisy environments, connecting V to an external logic high or low is recommended. E2 E2 11 NC No Connect. 12 V Logic Input C. IC 13 V Logic Output B. OB 14 V Logic Output A. OA 15 GND Ground 2. Ground reference for Isolator Side 2. 2 16 V Supply Voltage for Isolator Side 2. DD2 Rev. K | Page 22 of 32

Data Sheet ADuM1300/ADuM1301 TYPICAL PERFORMANCE CHARACTERISTICS 20 60 18 50 16 mA) 14 40 NT/CHANNEL ( 11208 5V URRENT (mA) 30 5V RRE 6 C 20 U 3V C 3V 4 10 2 00 20 DA4T0A RATE (Mb60ps) 80 100 03787-008 00 20 DA4T0A RATE (Mb60ps) 80 100 03787-011 Figure 6. Typical Input Supply Current per Channel vs. Data Rate Figure 9. Typical ADuM1300 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation for 5 V and 3 V Operation 6 16 14 5 12 A) m 4 NEL ( mA) 10 NT/CHAN 3 5V URRENT ( 86 5V RE 2 C 3V R CU 3V 4 1 2 00 20 DA4T0A RATE (Mb60ps) 80 100 03787-009 00 20 DA4T0A RATE (Mb60ps) 80 100 03787-012 Figure 7. Typical Output Supply Current per Channel vs. Data Rate Figure 10. Typical ADuM1300 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation (No Output Load) for 5 V and 3 V Operation 10 50 9 45 8 40 A) 7 35 m NEL ( 6 mA) 30 RRENT/CHAN 543 5V CURRENT ( 122550 5V 3V CU 3V 2 10 1 5 00 20 DA4T0A RATE (Mb60ps) 80 100 03787-010 00 20 DA4T0A RATE (Mb60ps) 80 100 03787-013 Figure 8. Typical Output Supply Current per Channel vs. Data Rate Figure 11. Typical ADuM1301 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load) for 5 V and 3 V Operation Rev. K | Page 23 of 32

ADuM1300/ADuM1301 Data Sheet 30 40 25 s) 3V n 20 Y ( 35 mA) ELA RRENT ( 15 5V ATION D U G C 10 A 30 3V OP R P 5 5V 00 20 DA4T0A RATE (Mb60ps) 80 100 03787-014 25–50 –25 0TEMPERA2T5URE (°C)50 75 100 03787-019 Figure 12. Typical ADuM1301 VDD2 Supply Current vs. Data Rate Figure 13. Propagation Delay vs. Temperature, C Grade for 5 V and 3 V Operation Rev. K | Page 24 of 32

Data Sheet ADuM1300/ADuM1301 APPLICATIONS INFORMATION PRINTED CIRCUIT BOARD (PCB) LAYOUT DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY The ADuM1300/ADuM1301 digital isolator requires no external Positive and negative logic transitions at the isolator input cause interface circuitry for the logic interfaces. Power supply bypassing is narrow (approximately 1 ns) pulses to be sent to the decoder via strongly recommended at the input and output supply pins (see the transformer. The decoder is bistable and is therefore either Figure 14). Bypass capacitors are most conveniently connected set or reset by the pulses, indicating input logic transitions. In between Pin 1 and Pin 2 for V and between Pin 15 and Pin 16 the absence of logic transitions at the input for more than DD1 approximately 1 μs, a periodic set of refresh pulses indicative of for V . The capacitor value should be between 0.01 μF and 0.1 μF. DD2 the correct input state are sent to ensure dc correctness at the The total lead length between both ends of the capacitor and output. If the decoder receives no internal pulses for more than the input power supply pin should not exceed 20 mm. Bypassing about 5 μs, the input side is assumed to be unpowered or between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should nonfunctional, in which case the isolator output is forced to also be considered unless the ground pair on each package side a default state (see Table 15) by the watchdog timer circuit. is connected close to the package. The ADuM1300/ADuM1301 is extremely immune to external VDD1 VDD2 GND1 GND2 magnetic fields. The limitation on the magnetic field immunity VIA VOA of the ADuM1300/ADuM1301 is set by the condition in which VIB VOB VIC/VOC VOC/VIC induced voltage in the receiving coil of the transformer is NC NC NCG/NVDE11 VGEN2D2 03787-015 sTuhfefi cfoiellnotwlyi nlagr gaen eanlyosuisg hd etofi neietsh ethr efa clsoenlyd siteito onrs r uesnedt etrh ew dheiccohd tehri. s Figure 14. Recommended Printed Circuit Board Layout may occur. The 3 V operating condition of the ADuM1300/ In applications involving high common-mode transients, ADuM1301 is examined because it represents the most take care to ensure that board coupling across the isolation susceptible mode of operation. barrier is minimized. Furthermore, the board layout should be The pulses at the transformer output have an amplitude greater designed such that any coupling that does occur equally affects than 1.0 V. The decoder has a sensing threshold at about 0.5 V, all pins on a given component side. Failure to ensure this could thus establishing a 0.5 V margin in which induced voltages can be cause voltage differentials between pins exceeding the absolute tolerated. The voltage induced across the receiving coil is given by maximum ratings of the device, thereby leading to latch-up or V = (−dβ/dt)∑∏r2; n = 1, 2, … , N permanent damage. n where: See the AN-1109 Application Note for board layout guidelines. β is magnetic flux density (gauss). PROPAGATION DELAY-RELATED PARAMETERS N is the number of turns in the receiving coil. Propagation delay is a parameter that describes the time it takes rn is the radius of the nth turn in the receiving coil (cm). a logic signal to propagate through a component. The propagation Given the geometry of the receiving coil in the ADuM1300/ delay to a logic low output may differ from the propagation ADuM1301 and an imposed requirement that the induced delay to a logic high output. voltage be 50% at most of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in INPUT (VIx) 50% Figure 16. tPLH tPHL 100 OUTPUT (VOx) Figure 15. Propagation Delay Parameters5 0% 03787-016 TIC FLUX 10 E N Pulse width distortion is the maximum difference between AGss) these two propagation delay values and is an indication of E Mgau 1 Lk how accurately the timing of the input signal is preserved. ABY ( Cthhaat nthnee lp-troo-pcahgaantinoenl mdealtacyh dinifgf erresf ebrest wtoe tehne c mhaanxnimelus mw iathmino uan t M ALLOWDENSIT0.1 U single ADuM1300/ADuM1301 component. XIM 0.01 A Propagation delay skew refers to the maximum amount that the M propagation delay differs between multiple ADuM1300/ ADuM1301 components operating under the same conditions. 0.0011k 10kMAGNETI1C0 0FkIELD FREQ1MUENCY (Hz1)0M 100M 03787-017 Figure 16. Maximum Allowable External Magnetic Flux Density Rev. K | Page 25 of 32

ADuM1300/ADuM1301 Data Sheet For example, at a magnetic field frequency of 1 MHz, the POWER CONSUMPTION maximum allowable magnetic field of 0.2 kgauss induces a The supply current at a given channel of the ADuM1300/ voltage of 0.25 V at the receiving coil. This is about 50% of the ADuM1301 isolator is a function of the supply voltage, the data sensing threshold and does not cause a faulty output transition. rate of the channel, and the output load of the channel. Similarly, if such an event occurs during a transmitted pulse For each input channel, the supply current is given by (and has the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing I = I f ≤ 0.5 f DDI DDI (Q) r threshold of the decoder. I = I × (2f − f) + I f > 0.5 f DDI DDI (D) r DDI (Q) r The preceding magnetic flux density values correspond to For each output channel, the supply current is given by specific current magnitudes at given distances from the I = I f ≤ 0.5 f ADuM1300/ADuM1301 transformers. Figure 17 shows these DDO DDO (Q) r allowable current magnitudes as a function of frequency for I = (I + (0.5 × 10−3) × C × V ) × (2f − f) + I DDO DDO (D) L DDO r DDO (Q) selected distances. The ADuM1300/ADuM1301 is extremely f > 0.5 f r immune and can be affected only by extremely large currents where: operated at a high frequency very close to the component. For I , I are the input and output dynamic supply currents DDI (D) DDO (D) the 1 MHz example noted, one would have to place a 0.5 kA per channel (mA/Mbps). current 5 mm away from the ADuM1300/ADuM1301 to affect C is the output load capacitance (pF). L the operation of the component. V is the output supply voltage (V). DDO 1000 f is the input logic signal frequency (MHz); it is half of the input A) DISTANCE = 1m data rate expressed in units of Mbps. k NT ( 100 fr is the input stage refresh rate (Mbps). RRE IDDI (Q), IDDO (Q) are the specified input and output quiescent CU supply currents (mA). E 10 L B To calculate the total V and V supply current, the supply A DISTANCE = 100mm DD1 DD2 W O currents for each input and output channel corresponding to L 1 AL VDD1 and VDD2 are calculated and totaled. Figure 6 and Figure 7 M DISTANCE = 5mm U provide per-channel supply currents as a function of data rate M XI 0.1 for an unloaded output condition. Figure 8 provides per-channel A M supply current as a function of data rate for a 15 pF output 0.01 condition. Figure 9 through Figure 12 provide total VDD1 and 1k 10MkAGNET1IC0 0FkIELD FRE1QMUENCY (H1z0)M 100M 03787-018 VADDDu2 Msu1p3p0ly1 ccuhrarnennet la cso an ffuignucrtaiotino nosf. data rate for ADuM1300/ Figure 17. Maximum Allowable Current for Various Current-to-ADuM1300/ADuM1301 Spacings Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Take care in the layout of such traces to avoid this possibility. Rev. K | Page 26 of 32

Data Sheet ADuM1300/ADuM1301 INSULATION LIFETIME In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower, which allows operation at All insulation structures eventually break down when subjected to higher working voltages while still achieving a 50-year service voltage stress over a sufficiently long period. The rate of insulation life. The working voltages listed in Table 14 can be applied while degradation is dependent on the characteristics of the voltage maintaining the 50-year minimum lifetime provided the voltage waveform applied across the insulation. In addition to the conforms to either the unipolar ac or dc voltage cases. Any cross testing performed by the regulatory agencies, Analog Devices insulation voltage waveform that does not conform to Figure 19 carries out an extensive set of evaluations to determine the or Figure 20 should be treated as a bipolar ac waveform, and its lifetime of the insulation structure within the ADuM1300/ peak voltage should be limited to the 50-year lifetime voltage ADuM1301. value listed in Table 14. Analog Devices performs accelerated life testing using voltage Note that the voltage presented in Figure 19 is shown as sinusoidal levels higher than the rated continuous working voltage. Accel- for illustration purposes only. It is meant to represent any voltage eration factors for several operating conditions are determined. waveform varying between 0 V and some limiting value. The These factors allow calculation of the time to failure at the actual limiting value can be positive or negative, but the voltage working voltage. The values shown in Table 14 summarize the cannot cross 0 V. peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working RATED PEAK VOLTAGE vthoaltna gthese. 5In0- myeaanry s ecravsiecse, tlhifee avpopltraogvee. dO wpoerraktiinogn v aotl ttahgees ies hhiigghhe r 0V 03787-021 working voltages can lead to shortened insulation life in some Figure 18. Bipolar AC Waveform cases. The insulation lifetime of the ADuM1300/ADuM1301 depends RATED PEAK VOLTAGE doTnehp ete hinCed oviounlpgta loegrne iwwnashvueeltafhoteirormn t htsyetpr wue caimtvueprfeoo rsdemedg iarsac brdoiepssso atltha red aiifscfo,e lruaetnnioitpn ro abltaaerrs ra iecr, . 0V 03787-022 Figure 19. Unipolar AC Waveform or dc. Figure 18, Figure 19, and Figure 20 illustrate these different isolation voltage waveforms, respectively. Bipolar ac voltage is the most stringent environment. The goal RATED PEAK VOLTAGE odfe tae r5m0-iyneeasr tohpee Arantainlogg l iDfeetvimicee su rnedceorm thmee ancd bedip molaarx icmonudmit ion 0V 03787-023 working voltage. Figure 20. DC Waveform Rev. K | Page 27 of 32

ADuM1300/ADuM1301 Data Sheet OUTLINE DIMENSIONS 10.50(0.4134) 10.10(0.3976) 16 9 7.60(0.2992) 7.40(0.2913) 1 8 10.65(0.4193) 10.00(0.3937) 1.27(0.0500) 0.75(0.0295) BSC 2.65(0.1043) 0.25(0.0098) 45° 0.30(0.0118) 2.35(0.0925) 8° 0.10(0.0039) 0° COPLANARITY 0.10 0.51(0.0201) PSELAATNIENG 0.33(0.0130) 1.27(0.0500) 0.31(0.0122) 0.20(0.0079) 0.40(0.0157) R(CINEOFNPEATRRREOENNLCLTEIHNCEOGOSNDMELISPYM)LAEAIANNRNDSETIAORTRNOOESUJNANEORDDETEEDAICN-POSMPFTRIFALONLMPIDMIRLAELIRATIMTDEEESRTFSMEO;SRIRN-0ECU1QH3SU-EADIVAIINMAELDENENSSTIIOGSNNFS.OR 27-2007-B03- Figure 21. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters (and inches) Rev. K | Page 28 of 32

Data Sheet ADuM1300/ADuM1301 ORDERING GUIDE Number Number Maximum Maximum Maximum of Inputs, of Inputs, Data Rate Propagation Pulse Width Package Model1, 2, 3 V Side V Side (Mbps) Delay, 5 V (ns) Distortion (ns) Temperature Range Option4 DD1 DD2 ADuM1300ARW 3 0 1 100 40 −40°C to +105°C RW-16 ADuM1300ARW-RL 3 0 1 100 40 −40°C to +105°C RW-16 ADuM1300ARWZ 3 0 1 100 40 −40°C to +105°C RW-16 ADuM1300ARWZ-RL 3 0 1 100 40 −40°C to +105°C RW-16 ADuM1300BRWZ 3 0 10 50 3 −40°C to +105°C RW-16 ADuM1300BRWZ-RL 3 0 10 50 3 −40°C to +105°C RW-16 ADuM1300CRWZ 3 0 90 32 2 −40°C to +105°C RW-16 ADuM1300CRWZ-RL 3 0 90 32 2 −40°C to +105°C RW-16 ADuM1300WSRWZ 3 0 1 100 40 −40°C to +125°C RW-16 ADuM1300WSRWZ-RL 3 0 1 100 40 −40°C to +125°C RW-16 ADuM1300WTRWZ 3 0 10 32 3 −40°C to +125°C RW-16 ADUM1300WTRWZ-RL 3 0 10 32 3 −40°C to +125°C RW-16 ADuM1301ARW 2 1 1 100 40 −40°C to +105°C RW-16 ADUM1301ARW-RL 2 1 1 100 40 −40°C to +105°C RW-16 ADUM1301ARWZ 2 1 1 100 40 −40°C to +105°C RW-16 ADUM1301ARWZ-RL 2 1 1 100 40 −40°C to +105°C RW-16 ADuM1301BRW 2 1 10 50 3 −40°C to +105°C RW-16 ADuM1301BRW-RL 2 1 10 50 3 −40°C to +105°C RW-16 ADUM1301BRWZ 2 1 10 50 3 −40°C to +105°C RW-16 ADUM1301BRWZ-RL 2 1 10 50 3 −40°C to +105°C RW-16 ADuM1301CRW 2 1 90 32 2 −40°C to +105°C RW-16 ADuM1301CRWZ 2 1 90 32 2 −40°C to +105°C RW-16 ADuM1301CRWZ-RL 2 1 90 32 2 −40°C to +105°C RW-16 ADuM1301WSRWZ 2 1 1 100 40 −40°C to +125°C RW-16 ADUM1301WSRWZ-RL 2 1 1 100 40 −40°C to +125°C RW-16 ADuM1301WTRWZ 2 1 10 32 3 −40°C to +125°C RW-16 ADUM1301WTRWZ-RL 2 1 10 32 3 −40°C to +125°C RW-16 EVAL-ADuMQSEBZ 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. 3 The addition of an -RL suffix designates a 13” (1,000 units) tape-and-reel option. 4 RW-16 = 16-lead wide body SOIC. AUTOMOTIVE PRODUCTS The ADuM1300W/ADuM1301W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. K | Page 29 of 32

ADuM1300/ADuM1301 Data Sheet NOTES Rev. K | Page 30 of 32

Data Sheet ADuM1300/ADuM1301 NOTES Rev. K | Page 31 of 32

ADuM1300/ADuM1301 Data Sheet NOTES ©2003–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03787-0-11/15(K) Rev. K | Page 32 of 32