Hot Swappable, Dual I2C Isolators Data Sheet ADuM1250/ADuM1251 FEATURES FUNCTIONAL BLOCK DIAGRAMS Bidirectional I2C communication Open-drain interfaces VDD1 1 DECODE ENCODE 8 VDD2 Suitable for hot swap applications 30 mA current sink capability SDA1 2 ENCODE DECODE 7 SDA2 1000 kHz operation SCL1 3 DECODE ENCODE 6 SCL2 38.-0le Va dto, R 5o.5H VS csoumpppllyia/lnotg SicO lIeCv pelasc kage GND1 4 ENCODE DECODE 5 GND2 06113-001 High temperature operation: 125°C Figure 1. ADuM1250 Qualified for automotive applications Safety and regulatory approvals VDD1 1 DECODE ENCODE 8 VDD2 UL recognition 2500 V rms for 1 minute per UL 1577 SDA1 2 ENCODE DECODE 7 SDA2 CSA Component Acceptance Notice 5A SCL1 3 ENCODE DECODE 6 SCL2 VDE certificate of conformity DVIN V = V 5D6E0 V V 0 p8e8a4k- 10 (VDE V 0884-10):2006-12 GND1 4 5 GND2 06113-002 IORM Figure 2. ADuM1251 APPLICATIONS Isolated I2C, SMBus, or PMBus interfaces Multilevel I2C interfaces Power supplies Networking Power over Ethernet Hybrid electric vehicle battery management GENERAL DESCRIPTION The ADuM1250/ADuM12511 are hot swappable digital isolators Both the ADuM1250 and the ADuM1251 contain hot swap with nonlatching, bidirectional communication channels that circuitry to prevent glitching data when an unpowered card is are compatible with I2C interfaces. This eliminates the need for inserted onto an active bus. splitting I2C signals into separate transmit and receive signals These isolators are based on the iCoupler® chip scale transformer for use with standalone optocouplers. technology from Analog Devices, Inc. iCoupler is a magnetic The ADuM1250 provides two bidirectional channels, supporting isolation technology with functional, performance, size, and a complete isolated I2C interface. The ADuM1251 provides one power consumption advantages as compared to optocouplers. bidirectional channel and one unidirectional channel for applica- With the ADuM1250/ADuM1251, iCoupler channels can be tions where a bidirectional clock is not required. integrated with semiconductor circuitry, which enables a complete isolated I2C interface to be implemented in a small form factor. 1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADuM1250/ADuM1251 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................7 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions ..............................8 Functional Block Diagrams ............................................................. 1 Test Conditions ..................................................................................9 General Description ......................................................................... 1 Applications Information .............................................................. 10 Revision History ............................................................................... 2 Functional Description .............................................................. 10 Specifications ..................................................................................... 3 Startup .......................................................................................... 10 Electrical Characteristics ............................................................. 3 Typical Application Diagram .................................................... 11 Package Characteristics ............................................................... 5 Capacitive Load at Low Speeds ................................................ 11 Regulatory Information ............................................................... 5 Magnetic Field Immunity ......................................................... 12 Insulation and Safety-Related Specifications ............................ 5 Outline Dimensions ....................................................................... 13 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Ordering Guide .......................................................................... 13 Characteristics .............................................................................. 6 Automotive Products ................................................................. 13 Recommended Operating Conditions ...................................... 6 Absolute Maximum Ratings ............................................................ 7 REVISION HISTORY 7/15—Rev. G to Rev. H 12/09—Rev. A to Rev. B Changes to Table 4 and Table 5 ....................................................... 5 Changes to Features Section ............................................................ 1 Changes to Operating Temperature (T ) Parameter, Table 7 ...... 6 A 3/14—Rev. F to Rev. G Changes to Ambient Operating Temperature (T ) Parameter, A Moved Typical Application Diagram Section ............................. 11 Table 8 ................................................................................................. 7 Added Capacitive Load at Low Speeds Section and Table 11 ........ 11 Changes to Ordering Guide .......................................................... 12 Moved Magnetic Field Immunity Section ................................... 12 Changes to Ordering Guide .......................................................... 13 6/07—Rev. 0 to Rev. A Updated VDE Certification Throughout ....................................... 1 9/12—Rev. E to Rev. F Changes to Features and Note 1 ...................................................... 1 Created Hyperlink for Safety and Regulatory Approvals Changes to Table 4 and Table 5 ....................................................... 5 Entry in Features Section ................................................................. 1 Changes to Table 6 ............................................................................. 6 Changes to Ordering Guide .......................................................... 12 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 12 12/11—Rev. D to Rev. E Change to Ordering Guide ............................................................ 12 10/06—Revision 0: Initial Version Changes to Automotive Products Section ................................... 12 7/11—Rev. C to Rev. D Change to Typical Application Diagram Section ....................... 11 5/10—Rev. B to Rev. C Changes to Features Section and Applications Section ............... 1 Changed V = 5 V, and V = 5 V to V = 3.3 V or 5 V, DD1 DD2 DD1 and V = 3.3 V or 5 V ................................................................... 3 DD2 Changed V = 5 V, and V = 5 V to V = 3.3 V or 5 V, DD1 DD2 DD1 and V = 3.3 V or 5 V ................................................................... 4 DD2 Changes to Typical Application Diagram Section and Figure 9 ..................................................................................... 11 Changes to Ordering Guide .......................................................... 12 Added Automotive Products Section .......................................... 12 Rev. H | Page 2 of 16

Data Sheet ADuM1250/ADuM1251 SPECIFICATIONS ELECTRICAL CHARACTERISTICS DC Specifications1 All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at T = 25°C, V = 3.3 V or 5 V, and V = 3.3 V or 5 V, unless otherwise noted. A DD1 DD2 Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments ADuM1250 Input Supply Current, Side 1, 5 V I 2.8 5.0 mA V = 5 V DD1 DD1 Input Supply Current, Side 2, 5 V I 2.7 5.0 mA V = 5 V DD2 DD2 Input Supply Current, Side 1, 3.3 V I 1.9 3.0 mA V = 3.3 V DD1 DD1 Input Supply Current, Side 2, 3.3 V I 1.7 3.0 mA V = 3.3 V DD2 DD2 ADuM1251 Input Supply Current, Side 1, 5 V I 2.8 6.0 mA V = 5 V DD1 DD1 Input Supply Current, Side 2, 5 V I 2.5 4.7 mA V = 5 V DD2 DD2 Input Supply Current, Side 1, 3.3 V I 1.8 3.0 mA V = 3.3 V DD1 DD1 Input Supply Current, Side 2, 3.3 V I 1.6 2.8 mA V = 3.3 V DD2 DD2 LEAKAGE CURRENTS I , I , 0.01 10 µA V = V , V = V , SDA1 SDA2 SDA1 DD1 SDA2 DD2 I , I V = V , V = V SCL1 SCL2 SCL1 DD1 SCL2 DD2 SIDE 1 LOGIC LEVELS Logic Input Threshold2 V , V 500 700 mV SDA1T SCL1T Logic Low Output Voltages V , V 600 900 mV I = I = 3.0 mA SDA1OL SCL1OL SDA1 SCL1 600 850 mV I = I = 0.5 mA SDA1 SCL1 Input/Output Logic Low Level Difference3 ΔV , ΔV 50 mV SDA1 SCL1 SIDE 2 LOGIC LEVELS Logic Low Input Voltage V , V 0.3 V V SDA2IL SCL2IL DD2 Logic High Input Voltage V , V 0.7 V V SDA2IH SCL2IH DD2 Logic Low Output Voltage V , V 400 mV I = I = 30 mA SDA2OL SCL2OL SDA2 SCL2 1 All voltages are relative to their respective ground. 2 VIL < 0.5 V, VIH > 0.7 V. 3 ΔVS1 = VS1OL − VS1T. This is the minimum difference between the output logic low level and the input logic threshold within a given component. This ensures that there is no possibility of the part latching up the bus to which it is connected. Rev. H | Page 3 of 16

ADuM1250/ADuM1251 Data Sheet AC Specifications1 All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at T = 25°C, V = 3.3 V or 5 V, and V = 3.3 V or 5 V, unless otherwise noted. Refer to Figure 5. A DD1 DD2 Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments MAXIMUM FREQUENCY 1000 kHz OUTPUT FALL TIME 5 V Operation 4.5 V ≤ V , V ≤ 5.5 V, C = 40 pF, DD1 DD2 L1 R1 = 1.6 kΩ, C = 400 pF, R2 = 180 Ω L2 Side 1 Output (0.9 V to 0.9 V) t 13 26 120 ns DD1 f1 Side 2 Output (0.9 V to 0.1 V ) t 32 52 120 ns DD2 DD2 f2 3 V Operation 3.0 V ≤ V , V ≤ 3.6 V, C = 40 pF, DD1 DD2 L1 R1 = 1.0 kΩ, C = 400 pF, R2 = 120 Ω L2 Side 1 Output (0.9 V to 0.9 V) t 13 32 120 ns DD1 f1 Side 2 Output (0.9 V to 0.1 V ) t 32 61 120 ns DD2 DD2 f2 PROPAGATION DELAY 5 V Operation 4.5 ≤ V , V ≤ 5.5 V, C = C = 0 pF, DD1 DD2 L1 L2 R1 = 1.6 kΩ, R2 = 180 Ω Side 1 to Side 2, Rising Edge2 t 95 130 ns PLH12 Side 1 to Side 2, Falling Edge3 t 162 275 ns PHL12 Side 2 to Side 1, Rising Edge4 t 31 70 ns PLH21 Side 2 to Side 1, Falling Edge5 t 85 155 ns PHL21 3 V Operation 3.0 V ≤ V , V ≤ 3.6 V, C = C = 0 pF, DD1 DD2 L1 L2 R1 = 1.0 kΩ, R2 = 120 Ω Side 1 to Side 2, Rising Edge2 t 82 125 ns PLH12 Side 1 to Side 2, Falling Edge3 t 196 340 ns PHL12 Side 2 to Side 1, Rising Edge4 t 32 75 ns PLH21 Side 2 to Side 1, Falling Edge5 t 110 210 ns PHL21 PULSE WIDTH DISTORTION 5 V Operation 4.5 V ≤ V , V ≤ 5.5 V, C = C = 0 pF, DD1 DD2 L1 L2 R1 = 1.6 kΩ, R2 = 180 Ω Side 1 to Side 2, |t − t | PWD 67 145 ns PLH12 PHL12 12 Side 2 to Side 1, |t − t | PWD 54 85 ns PLH21 PHL21 21 3 V Operation 3.0 V ≤ V , V ≤ 3.6 V, C = C = 0 pF, DD1 DD2 L1 L2 R1 = 1.0 kΩ, R2 = 120 Ω Side 1 to Side 2, |t − t | PWD 114 215 ns PLH12 PHL12 12 Side 2 to Side 1, |t − t | PWD 77 135 ns PLH21 PHL21 21 COMMON-MODE TRANSIENT IMMUNITY6 |CM |, |CM| 25 35 kV/μs H L 1 All voltages are relative to their respective ground. 2 tPLH12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.7 VDD2. 3 tPHL12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.4 V. 4 tPLH21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.7 VDD1. 5 tPHL21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.9 V. 6 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. Rev. H | Page 4 of 16

Data Sheet ADuM1250/ADuM1251 PACKAGE CHARACTERISTICS Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments Resistance (Input to Output)1 R 1012 Ω I-O Capacitance (Input to Output)1 C 1.0 pF f = 1 MHz I-O Input Capacitance C 4.0 pF I IC Junction to Case Thermal Resistance, Side 1 θ 46 °C/W Thermocouple located at center of package underside JCI IC Junction to Case Thermal Resistance, Side 2 θ 41 °C/W JCO 1 The device is considered a 2-terminal device; Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together. REGULATORY INFORMATION The ADuM1250/ADuM1251 have been approved by the organizations listed in Table 4. Table 4. UL CSA CQC VDE Recognized Under 1577 Approved under CSA Component Approved under CQC11-471543-2012 Certified according to Component Acceptance Notice 5A DIN V VDE V 0884-10 Recognition (VDE V 0884-10): 2006-122 Program1 Single/Basic 2500 V rms Reinforced insulation per Basic insulation per GB4943.1-2011, Reinforced insulation, Isolation Voltage CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working 560 V peak 125 V rms (177 V peak) maximum voltage, tropical climate, altitude ≤ 5000 m working voltage Basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage File E214100 File 205078 File CQC14001108691 File 2471900-4880-0001 1 In accordance with UL 1577, each ADuM1250/ADuM1251 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA). 2 In accordance with DIN V VDE V 0884-10, each ADuM1250/ADuM1251 is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY RELATED SPECIFICATIONS Table 5. Parameter Symbol Value Unit Test Conditions/Comments Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 4.90 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 4.01 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1 Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1) Maximum Working Voltage Compatible with V 565 V peak Continuous peak voltage across the isolation barrier IORM 50 Year Service Life Rev. H | Page 5 of 16

ADuM1250/ADuM1251 Data Sheet DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage. Table 6. Description Test Conditions/Comments Symbol Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V 560 V peak IORM Input to Output Test Voltage, Method B1 V × 1.875 = V , 100% production test, t = 1 sec, V 1050 V peak IORM PR m PR partial discharge < 5 pC Input to Output Test Voltage, Method A V × 1.6 = V , t = 60 sec, partial discharge < 5 pC V IORM PR m PR After Environmental Tests Subgroup 1 896 V peak After Input and/or Safety Tests Subgroup 2 V × 1.2 = V , t = 60 sec, partial discharge < 5 pC 672 V peak IORM PR m and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, t = 10 sec V 4000 V peak TR TR Safety Limiting Values Maximum value allowed in the event of a failure (see Figure 3) Case Temperature T 150 °C S V + V Current I 212 mA DD1 DD2 TMAX Insulation Resistance at T V = 500 V R >109 Ω S IO S 350 RECOMMENDED OPERATING CONDITIONS 300 Table 7. A) m Parameter Rating T ( 250 EN Operating Temperature (TA) R R 200 A Grade −40°C to +105°C U G C S Grade −40°C to +125°C MITIN 150 Supply Voltages (VDD1, VDD2)1 3.0 V to 5.5 V LI Input/Output Signal Voltage 5.5 V ETY- 100 (VSDA1, VSCL1, VSDA2, VSCL2) AF Capacitive Load S 50 Side 1 (C ) 40 pF L1 00 50CASE TEMP1E0R0ATURE (°C)150 200 06113-003 StaStiidc eO 2u t(CpLu2t) Loading 400 pF Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values on Side 1 (ISDA1, ISCL1) 0.5 mA to 3 mA Case Temperature, per DIN V VDE V 0884-10 Side 2 (I , I ) 0.5 mA to 30 mA SDA2 SCL2 1 All voltages are relative to their respective ground. See the Magnetic Field Immunity section for information about immunity to external magnetic fields. Rev. H | Page 6 of 16

Data Sheet ADuM1250/ADuM1251 ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. ESD CAUTION Table 8. Parameter Rating Storage Temperature (T ) −55°C to +150°C ST Ambient Operating Temperature (T ) A A Grade −40°C to +105°C S Grade −40°C to +125°C Supply Voltages (V , V )1 −0.5 V to +7.0 V DD1 DD2 Input/Output Voltage, Side 1 (VSDA1, VSCL1)2 −0.5 V to VDD1 + 0.5 V Side 2 (V , V ) 2 −0.5 V to V + 0.5 V SDA2 SCL2 DD2 Average Output Current per Pin2 Side 1 (I ) ±18 mA O1 Side 2 (I ) ±100 mA O2 Common-Mode Transients3 −100 kV/μs to +100 kV/μs 1 All voltages are relative to their respective ground. 2 See Figure 3 for maximum rated current values for various temperatures. 3 Refers to common-mode transients across the insulation barrier. Common- mode transients exceeding the absolute maximum rating may cause latch-up or permanent damage. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. H | Page 7 of 16

ADuM1250/ADuM1251 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD1 1 ADuM1250/ 8 VDD2 SDA1 2 ADuM1251 7 SDA2 GSNCDL11 34 (NToOt Pto V SIEcaWle) 65 SGCNLD22 06113-004 Figure 4. ADuM1250/ADuM1251 Pin Configuration Table 9. ADuM1250 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage, 3.0 V to 5.5 V. DD1 2 SDA Data Input/Output, Side 1. 1 3 SCL Clock Input/Output, Side 1. 1 4 GND Ground 1. Ground reference for Isolator Side 1. 1 5 GND Ground 2. Isolated ground reference for Isolator Side 2. 2 6 SCL Clock Input/Output, Side 2. 2 7 SDA Data Input/Output, Side 2. 2 8 V Supply Voltage, 3.0 V to 5.5 V. DD2 Table 10. ADuM1251 Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage, 3.0 V to 5.5 V. DD1 2 SDA Data Input/Output, Side 1. 1 3 SCL Clock Input, Side 1. 1 4 GND Ground 1. Ground reference for Isolator Side 1. 1 5 GND Ground 2. Isolated ground reference for Isolator Side 2. 2 6 SCL Clock Output, Side 2. 2 7 SDA Data Input/Output, Side 2. 2 8 V Supply Voltage, 3.0 V to 5.5 V. DD2 Rev. H | Page 8 of 16

Data Sheet ADuM1250/ADuM1251 TEST CONDITIONS VDD1 1 DECODE ENCODE 8 VDD2 R1 R1 SDA1 2 ENCODE DECODE 7 SDA2 R2 R2 SCL1 3 DECODE ENCODE 6 SCL2 CL1 CL1 GND1 4 ENCODE DECODE 5 GND2 CL2 CL2 06113-005 Figure 5. Timing Test Diagram Rev. H | Page 9 of 16

ADuM1250/ADuM1251 Data Sheet APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION STARTUP The ADuM1250/ADuM1251 interface on each side to a Both the V and V supplies have an undervoltage lockout DD1 DD2 bidirectional I2C signal. Internally, the I2C interface is split feature to prevent the signal channels from operating unless into two unidirectional channels communicating in opposing certain criteria are met. This feature prevents input logic low directions via a dedicated iCoupler isolation channel for each. signals from pulling down the I2C bus inadvertently during One channel (the bottom channel of each channel pair shown power-up/power-down. in Figure 6) senses the voltage state of the Side 1 I2C pin and For the signal channels to be enabled, the following two criteria transmits its state to its respective Side 2 I2C pin. must be met: Both the Side 1 and the Side 2 I2C pins are designed to interface  Both supplies must be at least 2.5 V. to an I2C bus operating in the 3.0 V to 5.5 V range. A logic low  At least 40 μs must elapse after both supplies exceed the on either pin causes the opposite pin to be pulled low enough to internal startup threshold of 2.0 V. comply with the logic low threshold requirements of other I2C devices on the bus. Avoidance of I2C bus contention is ensured Until both criteria are met for both supplies, the ADuM1250/ by an input low threshold at SDA or SCL guaranteed to be at ADuM1251 outputs are pulled high, ensuring a startup that 1 1 least 50 mV less than the output low signal at the same pin. This avoids any disturbances on the bus. Figure 7 and Figure 8 illustrate prevents an output logic low at Side 1 being transmitted back to the supply conditions for fast and slow input supply slew rates. Side 2 and pulling down the I2C bus. Because the Side 2 logic levels/thresholds are standard I2C values, multiple ADuM1250/ADuM1251 devices connected to a bus by MINIMUM RECOMMENDED OPERATING SUPPLY, 3.0V their Side 2 pins can communicate with each other and with other SUPPLY VALID I2C compatible devices. A distinction is made between I2C compat- MINIMUM VALID SUPPLY, 2.5V ibility and I2C compliance. I2C compatibility refers to situations in INTERNAL START-UP which the logic levels of a component do not necessarily meet the THRESHOLD, 2.0V rtoeq cuoimremmeunntisc oaft et hwei It2hC a snp eI2cCif iccoatmiopnl ibauntt sdtiellv aiclleo.w I2 tCh ec ocommpplioannecne t 40µs 06113-007 refers to situations in which the logic levels of a component meet Figure 7. Start-Up Condition, Supply Slew Rate > 12.5 V/ms the requirements of the I2C specification. However, because the Side 1 pin has a modified output level/ input threshold, this side of the ADuM1250/ADuM1251 can MINIMUM RECOMMENDED communicate only with devices that conform to the I2C stan- OPERATING SUPPLY, 3.0V dard. In other words, Side 2 of the ADuM1250/ADuM1251 is MINIMUMVALID SUPPLY, 2.5V SUPPLYVALID I2C compliant, whereas Side 1 is only I2C compatible. INTERNAL START-UP THRESHOLD, 2.0V The output logic low levels are independent of the V and DD1 VinDdDe2p veonltdaegnets .o Tf Vhe in.p Huot wloegvice rl,o twhe t hinrpesuhto loldg iact lSoiwde t h1 riess ahlosold at 40µs 06113-008 DD1 Figure 8. Start-Up Condition, Supply Slew Rate < 12.5 V/ms Side 2 is designed to be at 0.3 V , consistent with I2C require- DD2 ments. The Side 1 and Side 2 pins have open-collector outputs whose high levels are set via pull-up resistors to their respective supply voltages. VDD2 VDD1 1 DECODE ENCODE 8 SDA2 R2 R2 SDA1 2 ENCODE DECODE 7 SCL2 SCL1 3 DECODE ENCODE 6 GND1 4 ENCODE DECODE 5 GND2 CL CL 06113-006 Figure 6. ADuM1250 Block Diagram Rev. H | Page 10 of 16

Data Sheet ADuM1250/ADuM1251 TYPICAL APPLICATION DIAGRAM CAPACITIVE LOAD AT LOW SPEEDS Figure 9 shows a typical application circuit including the pull-up The ADuM1250/ADuM1251 are designed for operation at resistors required for both Side 1 and Side 2 buses. Bypass capaci- speeds up to 1 Mbps. Due to the limited current available on tors with values from 0.01 μF to 0.1 μF are required between V Side 1, operation at 1 Mbps limits the capacitance that can be DD1 and GND and between V and GND. The 200 Ω resistor shown driven at the minimum pull-up value to 40 pF. 1 DD2 2 in Figure 9 is required for latch-up immunity if the ambient Most applications operate at 100 kbps in standard mode or temperature can be between 105°C and 125°C. 400 kbps in fast mode. At these lower operating speeds, the OPTIONAL limitation on the load capacitance can be significantly relaxed. VDD1 200Ω 1 ADuM1250 8 VDD2 Table 11 shows the maximum capacitance at minimum pull-up SDA1 2 7 SDA2 I2C BUS values for standard and fast operating modes. If larger values for SCL1 3 6 SCL2 the pull up resistor are used, the maximum supported capacitance must be scaled down proportionately so that the rise time does GND1 4 5 GND2 06113-009 not increase beyond the values required by the standard. Figure 9. Typical Isolated I2C Interface Using the ADuM1250 Table 11. Side 1 Maximum Load Conditions Maximum Capacitive Load for Side 1 Mode V Data Rate (kbps) t (ns) t (ns) R (Ω) C (pF) DD1 r f 1 L1 Standard 5 100 1000 187 1600 484 Fast 5 400 300 172 1600 120 Standard 3.3 100 1000 270 1000 771 Fast 3.3 400 300 235 1000 188 Rev. H | Page 11 of 16

ADuM1250/ADuM1251 Data Sheet MAGNETIC FIELD IMMUNITY For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a The ADuM1250/ADuM1251 are extremely immune to external voltage of 0.25 V at the receiving coil. This voltage is approxi- magnetic fields. The limitation on the magnetic field immunity mately 50% of the sensing threshold and does not cause a faulty of the ADuM1250/ADuM1251 is set by the condition in which output transition. Similarly, if such an event occurs during a induced voltage in the receiving coil of the transformer is suffi- transmitted pulse (and is of the worst-case polarity), it reduces the ciently large to either falsely set or reset the decoder. The following received pulse from >1.0 V to 0.75 V, still well above the 0.5 V analysis defines the conditions under which this may occur. The sensing threshold of the decoder. 3 V operating condition of the ADuM1250/ADuM1251 is exam- ined because it represents the most susceptible mode of operation. The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM1250/ The pulses at the transformer output have an amplitude greater ADuM1251 transformers. Figure 11 expresses these allowable than 1.0 V. The decoder has a sensing threshold at approximately current magnitudes as a function of frequency for selected 0.5 V, thus establishing a 0.5 V margin in which induced voltages distances. As shown in Figure 11, the ADuM1250/ADuM1251 can be tolerated. The voltage induced across the receiving coil is are extremely immune and can be affected only by extremely given by large currents operated at high frequency very close to the V = (−dβ/dt) ∑ πr2; n = 1, 2, … , N n component. For the 1 MHz example, a 0.5 kA current placed where: 5 mm away from the ADuM1250/ADuM1251 is required to β is the magnetic flux density (gauss). affect the operation of the component. rn is the radius of the nth turn in the receiving coil (cm). 1000 N is the total number of turns in the receiving coil. A) DISTANCE = 1m k Given the geometry of the receiving coil in the ADuM1250/ T ( 100 N ADuM1251 and an imposed requirement that the induced E R R voltage be, at most, 50% of the 0.5 V margin at the decoder, U C a maximum allowable magnetic field is calculated as shown LE 10 B in Figure 10. WA DISTANCE = 100mm O 100 LL 1 A X M DISTANCE = 5mm U U L M TIC F 10 MAXI 0.1 E N ALLOWABLE MAGDENSITY (kgauss) 0.11 0.011kFiguCruer 1re1n.1 tM0-MktaoAx-GiAmNDEuuTmM1IC0 1A 0F2klIl5Eo0Lw/DAa FDbRlueEM 1CQM1uU2rEr5Ne1Cn SYt pf (oaHrc1z V0i)nMagrsio us 100M 06113-011 M U Note that at combinations of strong magnetic field and high M 0.01 XI frequency, any loops formed by PCB traces can induce error A M voltages sufficiently large to trigger the thresholds of succeeding 0.0011k 10kMAGNETI1C0 0FkIELD FREQ1MUENCY (Hz1)0M 100M 06113-010 cpiorscsuiibtirlyit. yE. xercise care in the layout of such traces to avoid this Figure 10. Maximum Allowable External Magnetic Flux Density Rev. H | Page 12 of 16

Data Sheet ADuM1250/ADuM1251 OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 12. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Number Number Maximum Maximum of Inputs, of Inputs, Data Rate Propagation Temperature Package Package Model1, 2 V Side V Side (Mbps) Delay (ns) Range Description Option DD1 DD2 ADuM1250ARZ 2 2 1 150 −40°C to +105°C 8-Lead SOIC_N R-8 ADuM1250ARZ-RL7 2 2 1 150 −40°C to +105°C 8-Lead SOIC_N R-8 ADuM1250SRZ 2 2 1 150 −40°C to +125°C 8-Lead SOIC_N R-8 ADuM1250SRZ-RL7 2 2 1 150 −40°C to +125°C 8-Lead SOIC_N R-8 ADuM1250WSRZ 2 2 1 150 −40°C to +125°C 8-Lead SOIC_N R-8 ADuM1250WSRZ-RL7 2 2 1 150 −40°C to +125°C 8-Lead SOIC_N R-8 ADuM1251ARZ 2 1 1 150 −40°C to +105°C 8-Lead SOIC_N R-8 ADuM1251ARZ-RL7 2 1 1 150 −40°C to +105°C 8-Lead SOIC_N R-8 ADuM1251WARZ 2 1 1 150 −40°C to +125°C 8-Lead SOIC_N R-8 ADuM1251WARZ-RL7 2 1 1 150 −40°C to +125°C 8-Lead SOIC_N R-8 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADuM1250W and ADuM1251W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. H | Page 13 of 16

ADuM1250/ADuM1251 Data Sheet NOTES Rev. H | Page 14 of 16

Data Sheet ADuM1250/ADuM1251 NOTES Rev. H | Page 15 of 16

ADuM1250/ADuM1251 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2006–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06113-0-7/15(H) Rev. H | Page 16 of 16

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADUM1250SRZ-RL7 ADUM1250ARZ ADUM1250ARZ-RL7 ADUM1250SRZ ADUM1251ARZ-RL7 ADUM1251ARZ ADUM1250WSRZ-RL7 ADUM1250WSRZ ADUM1251WARZ-RL7 ADUM1251WARZ EVAL-ADUM1250EBZ