Micropower, Dual-Channel Digital Isolators Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 FEATURES FUNCTIONAL BLOCK DIAGRAMS Ultralow power operation VDD1 1 ADuM124x 20VDD2 3.3 V operation GND1 2 19 GND2 5.6 μA per channel quiescent current, refresh enabled NIC 3 18 NIC 0.3 μA per channel quiescent current, refresh disabled NIC 4 17 NIC 148 μA/Mbps per channel typical dynamic current 2.5 V operation VIA/VOA 5 ENCODE DECODE 16 VOA/VIA 3.1 μA per channel quiescent current, refresh enabled VIB 6 ENCODE DECODE 15 VOB 0.1 μA per channel quiescent current, refresh disabled EN1 7 14 EN2 116 μA/Mbps per channel typical dynamic current NIC 8 13NIC SBmidairlel,c 2t0io-lneaald c SoSmOmP upnaicckaatgioen a nd small 8-lead SOIC package GNNDIC1 190 1121NGINCD2 11925-002 Up to 2 Mbps data rate nonreturn to zero (NRZ) Figure 1. 20-Lead SSOP Package Functional Block Diagram High temperature operation: 125°C High common-mode transient immunity: >25 kV/μs VDD1 1 ADuM124x 8 VDD2 Safety and Regulatory Approvals VIA/VOA 2 ENCODE DECODE 7 VOA/VIA UL 1577 component recognition program VIB 3 ENCODE DECODE 6 VOB 3750 V rms for 1 minute per UL 1577 (20-lead SSOP) GND1 4 5 GND2 11925-102 3000 V rms for 1 minute per UL 1577 (8-lead SOIC) Figure 2. 8-Lead SOIC Package Functional Block Diagram CSA Component Acceptance Notice 5A The ADuM1240/ADuM1241/ADuM1245/ADuM1246 are VDE certificate of conformity packaged in either a 20-lead SSOP for 3.75 kV reinforced DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 isolation or an 8-lead SOIC for 3 kV basic isolation. The devices V = 849 V peak (20-lead SSOP) IORM meet regulatory requirements, such as UL and CSA standards. V = 560 V peak (8-lead SOIC) IORM APPLICATIONS In addition to the space saving package options, the ADuM1240/ ADuM1241/ADuM1245/ADuM1246 operate with supplies as General-purpose, low power, multichannel isolation low as 2.25 V. All models provide low, pulse width distortion at 1 MHz low power serial peripheral interface (SPI) <8 ns. In addition, every model has an input glitch filter to 4 mA to 20 mA loop process control protect against extraneous noise disturbances. GENERAL DESCRIPTION 1000 The ADuM1240/ADuM1241/ADuM1245/ADuM12461 are T micropower, 2-channel, digital isolators based on the Analog N E Devices, Inc., iCoupler® technology. Combining high speed, RR 100 cmcsuooompmnepprolioeloimntrhe etinonct t staa hirpryer comaovltreieetdra etnl r ooaaxtuniivtdssfeetos asr,n emsmdueicinrch ogt ena pcsde huorncpfototoorlromc g(oCaiuenMpsc,l eeOt hrcS ehd)sae earv naiisccdote elsar. tisiotinc s OTAL SUPPLY CUR CHANNEL (µA) 10 ENx = 0 TE The 20-lead SSOP version of the ADuM1240/ADuM1241/ LP ADuM1245/ADuM1246 allows control of the internal refresh PICA 1 ENx = 1 Y functions. As shown in Figure 3, in standard operating mode, T when EN = 0 (internal refresh enabled), the current per channel is x lWeshs etnh aEnN 1x0 = μ 1A (. internal refresh disabled), the current per 0.10.1 1 DA10TA RATE (k1b0p0s) 1000 10000 11925-001 Figure 3. Typical Total Supply Current (IDD1 + IDD2) per Channel (VDDx = channel drops to less than 1 μA. 3.3 V) as a Function of Data Rate 1 Protected by U.S. Patents 5,952,849, 6,873,065, 7,075,329, 6,262,600. Other patents pending. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ..................................................... 10 Applications ....................................................................................... 1 Continuous Working Voltage ................................................... 10 General Description ......................................................................... 1 ESD Caution................................................................................ 10 Functional Block Diagrams ............................................................. 1 Pin Configurations and Function Descriptions ......................... 11 Revision History ............................................................................... 2 Truth Tables................................................................................. 13 Specifications ..................................................................................... 3 Typical Performance Characteristics ........................................... 14 Electrical Characteristics—3.3 V Operation ............................ 3 Applications Information .............................................................. 17 Electrical Characteristics—2.5 V Operation ............................ 4 PCB Layout ................................................................................. 17 Electrical Characteristics—V = 3.3 V, V = 2.5 V Propagation Delay Related Parameters ................................... 17 DD1 DD2 Operation ....................................................................................... 6 DC Correctness and Low Power Operation ........................... 17 Electrical Characteristics—VDD1 = 2.5 V, VDD2 = 3.3 V Magnetic Field Immunity.......................................................... 18 Operation ....................................................................................... 6 Power Consumption .................................................................. 19 Package Characteristics ............................................................... 7 Insulation Lifetime ..................................................................... 19 Regulatory Information ............................................................... 7 Packaging and Ordering Information .......Error! Bookmark not Insulation and Safety Related Specifications ............................ 8 defined. DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 Outline Dimensions ................................................................... 20 Insulation Characteristics ............................................................ 8 Ordering Guide .......................................................................... 20 Recommended Operating Conditions ...................................... 9 REVISION HISTORY 9/2016—Rev. A to Rev. B Added Figure 5................................................................................ 11 Changes to Features Section............................................................ 1 Changes to Table 19 ....................................................................... 11 Changes to Regulatory Information Section and Table 12 ......... 7 Added Figure 7................................................................................ 12 Changes to Table 20 ....................................................................... 12 3/2014—Rev. 0 to Rev. A Changes to Table 22 and Table 23 ....................................................... 13 Added 8-lead SOIC Package ............................................. Universal Changes to PCB Layout Section ............................................................. 17 Changes to Features Section, General Description Section, and Added Figure 28 ......................................................................................... 17 Figure 3 .............................................................................................. 1 Changes to Recommended Input Voltage for Low Power Deleted Product Highlights Section............................................... 1 Operation Section........................................................................... 18 Added Figure 2; Renumbered Sequentially .................................. 1 Added Figure 35, Outline Dimensions ........................................ 20 Changes to Table 12 .......................................................................... 7 Changes to Ordering Guide .......................................................... 21 Changes to Table 13 .......................................................................... 8 Added Table 14; Renumbered Sequentially .................................. 8 12/2013—Revision 0: Initial Version Changed Case Temperature to Ambient Temperature, Figure 4 Caption ............................................................................... 9 Rev. B | Page 2 of 24

Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—3.3 V OPERATION All typical specifications are at T = 25°C, V = V = 3.3 V. Minimum and maximum specifications apply over the entire A DD1 DD2 recommended operation range of 3.0 V ≤ V ≤ 3.6 V, 3.0 V ≤ V ≤ 3.6 V, and −40°C ≤ T ≤ +125°C, unless otherwise noted. Switching DD1 DD2 A specifications are tested with C = 15 pF and CMOS signal levels, unless otherwise noted. L Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS Data Rate 2 Mbps Within pulse width distortion (PWD) limit Propagation Delay t , t 80 180 ns 50% input to 50% output PHL PLH Change vs. Temperature 200 ps/°C Minimum Pulse Width PW 500 ns Within PWD limit Pulse Width Distortion PWD 8 ns |t − t | PLH PHL Propagation Delay Skew1 t 10 ns PSK Channel Matching Codirectional t 10 ns PSKCD Opposing Direction t 15 ns PSKOD 1 tPSK is the magnitude of the worst case difference in tPHL and tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SUPPLY CURRENT 2 Mbps, no load ADuM1240/ADuM1245 I 366 600 µA DD1 I 246 375 µA DD2 ADuM1241/ADuM1246 I 306 450 µA DD1 I 306 450 µA DD2 Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Input Threshold Logic High V 0.7 V 1 V IH DDx Logic Low V 0.3 V 1 V IL DDx Output Voltages Logic High V V 1 − 0.1 3.3 V I = −20 µA, V = V OH DDx OUTx Ix IxH V 1 − 0.4 3.1 V I = −4 mA, V = V DDx OUTx Ix IxH Logic Low V 0.0 0.1 V I = 20 µA, V = V OL OUTx Ix IxL 0.2 0.4 V I = 4 mA, V = V OUTx Ix IxL Input Current per Channel II −1 +0.01 +1 µA 0 V ≤ VIx ≤ VDDx1 Input Switching Thresholds Positive Threshold Voltage V 1.8 V T+ Negative Going Threshold V 1.2 V T− Input Hysteresis ΔV 0.6 V T Undervoltage Lockout, V or V UVLO 1.5 V DD1 DD2 Supply Current per Channel Quiescent Current Input Supply I 4.8 10 µA EN low DDI (Q) X Output Supply I 0.8 6 µA EN low DDO (Q) X Input (Refresh Off) I 0.12 µA EN high DDI (Q) X Output (Refresh Off) I 0.13 µA EN high DDO (Q) X Rev. B | Page 3 of 24

ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments Dynamic Supply Current Input I 88 µA/Mbps DDI (D) Output I 60 µA/Mbps DDO (D) AC SPECIFICATIONS Output Rise Time/Fall Time t /t 2 ns 10% to 90% R F Common-Mode Transient Immunity2 |CM| 25 40 kV/µs V = V 1, V = 1000 V, Ix DDx CM transient magnitude = 800 V Refresh Rate f 14 kbps r 1 VDDx = VDD1 or VDD2. 2 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 VDDx. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. ELECTRICAL CHARACTERISTICS—2.5 V OPERATION All typical specifications are at T = 25°C, V = V = 2.5 V. Minimum and maximum specifications apply over the entire A DD1 DD2 recommended operation range of 2.25 V ≤ V ≤ 2.75 V, 2.25 V ≤ V ≤ 2.75 V, and −40°C ≤ T ≤ +125°C, unless otherwise noted. DD1 DD2 A Switching specifications are tested with C = 15 pF and CMOS signal levels, unless otherwise noted. L Table 4. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS Data Rate 2 Mbps Within PWD limit Propagation Delay t , t 112 180 ns 50% input to 50% output PHL PLH Change vs. Temperature 280 ps/°C Pulse Width Distortion PWD 12 ns |t − t | PLH PHL Minimum Pulse Width PW 500 ns Within PWD limit Propagation Delay Skew1 t 10 ns PSK Channel Matching Codirectional t 10 ns PSKCD Opposing Direction t 30 ns PSKOD 1 tPSK is the magnitude of the worst case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Table 5. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SUPPLY CURRENT 2 Mbps, no load ADuM1240/ADuM1245 I 312 400 µA DD1 I 168 250 µA DD2 ADuM1241/ADuM1246 I 240 375 µA DD1 I 240 375 µA DD2 Rev. B | Page 4 of 24

Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 Table 6. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Input Threshold Logic High V 0.7 V 1 V IH DDx Logic Low V 0.3 V 1 V IL DDx Output Voltages Logic High V V 1 − 0.1 2.5 V I = −20 µA, V = V OH DDx Ox Ix IxH V 1 − 0.4 2.35 V I = −4 mA, V = V DDx Ox Ix IxH Logic Low V 0.0 0.1 V I = 20 µA, V = V OL Ox Ix IxL 0.1 0.4 V I = 4 mA, V = V Ox Ix IxL Input Current per Channel II −1 +0.01 +1 µA 0 V ≤ VIx ≤ VDDx1 Input Switching Thresholds Positive Threshold Voltage V 1.5 V T+ Negative Going Threshold V 1.0 V T− Input Hysteresis ΔV 0.5 V T Undervoltage Lockout, V or V UVLO 1.5 V DD1 DD2 Supply Current per Channel Quiescent Current Input Supply I 2.6 3.75 µA EN low DDI (Q) X Output Supply I 0.5 3.75 µA EN low DDO (Q) X Input (Refresh Off) I 0.05 µA EN high DDI (Q) X Output (Refresh Off) I 0.05 µA EN high DDO (Q) X Dynamic Supply Current Input I 76 µA/Mbps DDI (D) Output I 41 µA/Mbps DDO (D) AC SPECIFICATIONS Output Rise Time/Fall Time t /t 2 ns 10% to 90% R F Common-Mode Transient Immunity2 |CM| 25 40 kV/µs V = V 1, V = 1000 V, Ix DDx CM transient magnitude = 800 V Refresh Rate f 14 kbps r 1 VDDx = VDD1 or VDD2. 2 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 VDDx. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. B | Page 5 of 24

ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet ELECTRICAL CHARACTERISTICS—V = 3.3 V, V = 2.5 V OPERATION DD1 DD2 All typical specifications are at T = 25°C, V = 3.3 V, and V = 2.5 V. Minimum and maximum specifications apply over the entire A DD1 DD2 recommended operation range of 3.0 V ≤ V ≤ 3.6 V, 2.25 V ≤ V ≤ 2.75 V, and −40°C ≤ T ≤ +125°C, unless otherwise noted. DD1 DD2 A Switching specifications are tested with C = 15 pF and CMOS signal levels, unless otherwise noted. L For dc specifications and ac specifications, see Table 3 for parameters related to Side 1 operation, and see Table 6 for parameters related to Side 2 operation. Table 7. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS Data Rate 2 Mbps Within PWD limit Propagation Delay Side 1 to Side 2 t , t 84 180 ns 50% input to 50% output PHL PLH Side 2 to Side 1 t , t 120 180 ns 50% input to 50% output PHL PLH Change vs. Temperature 280 ps/°C Pulse Width Distortion PWD 12 ns |t − t | PLH PHL Pulse Width PW 500 ns Within PWD limit Propagation Delay Skew1 t 10 ns PSK Channel Matching Codirectional t 10 ns PSKCD Opposing Direction t 60 ns PSKOD 1 tPSK is the magnitude of the worst case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Table 8. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SUPPLY CURRENT 2 Mbps, no load ADuM1240/ADuM1245 I 366 500 µA DD1 I 168 375 µA DD2 ADuM1241/ADuM1246 I 306 400 µA DD1 I 240 375 µA DD2 ELECTRICAL CHARACTERISTICS—V = 2.5 V, V = 3.3 V OPERATION DD1 DD2 All typical specifications are at T = 25°C, V = 2.5 V, and V = 3.3 V. Minimum and maximum specifications apply over the entire A DD1 DD2 recommended operation range of 2.25 V ≤ V ≤ 2.75 V, 3.0 V ≤ V ≤ 3.6 V, and −40°C ≤ T ≤ +125°C, unless otherwise noted. DD1 DD2 A Switching specifications are tested with C = 15 pF and CMOS signal levels, unless otherwise noted. L For dc specifications and ac specifications, see Table 6 for parameters related to Side 1 operation, and see Table 3 for parameters related to Side 2 operation. Table 9. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS Data Rate 2 Mbps Within PWD limit Propagation Delay Side 1 to Side 2 t , t 120 180 ns 50% input to 50% output PHL PLH Side 2 to Side 1 t , t 84 180 ns 50% input to 50% output PHL PLH Change vs. Temperature 200 ps/°C Pulse Width Distortion PWD 12 ns |t − t | PLH PHL Pulse Width PW 500 ns Within PWD limit Propagation Delay Skew1 t 10 ns PSK Channel Matching Codirectional t 10 ns PSKCD Opposing Direction t 60 ns PSKOD 1 tPSK is the magnitude of the worst case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Rev. B | Page 6 of 24

Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 Table 10. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SUPPLY CURRENT 2 Mbps, no load ADuM1240/ADuM1245 I 306 500 µA DD1 I 248 375 µA DD2 ADuM1241/ADuM1246 I 240 375 µA DD1 I 306 450 µA DD2 PACKAGE CHARACTERISTICS Table 11. Parameter Symbol Min Typ Max Unit Test Conditions/Comments Resistance (Input to Output)1 R 1013 Ω I-O Capacitance (Input to Output)1 C 2 pF f = 1 MHz I-O Input Capacitance2 C 4.0 pF I IC Junction to Ambient Thermal Resistance θ 85 °C/W Thermocouple located at center of package underside JA 1 The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. 2 Input capacitance is from any input data pin to ground. REGULATORY INFORMATION See Table 18 and the Absolute Maximum Ratings section for recommended maximum working voltages for specific cross isolation waveforms and insulation levels. Table 12. UL CSA VDE Recognized under 1577 component Approved under CSA Component Acceptance Notice 5A Certified according to DIN V VDE V recognition program1 0884-10 (VDE V 0884-10): 2006-122 Single protection, 8-lead SOIC package, 8-lead SOIC package, basic insulation per CSA 60950-1-03 8-lead SOIC package, reinforced 3000 V rms isolation voltage and IEC 60950-1, 400 V rms (565 V peak) maximum working insulation, 560 V PEAK voltage Single protection, 20-lead SSOP package, 20-lead SSOP package, basic insulation per CSA 60950-1-03 20-lead SSOP package, reinforced 3750 V rms isolation voltage and IEC 60950-1, 530 V rms (700 V peak) maximum working insulation, 849 V PEAK voltage 20-lead SSOP package, reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 265 V rms (374 V peak) maximum working voltage File E214100 File 205078 File 2471900-4880-0001 1 In accordance with UL1577, each ADuM1240/ADuM1241/ADuM1245/ADuM1246 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 second (current leakage detection limit = 5 µA). 2 In accordance with DIN V VDE V 0884-10, each ADuM1240/ADuM1241/ADuM1245/ADuM1246 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval. Rev. B | Page 7 of 24

ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet INSULATION AND SAFETY RELATED SPECIFICATIONS Table 13. Parameter Symbol Value Unit Test Conditions/Comments Rated Dielectric Insulation Voltage 3000 V rms 1 minute duration (8-Lead SOIC) Rated Dielectric Insulation Voltage 3750 V rms 1 minute duration (20-Lead SSOP) Minimum External Tracking and Air Gap, L(I02) 4 mm min Measured from input terminals to output terminals, 8-Lead SOIC (Creepage and Clearance) shortest distance path along package body Minimum Clearance in the Plane of the L(I01) 4.5 mm min Measured from input terminals to output terminals, shortest Printed Circuit Board, 8-Lead SOIC (PCB distance through air, line of sight, in the PCB mounting plane Clearance) Minimum Clearance in the Plane of the L(I01) 5.1 mm min Measured from input terminals to output terminals, Printed Circuit Board, 20-Lead SSOP shortest distance path along package body (PCB Clearance) Minimum Clearance in the Plane of the L(I02) 5.1 mm min Measured from input terminals to output terminals, shortest Printed Circuit Board, 20-Lead SSOP distance through air, line of sight, in the PCB mounting plane (PCB Clearance) Minimum Internal Gap (Internal 0.017 mm min Insulation distance through insulation Clearance) Tracking Resistance (Comparative CTI >400 V DIN IEC 112/VDE 0303 Part 1 Tracking Index) Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1) DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation within the safety limit data only. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval. Table 14. 8-Lead SOIC (R-8) Parameter Symbol Test Conditions/Comments Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V 560 V IORM PEAK Input to Output Test Voltage, Method b1 V V × 1.875 = V , 100% production test, 1050 V pd(m) IORM pd(m) PEAK t = t = one second, partial discharge < 5 pC ini m Input to Output Test Voltage, Method a After Environmental Tests Subgroup 1 V V × 1.5 = V , t = 60 seconds, t = 10 seconds, 840 V pd(m) IORM pd(m) ini m PEAK partial discharge < 5 pC After Input and/or Safety Test Subgroup 2 V V × 1.2 = V , t = 60 seconds, t = 10 seconds, 672 V pd(m) IORM pd(m) ini m PEAK and Subgroup 3 partial discharge < 5 pC Highest Allowable Overvoltage V 3500 V IOTM PEAK Surge Isolation Voltage V V = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time 4000 V IOSM PEAK PEAK Safety Limiting Values Maximum value allowed in the event of a failure (see Figure 4) Case Temperature T 150 °C S Total Power Dissipation at 25°C I 1.64 W S1 Insulation Resistance at T R V = 500 V >109 Ω S S IO Rev. B | Page 8 of 24

Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 Table 15. 20-Lead SSOP (RS-20) Parameter Symbol Test Conditions/Comments Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V 849 V IORM PEAK Input to Output Test Voltage, Method b1 V V × 1.875 = V , 100% production test, 1592 V pd(m) IORM pd(m) PEAK t = t = one second, partial discharge < 5 pC ini m Input to Output Test Voltage, Method a After Environmental Tests Subgroup 1 V V × 1.5 = V , t =60 seconds, 1273 V pd(m) IORM pd(m) ini PEAK t = 10 seconds, partial discharge < 5 pC m After Input and/or Safety Test Subgroup 2 and V V × 1.2 = V , t = 60 seconds, 1018 V pd(m) IORM pd(m) ini PEAK Subgroup 3 t = 10 seconds, partial discharge < 5 pC m Highest Allowable Overvoltage V 5335 V IOTM PEAK Surge Isolation Voltage V V = 10 kV, 1.2 µs rise time, 50 µs, 6000 V IOSM PEAK PEAK 50% fall time Safety Limiting Values Maximum value allowed in the event of a failure (see Figure 4) Case Temperature T 150 °C S Side 1 I Current I 2.5 W DD1 S1 Insulation Resistance at T R V = 500 V >109 Ω S S IO 3.0 RECOMMENDED OPERATING CONDITIONS Table 16. 2.5 W) Parameter Symbol Min Max Unit ER (2.0 Operating Temperature TA −40 +125 °C OW Supply Voltages1 VDD1, VDD2 2.25 3.6 V P G Input Signal Rise and Fall Times 1.0 ms N1.5 TI MI LI 1 See the DC Correctness and Low Power Operation section for more FE 1.0 information. A S 0.5 00 50AMBIENT TEM10P0ERATURE(°C1)50 200 11925-003 Figure 4. Thermal Derating Curve, Dependent on Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-10 Rev. B | Page 9 of 24

ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet ABSOLUTE MAXIMUM RATINGS CONTINUOUS WORKING VOLTAGE T = 25°C, unless otherwise noted. A Table 18. Maximum Continuous Working Voltage1 Table 17. Parameter Max Unit Constraint Parameter Rating AC Voltage Storage Temperature (T ) Range −65°C to +150°C ST Bipolar Waveform 565 V peak 50-year minimum Ambient Operating Temperature −40°C to +125°C lifetime (T ) Range A Unipolar Waveform 1131 V peak 50-year minimum Supply Voltages (V , V ) −0.5 V to +5 V DD1 DD2 lifetime Input Voltages (V , V ) −0.5 V to V + 0.5 V IA IB DDI DC Voltage 1131 V peak 50-year minimum Output Voltages (V , V ) −0.5 V to V + 0.5 V OA OB DD2 lifetime Average Output Current per Pin1 Side 1 (IO1) −10 mA to +10 mA 1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Side 2 (I ) −10 mA to +10 mA O2 ESD CAUTION Common-Mode Transients2 −100 kV/μs to +100 kV/μs 1 See Figure 4 for maximum rated current values for various temperatures. 2 Refers to common-mode transients across the insulation barrier. Common- mode transients exceeding the absolute maximum ratings can cause latch-up or permanent damage. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 10 of 24

Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1 1 20 VDD2 GND1 2 19 GND2 NIC 3 18 NIC NIC 4 17 NIC ADuM1240/ VIA 5 ADuM1245 16 VOA VIB 6 TOP VIEW 15 VOB (Not to Scale) EN1 7 14 EN2 VDD1 1 8 VDD2 NIC 8 13 NIC VIA 2 AADDuuMM11224405/ 7 VOA NIC 9 12 NIC GNVDIB1 34 (NToOt Pto V SIEcaWle) 56 GVONBD2 11925-104 NGICN =D 1NO10T INTERNALLY CON11NEGCNTDE2D. 11925-004 Figure 5. ADuM1240/ADuM1245 8-Lead SOIC (R-8) Pin Configuration Figure 6. ADuM1240/ADuM1245 20-Lead SSOP (RS-20) Pin Configuration Table 19. ADuM1240/ADuM1245 8-Lead SOIC (R-8) and 20-Lead SSOP (RS-20) Pin Function Descriptions1 8-Lead 20-Lead SOIC SSOP Pin No.2 Pin No. Mnemonic Description 1 1 V Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the range DD1 of 0.01 μF to 0.1 μF between V and GND. DD1 1 N/A 2 GND Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and 1 connecting both to GND is recommended. 1 N/A 3 NIC Not Internally Connected. Leave this pin floating. N/A 4 NIC Not Internally Connected. Leave this pin floating. 2 5 V Logic Input A. IA 3 6 V Logic Input B. IB N/A 7 EN Refresh and Watchdog Enable 1. In the 20-lead SSOP package, connecting Pin 7 to GND enables 1 1 the input/output refresh and watchdog functionality for Side 1, supporting standard iCoupler operation. Tying Pin 7 to V disables the refresh and watchdog functionality for the lowest power DD1 operation. See the DC Correctness and Low Power Operation section for a description of this mode. EN and EN must be set to the same logic state. 1 2 N/A 8 NIC Not Internally Connected. Leave this pin floating. N/A 9 NIC Not Internally Connected. Leave this pin floating. 4 10 GND Ground 1. Ground reference for Isolator Side 1. In the 20-lead SSOP package, Pin 2 and Pin 10 are 1 internally connected, and connecting both to GND is recommended. 1 5 11 GND Ground 2. Ground reference for Isolator Side 2. In the 20-lead SSOP package, Pin 11 and Pin 19 are 2 internally connected, and connecting both to GND is recommended. 2 N/A 12 NIC Not Internally Connected. Leave this pin floating. N/A 13 NIC Not Internally Connected. Leave this pin floating. N/A 14 EN Refresh and Watchdog Enable 2. In the 20-lead SSOP package, connecting Pin 14 to GND enables 2 2 the input/output refresh and watchdog functionality for Side 2, supporting standard iCoupler operation. Tying Pin 14 to V disables the refresh and watchdog functionality for lowest power DD2 operation. See the DC Correctness and Low Power Operation section for a description of this mode. EN1 and EN2 must be set to the same logic state. 6 15 V Logic Output B. OB 7 16 V Logic Output A. OA N/A 17 NIC Not Internally Connected. Leave this pin floating. N/A 18 NIC Not Internally Connected. Leave this pin floating. N/A 19 GND Ground 2. Ground reference for Isolator Side 2. In the 20-lead SSOP package, Pin 11 and Pin 19 are 2 internally connected, and connecting both to GND is recommended. 2 8 20 V Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the range DD2 of 0.01 μF to 0.1 μF between V and GND. DD2 2 1 Reference AN-1109 for specific layout guidelines. 2 N/A means not applicable. Rev. B | Page 11 of 24

ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet VDD1 1 20 VDD2 GND1 2 19 GND2 NIC 3 18 NIC NIC 4 17 NIC ADuM1241/ VOA 5 ADuM1246 16 VIA VIB 6 TOP VIEW 15 VOB (Not to Scale) EN1 7 14 EN2 VDD1 1 8 VDD2 NIC 8 13 NIC ADuM1241/ VOA 2 ADuM1246 7 VIA NIC 9 12 NIC GNVDIB1 43 (NToOt Pto V SIEcaWle) 65 GVONBD2 11925-105 NGICN =D 1NO10T INTERNALLY CON11NEGCNTDE2D. 11925-005 Figure 7. ADuM1241/ADuM1246 8-Lead SOIC (R-8) Pin Configuration Figure 8. ADuM1241/ADuM1246 20-Lead SSOP (RS-20) Pin Configuration Table 20. ADuM1241/ADuM1246 8-Lead SOIC (R-8) and 20-Lead SSOP (RS-20) Pin Function Descriptions1 8-Lead 20-Lead SOIC SSOP Pin No.2 Pin No. Mnemonic Description 1 1 V Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the range DD1 of 0.01 µF to 0.1 µF between V and GND. DD1 1 N/A 2 GND Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and 1 connecting both to GND is recommended. 1 N/A 3 NIC Not Internally Connected. Leave this pin floating. N/A 4 NIC Not Internally Connected. Leave this pin floating. 2 5 V Logic Output A. OA 3 6 V Logic Input B. IB N/A 7 EN Refresh and Watchdog Enable 1. In the 20-lead SSOP package, connecting Pin 7 to GND enables 1 1 the input/output refresh and watchdog functionality for Side 1, supporting standard iCoupler operation. Tying Pin 7 to V disables the refresh and watchdog functionality for the lowest power DD1 operation. See the DC Correctness and Low Power Operation section for a description of this mode. EN and EN must be set to the same logic state. 1 2 N/A 8 NIC Not Internally Connected. Leave this pin floating. N/A 9 NIC Not Internally Connected. Leave this pin floating. 4 10 GND Ground 1. Ground reference for Isolator Side 1. In the 20-lead SSOP package, Pin 2 and Pin 10 are 1 internally connected, and connecting both to GND is recommended. 1 5 11 GND Ground 2. Ground reference for Isolator Side 2. In the 20-lead SSOP package, Pin 11 and Pin 19 are 2 internally connected, and connecting both to GND is recommended. 2 N/A 12 NIC Not Internally Connected. Leave this pin floating. N/A 13 NIC Not Internally Connected. Leave this pin floating. N/A 14 EN Refresh and Watchdog Enable 2. In the 20-lead SSOP package, connecting Pin 14 to GND enables 2 2 the input/output refresh and watchdog functionality for Side 2, supporting standard iCoupler operation. Tying Pin 14 to V disables the refresh and watchdog functionality for lowest power DD2 operation. See the DC Correctness and Low Power Operation section for a description of this mode. EN1 and EN2 must be set to the same logic state. 6 15 V Logic Output B. OB 7 16 V Logic Input A. IA N/A 17 NIC Not Internally Connected. Leave this pin floating. N/A 18 NIC Not Internally Connected. Leave this pin floating. N/A 19 GND Ground 2. Ground reference for Isolator Side 2. In the 20-lead SSOP package, Pin 11 and Pin 19 are 2 internally connected, and connecting both to GND is recommended. 2 8 20 V Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the range DD2 of 0.01 µF to 0.1 µF between V and GND. DD2 2 1 Reference AN-1109 for specific layout guidelines. 2 N/A means not applicable. Rev. B | Page 12 of 24

Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 TRUTH TABLES Table 22 provides the truth table (positive logic) for the Table 21. Truth Table Abbreviations ADuM1240 and the ADuM1241, and Table 23 provides the Letter Description truth table (positive logic) for the ADuM1245 and the H High level ADuM1246. For a description of the abbreviations used in the L Low level truth tables, see Table 21. Rising data transition ↑ Falling data transition ↓ X Irrelevant Q Level of V prior to levels being established O OX Z High impedance Table 22. ADuM1240/ADuM1241 Truth Table (Positive Logic)1, 2, 3 EN x VIx Input VDDI State VDDO State State VOx Output Description H Powered Powered L H Normal operation; data is high and refresh is enabled. L Powered Powered L L Normal operation; data is low and refresh is enabled. X Unpowered Powered L H Input unpowered. Outputs are in the default high state. Outputs return to the input state within 150 µs of V power restoration. See the pin function DDI descriptions (Table 19 and Table 20) for details. X Unpowered Powered H Q Input unpowered. Outputs are static at the level that was last sent from O the input or at the power-up level. See the pin function descriptions (Table 19 and Table 20) for details.  Powered Powered H H Output is high after propagation delay, refresh is disabled.  Powered Powered H L Output is low after propagation delay, refresh is disabled. X Powered Unpowered X Z Output unpowered. Output pins are in high impedance state. Outputs return to the input state within 150 µs of V power restoration. See the DDO pin function descriptions (Table 19 and Table 20) for details. 1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). 2 VDDI refers to the power supply on the input side of a given channel (A, B, C, or D). 3 VDDO refers to the power supply on the output side of a given channel (A, B, C, or D). Table 23. ADuM1245/ADuM1246 Truth Table (Positive Logic)1, 2, 3 V Input V State V State EN State V Output Description Ix DDI DDO x Ox H Powered Powered L H Normal operation; data is high and refresh is enabled. L Powered Powered L L Normal operation; data is low and refresh is enabled. X Unpowered Powered L L Input unpowered. Outputs are in the default low state. Outputs return to the input state within 150 µs of V power restoration. See DDI the pin function descriptions (Table 19 and Table 20) for details. X Unpowered Powered H Q Input unpowered. Outputs are static at the level that was last sent O from the input or at the power-up level. See the pin function descriptions (Table 19 and Table 20) for details.  Powered Powered H H Output is high, refresh is disabled.  Powered Powered H L Output is low, refresh is disabled. X Powered Unpowered X Z Output unpowered. Output pins are in high impedance state. Outputs return to input state within 150 µs of V power restoration. DDO See the pin function descriptions (Table 19 and Table 20) for details. 1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). 2 VDDI refers to the power supply on the input side of a given channel (A, B, C, or D). 3 VDDO refers to the power supply on the output side of a given channel (A, B, C, or D). Rev. B | Page 13 of 24

ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 350 140 ON PER INPUT (µA)223050000 1105050 20 40 N PER OUTPUT (µA)11028000 0240 20 40 PTI TIO M P U150 M 60 S U N S O N NT C100 T CO 40 E N R E UR 50 RR 20 C U VDDx INPUT CURRENT C VDDx OUTPUT CURRENT 00 500 DATA R1A0T00E (kbps) 1500 2000 11925-006 00 500 DATA R1A0T00E (kbps) 1500 2000 11925-009 Figure 9. Current Consumption per Input vs. Data Rate for 2.5 V, Figure 12. Current Consumption per Output vs. Data Rate for 3.3 V, ENx = Low Operation ENx = Low Operation 90 160 UT (µA) 80 T (µA)140 1.0 UTP 70 4 NPU120 0.5 TION PER O 5600 020 20 40 PTION PER I10800 00 5 10 MP 40 UM U S S N 60 ON 30 CO NT C 20 ENT 40 E R R R UR 10 CU 20 C VDDx OUTPUT CURRENT VDDx INPUT CURRENT 00 500 DATA R1A0T00E (kbps) 1500 2000 11925-007 00 500 DATA R1A0T00E (kbps) 1500 2000 11925-010 Figure 10. Current Consumption per Output vs. Data Rate for 2.5 V, Figure 13. Current Consumption per Input vs. Data Rate for 2.5 V, ENx = Low Operation ENx = High Operation 400 90 T (µA)350 15 UT (µA) 80 1.0 PTION PER INPU223050000 10050 20 40 TION PER OUTP 567000 0.500 5 10 UM MP 40 S U N150 S CO ON 30 ENT 100 NT C 20 R E R R CU 50 UR 10 C VDDx INPUT CURRENT VDDx OUTPUT CURRENT 00 500 DATA R1A0T00E (kbps) 1500 2000 11925-008 00 500 DATA R1A0T00E (kbps) 1500 2000 11925-011 Figure 11. Current Consumption per Input vs. Data Rate for 3.3 V, Figure 14. Current Consumption per Output vs. Data Rate for 2.5 V, ENx = Low Operation ENx = High Operation Rev. B | Page 14 of 24

Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 200 300 FALLING A)180 RISING µ T ( 1.0 250 U160 P N 0.5 N PER I112400 00 5 10 T (µA)200 O N MPTI100 URRE150 ONSU 80 CDDx100 C 60 I T N RRE 40 50 U C 20 VDDx INPUT CURRENT 00 500 DATA R1A0T00E (kbps) 1500 2000 11925-012 00 0.5 D1A.0TA INPUT1 .V5OLTAGE2 .(0V) 2.5 3.0 11925-015 Figure 15. Current Consumption per Input vs. Data Rate for VDDx = 3.3 V, Figure 18. IDDx Current per Input vs. Data Input Voltage for VDDx = 2.5 V ENx = High Operation 140 10 A) PUT (µ120 1.0 L (µA) 89 N PER OUT10800 0.500 5 10 R CHANNE 67 O E PTI T P 5 URRENT CONSUM 246000 SUPPLY CURREN 1234 C VDDx OUTPUT CURRENT OINUPTUPTUT 00 500 DATA R1A0T00E (kbps) 1500 2000 11925-013 0–40 –20 0 20TEMP4E0RATU6R0E (°C8)0 100 120 140 11925-016 Figure 16. Current Consumption per Output vs. Data Rate for VDDx = 3.3 V, Figure 19. Typical Input and Output Supply Current per Channel vs. ENx = High Operation Temperature for VDDx = 2.5 V, Data Rate = 100 kbps 600 10 FALLING RISING A) 9 500 µ L ( 8 E N A)400 AN 7 NT (µ R CH 6 E E URR300 NT P 5 CDx RRE 4 ID200 CU 3 Y L 100 UPP 2 S 1 OUTPUT 00 1 DATA INPUT2 VOLTAGE (V) 3 4 11925-014 0–40 –20 0 20TEMP4E0RATU6R0E (°C8)0 100 IN12P0UT 140 11925-017 Figure 17. Typical IDDx Current per Input vs. Data Input Voltage for Figure 20. Typical Input and Output Supply Current per Channel vs. VDDx = 3.3 V Temperature for VDDx = 3.3 V, Data Rate = 100 kbps Rev. B | Page 15 of 24

ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet 100 120 A) 90 L (µ 80 100 HANNE 70 TH (ns) 80 RC 60 WID NT PE 50 LTER 60 RRE 40 H FI LY CU 30 GLITC 40 PP 20 U 20 S 10 OUTPUT INPUT 0–40 –20 0 20TEMP4E0RATU6R0E (°C8)0 100 120 140 11925-018 02.0 2.5 TRANSMIT3T.0ER VDDx (V) 3.5 4.0 11925-021 Figure 21. Typical Input and Output Supply Current per Channel vs. Figure 24. Typical Glitch Filter Operation Threshold Temperature for VDDX = 2.5 V, Data Rate = 1000 kbps 100 140 A) 90 120 µ L ( 80 E HANN 70 D (µs)100 R C 60 RIO 80 URRENT PE 4500 EFRESH PE 60 Y C 30 R 40 L PP 20 U 20 S 10 OINUPTUPTUT VVDDDDxx == 23..53VV 0–40 –20 0 20TEMP4E0RATU6R0E (°C8)0 100 120 140 11925-019 0–40 –20 0 20TEMP4E0RATU6R0E (°C8)0 100 120 140 11925-022 Figure 22. Typical Input and Output Supply Current per Channel vs. Figure 25. Typical Refresh Period vs. Temperature for Temperature for VDDX = 3.3 V, Data Rate = 1000 kbps 3.3 V and 2.5 V Operation 140 120 120 100 s) LAY (n100 D (µs) 80 E O N D 80 ERI O P 60 TI H A 60 S G E A R OP EF 40 R 40 R P 20 20 VDDx = 2.5V VDDx = 3.3V 0–40 –20 0 20TEMP4E0RATU6R0E (°C8)0 100 120 140 11925-020 02.0 2.5 VDDx VO3L.0TAGE (V) 3.5 4.0 11925-023 Figure 23. Typical Propagation Delay vs. Temperature for Figure 26. Typical Refresh Period vs. VDDx Voltage VDDx = 3.3 V or VDDx = 2.5 V Rev. B | Page 16 of 24

Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 APPLICATIONS INFORMATION PCB LAYOUT Channel to channel matching refers to the maximum amount the propagation delay differs between channels within a single The ADuM1240/ADuM1241/ADuM1245/ADuM1246 digital component of the ADuM1240/ADuM1241/ADuM1245/ isolators require no external interface circuitry for the logic ADuM1246. interfaces. Power supply bypassing is strongly recommended at both the input and output supply pins: V and V (see Propagation delay skew refers to the maximum amount the DD1 DD2 Figure 27). Maintain the capacitor value between 0.01 μF and propagation delay differs between multiple ADuM1240/ 0.1 μF and for best results, ensure that the total lead length ADuM1241/ADuM1245/ADuM1246 components operating between both ends of the capacitor and the input power supply under the same conditions. does not exceed 20 mm. DC CORRECTNESS AND LOW POWER OPERATION With proper PCB design choices, these digital isolators readily Standard Operating Mode meet CISPR 22 Class A (and FCC Class A) emissions standards, Positive and negative logic transitions at the isolator input cause as well as the more stringent CISPR 22 Class B (and FCC Class B) narrow (~1 ns) pulses to be sent to the decoder using the standards in an unshielded environment. Refer to AN-1109 for transformer. The decoder is bistable and is, therefore, either set PCB related electromagnetic interference (EMI) mitigation or reset by the pulses, indicating input logic transitions. When techniques, including board layout and stack up issues. refresh and watchdog functions are enabled, by pulling EN and 1 VDD1 VDD2 EN2 low, in the absence of logic transitions at the input for more GNNDIC1 GNINCD2 than ~140 μs, a periodic set of refresh pulses, indicative of the NIC NIC correct input state, is sent to ensure dc correctness at the output. If VIA/VOA VOA/VIA the decoder receives no internal pulses of more than approximately VIB VOB EN1 EN2 200 μs, the device assumes that the input side is unpowered or NIC NIC nonfunctional, in which case, the isolator watchdog circuit NIC NIC NIGC N=D N1OT INTERNALLY CONNECTED. GND2 11925-024 faos ricne tsh teh Ae DouutMpu1t2 t4o0 aa nddef aAuDltu sMtat1e2. 4T1h vee drseifoanuslt, ostra ltoew is, aesi tihne trh hei gh, Figure 27. Recommended PCB Layout, 20-Lead SSOP (RS-20) ADuM1245 and ADuM1246 versions. VDD1 VDD2 Low Power Operating Mode VIAG/VNVODIAB1 VVGOONABD/V2IA 11925-124 Fwoartc thhdeo lgo wfuensct tpioonws eorf cthoen sAuDmupMtio12n4, 0d/iAsaDbuleM th1e2 4r1ef/AreDshu Man1d2 45/ Figure 28. Recommended PCB Layout, 8-Lead SOIC (R-8) ADuM1246 by pulling EN and EN to logic high. These control 1 2 For applications involving high common-mode transients, it is pins must be set to the same value on each side of the component important to minimize board coupling across the isolation barrier. for proper operation. Furthermore, design the board layout so that any coupling that In this mode, the current consumption of the chip drops to the does occur equally affects all pins on a given component side. microampere range. However, be careful when using this mode, Failure to ensure this equal capacitive coupling of pins can because dc correctness is no longer guaranteed at startup. For cause voltage differentials between pins exceeding the absolute example, if the following sequence of events occurs: maximum ratings of the device, thereby leading to latch-up or 1. Power is applied to Side 1. permanent damage. 2. A high level is asserted on the VIA input. PROPAGATION DELAY RELATED PARAMETERS 3. Power is applied to Side 2. Propagation delay is a parameter that describes the time it takes The high on V is not automatically transferred to the Side 2 IA a logic signal to propagate through a component. The input to V , and there can be a level mismatch that is not corrected until a OA output propagation delay time for a high to low transition can transition occurs at V . When power is stable on each side, and a IA differ from the propagation delay time of a low to high transition. transition occurs on the input of the channel, the input and output state of that channel is correctly matched. This contingency can INPUT(VIx) 50% be resolved in several ways, such as sending dummy data, or tPLH tPHL toggling refresh on for a short period to force synchronization after OUTPUT(VOx) 50% 11925-025 turn on. Figure 29. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values, and an indication of how accurately the timing of the input signal is preserved. Rev. B | Page 17 of 24

ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet Recommended Input Voltage for Low Power Operation s) 1000 s u a The ADuM1240/ADuM1241/ADuM1245/ADuM1246 kg implement Schmitt trigger input buffers so that the devices UX( 100 L operate cleanly in low data rate, or in noisy environments. Schmitt C F TI 10 triggers allow a small amount of shoot through current when the E N G input voltage is not approximate to either VDDx or GNDx levels. MA 1 Shoot through is possible because the two transistors are both E L B slightly on when input voltages are in the middle of the supply A W 0.1 range. For many digital devices, this leakage is not a large portion LO L A of the total supply current and cannot be noticed; however, in the M 0.01 U ultralow power M XI AcaDn ubMe l1a2r4g0er/ AthDaunM th1e2 t4o1t/aAl DopueMra1ti2n4g5 c/AurDreunMt o1f2 4th6e, tdheivs ilceea kanagde MA 0.0011k 1M0kAGNETIC1 F00IEkLD FREQ1UMENCY (Hz1)0M 100M 11925-026 must not be ignored. Figure 30. Maximum Allowable External Magnetic Flux Density To achieve optimum power consumption with the ADuM1240/ For example, at a magnetic field frequency of 1 MHz, the maxi- ADuM1241/ADuM1245/ADuM1246, always drive the inputs as mum allowable magnetic field of 0.5 kgauss induces a voltage of near to V or GND levels as possible. Figure 17 and Figure 18 DDx x 0.25 V at the receiving coil. This is about 50% of the sensing illustrate the shoot through leakage of an input; therefore, whereas threshold and does not cause a faulty output transition. If such the logic thresholds of the input are standard CMOS levels, an event occurs, with the worst case polarity, during a transmitted optimum power performance is achieved when the input logic pulse, it would reduce the received pulse from >1.0 V to 0.75 V. levels are driven within 0.5 V of either V or GND levels. DDx x This is still higher than the 0.5 V sensing threshold of the decoder. MAGNETIC FIELD IMMUNITY The preceding magnetic flux density values correspond to specific The limitation on the magnetic field immunity of the device is current magnitudes at given distances away from the ADuM1240 set by the condition in which, induced voltage in the transformer transformers. Figure 31 expresses these allowable current magni- receiving coil is sufficiently large, to either falsely set or reset the tudes as a function of frequency for selected distances. The decoder. The following analysis defines such conditions. The ADuM1240 is very insensitive to external fields. Only extremely ADuM1240 is examined in a 3 V operating condition, because it large, high frequency currents, very close to the component, represents the typical mode of operation for these products. could potentially be a concern. For the 1 MHz example noted, the user would have to place a 1.2 kA current 5 mm away from The pulses at the transformer output have an amplitude greater the ADuM1240 to affect component operation. than 1.5 V. The decoder has a sensing threshold of about 1.0 V, therefore establishing a 0.5 V margin in which induced voltages 1000 are tolerated. The voltage induced across the receiving coil is A) DISTANCE = 1m k given by T( 100 N E V = (−dβ/dt)∑πrn2; n = 1, 2, …, N URR C 10 where: E L B β is the magnetic flux density. A W DISTANCE = 100mm rn is the radius of the nth turn in the receiving coil. LO 1 L N is the number of turns in the receiving coil. A UM DISTANCE = 5mm M Given the geometry of the receiving coil in the ADuM1240, and XI 0.1 A an imposed requirement that the induced voltage be, at most, M 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 30. 0.011k 1M0kAGNETIC1 F00IEkLD FREQ1UMENCY (Hz1)0M 100M 11925-027 Figure 31. Maximum Allowable Current for Various Currents to ADuM1240 Spacings Note that at combinations of strong magnetic field and high frequency, any loops formed by PCB traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Avoid PCB structures that form loops. Rev. B | Page 18 of 24

Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 POWER CONSUMPTION The values shown in Table 18 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the The supply current with refresh enabled at a given channel of maximum CSA/VDE approved working voltages. In many cases, the ADuM1240/ADuM1241/ADuM1245/ADuM1246 isolators, the approved working voltage is higher than 50-year service life is a function of the supply voltage, the data rate of the channel, voltage. Operation at these high working voltages can lead to and the output load of the channel. shortened insulation life, in some cases. For each input channel, the supply current is given by The insulation lifetime of the ADuM1240/ADuM1241/ I = I f ≤ 0.5 f DDI DDI (Q) r ADuM1245/ADuM1246 depends on the voltage waveform type I = I × (2f − f) + I f > 0.5 f imposed across the isolation barrier. The iCoupler insulation DDI DDI (D) r DDI (Q) r structure degrades at different rates, depending on whether the For each output channel, the supply current is given by waveform is bipolar ac, unipolar ac, or dc. Figure 19, Figure 20, I = I f ≤ 0.5 f DDO DDO (Q) r and Figure 21 illustrate these different isolation voltage waveforms. I = (I + (0.5 × 10−3) × C × V ) × (2f − f) + I DDO DDO (D) L DDO r DDO (Q) Bipolar ac voltage is the most stringent environment. The goal f > 0.5 f r of a 50-year operating lifetime, under the ac bipolar condition, where: determines the Analog Devices recommended maximum I and I are the input and output dynamic supply working voltage. DDI (D) DDO (D) currents per channel (mA/Mbps). In the case of unipolar ac or dc voltage, the stress on the insulation C is the output load capacitance (pF). L is significantly lower. This allows operation at higher working V is the output supply voltage (V). DDO voltages, while still achieving a 50-year service life. The working f is the input logic signal frequency (MHz); it is half the input voltages listed in Table 18 can be applied while maintaining the 50- data rate, expressed in units of Mbps. year minimum lifetime, provided the voltages conform to either the f is the input stage refresh rate (Mbps) = 1/T (µs). r r unipolar ac or dc voltage case. Treat any cross-insulation voltage I and I are the specified input and output quiescent DDI (Q) DDO (Q) waveform that does not conform to Figure 33 or Figure 34 as a supply currents (mA). bipolar ac waveform, and limit peak voltage to the 50-year lifetime To calculate the total V and V supply current, the supply voltage value listed in Table 18. DD1 DD2 currents for each input and output channel corresponding to Note that the voltage presented in Figure 33 is shown as sinusoidal V and V are calculated and totaled. Figure 9 through DD1 DD2 for illustration purposes only. It represents any voltage waveform Figure 16 show per channel supply currents as a function of varying between 0 V and some limiting value. The limiting value data rate for an unloaded output condition. can be positive or negative, but the voltage must not cross 0 V. INSULATION LIFETIME RATED PEAK VOLTAGE Avolllt aingseu sltarteisosn fo srt rau scutfufriceise netvleyn lotunagl lpye drieogdr.a Tdhee, wrahtee no fs iunbsjuelcatteiodn t o 0V 11925-028 degradation is dependent on the characteristics of the voltage Figure 32. Bipolar AC Waveform waveform applied across the insulation. In addition to the testing RATED PEAK VOLTAGE performed by the regulatory agencies, Analog Devices carries othuet ianns uexlatteinosni vsetr suectt oufr ee vwailtuhaitnio tnhse to determine the lifetime of 0V 11925-029 Figure 33. Unipolar AC Waveform ADuM1240/ADuM1241/ADuM1245/ADuM1246. RATED PEAK VOLTAGE Analog Devices performs accelerated life testing using voltage levels hfaicgthoerrs tfhoar ns etvheer raal toepde croatnitnign ucoounsd iwtioornksi nagre v doelttaegrme. iAncecde. lTerhaetisoen 0V 11925-030 factors allow calculation of the time to failure at the actual working Figure 34. DC Waveform voltage. Rev. B | Page 19 of 24

ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA R(CINEOFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 35. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 7.50 7.20 6.90 20 11 5.60 5.30 5.00 8.20 7.80 1 7.40 10 1.85 0.25 2.00 MAX 1.75 0.09 1.65 COPLA0N.0A5R MITIYN 0.65 BSC 00..3282 SPLEAATNIENG 840°°° 000...975555 0.10 COMPLIANTTO JEDEC STANDARDS MO-150-AE 060106-A Figure 36. 20-Lead Shrink Small Outline Package [SSOP] (RS-20) Dimensions shown in millimeters Rev. B | Page 20 of 24

Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 ORDERING GUIDE No. No. Maximum Maximum Output of Inputs, of Inputs, Data Rate Propagation Default Temperature Package Package Model1, 2 V Side V Side (Mbps) Delay, 3.3 V State Range Description Option DD1 DD2 ADuM1240ARZ 2 0 2 180 High −40°C to +125°C 8-Lead SOIC_N R-8 ADuM1240ARZ-RL7 2 0 2 180 High −40°C to +125°C 8-Lead SOIC_N R-8 ADuM1240ARSZ 2 0 2 180 High −40°C to +125°C 20-Lead SSOP RS-20 ADuM1240ARSZ-RL7 2 0 2 180 High −40°C to +125°C 20-Lead SSOP RS-20 ADuM1241ARZ 1 1 2 180 High −40°C to +125°C 8-Lead SOIC_N R-8 ADuM1241ARZ-RL7 1 1 2 180 High −40°C to +125°C 8-Lead SOIC_N R-8 ADuM1241ARSZ 1 1 2 180 High −40°C to +125°C 20-Lead SSOP RS-20 ADuM1241ARSZ-RL7 1 1 2 180 High −40°C to +125°C 20-Lead SSOP RS-20 ADuM1245ARZ 2 0 2 180 Low −40°C to +125°C 8-Lead SOIC_N R-8 ADuM1245ARZ-RL7 2 0 2 180 Low −40°C to +125°C 8-Lead SOIC_N R-8 ADuM1245ARSZ 2 0 2 180 Low −40°C to +125°C 20-Lead SSOP RS-20 ADuM1245ARSZ-RL7 2 0 2 180 Low −40°C to +125°C 20-Lead SSOP RS-20 ADuM1246ARZ 1 1 2 180 Low −40°C to +125°C 8-Lead SOIC_N R-8 ADuM1246ARZ-RL7 1 1 2 180 Low −40°C to +125°C 8-Lead SOIC_N R-8 ADuM1246ARSZ 1 1 2 180 Low −40°C to +125°C 20-Lead SSOP RS-20 ADuM1246ARSZ-RL7 1 1 2 180 Low −40°C to +125°C 20-Lead SSOP RS-20 1 Z = RoHS Compliant Part. 2 Tape and reel is available. The addition of the -RL7 suffix indicates that the product is shipped on 7” tape and reel. Rev. B | Page 21 of 24

ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet NOTES Rev. B | Page 22 of 24

Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 NOTES Rev. B | Page 23 of 24

ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet NOTES ©2013–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11925-0-9/16(B) Rev. B | Page 24 of 24

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