Dual-Channel Digital Isolator Data Sheet ADuM1210 FEATURES GENERAL DESCRIPTION Narrow body, RoHS-compliant, 8-lead SOIC The ADuM12101 is a dual-channel, digital isolator based on Low power operation Analog Devices, Inc., iCoupler® technology. Combining high 5 V operation speed CMOS and monolithic transformer technology, this 1.1 mA per channel maximum @ 0 Mbps to 2 Mbps isolation component provides outstanding performance 3.7 mA per channel maximum @ 10 Mbps characteristics superior to alternatives such as optocoupler 3 V operation devices. 0.8 mA per channel maximum @ 0 Mbps to 2 Mbps By avoiding the use of LEDs and photodiodes, iCoupler devices 2.2 mA per channel maximum @ 10 Mbps remove the design difficulties commonly associated with opto- 3 V/5 V level translation couplers. The concerns of the typical optocoupler regarding High temperature operation: 105°C uncertain current transfer ratios, nonlinear transfer functions, High data rate: dc to 10 Mbps (NRZ) and temperature and lifetime effects are eliminated with the Precise timing characteristics simple iCoupler digital interfaces and stable performance 3 ns maximum pulse width distortion characteristics. The need for external drivers and other discrete 3 ns maximum channel-to-channel matching components is eliminated with iCoupler products. Furthermore, High common-mode transient immunity: >25 kV/μs iCoupler devices consume one-tenth to one-sixth the power of Safety and regulatory approvals optocouplers at comparable signal data rates. UL recognition 2500 V rms for 1 minute per UL 1577 The ADuM1210 isolator provides two independent isolation CSA Component Acceptance Notice #5A channels operable with the supply voltage on either side, VDE certificate of conformity ranging from 2.7 V to 5.5 V. This provides compatibility with DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 lower voltage systems and enables voltage translation V = 560 V peak functionality across the isolation barrier. In addition, the IORM ADuM1210 provides low pulse width distortion (<3 ns) and APPLICATIONS tight channel-to-channel matching (<3 ns). Unlike other opto- Size-critical multichannel isolation coupler alternatives, the ADuM1210 isolator has a patented SPI interface/data converter isolation refresh feature that ensures dc correctness in the absence of RS-232/RS-422/RS-485 transceiver isolation input logic transitions and during power-up/power-down Digital field bus isolation conditions. Furthermore, as an alternative to the ADuM1200 Gate drive interface dual-channel digital isolator that defaults to an output high condition, the ADuM1210 outputs default to a logic low state when input power is off. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329. FUNCTIONAL BLOCK DIAGRAM VDD1 1 8 VDD2 VIA 2 ENCODE DECODE 7 VOA VIB 3 ENCODE DECODE 6 VOB GND1 4 5 GND2 05459-001 Figure 1. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2005–2012 Analog Devices, Inc. All rights reserved.

ADuM1210 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Recommended Operating Conditions .................................... 10  Applications ....................................................................................... 1  Absolute Maximum Ratings ......................................................... 11  General Description ......................................................................... 1  ESD Caution................................................................................ 11  Functional Block Diagram .............................................................. 1  Pin Configuration and Function Descriptions ........................... 12  Revision History ............................................................................... 2  Typical Performance Characteristics ........................................... 13  Specifications ..................................................................................... 3  Applications Information .............................................................. 14  Electrical Characteristics—5 V Operation................................ 3  PC Board Layout ........................................................................ 14  Electrical Characteristics—3 V Operation................................ 5  Propagation Delay-Related Parameters ................................... 14  Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V DC Correctness and Magnetic Field Immunity ........................... 14  Operation ....................................................................................... 7  Power Consumption .................................................................. 15  Package Characteristics ............................................................... 9  Insulation Lifetime ..................................................................... 15  Regulatory Information ............................................................... 9  Outline Dimensions ....................................................................... 17  Insulation and Safety-Related Specifications ............................ 9  Ordering Guide .......................................................................... 17  DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 Insulation Characteristics .......................................................... 10  REVISION HISTORY 3/07—Rev. A to Rev. B 3/12—Rev. C to Rev. D Changes to Table 1 ............................................................................. 3 Created Hyperlink for Safety and Regulatory Approvals Entry in Features Section ................................................................. 1 2/06—Rev. 0 to Rev. A Change to PC Board Layout Section ............................................ 14 Updated Format .................................................................. Universal Added Note 1 ..................................................................................... 1 6/07—Rev. B to Rev. C Changes to Absolute Maximum Ratings ..................................... 11 Updated VDE Certification Throughout ...................................... 1 Changes to DC Correctness and Magnetic Field Changes to Features, Applications, and Note 1 ............................ 1 Immunity Section ........................................................................... 14 Changes to DC Specifications in Table 1 ....................................... 3 Changes to DC Specifications in Table 2 ....................................... 5 7/05—Revision 0: Initial Version Changes to DC Specifications in Table 3 ....................................... 7 Added Endnote 2 to Table 4 ............................................................ 9 Changes to Regulatory Information Section ................................ 9 Changes to Table 7 .......................................................................... 10 Added Table 10 ............................................................................... 11 Added Insulation Lifetime Section .............................................. 15 Rev. D | Page 2 of 20

Data Sheet ADuM1210 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION 4.5 V ≤ V ≤ 5.5 V, 4.5 V ≤ V ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range, DD1 DD2 unless otherwise noted. All typical specifications are at T = 25°C, V = V = 5 V. All voltages are relative to their respective ground. A DD1 DD2 Table 1. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, per Channel, I 0.50 0.60 mA DDI (Q) Quiescent Output Supply Current, per Channel, I 0.19 0.25 mA DDO (Q) Quiescent Total Supply Current, Two Channels1 DC to 2 Mbps V Supply Current I 1.1 1.4 mA DC to 1 MHz logic signal frequency DD1 DD1 (Q) V Supply Current I 0.5 0.8 mA DC to 1 MHz logic signal frequency DD2 DD2 (Q) 10 Mbps V Supply Current I 4.3 5.5 mA 5 MHz logic signal frequency DD1 DD1 (10) V Supply Current I 1.3 2.0 mA 5 MHz logic signal frequency DD2 DD2 (10) Input Currents I , I −10 +0.01 +10 μA 0 V ≤ V , V ≤ V IA IB IA IB DD1 Logic High Input Threshold V 0.7 × V V IH DD1 Logic Low Input Threshold V 0.3 × V V IL DD1 Logic High Output Voltages V , V V − 0.1 5.0 V I = −20 μA, V = V OAH OBH DD2 Ox Ix IxH V − 0.5 4.8 V I = −4 mA, V = V DD2 Ox Ix IxH Logic Low Output Voltages V , V 0.0 0.1 V I = 20 μA, V = V OAL OBL Ox Ix IxL 0.04 0.1 V I = 400 μA, V = V Ox Ix IxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS Minimum Pulse Width2 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 20 50 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 15 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 3 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 15 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 Output Rise/Fall Time (10% to 90%) t/t 2.5 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity |CM | 25 35 kV/μs V = V , V = 1000 V, H Ix DD1 CM at Logic High Output7 transient magnitude = 800 V Common-Mode Transient Immunity |CM| 25 35 kV/μs V = 0 V, V = 1000 V, L Ix CM at Logic Low Output7 transient magnitude = 800 V Refresh Rate f 1.2 Mbps r Input Dynamic Supply Current, I 0.19 mA/Mbps DDI (D) per Channel8 Output Dynamic Supply Current, I 0.05 mA/Mbps DDO (D) per Channel8 1 Supply current values are for both channels running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total VDD1 and VDD2 supply currents as a function of data rate. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. Rev. D | Page 3 of 20

ADuM1210 Data Sheet 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate. Rev. D | Page 4 of 20

Data Sheet ADuM1210 ELECTRICAL CHARACTERISTICS—3 V OPERATION 2.7 V ≤ V ≤ 3.6 V, 2.7 V ≤ V ≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operating range, DD1 DD2 unless otherwise noted. All typical specifications are at T = 25°C, V = V = 3.0 V. All voltages are relative to their respective ground. A DD1 DD2 Table 2. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, per Channel, I 0.26 0.35 mA DDI (Q) Quiescent Output Supply Current, per Channel, I 0.11 0.20 mA DDO (Q) Quiescent Total Supply Current, Two Channels1 DC to 2 Mbps V Supply Current I 0.6 1.0 mA DC to 1 MHz logic signal frequency DD1 DD1 (Q) V Supply Current I 0.2 0.6 mA DC to 1 MHz logic signal frequency DD2 DD2 (Q) 10 Mbps V Supply Current I 2.2 3.4 mA 5 MHz logic signal frequency DD1 DD1 (10) V Supply Current I 0.7 1.1 mA 5 MHz logic signal frequency DD2 DD2 (10) Input Currents I , I −10 +0.01 +10 μA 0 V ≤ V , V , ≤ V IA IB IA IB DD1 Logic High Input Threshold V 0.7 × V V IH DD1 Logic Low Input Threshold V 0.3 × V V IL DD1 Logic High Output Voltages V , V V − 0.1 3.0 V I = −20 μA, V = V OAH OBH DD2 Ox Ix IxH V − 0.5 2.8 V I = −4 mA, V = V DD2 Ox Ix IxH Logic Low Output Voltages V , V 0.0 0.1 V I = 20 μA, V = V OAL OBL Ox Ix IxL 0.04 0.1 V I = 400 μA, V = V Ox Ix IxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS Minimum Pulse Width2 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 20 60 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 22 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 3 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 22 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 Output Rise/Fall Time (10% to 90%) t/t 3.0 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity |CM | 25 35 kV/μs V = V , V = 1000 V, H Ix DD1 CM at Logic High Output7 transient magnitude = 800 V Common-Mode Transient Immunity |CM| 25 35 kV/μs V = 0 V, V = 1000 V, L Ix CM at Logic Low Output7 transient magnitude = 800 V Refresh Rate f 1.1 Mbps r Input Dynamic Supply Current, I 0.10 mA/Mbps DDI (D) per Channel8 Output Dynamic Supply Current, I 0.03 mA/Mbps DDO (D) per Channel8 1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total VDD1 and VDD2 supply currents as a function of data rate. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. Rev. D | Page 5 of 20

ADuM1210 Data Sheet 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate. Rev. D | Page 6 of 20

Data Sheet ADuM1210 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION 5 V/3 V operation: 4.5 V ≤ V ≤ 5.5 V, 2.7 V ≤ V ≤ 3.6 V. 3 V/5 V operation: 2.7 V ≤ V ≤ 3.6 V, 4.5 V ≤ V ≤ 5.5 V. All minimum/ DD1 DD2 DD1 DD2 maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at T = 25°C; V = 3.0 V, V = 5.0 V; or V = 5.0 V, V = 3.0 V. All voltages are relative to their respective ground. A DD1 DD2 DD1 DD2 Table 3. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, per Channel, I mA DDI (Q) Quiescent 5 V/3 V Operation 0.50 0.6 mA 3 V/5 V Operation 0.26 0.35 mA Output Supply Current, per Channel, I mA DDO (Q) Quiescent 5 V/3 V Operation 0.11 0.20 mA 3 V/5 V Operation 0.19 0.25 mA Total Supply Current, Two Channels1 DC to 2 Mbps V Supply Current I DD1 DD1 (Q) 5 V/3 V Operation 1.1 1.4 mA DC to 1 MHz logic signal frequency 3 V/5 V Operation 0.6 1.0 mA DC to 1 MHz logic signal frequency V Supply Current I DD2 DD2 (Q) 5 V/3 V Operation 0.2 0.6 mA DC to 1 MHz logic signal frequency 3 V/5 V Operation 0.5 0.8 mA DC to 1 MHz logic signal frequency 10 Mbps V Supply Current I DD1 DD1 (10) 5 V/3 V Operation 4.3 5.5 mA 5 MHz logic signal frequency 3 V/5 V Operation 2.2 3.4 mA 5 MHz logic signal frequency V Supply Current I DD2 DD2 (10) 5 V/3 V Operation 0.7 1.1 mA 5 MHz logic signal frequency 3 V/5 V Operation 1.3 2.0 mA 5 MHz logic signal frequency Input Currents I , I −10 +0.01 +10 μA 0 V ≤ V , V ≤ V IA IB IA IB DD1 Logic High Input Threshold V 0.7 × V V IH DD1 Logic Low Input Threshold V 0.3 × V V IL DD1 Logic High Output Voltages V , V V − 0.1 V V I = −20 μA, V = V OAH OBH DD2 DD2 Ox Ix IxH V − 0.5 V − 0.2 V I = −4 mA, V = V DD2 DD2 Ox Ix IxH Logic Low Output Voltages V , V 0.0 0.1 V I = 20 μA, V = V OAL OBL Ox Ix IxL 0.04 0.1 V I = 400 μA, V = V Ox Ix IxL 0.2 0.4 V I = 4 mA, V = V Ox Ix IxL SWITCHING SPECIFICATIONS Minimum Pulse Width2 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 10 Mbps C = 15 pF, CMOS signal levels L Propagation Delay4 t , t 15 55 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |4 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature 5 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew5 t 22 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 3 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels6 Channel-to-Channel Matching, t 22 ns C = 15 pF, CMOS signal levels PSKOD L Opposing-Directional Channels6 Output Rise/Fall Time (10% to 90%) t/t C = 15 pF, CMOS signal levels R F L 5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns Rev. D | Page 7 of 20

ADuM1210 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions Common-Mode Transient Immunity |CM | 25 35 kV/μs V = V , V = 1000 V, H Ix DD1 CM at Logic High Output7 transient magnitude = 800 V Common-Mode Transient Immunity |CM| 25 35 kV/μs V = 0 V, V = 1000 V, L Ix CM at Logic Low Output7 transient magnitude = 800 V Refresh Rate f r 5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps Input Dynamic Supply Current, I DDI (D) per Channel8 5 V/3 V Operation 0.19 mA/Mbps 3 V/5 V Operation 0.10 mA/Mbps Output Dynamic Supply Current, I DDO (D) per Channel8 5 V/3 V Operation 0.03 mA/Mbps 3 V/5 V Operation 0.05 mA/Mbps 1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total VDD1 and VDD2 supply currents as a function of data rate. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate. Rev. D | Page 8 of 20

Data Sheet ADuM1210 PACKAGE CHARACTERISTICS Table 4. Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input-to-Output)1 R 1012 Ω I-O Capacitance (Input-to-Output)1 C 1.0 pF f = 1 MHz I-O Input Capacitance2 C 4.0 pF I IC Junction-to-Case Thermal Resistance Side 1 θ 46 °C/W Thermocouple located at center of package underside JCI Side 2 θ 41 °C/W JCO 1 The device is considered a 2-terminal device; Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together. 2 Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM1210 is approved by the organizations listed in Table 5. See Table 10 and the Insulation Lifetime section for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 5. UL CSA VDE Recognized Under 1577 Approved under CSA Component Acceptance Notice #5A Certified according to DIN V VDE V 0884-10 Component Recognition (VDE V 0884-10): 2006-122 Program1 Single/Basic 2500 V rms Basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms Reinforced insulation, 560 V peak Isolation Voltage (566 peak) maximum working voltage Functional insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage File E214100 File 205078 File 2471900-4880-0001 1 In accordance with UL 1577, each ADuM1210 is proof-tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA). 2 In accordance with DIN V VDE V 0884-10, each ADuM1210 is proof-tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 4.90 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 4.01 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Rev. D | Page 9 of 20

ADuM1210 Data Sheet DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS This isolator is suitable for reinforced isolation within the safety limit data only. Maintenance of the safety data is ensured by protective circuits. Note that the asterisk (*) marked on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage. Table 7. Description Conditions Symbol Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V 560 V peak IORM Input-to-Output Test Voltage, Method B1 V × 1.875 = V , 100% production test, t = 1 sec, V 1050 V peak IORM PR m PR partial discharge < 5 pC Input-to-Output Test Voltage, Method A V × 1.6 = V , t = 60 sec, partial discharge < 5 pC V IORM PR m PR After Environmental Tests Subgroup 1 896 V peak After Input and/or Safety Test Subgroup 2 V × 1.2 = V , t = 60 sec, partial discharge < 5 pC 672 V peak IORM PR m and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, t = 10 seconds V 4000 V peak TR TR Safety-Limiting Values Maximum value allowed in the event of a failure; see Figure 2 Case Temperature T 150 °C S Side 1 Current I 160 mA S1 Side 2 Current I 170 mA S2 Insulation Resistance at T V = 500 V R >109 Ω S IO S 200 RECOMMENDED OPERATING CONDITIONS 180 Table 8. A) 160 Parameter Symbol Min Max Unit m T ( 140 Operating Temperature T −40 +105 °C EN SIDE #1 SIDE #2 A RR 120 Supply Voltages1 VDD1, VDD2 2.7 5.5 V U G C 100 Input Signal Rise and Fall Times 1.0 ms N MITI 80 1 All voltages are relative to their respective ground. See the DC Correctness and TY-LI 60 Mmaaggnneettiicc Ffiieelldd sI.m munity section for information on immunity to external E F 40 A S 20 00 50CASE TEMP1E0R0ATURE (°C)150 200 05459-002 Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values on Case Temperature, per DIN V VDE V 0884-10 Rev. D | Page 10 of 20

Data Sheet ADuM1210 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses above those listed under Absolute Maximum Ratings Table 9. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any other conditions above those indicated in the operational Storage Temperature (T ) Range −55°C to +150°C ST section of this specification is not implied. Exposure to absolute Ambient Operating Temperature −40°C to +105°C (T ) Range maximum rating conditions for extended periods may affect A Supply Voltages (V , V )1 −0.5 V to +7.0 V device reliability. DD1 DD2 Input Voltage (VIA, VIB)1 −0.5 V to VDDI + 0.5 V Output Voltage (VOA, VOB)1 −0.5 V to VDDO + 0.5 V ESD CAUTION Average Output Current, Per Pin (I )2 −35 mA to +35 mA O Common-Mode Transients (CM, CM )3 −100 kV/μs to +100 kV/μs L H 1 All voltages are relative to their respective ground. 2 See Figure 2 for maximum rated current values for various temperatures. 3 Refers to common-mode transients across the insulation barrier. Common- mode transients exceeding the absolute maximum rating may cause latch-up or permanent damage. Table 10. Maximum Continuous Working Voltage1 Parameter Max Unit Constraint AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime AC Voltage, Unipolar Waveform Functional Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Basic Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 DC Voltage Functional Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Basic Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Rev. D | Page 11 of 20

ADuM1210 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD1 1 8 VDD2 ADuM1210 VIA 2 7 VOA GNVDIB1 34 (NToOt Pto V SIEcaWle) 65 VGONBD2 05459-003 Figure 3. Pin Configuration Table 11. Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. DD1 2 V Logic Input A. IA 3 V Logic Input B. IB 4 GND Ground 1. Ground reference for Isolator Side 1. 1 5 GND Ground 2. Ground reference for Isolator Side 2. 2 6 V Logic Output B. OB 7 V Logic Output A. OA 8 V Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V. DD2 Table 12. ADuM1210 Truth Table (Positive Logic) V Input V Input V State V State V Output V Output Description IA IB DD1 DD2 OA OB H H Powered Powered H H L L Powered Powered L L H L Powered Powered H L L H Powered Powered L H X X Unpowered Powered L L Outputs return to the input state within 1 μs of V power restoration. DDI X X Powered Unpowered Indeterminate Indeterminate Outputs return to the input state within 1 μs of V power restoration. DDO Rev. D | Page 12 of 20

Data Sheet ADuM1210 TYPICAL PERFORMANCE CHARACTERISTICS 10 20 8 15 A) m NEL ( 6 mA) NT/CHAN 4 URRENT ( 10 5V RE 5V C R U 3V 5 C 2 3V 00 10DATA RATE (Mbps)20 30 05459-004 00 10DATA RATE (Mbps)20 30 05459-007 Figure 4. Typical Input Supply Current per Channel vs. Data Rate Figure 7. Typical VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation for 5 V and 3 V Operation 4 4 3 3 A) m NEL ( mA) T/CHAN 2 RRENT ( 2 RREN 5V CU 5V 3V U 1 1 C 3V 00 10DATA RATE (Mbps)20 30 05459-005 00 10DATA RATE (Mbps)20 30 05459-008 Figure 5. Typical Output Supply Current per Channel vs. Data Rate Figure 8. Typical VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation for 5 V and 3 V Operation (No Output Load) 4 3 A) m L ( E 5V N N A 2 H C T/ N E R UR 1 3V C 00 10DATA RATE (Mbps)20 30 05459-006 Figure 6. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load) Rev. D | Page 13 of 20

ADuM1210 Data Sheet APPLICATIONS INFORMATION PC BOARD LAYOUT The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, The ADuM1210 digital isolator requires no external interface therefore establishing a 0.5 V margin in which induced voltages circuitry for the logic interfaces. Power supply bypassing is can be tolerated. The voltage induced across the receiving coil is strongly recommended at the input and output supply pins. The given by capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input V = (−dβ/dt) ∑ π rn2; n = 1, 2, … , N power supply pin should not exceed 20 mm. where: See the AN-1109 Application Note for board layout guidelines. β is the magnetic flux density (gauss). r is the radius of the nth turn in the receiving coil (cm). PROPAGATION DELAY-RELATED PARAMETERS n N is the number of turns in the receiving coil. Propagation delay is a parameter that describes the time it takes Given the geometry of the receiving coil in the ADuM1210 and a logic signal to propagate through a component. The propagation an imposed requirement that the induced voltage be at most delay to a logic low output can differ from the propagation 50% of the 0.5 V margin at the decoder, a maximum allowable delay to a logic high output. magnetic field is calculated, as shown in Figure 10. INPUT (VIx) 50% 100 tPLH tPHL LUX OUTPUT (VOx) 50% 05459-009 NETIC F 10 Figure 9. Propagation Delay Parameters AGss) Mu 1 Pulse width distortion is the maximum difference between the LE kga tawccou praroteplya gtahteio innp duetl asyig vnaallu’se tsi manidn gis i sa np riensdeircvaetdio. n of how ALLOWABDENSITY (0.1 Channel-to-channel matching refers to the maximum amount UM M 0.01 that the propagation delay differs between channels within a XI A single ADuM1210 component. M Pthreo pparogaptaigoant idoenla dye slakye wd irfefefersr sb teot wtheee nm maxuilmtipulme AamDuouMn1t 2t0hxa t 0.0011k 10kMAGNETI1C0 0FkIELD FREQ1MUENCY (Hz1)0M 100M 05459-010 components operating under the same conditions. Figure 10. Maximum Allowable External Magnetic Flux Density DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a Positive and negative logic transitions at the isolator input cause voltage of 0.25 V at the receiving coil. This is about 50% of the narrow (~1 ns) pulses to be sent to the decoder via the transformer. sensing threshold and does not cause a faulty output transition. The decoder is bistable and is therefore either set or reset by the Similarly, if such an event occurred during a transmitted pulse pulses, indicating input logic transitions. In the absence of logic (and had the worst-case polarity), it would reduce the received transitions of more than ~1 μs at the input, a periodic set of pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing refresh pulses indicative of the correct input state is sent to threshold of the decoder. ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, the input side is The preceding magnetic flux density values correspond to assumed to be unpowered or nonfunctional, in which case the specific current magnitudes at given distances away from the isolator output is forced to a default state (see Table 12) by the ADuM1210 transformers. Figure 11 expresses these allowable watchdog timer circuit. current magnitudes as a function of frequency for selected distances. As seen in Figure 11, the ADuM1210 is extremely The ADuM1210 is extremely immune to external magnetic immune and can be affected only by extremely large currents fields. The limitation on the ADuM1210 magnetic field operated at high frequency and very close to the component. immunity is set by the condition in which induced voltage in For the 1 MHz example, a 0.5 kA current would have to be the transformer’s receiving coil is sufficiently large to either placed 5 mm away from the ADuM1210 to affect the falsely set or reset the decoder. The following analysis defines component’s operation. the conditions under which this can occur. The 3 V operating condition of the ADuM1210 is examined because it represents the most susceptible mode of operation. Rev. D | Page 14 of 20

Data Sheet ADuM1210 1000 To calculate the total I and I supply current, the supply DD1 DD2 A) DISTANCE = 1m currents for each input and output channel corresponding to k T ( 100 IDD1 and IDD2 are calculated and totaled. Figure 4 and Figure 5 N E show per-channel supply currents as a function of data rate for R R U an unloaded output condition. Figure 6 shows per-channel C LE 10 supply current as a function of data rate for a 15 pF output B WA DISTANCE = 100mm condition. Figure 7 and Figure 8 show total VDD1 and VDD2 O L 1 supply current as a function of data rate. L A M DISTANCE = 5mm INSULATION LIFETIME U M AXI 0.1 All insulation structures eventually break down when subjected M to voltage stress over a sufficiently long period. The rate of 0.01 insulation degradation is dependent on the characteristics of the 1k 10MkAGNET1IC0 0FkIELD FRE1QMUENCY (H1z0)M 100M 05459-011 vthoelt taegset iwnga vpeeforfromrm apedp lbieyd t hacer roesgsu tlhaeto irnys ualgaetniocnie. sI,n A andadliotgio n to Figure 11. Maximum Allowable Current for Various Current-to-ADuM1210 Spacings Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM1210. Note that, at combinations of strong magnetic fields and high frequencies, any loops formed by printed circuit board traces Analog Devices performs accelerated life testing using voltage can induce sufficiently large error voltages to trigger the levels higher than the rated continuous working voltage. threshold of succeeding circuitry. Care should be taken in the Acceleration factors for several operating conditions are layout of such traces to avoid this possibility. determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 10 POWER CONSUMPTION summarize the peak voltage for 50 years of service life for a The supply current at a given channel of the ADuM1210 bipolar ac operating condition and the maximum CSA/VDE isolator is a function of the supply voltage, the channel data rate, approved working voltages. In many cases, the approved and the channel output load. working voltage is higher than 50-year service life voltage. For each input channel, the supply current is given by Operation at these high working voltages can lead to shortened insulation life in some cases. I = I f ≤ 0.5f DDI DDI (Q) r The insulation lifetime of the ADuM1210 depends on the I = I × (2f − f) + I f > 0.5f DDI DDI (D) r DDI (Q) r voltage waveform type imposed across the isolation barrier. For each output channel, the supply current is given by The iCoupler insulation structure degrades at different rates I = I f ≤ 0.5f depending on whether the waveform is bipolar ac, unipolar ac, DDO DDO (Q) r or dc. Figure 12, Figure 13, and Figure 14 illustrate these I = (I + (0.5 × 10−3) × CV ) × (2f − f) + I DDO DDO (D) L DDO r DDO (Q) different isolation voltage waveforms. f > 0.5f r Bipolar ac voltage is the most stringent environment. The goal where: of a 50-year operating lifetime under the ac bipolar condition I , I are the input and output dynamic supply currents DDI (D) DDO (D) determines the Analog Devices recommended maximum per channel (mA/Mbps). working voltage. C is the output load capacitance (pF). L V is the output supply voltage (V). DDO f is the input logic signal frequency (MHz, half the input data rate, NRZ signaling). f is the input stage refresh rate (Mbps). r I , I are the specified input and output quiescent DDI (Q) DDO (Q) supply currents (mA). Rev. D | Page 15 of 20

ADuM1210 Data Sheet In the case of unipolar ac or dc voltage, the stress on the RATED PEAK VOLTAGE iwnosurklaintigo nvo islt asiggens iwfichainlet lsyt illol wacehr.i eTvhinisg a all 5o0w-sy eoapre sreartivoince a lti fhei.g Thheer 0V 05459-014 working voltages listed in Table 10 can be applied while main- Figure 12. Bipolar AC Waveform taining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage case. Any cross- RATED PEAK VOLTAGE insulation voltage waveform that does not conform to Figure 13 opre aFkig vuorleta 1g4e sshhoouulldd bbee tlrimeaitteedd atso at hbeip 5o0l-ayre aacr wlifaevteimfoerm vo, latnagde i ts 0V 05459-012 value listed in Table 10. Figure 13. Unipolar AC Waveform Note that the voltage presented in Figure 13 is shown as sinusoidal for illustration purposes only. It is meant to represent RATED PEAK VOLTAGE any voltage waveform varying between 0 V and some limiting vvoallutaeg. eT chaen lnimoti tcirnogs sv a0l uVe. can be positive or negative, but the 0V 05459-013 Figure 14. DC Waveform Rev. D | Page 16 of 20

Data Sheet ADuM1210 OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 1.27(0.0500) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 0.40(0.0157) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA CONTROLLINGDIMENSIONSAREINMILLIMETERS;INCHDIMENSIONS A (RINEFPEARREENNCTEHEOSNELSY)AANRDEARROEUNNODTEDA-POPFRFOMPIRLLIAIMTEETFEORREUQSUEIVINALDEENSTIGSNF.OR 012407- Figure 15. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Number Number Maximum Maximum of Inputs, of Inputs, Maximum Propagation Pulse Width Temperature Package Package Model1 V Side V Side Data Rate Delay, 5 V Distortion Range Description Option DD1 DD2 ADuM1210BRZ 2 0 10 Mbps 50 ns 3 ns −40°C to +105°C 8-Lead SOIC_N R-8 ADuM1210BRZ-RL7 2 0 10 Mbps 50 ns 3 ns −40°C to +105°C 8-Lead SOIC_N R-8 1 Z = RoHS Compliant Part. Rev. D | Page 17 of 20

ADuM1210 Data Sheet NOTES Rev. D | Page 18 of 20

Data Sheet ADuM1210 NOTES Rev. D | Page 19 of 20

ADuM1210 Data Sheet NOTES ©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05459-0-3/12(D) Rev. D | Page 20 of 20

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