iCoupler Digital Isolator Data Sheet ADuM1100 FEATURES GENERAL DESCRIPTION High data rate: dc to 100 Mbps (NRZ) The ADuM11001 is a digital isolator based on Analog Devices Compatible with 3.3 V and 5.0 V operation/level translation Inc., iCoupler® technology. Combining high speed CMOS and 125°C maximum operating temperature monolithic air core transformer technology, this isolation Low power operation component provides outstanding performance characteristics 5 V operation superior to alternatives, such as optocoupler devices. 1.0 mA maximum @ 1 Mbps Configured as a pin-compatible replacement for existing high 4.5 mA maximum @ 25 Mbps speed optocouplers, the ADuM1100 supports data rates as high 16.8 mA maximum @ 100 Mbps as 25 Mbps and 100 Mbps. 3.3 V operation 0.4 mA maximum @ 1 Mbps The ADuM1100 operates with a voltage supply ranging from 3.5 mA maximum @ 25 Mbps 3.0 V to 5.5 V, boasts a propagation delay of <18 ns and edge 7.1 mA maximum @ 50 Mbps asymmetry of <2 ns, and is compatible with temperatures up 8-lead SOIC_N package (RoHS compliant version available) to 125°C. It operates at very low power, less than 0.9 mA of High common-mode transient immunity: >25 kV/μs quiescent current (sum of both sides), and a dynamic current Safety and regulatory approvals of less than 160 μA per Mbps of data rate. Unlike other optocoupler UL recognized alternatives, the ADuM1100 provides dc correctness with a 2500 V rms for 1 minute per UL 1577 patented refresh feature that continuously updates the output CSA Component Acceptance Notice 5A signal. VDE Certificate of Conformity The ADuM1100 is offered in three grades. The ADuM1100AR DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and ADuM1100BR can operate up to a maximum temperature V = 560 V peak IORM of 105°C and support data rates up to 25 Mbps and 100 Mbps, APPLICATIONS respectively. The ADuM1100UR can operate up to a maximum temperature of 125°C and supports data rates up to 100 Mbps. Digital field bus isolation Opto-isolator replacement Computer peripheral interface Microprocessor system interface General instrumentation and data acquisition applications FUNCTIONAL BLOCK DIAGRAM VDD1 1 8 VDD2 E D N E (DATA INV)I 2 OC OC 7 GND2 D D E E VDD1 3 6 V(DOATA OUT) UPDATE WATCHDOG GND1 4 5 GND2 ADuM1100 N1 . O FDTOCER SC PORRIRNECCIPTLNEESS SO,F A ONPDE MRAAGTINOENT, ISCE FEIE MLEDT IHMOMDU NOIFT YO PSEERCATITOIONN., 02462-001 Figure 1. 1 Protected by U.S. Patents 5,952,849; 6,525,566; 6,922,080; 6,903,578; 6,873,065; 7,075,329. Rev. K Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADuM1100 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Recommended Operating Conditions .................................... 11 Applications ....................................................................................... 1 Absolute Maximum Ratings ......................................................... 12 General Description ......................................................................... 1 ESD Caution................................................................................ 12 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions ........................... 13 Revision History ............................................................................... 3 Typical Performance Characteristics ........................................... 14 Specifications ..................................................................................... 4 Application Information ................................................................ 16 Electrical Specifications—5 V Operation ................................. 4 PC Board Layout ........................................................................ 16 Electrical Specifications—3.3 V Operation .............................. 6 Propagation Delay-Related Parameters ................................... 16 Electrical Specifications—Mixed 5 V/3 V or 3 V/5 V Method of Operation, DC Correctness, and Magnetic Operation ....................................................................................... 8 Field Immunity ........................................................................... 17 Package Characteristics ............................................................. 10 Power Consumption .................................................................. 18 Regulatory Information ............................................................. 10 Outline Dimensions ....................................................................... 19 Insulation and Safety-Related Specifications .......................... 10 Ordering Guide .......................................................................... 19 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics .......................................................... 11 Rev. K | Page 2 of 20

Data Sheet ADuM1100 REVISION HISTORY 7/15—Rev. J to Rev. K 4/03—Rev. B to Rev. C Changes to Table 5 and Table 6 ............................................................. 10 Changes to Features and Patent Note ............................................. 1 Changes to Regulatory Information ............................................... 6 4/15—Rev. I to Rev. J Changes to Insulation Characteristics Section .............................. 6 Changes to Logic Low Output Voltage Parameter, Test Changes to Absolute Maximum Ratings........................................ 7 Conditions, Table 2 ..................................................................................... 6 Changes to Package Branding ......................................................... 8 Changes to Method of Operation, DC Correctness, and 3/12—Rev. H to Rev. I Magnetic Field Immunity Section ................................................ 11 Created Hyperlink for Safety and Regulatory Approvals Replaced Figure 9 ............................................................................ 12 Entry in Features Section ................................................................. 1 Change to PC Board Layout Section ............................................ 16 1/03—Rev. A to Rev. B Added ADuM1100UR Grade ........................................... Universal 3/11—Rev. G to Rev. H Changed ADuM1100AR/ADuM1100BR to Changes to Data Sheet Title ............................................................. 1 ADuM1100 ......................................................................... Universal Changes to Ordering Guide ........................................................... 18 Changes to Features and General Description .............................. 1 Changes to Specifications................................................................. 2 6/07—Rev. F to Rev. G Added Electrical Specifications, Mixed 5 V/3 V or 3 V/5 V Updated VDE Certification Throughout ....................................... 1 Operation Table ................................................................................. 4 Changes to Features and Endnote 1 ................................................ 1 Updated Regulatory Information ................................................... 6 Changes to Table 5 and Table 6 ....................................................... 9 Changes to VDE 0884 Insulation Characteristics ........................ 6 Updated Outline Dimensions ....................................................... 18 Changes to Absolute Maximum Ratings........................................ 7 Changes to Ordering Guide .......................................................... 18 Changes to Package Branding ......................................................... 8 Updated TPC 3 to TPC 8 ................................................................. 9 3/06—Rev. E to Rev. F Deleted iCoupler in Field Bus Networks Section ....................... 11 Updated Format.................................................................. Universal Changes to Figure 8 ........................................................................ 12 Added Note 1 ..................................................................................... 1 Added Figure 9 and Related Text .................................................. 12 Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 6 11/02—Rev. 0 to Rev. A Changes to Table 3 ............................................................................ 8 Edits to Features ................................................................................ 1 Added Table 11 ................................................................................ 13 Edits to Regulatory Information ..................................................... 4 Inserted Power Consumption Section.......................................... 18 Edits to VDE 0884 Insulation Characteristics ............................... 5 Added Revision History ................................................................. 12 10/03—Rev. D to Rev. E Updated Outline Dimensions........................................................ 12 Changes to Product Name, Features, and General Description . 1 Changes to Regulatory Information ............................................... 6 Changes to DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation Characteristics ................................................................................... 6 Changes to Absolute Maximum Ratings ........................................ 7 Changes to Recommended Operating Conditions ....................... 7 Changes to Ordering Guide ............................................................. 8 6/03—Rev. C to Rev. D Changed DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation Characteristics ................................................................................... 6 Updated Ordering Guide ................................................................. 8 Updated Outline Dimensions ........................................................ 13 Rev. K | Page 3 of 20

ADuM1100 Data Sheet SPECIFICATIONS ELECTRICAL SPECIFICATIONS—5 V OPERATION All voltages are relative to their respective ground. 4.5 V ≤ V ≤ 5.5 V, 4.5 V ≤ V ≤ 5.5 V. All minimum/maximum specifications DD1 DD2 apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at T = 25°C, V = V = 5 V. A DD1 DD2 Table 1. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current I 0.3 0.8 mA V = 0 V or V DD1 (Q) I DD1 Output Supply Current I 0.01 0.06 mA V = 0 V or V DD2 (Q) I DD1 Input Supply Current (25 Mbps) I 2.2 3.5 mA 12.5 MHz logic signal frequency DD1 (25) (See Figure 5) Output Supply Current1 (25 Mbps) I 0.5 1.0 mA 12.5 MHz logic signal frequency DD2 (25) (See Figure 6) Input Supply Current (100 Mbps) I 9.0 14 mA 50 MHz logic signal frequency, DD1 (100) (See Figure 5) ADuM1100BR/ADuM1100UR only Output Supply Current1 (100 Mbps) I 2.0 2.8 mA 50 MHz logic signal frequency, DD2 (100) (See Figure 6) ADuM1100BR/ADuM1100UR only Input Current I −10 +0.01 +10 µA 0 V ≤ V ≤ V I IN DD1 Logic High Output Voltage V V − 0.1 5.0 V I = −20 μA, V = V OH DD2 O I IH V − 0.8 4.6 V I = −4 mA, V = V DD2 O I IH Logic Low Output Voltage V 0.0 0.1 V I = 20 μA, V = V OL O I IL 0.03 0.1 V I = 400 μA, V = V O I IL 0.3 0.8 V I = 4 mA, V = V O I IL SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width2 PW 40 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 25 Mbps C = 15 pF, CMOS signal levels L For ADuM1100BR/ADuM1100UR Minimum Pulse Width2 PW 6.7 10 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 100 150 Mbps C = 15 pF, CMOS signal levels L For All Grades Propagation Delay Time to Logic Low t 10.5 18 ns C = 15 pF, CMOS signal levels PHL L Output4, 5 (See Figure 7) Propagation Delay Time to Logic High t 10.5 18 ns C = 15 pF, CMOS signal levels PLH L Output4, 5 (See Figure 7) Pulse Width Distortion |t − t |5 PWD 0.5 2 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature6 3 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew t 8 ns C = 15 pF, CMOS signal levels PSK1 L (Equal Temperature)5, 7 Propagation Delay Skew t 6 ns C = 15 pF, CMOS signal levels PSK2 L (Equal Temperature, Supplies)5, 7 Output Rise/Fall Time t , t 3 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity |CM|, 25 35 kV/µs V = 0 V or V , V = 1000 V, L I DD1 CM at Logic Low/High Output8 |CM | transient magnitude = 800 V H Refresh Rate f 1.2 Mbps r Input Dynamic Supply Current9 I 0.09 mA/Mbps DDI (D) Output Dynamic Supply Current9 I 0.02 mA/Mbps DDO (D) Rev. K | Page 4 of 20

Data Sheet ADuM1100 1 Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH is measured from the 50% level of the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 5 Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the impact of given input rise/fall times on these parameters. 6 Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature. 7 tPSK1 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature and output load within the recommended operating conditions. tPSK2 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load. Rev. K | Page 5 of 20

ADuM1100 Data Sheet ELECTRICAL SPECIFICATIONS—3.3 V OPERATION All voltages are relative to their respective ground. 3.0 V ≤ V ≤ 3.6 V, 3.0 V ≤ V ≤ 3.6 V. All minimum/maximum specifications apply DD1 DD2 over the entire recommended operation range, unless otherwise noted. All typical specifications are at T = 25°C, V = V = 3.3 V. A DD1 DD2 Table 2. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current I 0.1 0.3 mA V = 0 V or V DD1 (Q) I DD1 Output Supply Current I 0.005 0.04 mA V = 0 V or V DD2 (Q) I DD1 Input Supply Current (25 Mbps) I 2.0 2.8 mA 12.5 MHz logic signal frequency DD1 (25) (See Figure 5) Output Supply Current1 (25 Mbps) I 0.3 0.7 mA 12.5 MHz logic signal frequency DD2 (25) (See Figure 6) Input Supply Current (50 Mbps) I 4.0 6.0 mA 25 MHz logic signal frequency, DD1 (50) (See Figure 5) ADuM1100BR/ADuM1100UR only Output Supply Current1 (50 Mbps) I 1.2 1.6 mA 25 MHz logic signal frequency, DD2 (50) (See Figure 6) ADuM1100BR/ADuM1100UR only Input Current I −10 +0.01 +10 µA 0 V ≤ V ≤ V I IN DD1 Logic High Output Voltage V V − 0.1 3.3 V I = −20 μA, V = V OH DD2 O I IH V − 0.5 3.0 V I = −2.5 mA, V = V DD2 O I IH Logic Low Output Voltage V 0.0 0.1 V I = 20 μA, V = V OL O I IL 0.04 0.1 V I = 400 μA, V = V O I IL 0.3 0.4 V I = 2.5 mA, V = V O I IL SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width2 PW 40 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 25 Mbps C = 15 pF, CMOS signal levels L For ADuM1100BR/ADuM1100UR Minimum Pulse Width2 PW 10 20 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 50 100 Mbps C = 15 pF, CMOS signal levels L For All Grades Propagation Delay Time to Logic Low t 14.5 28 ns C = 15 pF, CMOS signal levels PHL L Output4, 5 (See Figure 8) Propagation Delay Time to Logic t 15.0 28 ns C = 15 pF, CMOS signal levels PLH L High Output4, 5 (See Figure 8) Pulse Width Distortion |t − t |5 PWD 0.5 3 ns C = 15 pF, CMOS signal levels PLH PHL L Change vs. Temperature6 10 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew t 15 ns C = 15 pF, CMOS signal levels PSK1 L (Equal Temperature)5, 7 Propagation Delay Skew t 12 ns C = 15 pF, CMOS signal levels PSK2 L (Equal Temperature, Supplies)5, 7 Output Rise/Fall Time t , t 3 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity |CM|, 25 35 kV/µs V = 0 V or V , V = 1000 V, L I DD1 CM at Logic Low/High Output8 |CM | transient magnitude = 800 V H Refresh Rate f 1.1 Mbps r Input Dynamic Supply Current9 I 0.08 mA/Mbps DDI (D) Output Dynamic Supply Current9 I 0.04 mA/Mbps DDO (D) Rev. K | Page 6 of 20

Data Sheet ADuM1100 1 Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH is measured from the 50% level of the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 5 Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the impact of given input rise/fall times on these parameters. 6 Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature. 7 tPSK1 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature and output load within the recommended operating conditions. tPSK2 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load. Rev. K | Page 7 of 20

ADuM1100 Data Sheet ELECTRICAL SPECIFICATIONS—MIXED 5 V/3 V OR 3 V/5 V OPERATION All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ V ≤ 5.5 V, 3.0 V ≤ V ≤ 3.6 V. 3 V/5 V operation: DD1 DD2 3.0 V ≤ V ≤ 3.6 V, 4.5 V ≤ V ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range, DD1 DD2 unless otherwise noted. All typical specifications are at T = 25°C, V = 3.3 V, V = 5 V or V = 5 V, V = 3.3 V. A DD1 DD2 DD1 DD2 Table 3. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, Quiescent I DDI (Q) 5 V/3 V Operation 0.3 0.8 mA 3 V/5 V Operation 0.1 0.3 mA Output Supply Current, Quiescent I DDO (Q) 5 V/3 V Operation 0.005 0.04 mA 3 V/5 V Operation 0.01 0.06 mA Input Supply Current, 25 Mbps I DDI (25) 5 V/3 V Operation 2.2 3.5 mA 12.5 MHz logic signal frequency 3 V/5 V Operation 2.0 2.8 mA 12.5 MHz logic signal frequency Output Supply Current1, 25 Mbps I DDO (25) 5 V/3 V Operation 0.3 0.7 mA 12.5 MHz logic signal frequency 3 V/5 V Operation 0.5 1.0 mA 12.5 MHz logic signal frequency Input Supply Current, 50 Mbps I DDI (50) 5 V/3 V Operation 4.5 7.0 mA 25 MHz logic signal frequency 3 V/5 V Operation 4.0 6.0 mA 25 MHz logic signal frequency Output Supply Current1, 50 Mbps I DDO (50) 5 V/3 V Operation 1.2 1.6 mA 25 MHz logic signal frequency 3 V/5 V Operation 1.0 1.5 mA 25 MHz logic signal frequency Input Currents I −10 +0.01 +10 μA 0 V ≤ V , V , V , V ≤ V or V IA IA IB IC ID DD1 DD2 Logic High Output Voltage V V − 0.1 3.3 V I = −20 μA, V = V OH DD2 O I IH 5 V/3 V Operation V − 0.5 3.0 V I = −2.5 mA, V = V DD2 O I IH Logic Low Output Voltage V 0.0 0.1 V I = 20 μA, V = V OL O I IL 5 V/3 V Operation 0.04 0.1 V I = 400 μA, V = V O I IL 0.3 0.4 V I = 2.5 mA, V = V O I IL Logic High Output Voltage V V − 0.1 5.0 V I = −20 μA, V = V OH DD2 O I IH 3 V/5 V Operation V − 0.8 4.6 V I = −4 mA, V = V DD2 O I IH Logic Low Output Voltage V 0.0 0.1 V I = 20 μA, V = V OL O I IL 3 V/5 V Operation 0.03 0.1 V I = 400 μA, V = V O I IL 0.3 0.8 V I = 4 mA, V = V O I IL SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width2 PW 40 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 25 Mbps C = 15 pF, CMOS signal levels L For ADuM1100BR/ADuM1100UR Minimum Pulse Width2 PW 20 ns C = 15 pF, CMOS signal levels L Maximum Data Rate3 50 Mbps C = 15 pF, CMOS signal levels L For All Grades Propagation Delay Time to Logic t , t PHL PLH Low/High Output4, 5 5 V/3 V Operation (See Figure 9) 13 21 ns C = 15 pF, CMOS signal levels L 3 V/5 V Operation (See Figure 10) 16 26 ns C = 15 pF, CMOS signal levels L Rev. K | Page 8 of 20

Data Sheet ADuM1100 Parameter Symbol Min Typ Max Unit Test Conditions Pulse Width Distortion, |t − t |5 PWD PLH PHL 5 V/3 V Operation 0.5 2 ns C = 15 pF, CMOS signal levels L 3 V/5 V Operation 0.5 3 ns C = 15 pF, CMOS signal levels L Change in Pulse Width Distortion vs. Temperature6 5 V/3 V Operation 3 ps/°C C = 15 pF, CMOS signal levels L 3 V/5 V Operation 10 ps/°C C = 15 pF, CMOS signal levels L Propagation Delay Skew (Equal t PSK1 Temperature)5, 7 5 V/3 V Operation 12 ns C = 15 pF, CMOS signal levels L 3 V/5 V Operation 15 ns C = 15 pF, CMOS signal levels L Propagation Delay Skew (Equal t PSK2 Temperature, Supplies)5, 7 5 V/3 V Operation 9 ns C = 15 pF, CMOS signal levels L 3 V/5 V Operation 12 ns C = 15 pF, CMOS signal levels L Output Rise/Fall Time (10% to 90%) t , t 3 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient Immunity at |CM|, 25 35 kV/µs V = 0 V or V , V = 1000 V, L I DD1 CM Logic Low/High Output8 |CM | transient magnitude = 800 V H Refresh Rate f r 5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps Input Dynamic Supply Current9 C PD1 5 V/3 V Operation 0.09 mA/Mbps 3 V/5 V Operation 0.08 mA/Mbps Output Dynamic Supply Current9 C PD2 5 V/3 V Operation 0.04 mA/Mbps 3 V/5 V Operation 0.02 mA/Mbps 1 Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH is measured from the 50% level of the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 5 Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the impact of given input rise/fall times on these parameters. 6 Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature. 7 tPSK1 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature and output load within the recommended operating conditions. tPSK2 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load. Rev. K | Page 9 of 20

ADuM1100 Data Sheet PACKAGE CHARACTERISTICS Table 4. Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input-to-Output)1 R 1012 Ω I-O Capacitance (Input-to-Output)1 C 1.0 pF f = 1 MHz I-O Input Capacitance2 C 4.0 pF I IC Junction-to-Case Thermal Resistance, Side 1 θ 46 °C/W Thermocouple located at JCI IC Junction-to-Case Thermal Resistance, Side 2 θ 41 °C/W center of package underside JCO Package Power Dissipation P 240 mW PD 1 The device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, and Pin 4 are shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together. 2 Input capacitance is measured at Pin 2 (VI). REGULATORY INFORMATION The ADuM1100 is approved by the following organizations. Table 5. UL CSA CQC VDE Recognized Under Approved under CSA Approved under Certified according to 1577 Component Component Acceptance CQC11-471543-2012 DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Recognition Notice 5A Program1 Single/Basic Insulation, Basic insulation per Basic insulation per GB4943.1- Reinforced insulation, 560 V peak 2500 V rms Isolation CSA 60950-1-03 and IEC 2011 400 V rms (588 V peak) Voltage 60950-1, 400 V rms maximum working voltage, (565 V peak) maximum tropical climate, altitude ≤ working voltage 5000 meters File E214100 File 205078 File CQC14001117247 File 2471900-4880-0001 1 In accordance with UL 1577, each ADuM1100 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA). 2 In accordance with DIN V VDE V 0884-10, each ADuM1100 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Symbol Value Unit Conditions Minimum External Air Gap (Clearance) L(I01) 4.90 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 4.01 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.016 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1 Isolation Group II Material Group (DIN VDE 0110, 1/89, Table I) Maximum Working Voltage Compatible with V 565 V peak Continuous peak voltage across the isolation barrier IORM 50 Years Service Life Rev. K | Page 10 of 20

Data Sheet ADuM1100 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage. Table 7. Description Conditions Symbol Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V 560 V peak IORM Input-to-Output Test Voltage, Method B1 V × 1.875 = V , 100% production test, V 1050 V peak IORM PR PR t = 1 sec, partial discharge < 5 pC m Input-to-Output Test Voltage, Method A V × 1.6 = V , t = 60 sec, partial V IORM PR m PR discharge < 5 pC After Environmental Tests Subgroup 1 896 V peak After Input and/or Safety Test Subgroup 2 and Subgroup 3 V × 1.2 = V , t = 60 sec, partial 672 V peak IORM PR m discharge < 5 pC Highest Allowable Overvoltage Transient overvoltage, t = 10 seconds V 4000 V peak TR TR Safety-Limiting Values Maximum value allowed in the event of a failure (see Figure 2) Case Temperature T 150 °C S Side 1 Current I 160 mA S1 Side 2 Current I 170 mA S2 Insulation Resistance at T V = 500 V R >109 Ω S IO S 180 RECOMMENDED OPERATING CONDITIONS 160 A) Table 8. m140 T ( OUTPUT CURRENT Parameter Symbol Min Max Unit N E120 Operating Temperature R R U ADuM1100AR/ADuM1100BR T −40 +105 °C C100 A NG INPUT CURRENT ADuM1100UR TA −40 +125 °C MITI 80 Supply Voltages1 VDD1, 3.0 5.5 V Y-LI 60 VDD2 T E Logic High Input Voltage, V 2.0 V V SAF 40 5 V Operation1, 2 IH DD1 200 02462-002 Log(Siece L oFiwg uInrep 1u1t Vaonldta Fgigeu, re 12) VIL 0.0 0.8 V 0 50 100 150 200 5 V Operation1, 2 CASE TEMPERATURE (°C) (See Figure 11 and Figure 12) Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values Logic High Input Voltage, V 1.5 V V IH DD1 with Case Temperature per DIN V VDE V 0884-10 3.3 V Operation1, 2 (See Figure 11 and Figure 12) Logic Low Input Voltage, V 0.0 0.5 V IL 3.3 V Operation1, 2 (See Figure 11 and Figure 12) Input Signal Rise and Fall Times 1.0 ms 1 All voltages are relative to their respective ground. 2 Input switching thresholds have 300 mV of hysteresis. See the Method of Operation, DC Correctness, and Magnetic Field Immunity section, Figure 19, and Figure 20 for information on immunity to external magnetic fields. Rev. K | Page 11 of 20

ADuM1100 Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Table 9. Ratings may cause permanent damage to the product. This is a Parameter Symbol Min Max Unit stress rating only; functional operation of the product at these Storage Temperature T −55 +150 °C ST or any other conditions above those indicated in the operational Ambient Operating T −40 +125 °C A Temperature section of this specification is not implied. Operation beyond Supply Voltages1 VDD1, VDD2 −0.5 +6.5 V the maximum operating conditions for extended periods may Input Voltage1 V −0.5 V + 0.5 V affect product reliability. I DD1 Output Voltage1 VO −0.5 VDD2 + 0.5 V ESD CAUTION Average Current, per Pin2 Temperature ≤ 105°C −25 +25 mA Temperature ≤ 125°C Input Current −7 +7 mA Output Current −20 +20 mA Common-Mode Transients3 −100 +100 kV/µs 1 All voltages are relative to their respective ground. 2 See Figure 2 for information on maximum allowable current for various temperatures. 3 Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or permanent damage. Table 10. Truth Table (Positive Logic) V Input V State V State V Output I DD1 DD2 O H Powered Powered H L Powered Powered L X Unpowered Powered H1 X Powered Unpowered X1 1 VO returns to VI state within 1 μs of power restoration. Figure 3 shows the package branding. The asterisk (*) is the DIN EN 60747-5-2 mark, R is the package designator (R denotes SOIC_N), YYWW is the date code, and XXXXXX is the lot code. ADuM1100AR, ADuM1100BR, ADuM1100UR, ADuM1100AR-RL7 ADuM1100BR-RL7 ADuM1100UR-RL7 8 8 8 AD1100A AD1100B AD1100U R YYWW* R YYWW* R YYWW* XXXXXX XXXXXX XXXXXX 1 1 1 02462-003 Figure 3. Package Branding Rev. K | Page 12 of 20

Data Sheet ADuM1100 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD11 1 8 VDD2 VI 2 ADuM1100 7 GND22 VDD11 3 (NToOt Pto V SIEcaWle) 6 VO GND1 4 5 GND22 1PIN 1 AND PIN 3 ARE INTERNALLY CONNECTED. EITHER OR BOTH 2MPMIAANYY 5 BB AEEN UUDSS PEEINDD 7FF OOARRR EVG DINNDDT12.E.RNALLY CONNECTED. EITHER OR BOTH 02462-004 Figure 4. Pin Configuration Table 11. Pin Function Descriptions Pin No. Mnemonic Description 1 V Input Supply Voltage, 3.0 V to 5.5 V. DD1 2 V Logic Input. I 3 V Input Supply Voltage, 3.0 V to 5.5 V. DD1 4 GND Input Ground Reference. 1 5 GND Output Ground Reference. 2 6 V Logic Output. O 7 GND Output Ground Reference. 2 8 V Output Supply Voltage, 3.0 V to 5.5 V. DD2 Rev. K | Page 13 of 20

ADuM1100 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 20 18 18 17 16 s) n ENT (mA) 111420 ON DELAY ( 1156 tPHL URR 8 GATI tPLH C 5V A P 14 6 O 3.3V R P 4 13 20 02462-005 12 02462-008 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 DATA RATE (Mbps) TEMPERATURE (°C) Figure 5. Typical Input Supply Current vs. Logic Signal Frequency Figure 8. Typical Propagation Delays vs. Temperature, 3.3 V Operation for 5 V and 3.3 V Operation 5 14 4 13 s) n Y ( tPLH mA) 3 ELA 12 RENT ( 5V TION D tPHL UR 2 GA 11 C A P O R 3.3V P 1 10 0 02462-006 9 02462-009 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 DATA RATE (Mbps) TEMPERATURE (°C) Figure 6. Typical Output Supply Current vs. Logic Signal Frequency Figure 9. Typical Propagation Delays vs. Temperature, 5 V/3 V Operation for 5 V and 3.3 V Operation 13 18 17 s) 12 s) n n AY ( AY ( 16 L L TION DE 11 tPLH TION DE 15 tPHL tPLH GA tPHL GA A A P P 14 O O PR 10 PR 13 9 02462-007 12 02462-010 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. Typical Propagation Delays vs. Temperature, 5 V Operation Figure 10. Typical Propagation Delays vs. Temperature, 3 V/5 V Operation Rev. K | Page 14 of 20

Data Sheet ADuM1100 1.7 1.4 –40°C +25°C 1.6 1.3 OLD, V (V)ITH1.5 +–2450°C°C OLD, V (V)ITH1.2 +125°C HRESH 1.4 HRESH 1.1 NPUT T 1.3 +125°C NPUT T 1.0 I I 1.2 0.9 1.1 02462-011 0.8 02462-012 3.0 3.5 4.0 4.5 5.0 5.5 3.0 3.5 4.0 4.5 5.0 5.5 INPUT SUPPLY VOLTAGE, VDD1 (V) INPUT SUPPLY VOLTAGE, VDD1 (V) Figure 11. Typical Input Voltage Switching Threshold, Figure 12. Typical Input Voltage Switching Threshold, Low-to-High Transition High-to-Low Transition Rev. K | Page 15 of 20

ADuM1100 Data Sheet APPLICATION INFORMATION PC BOARD LAYOUT Pulse width distortion is the maximum difference between t and t and provides an indication of how accurately the PLH PHL The ADuM1100 digital isolator requires no external interface input signal’s timing is preserved in the component’s output circuitry for the logic interfaces. A bypass capacitor is recom- signal. Propagation delay skew is the difference between the mended at the input and output supply pins. The input bypass minimum and maximum propagation delay values among capacitor can conveniently be connected between Pin 3 and multiple ADuM1100 components operated at the same Pin 4 (see Figure 13). Alternatively, the bypass capacitor can be operating temperature and having the same output load. located between Pin 1 and Pin 4. The output bypass capacitor Depending on the input signal rise/fall time, the measured can be connected between Pin 7 and Pin 8 or Pin 5 and Pin 8. propagation delay based on the input 50% level can vary from The capacitor value should be between 0.01 μF and 0.1 μF. The the true propagation delay of the component (as measured from total lead length between both ends of the capacitor and the its input switching threshold). This is because the input threshold, power supply pins should not exceed 20 mm. as is the case with commonly used optocouplers, is at a different VDD1 VDD2 voltage level than the 50% point of typical input signals. This VI (DATA IN) (OPTIONAL) propagation delay difference is given by GND1 VGON D(D2ATA OUT) 02462-013 ΔLH = t′PLH − tPLH = (tR/0.8 VI)(0.5 VI − VITH (L-H)) Figure 13. Recommended Printed Circuit Board Layout Δ = t′ − t = (t/0.8 V)(0.5 V − V ) HL PHL PHL F I I ITH (H-L) See the AN-1109 Application Note for board layout guidelines. where: PROPAGATION DELAY-RELATED PARAMETERS t and t are the propagation delays as measured from the PLH PHL input 50% level. Propagation delay time describes the length of time it takes for t’ and t’ are the propagation delays as measured from the a logic signal to propagate through a component. Propagation PLH PHL input switching thresholds. delay time to logic low output and propagation delay time to t and t are the input 10% to 90% rise/fall times. logic high output refer to the duration between an input R F V is the amplitude of the input signal (0 V to V levels assumed). signal transition and the respective output signal transition I I V and V are the input switching thresholds. (see Figure 14). ITH (L–H) ITH (H–L) INPUT (VI) 50% t t PLH PHL OUTPUT (VO) 50% 02462-014 Figure 14. Propagation Delay Parameters VI ∆LH ∆HL VITH(L–H) 50% VITH(H–L) INPUT (VI) tPLH t t'PHL t' PHL OUTPUT (VO) PLH 50% 02462-015 Figure 15. Impact of Input Rise/Fall Time on Propagation Delay Rev. K | Page 16 of 20

Data Sheet ADuM1100 4 6 (ns)H MENT, 5 GE, ΔL 3 DJUST N A 4 CHA 5V INPUT SIGNAL ON s) 5V INPUT SIGNAL LAY 2 ORTI (nWD3 N DE DISTΔP 3.3V INPUT SIGNAL GATIO 1 WIDTH 2 PROPA 0 3.3V INPUT SIGNAL 02462-016 PULSE 01 02462-018 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 INPUT RISE TIME (10%–90%, ns) INPUT RISE/FALL TIME (10%–90%, ns) Figure 16. Typical Propagation Delay Change Due to Figure 18. Typical Pulse Width Distortion Adjustment Due to Input Rise Time Variation (for VDD1 = 3.3 V and 5 V) Input Rise/Fall Time Variation (for VDD1 = 3.3 V and 5 V) METHOD OF OPERATION, DC CORRECTNESS, AND 0 MAGNETIC FIELD IMMUNITY s) n (HL The two coils in Figure 1 act as a pulse transformer. Positive Δ E, –1 and negative logic transitions at the isolator input cause narrow G AN 5V INPUT SIGNAL (2 ns) pulses to be sent via the transformer to the decoder. The H Y C decoder is bistable and therefore either set or reset by the pulses A –2 L indicating input logic transitions. In the absence of logic transi- DE 3.3V INPUT SIGNAL N tions at the input for more than ~1 μs, a periodic update pulse O TI of the appropriate polarity is sent to ensure dc correctness at the A G –3 A output. If the decoder receives none of these update pulses for P PRO –4 02462-017 omro nroe nthfuannc atbioonuat l5, iμns ,w thheic ihn pcuats esi tdhee i si saoslsautmore odu totp buet uisn fpoorwceedre tdo 1 2 3 4 5 6 7 8 9 10 a logic high state by the watchdog timer circuit. INPUT RISE TIME (10%–90%, ns) The limitation on the magnetic field immunity of the Figure 17. Typical Propagation Delay Change Due to Input Fall Time Variation (for VDD1 = 3.3 V and 5 V) ADuM1100 is set by the condition in which induced voltage in the transformer’s receiving coil is sufficiently large to either The impact of the slower input edge rates can also affect the falsely set or reset the decoder. The analysis that follows defines measured pulse width distortion as based on the input 50% the conditions under which this can occur. The 3.3 V operating level. This impact can either increase or decrease the apparent condition of the ADuM1100 is examined because it represents pulse width distortion depending on the relative magnitudes of the most susceptible mode of operation. t , t , and PWD. The case of interest here is the condition PHL PLH The pulses at the transformer output are greater than 1.0 V in that leads to the largest increase in pulse width distortion. The amplitude. The decoder has sensing thresholds at about 0.5 V, change in this case is given by therefore establishing a 0.5 V margin in which induced voltages ∆ = PWD′ − PWD = ∆ − ∆ = PWD LH HL can be tolerated. The voltage induced across the receiving coil (t/0.8 VI)(V − VITH (L-H) − VITH (H-L)), (for t = tR = tF) is given by where: V = (−dβ/dt) ∑π r2, n = 1, 2, . . . , N n PWD = |t − t |. PLH PHL where: PWD’ = |t’ − t’ |. PLH PHL β is the magnetic flux density (gauss). This adjustment in pulse width distortion is plotted as a N is the number of turns in the receiving coil. function of input rise/fall time in Figure 18. r is the radius of the nth turn in the receiving coil (cm). n Rev. K | Page 17 of 20

ADuM1100 Data Sheet Given the geometry of the receiving coil in the ADuM1100 and 1000 an imposed requirement that the induced voltage be at most A) DISTANCE = 1m k 50% of the 0.5 V margin at the decoder, a maximum allowable T ( 100 N magnetic field is calculated, as shown in Figure 19. RE R 100 E CU 10 FLUX WABL DISTANCE = 100mm GNETIC s) 10 M ALLO 1 DISTANCE = 5mm LOWABLE MAENSITY (kgaus 0.11 MAXIMU 0.00.11 02462-020 ALD 1k 10k 100k 1M 10M 100M UM MAGNETIC FIELD FREQUENCY (Hz) XIM 0.01 Figure 20. Maximum Allowable Current for MA 0.001 02462-019 Note that at comVabriinouast iCounrrse ontf- tsotr-AoDnugM m11a0g0n Septaicc ifnigesl d and high 1k 10k 100k 1M 10M 100M frequency, any loops formed by printed circuit board traces MAGNETIC FIELD FREQUENCY (Hz) Figure 19. Maximum Allowable External Magnetic Field could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the For example, at a magnetic field frequency of 1 MHz, the layout of such traces to avoid this possibility. maximum allowable magnetic field of 0.2 kgauss induces a POWER CONSUMPTION voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. The supply current of the ADuM1100 isolator is a function of Similarly, if such an event were to occur during a transmitted the supply voltage, the input data rate, and the output load. pulse (and was of the worst-case polarity), it would reduce the The input supply current is given by received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder. IDDI = IDDI (Q) f ≤ 0.5fr The preceding magnetic flux density values correspond to IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5fr specific current magnitudes at given distances away from the The output supply current is given by ADuM1100 transformers. Figure 20 expresses these allowable I = I f ≤ 0.5f DDO DDO (Q) r current magnitudes as a function of frequency for selected distances. As can be seen, the ADuM1100 is extremely immune IDDO = (IDDO (D) + (0.5 × 10−3) × CLVDDO) × (2f − fr) + IDDO (Q) and can be affected only by extremely large currents operated at f > 0.5fr high frequency and very close to the component. For the 1 MHz where: example noted, one would have to place a current of 0.5 kA I , I are the input and output dynamic supply currents DDI (D) DDO (D) 5 mm away from the ADuM1100 to affect the component’s per channel (mA/Mbps). operation. C is the output load capacitance (pF). L V is the output supply voltage (V). DDO f is the input logic signal frequency (MHz, half the input data rate, NRZ signaling). f is the input stage refresh rate (Mbps). r I , I are the specified input and output quiescent DDI (Q) DDO (Q) supply currents (mA). Rev. K | Page 18 of 20

Data Sheet ADuM1100 OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 21. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Maximum Data Minimum Package Model1 Temperature Range Rate (Mbps) Pulse Width (ns) Package Description Option ADuM1100AR −40°C to +105°C 25 40 8-Lead SOIC_N R-8 ADuM1100AR-RL7 −40°C to +105°C 25 40 8-Lead SOIC_N, 1,000 Piece Reel R-8 ADuM1100ARZ −40°C to +105°C 25 40 8-Lead SOIC_N R-8 ADuM1100ARZ-RL7 −40°C to +105°C 25 40 8-Lead SOIC_N, 1,000 Piece Reel R-8 ADuM1100BR −40°C to +105°C 100 10 8-Lead SOIC_N R-8 ADuM1100BR-RL7 −40°C to +105°C 100 10 8-Lead SOIC_N, 1,000 Piece Reel R-8 ADuM1100BRZ −40°C to +105°C 100 10 8-Lead SOIC_N R-8 ADuM1100BRZ-RL7 −40°C to +105°C 100 10 8-Lead SOIC_N, 1,000 Piece Reel R-8 ADuM1100UR −40°C to +125°C 100 10 8-Lead SOIC_N R-8 ADuM1100UR-RL7 −40°C to +125°C 100 10 8-Lead SOIC_N, 1,000 Piece Reel R-8 ADuM1100URZ −40°C to +125°C 100 10 8-Lead SOIC_N R-8 ADuM1100URZ-RL7 −40°C to +125°C 100 10 8-Lead SOIC_N, 1,000 Piece Reel R-8 1 Z = RoHS Compliant Part. Rev. K | Page 19 of 20

ADuM1100 Data Sheet NOTES ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02462-0-7/15(K) Rev. K | Page 20 of 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADUM1100BR ADUM1100AR-RL7 ADUM1100ARZ-RL7 ADUM1100BRZ-RL7 ADUM1100URZ ADUM1100UR ADUM1100URZ-RL7 ADUM1100AR ADUM1100BR-RL7 ADUM1100BRZ ADUM1100UR-RL7 ADUM1100ARZ