MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62 kB Flash MCU Data Sheet ADuC841/ADuC842/ADuC843 FEATURES FUNCTIONAL BLOCK DIAGRAM Pin compatible upgrade of ADuC812/ADuC831/ADuC832 Increased performance ADuC841/ADuC842/ADuC843 1D2-ABCIT BUF DAC1 Single-cycle 20 MIPS 8052 core High speed 420 kSPS 12-bit ADC Increased memory ADC0 1D2-ABCIT BUF DAC1 ADC1 T/H 12-BIT ADC Up to 62 kBytes on-chip Flash/EE program memory 16-BIT 4 kBytes on-chip Flash/EE data memory MUX Σ-∆DAC ADC5 In-circuit reprogrammable ADC6 16-BIT Flash/EE, 100 year retention, 100 kCycle endurance ADC7 CHAALRIBDRWAATROEN Σ-∆DAC MUX PWM0 2304 bytes on-chip data RAM 16-BIT TEMP PWM PWM1 Smaller package SENSOR 8 mm × 8 mm chip scale package 16-BIT PWM 52-lead PQFP—pin-compatible upgrade 20 MIPS 8052 BASED MCU WITH ADDITIONAL Analog I/O PERIPHERALS 8-channel, 420 kSPS high accuracy, 12-bit ADC PLL2 62kBYTES FLASH/EE PROGRAM MEMORY 4kBYTES FLASH/EE DATA MEMORY On-chip, 15 ppm/°C voltage reference 2304 BYTES USER RAM 3×16 BIT TIMERS POWER SUPPLY MON DMA controller, high speed ADC-to-RAM capture INTERNAL 1×REALTIMECLOCK WATCHDOG TIMER TDwuoa l1 o2u-btpitu vt oPlWtaMge ∑ o-∆u tDpAuCt sD ACs1 BAVNRDE GFAP OSC 4×P POARRTASLLEL UARSTE,IR2CIA, LA IN/OD SPI 03260-0-001 On-chip temperature monitor function CREF XTAL1 XTAL2 8052 based core Figure 1. 8051 compatible instruction set (20 MHz max) GENERAL DESCRIPTION High performance single-cycle core The ADuC841/ADuC842/ADuC8431 are complete smart 32 kHz external crystal, on-chip programmable PLL transducer front ends, that integrates a high performance self- 12 interrupt sources, 2 priority levels calibrating multichannel ADC, a dual DAC, and an optimized Dual data pointers, extended 11-bit stack pointer single-cycle 20 MHz 8-bit MCU (8051 instruction set compatible) On-chip peripherals on a single chip. Time interval counter (TIC) UART, I2C®, and SPI® Serial I/O The ADuC841 and ADuC842 are identical with the exception Watchdog timer (WDT) of the clock oscillator circuit; the ADuC841 is clocked directly Power supply monitor (PSM) from an external crystal up to 20 MHz whereas the ADuC842 Power uses a 32 kHz crystal with an on-chip PLL generating a Normal: 4.5 mA @ 3 V (core CLK = 2.098 MHz) programmable core clock up to 16.78 MHz. Power-down: 10 µA @ 3 V2 The ADuC843 is identical to the ADuC842 except that the Development tools ADuC843 has no analog DAC outputs. Low cost, comprehensive development system incorporating nonintrusive single-pin emulation, The microcontroller is an optimized 8052 core offering up to IDE based assembly and C source debugging 20 MIPS peak performance. Three different memory options are available offering up to 62 kBytes of nonvolatile Flash/EE APPLICATIONS program memory. Four kBytes of nonvolatile Flash/EE data Optical networking—laser power control memory, 256 bytes RAM, and 2 kBytes of extended RAM are Base station systems also integrated on-chip. Precision instrumentation, smart sensors Transient capture systems 1 Protected by U.S. Patent No. 5,969,657. DAS and communications systems (continued on page 23) 1 ADuC841/ADuC842 only. 2 ADuC842/ADuC843 only, ADuC841 driven directly by external crystal. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2003–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADuC841/ADuC842/ADuC843 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 User Interface to On-Chip Peripherals.................................... 46 Applications ....................................................................................... 1 On-Chip PLL .............................................................................. 49 Functional Block Diagram .............................................................. 1 Pulse-Width Modulator (PWM) .............................................. 50 General Description ......................................................................... 1 Serial Peripheral Interface (SPI) ............................................... 53 Revision History ............................................................................... 2 I2C Compatible Interface ........................................................... 56 Specifications ..................................................................................... 3 Dual Data Pointer ....................................................................... 59 Absolute Maximum Ratings ............................................................ 8 Power Supply Monitor ............................................................... 60 ESD Caution .................................................................................. 8 Watchdog Timer ......................................................................... 61 Pin Configurations and Function Descriptions ........................... 9 Time Interval Counter (TIC) .................................................... 62 Terminology .................................................................................... 19 8052 Compatible On-Chip Peripherals ................................... 65 ADC Specifications .................................................................... 19 Timer/Counter 0 and 1 Operating Modes .............................. 70 DAC Specifications..................................................................... 19 Timer/Counter Operating Modes ............................................ 72 Typical Performance Characteristics ........................................... 20 UART Serial Interface ................................................................ 73 Functional Description .................................................................. 24 SBUF ............................................................................................ 73 8052 Instruction Set ................................................................... 24 Interrupt System ......................................................................... 78 Other Single-Cycle Core Features ............................................ 26 Hardware Design Considerations ............................................ 80 Memory Organization ............................................................... 27 Other Hardware Considerations .............................................. 84 Special Function Registers (SFRs) ............................................ 28 Development Tools .................................................................... 85 Accumulator SFR (ACC) ........................................................... 29 QuickStart Development System ............................................. 85 Special Function Register Banks .............................................. 30 Timing Specifications, , .................................................................. 86 ADC Circuit Information.......................................................... 31 Outline Dimensions ....................................................................... 94 Calibrating the ADC .................................................................. 38 Ordering Guide .......................................................................... 95 Nonvolatile Flash/EE Memory ................................................. 39 Using Flash/EE Data Memory .................................................. 42 REVISION HISTORY Changes to Figure 4 ........................................................................ 14 6/2017—Rev. A to Rev. B Added Table 4; Renumbered Sequentially .................................. 14 Change to Notes, Figure 4 ............................................................. 14 Changes to Using the DAC Section ............................................. 47 Changes to Figure 96 ...................................................................... 95 Updated Outline Dimensions ....................................................... 94 Changes to Ordering Guide .......................................................... 95 4/2016—Rev. 0 to Rev. A Added Patent Note, Note 1 .............................................................. 1 11/2003—Revision 0: Initial Version Changes to Figure 3 and Table 3 ..................................................... 9 Rev. B | Page 2 of 95

Data Sheet ADuC841/ADuC842/ADuC843 SPECIFICATIONS1 Table 1. AVDD = DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; VREF = 2.5 V internal reference, fCORE = 16.78 MHz @ 5 V 8.38 MHz @ 3 V; all specifications TA = TMIN to TMAX, unless otherwise noted Parameter V = 5 V V = 3 V Unit Test Conditions/Comments DD DD ADC CHANNEL SPECIFICATIONS DC ACCURACY2, 3 f = 120 kHz, see the Typical SAMPLE Performance Characteristics for typical performance at other values of f SAMPLE Resolution 12 12 Bits Integral Nonlinearity ±1 ±1 LSB max 2.5 V internal reference ±0.3 ±0.3 LSB typ Differential Nonlinearity +1/–0.9 +1/–0.9 LSB max 2.5 V internal reference ±0.3 ±0.3 LSB typ Integral Nonlinearity4 ±2 ±1.5 LSB max 1 V external reference Differential Nonlinearity4 +1.5/–0.9 +1.5/–0.9 LSB max 1 V external reference Code Distribution 1 1 LSB typ ADC input is a dc voltage CALIBRATED ENDPOINT ERRORS5, 6 Offset Error ±3 ±2 LSB max Offset Error Match ±1 ±1 LSB typ Gain Error ±3 ±2 LSB max Gain Error Match ±1 ±1 LSB typ DYNAMIC PERFORMANCE f = 10 kHz sine wave IN f = 120 kHz SAMPLE Signal-to-Noise Ratio (SNR)7 71 71 dB typ Total Harmonic Distortion (THD) –85 –85 dB typ Peak Harmonic or Spurious Noise –85 –85 dB typ Channel-to-Channel Crosstalk8 –80 –80 dB typ ANALOG INPUT Input Voltage Range 0 to V 0 to V V REF REF Leakage Current ±1 ±1 µA max Input Capacitance 32 32 pF typ TEMPERATURE SENSOR9 Voltage Output at 25°C 700 700 mV typ Voltage TC –1.4 –1.4 mV/°C typ Accuracy ±1.5 ±1.5 °C typ Internal/External 2.5 V V REF DAC CHANNEL SPECIFICATIONS DAC load to AGND Internal Buffer Enabled RL = 10 kΩ, CL = 100 pF ADuC841/ADuC842 Only DC ACCURACY10 Resolution 12 12 Bits Relative Accuracy ±3 ±3 LSB typ Differential Nonlinearity11 –1 –1 LSB max Guaranteed 12-bit monotonic ±1/2 ±1/2 LSB typ Offset Error ±50 ±50 mV max V range REF Gain Error ±1 ±1 % max AV range DD ±1 ±1 % typ V range REF Gain Error Mismatch 0.5 0.5 % typ % of full-scale on DAC1 ANALOG OUTPUTS Voltage Range_0 0 to V 0 to V V typ DAC V = 2.5 V REF REF REF Voltage Range_1 0 to V 0 to V V typ DAC V = V DD DD REF DD Output Impedance 0.5 0.5 Ω typ Rev. B | Page 3 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Parameter V = 5 V V = 3 V Unit Test Conditions/Comments DD DD DAC AC CHARACTERISTICS Voltage Output Settling Time 15 15 µs typ Full-scale settling time to within ½ LSB of final value Digital-to-Analog Glitch Energy 10 10 nV-sec typ 1 LSB change at major carry DAC CHANNEL SPECIFICATIONS12, 13 Internal Buffer Disabled ADuC841/ADuC842 Only DC ACCURACY10 Resolution 12 12 Bits Relative Accuracy ±3 ±3 LSB typ Differential Nonlinearity11 –1 –1 LSB max Guaranteed 12-bit monotonic ±1/2 ±1/2 LSB typ Offset Error ±5 ±5 mV max V range REF Gain Error ±0.5 ±0.5 % typ V range REF Gain Error Mismatch4 0.5 0.5 % typ % of full-scale on DAC1 ANALOG OUTPUTS Voltage Range_0 0 to V 0 to V V typ DAC V = 2.5 V REF REF REF REFERENCE INPUT/OUTPUT REFERENCE OUTPUT14 Output Voltage (V ) 2.5 2.5 V REF Accuracy ±10 ±10 mV Max Of V measured at the C pin REF REF T = 25°C A Power Supply Rejection 65 67 dB typ Reference Temperature Coefficient ±15 ±15 ppm/°C typ Internal V Power-On Time 2 2 ms typ REF EXTERNAL REFERENCE INPUT15 Voltage Range (V ) 4 1 1 V min REF V V V max DD DD Input Impedance 20 20 kΩ typ Input Leakage 1 1 µA max Internal band gap deselected via ADCCON1.6 POWER SUPPLY MONITOR (PSM) DV Trip Point Selection Range 2.93 V min Two trip points selectable in this DD 3.08 V max range programmed via TPD1–0 in PSMCON, 3 V part only DV Power Supply Trip Point Accuracy ±2.5 % max DD WATCHDOG TIMER (WDT) 4 Timeout Period 0 0 ms min Nine timeout periods selectable in 2000 2000 ms max this range FLASH/EE MEMORY RELIABILITY CHARACTERISTICS16 Endurance17 100,000 100,000 Cycles min Data Retention18 100 100 Years min DIGITAL INPUTS Input Leakage Current (Port 0, EA) ±10 ±10 µA max VIN = 0 V or VDD ±1 ±1 µA typ V = 0 V or V IN DD Logic 1 Input Current (All Digital Inputs), SDATA, SCLOCK ±10 ±10 µA max V = V IN DD ±1 ±1 µA typ V = V IN DD Logic 0 Input Current (Ports 1, 2, 3) SDATA, SCLOCK –75 –25 µA max –40 –15 µA typ V = 450 mV IL Logic 1 to Logic 0 Transition Current (Ports 2 and 3) –660 –250 µA max V = 2 V IL –400 –140 µA typ V = 2 V IL RESET ±10 ±10 µA max V = 0 V IN 10 5 µA min V = 5 V, 3 V Internal Pull Down IN 105 35 µA max V = 5 V, 3 V Internal Pull Down IN Rev. B | Page 4 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Parameter V = 5 V V = 3 V Unit Test Conditions/Comments DD DD LOGIC INPUTS4 INPUT VOLTAGES All Inputs Except SCLOCK, SDATA, RESET, and XTAL1 VINL, Input Low Voltage 0.8 0.4 V max VINH, Input High Voltage 2.0 2.0 V min SDATA VINL, Input Low Voltage 0.8 0.8 V max VINH, Input High Voltage 2.0 2.0 V min SCLOCK and RESET ONLY4 (Schmitt-Triggered Inputs) V 1.3 0.95 V min T+ 3.0 0.25 V max V 0.8 0.4 V min T– 1.4 1.1 V max V – V 0.3 0.3 V min T+ T– 0.85 0.85 V max CRYSTAL OSCILLATOR Logic Inputs, XTAL1 Only V , Input Low Voltage 0.8 0.4 V typ INL V , Input High Voltage 3.5 2.5 V typ INH XTAL1 Input Capacitance 18 18 pF typ XTAL2 Output Capacitance 18 18 pF typ MCU CLOCK RATE 16.78 8.38 MHz max ADuC842/ADuC843 Only 20 8.38 MHz max ADuC841 Only DIGITAL OUTPUTS Output High Voltage (V ) 2.4 V min V = 4.5 V to 5.5 V OH DD 4 V typ I = 80 µA SOURCE 2.4 V min V = 2.7 V to 3.3 V DD 2.6 V typ I = 20 µA SOURCE Output Low Voltage (V ) OL ALE, Ports 0 and 2 0.4 0.4 V max I = 1.6 mA SINK 0.2 0.2 V typ I = 1.6 mA SINK Port 3 0.4 0.4 V max I = 4 mA SINK SCLOCK/SDATA 0.4 0.4 V max I = 8 mA, I2C Enabled SINK Floating State Leakage Current4 ±10 ±10 µA max ±1 ±1 µA typ STARTUP TIME At any core CLK At Power-On 500 500 ms typ From Idle Mode 100 100 µs typ From Power-Down Mode Wake-up with INT0 Interrupt 150 400 µs typ Wake-up with SPI/I2C Interrupt 150 400 µs typ Wake-up with External RESET 150 400 µs typ After External RESET in Normal Mode 30 30 ms typ After WDT Reset in Normal Mode 3 3 ms typ Controlled via WDCON SFR Rev. B | Page 5 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Parameter V = 5 V V = 3 V Unit Test Conditions/Comments DD DD POWER REQUIREMENTS19, 20 Power Supply Voltages AV /DV – AGND 2.7 V min AV /DV = 3 V nom DD DD DD DD 3.6 V max 4.75 V min AV /DV = 5 V nom DD DD 5.25 V max Power Supply Currents Normal Mode21 DV Current4 10 4.5 mA typ Core CLK = 2.097 MHz DD AV Current 1.7 1.7 mA max Core CLK = 2.097 MHz DD DV Current 38 12 mA max Core CLK = 16.78 MHz/8.38 MHz 5 V/3 V DD 33 10 mA typ Core CLK = 16.78 MHz/8.38 MHz 5 V/3 V AV Current 1.7 1.7 mA max Core CLK = 16.78 MHz/8.38 MHz 5 V/3 V DD DVDD Current4 45 N/A mA max Core CLK = 20MHz ADuC841 Only Power Supply Currents Idle Mode21 DV Current 4.5 2.2 mA typ Core CLK = 2.097 MHz DD AV Current 3 2 µA typ Core CLK = 2.097 MHz DD DV Current4 12 5 mA max Core CLK = 16.78 MHz/8.38 MHz 5 V/3 V DD 10 3.5 mA typ Core CLK = 16.78 MHz/8.38 MHz 5 V/3 V AV Current 3 2 µA typ Core CLK = 16.78 MHz/8.38 MHz 5 V/3 V DD Power Supply Currents Power-Down Mode21 Core CLK = any frequency DV Current 28 18 µA max Oscillator Off / TIMECON.1 = 0 DD 20 10 µA typ AVDD Current 2 1 µA typ Core CLK = any frequency, ADuC841 Only DV Current4 3 1 mA max TIMECON.1 = 1 DD DV Current4 50 22 µA max Core CLK = any frequency DD 40 15 µA typ ADuC842/ADuC843 Only, oscillator on Typical Additional Power Supply Currents PSM Peripheral 15 10 µA typ AV = DV DD DD ADC4 1.0 1.0 mA min MCLK Divider = 32 2.8 1.8 mA max MCLK Divider = 2 DAC 150 130 µA typ See footnotes on the next page. Rev. B | Page 6 of 95

Data Sheet ADuC841/ADuC842/ADuC843 1 Temperature Range –40°C to +85°C. 2 ADC linearity is guaranteed during normal MicroConverter core operation. 3 ADC LSB size = VREF/212, that is, for internal VREF = 2.5 V, 1 LSB = 610 µV, and for external VREF = 1 V, 1 LSB = 244 µV. 4 These numbers are not production tested but are supported by design and/or characterization data on production release. 5 Offset and gain error and offset and gain error match are measured after factory calibration. 6 Based on external ADC system components, the user may need to execute a system calibration to remove additional external channel errors to achieve these specifications. 7 SNR calculation includes distortion and noise components. 8 Channel-to-channel crosstalk is measured on adjacent channels. 9 The temperature monitor gives a measure of the die temperature directly; air temperature can be inferred from this result. 10 DAC linearity is calculated using: Reduced code range of 100 to 4095, 0 V to VREF range. Reduced code range of 100 to 3945, 0 V to VDD range. DAC output load = 10 kΩ and 100 pF. 11 DAC differential nonlinearity specified on 0 V to VREF and 0 V to VDD ranges. 12 DAC specification for output impedance in the unbuffered case depends on DAC code. 13 DAC specifications for ISINK, voltage output settling time, and digital-to-analog glitch energy depend on external buffer implementation in unbuffered mode. DAC in unbuffered mode tested with OP270 external buffer, which has a low input leakage current. 14 Measured with CREF pin decoupled with 0.47 µF capacitor to ground. Power-up time for the internal reference is determined by the value of the decoupling capacitor chosen for the CREF pin. 15 When using an external reference device, the internal band gap reference input can be bypassed by setting the ADCCON1.6 bit. 16 Flash/EE memory reliability characteristics apply to both the Flash/EE program memory and the Flash/EE data memory. 17 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40°C, +25°C, and +85°C. Typical endurance at 25°C is 700,000 cycles. 18 Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6 eV derates with junction temperature as shown in Figure 38 in the Flash/EE Memory Reliability section. 19 Power supply current consumption is measured in normal, idle, and power-down modes under the following conditions: Normal Mode: Reset = 0.4 V, digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON (ADuC842/ADuC843), core executing internal software loop. Idle Mode: Reset = 0.4 V, digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON (ADuC842/ADuC843), PCON.0 = 1, core execution suspended in idle mode. Power-Down Mode: Reset = 0.4 V, all Port 0 pins = 0.4 V, All other digital I/O and Port 1 pins are open circuit, Core Clk changed via CD bits in PLLCON (ADuC842/ADuC843), PCON.0 = 1, core execution suspended in power-down mode, OSC turned on or off via OSC_PD bit (PLLCON.7) in PLLCON SFR (ADuC842/ADuC843). 20 DVDD power supply current increases typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle. 21 Power supply currents are production tested at 5.25 V and 3.3 V for a 5 V and 3 V part, respectively. Rev. B | Page 7 of 95

ADuC841/ADuC842/ADuC843 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. TA = 25°C, unless otherwise noted Stresses at or above those listed under Absolute Maximum Parameter Rating Ratings may cause permanent damage to the product. This is a AV to DV –0.3 V to +0.3 V DD DD stress rating only; functional operation of the product at these AGND to DGND –0.3 V to +0.3 V or any other conditions above those indicated in the operational DV to DGND, AV to AGND –0.3 V to +7 V DD DD section of this specification is not implied. Operation beyond Digital Input Voltage to DGND –0.3 V to DV + 0.3 V DD the maximum operating conditions for extended periods may Digital Output Voltage to DGND –0.3 V to DV + 0.3 V DD affect product reliability. V to AGND –0.3 V to AV + 0.3 V REF DD ESD CAUTION Analog Inputs to AGND –0.3 V to AV + 0.3 V DD Operating Temperature Range, Industrial –40°C to +85°C ADuC841BS, ADuC842BS, ADuC843BS, ADuC841BCP, ADuC842BCP, ADuC843BCP Storage Temperature Range –65°C to +150°C Junction Temperature 150°C θ Thermal Impedance (ADuC84xBS) 90°C/W JA θ Thermal Impedance (ADuC84xBCP) 52°C/W JA Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 12-BIT ADuC841/ADuC842/ADuC843 VOLTAGE DAC0 OUTPUT DAC AADDCC01 T/H 1A2D-CBIT COAANDNTCDROL CODNATCROL OUVTO1P2LU-TBTAI TGDEAC DAC1 ... CALIBRATION 16-BIT Σ-∆DAC MUX ADC..6. COPNWTRMOL Σ1-∆6-BDIATC MUX PWM0 16-BIT ADC7 PWM PWM1 62 kBYTES PROGRAM 16-BIT TEMP FLASH/EE INCLUDING PWM SENSOR USER MDOOWDENLOAD 256 BYRTAEMS USER T0 RBEAFNEDR EGNACPE 4 kBFLYATSEHS /DEEATA 8052 WATTICMHEDROG CTO1IMU6-NEBTRITESR TT12 2 kBYTES USER XRAM MCU T2EX CORE BUF POWER SUPPLY 2× DATA POINTERS MONITOR 11-BIT STACK POINTER INT0 CREF DOWNLOADER TIME INTERVAL INT1 DEBUGGER COUNTER (WAKE-UP CCT) NR POR ASSYENR(CUIAHALRR POTO)NROTUS TUIAMRETR SINGLE-PIEMULATO SESR(YII2NACCL AH INNRTDOE NSROPFIUA )SCE OPLSLC 03260-0-002 AVDD AGND DVDD DVDD DVDD DGND DGND DGND RESET RxD TxD ALE PSEN EA CLOCK A\MOSI MISO SS XTAL1 XTAL2 S T A D S Figure 2. ADuC841/ADuC842/ADuC843 Block Diagram (Shaded Areas are Features Not Present on the ADuC812), No DACs on ADuC843, PLL on ADuC842/ADuC843 Only. Rev. B | Page 8 of 95

Data Sheet ADuC841/ADuC842/ADuC843 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 7 6 5 4 3 2 1 0 7/A 6/A 5/A 4/A DDND 3/A 2/A 1/A 0/A E EN P0. P0. P0. P0. DV DG P0. P0. P0. P0. AL PS EA 52 51 50 49 48 47 46 45 44 43 42 41 40 P1.0/ADC0/T2 1 39 P2.7/PWM1/A15/A23 PIN 1 P1.1/ADC1/T2EX 2 IDENTIFIER 38 P2.6/PWM0/A14/A22 P1.2/ADC2 3 37 P2.5/A13/A21 P1.3/ADC3 4 36 P2.4/A12/A20 AVDD 5 ADuC841/ADuC842/ADuC843 35 DGND AGND 6 52-LEAD MQFP 34 DVDD CREF 7 TOP VIEW 33 XTAL2 VREF 8 (Not to Scale) 32 XTAL1 DAC0 9 31 P2.3/A11/A19 DAC1 10 30 P2.2/A10/A18 P1.4/ADC4 11 29 P2.1/A9/A17 P1.5/ADC5/SS 12 28 P2.0/A8/A16 P1.6/ADC6 13 27 SDATA/MOSI 14 15 16 17 18 19 20 21 22 23 24 25 26 P1.7/ADC7 RESET P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1/MISO/PWM1DVDDDGNDPWMC/PWM0/EXTCLK* P3.5/T1/CONVSTP3.6/WRP3.7/RD SCLOCK 0/ T *EXTCLK NOT PRESENT P3.4/ON THE ADuC841. 03260-003 Figure 3. 52-Lead MQFP Pin Configuration Table 3. 52-Lead MQFP Pin Function Descriptions Pin No. Mnemonic Type1 Description 1 P1.0/ADC0/T2 I Input Port 1 (P1.0). Port 1 is an 8-bit input port only. Unlike the other ports, Port 1 defaults to analog input mode. To configure this port pin as a digital input, write a 0 to the port bit. Single-Ended Analog Input (ADC0). Channel selection is via ADCCON2 SFR. Timer 2 Digital Input (T2). Input to Timer/Counter 2. When enabled, Counter 2 is incremented in response to a 1 to 0 transition of the T2 input. 2 P1.1/ADC1/T2EX I Input Port 1 (P1.1). Port 1 is an 8-bit input port only. Unlike the other ports, Port 1 defaults to analog input mode. To configure this port pin as a digital input, write a 0 to the port bit. Single-Ended Analog Input 1 (ADC1). Channel selection is via ADCCON2 SFR. Capture/Reload Trigger for Counter 2 (T2EX). T2EX is a digital input. This pin also functions as an up/down control input for Counter 2. 3 P1.2/ADC2 I Input Port 1 (P1.2). Port 1 is an 8-bit input port only. Unlike the other ports, Port 1 defaults to analog input mode. To configure this port pin as a digital input, write a 0 to the port bit. Single-Ended Analog Input (ADC2). Channel selection is via ADCCON2 SFR. 4 P1.3/ADC3 I Input Port 1 (P1.3). Port 1 is an 8-bit input port only. Unlike the other ports, Port 1 defaults to analog input mode. To configure this port pin as a digital input, write a 0 to the port bit. Single-Ended Analog Input (ADC3). Channel selection is via ADCCON2 SFR. 5 AV P Analog Positive Supply Voltage. 3 V or 5 V nominal. DD 6 AGND G Analog Ground. AGND is the ground reference point for the analog circuitry. 7 C I/O Decoupling Input for On-Chip Reference. Connect a 0.47 µF capacitor between this REF pin and AGND. 8 V NC Not Connected. This was a reference output on the ADuC812; use the C pin REF REF instead. 9 DAC0 O Voltage Output from DAC0. This pin is a no connect on the ADuC843. 10 DAC1 O Voltage Output from DAC1. This pin is a no connect on the ADuC843. Rev. B | Page 9 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Pin No. Mnemonic Type1 Description 11 P1.4/ADC4 Input Port 1 (P1.4). Port 1 is an 8-bit input port only. Unlike the other ports, Port 1 defaults to analog input mode. To configure this port pin as a digital input, write a 0 to the port bit. Single-Ended Analog Input 4 (ADC4). Channel selection is via ADCCON2 SFR. 12 P1.5/ADC5/SS I Input Port 1 (P1.5). Port 1 is an 8-bit input port only. Unlike the other ports, Port 1 defaults to analog input mode. To configure this port pin as a digital input, write a 0 to the port bit. Single-Ended Analog Input 5 (ADC5). Channel selection is via ADCCON2 SFR. Slave Select Input for the SPI Interface (SS). 13 P1.6/ADC6 I Input Port 1 (P1.6). Port 1 is an 8-bit input port only. Unlike the other ports, Port 1 defaults to analog input mode. To configure this port pin as a digital input, write a 0 to the port bit. Single-Ended Analog Input 6 (ADC6). Channel selection is via ADCCON2 SFR. 14 P1.7/ADC7 I Input Port 1(P1.7). Port 1 is an 8-bit input port only. Unlike the other ports, Port 1 defaults to analog input mode. To configure this port pin as a digital input, write a 0 to the port bit. Single-Ended Analog Input 7 (ADC7). Channel selection is via ADCCON2 SFR. 15 RESET I Reset. Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the device. 16 P3.0/RxD I/O Input/Output Port 3 (P3.0). Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of the Serial (UART) Port (RxD). 17 P3.1/TxD I/O Input/Output Port 3 (P3.1). Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of the Serial (UART) Port (TxD). 18 P3.2/INT0 I/O Input/Output Port 3 (P3.2). Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Interrupt 0 (INT0). Programmable edge or level triggered interrupt input; can be programmed to one of two priority levels. This pin can also be used as a gate control input to Timer 0. 19 P3.3/INT1/MISO/PWM1 I/O Input/Output Port 3 (P3.3). Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Interrupt 1 (INT1). Programmable edge or level triggered interrupt input; can be programmed to one of two priority levels. This pin can also be used as a gate control input to Timer 1. SPI Master Input/Slave Output Data I/O Pin for SPI Serial Interface (MISO). PWM 1 Voltage Output (PWM1). See the CFG841/CFG842 register for further information. 20, 34, 48 DV P Digital Positive Supply Voltage. 3 V or 5 V nominal. DD 21, 35, 47 DGND G Digital Ground. DGND is the ground reference point for the digital circuitry. Rev. B | Page 10 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Pin No. Mnemonic Type1 Description 22 P3.4/T0/PWMC/PWM0/EXTCLK I/O Input/Output Port 3 (P3.4). Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Timer/Counter 0 Input (T0). PWM Clock Input (PWMC). PWM 0 Voltage Output (PWM0). PWM outputs can be configured to use Port 2.6 and Port 2.7 or Port 3.4 and Port 3.3. Input for External Clock Signal (EXTCLK). This pin function must be enabled via the CFG842 register. 23 P3.5/T1/CONVST I/O Input/Output Port 3 (P3.5). Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Timer/Counter 1 Input (T1). Active Low Convert Start Logic Input for the ADC Block When the External Convert Start Function is Enabled (CONVST). A low to high transition on this input puts the track-and-hold into hold mode and starts the conversion. 24 P3.6/WR I/O Input/Output Port 3 (P3.6). Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Write Control Signal, Logic Output (WR). Latches the data byte from Port 0 into the external data memory. 25 P3.7/RD I/O Input/Output Port 3 (P3.7). Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Read Control Signal, Logic Output (RD). Enables the external data memory to Port 0. 26 SCLOCK I/O Serial Clock Pin for I2C-Compatible Clock or for SPI Serial Interface Clock. 27 SDATA/MOSI I/O User Selectable, I2C Compatible, or SPI Data Input/Output Pin (SDATA). SPI Master Output/Slave Input Data I/O Pin for SPI Interface (MOSI). 28 P2.0/A8/A16 I/O Input/Output Port 2 (P2.0). Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. External Memory Addresses (A8). Port 2 emits the middle order address byte during accesses to the external 24-bit external data memory space. External Memory Addresses (A16). Port 2 emits the high order address byte during accesses to the external 24-bit external data memory space. 29 P2.1/A9/A17 I/O Input/Output Port 2 (P2.1). Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. External Memory Addresses (A9). Port 2 emits the middle order address byte during accesses to the external 24-bit external data memory space. External Memory Addresses (A17). Port 2 emits the high order address byte during accesses to the external 24-bit external data memory space. 30 P2.2/A10/A18 I/O Input/Output Port 2 (P2.2). Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. External Memory Addresses (A10). Port 2 emits the middle order address byte during accesses to the external 24-bit external data memory space. External Memory Addresses (A18). Port 2 emits the high order address byte during accesses to the external 24-bit external data memory space. Rev. B | Page 11 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Pin No. Mnemonic Type1 Description 31 P2.3/A11/A19 I/O Input/Output Port 2 (P2.3). Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. External Memory Addresses (A11). Port 2 emits the middle order address byte during accesses to the external 24-bit external data memory space. External Memory Addresses (A19). Port 2 emits the high order address byte during accesses to the external 24-bit external data memory space. 32 XTAL1 I Input to the Inverting Oscillator Amplifier. 33 XTAL2 O Output of the Inverting Oscillator Amplifier. 36 P2.4/A12/A20 I/O Input/Output Port 2 (P2.4). Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. External Memory Addresses (A12). Port 2 emits the middle order address byte during accesses to the external 24-bit external data memory space. External Memory Addresses (A20). Port 2 emits the high order address byte during accesses to the external 24-bit external data memory space. 37 P2.5/A13/A21 I/O Input/Output Port 2 (P2.5). Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. External Memory Addresses (A13). Port 2 emits the middle order address byte during accesses to the external 24-bit external data memory space. External Memory Addresses (A21). Port 2 emits the high order address byte during accesses to the external 24-bit external data memory space. 38 P2.6/PWM0/A14/A22 I/O Input/Output Port 2 (P2.6). Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. PWM 0 Voltage Output (PWM0). PWM outputs can be configured to use Port 2.6 and Port 2.7 or Port 3.4 and Port 3.3. External Memory Addresses (A14). Port 2 emits the middle order address byte during accesses to the external 24-bit external data memory space. External Memory Addresses (A22). Port 2 emits the high order address byte during accesses to the external 24-bit external data memory space. 39 P2.7/PWM1/A15/A23 I/O Input/Output Port 2 (P2.7). Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. PWM 1 Voltage Output (PWM1). See the CFG841/CFG842 register for further information. External Memory Addresses (A15). Port 2 emits the middle-order address byte during accesses to the external 24-bit external data memory space. External Memory Addresses (A23). Port 2 emits the high-order address bytes during accesses to the external 24-bit external data memory space. 40 EA I External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal program memory locations. The devices do not support external code memory. Do not leave this pin floating. 41 PSEN O Program Store Enable, Logic Output. This pin remains low during internal program execution. PSEN enables serial download mode when pulled low through a resistor on power-up or reset. On reset, this pin momentarily becomes an input and the status of the pin is sampled. If there is no pull-down resistor in place, the pin goes momentarily high and then user code executes. If a pull-down resistor is in place, the embedded serial download/debug kernel executes. 42 ALE O Address Latch Enable, Logic Output. This output latches the low byte and page byte for 24-bit address space accesses of the address into external data memory. Rev. B | Page 12 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Pin No. Mnemonic Type1 Description 43 P0.0/A0 I/O Input/Output Port 0 (P0.0). Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. External Memory Address (A0). Port 0 is also the multiplexed low order address and data bus during accesses to external data memory. In this application, it uses strong internal pull-up resistors when emitting 1s. 44 P0.1/A1 I/O Input/Output Port 0 (P0.1). Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. External Memory Address (A1). Port 0 is also the multiplexed low order address and data bus during accesses to external data memory. In this application, it uses strong internal pull-up resistors when emitting 1s. 45 P0.2/A2 I/O Input/Output Port 0 (P0.2). Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. External Memory Address (A2). Port 0 is also the multiplexed low order address and data bus during accesses to external data memory. In this application, it uses strong internal pull-up resistors when emitting 1s. 46 P0.3/A3 I/O Input/Output Port 0 (P0.3).Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. External Memory Address (A3). Port 0 is also the multiplexed low order address and data bus during accesses to external data memory. In this application, it uses strong internal pull-up resistors when emitting 1s. 49 P0.4/A4 I/O Input/Output Port 0 (P0.4). Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. External Memory Address (A4). Port 0 is also the multiplexed low order address and data bus during accesses to external data memory. In this application, it uses strong internal pull-up resistors when emitting 1s. 50 P0.5/A5 I/O Input/Output Port 0 (P0.5). Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. External Memory Address (A5). Port 0 is also the multiplexed low order address and data bus during accesses to external data memory. In this application, it uses strong internal pull-up resistors when emitting 1s. 51 P0.6/A6 I/O Input/Output Port 0 (P0.6). Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. External Memory Address (A6). Port 0 is also the multiplexed low order address and data bus during accesses to external data memory. In this application, it uses strong internal pull-up resistors when emitting 1s. 52 P0.7/A7 I/O Input/Output Port 0 (P0.7). Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. External Memory Address (A7). Port 0 is also the multiplexed low order address and data bus during accesses to external data memory. In this application, it uses strong internal pull-up resistors when emitting 1s. 1 P = power, G = ground, I= input, O = output., NC = no connect. Rev. B | Page 13 of 95

ADuC841/ADuC842/ADuC843 Data Sheet 2 T 0/ C D 7 6 5 4 3 2 1 0 0/A 7/A 6/A 5/A 4/A DDND 3/A 2/A 1/A 0/A E EN 1. 0. 0. 0. 0.V G 0. 0. 0. 0. L S A P P P P PD D P P P P A P E 6 543 2 1098 765 43 5 555 5 5544 444 44 P1.1/ADC1/T2EX 1 42 P2.7/A15/A23 P1.2/ADC2 2 41 P2.6/A14/A22 P1.3/ADC3 3 40 P2.5/A13/A21 AVDD 4 39 P2.4/A12/A20 AVDD 5 38 DGND AGND 6 37 DGND ADuC841/ADuC842/ADuC843 AGND 7 56-LEAD LFCSP 36 DVDD AGND 8 35 XTAL2 TOP VIEW CREF 9 (Not to Scale) 34 XTAL1 VREF 10 33 P2.3/A11/A19 DAC0 11 32 P2.2/A10/A18 DAC1 12 31 P2.1/A9/A17 P1.4/ADC4 13 30 P2.0/A8/A16 P1.5/ADC5/SS 14 29 SDATA/MOSI 5 678 9 012 3 4 5 67 8 1 111 1 222 2 2 2 22 2 P1.6/ADC6 P.7/ADC7 RESET P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1/MISO/PWM1DVDDDGND PWMC/PWM0/EXTCLK* P3.5/T1/CONVST P3.6/WR P3.7/RD SCLOCK 0/ T 4/ 3. P *EXTCLK NOT PRESENT ON THEADuC841 NOTES 1. RMTHEEIATSAS LOLF NPCSLSA.P TT HHEAI SOS NMA ETNHT AEELX P PPROLINSATTEEEDD MP ACUDISR TTC HUNAIOTTT B MBOUEAS CRTOD B N(EPN CSEBOC)TL FEDODERRT EOMD EGTCROHO ATUNHNIECDA.L 03260-004 Figure 4. 56-Lead LFCSP Pin Configuration Table 4. 56-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Type1 Description 1 P1.1/ADC1/T2EX I Input Port 1 (P1.1). Port 1 is an 8-bit input port only. Unlike the other ports, Port 1 defaults to analog input mode. To configure this port pin as a digital input, write a 0 to the port bit. Single-Ended Analog Input 1 (ADC1). Channel selection is via ADCCON2 SFR. Capture/Reload Trigger for Counter 2 (T2EX). Digital Input. This pin also functions as an up/down control input for Counter 2. 2 P1.2/ADC2 I Input Port 1 (P1.2). Port 1 is an 8-bit input port only. Unlike the other ports, Port 1 defaults to analog input mode. To configure this port pin as a digital input, write a 0 to the port bit. Single-Ended Analog Input (ADC2). Channel selection is via ADCCON2 SFR. 3 P1.3/ADC3 I Input Port 1 (P1.3). Port 1 is an 8-bit input port only. Unlike the other ports, Port 1 defaults to analog input mode. To configure this port pin as a digital input, write a 0 to the port bit. Single-Ended Analog Input (ADC3). Channel selection is via ADCCON2 SFR. 4, 5 AV P Analog Positive Supply Voltage. 3 V or 5 V nominal. DD 6, 7, 8 AGND G Analog Ground. AGND is the ground reference point for the analog circuitry. 9 C I/O Decoupling Input for On-Chip Reference. Connect a 0.47 µF capacitor between REF this pin and AGND. 10 V NC Not Connected. This was a reference output on the ADuC812; use the C pin REF REF instead. 11 DAC0 O Voltage Output from DAC0. This pin is a no connect on the ADuC843. Rev. B | Page 14 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Pin No. Mnemonic Type1 Description 12 DAC1 O Voltage Output from DAC1. This pin is a no connect on the ADuC843. 13 P1.4/ADC4 Input Port 1 (P1.0). Port 1 is an 8-bit input port only. Unlike the other ports, Port 1 defaults to analog input mode. To configure this port pin as a digital input, write a 0 to the port bit. Single-Ended Analog Input 4 (ADC4). Channel selection is via ADCCON2 SFR. 14 P1.5/ADC5/SS I Input Port 1 (P1.5). Port 1 is an 8-bit input port only. Unlike the other ports, Port 1 defaults to analog input mode. To configure this port pin as a digital input, write a 0 to the port bit. Single-Ended Analog Input 5 (ADC5). Channel selection is via ADCCON2 SFR. Slave Select Input for the SPI Interface (SS). 15 P1.3/ADC6 I Input Port 1 (P1.3). Port 1 is an 8-bit input port only. Unlike the other ports, Port 1 defaults to analog input mode. To configure this port pin as a digital input, write a 0 to the port bit. Single-Ended Analog Input 6 (ADC6). Channel selection is via ADCCON2 SFR. 16 P1.7/ADC7 I Input Port 1(P1.7). Port 1 is an 8-bit input port only. Unlike the other ports, Port 1 defaults to analog input mode. To configure this port pin as a digital input, write a 0 to the port bit. Single-Ended Analog Input 7 (ADC7). Channel selection is via ADCCON2 SFR. 17 RESET I Reset. Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the device. 18 P3.0/RxD I/O Input/Output Port 3 (P3.0). Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of the Serial (UART) Port (RxD). 19 P3.1/TxD I/O Input/Output Port 3 (P3.1). Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of the Serial (UART) Port (TxD). 20 P3.2/INT0 I/O Input/Output Port 3 (P3.2). Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Interrupt 0 (INT0). Programmable edge or level triggered interrupt input; can be programmed to one of two priority levels. This pin can also be used as a gate control input to Timer 0. 21 P3.3/INT1/MISO/PWM1 I/O Input/Output Port 3 (P3.3). Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Interrupt 1 (INT1). Programmable edge or level triggered interrupt input; can be programmed to one of two priority levels. This pin can also be used as a gate control input to Timer 1. SPI Master Input/Slave Output Data I/O Pin for SPI Serial Interface (MISO). PWM 1 Voltage Output (PWM1). See the CFG841/CFG842 register for further information. 22, 36, 51 DV P Digital Positive Supply Voltage. 3 V or 5 V nominal. DD 23, 37, 38, DGND G Digital Ground. DGND is the ground reference point for the digital circuitry. 50 Rev. B | Page 15 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Pin No. Mnemonic Type1 Description 24 P3.4/T0/PWMC/PWM0/EXTCLK I/O Input/Output Port 3 (P3.4). Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Timer/Counter 0 Input (T0). PWM Clock Input (PWMC). PWM 0 Voltage Output (PWM0). PWM outputs can be configured to use Port 2.6 and Port 2.7 or Port 3.4 and Port 3.3. Input for External Clock Signal (EXTCLK). This pin function must be enabled via the CFG842 register. 25 P3.5/T1/CONVST I/O Input/Output Port 3 (P3.5). Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Timer/Counter 1 Input (T1). Active Low Convert Start Logic Input for the ADC Block when the External Convert Start Function is Enabled (CONVST). A low to high transition on this input puts the track-and-hold into hold mode and starts the conversion. 26 P3.6/WR I/O Input/Output Port 3 (P3.6). Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Write Control Signal, Logic Output (WR). Latches the data byte from Port 0 into the external data memory. 27 P3.7/RD I/O Input/Output Port 3 (P3.7). Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Read Control Signal, Logic Output (RD). Enables the external data memory to Port 0. 28 SCLOCK I/O Serial Clock Pin for I2C-Compatible Clock or for SPI Serial Interface Clock. 29 SDATA/MOSI I/O User Selectable, I2C Compatible, or SPI Data Input/Output Pin (SDATA). SPI Master Output/Slave Input Data I/O Pin for SPI Interface (MOSI). 30 P2.0/A8/A16 I/O Input/Output Port 2 (P2.0). Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. External Memory Addresses (A8). Port 2 emits the middle order address byte during accesses to the external 24-bit external data memory space. External Memory Addresses (A16). Port 2 emits the high order address byte during accesses to the external 24-bit external data memory space. 31 P2.1/A9/A17 I/O Input/Output Port 2 (P2.1). Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. External Memory Addresses (A9). Port 2 emits the middle order address byte during accesses to the external 24-bit external data memory space. External Memory Addresses (A17). Port 2 emits the high order address byte during accesses to the external 24-bit external data memory space. 32 P2.2/A10/A18 I/O Input/Output Port 2 (P2.2). Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. External Memory Addresses (A10). Port 2 emits the middle address byte during accesses to the external 24-bit external data memory space. External Memory Addresses (A18). Port 2 emits the high-order address byte during accesses to the external 24-bit external data memory space. Rev. B | Page 16 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Pin No. Mnemonic Type1 Description 33 P2.3/A11/A19 I/O Input/Output Port 2 (P2.3). Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. External Memory Addresses (A11). Port 2 emits the middle order address byte during accesses to the external 24-bit external data memory space. External Memory Addresses (A19). Port 2 emits the high order address byte during accesses to the external 24-bit external data memory space. 34 XTAL1 I Input to the Inverting Oscillator Amplifier. 35 XTAL2 O Output of the Inverting Oscillator Amplifier. 39 P2.4/A12/A20 I/O Input/Output Port 2 (P2.4). Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. External Memory Addresses (A12). Port 2 emits the middle order address byte during accesses to the external 24-bit external data memory space. External Memory Addresses (A20). Port 2 emits the high order address byte during accesses to the external 24-bit external data memory space. 40 P2.5/A13/A21 I/O Input/Output Port 2 (P2.5). Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. External Memory Addresses (A13). Port 2 emits the middle order address byte during accesses to the external 24-bit external data memory space. External Memory Addresses (A21). Port 2 emits the high order address byte during accesses to the external 24-bit external data memory space. 41 P2.6/A14/A22 I/O Input/Output Port 2 (P2.6). Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. External Memory Addresses (A14). Port 2 emits the middle order address byte during accesses to the external 24-bit external data memory space. External Memory Addresses (A22). Port 2 emits the high order address byte during accesses to the external 24-bit external data memory space. 42 P2.7/A15/A23 I/O Input/Output Port 2 (P2.7). Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. External Memory Addresses (A15). Port 2 emits the middle order address byte during accesses to the external 24-bit external data memory space. External Memory Addresses (A23). Port 2 emits the high order address byte during accesses to the external 24-bit external data memory space. 43 EA I External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal program memory locations. The devices do not support external code memory. Do not leave this pin floating. 44 PSEN O Program Store Enable, Logic Output. This pin remains low during internal program execution. PSEN enables serial download mode when pulled low through a resistor on power-up or reset. On reset, this pin momentarily becomes an input and the status of the pin is sampled. If there is no pull-down resistor in place, the pin goes momentarily high and then user code executes. If a pull-down resistor is in place, the embedded serial download/debug kernel executes. 45 ALE O Address Latch Enable, Logic Output. This output latches the low byte and page byte for 24-bit address space accesses of the address into external data memory. Rev. B | Page 17 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Pin No. Mnemonic Type1 Description 46 P0.0/A0 I/O Input/Output Port 0 (P0.0). Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. External Memory Address (A0). Port 0 is also the multiplexed low order address and data bus during accesses to external data memory. In this application, it uses strong internal pull-ups when emitting 1s. 47 P0.1/A1 I/O Input/Output Port 0 (P0.1). Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. External Memory Address (A1). Port 0 is also the multiplexed low order address and data bus during accesses to external data memory. In this application, it uses strong internal pull-up resistors when emitting 1s. 48 P0.2/A2 I/O Input/Output Port 0 (P0.2). Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. External Memory Address (A2). Port 0 is also the multiplexed low order address and data bus during accesses to external data memory. In this application, it uses strong internal pull-up resistors when emitting 1s. 49 P0.3/A3 I/O Input/Output Port 0 (P0.3). Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. External Memory Address (A3). Port 0 is also the multiplexed low order address and data bus during accesses to external data memory. In this application, it uses strong internal pull-up resistors when emitting 1s. 52 P0.4/A4 I/O Input/Output Port 0 (P0.4). Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. External Memory Address (A4). Port 0 is also the multiplexed low order address and data bus during accesses to external data memory. In this application, it uses strong internal pull-up resistors when emitting 1s. 53 P0.5/A5 I/O Input/Output Port 0 (P0.5). Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. External Memory Address (A5). Port 0 is also the multiplexed low order address and data bus during accesses to external data memory. In this application, it uses strong internal pull-up resistors when emitting 1s. 54 P0.6/A6 I/O Input/Output Port 0 (P0.6). Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. External Memory Address (A6). Port 0 is also the multiplexed low order address and data bus during accesses to external data memory. In this application, it uses strong internal pull-up resistors when emitting 1s. 55 P0.7/A7 I/O Input/Output Port 0 (P0.7). Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. External Memory Address (A7). Port 0 is also the multiplexed low order address and data bus during accesses to external data memory. In this application, it uses strong internal pull-up resistors when emitting 1s. 56 P1.0/ADC0/T2 I Input Port 1 (P1.0). Port 1 is an 8-bit input port only. Unlike the other ports, Port 1 defaults to analog input mode. To configure this port pin as a digital input, write a 0 to the port bit. Single-Ended Analog Input (ADC0). Channel selection is via ADCCON2 SFR. Timer 2 Digital Input (T2). Input to Timer/Counter 2. When enabled, Counter 2 is incremented in response to a 1-to-0 transition of the T2 input. EPAD Exposed Pad. The LFCSP has an exposed pad that must be soldered to the metal plate on the printed circuit board (PCB) for mechanical reasons. This metal plate must not be connected to GND. 1 P = power, G = ground, I = input, O = output, and NC = no connect. Rev. B | Page 18 of 95

Data Sheet ADuC841/ADuC842/ADuC843 TERMINOLOGY ADC SPECIFICATIONS DAC SPECIFICATIONS Integral Nonlinearity Relative Accuracy The maximum deviation of any code from a straight line Relative accuracy or endpoint linearity is a measure of the passing through the endpoints of the ADC transfer function. maximum deviation from a straight line passing through the The endpoints of the transfer function are zero scale, a point endpoints of the DAC transfer function. It is measured after ½ LSB below the first code transition, and full scale, a point adjusting for zero error and full-scale error. ½ LSB above the last code transition. Voltage Output Settling Time Differential Nonlinearity The amount of time it takes for the output to settle to a The difference between the measured and the ideal 1 LSB specified level for a full-scale input change. change between any two adjacent codes in the ADC. Digital-to-Analog Glitch Impulse Offset Error The amount of charge injected into the analog output when the The deviation of the first code transition (0000 . . . 000) to inputs change state. It is specified as the area of the glitch in nV-sec. (0000 . . . 001) from the ideal, that is, +½ LSB. Gain Error The deviation of the last code transition from the ideal AIN voltage (Full Scale – ½ LSB) after the offset error has been adjusted out. Signal-to-(Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f/2), excluding dc. S The ratio depends on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB Thus for a 12-bit converter, this is 74 dB. Total Harmonic Distortion (THD) The ratio of the rms sum of the harmonics to the fundamental. Rev. B | Page 19 of 95

ADuC841/ADuC842/ADuC843 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS The typical performance plots presented in this section Figure 16 shows a histogram plot of 10,000 ADC conversion illustrate typical performance of the ADuC841/ADuC842/ results on a dc input for VDD = 3 V. The plot again illustrates a ADuC843 under various operating conditions. very tight code distribution of 1 LSB with the majority of codes appearing in one output pin. Figure 5 and Figure 6 show typical ADC integral nonlinearity (INL) errors from ADC Code 0 to Code 4095 at 5 V and 3 V Figure 17 and Figure 18 show typical FFT plots for the parts. supplies, respectively. The ADC is using its internal reference These plots were generated using an external clock input. The (2.5 V) and is operating at a sampling rate of 152 kHz; the ADC is using its internal reference (2.5 V), sampling a full- typical worst-case errors in both plots are just less than 0.3 LSB. scale, 10 kHz sine wave test tone input at a sampling rate of Figure 7 and Figure 8 also show ADC INL at a higher sampling 149.79 kHz. The resulting FFTs shown at 5 V and 3 V supplies rate of 400 kHz. Figure 9 and Figure 10 show the variation in illustrate an excellent 100 dB noise floor, 71 dB signal-to-noise worst-case positive (WCP) INL and worst-case negative (WCN) ratio (SNR), and THD greater than –80 dB. INL versus external reference input voltage. Figure 19 and Figure 20 show typical dynamic performance Figure 11 and Figure 12 show typical ADC differential versus external reference voltages. Again, excellent ac perform- nonlinearity (DNL) errors from ADC Code 0 to Code 4095 at ance can be observed in both plots with some roll-off being 5 V and 3 V supplies, respectively. The ADC is using its internal observed as VREF falls below 1 V. reference (2.5 V) and is operating at a sampling rate of 152 kHz; Figure 21 shows typical dynamic performance versus sampling the typical worst-case errors in both plots are just less than frequency. SNR levels of 71 dB are obtained across the sampling 0.2 LSB. Figure 13 and Figure 14 show the variation in worst- range of the parts. case positive (WCP) DNL and worst-case negative (WCN) DNL versus external reference input voltage. Figure 22 shows the voltage output of the on-chip temperature sensor versus temperature. Although the initial voltage output Figure 15 shows a histogram plot of 10,000 ADC conversion at 25°C can vary from part to part, the resulting slope of results on a dc input with V = 5 V. The plot illustrates an DD −1. 4 mV/°C is constant across all parts. excellent code distribution pointing to the low noise performance of the on-chip precision ADC. 1.0 1.0 0.8 AfSV =D D1 5/ 2DkVHDzD = 5V 0.8 AfVS D=D 1/5D2VkDHDz = 3V 0.6 0.6 0.4 0.4 0.2 0.2 LSBs 0 LSBs 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.00 511 1023 1535ADC2 0C4O7DES2559 3071 3583 409503260-0-005 –1.00 511 1023 1535ADC2 0C4O7DES2559 3071 3583 4095 03260-0-006 Figure 5. Typical INL Error, VDD = 5 V, fs = 152 kHz Figure 6. Typical INL Error, VDD = 3 V, fs = 152 kHz Rev. B | Page 20 of 95

Data Sheet ADuC841/ADuC842/ADuC843 1.0 0.8 0.8 0.8 AfSV =D D4/0D0VkDHDz = 5V 0.6 AfSV D=D 1/5D2VkDHDz = 3V 0.6 CD = 4 0.6 0.4 WCP INL 0.4 0.4 0.2 SBs) 0.2 0.2 SBs) L L SBs 0 (NL 0 0 (NL L–0.2 WCP–I–0.2 –0.2WCN–I –0.4 –0.4 WCN INL –0.4 –0.6 –0.6 –0.6 –0.8 –1.00 511 1023 1535ADC2 0C4O7DES2559 3071 3583 409503260-0-098 –0.8 0.5 1.E0XTERN1A.5L REFE2R.0ENCE(2V.)5 3.0 –0.8 03260-0-008 Figure 7. Typical INL Error, VDD = 5 V, fS = 400 kHz Figure 10. Typical Worst-Case INL Error vs. VREF, VDD = 3 V 1.0 1.0 0.8 AfSV =D D4/0D0VkDHDz = 3V 0.8 AfSV =D D1/5D2VkDHDz = 5V CD = 4 0.6 0.6 0.4 0.4 0.2 0.2 LSBs 0 LSBs 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.00 511 1023 1535ADC2 0C4O7DES2559 3071 3583 409503260-0-099 –1.00 511 1023 1535ADC2 0C4O7DES2559 3071 3583 4095 03260-0-009 Figure 8. Typical INL Error, VDD = 3 V, fS = 400 kHz Figure 11. Typical DNL Error, VDD = 5 V 1.2 0.6 1.0 AVDD/DVDD = 5V AVDD/DVDD = 3V 1.0 fS = 152kHz 0.8 fS = 152kHz 0.4 0.8 0.6 Bs)0.6 WCP INL 0.2 Bs) 0.4 S S 0.2 L0.4 L NL ( 0 NL ( SBs 0 P–I0.2 N–I L C C –0.2 W W 0 –0.2 –0.4 –0.2 WCN INL –0.4 –0.6 –0.4 –0.8 –0.6 0.5 1.E0XTERN1A.5L REFE2R.0ENCE (2V.)5 5.0 –0.6 03260-0-007 –1.00 511 1023 1535ADC2 0C4O7DES2559 3071 3583 409503260-0-010 Figure 9. Typical Worst-Case INL Error vs. VREF, VDD = 5 V Figure 12. Typical DNL Error, VDD = 3 V Rev. B | Page 21 of 95

ADuC841/ADuC842/ADuC843 Data Sheet 0.6 0.6 10000 AVDD /DVDD = 5V fS = 152kHz 9000 0.4 0.4 8000 Bs) 0.2 WCP DNL 0.2 Bs) E7000 S S C6000 L L N (WCP–DNL–0.20 –00.2 (WCN–DNL OCCURRE45000000 3000 WCN DNL –0.4 –0.4 2000 1000 –0.6 0.5 1.E0XTERN1A.5L REFE2R.0ENCE 2(V.5) 5.0 –0.6 03260-0-011 0 817 818 C8O19DE 820 821 03260-0-014 Figure 13. Typical Worst-Case DNL Error vs. VREF, VDD = 5 V Figure 16. Code Histogram Plot, VDD = 3 V 0.7 0.7 20 0.5 AfSV =D D1/5D2VkDHDz= 3V 0.5 0 fAfSINV =D= D 195/.D92V1k0HDkDzH =z 5V SNR = 71.3dB WCP DNL –20 THD =–88.0dB 0.3 0.3 ENOB = 11.6 Bs) Bs) –40 NL (LS 0.1 0.1 NL (LS Bs –60 –D–0.1 –0.1 –D d –80 CP WCN DNL CN W W –100 –0.3 –0.3 –120 –0.5 –0.5 –140 –0.7 0.5 1.E0XTERN1A.5L REFE2R.0ENCE 2(V.5) 3.0 –0.7 03260-0-012 –1600 10 20 FREQ30UENCY 4(k0Hz) 50 60 7003260-0-015 Figure 14. Typical Worst-Case DNL Error vs. VREF, VDD = 3 V Figure 17. Dynamic Performance at VDD = 5 V 10000 20 AVDD/DVDD = 3V 0 fS = 149.79kHz fIN = 9.910kHz 8000 SNR = 71.0dB –20 THD =–83.0dB ENOB = 11.5 –40 E C6000 N E –60 R s R B CU d –80 C4000 O –100 –120 2000 –140 0 817 818 C8O19DE 820 821 03260-0-013 –1600 10 20 FRE3Q0UENCY4 (0kHz) 50 60 70 03260-0-016 Figure 15. Code Histogram Plot, VDD = 5 V Figure 18. Dynamic Performance at VDD = 3 V Rev. B | Page 22 of 95

Data Sheet ADuC841/ADuC842/ADuC843 80 –70 80 AVDD/DVDD = 5V 78 AVDD /DVDD = 5V 75 fS = 152kHz –75 76 SNR 74 70 –80 SNR (dBs) 65 THD –85 THD (dBs) (dBs)SNR 677820 60 –90 66 64 55 –95 62 50 0.5 1.E0XTERN1A.5L REFE2R.0ENCE(2V.)5 5.0 –100 03260-0-017 6065.476 92.262 119.050 145.830 172.620 199.410 226.190 300.000 350.000 400.000 03260-0-019 FREQUENCY (kHz) Figure 19. Typical Dynamic Performance vs. VREF, VDD = 5 V Figure 21. Typical Dynamic Performance vs. Sampling Frequency 80 –70 0.9 75 AfSV D=D 1/5D2VkDHDz = 3V –75 0.8 ASLVODDP/ED V=D–D1 .=4 m3VV/°C SNR 0.7 70 –80 Bs) THD Bs) GE0.6 R (d65 –85 D (d LTA SN TH VO0.5 60 –90 0.4 55 –95 0.3 50 0.5 1.E0XTERN1A.5L REFE2R.0ENCE (2V.)5 3.0 –100 03260-0-018 0.2 –40 TEMPERA2T5URE (°C) 85 03260-0-100 Figure 20. Typical Dynamic Performance vs. VREF, VDD = 3 V Figure 22. Typical Temperature Sensor Output vs. Temperature GENERAL DESCRIPTION (continued) However, there is also the option to allow SPI operate separately The parts also incorporate additional analog functionality with on P3.3, P3.4, and P3.5, while I2C uses the standard pins. The two 12-bit DACs, power supply monitor, and a band gap I2C interface has also been enhanced to offer repeated start, reference. On-chip digital peripherals include two 16-bit ∑-∆. general call, and quad addressing. DACs, a dual output 16-bit PWM, a watchdog timer, a time interval counter, three timers/counters, and three serial I/O On-chip factory firmware supports in-circuit serial download ports (SPI, I2C, and UART). and debug modes (via UART) as well as single-pin emulation On the ADuC812 and the ADuC832, the I2C and SPI interfaces mode via the EA pin. A functional block diagram of the parts is share some of the same pins. For backwards compatibility, this shown on the first page. is also the case for the ADuC841/ADuC842/ADuC843. Rev. B | Page 23 of 95

ADuC841/ADuC842/ADuC843 Data Sheet FUNCTIONAL DESCRIPTION 8052 INSTRUCTION SET Table 5 documents the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles, resulting in a 16 MIPS peak performance when operating at PLLCON = 00H on the ADuC842/ADuC843. On the ADuC841, 20 MIPS peak performance is possible with a 20 MHz external crystal. Table 5. Instructions Mnemonic Description Bytes Cycles Arithmetic ADD A,Rn Add register to A 1 1 ADD A,@Ri Add indirect memory to A 1 2 ADD A,dir Add direct byte to A 2 2 ADD A,#data Add immediate to A 2 2 ADDC A,Rn Add register to A with carry 1 1 ADDC A,@Ri Add indirect memory to A with carry 1 2 ADDC A,dir Add direct byte to A with carry 2 2 ADD A,#data Add immediate to A with carry 2 2 SUBB A,Rn Subtract register from A with borrow 1 1 SUBB A,@Ri Subtract indirect memory from A with borrow 1 2 SUBB A,dir Subtract direct from A with borrow 2 2 SUBB A,#data Subtract immediate from A with borrow 2 2 INC A Increment A 1 1 INC Rn Increment register 1 1 INC @Ri Increment indirect memory 1 2 INC dir Increment direct byte 2 2 INC DPTR Increment data pointer 1 3 DEC A Decrement A 1 1 DEC Rn Decrement register 1 1 DEC @Ri Decrement indirect memory 1 2 DEC dir Decrement direct byte 2 2 MUL AB Multiply A by B 1 9 DIV AB Divide A by B 1 9 DA A Decimal adjust A 1 2 Logic ANL A,Rn AND register to A 1 1 ANL A,@Ri AND indirect memory to A 1 2 ANL A,dir AND direct byte to A 2 2 ANL A,#data AND immediate to A 2 2 ANL dir,A AND A to direct byte 2 2 ANL dir,#data AND immediate data to direct byte 3 3 ORL A,Rn OR register to A 1 1 ORL A,@Ri OR indirect memory to A 1 2 ORL A,dir OR direct byte to A 2 2 ORL A,#data OR immediate to A 2 2 ORL dir,A OR A to direct byte 2 2 ORL dir,#data OR immediate data to direct byte 3 3 XRL A,Rn Exclusive-OR register to A 1 1 XRL A,@Ri Exclusive-OR indirect memory to A 2 2 XRL A,#data Exclusive-OR immediate to A 2 2 XRL dir,A Exclusive-OR A to direct byte 2 2 Rev. B | Page 24 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Mnemonic Description Bytes Cycles XRL A,dir Exclusive-OR indirect memory to A 2 2 XRL dir,#data Exclusive-OR immediate data to direct 3 3 CLR A Clear A 1 1 CPL A Complement A 1 1 SWAP A Swap nibbles of A 1 1 RL A Rotate A left 1 1 RLC A Rotate A left through carry 1 1 RR A Rotate A right 1 1 RRC A Rotate A right through carry 1 1 Data Transfer MOV A,Rn Move register to A 1 1 MOV A,@Ri Move indirect memory to A 1 2 MOV Rn,A Move A to register 1 1 MOV @Ri,A Move A to indirect memory 1 2 MOV A,dir Move direct byte to A 2 2 MOV A,#data Move immediate to A 2 2 MOV Rn,#data Move register to immediate 2 2 MOV dir,A Move A to direct byte 2 2 MOV Rn, dir Move register to direct byte 2 2 MOV dir, Rn Move direct to register 2 2 MOV @Ri,#data Move immediate to indirect memory 2 2 MOV dir,@Ri Move indirect to direct memory 2 2 MOV @Ri,dir Move direct to indirect memory 2 2 MOV dir,dir Move direct byte to direct byte 3 3 MOV dir,#data Move immediate to direct byte 3 3 MOV DPTR,#data Move immediate to data pointer 3 3 MOVC A,@A+DPTR Move code byte relative DPTR to A 1 4 MOVC A,@A+PC Move code byte relative PC to A 1 4 MOVX A,@Ri Move external (A8) data to A 1 4 MOVX A,@DPTR Move external (A16) data to A 1 4 MOVX @Ri,A Move A to external data (A8) 1 4 MOVX @DPTR,A Move A to external data (A16) 1 4 PUSH dir Push direct byte onto stack 2 2 POP dir Pop direct byte from stack 2 2 XCH A,Rn Exchange A and register 1 1 XCH A,@Ri Exchange A and indirect memory 1 2 XCHD A,@Ri Exchange A and indirect memory nibble 1 2 XCH A,dir Exchange A and direct byte 2 2 Boolean CLR C Clear carry 1 1 CLR bit Clear direct bit 2 2 SETB C Set carry 1 1 SETB bit Set direct bit 2 2 CPL C Complement carry 1 1 CPL bit Complement direct bit 2 2 ANL C,bit AND direct bit and carry 2 2 ANL C,/bit AND direct bit inverse to carry 2 2 ORL C,bit OR direct bit and carry 2 2 ORL C,/bit OR direct bit inverse to carry 2 2 MOV C,bit Move direct bit to carry 2 2 MOV bit,C Move carry to direct bit 2 2 Rev. B | Page 25 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Mnemonic Description Bytes Cycles Branching JMP @A+DPTR Jump indirect relative to DPTR 1 3 RET Return from subroutine 1 4 RETI Return from interrupt 1 4 ACALL addr11 Absolute jump to subroutine 2 3 AJMP addr11 Absolute jump unconditional 2 3 SJMP rel Short jump (relative address) 2 3 JC rel Jump on carry equal to 1 2 3 JNC rel Jump on carry equal to 0 2 3 JZ rel Jump on accumulator = 0 2 3 JNZ rel Jump on accumulator not equal to 0 2 3 DJNZ Rn,rel Decrement register, JNZ relative 2 3 LJMP Long jump unconditional 3 4 LCALL addr16 Long jump to subroutine 3 4 JB bit,rel Jump on direct bit = 1 3 4 JNB bit,rel Jump on direct bit = 0 3 4 JBC bit,rel Jump on direct bit = 1 and clear 3 4 CJNE A,dir,rel Compare A, direct JNE relative 3 4 CJNE A,#data,rel Compare A, immediate JNE relative 3 4 CJNE Rn,#data,rel Compare register, immediate JNE relative 3 4 CJNE @Ri,#data,rel Compare indirect, immediate JNE relative 3 4 DJNZ dir,rel Decrement direct byte, JNZ relative 3 4 Miscellaneous NOP No operation 1 1 1. One cycle is one clock. 2. Cycles of MOVX instructions are four cycles when they have 0 wait state. Cycles of MOVX instructions are 4 + n cycles when they have n wait states. 3. Cycles of LCALL instruction are three cycles when the LCALL instruction comes from interrupt. OTHER SINGLE-CYCLE CORE FEATURES Timer Operation External Memory Access Timers on a standard 8052 increment by 1 with each machine There is no support for external program memory access on the cycle. On the ADuC841/ADuC842/ADuC843, one machine parts. When accessing external RAM, the EWAIT register may cycle is equal to one clock cycle; therefore the timers increment need to be programmed to give extra machine cycles to MOVX at the same rate as the core clock. commands. This is to account for differing external RAM access ALE speeds. EWAIT SFR The output on the ALE pin on a standard 8052 part is a clock at 1/6th of the core operating frequency. On the ADuC841/ SFR Address 9FH ADuC842/ADuC843 the ALE pin operates as follows. For a Power-On Default 00H single machine cycle instruction, ALE is high for the first half of the machine cycle and low for the second half. The ALE output Bit Addressable No is at the core operating frequency. For a two or more machine cycle instruction, ALE is high for the first half of the first machine cycle and low for the rest of the machine cycles. This special function register (SFR) is programmed with the number of wait states for a MOVX instruction. This value can range from 0H to 7H. Rev. B | Page 26 of 95

Data Sheet ADuC841/ADuC842/ADuC843 MEMORY ORGANIZATION The ADuC841/ADuC842/ADuC843 each contain four different The lower 128 bytes of internal data memory are mapped as memory blocks: shown in Figure 23. The lowest 32 bytes are grouped into four banks of eight registers addressed as R0 to R7. The next 16 bytes • Up to 62 kBytes of on-chip Flash/EE program memory (128 bits), locations 20H to 2FH above the register banks, form • 4 kBytes of on-chip Flash/EE data memory a block of directly addressable bit locations at Bit Addresses • 256 bytes of general-purpose RAM 00H to 7FH. The stack can be located anywhere in the internal memory address space, and the stack depth can be expanded up • 2 kBytes of internal XRAM to 2048 bytes. Flash/EE Program Memory Reset initializes the stack pointer to location 07H and incre- The parts provide up to 62 kBytes of Flash/EE program mem- ments it once before loading the stack to start from location ory to run user code. The user can run code from this internal 08H, which is also the first register (R0) of register bank 1. memory only. Unlike the ADuC812, where code execution can Thus, if the user needs to use more than one register bank, the overflow from the internal code space to external code space stack pointer should be initialized to an area of RAM not used once the PC becomes greater than 1FFFH, the parts do not for data storage. support the roll-over from F7FFH in internal code space to 7FH F800H in external code space. Instead, the 2048 bytes between GENERAL-PURPOSE F800H and FFFFH appear as NOP instructions to user code. AREA This internal code space can be downloaded via the UART 30H 2FH serial port while the device is in-circuit. 56 kBytes of the BIT-ADDRESSABLE program memory can be reprogrammed during run time; thus BANKS (BIT ADDRESSES) SELECTED the code space can be upgraded in the field by using a user VIA 20H defined protocol, or it can be used as a data memory. This is BITS IN PSW 1FH 11 discussed in more detail in the Flash/EE Memory section. 18H 17H For the 32 kBytes memory model, the top 8 kBytes function as 10 10H FOUR BANKS OF EIGHT the ULOAD space; this is explained in the Flash/EE Memory 0FH REGISTERS section. 01 R0 TO R7 08H Flash/EE Data Memory 4 kBytes of Flash/EE data memory are available to the user and 00 00H 07H RSTEASCEKT VPAOLINUTEE ORF 03260-0-021 can be accessed indirectly via a group of control registers Figure 23. Lower 128 Bytes of Internal Data Memory mapped into the special function register (SFR) area. Access to the Flash/EE data memory is discussed in detail in the Flash/EE The parts contain 2048 bytes of internal XRAM, 1792 bytes of Memory section. which can be configured to an extended 11-bit stack pointer. General-Purpose RAM By default, the stack operates exactly like an 8052 in that it rolls over from FFH to 00H in the general-purpose RAM. On the The general-purpose RAM is divided into two separate parts, however, it is possible (by setting CFG841.7 or CFG842.7) memories: the upper and the lower 128 bytes of RAM. The to enable the 11-bit extended stack pointer. In this case, the lower 128 bytes of RAM can be accessed through direct or stack rolls over from FFH in RAM to 0100H in XRAM. indirect addressing. The upper 128 bytes of RAM can be accessed only through indirect addressing because it shares the The 11-bit stack pointer is visible in the SP and SPH SFRs. The same address space as the SFR space, which can be accessed SP SFR is located at 81H as with a standard 8052. The SPH SFR only through direct addressing. is located at B7H. The 3 LSBs of this SFR contain the 3 extra bits necessary to extend the 8-bit stack pointer into an 11-bit stack pointer. Rev. B | Page 27 of 95

ADuC841/ADuC842/ADuC843 Data Sheet 07FFH FFFFFFH FFFFFFH UPPER 1792 BYTES OF EXTERNAL EXTERNAL ON-CHIP XRAM DATA DATA (DATA + STACK MEMORY MEMORY FOR EXSP = 1, SPACE SPACE DATA ONLY (24-BIT (24-BIT FOR EXSP = 0) ADDRESS ADDRESS CFG841.7 = 0 CFG841.7 = 1 SPACE) SPACE) CFG842.7 = 0 CFG842.7 = 1 100H 000800H FFH 0007FFH 256 BYTES OF LOWER 256 2 kBYTES ON-CHIP DATA BYTES OF ON-CHIP 00H (SDTRAAATCMAK +) 00H O(ND-ACTHAIP O XNRLAYM) 03260-0-022 000000H CCFFGG884412..00 == 00 000000H CCFFGGX88R44A12M..00 == 10 03260-0-023 Figure 24. Extended Stack Pointer Operation Figure 25. Internal and External XRAM External Data Memory (External XRAM) SPECIAL FUNCTION REGISTERS (SFRS) Just like a standard 8051 compatible core, the ADuC841/ ADuC842/ADuC843 can access external data memory by using The SFR space is mapped into the upper 128 bytes of internal a MOVX instruction. The MOVX instruction automatically data memory space and is accessed by direct addressing only. It outputs the various control strobes required to access the data provides an interface between the CPU and all on-chip periph- memory. erals. A block diagram showing the programming model of the parts via the SFR area is shown in Figure 26. The parts, however, can access up to 16 MBytes of external data memory. This is an enhancement of the 64 kBytes of external All registers, except the program counter (PC) and the four data memory space available on a standard 8051 compatible core. general-purpose register banks, reside in the SFR area. The SFR The external data memory is discussed in more detail in the registers include control, configuration, and data registers, which Hardware Design Considerations section. provide an interface between the CPU and all on-chip peripherals. Internal XRAM 4-kBYTE The parts contain 2 kBytes of on-chip data memory. This 62-kBYTE ELECTRICALLY ELECTRICALLY REPROGRAMMABLE memory, although on-chip, is also accessed via the MOVX REPROGRAMMABLE NONVOLATILE NONVOLATILE FLASH/EE DATA instruction. The 2 kBytes of internal XRAM are mapped into FLASH/EE PROGRAM MEMORY MEMORY the bottom 2 kBytes of the external address space if the CFG841/CFG842 bit is set. Otherwise, access to the external data memory occurs just like a standard 8051. When using the 8-CHANNEL 128-BYTE 12-BIT ADC internal XRAM, Ports 0 and 2 are free to be used as general- 8051 SPECIAL COMPATIBLE FUNCTION purpose I/O. CORE REGISTER AREA OTHER ON-CHIP PERIPHERALS TEMPERATURE SENSOR 2×12-BIT DACs 2304 BYTES SERIAL I/O RAM WDT PSM TIC PWM 03260-0-024 Figure 26. Programming Model Rev. B | Page 28 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Program Status Word (PSW) ACCUMULATOR SFR (ACC) The PSW SFR contains several bits reflecting the current status ACC is the accumulator register and is used for math opera- of the CPU, as detailed in Table 6. tions including addition, subtraction, integer multiplication and division, and Boolean bit manipulations. The mnemonics for SFR Address D0H accumulator-specific instructions refer to the accumulator as A. Power-On Default 00H B SFR (B) Bit Addressable Yes The B register is used with the ACC for multiplication and division operations. For other instructions, it can be treated as a Table 6. PSW SFR Bit Designations general-purpose scratchpad register. Bit Name Description Stack Pointer (SP and SPH) 7 CY Carry Flag. The SP SFR is the stack pointer and is used to hold an internal 6 AC Auxiliary Carry Flag. RAM address that is called the top of the stack. The SP register 5 F0 General-Purpose Flag. is incremented before data is stored during PUSH and CALL 4 RS1 Register Bank Select Bits. executions. While the stack may reside anywhere in on-chip 3 RS0 RS1 RS0 Selected Bank RAM, the SP register is initialized to 07H after a reset, which 0 0 0 causes the stack to begin at location 08H. 0 1 1 1 0 2 As mentioned earlier, the parts offer an extended 11-bit stack 1 1 3 pointer. The 3 extra bits used to make up the 11-bit stack 2 OV Overflow Flag. pointer are the 3 LSBs of the SPH byte located at B7H. 1 F1 General-Purpose Flag. Data Pointer (DPTR) 0 P Parity Bit. The data pointer is made up of three 8-bit registers named DPP (page byte), DPH (high byte), and DPL (low byte). These are Power Control SFR (PCON) used to provide memory addresses for internal and external The PCON SFR contains bits for power-saving options and code access and for external data access. They may be manipu- general-purpose status flags, as shown in Table 7. lated as a 16-bit register (DPTR = DPH, DPL), although INC DPTR instructions automatically carry over to DPP, or as three SFR Address 87H independent 8-bit registers (DPP, DPH, DPL). The parts support Power-On Default 00H dual data pointers. Refer to the Dual Data Pointer section. Bit Addressable No Table 7. PCON SFR Bit Designations Bit No. Name Description 7 SMOD Double UART Baud Rate. 6 SERIPD I2C/SPI Power-Down Interrupt Enable. 5 INT0PD INT0 Power-Down Interrupt Enable. 4 ALEOFF Disable ALE Output. 3 GF1 General-Purpose Flag Bit. 2 GF0 General-Purpose Flag Bit. 1 PD Power-Down Mode Enable. 0 IDL Idle Mode Enable. Rev. B | Page 29 of 95

ADuC841/ADuC842/ADuC843 Data Sheet SPECIAL FUNCTION REGISTER BANKS implemented, that is, no register exists at this location. If an All registers except the program counter and the four general- unoccupied location is read, an unspecified value is returned. purpose register banks reside in the special function register SFR locations reserved for on-chip testing are shown lighter (SFR) area. The SFR registers include control, configuration, shaded (RESERVED) and should not be accessed by user and data registers, which provide an interface between the CPU software. Sixteen of the SFR locations are also bit addressable and other on-chip peripherals. Figure 27 shows a full SFR and denoted by 1 in Figure 27, that is, the bit addressable SFRs memory map and SFR contents on reset. Unoccupied SFR are those whose address ends in 0H or 8H. locations are shown dark-shaded in the figure (NOT USED). Unoccupied locations in the SFR address space are not ISPI WCOL SPE SPIM CPOL CPHA SPR1 SPR0 SPICON1 DAC0L DAC0H DAC1L DAC1H DACCON BITS RESERVED RESERVED FFH 0 FEH 0 FDH 0 FCH 0 FBH 0 FAH 1 F9H 0 F8H 0 F8H 04H F9H 00H FAH 00H FBH 00H FCH 00H FDH 04H B1 ADCOFSL3ADCOFSH3ADCGAINL3ADCGAINH3ADCCON3 SPIDAT BITS RESERVED F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H 0 F1H 0 F0H 0 F0H 00H F1H 00H F2H 20H F3H 00H F4H 00H F5H 00H F7H 00H I2CSI/MDOI2CGC/MDEI2C1O1MCOI2C1O0/MDI I2CM I2CRS I2CTX I2CI BITS I2CCON1 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVEDADCCON1 EFH 0 EEH 0 EDH 0 ECH 0 EBH 0 EAH 0 E9H 0 E8H 0 E8H 00H EFH 40H ACC1 BITS RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED E7H 0 E6H 0 E5H 0 E4H 0 E3H 0 E2H 0 E1H 0 E0H 0 E0H 00H ADCI DMA CCONVSCONV CS3 CS2 CS1 CS0 ADCCON21ADCDATALADCDATAH PSMCON BITS RESERVED RESERVED RESERVED RESERVED DFH 0 DEH 0 DDH 0 DCH 0 DBH 0 DAH 0 D9H 0 D8H 0 D8H 00H D9H 00H DAH 00H DFH DEH CY AC F0 RS1 RS0 OV FI P PSW1 DMAL DMAH DMAP PLLCON BITS RESERVED RESERVED RESERVED D7H 0 D6H 0 D5H 0 D4H 0 D3H 0 D2H 0 D1H 0 D0H 0 D0H 00H D2H 00H D3H 00H D4H 00H D7H 53H TF2 EXF2 RCLK TCLK EXEN2 TR2 CNT2 CAP2 T2CON1 RCAP2L RCAP2H TL2 TH2 BITS RESERVED RESERVED RESERVED CFH 0 CEH 0 CDH 0 CCH 0 CBH 0 CAH 0 C9H 0 C8H 0 C8H 00H CAH 00H CBH 00H CCH 00H CDH 00H PRE3 PRE2 PRE1 PRE0 WDIR WDS WDE WDWR BITS WDCON1 RESERVED CHIPID RESERVED RESERVED RESERVED EDARL EDARH C7H 0 C6H 0 C5H 0 C4H 1 C3H 0 C2H 0 C1H 0 C0H 0 C0H 10H C2H XXH C6H 00H C7H 00H PSI PADC PT2 PS PT1 PX1 PT0 PX0 BITS IP1 ECON RESERVED RESERVED EDATA1 EDATA2 EDATA3 EDATA4 BFH 0 BEH 0 BDH 0 BCH 0 BBH 0 BAH 0 B9H 0 B8H 0 B8H 00H B9H 00H BCH 00H BDH 00H BEH 00H BFH 00H RD WR T1 T0 INT1 INT0 TxD RxD P31 PWM0L PWM0H PWM1L PWM1H SPH BITS NOT USED NOT USED B7H 1 B6H 1 B5H 1 B4H 1 B3H 1 B2H 1 B1H 1 B0H 1 B0H FFH B1H 00HB2H 00HB3H 00H B4H 00H B7H 00H EA EADC ET2 ES ET1 EX1 ET0 EX0 IE1 IEIP2 PWMCON CFG841/ BITS RESERVED RESERVED RESERVED RESERVED CFG842 AFH 0 AEH 0 ADH 0 ACH 0 ABH 0 AAH 0 A9H 0 A8H 0 A8H 00H A9H A0H AEH 00HAFH 00H P21 TIMECON HTHSEC SEC MIN HOUR INTVAL DPCON BITS A7H 1 A6H 1 A5H 1 A4H 1 A3H 1 A2H 1 A1H 1 A0H 1 A0H FFH A1H 00H A2H 00H A3H 00H A4H 00H A5H 00H A6H 00H A7H 00H SM0 SM1 SM2 REN TB8 RB8 TI RI SCON1 SBUF I2CDAT I2CADD T3FD T3CON BITS NOT USED NOT USED 9FH 0 9EH 0 9DH 0 9CH 0 9BH 0 9AH 0 99H 0 98H 0 98H 00H 99H 00H 9AH 00H 9BH 55H 9DH 00H9EH 00H T2EX T2 P11, 2 I2CADD1 I2CADD2 I2CADD3 BITS NOT USED NOT USED NOT USED NOT USED 97H 1 96H 1 95H 1 94H 1 93H 1 92H 1 91H 1 90H 1 90H FFH 91H 7FH 92H 7FH 93H 7FH TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 BITS TCON1 TMOD TL0 TL1 TH0 TH1 RESERVED RESERVED 8FH 0 8EH 0 8DH 0 8CH 0 8BH 0 8AH 0 89H 0 88H 0 88H 00H 89H 00H 8AH 00H 8BH 00H 8CH 00H 8DH 00H P01 SP DPL DPH DPP PCON BITS RESERVED RESERVED 87H 1 86H 1 85H 1 84H 1 83H 1 82H 1 81H 1 80H 1 80H FFH 81H 07H 82H 00H 83H 00H 84H 00H 87H 00H SFR MAP KEY: THESE BITS ARE CONTAINED IN THIS BYTE. MNEMONIC IE0 IT0 TCON MNEMONIC SFR ADDRESS 89H 0 88H 0 88H 00H DEFAULT VALUE DEFAULT VALUE SFR ADDRESS NOTES 123 STCPHFOARELRs PIT BWR RPIHMIANOATSSRIEO,Y WN AFD RUCDINOTRCEEET FSAIOFS 0NI CE TONIEOFDN SPTT OHISNRE A0T CH1R O EIOSR R PAR R8SEHE AS CANPOR OAENNN FBDAIIGLTINO UAGGRD PDEINORDPER UOSTTNS 1PA P OBSORLFWETR;. E BTRHIT-EU.RPE FTOOR FEA, CTOT OERNAYB CLAEL TIHBER ADITGEITDA VL ASLEUCEOSN.DARY FUNCTIONS ON THESE 03260-0-025 Figure 27. Special Function Register Locations and Reset Values Rev. B | Page 30 of 95

Data Sheet ADuC841/ADuC842/ADuC843 ADC CIRCUIT INFORMATION General Overview ADC Transfer Function The ADC conversion block incorporates a fast, 8-channel, The analog input range for the ADC is 0 V to V . For this REF 12-bit, single-supply ADC. This block provides the user with range, the designed code transitions occur midway between multichannel mux, track-and-hold, on-chip reference, calibra- successive integer LSB values, that is, 0.5 LSB, 1.5 LSB, 2.5 LSB . tion features, and ADC. All components in this block are easily . . FS –1.5 LSB. The output coding is straight binary with 1 LSB configured via a 3-register SFR interface. = FS/4096 or 2.5 V/4096 = 0.61 mV when V = 2.5 V. The REF ideal input/output transfer characteristic for the 0 V to V REF The ADC converter consists of a conventional successive range is shown in Figure 28. approximation converter based around a capacitor DAC. The converter accepts an analog input range of 0 V to V . A high OUTPUT REF CODE precision, 15 ppm, low drift, factory calibrated 2.5 V reference is 111...111 provided on-chip. An external reference can be connected as 111...110 described in the Voltage Reference Connections section. This 111...101 external reference can be in the range 1 V to AV . 111...100 DD FS 1LSB = 4096 Single-step or continuous conversion modes can be initiated in software or alternatively by applying a convert signal to an external pin. Timer 2 can also be configured to generate a 000...011 000...010 repetitive trigger for ADC conversions. The ADC may be 000...001 ccoonntfiinguuroeuds ltyo coopnevrearttes iann ad DcaMptAu rmeso sdaem wphleesr etoby a nth eex AteDrnCa lb lock 000...0000V1LSB +FS 03260-0-026 RAM space without any interaction from the MCU core. This Figure 28. ADC Transfer Function automatic capture facility can extend through a 16 MByte external data memory space. Typical Operation The ADuC841/ADuC842/ADuC843 are shipped with factory Once configured via the ADCCON 1–3 SFRs, the ADC programmed calibration coefficients that are automatically converts the analog input and provides an ADC 12-bit result downloaded to the ADC on power-up, ensuring optimum ADC word in the ADCDATAH/L SFRs. The top 4 bits of the performance. The ADC core contains internal offset and gain ADCDATAH SFR are written with the channel selection bits to calibration registers that can be hardware calibrated to identify the channel result. The format of the ADC 12-bit result minimize system errors. word is shown in Figure 29. A voltage output from an on-chip band gap reference propor- tional to absolute temperature can also be routed through the ADCDATAH SFR front end ADC multiplexer (effectively a 9th ADC channel CH–ID HIGH 4 BITS OF TOP 4 BITS ADC RESULT WORD input), facilitating a temperature sensor implementation. ADCDATAL SFR LAODWC R8E BSITUSL TO WF OTHRED 03260-0-027 Figure 29. ADC Result Word Format Rev. B | Page 31 of 95

ADuC841/ADuC842/ADuC843 Data Sheet ADCCON1—(ADC Control SFR 1) The ADCCON1 register controls conversion and acquisition times, hardware conversion modes, and power-down modes as detailed below. SFR Address EFH SFR Power-On Default 40H Bit Addressable No Table 8. ADCCON1 SFR Bit Designations Bit No. Name Description 7 MD1 The mode bit selects the active operating mode of the ADC. Set by the user to power up the ADC. Cleared by the user to power down the ADC. 6 EXT_REF Set by the user to select an external reference. Cleared by the user to use the internal reference. 5 CK1 The ADC clock divide bits (CK1, CK0) select the divide ratio for the PLL master clock (ADuC842/ADuC843) or the 4 CK0 external crystal (ADuC841) used to generate the ADC clock. To ensure correct ADC operation, the divider ratio must be chosen to reduce the ADC clock to 8.38 MHz or lower. A typical ADC conversion requires 16 ADC clocks plus the selected acquisition time. The divider ratio is selected as follows: CK1 CK0 MCLK Divider 0 0 32 0 1 4 (Do not use with a CD setting of 0) 1 0 8 1 1 2 3 AQ1 The ADC acquisition select bits (AQ1, AQ0) select the time provided for the input track-and-hold amplifier to 2 AQ0 acquire the input signal. An acquisition of three or more ADC clocks is recommended; clocks are as follows: AQ1 AQ0 No. ADC Clks 0 0 1 0 1 2 1 0 3 1 1 4 1 T2C The Timer 2 conversion bit (T2C) is set by the user to enable the Timer 2 overflow bit to be used as the ADC conversion start trigger input. 0 EXC The external trigger enable bit (EXC) is set by the user to allow the external Pin P3.5 (CONVST) to be used as the active low convert start input. This input should be an active low pulse (minimum pulse width >100 ns) at the required sample rate. Rev. B | Page 32 of 95

Data Sheet ADuC841/ADuC842/ADuC843 ADCCON2—(ADC Control SFR 2) The ADCCON2 register controls ADC channel selection and conversion modes as detailed below. SFR Address D8H SFR Power-On Default 00H Bit Addressable Yes Table 9. ADCCON2 SFR Bit Designations Bit No. Name Description 7 ADCI ADC Interrupt Bit. Set by hardware at the end of a single ADC conversion cycle or at the end of a DMA block conversion. Cleared by hardware when the PC vectors to the ADC interrupt service routine. Otherwise, the ADCI bit is cleared by user code. 6 DMA DMA Mode Enable Bit. Set by the user to enable a preconfigured ADC DMA mode operation. A more detailed description of this mode is given in the ADC DMA Mode section. The DMA bit is automatically set to 0 at the end of a DMA cycle. Setting this bit causes the ALE output to cease; it starts again when DMA is started and operates correctly after DMA is complete. 5 CCONV Continuous Conversion Bit. Set by the user to initiate the ADC into a continuous mode of conversion. In this mode, the ADC starts converting based on the timing and channel configuration already set up in the ADCCON SFRs; the ADC automatically starts another conversion once a previous conversion has completed. 4 SCONV Single Conversion Bit. Set to initiate a single conversion cycle. The SCONV bit is automatically reset to 0 on completion of the single conversion cycle. 3 CS3 Channel Selection Bits. 2 CS2 Allow the user to program the ADC channel selection under software control. When a conversion is initiated, the 1 CS1 converted channel is the one pointed to by these channel selection bits. In DMA mode, the channel selection is 0 CS0 derived from the channel ID written to the external memory. CS3 CS2 CS1 CS0 CH# 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 Temp Monitor Requires minimum of 1 µs to acquire. 1 0 0 1 DAC0 Only use with internal DAC output buffer on. 1 0 1 0 DAC1 Only use with internal DAC output buffer on. 1 0 1 1 AGND 1 1 0 0 V REF 1 1 1 1 DMA STOP Place in XRAM location to finish DMA sequence; refer to the ADC DMA Mode section. All other combinations reserved. Rev. B | Page 33 of 95

ADuC841/ADuC842/ADuC843 Data Sheet ADCCON3—(ADC Control SFR 3) The ADCCON3 register controls the operation of various calibration modes and also indicates the ADC busy status. SFR Address F5H SFR Power-On Default 00H Bit Addressable No Table 10. ADCCON3 SFR Bit Designations Bit No. Name Description 7 BUSY ADC Busy Status Bit. A read-only status bit that is set during a valid ADC conversion or during a calibration cycle. Busy is automatically cleared by the core at the end of conversion or calibration. 6 RSVD Reserved. This bit should always be written as 0. 5 AVGS1 Number of Average Selection Bits. 4 AVGS0 This bit selects the number of ADC readings that are averaged during a calibration cycle. AVGS1 AVGS0 Number of Averages 0 0 15 0 1 1 1 0 31 1 1 63 3 RSVD Reserved. This bit should always be written as 0. 2 RSVD This bit should always be written as 1 by the user when performing calibration. 1 TYPICAL Calibration Type Select Bit. This bit selects between offset (zero-scale) and gain (full-scale) calibration. Set to 0 for offset calibration. Set to 1 for gain calibration. 0 SCAL Start Calibration Cycle Bit. When set, this bit starts the selected calibration cycle. It is automatically cleared when the calibration cycle is completed. Rev. B | Page 34 of 95

Data Sheet ADuC841/ADuC842/ADuC843 kHz sample rate. Though the R/C does help to reject some The ADC incorporates a successive approximation architecture incoming high frequency noise, its primary function is to ensure (SAR) involving a charge-sampled input stage. Figure 30 shows that the transient demands of the ADC input stage are met. the equivalent circuit of the analog input section. Each ADC conversion is divided into two distinct phases, as defined by the ADuC841/ position of the switches in Figure 30. During the sampling ADuC842/ phase (with SW1 and SW2 in the track position), a charge ADuC843 proportional to the voltage on the analog input is developed 10Ω AIN0 across the input sampling capacitor. During the conversion 0.1µF phase (with both switches in the hold position), the capacitor DNAodCe iAs aids j0u,s itnedd ivciaat iinngt etrhnaat lt ShAe Rsa lmogpilce du nchtial rtghee ovno ltthagee i nopnu t 03260-0-029 capacitor is balanced out by the charge being output by the Figure 31. Buffering Analog Inputs capacitor DAC. The final digital value contained in the SAR is It does so by providing a capacitive bank from which the 32 pF then latched out as the result of the ADC conversion. Control of sampling capacitor can draw its charge. Its voltage does not the SAR and timing of acquisition and sampling modes is change by more than one count (1/4096) of the 12-bit transfer handled automatically by built-in ADC control logic. function when the 32 pF charge from a previous channel is Acquisition and conversion times are also fully configurable dumped onto it. A larger capacitor can be used if desired, but under user control. not a larger resistor (for reasons described below). The Schottky diodes in Figure 31 may be necessary to limit the voltage ADuC841/ADuC842/ADuC843 applied to the analog input pin per the Absolute Maximum VREF AGND Ratings. They are not necessary if the op amp is powered from DAC1 the same supply as the part since in that case the op amp is DAC0 TEMPERATURE MONITOR unable to generate voltages above V or below ground. An op DD AIN7 amp of some kind is necessary unless the signal source is very low impedance to begin with. DC leakage currents at the parts’ analog inputs can cause measurable dc errors with external source impedances as low as 100 Ω or so. To ensure accurate AIN0 200Ω CAPDAACCITOR ADC operation, keep the total source impedance at each analog input less than 61 Ω. The Table 11 illustrates examples of how TRACK sw1 source impedance can affect dc accuracy. HOLD COMPARATOR 32pF Table 11. Source Impedance and DC Accuracy 200Ω NODE A sw2 Source Error from 1 µA Error from 10 µA AGND TRACK HOLD 03260-0-028 I6m1 p edance Ω L6e1 aµkVa =g e0 .C1u LrSrBe nt L6e10a kµaVg =e 1C uLSrrBe nt Figure 30. Internal ADC Structure 610 610 µV = 1 LSB 6.1 mV = 10 LSB Note that whenever a new input channel is selected, a residual charge from the 32 pF sampling capacitor places a transient on Although Figure 31 shows the op amp operating at a gain of 1, the newly selected input. The signal source must be capable of one can, of course, configure it for any gain needed. Also, one recovering from this transient before the sampling switches go can just as easily use an instrumentation amplifier in its place to into hold mode. Delays can be inserted in software (between condition differential signals. Use an amplifier that is capable of channel selection and conversion request) to account for input delivering the signal (0 V to V ) with minimal saturation. REF stage settling, but a hardware solution alleviates this burden Some single-supply rail-to-rail op amps that are useful for this from the software design task and ultimately results in a cleaner purpose are described in Table 12. Check Analog Devices website system implementation. One hardware solution is to choose a www.analog.com for details on these and other op amps and very fast settling op amp to drive each analog input. Such an op instrumentation amps. amp would need to fully settle from a small signal transient in less than 300 ns in order to guarantee adequate settling under all software configurations. A better solution, recommended for use with any amplifier, is shown in Figure 31. Though at first glance the circuit in Figure 31 may look like a simple antialias- ing filter, it actually serves no such purpose since its corner frequency is well above the Nyquist frequency, even at a 200 Rev. B | Page 35 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Table 12. Some Single-Supply Op Amps If an external voltage reference is preferred, it should be Op Amp Model Characteristics connected to the C pin as shown in Figure 33. Bit 6 of the REF OP281/OP481 Micropower ADCCON1 SFR must be set to 1 to switch in the external OP191/OP291/OP491 I/O Good up to V , Low Cost DD reference voltage. OP196/OP296/OP496 I/O to V , Micropower, Low Cost DD OP183/OP283 High Gain-Bandwidth Product To ensure accurate ADC operation, the voltage applied to CREF OP162/OP262/OP462 High GBP, Micro Package must be between 1 V and AVDD. In situations where analog AD820/AD822/AD824 FET Input, Low Cost input signals are proportional to the power supply (such as in AD823 FET Input, High GBP some strain gage applications), it may be desirable to connect the C pin directly to AV . Operation of the ADC or DACs REF DD with a reference voltage below 1 V, however, may incur loss of Keep in mind that the ADC transfer function is 0 V to V , and REF accuracy, eventually resulting in missing codes or non- that any signal range lost to amplifier saturation near ground monotonicity. For that reason, do not use a reference voltage impacts dynamic range. Though the op amps in Table 12 are lower than 1 V. capable of delivering output signals that very closely approach ground, no amplifier can deliver signals all the way to ground ADuC841/ADuC842/ADuC843 when powered by a single supply. Therefore, if a negative supply VDD is available, you might consider using it to power the front end amplifiers. If you do, however, be sure to include the Schottky EXTERNAL 51Ω 2.5V VOLTAGE BAND GAP diodes shown in Figure 31 (or at least the lower of the two diodes) REFERENCE REFERENCE to protect the analog input from undervoltage conditions. To BUFFER summarize this section, use the circuit in Figure 31 to drive the 0 = INTERNAL analog input pins of the parts. VREF = NC 1 = EXTERNAL Voltage Reference Connections ADCCON1.6 The on-chip 2.5 V band gap voltage reference can be used as the roeff ethreen vcoel staoguer cree ffeorre tnhcee A, yDoCu amnuds Dt dAeCcso.u Tpol ee nthsuer Ce RthEFe paicnc utor acy 0.1CµRFEF 03260-0-031 ground with a 0.47 µF capacitor, as shown in Figure 32. Note Figure 33. Using an External Voltage Reference that this is different from the ADuC812/ADuC831/ADuC832. Configuring the ADC ADuC841/ADuC842/ADuC843 The parts’ successive approximation ADC is driven by a divided 51Ω 2.5V down version of the master clock. To ensure adequate ADC BAND GAP REFERENCE operation, this ADC clock must be between 400 kHz and 8.38 MHz. Frequencies within this range can be achieved easily with master clock frequencies from 400 kHz to well above BUFFER 16 MHz, with the four ADC clock divide ratios to choose from. VREF = NC For example, set the ADC clock divide ratio to 8 (that is, ADCCLK = 16.777216 MHz/8 = 2 MHz) by setting the appropriate bits in CREF ADCCON1 (ADCCON1.5 = 1, ADCCON1.4 = 0). The total BUFFER 0.47µF 03260-0-030 AsAyDDncCCh rccoolonncivkzeasr)tsi. ioFonon,r pt tilmhuese p tihrse e1c s5ee dAleinDcgtCe ed xc aalocmqckpuslies, ,ip twilouinsth 1t i aAm 3De- cC(l1o ,cc l2ko, c3k, oforr 4 Figure 32. Decoupling VREF and CREF acquisition time, total conversion time is 19 ADC clocks (or 9.05 µs for a 2 MHz ADC clock). If the internal voltage reference is to be used as a reference for external circuitry, the C output should be used. However, a REF In continuous conversion mode, a new conversion begins each buffer must be used in this case to ensure that no current is time the previous one finishes. The sample rate is then simply drawn from the C pin itself. The voltage on the C pin is REF REF the inverse of the total conversion time described previously. In that of an internal node within the buffer block, and its voltage the preceding example, the continuous conversion mode sample is critical for ADC and DAC accuracy. The parts power up with rate is 110.3 kHz. their internal voltage reference in the off state. Rev. B | Page 36 of 95

Data Sheet ADuC841/ADuC842/ADuC843 If using the temperature sensor as the ADC input, the ADC 00000AH 1 1 1 1 STOP COMMAND should be configured to use an ADCCLK of MCLK/32 and four REPEAT LAST CHANNEL acquisition clocks. 0 0 1 1 FOR A VALID STOP CONDITION Increasing the conversion time on the temperature monitor 0 0 1 1 CONVERT ADC CH 3 channel improves the accuracy of the reading. To further 1 0 0 0 CONVERT TEMP SENSOR improve the accuracy, an external reference with low tempera- tAuDreC d DriMft Ash Mouoldd ea lso be used. 000000H 00 10 01 10 CCOONNVVEERRTT AADDCC CCHH 25 03260-0-033 The on-chip ADC has been designed to run at a maximum Figure 34. Typical DMA External Memory Preconfiguration conversion speed of 2.38 µs (420 kHz sampling rate). When 4. The DMA is initiated by writing to the ADC SFRs in the converting at this rate, the ADuC841/ADuC842/ADuC843 following sequence: MicroConverter® has 2 µs to read the ADC result and to store the result in memory for further postprocessing; otherwise the a. ADCCON2 is written to enable the DMA mode, that next ADC sample could be lost. In an interrupt driven routine, is, MOV ADCCON2, #40H; DMA mode enabled. the MicroConverter would also have to jump to the ADC interrupt service routine, which also increases the time required b. ADCCON1 is written to configure the conversion to store the ADC results. In applications where the parts cannot time and power-up of the ADC. It can also enable sustain the interrupt rate, an ADC DMA mode is provided. Timer 2 driven conversions or external triggered conversions if required. To enable DMA mode, Bit 6 in ADCCON2 (DMA) must be set, which allows the ADC results to be written directly to a 16 MByte c. ADC conversions are initiated. This is done by external static memory SRAM (mapped into data memory starting single conversions, starting Timer 2, running space) without any interaction from the core of the part. This for Timer 2 conversions, or receiving an external mode allows the part to capture a contiguous sample stream at trigger. full ADC update rates (420 kHz). When the DMA conversions are complete, the ADC interrupt Typical DMA Mode Configuration Example bit, ADCI, is set by hardware, and the external SRAM contains Setting the parts to DMA mode consists of the following steps: the new ADC conversion results as shown in Figure 35. Note that no result is written to the last two memory locations. 1. The ADC must be powered down. This is done by ensuring that MD1 and MD0 are both set to 0 in ADCCON1. When the DMA mode logic is active, it takes the responsibility of storing the ADC results away from both the user and the core 2. The DMA address pointer must be set to the start address logic of the part. As the DMA interface writes the results of the of where the ADC results are to be written. This is done by ADC conversions to external memory, it takes over the external writing to the DMA mode address pointers DMAL, DMAH, memory interface from the core. Thus, any core instructions and DMAP. DMAL must be written to first, followed by that access the external memory while DMA mode is enabled DMAH, and then by DMAP. does not get access to the external memory. The core executes the instructions, and they take the same time to execute, but 3. The external memory must be preconfigured. This consists they cannot access the external memory. of writing the required ADC channel IDs into the top four bits of every second memory location in the external 00000AH 1 1 1 1 STOP COMMAND SRAM, starting at the first address specified by the DMA NO CONVERSION address pointer. Because the ADC DMA mode operates 0 0 1 1 RESULT WRITTEN HERE independently from the ADuC841/ADuC842/ADuC843 CONVERSION RESULT 0 0 1 1 FOR ADC CH 3 core, it is necessary to provide it with a stop command. CONVERSION RESULT This is done by duplicating the last channel ID to be 1 0 0 0 FOR TEMP SENSOR converted followed by 1111 into the next channel selection CONVERSION RESULT 0 1 0 1 FOR ADC CH 5 fsiheoldw. nA i nty Fpiigcaulr ep r3e4c.o nfiguration of external memory is 000000H 0 0 1 0 CFOORN VAEDRCS CIOHN 2 RESULT 03260-0-034 Figure 35. Typical External Memory Configuration Post ADC DMA Operation Rev. B | Page 37 of 95

ADuC841/ADuC842/ADuC843 Data Sheet ADC Offset and Gain Calibration Coefficients The DMA logic operates from the ADC clock and uses pipelin- ing to perform the ADC conversions and to access the external The ADuC841/ADuC842/ADuC843 have two ADC calibration memory at the same time. The time it takes to perform one ADC coefficients, one for offset calibration and one for gain calibra- conversion is called a DMA cycle. The actions performed by the tion. Both the offset and gain calibration coefficients are 14-bit logic during a typical DMA cycle are shown in Figure 36. words, and are each stored in two registers located in the special function register (SFR) area. The offset calibration coefficient is CONVERT CHANNEL READ DURING PREVIOUS DMA CYCLE divided into ADCOFSH (six bits) and ADCOFSL (8 bits), and the gain calibration coefficient is divided into ADCGAINH WRITE ADC RESULT READ CHANNEL ID (6 bits) and ADCGAINL (8 bits). CONVERTED DURING TO BE CONVERTED DURING PREVIOUS DMA CYCLEDMA CYCLE NEXT DMA CYCLE 03260-0-035 Terhreo rosf finse bt ocathli bthraet iAoDn Cco aenffdic tihene ti ncopmutp seignnsaatle. sI nfocrre dacs ionfgf stehte offset coefficient compensates for positive offset, and effectively Figure 36. DMA Cycle pushes the ADC transfer function down. Decreasing the offset Figure 36 shows that during one DMA cycle, the following coefficient compensates for negative offset, and effectively actions are performed by the DMA logic: pushes the ADC transfer function up. The maximum offset that 1. An ADC conversion is performed on the channel whose can be compensated is typically ±5% of VREF, which equates to ID was read during the previous cycle. typically ±125 mV with a 2.5 V reference. 2. The 12-bit result and the channel ID of the conversion Similarly, the gain calibration coefficient compensates for dc performed in the previous cycle is written to the external gain errors in both the ADC and the input signal. Increasing the memory. gain coefficient compensates for a smaller analog input signal range and scales the ADC transfer function up, effectively 3. The ID of the next channel to be converted is read from increasing the slope of the transfer function. Decreasing the external memory. gain coefficient compensates for a larger analog input signal range and scales the ADC transfer function down, effectively For the previous example, the complete flow of events is shown decreasing the slope of the transfer function. The maximum in Figure 36. Because the DMA logic uses pipelining, it takes analog input signal range for which the gain coefficient can three cycles before the first correct result is written out. compensate is 1.025 × V , and the minimum input range is REF Micro Operation during ADC DMA Mode 0.975 × V , which equates to typically ±2.5% of the reference REF During ADC DMA mode, the MicroConverter core is free to voltage. continue code execution, including general housekeeping and CALIBRATING THE ADC communication tasks. However, note that MCU core accesses to Ports 0 and 2 (which of course are being used by the DMA con- Two hardware calibration modes are provided, which can be troller) are gated off during the ADC DMA mode of operation. easily initiated by user software. The ADCCON3 SFR is used to This means that even though the instruction that accesses the calibrate the ADC. Bit 1 (typical) and CS3 to CS0 (ADCCON2) set external Ports 0 or 2 appears to execute, no data is seen at these up the calibration modes. external ports as a result. Note that during DMA to the inter- Device calibration can be initiated to compensate for significant nally contained XRAM, Ports 0 and 2 are available for use. changes in operating condition frequency, analog input range, The only case in which the MCU can access XRAM during reference voltage, and supply voltages. In this calibration mode, DMA is when the internal XRAM is enabled and the section of offset calibration uses internal AGND selected via ADCCON2 RAM to which the DMA ADC results are being written to lies register Bits CS3 to CS0 (1011), and gain calibration uses inter- in an external XRAM. Then the MCU can access the internal nal VREF selected by Bits CS3 to CS0 (1100). Offset calibration XRAM only. This is also the case for use of the extended stack should be executed first, followed by gain calibration. System pointer. calibration can be initiated to compensate for both internal and external system errors. To perform system calibration by using The MicroConverter core can be configured with an interrupt an external reference, tie the system ground and reference to to be triggered by the DMA controller when it has finished any two of the six selectable inputs. Enable external reference filling the requested block of RAM with ADC results, allowing mode (ADCCON1.6). Select the channel connected to AGND the service routine for this interrupt to postprocess data without via Bits CS3 to CS0 and perform system offset calibration. any real-time timing constraints. Select the channel connected to V via Bits CS3 to CS0 and REF perform system gain calibration. Rev. B | Page 38 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Initiating the Calibration in Code NONVOLATILE FLASH/EE MEMORY When calibrating the ADC using ADCCON1, the ADC must The ADuC841/ADuC842/ADuC843 incorporate Flash/EE be set up into the configuration in which it is used. The memory technology on-chip to provide the user with nonvola- ADCCON3 register can then be used to set up the device and to tile, in-circuit, reprogrammable code and data memory space. calibrate the ADC offset and gain. Flash/EE memory is a relatively recent type of nonvolatile memory technology, which is based on a single transistor cell MOV ADCCON1,#08CH ; ADC on; ADCCLK set ;to divide by 32,4 architecture. Flash/EE memory combines the flexible in-circuit ;acquisition clock reprogrammable features of EEPROM with the space efficient/ density features of EPROM as shown in Figure 37. To calibrate device offset: Because Flash/EE technology is based on a single transistor cell MOV ADCCON2,#0BH ;select internal AGND architecture, a flash memory array, such as EPROM, can be MOV ADCCON3,#25H ;select offset calibration, ;31 averages per bit, implemented to achieve the space efficiencies or memory densities ;offset calibration required by a given design. Like EEPROM, flash memory can be programmed in-system at a byte level; it must first be erased, To calibrate device gain: the erase being performed in page blocks. Thus, flash memory MOV ADCCON2,#0CH ;select internal VREF is often and more correctly referred to as Flash/EE memory. MOV ADCCON3,#27H ;select offset calibration, ;31 averages per bit, EPROM EEPROM ;offset calibration TECHNOLOGY TECHNOLOGY To calibrate system offset, connect system AGND to an ADC SPACE EFFICIENT/ IN-CIRCUIT channel input (0). DENSITY REPROGRAMMABLE MMOOVV AADDCCCCOONN23,,##0205HH ;;sseelleecctt eoxftfesrenta lc aAlGiNbDr ation, FLTAESCHH/ENEOMLEOMGOYRY 03260-0-036 ;31 averages per bit Figure 37. Flash/EE Memory Development Overall, Flash/EE memory represents a step closer to the ideal To calibrate system gain, connect system V to an ADC REF memory device that includes nonvolatility, in-circuit program- channel input (1). mability, high density, and low cost. Incorporated in the parts, MOV ADCCON2,#01H ;select external VREF Flash/EE memory technology allows the user to update program MOV ADCCON3,#27H ;select offset calibration, ;31 averages per bit, code space in-circuit, without the need to replace one-time ;offset calibration programmable (OTP) devices at remote operating nodes. Flash/EE Memory and the ADuC841/ADuC842/ADuC843 The calibration cycle time T is calculated by the following CAL The parts provide two arrays of Flash/EE memory for user equation: T =14×ADCCLK×NUMAV×(16+T ) applications. Up to 62 kBytes of Flash/EE program space are CAL ACQ provided on-chip to facilitate code execution without any For an ADCCLK/FCORE divide ratio of 32, T = 4 ADCCLK, external discrete ROM device requirements. The program ACQ and NUMAV = 15, the calibration cycle time is memory can be programmed in-circuit by using the serial download mode provided, by using conventional third party T =14×(1/524288)×15×(16+4) CAL memory programmers, or via a user defined protocol that can TCAL =8ms configure it as data if required. In a calibration cycle, the ADC busy flag (Bit 7), instead of Note that the following sections use the 62 kByte program space framing an individual ADC conversion as in normal mode, as an example when referring to ULOAD mode. For the other goes high at the start of calibration and returns to zero only at memory models (32 kByte and 8 kByte), the ULOAD space the end of the calibration cycle. It can therefore be monitored in moves to the top 8 kBytes of the on-chip program memory, that is, code to indicate when the calibration cycle is completed. The for 32 kBytes, the ULOAD space is from 24 kBytes to 32 kBytes, following code can be used to monitor the BUSY signal during the kernel still resides in a protected space from 60 kBytes to a calibration cycle: 62 kBytes. There is no ULOAD space present on the 8 kBtye part. WAIT: MOV A, ADCCON3 ;move ADCCON3 to A JB ACC.7, WAIT ;If Bit 7 is set jump to WAIT else continue Rev. B | Page 39 of 95

ADuC841/ADuC842/ADuC843 Data Sheet A 4 kByte Flash/EE data memory space is also provided on- 300 chip. This may be used as a general-purpose nonvolatile scratchpad area. User access to this area is via a group of six 250 SFRs. This space can be programmed at a byte level, although it must first be erased in 4-byte pages. ears)200 ADI SPECIFICATION Flash/EE Memory Reliability (YON150 10A0T Y TEJA =R S5 5M°ICN. TI The Flash/EE program and data memory arrays on the parts are N E T fully qualified for two key Flash/EE memory characteristics: RE100 Flash/EE memory cycling endurance and Flash/EE memory data retention. 50 Endurance quantifies the ability of the Flash/EE memory to be 040 50 60 70 80 90 100 110 03260-0-037 cycled through many program, read, and erase cycles. In real TJ JUNCTION TEMPERATURE (°C) terms, a single endurance cycle is composed of four independ- Figure 38. Flash/EE Memory Data Retention ent, sequential events, defined as 1. Initial page erase sequence. Using the Flash/EE Program Memory The 62 kByte Flash/EE program memory array is mapped into 2. Read/verify sequence a single Flash/EE. the lower 62 kBytes of the 64 kByte program space addressable 3. Byte program sequence memory. by the parts, and is used to hold user code in typical applica- tions. The program Flash/EE memory array can be 4. Second read/verify sequence endurance cycle. programmed in three ways: In reliability qualification, every byte in both the program and Serial Downloading (In-Circuit Programming) data Flash/EE memory is cycled from 00H to FFH until a first The parts facilitate code download via the standard UART serial fail is recorded, signifying the endurance limit of the on-chip port. The parts enter serial download mode after a reset or Flash/EE memory. power cycle if the PSEN pin is pulled low through an external 1 kΩ resistor. Once in serial download mode, the user can As indicated in the Specifications table, the parts’ Flash/EE download code to the full 62 kBytes of Flash/EE program memory endurance qualification has been carried out in memory while the device is in-circuit in its target application accordance with JEDEC Retention Lifetime Specification A117 over the industrial temperature range of –40°C to +25°C and hardware. +25°C to +85°C. The results allow the specification of a mini- A PC serial download executable is provided as part of the mum endurance figure over supply and over temperature of ADuC841/ADuC842 QuickStart development system. The 100,000 cycles, with an endurance figure of 700,000 cycles being serial download protocol is detailed in MicroConverter typical of operation at 25°C. Application Note uC004. Retention quantifies the ability of the Flash/EE memory to Parallel Programming retain its programmed data over time. Again, the parts have Parallel programming mode is fully compatible with conven- been qualified in accordance with the formal JEDEC Retention tional third party flash or EEPROM device programmers. In Lifetime Specification (A117) at a specific junction temperature this mode, Ports P0, P1, and P2 operate as the external data and (T = 55°C). As part of this qualification procedure, the J address bus interface, ALE operates as the write enable strobe, Flash/EE memory is cycled to its specified endurance limit, and Port P3 is used as a general configuration port, which described previously, before data retention is characterized. configures the device for various program and erase operations This means that the Flash/EE memory is guaranteed to retain during parallel programming. The high voltage (12 V) supply its data for its fully specified retention lifetime every time the required for flash programming is generated using on-chip Flash/EE memory is reprogrammed. Also note that retention charge pumps to supply the high voltage program lines. The lifetime, based on an activation energy of 0.6 eV, derates with T J complete parallel programming specification is available on the as shown in Figure 38. MicroConverter home page at www.analog.com/microconverter. Rev. B | Page 40 of 95

Data Sheet ADuC841/ADuC842/ADuC843 User Download Mode (ULOAD) EMBEDDED DOWNLOAD/DEBUG KERNEL PERMANENTLY EMBEDDED FIRMWARE ALLOWS Figure 39 shows that it is possible to use the 62 kBytes of CODE TO BE DOWNLOADED TO ANY OF THE FFFFH 32 kBYTES OF ON-CHIP PROGRAM MEMORY. 2kBYTE Flash/EE program memory available to the user as a single THE KERNEL PROGRAM APPEARS AS 'NOP' F800H INSTRUCTIONS TO USER CODE F7FFH block of memory. In this mode, all of the Flash/EE memory is NOP'S read-only to user code. USER BOOTLOADER SPACE 8000H THE USER BOOTLOADER SPACE CAN BE PROGRAMMED IN 7FFFH However, the Flash/EE program memory can also be written to DOWNLOAD/DEBUG MODE VIA THE 8kBYTE KERNEL BUT IS READ ONLY WHEN 6000H during runtime simply by entering ULOAD mode. In ULOAD 32 kBYTES EXECUTING USER CODE OF USER mode, the lower 56 kBytes of program memory can be erased CODE USER DOWNLOADER SPACE and reprogrammed by user software as shown in Figure 39. MEMORY EITHER THE DOWNLOAD/DEBUG 5FFFH KERNEL OR USER CODE (IN 26kBYTE UanLyO uAseDr dmeofidnee dca dno bwen ulosaedd tpor outpogcroald. Be yy ocuonr fciogduer iinng t thhee f SiePldI via ULOAD MOTHDIES) SCPAANC PEROGRAM 0000H �03260-0-039 port on the part as a slave, it is possible to completely reprogram the 56 kBytes of Flash/EE program memory in only 5 seconds Figure 40. Flash/EE Program Memory Map in ULOAD Mode (refer to Application Note uC007). (32 kByte Part) Alternatively, ULOAD mode can be used to save data to the Flash/EE Program Memory Security 56 kBytes of Flash/EE memory. This can be extremely useful in data logging applications where the part can provide up to The ADuC841/ADuC842/ADuC843 facilitate three modes of 60 kBytes of NV data memory on chip (4 kBytes of dedicated Flash/EE program memory security. These modes can be Flash/EE data memory also exist). independently activated, restricting access to the internal code space. These security modes can be enabled as part of serial The upper 6 kBytes of the 62 kBytes of Flash/EE program download protocol as described in Application Note uC004 or memory are programmable only via serial download or parallel via parallel programming. The security modes available on the programming. This means that this space appears as read-only parts are as follows: to user code. Therefore, it cannot be accidentally erased or Lock Mode reprogrammed by erroneous code execution, which makes it This mode locks the code memory, disabling parallel program- very suitable to use the 6 kBytes as a bootloader. ming of the program memory. However, reading the memory in A bootload enable option exists in the serial downloader to parallel mode and reading the memory via a MOVC command “always run from E000H after reset.” If using a bootloader, this from external memory is still allowed. This mode is deactivated option is recommended to ensure that the bootloader always by initiating a code-erase command in serial download or executes correct code after reset. Programming the Flash/EE parallel programming modes. program memory via ULOAD mode is described in more detail Secure Mode in the description of ECON and in Application Note uC007. This mode locks code in memory, disabling parallel program- EMBEDDED DOWNLOAD/DEBUG KERNEL ming (program and verify/read commands) as well as disabling PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE TO BE DOWNLOADED TO ANY OF THE FFFFH the execution of a MOVC instruction from external memory, 62 kBYTES OF ON-CHIP PROGRAM MEMORY. 2kBYTE THE KERNEL PROGRAM APPEARS AS 'NOP' F800H which is attempting to read the op codes from internal memory. INSTRUCTIONS TO USER CODE F7FFH Read/write of internal data Flash/EE from external memory is USER BOOTLOADER SPACE 6kBYTE also disabled. This mode is deactivated by initiating a code-erase E000H THE USER BOOTLOADER SPACE CAN BE PROGRAMMED IN command in serial download or parallel programming modes. DOWNLOAD/DEBUG MODE VIA THE KERNEL BUT IS READ ONLY WHEN Serial Safe Mode 62 kBYTES EXECUTING USER CODE OF USER CODE dFFFH This mode disables serial download capability on the device. If USER DOWNLOADER SPACE 56kBYTE MEMORY EITHER THE DOWNLOAD/DEBUG 0000H serial safe mode is activated and an attempt is made to reset the KERNEL OR USER CODE (IN ULOAD MOTHDIES) SCPAANC PEROGRAM �03260-0-038 pasasretr itnetdo wseitrhia Pl SdEoNwn lolowa,d t hme opdaer,t tihnatte risp,r RetEs StEhTe saesrsiearl tdedow anndlo dade- reset as a normal reset only. It therefore cannot enter serial Figure 39. Flash/EE Program Memory Map in ULOAD Mode download mode but can only execute as a normal reset (62 kByte Part) sequence. Serial safe mode can be disabled only by initiating a code-erase command in parallel programming mode. Rev. B | Page 41 of 95

ADuC841/ADuC842/ADuC843 Data Sheet USING FLASH/EE DATA MEMORY The 4 kBytes of Flash/EE data memory are configured as 1024 BYTE 1 BYTE 2 BYTE 3 BYTE 4 3FFH (0FFCH) (0FFDH) (0FFEH) (0FFFH) pages, each of 4 bytes. As with the other ADuC841/ADuC842/ 3FEH BYTE 1 BYTE 2 BYTE 3 BYTE 4 ADuC843 peripherals, the interface to this memory space is via (0FF8H) (0FF9H) (0FFAH) (0FFBH) S ad agtrao ruepg iosft erresg (isEtDerAs TmAa1p–p4e)d i sin u tsheed StoF Rh oslpda cthe.e Afo gurro buypt eosf ofof udra ta DRESH/L) DR at each page. The page is addressed via the two registers, EADRH GE AEAD03H (0B0Y0TCEH 1) (B00Y0TDEH 2) (B00Y0TEEH 3) (0B0Y0TFEH 4) and EADRL. Finally, ECON is an 8-bit control register that may PA(02H BYTE 1 BYTE 2 BYTE 3 BYTE 4 be written with one of nine Flash/EE memory access commands (0008H) (0009H) (000AH) (000BH) 01H BYTE 1 BYTE 2 BYTE 3 BYTE 4 to trigger various read, write, erase, and verify functions. A (0004H) (0005H) (0006H) (0007H) block diagram of the SFR interface to the Flash/EE data memory 00H BYTE 1 BYTE 2 BYTE 3 BYTE 4 (0000H) (0001H) (0002H) (0003H) array is shown in Figure 41. R R R R F F F F ECON—Flash/EE Memory Control SFR BYTE 1 S 2 S 3 S 4 S ADDRESSES A A A A Pprrooggrraamm mmienmg oorf ye iitsh deor nFela tshhr/oEuEg hd atthae m Fleamsho/rEyE o mr Felmasohr/y E E ABRREACGKIVEETNSIN EDAT EDAT EDAT EDAT 03260-0-040 control SFR (ECON). This SFR allows the user to read, write, Figure 41. Flash/EE Data Memory Control and Configuration erase, or verify the 4 kBytes of Flash/EE data memory or the 56 kBytes of Flash/EE program memory. Table 13. ECON—Flash/EE Memory Commands Command Description (Normal Mode) ECON VALUE (Power-On Default) Command Description (ULOAD Mode) 01H Results in 4 bytes in the Flash/EE data memory, addressed Not implemented. Use the MOVC instruction. READ by the page address EADRH/L, being read into EDATA1–4. 02H Results in 4 bytes in EDATA1–4 being written to the Results in bytes 0–255 of internal XRAM being written to WRITE Flash/EE data memory at the page address given by the 256 bytes of Flash/EE program memory at the page EADRH/L (0 – EADRH/L < 0400H). address given by EADRH (0 – EADRH < E0H). Note that the 4 bytes in the page being addressed must Note that the 256 bytes in the page being addressed must be pre-erased. be pre-erased. 03H Reserved. Reserved. 04H Verifies that the data in EDATA1–4 is contained in the Not implemented. Use the MOVC and MOVX instructions VERIFY page address given by EADRH/L. A subsequent read of the to verify the write in software. ECON SFR results in 0 being read if the verification is valid, or a nonzero value being read to indicate an invalid verification. 05H Results in erasing the 4-byte page of Flash/EE data Results in the 64 byte page of Flash/EE program memory, ERASE PAGE memory addressed by the page address EADRH/L. addressed by the byte address EADRH/L, being erased. EADRL can equal any of 64 locations within the page. A new page starts whenever EADRL is equal to 00H, 40H, 80H, or C0H. 06H Results in erasing the entire 4 kBytes of Flash/EE data Results in erasing the entire 56 kBytes of ULOAD Flash/EE ERASE ALL memory. program memory. 81H Results in the byte in the Flash/EE data memory, Not implemented. Use the MOVC command. READBYTE addressed by the byte address EADRH/L, being read into EDATA1 (0 – EADRH / L – 0FFFH). 82H Results in the byte in EDATA1 being written into Flash/EE Results in the byte in EDATA1 being written into Flash/EE WRITEBYTE data memory at the byte address EADRH/L program memory at the byte address EADRH/L (0 – EADRH/L – DFFFH). 0FH Leaves the ECON instructions to operate on the Flash/EE Enters normal mode directing subsequent ECON EXULOAD data memory. instructions to operate on the Flash/EE data memory. F0H Enters ULOAD mode, directing subsequent ECON Leaves the ECON instructions to operate on the Flash/EE ULOAD instructions to operate on the Flash/EE program memory. program memory. Rev. B | Page 42 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Example: Programming the Flash/EE Data Memory Flash/EE Memory Timing A user wants to program F3H into the second byte on Page 03H Typical program and erase times for the parts are as follows: of the Flash/EE data memory space while preserving the other Normal Mode (operating on Flash/EE data memory) 3 bytes already in this page. A typical program of the Flash/EE READPAGE (4 bytes) 22 machine cycles data array involves WRITEPAGE (4 bytes) 380 µs VERIFYPAGE (4 bytes) 22 machine cycles 1. Setting EADRH/L with the page address. ERASEPAGE (4 bytes) 2 ms 2. Writing the data to be programmed to the EDATA1–4. ERASEALL (4 kBytes) 2 ms READBYTE (1 byte) 9 machine cycles 3. Writing the ECON SFR with the appropriate command. WRITEBYTE (1 byte) 200 µs Step 1: Set Up the Page Address ULOAD Mode (operating on Flash/EE program memory) Address registers EADRH and EADRL hold the high byte WRITEPAGE (256 bytes) 16.5 ms address and the low byte address of the page to be addressed. ERASEPAGE (64 bytes) 2 ms The assembly language to set up the address may appear as ERASEALL (56 kBytes) 2 ms MOV EADRH,#0 ; Set Page Address Pointer WRITEBYTE (1 byte) 200 µs MOV EADRL,#03H Step 2: Set Up the EDATA Registers Note that a given mode of operation is initiated as soon as the Write the four values to be written into the page into the four command word is written to the ECON SFR. The core micro- SFRs, EDATA1–4. Unfortunately, the user does not know three controller operation on the parts is idled until the requested of them. Thus, the user must read the current page and over- program/read or erase mode is completed. In practice, this write the second byte. means that even though the Flash/EE memory mode of operation is typically initiated with a two machine cycle MOV instruction MOV ECON,#1 ; Read Page into EDATA1-4 (to write to the ECON SFR), the next instruction is not MOV EDATA2,#0F3H ; Overwrite byte 2 executed until the Flash/EE operation is complete. This means Step 3: Program Page that the core cannot respond to interrupt requests until the A byte in the Flash/EE array can be programmed only if it has Flash/EE operation is complete, although the core peripheral previously been erased. To be more specific, a byte can be functions like counter/timers continue to count and time as programmed only if it already holds the value FFH. Because of configured throughout this period. the Flash/EE architecture, this erase must happen at a page level; therefore, a minimum of 4 bytes (1 page) are erased when an erase command is initiated. Once the page is erase, the user can program the 4 bytes in-page and then perform a verification of the data. MOV ECON,#5 ; ERASE Page MOV ECON,#2 ; WRITE Page MOV ECON,#4 ; VERIFY Page MOV A,ECON ; Check if ECON=0 (OK!) JNZ ERROR Although the 4 kBytes of Flash/EE data memory are shipped from the factory pre-erased, that is, byte locations set to FFH, it is nonetheless good programming practice to include an ERASEALL routine as part of any configuration/setup code running on the parts. An ERASEALL command consists of writing 06H to the ECON SFR, which initiates an erase of the 4-kByte Flash/EE array. This command coded in 8051 assembly would appear as MOV ECON,#06H ; Erase all Command ; 2 ms Duration Rev. B | Page 43 of 95

ADuC841/ADuC842/ADuC843 Data Sheet ADuC842/ADuC843 Configuration SFR (CFG842) The CFG842 SFR contains the necessary bits to configure the CFG842 ADuC842/ADuC843 Config SFR internal XRAM, external clock select, PWM output selection, SFR Address AFH DAC buffer, and the extended SP for both the ADuC842 and Power-On Default 00H the ADuC843. By default, it configures the user into 8051 mode, that is, extended SP is disabled and internal XRAM is Bit Addressable No disabled. On the ADuC841, this register is the CFG841 register and is described on the next page. Table 14. CFG842 SFR Bit Designations Bit No. Name Description 7 EXSP Extended SP Enable. When set to 1 by the user, the stack rolls over from SPH/SP = 00FFH to 0100H. When set to 0 by the user, the stack rolls over from SP = FFH to SP = 00H. 6 PWPO PWM Pin Out Selection. Set to 1 by the user to select P3.4 and P3.3 as the PWM output pins. Set to 0 by the user to select P2.6 and P2.7 as the PWM output pins. 5 DBUF DAC Output Buffer. Set to 1 by the user to bypass the DAC output buffer. Set to 0 by the user to enable the DAC output buffer. 4 EXTCLK Set by the user to 1 to select an external clock input on P3.4. Set by the user to 0 to use the internal PLL clock. 3 RSVD Reserved. This bit should always contain 0. 2 RSVD Reserved. This bit should always contain 0. 1 MSPI Set to 1 by the user to move the SPI functionality of MISO, MOSI, and SCLOCK to P3.3, P3.4, and P3.5, respectively. Set to 0 by the user to leave the SPI functionality as usual on MISO, MOSI, and SCLOCK pins. 0 XRAMEN XRAM Enable Bit. When set to 1 by the user, the internal XRAM is mapped into the lower 2 kBytes of the external address space. When set to 0 by the user, the internal XRAM is not accessible, and the external data memory is mapped into the lower 2 kBytes of external data memory. Rev. B | Page 44 of 95

Data Sheet ADuC841/ADuC842/ADuC843 CFG841 ADuC841 Config SFR SFR Address AFH Power-On Default 10H1 Bit Addressable No Table 15. CFG841 SFR Bit Designations Bit No. Name Description 7 EXSP Extended SP Enable. When set to 1 by the user, the stack rolls over from SPH/SP = 00FFH to 0100H. When set to 0 by the user, the stack rolls over from SP = FFH to SP = 00H. 6 PWPO PWM Pin Out Selection. Set to 1 by the user to select P3.4 and P3.3 as the PWM output pins. Set to 0 by the user to select P2.6 and P2.7 as the PWM output pins. 5 DBUF DAC Output Buffer. Set to 1 by the user to bypass the DAC output buffer. Set to 0 by the user to enable the DAC output buffer. 4 EPM2 Flash/EE Controller and PWM Clock Frequency Configuration Bits. Frequency should be configured such that F /Divide Factor = 32 kHz + 50%. OSC 3 EPM1 EPM2 EPM1 EPM0 Divide Factor 2 EPM0 0 0 0 32 0 0 1 64 0 1 0 128 0 1 1 256 1 0 0 512 1 0 1 1024 1 MSPI Set to 1 by the user to move the SPI functionality of MISO, MOSI, and SCLOCK to P3.3, P3.4, and P3.5, respectively. Set to 0 by the user to leave the SPI functionality as usual on MISO, MOSI, and SCLOCK pins. 0 XRAMEN XRAM Enable Bit. When set to 1 by the user, the internal XRAM is mapped into the lower two kBytes of the external address space. When set to 0 by the user, the internal XRAM is not accessible, and the external data memory is mapped into the lower two kBytes of external data memory. 1 Note that the Flash/EE controller bits EPM2, EPM1, EPM0 are set to their correct values depending on the crystal frequency at power-up. The user should not modify these bits so all instructions to the CFG841 register should use the ORL, XRL, or ANL instructions. Value of 10H is for 11.0592 MHz crystal. Rev. B | Page 45 of 95

ADuC841/ADuC842/ADuC843 Data Sheet USER INTERFACE TO ON-CHIP PERIPHERALS Both DACs share a control register, DACCON, and four data registers, DAC1H/L, DAC0/L. Note that in 12-bit asynchronous This section gives a brief overview of the various peripherals mode, the DAC voltage output is updated as soon as the DACL also available on-chip. A summary of the SFRs used to control data SFR has been written; therefore, the DAC data registers and configure these peripherals is also given. should be updated as DACH first, followed by DACL. Note that DAC for correct DAC operation on the 0 V to V range, the ADC REF The ADuC841/ADuC842 incorporate two 12-bit voltage output must be switched on. This results in the DAC using the correct DACs on-chip. Each has a rail-to-rail voltage output buffer reference value. capable of driving 10 kΩ/100 pF. Each has two selectable ranges, DACCON DAC Control Register 0 V to V (the internal band gap 2.5 V reference) and 0 V to REF AV . Each can operate in 12-bit or 8-bit mode. SFR Address FDH DD Power-On Default 04H Bit Addressable No Table 16. DACCON SFR Bit Designations Bit No. Name Description 7 MODE The DAC MODE bit sets the overriding operating mode for both DACs. Set to 1 by the user to select 8-bit mode (write 8 bits to DACxL SFR). Set to 0 by the user to select 12-bit mode. 6 RNG1 DAC1 Range Select Bit. Set to 1 by the user to select the range for DAC1 as 0 V to V . DD Set to 0 by the user to select the range for DAC1 as 0 V to V . REF 5 RNG0 DAC0 Range Select Bit. Set to 1 by the user to select the range for DAC0 as 0 V to V . DD Set to 0 by the user to select the range for DAC0 as 0 V to V . REF 4 CLR1 DAC1 Clear Bit. Set to 1 by the user to leave the output of DAC1 at its normal level. Set to 0 by the user to force the output of DAC1 to 0 V. 3 CLR0 DAC0 Clear Bit. Set to 1 by the user to leave the output of DAC0 at its normal level. Set to 0 by the user to force the output of DAC0 to 0 V. 2 SYNC DAC0/1 Update Synchronization Bit. When set to 1, the DAC outputs update as soon as DACxL SFRs are written. The user can simultaneously update both DACs by first updating the DACxL/H SFRs while SYNC is 0. Both DACs then update simultaneously when the SYNC bit is set to 1. 1 PD1 DAC1 Power-Down Bit. Set to 1 by the user to power on DAC1. Set to 0 by the user to power off DAC1. 0 PD0 DAC0 Power-Down Bit. Set to 1 by the user to power on DAC0. Set to 0 by the user to power off DAC0. DACxH/L DAC Data Registers Function DAC data registers, written by the user to update the DAC output. SFR Address DAC0L (DAC0 Data Low Byte) -> F9H; DAC1L (DAC1 Data Low Byte) -> FBH DACH (DAC0 Data High Byte) -> FAH; DAC1H (DAC1 Data High Byte) -> FCH Power-On Default 00H All Four Registers. Bit Addressable No All Four Registers. The 12-bit DAC data should be written into DACxH/L right-justified such that DACxL contains the lower 8 bits, and the lower nibble of DACxH contains the upper 4 bits. Rev. B | Page 46 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Using the DAC The on-chip DAC architecture consists of a resistor string DAC VDD followed by an output buffer amplifier, the functional equivalent VDD–50mV of which is illustrated in Figure 42. Features of this architecture VDD–100mV include inherent guaranteed monotonicity and excellent differential linearity. ADuC841/ADuC842 AVDD VREF R OUTPUT 100mV BUFFER RR DAC0 500mmVV 000H FFFH 03260-0-042 HIGH Z Figure 43. Endpoint Nonlinearities Due to Amplifier Saturation DISABLE (FROM MCU) R 5 R 03260-0-041 E (V) 4 DAC LOADED WITH 0FFFH Figure 42. Resistor String DAC Functional Equivalent AG 3 T L As shown in Figure 42, the reference source for each DAC is O V user selectable in software. It can be either AVDD or VREF. In PUT 2 T 0 V-to-AVDD mode, the DAC output transfer function spans OU from 0 V to the voltage at the AV pin. In 0 V-to-V mode, DD REF 1 the DAC output transfer function spans from 0 V to the internal DAC LOADED WITH 0000H V or, if an external reference is applied, the voltage at the C pouiRntE.pF Tuth set aDgAe Cim opultepmute nbtuaftfieorn a. mThpilisf imere afenast uthreast ua ntrlouaed readil,- teoa-crhaR EiFl 00 SOU5RCE/SINK CURRENT1 0(mA) 1503260-0-043 output is capable of swinging to within less than 100 mV of Figure 44. Source and Sink Current Capability with VREF = VDD = 5 V both AVDD and ground. Moreover, the DAC’s linearity specifica- tion (when driving a 10 kΩ resistive load to ground) is guaranteed 4 through the full transfer function except Codes 0 to 100, and, in 0 V-to-AVDD mode only, Codes 3995 to 4095. Linearity degrada- DAC LOADED WITH 0FFFH tion near ground and V is caused by saturation of the output DD amplifier, and a general representation of its effects (neglecting V) E ( 3 offset and gain error) is illustrated in Figure 43. The dotted line G A T in Figure 43 indicates the ideal transfer function, and the solid L O V line represents what the transfer function might look like with T U endpoint nonlinearities due to saturation of the output amplifier. UTP 1 Note that Figure 43 represents a transfer function in 0 V-to-V O DD mode only. In 0 V-to-V mode (with V < V ), the lower REF REF DD DAC LOADED WITH 0000H nonlinearity would be similar, but the upper portion of the t(rVaRnEsF fienr tfhuinsc ctaiosen, wnootu VldD fDo)l,l sohwo wthien gid neoal s liignnes r oigf hetn tdop tohien te nd 00 SOU5RCE/SINK CURRENT1 0(mA) 15 03260-0-044 linearity errors. Figure 45. Source and Sink Current Capability with VREF = VDD = 3 V Rev. B | Page 47 of 95

ADuC841/ADuC842/ADuC843 Data Sheet The endpoint nonlinearities illustrated in Figure 43 become To drive significant loads with the DAC outputs, external worse as a function of output loading. Most of the part’s buffering may be required (even with the internal buffer specifications assume a 10 kΩ resistive load to ground at the enabled), as illustrated in Figure 46. Table 12 lists some DAC output. As the output is forced to source or sink more recommended op amps. current, the nonlinear regions at the top or bottom (respectively) of Figure 43 become larger. Larger current demands can sig- nificantly limit output voltage swing. Figure 44 and Figure 45 DAC0 illustrate this behavior. Note that the upper trace in each of ADuC841/ these figures is valid only for an output range selection of ADuC842 0 V-to-AV . In 0 V-to-V mode, DAC loading does not cause DD REF hbeiglohw-s itdhee vuoplptaegre t rdarcoep isn a tsh leo ncog rarse stphoe nrdefienrge nficgeu vreo.l tFaogre erxeammapinles, DAC1 03260-0-045 if AV = 3 V and V = 2.5 V, the high-side voltage is not be DD REF Figure 46. Buffering the DAC Outputs affected by loads less than 5 mA. But somewhere around 7 mA, the upper curve in Figure 45 drops below 2.5 V (V ), indicating The DAC output buffer also features a high impedance disable REF that at these higher currents the output is not capable of function. In the chip’s default power-on state, both DACs are reaching V . disabled, and their outputs are in a high impedance state (or REF three-state) where they remain inactive until enabled in To reduce the effects of the saturation of the output amplifier at software. This means that if a zero output is desired during values close to ground and to give reduced offset and gain errors, power-up or power-down transient conditions, then a pull- the internal buffer can be bypassed. This is done by setting the down resistor must be added to each DAC output. Assuming DBUF bit in the CFG841/CFG842 register. This allows a full this resistor is in place, the DAC outputs remain at ground rail-to-rail output from the DAC, which should then be buffered potential whenever the DAC is disabled. externally using a dual-supply op amp in order to get a rail-to- rail output. This external buffer should be located as close as physically possible to the DAC output pin on the PCB. Note that the unbuffered mode works only in the 0 V to V range. REF Rev. B | Page 48 of 95

Data Sheet ADuC841/ADuC842/ADuC843 ON-CHIP PLL The ADuC842 and ADuC843 are intended for use with a At 5 V the core clock can be set to a maximum of 16.78 MHz, 32.768 kHz watch crystal. A PLL locks onto a multiple (512) of while at 3 V the maximum core clock setting is 8.38 MHz. The this to provide a stable 16.78 MHz clock for the system. The CD bits should not be set to 0 on a 3 V part. ADuC841 operates directly from an external crystal. The core Note that on the ADuC841, changing the CD bits in PLLCON can operate at this frequency or at binary submultiples of it to causes the core speed to change. The core speed is crystal freq/ allow power saving in cases where maximum core performance 2CD. The other bits in PLLCON are reserved in the case of the is not required. The default core clock is the PLL clock divided ADuC841 and should be written with 0. by 8 or 2.097152 MHz. The ADC clocks are also derived from the PLL clock, with the modulator rate being the same as the PLLCON PLL Control Register crystal oscillator frequency. The preceding choice of frequencies SFR Address D7H ensures that the modulators and the core are synchronous, regardless of the core clock rate. The PLL control register is Power-On Default 53H PLLCON. Bit Addressable No Table 17. PLLCON SFR Bit Designations Bit No. Name Description 7 OSC_PD Oscillator Power-Down Bit. Set by the user to halt the 32 kHz oscillator in power-down mode. Cleared by the user to enable the 32 kHz oscillator in power-down mode. This feature allows the TIC to continue counting even in power-down mode. 6 LOCK PLL Lock Bit. This is a read-only bit. Set automatically at power-on to indicate that the PLL loop is correctly tracking the crystal clock. If the external crystal subsequently becomes disconnected, the PLL rails. Cleared automatically at power-on to indicate that the PLL is not correctly tracking the crystal clock. This may be due to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output can be 16.78 MHz ±20%. 5 ---- Reserved. Should be written with 0. 4 ---- Reserved. Should be written with 0. 3 FINT Fast Interrupt Response Bit. Set by the user enabling the response to any interrupt to be executed at the fastest core clock frequency, regardless of the configuration of the CD2–0 bits (see below). Once user code has returned from an interrupt, the core resumes code execution at the core clock selected by the CD2–0 bits. Cleared by the user to disable the fast interrupt response feature. 2 CD2 CPU (Core Clock) Divider Bits. 1 CD1 This number determines the frequency at which the microcontroller core operates. 0 CD0 CD2 CD1 CD0 Core Clock Frequency (MHz) 0 0 0 16.777216 0 0 1 8.388608 0 1 0 4.194304 0 1 1 2.097152 (Default Core Clock Frequency) 1 0 0 1.048576 1 0 1 0.524288 1 1 0 0.262144 1 1 1 0.131072 Rev. B | Page 49 of 95

ADuC841/ADuC842/ADuC843 Data Sheet PULSE-WIDTH MODULATOR (PWM) The PWM on the ADuC841/ADuC842/ADuC843 is a highly PWMCON, as described in the following sections, controls the flexible PWM offering programmable resolution and an input different modes of operation of the PWM as well as the PWM clock, and can be configured for any one of six different modes clock frequency. of operation. Two of these modes allow the PWM to be config- PWM0H/L and PWM1H/L are the data registers that deter- ured as a Σ-Δ DAC with up to 16 bits of resolution. A block mine the duty cycles of the PWM outputs. The output pins that diagram of the PWM is shown in Figure 47. Note the PWM the PWM uses are determined by the CFG841/CFG842 register, clock’s sources are different for the ADuC841, and are given in and can be either P2.6 and P2.7 or P3.4 and P3.3. In this section Table 18. of the data sheet, it is assumed that P2.6 and P2.7 are selected as fVCO the PWM outputs. TO/EXTERNAL PWM CLOCK CLOCK PROGRAMMABLE fXTAL/15 SELECT DIVIDER To use the PWM user software, first write to PWMCON to fXTAL select the PWM mode of operation and the PWM input clock. Writing to PWMCON also resets the PWM counter. In any of 16-BIT PWM COUNTER the 16-bit modes of operation (Modes 1, 3, 4, 6), user software should write to the PWM0L or PWM1L SFRs first. This value is written to a hidden SFR. Writing to the PWM0H or PWM1H P2.6 COMPARE SFRs updates both the PWMxH and the PWMxL SFRs but does P2.7 not change the outputs until the end of the PWM cycle in MODE PWM0H/L PWM1H/L 03260-0-046 pursoedgr iens st.h Te hnee xvta lPuWes Mw rcitytcelne .t o these 16-bit registers are then Figure 47. PWM Block Diagram PWMCON PWM Control SFR The PWM uses five SFRs: the control SFR (PWMCON) and SFR Address AEH four data SFRs (PWM0H, PWM0L, PWM1H, and PWM1L). Power-On Default 00H Bit Addressable No Table 18. PWMCON SFR Bit Designations Bit No. Name Description 7 SNGL Turns off PMW output at P2.6 or P3.4, leaving the port pin free for digital I/O. 6 MD2 PWM Mode Bits. 5 MD1 The MD2/1/0 bits choose the PWM mode as follows: 4 MD0 MD2 MD1 MD0 Mode 0 0 0 Mode 0: PWM Disabled 0 0 1 Mode 1: Single variable resolution PWM on P2.7 or P3.3 0 1 0 Mode 2: Twin 8-bit PWM 0 1 1 Mode 3: Twin 16-bit PWM 1 0 0 Mode 4: Dual NRZ 16-bit ∑-∆ DAC 1 0 1 Mode 5: Dual 8-bit PWM 1 1 0 Mode 6: Dual RZ 16-bit ∑-∆ DAC 1 1 1 Reserved 3 CDIV1 PWM Clock Divider. 2 CDIV0 Scale the clock source for the PWM counter as follows: CDIV1 CDIV0 Description 0 0 PWM Counter = Selected Clock/1 0 1 PWM Counter = Selected Clock/4 1 0 PWM Counter = Selected Clock/16 1 1 PWM Counter = Selected Clock/64 1 CSEL1 PWM Clock Divider. 0 CSEL0 Select the clock source for the PWM as follows: CSEL1 CSEL0 Description 0 0 PWM Clock = f /15, ADuC841 = f /DIVIDE FACTOR /15 (see the CFG841 register) XTAL OCS 0 1 PWM Clock = f , ADuC841 = f /DIVIDE FACTOR (see the CFG841 register) XTAL OCS 1 0 PWM Clock = External input at P3.4/T0 1 1 PWM Clock = f = 16.777216 MHz, ADuC841 = f VCO OSC Rev. B | Page 50 of 95

Data Sheet ADuC841/ADuC842/ADuC843 PWM Modes of Operation Mode 0: PWM Disabled PWM1L PWM COUNTER The PWM is disabled allowing P2.6 and P2.7 to be used as PWM0H normal. PWM0L Mode 1: Single Variable Resolution PWM PWM1H In Mode 1, both the pulse length and the cycle time (period) are 0 programmable in user code, allowing the resolution of the PWM to be variable. P2.6 PPWWMM11HH//LL sreedtsu tchees ptheeri roeds oolfu tthioen o ouft pthuet wPWaveMfo ormut.p Ruet dbuucti ng P2.7 03260-0-048 Figure 49. PWM Mode 2 increases the maximum output rate of the PWM. For example, setting PWM1H/L to 65536 gives a 16-bit PWM with a maxi- Mode 3: Twin 16-Bit PWM mum output rate of 266 Hz (16.777 MHz/65536). Setting In Mode 3, the PWM counter is fixed to count from 0 to 65536, PWM1H/L to 4096 gives a 12-bit PWM with a maximum giving a fixed 16-bit PWM. Operating from the 16.777 MHz output rate of 4096 Hz (16.777 MHz/4096). core clock results in a PWM output rate of 256 Hz. The duty cycle of the PWM outputs at P2.6 and P2.7 is independently PWM0H/L sets the duty cycle of the PWM output waveform, as programmable. shown in Figure 48. As shown in Figure 50, while the PWM counter is less than PWM1H/L PWM COUNTER PWM0H/L, the output of PWM0 (P2.6) is high. Once the PWM0H/L PWM counter equals PWM0H/L, PWM0 (P2.6) goes low and remains low until the PWM counter rolls over. Similarly, while the PWM counter is less than PWM1H/L, the P02.7 03260-0-047 oPuWtpMut1 oHf/ PLW, PMW1M (P1 2(.P72) .i7s) h giogehs. lOownc aen tdh er ePmWaMins c loouwn utenrt eilq tuhael s PWM counter rolls over. Figure 48. PWM in Mode 1 In this mode, both PWM outputs are synchronized, that is, once Mode 2: Twin 8-Bit PWM the PWM counter rolls over to 0, both PWM0 (P2.6) and In Mode 2, the duty cycle of the PWM outputs and the resolu- PWM1 go high. tion of the PWM outputs are both programmable. The maximum 65536 resolution of the PWM output is 8 bits. PWM COUNTER PWM1L sets the period for both PWM outputs. Typically, this PWM1H/L is set to 255 (FFH) to give an 8-bit PWM, although it is possible to reduce this as necessary. A value of 100 could be loaded here PWM0H/L to give a percentage PWM, that is, the PWM is accurate to 1%. 0 The outputs of the PWM at P2.6 and P2.7 are shown in P2.6 Figure 49. As can be seen, the output of PWM0 (P2.6) goes low w(Ph2e.7n) t ghoee Ps WhiMgh cwohuennte trh eeq PuWalsM P WcoMun0tLer. Teqhuea olsu tPpWutM of1 PHW anMd1 P2.7 03260-0-049 Figure 50. PWM Mode 3 goes low again when the PWM counter equals PWM0H. Setting PWM1H to 0 ensures that both PWM outputs start simultaneously. Rev. B | Page 51 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Mode 4: Dual NRZ 16-Bit ∑-∆ DAC PWM1L PWM COUNTERS Mode 4 provides a high speed PWM output similar to that of a PWM1H ∑-∆ DAC. Typically, this mode is used with the PWM clock PWM0L equal to 16.777216 MHz. In this mode, P2.6 and P2.7 are updated every PWM clock (60 ns in the case of 16 MHz). Over PWM0H any 65536 cycles (16-bit PWM) PWM0 (P2.6) is high for 0 PWM0H/L cycles and low for (65536 – PWM0H/L) cycles. P2.6 Sfoimr (i6la5r5ly3,6 P –W PMW1M (P1H2.7/L) )i sc hyciglehs .f or PWM1H/L cycles and low P2.7 03260-0-051 For example, if PWM1H is set to 4010H (slightly above one Figure 52. PWM Mode 5 quarter of FS), then P2.7 is typically low for three clocks and Mode 6: Dual RZ 16-Bit ∑-∆ DAC high for one clock (each clock is approximately 60 ns). Over Mode 6 provides a high speed PWM output similar to that of a every 65536 clocks, the PWM compensates for the fact that the ∑-∆ DAC. Mode 6 operates very similarly to Mode 4. However, output should be slightly above one quarter of full scale by the key difference is that Mode 6 provides return-to-zero (RZ) having a high cycle followed by only two low cycles. ∑-∆ DAC output. Mode 4 provides non-return-to-zero ∑-∆ DAC outputs. The RZ mode ensures that any difference in the PWM0H/L = C000H rise and fall times do not affect the ∑-∆ DAC INL. However, the CARRY OUT AT P1.0 16-BIT 0 1 1 1 0 1 1 RZ mode halves the dynamic range of the ∑-∆ DAC outputs from 0 V–AV down to 0 V–AV /2. For best results, this DD DD mode should be used with a PWM clock divider of 4. 60µs 16-BIT 16-BIT If PWM1H is set to 4010H (slightly above one quarter of FS), P2.7 is typically low for three full clocks (3 × 60 ns), high for 16.777MHz LATCH half a clock (30 ns), and then low again for half a clock (30 ns) before repeating itself. Over every 65536 clocks, the PWM 16-BIT 16-BIT compensates for the fact that the output should be slightly above one quarter of full scale by leaving the output high for 0 0 0 1 0 0 0 two half clocks in four. The rate at which this happens depends CARRY OUT AT P2.7 on the value and degree of compensation required. 16-BIT 60µs 03260-0-050 PWM1H/L = 4000H PWM0H/L = C000H Figure 51. PWM Mode 4 CARRY OUT AT P2.6 16-BIT 0 1 1 1 0 1 1 For faster DAC outputs (at lower resolution), write 0s to the LSBs that are not required. If, for example, only 12-bit perform- ance is required, write 0s to the four LSBs. This means that a 12-bit 240µs 16-BIT 16-BIT accurate ∑-∆ DAC output can occur at 4.096 kHz. Similarly writing 0s to the 8 LSBs gives an 8-bit accurate ∑-∆ DAC output at 65 kHz. 4MHz LATCH Mode 5: Dual 8-Bit PWM 16-BIT 16-BIT In Mode 5, the duty cycle of the PWM outputs and the resolu- tion of the PWM outputs are individually programmable. The 0 0 0 1 0 0 0 0, 3/4, 1/2, 1/4, 0 CARRY OUT AT P2.7 maximum resolution of the PWM output is 8 bits. The output resolution is set by the PWM1L and PWM1H SFRs for the P2.6 16-BIT adnudty P c2y.c7l eosu otpf uthtse, PreWspMec toiuvetplyu. tPs Wat MP20.L6 aanndd PPW2.7M, r0eHsp seecttsiv tehley. PWM1H/L = 4000H 240µs 03260-0-052 Both PWMs have the same clock source and clock divider. Figure 53. PWM Mode 6 Rev. B | Page 52 of 95

Data Sheet ADuC841/ADuC842/ADuC843 SERIAL PERIPHERAL INTERFACE (SPI) SCLOCK (Serial Clock I/O Pin) The ADuC841/ADuC842/ADuC843 integrate a complete hard- The master serial clock (SCLOCK) is used to synchronize the ware serial peripheral interface on-chip. SPI is an industry- data being transmitted and received through the MOSI and standard synchronous serial interface that allows 8 bits of data MISO data lines. A single data bit is transmitted and received in to be synchronously transmitted and received simultaneously, each SCLOCK period. Therefore, a byte is transmitted/received that is, full duplex. Note that the SPI pins are shared with the after eight SCLOCK periods. The SCLOCK pin is configured as I2C pins. Therefore, the user can enable only one interface or an output in master mode and as an input in slave mode. In the other on these pins at any given time (see SPE in Table 19). master mode, the bit rate, polarity, and phase of the clock are SPI can be operated at the same time as the I2C interface if the controlled by the CPOL, CPHA, SPR0, and SPR1 bits in the MSPI bit in CFG841/CFG8842 is set. This moves the SPI SPICON SFR (see Table 19). In slave mode, the SPICON outputs (MISO, MOSI, and SCLOCK) to P3.3, P3.4, and P3.5, register must be configured with the phase and polarity (CPHA respectively). The SPI port can be configured for master or slave and CPOL) of the expected input clock. In both master and operation and typically consists of four pins, described in the slave modes, the data is transmitted on one edge of the following sections. SCLOCK signal and sampled on the other. It is important, therefore, that CPHA and CPOL are configured the same for MISO (Master In, Slave Out Data I/O Pin) the master and slave devices. The MISO pin is configured as an input line in master mode SS (Slave Select Input Pin) and as an output line in slave mode. The MISO line on the master (data in) should be connected to the MISO line in the The SS pin is shared with the ADC5 input. To configure this pin slave device (data out). The data is transferred as byte-wide as a digital input, the bit must be cleared, for example, CLR (8-bit) serial data, MSB first. P1.5. This line is active low. Data is received or transmitted in MOSI (Master Out, Slave In Pin) slave mode only when the SS pin is low, allowing the parts to be used in single-master, multislave SPI configurations. If CPHA = The MOSI pin is configured as an output line in master mode 1, the SS input may be permanently pulled low. If CPHA = 0, and as an input line in slave mode. The MOSI line on the the SS input must be driven low before the first bit in a byte- master (data out) should be connected to the MOSI line in the wide transmission or reception and return high again after the slave device (data in). The data is transferred as byte-wide (8- last bit in that byte-wide transmission or reception. In SPI slave bit) serial data, MSB first. mode, the logic level on the external SS pin can be read via the SPR0 bit in the SPICON SFR. The SFR registers, described in the following tables, are used to control the SPI interface. Rev. B | Page 53 of 95

ADuC841/ADuC842/ADuC843 Data Sheet SPICON SPI Control Register SFR Address F8H Power-On Default 04H Bit Addressable Yes Table 19. SPICON SFR Bit Designations Bit No. Name Description 7 ISPI SPI Interrupt Bit. Set by the MicroConverter at the end of each SPI transfer. Cleared directly by user code or indirectly by reading the SPIDAT SFR. 6 WCOL Write Collision Error Bit. Set by the MicroConverter if SPIDAT is written to while an SPI transfer is in progress. Cleared by user code. 5 SPE SPI Interface Enable Bit. Set by the user to enable the SPI interface. Cleared by the user to enable the I2C pins, this is not requiredto enable the I2C interface if the MSPI bit is set in CFG841/CFG842. In this case, the I2C interface is automatically enabled. 4 SPIM SPI Master/Slave Mode Select Bit. Set by the user to enable master mode operation (SCLOCK is an output). Cleared by the user to enable slave mode operation (SCLOCK is an input). 3 CPOL1 Clock Polarity Select Bit. Set by the user if SCLOCK idles high. Cleared by the user if SCLOCK idles low. 2 CPHA1 Clock Phase Select Bit. Set by the user if leading SCLOCK edge is to transmit data. Cleared by the user if trailing SCLOCK edge is to transmit data. 1 SPR1 SPI Bit Rate Select Bits. 0 SPR0 These bits select the SCLOCK rate (bit rate) in master mode as follows: SPR1 SPR0 Selected Bit Rate 0 0 f /2 OSC 0 1 f /4 OSC 1 0 f /8 OSC 1 1 f /16 OSC In SPI slave mode, that is, SPIM = 0, the logic level on the external SS pin can be read via the SPR0 bit. 1The CPOL and CPHA bits should both contain the same values for master and slave devices. SPIDAT SPI Data Register Function SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read data just received by the SPI interface. SFR Address F7H Power-On Default 00H Bit Addressable No Rev. B | Page 54 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Using the SPI Interface Depending on the configuration of the bits in the SPICON SFR In master mode, a byte transmission or reception is initiated by shown in Table 19, the ADuC841/ADuC842/ADuC843 SPI a write to SPIDAT. Eight clock periods are generated via the interface transmits or receives data in a number of possible SCLOCK pin and the SPIDAT byte being transmitted via MOSI. modes. Figure 54 shows all possible SPI configurations for the With each SCLOCK period, a data bit is also sampled via MISO. parts, and the timing relationships and synchronization After eight clocks, the transmitted byte is completely between the signals involved. Also shown in this figure is the transmitted, and the input byte waits in the input shift register. SPI interrupt bit (ISPI) and how it is triggered at the end of each The ISPI flag is set automatically, and an interrupt occurs if byte-wide communication. enabled. The value in the shift register is latched into SPIDAT. SPI Interface—Slave Mode SCLOCK (CPOL = 1) In slave mode, SCLOCK is an input. The SS pin must also be driven low externally during the byte communication. Trans- SCLOCK mission is also initiated by a write to SPIDAT. In slave mode, a (CPOL = 0) data bit is transmitted via MISO, and a data bit is received via SS MOSI through each input SCLOCK period. After eight clocks, SAMPLE INPUT the transmitted byte is completely transmitted, and the input (CPHA = 1) DATA OUTPUT ? MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB byte waits in the input shift register. The ISPI flag is set automatically, and an interrupt occurs if enabled. The value in the shift register is latched into SPIDAT only when the ISPI FLAG transmission/reception of a byte has been completed. The end SAMPLE INPUT of transmission occurs after the eighth clock has been received DATA OUTPUT MSB BIT 6BIT 5 BIT 4 BIT 3BIT 2 BIT 1 LSB ? (CPHA = 0) if CPHA = 1, or when SS returns high if CPHA = 0. ISPI FLAG 03260-0-053 Figure 54. SPI Timing, All Modes SPI Interface—Master Mode In master mode, the SCLOCK pin is always an output and generates a burst of eight clocks whenever user code writes to the SPIDAT register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. Also note that the SS pin is not used in master mode. If the parts need to assert the SS pin on an external slave device, a port digital output pin should be used. Rev. B | Page 55 of 95

ADuC841/ADuC842/ADuC843 Data Sheet I2C COMPATIBLE INTERFACE The ADuC841/ADuC842/ADuC843 support a fully licensed Three SFRs are used to control the I2C interface and are I2C serial interface. The I2C interface is implemented as a full described in the following tables. hardware slave and software master. SDATA is the data I/O pin, I2CCON I2C Control Register and SCLOCK is the serial clock. These two pins are shared with the MOSI and SCLOCK pins of the on-chip SPI interface. To SFR Address E8H enable the I2C interface, the SPI interface must be turned off Power-On Default 00H (see SPE in Table 19) or the SPI interface must be moved to Bit Addressable Yes P3.3, P3.4, and P3.5 via the CFG841.1/CFG842.1 bit. Application Note uC001 describes the operation of this interface as imple- mented and is available from the MicroConverter website at www.analog.com/microconverter. Table 20. I2CCON SFR Bit Designations, Master Mode Bit No. Name Description 7 MDO I2C Software Master Data Output Bit (Master Mode Only). This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit is output on the SDATA pin if the data output enable (MDE) bit is set. 6 MDE I2C Software Master Data Output Enable Bit (Master Mode Only). Set by the user to enable the SDATA pin as an output (Tx). Cleared by the user to enable the SDATA pin as an input (Rx). 5 MCO I2C Software Master Clock Output Bit (Master Mode Only). This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit is output on the SCLOCK pin. 4 MDI I2C Software Master Data Input Bit (Master Mode Only). This data bit is used to implement a master I2C receiver interface in software. Data on the SDATA pin is latched into this bit on SCLOCK if the data output enable (MDE) bit is 0. 3 I2CM I2C Master/Slave Mode Bit. Set by the user to enable I2C software master mode. Cleared by the user to enable I2C hardware slave mode. 2 ---- Reserved. 1 ---- Reserved. 0 ---- Reserved. Table 21. I2CCON SFR Bit Designations, Slave Mode Bit No. Name Description 7 I2CSI I2C Stop Interrupt Enable Bit. Set by the user to enable I2C stop interrupts. If set, a stop bit that follows a valid start condition generates an interrupt. Cleared by the user to disable I2C stop interrupts. 6 I2CGC I2C General Call Status Bit. Set by hardware after receiving a general call address. Cleared by the user. 5 I2CID1 I2C Interrupt Decode Bits. 4 I2CID0 Set by hardware to indicate the source of an I2C interrupt. 00 Start and Matching Address. 01 Repeated Start and Matching Address. 10 User Data. 11 Stop after a Start and Matching Address. 3 I2CM I2C Master/Slave Mode Bit. Set by the user to enable I2C software master mode. Cleared by the user to enable I2C hardware slave mode. Rev. B | Page 56 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Bit No. Name Description 2 I2CRS I2C Reset Bit (Slave Mode Only). Set by the user to reset the I2C interface. Cleared by the user code for normal I2C operation. 1 I2CTX I2C Direction Transfer Bit (Slave Mode Only). Set by the MicroConverter if the interface is transmitting. Cleared by the MicroConverter if the interface is receiving. 0 I2CI I2C Interrupt Bit (Slave Mode Only). Set by the MicroConverter after a byte has been transmitted or received. Cleared automatically when user code reads the I2CDAT SFR (see I2CDAT below). I2CADD I2C Address Register Function Holds the first I2C peripheral address for the part. It may be overwritten by user code. Application Note uC001 at www.analog.com/microconverter describes the format of the I2C standard 7-bit address in detail. SFR Address 9BH Power-On Default 55H Bit Addressable No I2CADD1 I2C Address Register Function Holds the second I2C peripheral address for the part. It may be overwritten by user code. SFR Address 91H Power-On Default 7FH Bit Addressable No I2CADD2 I2C Address Register Function Holds the third I2C peripheral address for the part. It may be overwritten by user code. SFR Address 92H Power-On Default 7FH Bit Addressable No I2CADD3 I2C Address Register Function Holds the fourth I2C peripheral address for the part. It may be overwritten by user code. SFR Address 93H Power-On Default 7FH Bit Addressable No I2CDAT I2C Data Register Function Written by the user to transmit data over the I2C interface or read by user code to read data just received by the I2C interface. Accessing I2CDAT automatically clears any pending I2C interrupt and the I2CI bit in the I2CCON SFR. User software should access I2CDAT only once per interrupt cycle. SFR Address 9AH Power-On Default 00H Bit Addressable No The main features of the MicroConverter I2C interface are • Only two bus lines are required: a serial data line (SDATA) address, single master/slave relationships can exist at all and a serial clock line (SCLOCK). times even in a multislave environment. • An I2C master can communicate with multiple slave • Ability to respond to four separate addresses when devices. Because each slave device has a unique 7-bit operating in slave mode. Rev. B | Page 57 of 95

ADuC841/ADuC842/ADuC843 Data Sheet • An I2C slave can respond to repeated start conditions Once enabled in I2C slave mode, the slave controller waits for a without a stop bit in between. This allows a master to start condition. If the part detects a valid start condition, fol- change direction of transfer without giving up the bus. lowed by a valid address, followed by the R/W bit, the I2CI Note that the repeated start is detected only when a slave interrupt bit is automatically set by hardware. The I2C peripheral has previously been configured as a receiver. generates a core interrupt only if the user has pre-configured • On-chip filtering rejects <50 ns spikes on the SDATA and the I2C interrupt enable bit in the IEIP2 SFR as well as the the SCLOCK lines to preserve data integrity. global interrupt bit, EA, in the IE SFR. That is, DVDD ;Enabling I2C Interrupts for the ADuC842 MOV IEIP2,#01h ; enable I2C interrupt SETB EA I2C I2C An autoclear of the I2CI bit is implemented on the parts so that MASTER SLAVE 1 this bit is cleared automatically on a read or write access to the I2CDAT SFR. SLAI2VCE 2 03260-0-054 MMOOVV IA2,C DIA2TC,D AAT ;; II22CCII aauuttoo--cclleeaarreedd Figure 55. Typical I2C System If for any reason the user tries to clear the interrupt more than Software Master Mode once, that is, access the data SFR more than once per interrupt, The ADuC841/ADuC842/ADuC843 can be used as I2C master then the I2C controller halts. The interface then must be reset devices by configuring the I2C peripheral in master mode and using the I2CRS bit. writing software to output the data bit by bit. This is referred to as a software master. Master mode is enabled by setting the I2CM The user can choose to poll the I2CI bit or to enable the inter- bit in the I2CCON register. rupt. In the case of the interrupt, the PC counter vectors to 003BH at the end of each complete byte. For the first byte, when To transmit data on the SDATA line, MDE must be set to enable the user gets to the I2CI ISR, the 7-bit address and the R/W bit the output driver on the SDATA pin. If MDE is set, the SDATA appear in the I2CDAT SFR. pin is pulled high or low depending on whether the MDO bit is set or cleared. MCO controls the SCLOCK pin and is always The I2CTX bit contains the R/W bit sent from the master. If configured as an output in master mode. In master mode, the I2CTX is set, the master is ready to receive a byte. Therefore the SCLOCK pin is pulled high or low depending on the whether slave transmits data by writing to the I2CDAT register. If I2CTX MCO is set or cleared. is cleared, the master is ready to transmit a byte. Therefore the slave receives a serial byte. Software can interrogate the state of To receive data, MDE must be cleared to disable the output I2CTX to determine whether it must write to or read from driver on SDATA. Software must provide the clocks by toggling I2CDAT. the MCO bit and reading the SDATA pin via the MDI bit. If MDE is cleared, MDI can be used to read the SDATA pin. The Once the part has received a valid address, hardware holds value of the SDATA pin is latched into MDI on a rising edge of SCLOCK low until the I2CI bit is cleared by software. This SCLOCK. MDI is set if the SDATA pin was high on the last allows the master to wait for the slave to be ready before rising edge of SCLOCK. MDI is clear if the SDATA pin was low transmitting the clocks for the next byte. on the last rising edge of SCLOCK. The I2CI interrupt bit is set every time a complete data byte is Software must control MDO, MCO, and MDE appropriately to received or transmitted, provided it is followed by a valid ACK. generate the start condition, slave address, acknowledge bits, If the byte is followed by a NACK, an interrupt is not generated. data bytes, and stop conditions. These functions are described The part continues to issue interrupts for each complete data in Application Note uC001. byte transferred until a stop condition is received or the inter- Hardware Slave Mode face is reset. After reset, the ADuC841/ADuC842/ADuC843 default to hardware slave mode. The I2C interface is enabled by clearing When a stop condition is received, the interface resets to a state in which it is waiting to be addressed (idle). Similarly, if the the SPE bit in SPICON (this is not necessary if the MSPI bit is interface receives a NACK at the end of a sequence, it also set). Slave mode is enabled by clearing the I2CM bit in I2CCON. The parts have a full hardware slave. In slave mode, the I2C returns to the default idle state. The I2CRS bit can be used to reset the I2C interface. This bit can be used to force the interface address is stored in the I2CADD register. Data received or to be back to the default idle state. transmitted is stored in the I2CDAT register. Rev. B | Page 58 of 95

Data Sheet ADuC841/ADuC842/ADuC843 DUAL DATA POINTER The ADuC841/ADuC842/ADuC843 incorporate two data DPCON Data Pointer Control SFR pointers. The second data pointer is a shadow data pointer and SFR Address A7H is selected via the data pointer control SFR (DPCON). DPCON Power-On Default 00H also includes some useful features such as automatic hardware post-increment and post-decrement as well as automatic data Bit Addressable No pointer toggle. DPCON is described in Table 22. Table 22. DPCON SFR Bit Designations Bit No. Name Description 7 ---- Reserved. 6 DPT Data Pointer Automatic Toggle Enable. Cleared by the user to disable autoswapping of the DPTR. Set in user software to enable automatic toggling of the DPTR after each each MOVX or MOVC instruction. 5 DP1m1 Shadow Data Pointer Mode. 4 DP1m0 These two bits enable extra modes of the shadow data pointer’s operation, allowing for more compact and more efficient code size and execution. m1 m0 Behavior of the shadow data pointer. 0 0 8052 behavior. 0 1 DPTR is post-incremented after a MOVX or a MOVC instruction. 1 0 DPTR is post-decremented after a MOVX or MOVC instruction. 1 1 DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction can be useful for moving 8-bit blocks to/from 16-bit devices.) 3 DP0m1 Main Data Pointer Mode. 2 DP0m0 These two bits enable extra modes of the main data pointer operation, allowing for more compact and more efficient code size and execution. m1 m0 Behavior of the main data pointer. 0 0 8052 behavior. 0 1 DPTR is post-incremented after a MOVX or a MOVC instruction. 1 0 DPTR is post-decremented after a MOVX or MOVC instruction. 1 1 DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction can be useful for moving 8-bit blocks to/from 16-bit devices.) 1 ---- This bit is not implemented to allow the INC DPCON instruction toggle the data pointer without incrementing the rest of the SFR. 0 DPSEL Data Pointer Select. Cleared by the user to select the main data pointer. This means that the contents of this 24-bit register are placed into the three SFRs: DPL, DPH, and DPP. Set by the user to select the shadow data pointer. This means that the contents of a separate 24-bit register appears in the three SFRs: DPL, DPH, and DPP. Note 1: This is the only place where the main and shadow data MOV DPCON,#55H ; Select shadow DPTR ; DPTR1 increment mode, pointers are distinguished. Everywhere else in this data sheet ; DPTR0 increment mode wherever the DPTR is mentioned, operation on the active ; DPTR auto toggling ON DPTR is implied. MOV DPTR,#0D000H ; Shadow DPTR = D000H MOVELOOP: Note 2: Only MOVC/MOVX @DPTR instructions are relevant CLR A above. MOVC/MOVX PC/@Ri instructions do not cause the MOVC A,@A+DPTR ; Get data ; Post Inc DPTR DPTR to automatically post increment/decrement, and so on. ; Swap to Main DPTR (Data) To illustrate the operation of DPCON, the following code copies MOVX @DPTR,A ; Put ACC in XRAM ; Increment main DPTR 256 bytes of code memory at address D000H into XRAM ; Swap Shadow DPTR (Code) starting from Address 0000H. MOV A, DPL JNZ MOVELOOP MOV DPTR,#0 ; Main DPTR = 0 Rev. B | Page 59 of 95

ADuC841/ADuC842/ADuC843 Data Sheet POWER SUPPLY MONITOR is also protected against spurious glitches triggering the As its name suggests, the power supply monitor, once enabled, interrupt circuit. monitors the DV supply on the ADuC841/ADuC842/ DD ADuC843. It indicates when any of the supply pins drops below Note that the 5 V part has an internal POR trip level of 4.5 V, one of two user selectable voltage trip points, 2.93 V and 3.08 V. which means that there are no usable PSM levels on the 5 V For correct operation of the power supply monitor function, part. The 3 V part has a POR trip level of 2.45 V, allowing all AV must be equal to or greater than 2.7 V. Monitor function DD PSM trip points to be used. is controlled via the PSMCON SFR. If enabled via the IEIP2 SFR, the monitor interrupts the core using the PSMI bit in the Power Supply Monitor PSMCON SFR. This bit is not cleared until the failing power PSMCON Control Register supply has returned above the trip point for at least 250 ms. SFR Address DFH This monitor function allows the user to save working registers Power-On Default DEH to avoid possible data loss due to the low supply condition, and also ensures that normal code execution does not resume until a Bit Addressable No safe supply level has been well established. The supply monitor Table 23. PSMCON SFR Bit Designations Bit No. Name Description 7 ---- Reserved. 6 CMPD DV Comparator Bit. DD This is a read-only bit that directly reflects the state of the DV comparator. DD Read 1 indicates that the DV supply is above its selected trip point. DD Read 0 indicates that the DV supply is below its selected trip point. DD 5 PSMI Power Supply Monitor Interrupt Bit. This bit is set high by the MicroConverter if either CMPA or CMPD is low, indicating low analog or digital supply. The PSMI bit can be used to interrupt the processor. Once CMPD and/or CMPA return (and remain) high, a 250 ms counter is started. When this counter times out, the PSMI interrupt is cleared. PSMI can also be written by the user. However, if either comparator output is low, it is not possible for the user to clear PSMI. 4 TPD1 DV Trip Point Selection Bits. DD 3 TPD0 These bits select the DV trip point voltage as follows: DD TPD1 TPD0 Selected DV Trip Point (V) DD 0 0 Reserved 0 1 3.08 1 0 2.93 1 1 Reserved 2 ---- Reserved. 1 ---- Reserved. 0 PSMEN Power Supply Monitor Enable Bit. Set to 1 by the user to enable the power supply monitor circuit. Cleared to 0 by the user to disable the power supply monitor circuit. Rev. B | Page 60 of 95

Data Sheet ADuC841/ADuC842/ADuC843 WATCHDOG TIMER the watchdog timer is clocked by an internal R/C oscillator at The purpose of the watchdog timer is to generate a device reset 32 kHz ±10%. The WDCON SFR can be written only by user or interrupt within a reasonable amount of time if the ADuC841/ software if the double write sequence described in WDWR ADuC842/ADuC843 enter an erroneous state, possibly due to a below is initiated on every write access to the WDCON SFR. programming error or electrical noise. The watchdog function can be disabled by clearing the WDE (watchdog enable) bit in WDCON Watchdog Timer Control Register the watchdog control (WDCON) SFR. When enabled, the SFR Address C0H watchdog circuit generates a system reset or interrupt (WDS) if the user program fails to set the watchdog (WDE) bit within a Power-On Default 10H predetermined amount of time (see PRE3-0 bits in Table 24. Bit Addressable Yes The watchdog timer is clocked directly from the 32 kHz external crystal on the ADuC842/ADuC843. On the ADuC841, Table 24. WDCON SFR Bit Designations Bit No. Name Description 7 PRE3 Watchdog Timer Prescale Bits. 6 PRE2 The watchdog timeout period is given by the equation t = (2PRE × (29/f )) WD XTAL 5 PRE1 (0 – PRE – 7; f = 32.768 kHz (ADuC842/ADuC843), or 32kHz ± 10% (ADuC841)) XTAL 4 PRE0 PRE3 PRE2 PRE1 PRE0 Timeout Period (ms) Action 0 0 0 0 15.6 Reset or Interrupt 0 0 0 1 31.2 Reset or Interrupt 0 0 1 0 62.5 Reset or Interrupt 0 0 1 1 125 Reset or Interrupt 0 1 0 0 250 Reset or Interrupt 0 1 0 1 500 Reset or Interrupt 0 1 1 0 1000 Reset or Interrupt 0 1 1 1 2000 Reset or Interrupt 1 0 0 0 0.0 Immediate Reset PRE3–0 > 1000 Reserved 3 WDIR Watchdog Interrupt Response Enable Bit. If this bit is set by the user, the watchdog generates an interrupt response instead of a system reset when the watchdog timeout period has expired. This interrupt is not disabled by the CLR EA instruction, and it is also a fixed, high priority interrupt. If the watchdog is not being used to monitor the system, it can be used alternatively as a timer. The prescaler is used to set the timeout period in which an interrupt is generated. 2 WDS Watchdog Status Bit. Set by the watchdog controller to indicate that a watchdog timeout has occurred. Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset. 1 WDE Watchdog Enable Bit. Set by the user to enable the watchdog and clear its counters. If this bit is not set by the user within the watchdog timeout period, the watchdog generates a reset or interrupt, depending on WDIR. Cleared under the following conditions: user writes 0, watchdog reset (WDIR = 0); hardware reset; PSM interrupt. 0 WDWR Watchdog Write Enable Bit. To write data to the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the very next instruction must be a write instruction to the WDCON SFR. For example: CLR EA ;disable interrupts while writing ;to WDT SETB WDWR ;allow write to WDCON MOV WDCON,#72H ;enable WDT for 2.0s timeout SETB EA ;enable interrupts again (if rqd) Rev. B | Page 61 of 95

ADuC841/ADuC842/ADuC843 Data Sheet TIME INTERVAL COUNTER (TIC) A TIC is provided on-chip for counting longer intervals than TCEN 32.768kHz EXTERNAL CRYSTAL the standard 8051 compatible timers are capable of. The TIC is ITS0, 1 capable of timeout intervals ranging from 1/128 second to 255 hours. Furthermore, this counter is clocked by the external 8-BIT PRESCALER 32.768 kHz crystal rather than by the core clock, and it has the ability to remain active in power-down mode and time long HUNDREDTHS COUNTER power-down intervals. This has obvious applications for remote HTHSEC battery-powered sensors where regular widely spaced readings INTERVAL TIMEBASE TIEN are required. SELECTION SECOND COUNTER MUX SEC Six SFRs are associated with the time interval counter, TIMECON being its control register. Depending on the MINUTE COUNTER configuration of the IT0 and IT1 bits in TIMECON, the MIN selected time counter register overflow clocks the interval counter. When this counter is equal to the time interval value HOUR COUNTER HOUR 8-BIT loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and INTERVAL COUNTER gmeonderea, taegs aainn iwntitehrr TuIpCt iifn etnearrbulepdt. eInf athbele pda, rtht eis TinII p boitw wera-kdeosw unp TIME INTEINRTVEARLV CAOLU TNIMTEEOR UINTTERRUPT COUCNOTM =P AINRTEVAL 03260-0-055 the device and resumes code execution by vectoring directly to the TIC interrupt service vector address at 0053H. The TIC- TIMER INTVAL related SFRs are described in Table 25. Note also that the time INTVAL based SFRs can be written initially with the current time; the Figure 56. TIC, Simplified Block Diagram TIC can then be controlled and accessed by user software. In effect, this facilitates the implementation of a real-time clock. A block diagram of the TIC is shown in Figure 56. The TIC is clocked directly from a 32 kHz external crystal on the ADuC842/ADuC843 and by the internal 32 kHz ±10% R/C oscillator on the ADuC841. Due to this, instructions that access the TIC registers are also clocked at this speed. The user should ensure that there is sufficient time between instructions to these registers to allow them to execute correctly. Rev. B | Page 62 of 95

Data Sheet ADuC841/ADuC842/ADuC843 TIMECON TIC Control Register SFR Address A1H Power-On Default 00H Bit Addressable No Table 25. TIMECON SFR Bit Designations Bit No. Name Description 7 ---- Reserved. 6 TFH Twenty-Four Hour Select Bit. Set by the user to enable the hour counter to count from 0 to 23. Cleared by the user to enable the hour counter to count from 0 to 255. 5 ITS1 Interval Timebase Selection Bits. 4 ITS0 Written by user to determine the interval counter update rate. ITS1 ITS0 Interval Timebase 0 0 1/128 Second 0 1 Seconds 1 0 Minutes 1 1 Hours 3 STI Single Time Interval Bit. Set by the user to generate a single interval timeout. If set, a timeout clears the TIEN bit. Cleared by the user to allow the interval counter to be automatically reloaded and start counting again at each interval timeout. 2 TII TIC Interrupt Bit. Set when the 8-bit interval counter matches the value in the INTVAL SFR. Cleared by user software. 1 TIEN Time Interval Enable Bit. Set by the user to enable the 8-bit time interval counter. Cleared by the user to disable the interval counter. 0 TCEN Time Clock Enable Bit. Set by the user to enable the time clock to the time interval counters. Cleared by the user to disable the clock to the time interval counters and reset the time interval SFRs to the last value written to them by the user. The time registers (HTHSEC, SEC, MIN, and HOUR) can be written while TCEN is low. Rev. B | Page 63 of 95

ADuC841/ADuC842/ADuC843 Data Sheet INTVAL User Time Interval Select Register Function User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt if enabled. SFR Address A6H Power-On Default 00H Bit Addressable No Valid Value 0 to 255 decimal HTHSEC Hundredths Seconds Time Register Function This register is incremented in 1/128 second intervals once TCEN in TIMECON is active. The HTHSEC SFR counts from 0 to 127 before rolling over to increment the SEC time register. SFR Address A2H Power-On Default 00H Bit Addressable No Valid Value 0 to 127 decimal SEC Seconds Time Register Function This register is incremented in 1-second intervals once TCEN in TIMECON is active. The SEC SFR counts from 0 to 59 before rolling over to increment the MIN time register. SFR Address A3H Power-On Default 00H Bit Addressable No Valid Value 0 to 59 decimal MIN Minutes Time Register Function This register is incremented in 1-minute intervals once TCEN in TIMECON is active. The MIN SFR counts from 0 to 59 before rolling over to increment the HOUR time register. SFR Address A4H Power-On Default 00H Bit Addressable No Valid Value 0 to 59 decimal HOUR Hours Time Register Function This register is incremented in 1-hour intervals once TCEN in TIMECON is active. The HOUR SFR counts from 0 to 23 before rolling over to 0. SFR Address A5H Power-On Default 00H Bit Addressable No Valid Value 0 to 23 decimal Rev. B | Page 64 of 95

Data Sheet ADuC841/ADuC842/ADuC843 8052 COMPATIBLE ON-CHIP PERIPHERALS This section gives a brief overview of the various secondary In general-purpose I/O port mode, Port 0 pins that have 1s writ- peripheral circuits that are also available to the user on-chip. ten to them via the Port 0 SFR are configured as open-drain and These remaining functions are mostly 8052 compatible (with a therefore float. In this state, Port 0 pins can be used as high few additional features) and are controlled via standard 8052 impedance inputs. This is represented in Figure 57 by the NAND SFR bit definitions. gate whose output remains high as long as the control signal is Parallel I/O low, thereby disabling the top FET. External pull-up resistors are therefore required when Port 0 pins are used as general-purpose The ADuC841/ADuC842/ADuC843 use four input/output outputs. Port 0 pins with 0s written to them drive a logic low ports to exchange data with external devices. In addition to output voltage (V ) and are capable of sinking 1.6 mA. OL performing general-purpose I/O, some ports are capable of Port 1 external memory operations while others are multiplexed with alternate functions for the peripheral features on the device. In Port 1 is also an 8-bit port directly controlled via the P1 SFR. general, when a peripheral is enabled, that pin may not be used Port 1 digital output capability is not supported on this device. as a general-purpose I/O pin. Port 1 pins can be configured as digital inputs or analog inputs. Port 0 By (power-on) default, these pins are configured as analog inputs, that is, 1 written in the corresponding Port 1 register bit. Port 0 is an 8-bit open-drain bidirectional I/O port that is To configure any of these pins as digital inputs, the user should directly controlled via the Port 0 SFR. Port 0 is also the write a 0 to these port bits to configure the corresponding pin as multiplexed low order address and data bus during accesses to a high impedance digital input. These pins also have various external program or data memory. secondary functions as described in Table 26. Figure 57 shows a typical bit latch and I/O buffer for a Port 0 Table 26. Port 1 Alternate Pin Functions port pin. The bit latch (one bit in the port’s SFR) is represented Pin No. Alternate Function as a Type D flip-flop, which clocks in a value from the internal P1.0 T2 (Timer/Counter 2 External Input) bus in response to a write to latch signal from the CPU. The Q P1.1 T2EX (Timer/Counter 2 Capture/Reload Trigger) output of the flip-flop is placed on the internal bus in response P1.5 SS (Slave Select for the SPI Interface) to a read latch signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU. Some instructions that read a port activate READ LATCH the read latch signal, and others activate the read pin signal. See INTERNAL the Read-Modify-Write Instructions section for details. BUS D Q ADDR/DATA DVDD TO LWARTICTHE CL Q LRAETACDH CONTROL P0.x REPAIND TLOA ATCDHC PP1IN.x 03260-0-057 INTERNAL PIN Figure 58. Port 1 Bit Latch and I/O Buffer BUS D Q Port 2 WRITE TO LATCH CL Q Port 2 is a bidirectional port with internal pull-up resistors REPAIND LATCH 03260-0-056 dorirdeecrt layd cdornestrso bllyetdes v diau rthineg P f2e tScFhRes. fProormt 2 e xaltseorn eaml pitrso tghrea mhi gh- memory, and middle and high order address bytes during Figure 57. Port 0 Bit Latch and I/O Buffer accesses to the 24-bit external data memory space. As shown in Figure 57, the output drivers of Port 0 pins are switchable to an internal ADDR and ADDR/DATA bus by an As shown in Figure 59, the output drivers of Port 2 are switch- internal control signal for use in external memory accesses. able to an internal ADDR and ADDR/DATA bus by an internal During external memory accesses, the P0 SFR has 1s written to control signal for use in external memory accesses (as for it, that is, all of its bit latches become 1. When accessing Port 0). In external memory addressing mode (CONTROL = 1), external memory, the control signal in Figure 57 goes high, the port pins feature push-pull operation controlled by the enabling push-pull operation of the output pin from the internal address bus (ADDR line). However, unlike the P0 SFR internal address or data bus (ADDR/DATA line). Therefore, no during external memory accesses, the P2 SFR remains unchanged. external pull-ups are required on Port 0 for it to access external memory. Rev. B | Page 65 of 95

ADuC841/ADuC842/ADuC843 Data Sheet P3.3 and P3.4 can also be used as PWM outputs. When they are In general-purpose I/O port mode, Port 2 pins that have 1s selected as the PWM outputs via the CFG841/CFG842 SFR, the written to them are pulled high by the internal pull-ups PWM outputs overwrite anything written to P3.4 or P3.3. (Figure 60) and, in that state, can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because DVDD of the internal pull-up resistors. Port 2 pins with 0s written to ALTERNATE them drive a logic low output voltage (VOL) and are capable of LRAETACDH FOUUNTCPTUIOTN IPNUTLELR-NUAP*L sinking 1.6 mA. P3.x INTERNAL PIN P2.6 and P2.7 can also be used as PWM outputs. When they are BUS D Q selected as the PWM outputs via the CFG841/CFG842 SFR, the WRITE TO LATCH CL Q PWM outputs overwrite anything written to P2.6 or P2.7. LATCH ADDR LRAETACDH CONTROL DVDDDVDDIPNUTLELR-NUAP*L REPAIND AFLUTINNECPRUTNITAOTNE *SFINEOTERE PRDRNEEATVALI IOPLUSU SLOL FF-IUGPURE 03260-0-060 INTERNAL BUS D Q P2.x Figure 61. Port 3 Bit Latch and I/O Buffer PIN TO LWARTICTHE CL Q REPAIND LATCH *SDEEET AFIOLLSL OOFW ININTGE RFINGAULR PEU FLOLR-UP 03260-0-058 AInd addidtiiotionna lt oD tihgei tpaolr It/ Opi ns, the dedicated SPI/I2C pins (SCLOCK Figure 59. Port 2 Bit Latch and I/O Buffer and SDATA/MOSI) also feature both input and output func- tions. Their equivalent I/O architectures are illustrated in DVDD DVDD DVDD Figure 62 and Figure 64, respectively, for SPI operation and in 2 CLK Q1 Q2 Q3 Figure 63 and Figure 65 for I2C operation. Notice that in I2C DELAY mode (SPE = 0), the strong pull-up FET (Q1) is disabled, leaving only a weak pull-up (Q2) present. By contrast, in SPI Q Q4 Px.x mode (SPE = 1) the strong pull-up FET (Q1) is controlled LFAPROTOCRMHT PIN 03260-0-059 directly by SPI hardware, giving the pin push-pull capability. Figure 60. Internal Pull-Up Configuration In I2C mode (SPE = 0), two pull-down FETs (Q3 and Q4) Port 3 operate in parallel to provide an extra 60% or 70% of current sinking capability. In SPI mode (SPE = 1), however, only one of Port 3 is a bidirectional port with internal pull-ups directly the pull-down FETs (Q3) operates on each pin, resulting in sink controlled via the P3 SFR. Port 3 pins that have 1s written to capabilities identical to that of Port 0 and Port 2 pins. On the them are pulled high by the internal pull-ups and, in that state, input path of SCLOCK, notice that a Schmitt trigger conditions can be used as inputs. As inputs, Port 3 pins being pulled the signal going to the SPI hardware to prevent false triggers externally low source current because of the internal pull-ups. (double triggers) on slow incoming edges. For incoming signals Port 3 pins with 0s written to them drive a logic low output from the SCLOCK and SDATA pins going to I2C hardware, a filter conditions the signals to reject glitches of up to 50 ns in voltage (V ) and are capable of sinking 4 mA. Port 3 pins also OL duration. have various secondary functions as described in Table 27. The alternate functions of Port 3 pins can be activated only if the Notice also that direct access to the SCLOCK and SDATA/ corresponding bit latch in the P3 SFR contains a 1. Otherwise, MOSI pins is afforded through the SFR interface in I2C master the port pin is stuck at 0. mode. Therefore, if you are not using the SPI or I2C functions, Table 27. Port 3 Alternate Pin Functions you can use these two pins to give additional high current Pin No. Alternate Function digital outputs. P3.0 RxD (UART Input Pin) (or Serial Data I/O in Mode 0) SPE = 1 (SPI ENABLE) P3.1 TxD (UART Output Pin) (or Serial Clock Output in Mode 0) DVDD P3.2 INT0 (External Interrupt 0) Q1 P3.3 INT1 (External Interrupt 1)/PWM 1/MISO Q2(OFF) P3.4 T0 (Timer/Counter 0 External Input) HARDWARE SPI SCLOCK (MASTER/SLAVE) PIN PWM External Clock/PWM 0 SCHMITT Q4 (OFF) PPP333...567 TWR1DR ( (T(EEixmxtteeerrrn/nCaaoll DuDnaatttaea r M M1e eEmmxtooerrryyn RaWel Iranidtpe Su Sttrt)or obbee) ) TRIGGER Q3 03260-0-061 Figure 62. SCLOCK Pin I/O Functional Equivalent in SPI Mode Rev. B | Page 66 of 95

Data Sheet ADuC841/ADuC842/ADuC843 MOSI is shared with P3.3 and, as such, has the same Read-Modify-Write Instructions configuration as the one shown in Figure 61. Some 8051 instructions that read a port read the latch while SPE = 0 (I2C ENABLE) DVDD others read the pin. The instructions that read the latch rather than the pins are the ones that read a value, possibly change it, HARDWARE I2C Q1 and then rewrite it to the latch. These are called read-modify- (SLAVE ONLY) (OFF) write instructions, which are listed below. When the destination SFR 50ns GLITCH Q2 BITS REJECTION FILTER operand is a port or a port bit, these instructions read the latch SCLOCK rather than the pin. PIN MCO Table 28. Read-Write-Modify Instructions Q4 I2CM Q3 03260-0-062 IAOnNRsLLtr uction DL(Loeogsgiccicraialp lA tOiNoRDn, ,f ofor re exxaammpplele, O, ARNL LP P21, A, A Figure 63. SCLOCK Pin I/O Functional Equivalent in I2C Mode XRL (Logical EX-OR, for example, XRL P3, A JBC Jump if Bit = 1 and clear bit, for example, JBC SPE = 1 (SPI ENABLE) P1.1, LABEL DVDD CPL Complement bit, for example, CPL P3.0 Q1 INC Increment, for example, INC P2 Q2(OFF) HARDWARE SPI SDATA/ DEC Decrement, for example, DEC P2 (MASTER/SLAVE) MOSI DJNZ Decrement and Jump if Not Zero, for example, PIN Q4 (OFF) DJNZ P3, LABEL Q3 03260-0-097 MCLORV P PXX.Y.Y1 , C1 MCloeavre BCita rYr yo tf oP oBritt YX of Port X Figure 64. SDATA/MOSI Pin I/O Functional Equivalent in SPI Mode SETB PX.Y1 Set Bit Y of Port X 1 These instructions read the port byte (all 8 bits), modify the addressed bit, and then write the new byte back to the latch. DVDD SPE = 0 (I2C ENABLE) HARDWARE I2C Q1 Read-modify-write instructions are directed to the latch rather (OFF) (SLAVE ONLY) than to the pin to avoid a possible misinterpretation of the SFR Q2 BITS 50ns GLITCH voltage level of a pin. For example, a port pin might be used to REJECTION FILTER drive the base of a transistor. When 1 is written to the bit, the SDATA/ MCI MOSI transistor is turned on. If the CPU then reads the same port bit PIN at the pin rather than the latch, it reads the base voltage of the Q4 MCO transistor and interprets it as a Logic 0. Reading the latch rather than the pin returns the correct value of 1. Q3 IM2CDEM 03260-0-063 Figure 65. SDATA/MOSI Pin I/O Functional Equivalent in I2C Mode Rev. B | Page 67 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Timers/Counters There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once The ADuC841/ADuC842/ADuC843 have three 16-bit timer/ before it changes, it must be held for a minimum of one full counters: Timer 0, Timer 1, and Timer 2. The timer/counter machine cycle. User configuration and control of all timer hardware is included on-chip to relieve the processor core of the operating modes is achieved via three SFRs: overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers: TMOD, TCON Control and configuration for THx and TLx (x = 0, 1, and 2). All three can be configured to Timers 0 and 1. operate either as timers or as event counters. T2CON Control and configuration for In timer function, the TLx register is incremented every Timer 2. machine cycle. Thus, one can think of it as counting machine TMOD Timer/Counter 0 and 1 Mode cycles. Since a machine cycle on a single-cycle core consists of Register one core clock period, the maximum count rate is the core clock SFR Address 89H frequency. Power-On Default 00H In counter function, the TLx register is incremented by a 1-to-0 Bit Addressable No transition at its corresponding external input pin: T0, T1, or T2. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. Since it takes two machine cycles (two core clock periods) to recognize a 1-to-0 transition, the maximum count rate is half the core clock frequency. Table 29. TMOD SFR Bit Designations Bit No. Name Description 7 Gate Timer 1 Gating Control. Set by software to enable Timer/Counter 1 only while the INT1 pin is high and the TR1 control bit is set. Cleared by software to enable Timer 1 whenever the TR1 control bit is set. 6 C/T Timer 1 Timer or Counter Select Bit. Set by software to select counter operation (input from T1 pin). Cleared by software to select timer operation (input from internal system clock). 5 M1 Timer 1 Mode Select Bit 1 (Used with M0 Bit). 4 M0 Timer 1 Mode Select Bit 0. M1 M0 0 0 TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler. 0 1 16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler. 1 0 8-Bit Autoreload Timer/Counter. TH1 holds a value that is to be reloaded into TL1 each time it overflows. 1 1 Timer/Counter 1 Stopped. 3 Gate Timer 0 Gating Control. Set by software to enable Timer/Counter 0 only while the INT0 pin is high and the TR0 control bit is set. Cleared by software to enable Timer 0 whenever the TR0 control bit is set. 2 C/T Timer 0 Timer or Counter Select Bit. Set by software to select counter operation (input from T0 pin). Cleared by software to select timer operation (input from internal system clock). 1 M1 Timer 0 Mode Select Bit 1. 0 M0 Timer 0 Mode Select Bit 0. M1 M0 0 0 TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler. 0 1 16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler. 1 0 8-Bit Autoreload Timer/Counter. TH0 holds a value that is to be reloaded into TL0 each time it overflows. 1 1 TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by Timer 1 control bits. Rev. B | Page 68 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Timer/Counter 0 and 1 TCON Control Register SFR Address 88H Power-On Default 00H Bit Addressable Yes Table 30. TCON SFR Bit Designations Bit No. Name Description 7 TF1 Timer 1 Overflow Flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware when the program counter (PC) vectors to the interrupt service routine. 6 TR1 Timer 1 Run Control Bit. Set by the user to turn on Timer/Counter 1. Cleared by the user to turn off Timer/Counter 1. 5 TF0 Timer 0 Overflow Flag. Set by hardware on a Timer/Counter 0 overflow. Cleared by hardware when the PC vectors to the interrupt service routine. 4 TR0 Timer 0 Run Control Bit. Set by the user to turn on Timer/Counter 0. Cleared by the user to turn off Timer/Counter 0. 3 IE11 External Interrupt 1 (INT1) Flag. Set by hardware by a falling edge or by a zero level being applied to the external interrupt pin, INT1, depending on the state of Bit IT1. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition- activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip hardware. 2 IT11 External Interrupt 1 (IE1) Trigger Type. Set by software to specify edge-sensitive detection, that is, 1-to-0 transition. Cleared by software to specify level-sensitive detection, that is, zero level. 1 IE01 External Interrupt 0 (INT0) Flag. Set by hardware by a falling edge or by a zero level being applied to external interrupt pin INT0, depending on the state of Bit IT0. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition- activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip hardware. 0 IT01 External Interrupt 0 (IE0) Trigger Type. Set by software to specify edge-sensitive detection, that is,1-to-0 transition. Cleared by software to specify level-sensitive detection, that is, zero level. 1These bits are not used in the control of Timer/Counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins. Timer/Counter 0 and 1 Data Registers TH0 and TL0 Each timer consists of two 8-bit registers. These can be used as Timer 0 high byte and low byte. independent registers or combined into a single 16-bit register SFR Address = 8CH 8AH, respectively. depending on the timer mode configuration. TH1 and TL1 Timer 1 high byte and low byte. SFR Address = 8DH, 8BH, respectively. Rev. B | Page 69 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Mode 2 (8-Bit Timer/Counter with Autoreload) TIMER/COUNTER 0 AND 1 OPERATING MODES Mode 2 configures the timer register as an 8-bit counter (TL0) The following sections describe the operating modes for with automatic reload, as shown in Figure 68. Overflow from TL0 Timer/Counters 0 and 1. Unless otherwise noted, assume that not only sets TF0, but also reloads TL0 with the contents of TH0, these modes of operation are the same for both Timer 0 and which is preset by software. The reload leaves TH0 unchanged. Timer 1. Mode 0 (13-Bit Timer/Counter) CORE CLK Mode 0 configures an 8-bit timer/counter. Figure 66 shows C/T = 0 Mode 0 operation. Note that the divide-by-12 prescaler is not TL0 INTERRUPT (8 BITS) TF0 present on the single-cycle core. C/T = 1 P3.4/T0 CORE CONTROL CLK TR0 C/T = 0 C/T = 1 (5 TBlI0TS) (8 TBHIT0S) TF0 INTERRUPT P3.2G/INATT0E R(8E TBLHOIT0ASD) 03260-0-067 P3.4/T0 Figure 68. Timer/Counter 0, Mode 2 TR0 CONTROL Mode 3 (Two 8-Bit Timer/Counters) P3.2G/IANTTE0 03260-0-064 Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in Mode 3 simply holds its count. The effect is the same as setting Figure 66. Timer/Counter 0, Mode 0 TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two In this mode, the timer register is configured as a 13-bit register. separate counters. This configuration is shown in Figure 69. As the count rolls over from all 1s to all 0s, it sets the timer TL0 uses the Timer 0 control bits: C/T, Gate, TR0, INT0, and overflow flag, TF0. TF0 can then be used to request an interrupt. TF0. TH0 is locked into a timer function (counting machine The counted input is enabled to the timer when TR0 = 1 and cycles) and takes over the use of TR1 and TF1 from Timer 1. either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the timer to Thus, TH0 now controls the Timer 1 interrupt. Mode 3 is be controlled by external input INT0 to facilitate pulse-width provided for applications requiring an extra 8-bit timer or measurements. TR0 is a control bit in the special function counter. register TCON; Gate is in TMOD. The 13-bit register consists of When Timer 0 is in Mode 3, Timer 1 can be turned on and off all 8 bits of TH0 and the lower five bits of TL0. The upper 3 bits by switching it out of and into its own Mode 3, or it can still be of TL0 are indeterminate and should be ignored. Setting the run used by the serial interface as a baud rate generator. In fact, it flag (TR0) does not clear the registers. can be used in any application not requiring an interrupt from Mode 1 (16-Bit Timer/Counter) Timer 1 itself. Mode 1 is the same as Mode 0, except that the Mode 1 timer register is running with all 16 bits. Mode 1 is shown in CORE CLK Figure 67. C/T = 0 INTERRUPT TL0 (8 BITS) TF0 CORE CLK C/T = 1 C/T = 0 P3.4/T0 INTERRUPT (8 TBLIT0S) (8 TBHIT0S) TF0 TR0 CONTROL C/T = 1 P3.4/T0 GATE CONTROL TR0 P3.2/INT0 P3.2G/INATT0E Figure 67. Timer/Counter 0, Mode 1 03260-0-066 CCLOKR/1E2 (8T BHIT0S) TF1 INTERRUPT 03260-0-068 TR1 Figure 69. Timer/Counter 0, Mode 3 Rev. B | Page 70 of 95

Data Sheet ADuC841/ADuC842/ADuC843 T2CON Timer/Counter 2 Control Register SFR Address C8H Power-On Default 00H Bit Addressable Yes Table 31. T2CON SFR Bit Designations Bit No. Name Description 7 TF2 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 cannot be set when either RCLK = 1 or TCLK = 1. Cleared by user software. 6 EXF2 Timer 2 External Flag. Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. Cleared by user software. 5 RCLK Receive Clock Enable Bit. Set by the user to enable the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. Cleared by the user to enable Timer 1 overflow to be used for the receive clock. 4 TCLK Transmit Clock Enable Bit. Set by the user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. Cleared by the user to enable Timer 1 overflow to be used for the transmit clock. 3 EXEN2 Timer 2 External Enable Flag. Set by the user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. Cleared by the user for Timer 2 to ignore events at T2EX. 2 TR2 Timer 2 Start/Stop Control Bit. Set by the user to start Timer 2. Cleared by the user to stop Timer 2. 1 CNT2 Timer 2 Timer or Counter Function Select Bit. Set by the user to select counter function (input from external T2 pin). Cleared by the user to select timer function (input from on-chip core clock). 0 CAP2 Timer 2 Capture/Reload Select Bit. Set by the user to enable captures on negative transitions at T2EX if EXEN2 = 1. Cleared by the user to enable autoreloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow. Timer/Counter 2 Data Registers Timer/Counter 2 also has two pairs of 8-bit data registers associated with it. These are used as both timer data registers and as timer capture/reload registers. TH2 and TL2 Timer 2, data high byte and low byte. SFR Address = CDH, CCH, respectively. RCAP2H and RCAP2L Timer 2, capture/reload byte and low byte. SFR Address = CBH, CAH, respectively. Rev. B | Page 71 of 95

ADuC841/ADuC842/ADuC843 Data Sheet 16-Bit Capture Mode TIMER/COUNTER OPERATING MODES Capture mode also has two options that are selected by bit The following sections describe the operating modes for EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit Timer/Counter 2. The operating modes are selected by bits in timer or counter that, upon overflowing, sets Bit TF2, the Timer the T2CON SFR, as shown in Table 32. 2 overflow bit, which can be used to generate an interrupt. If Table 32. T2CON Operating Modes EXEN2 = 1, then Timer 2 still performs the above, but a l-to-0 RCLK (or) TCLK CAP2 TR2 Mode transition on external input T2EX causes the current value in 0 0 1 16-Bit Autoreload the Timer 2 registers, TL2 and TH2, to be captured into 0 1 1 16-Bit Capture registers RCAP2L and RCAP2H, respectively. In addition, the 1 X 1 Baud Rate transition at T2EX causes Bit EXF2 in T2CON to be set, and X X 0 OFF EXF2, like TF2, can generate an interrupt. Capture mode is illustrated in Figure 71. The baud rate generator mode is 16-Bit Autoreload Mode selected by RCLK = 1 and/or TCLK = 1. Autoreload mode has two options that are selected by Bit EXEN2 In either case, if Timer 2 is being used to generate the baud rate, in T2CON. If EXEN2 = 0, then when Timer 2 rolls over, it not the TF2 interrupt flag does not occur. Therefore, Timer 2 only sets TF2 but also causes the Timer 2 registers to be reloaded interrupts does not occur, so they do not have to be disabled. In with the 16-bit value in registers RCAP2L and RCAP2H, which this mode, the EXF2 flag, however, can still cause interrupts, are preset by software. If EXEN2 = 1, then Timer 2 still performs which can be used as a third external interrupt. Baud rate the above, but with the added feature that a 1-to-0 transition at generation is described as part of the UART serial port external input T2EX also triggers the 16-bit reload and set operation in the following section. EXF2. Autoreload mode is illustrated in Figure 70. CORE CLK* C/T2 = 0 TL2 TH2 (8 BITS) (8 BITS) T2 C/T2 = 1 PIN CONTROL TR2 RELOAD TRANSITION DETECTOR RCAP2L RCAP2H TF2 TIMER INTERRUPT T2EX EXF2 PIN CONTROL *CORE CLK IS DEFINED BY THEE CXDE NB2ITS IN PLLCON 03260-0-069 Figure 70. Timer/Counter 2, 16-Bit Autoreload Mode CORE CLK* C/T2 = 0 TL2 TH2 (8 BITS) (8 BITS) TF2 T2 C/T2 = 1 PIN CONTROL TR2 CAPTURE TIMER INTERRUPT TRANSITION DETECTOR RCAP2L RCAP2H T2EX EXF2 PIN CONTROL *CORE CLK IS DEFINED BY THEEX CEDN 2BITS IN PLLCON 03260-0-070 Figure 71. Timer/Counter 2, 16-Bit Capture Mode Rev. B | Page 72 of 95

Data Sheet ADuC841/ADuC842/ADuC843 UART SERIAL INTERFACE SBUF The serial port is full-duplex, meaning it can transmit and Both the serial port receive and transmit registers are accessed receive simultaneously. It is also receive-buffered, meaning it through the SBUF SFR (SFR address = 99H). Writing to SBUF can begin receiving a second byte before a previously received loads the transmit register, and reading SBUF accesses a byte has been read from the receive register. However, if the first physically separate receive register. byte still has not been read by the time reception of the second SCON UART Serial Port Control Register byte is complete, the first byte is lost. The physical interface to SFR Address 98H the serial data network is via Pins RxD(P3.0) and TxD(P3.1), while the SFR interface to the UART is comprised of SBUF and Power-On Default 00H SCON, as described below. Bit Addressable Yes Table 33. SCON SFR Bit Designations Bit No. Name Description 7 SM0 UART Serial Mode Select Bits. 6 SM1 These bits select the serial port operating mode as follows: SM0 SM1 Selected Operating Mode. 0 0 Mode 0: Shift Register, fixed baud rate (Core_Clk/2). 0 1 Mode 1: 8-bit UART, variable baud rate. 1 0 Mode 2: 9-bit UART, fixed baud rate (Core_Clk/32) or (Core_Clk/16). 1 1 Mode 3: 9-bit UART, variable baud rate. 5 SM2 Multiprocessor Communication Enable Bit. Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 must be cleared. In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received. If SM2 is cleared, RI is set as soon as the byte of data has been received. In Modes 2 or 3, if SM2 is set, RI is not activated if the received 9th data bit in RB8 is 0. If SM2 is cleared, RI is set as soon as the byte of data has been received. 4 REN Serial Port Receive Enable Bit. Set by user software to enable serial port reception. Cleared by user software to disable serial port reception. 3 TB8 Serial Port Transmit (Bit 9). The data loaded into TB8 is the 9th data bit transmitted in Modes 2 and 3. 2 RB8 Serial Port Receiver Bit 9. The 9th data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8. 1 TI Serial Port Transmit Interrupt Flag. Set by hardware at the end of the 8th bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3. TI must be cleared by user software. 0 RI Serial Port Receive Interrupt Flag. Set by hardware at the end of the 8th bit in Mode 0, or halfway through the stop bit in Modes 1, 2, and 3. RI must be cleared by software. Rev. B | Page 73 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Mode 0: 8-Bit Shift Register Mode This is the case if, and only if, all of the following conditions are Mode 0 is selected by clearing both the SM0 and SM1 bits in the met at the time the final shift pulse is generated: SFR SCON. Serial data enters and exits through RxD. TxD out- puts the shift clock. Eight data bits are transmitted or received. • RI = 0 Transmission is initiated by any instruction that writes to SBUF. • Either SM2 = 0 or SM2 = 1 The data is shifted out of the RxD line. The 8 bits are transmitted with the least significant bit (LSB) first. • The received stop bit = 1 Reception is initiated when the receive enable bit (REN) is 1 If any of these conditions is not met, the received frame is and the receive interrupt bit (RI) is 0. When RI is cleared, the irretrievably lost, and RI is not set. data is clocked into the RxD line, and the clock pulses are Mode 2: 9-Bit UART with Fixed Baud Rate output from the TxD line. Mode 2 is selected by setting SM0 and clearing SM1. In this Mode 1: 8-Bit UART, Variable Baud Rate mode, the UART operates in 9-bit mode with a fixed baud rate. Mode 1 is selected by clearing SM0 and setting SM1. Each data The baud rate is fixed at Core_Clk/32 by default, although by byte (LSB first) is preceded by a start bit (0) and followed by a setting the SMOD bit in PCON, the frequency can be doubled stop bit (1). Therefore, 10 bits are transmitted on TxD or are to Core_Clk/16. Eleven bits are transmitted or received: a start received on RxD. The baud rate is set by the Timer 1 or Timer 2 bit (0), 8 data bits, a programmable 9th bit, and a stop bit (1). overflow rate, or a combination of the two (one for transmission The 9th bit is most often used as a parity bit, although it can be and the other for reception). used for anything, including a 9th data bit if required. Transmission is initiated by writing to SBUF. The write to SBUF To transmit, the 8 data bits must be written into SBUF. The 9th signal also loads a 1 (stop bit) into the 9th bit position of the bit must be written to TB8 in SCON. When transmission is transmit shift register. The data is output bit by bit until the stop initiated, the 8 data bits (from SBUF) are loaded onto the bit appears on TxD and the transmit interrupt flag (TI) is transmit shift register (LSB first). The contents of TB8 are loaded automatically set, as shown in Figure 72. into the 9th bit position of the transmit shift register. The transmission starts at the next valid baud rate clock. The TI flag START STOP BIT BIT is set as soon as the stop bit appears on TxD. D0 D1 D2 D3 D4 D5 D6 D7 TxD Reception for Mode 2 is similar to that of Mode 1. The 8 data TI (SCON.1) I.E., RESAEDTY I NFTOERR MROUPRTE DATA 03260-0-072 bsfohylitlfeots wr aeirngeig si tenevpre.u nWtt ash to eRcnxc auDlrl : (8 L bSBits f ihrastv)e a bnede nlo caldoecdk eodn tino , tthhee receive Figure 72. UART Serial Port Transmission, Mode 1 • The 8 bits in the receive shift register are latched into SBUF. Reception is initiated when a 1-to-0 transition is detected on • The 9th data bit is latched into RB8 in SCON. RxD. Assuming a valid start bit is detected, character reception continues. The start bit is skipped and the 8 data bits are • The receiver interrupt flag (RI) is set. clocked into the serial port shift register. When all 8 bits have This is the case if, and only if, all of the following conditions are been clocked in, the following events occur: met at the time the final shift pulse is generated: • The 8 bits in the receive shift register are latched into SBUF. • RI = 0 • The 9th bit (stop bit) is clocked into RB8 in SCON. • Either SM2 = 0 or SM2 = 1 • The receiver interrupt flag (RI) is set. • The received stop bit = 1 If any of these conditions is not met, the received frame is irretrievably lost, and RI is not set. Rev. B | Page 74 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Mode 3: 9-Bit UART with Variable Baud Rate Mode 3 is selected by setting both SM0 and SM1. In this mode, The Timer 1 interrupt should be disabled in this application. the 8051 UART serial port operates in 9-bit mode with a vari- The timer itself can be configured for either timer or counter able baud rate determined by either Timer 1 or Timer 2. The operation, and in any of its three running modes. In the most operation of the 9-bit UART is the same as for Mode 2, but the typical application, it is configured for timer operation in the baud rate can be varied as for Mode 1. autoreload mode (high nibble of TMOD = 0010 binary). In that case, the baud rate is given by the formula In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Modes 1 and 3 Baud Rate = Mode 0 by the condition RI = 0 and REN = 1. Reception is (2SMOD/32) × (Core Clock/ [256 − TH1]) initiated in the other modes by the incoming start bit if REN = 1. Timer 2 Generated Baud Rates UART Serial Port Baud Rate Generation Baud rates can also be generated using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 Mode 0 Baud Rate Generation times before a bit is transmitted/received. Because Timer 2 has a The baud rate in Mode 0 is fixed. 16-bit autoreload mode, a wider range of baud rates is possible using Timer 2. Mode 0 Baud Rate = (Core Clock Frequency/12) Modes 1 and 2 Baud Rate = (1/16) × (Timer 2 Overflow Rate) Mode 2 Baud Rate Generation The baud rate in Mode 2 depends on the value of the SMOD bit Therefore, when Timer 2 is used to generate baud rates, the in the PCON SFR. If SMOD = 0, the baud rate is 1/32 of the timer increments every two clock cycles rather than every core core clock. If SMOD = 1, the baud rate is 1/16 of the core clock: machine cycle as before. Thus, it increments six times faster than Timer 1, and therefore baud rates six times faster are possi- Mode 2 Baud Rate = (2SMOD/32 × [Core Clock Frequency]) ble. Because Timer 2 has 16-bit autoreload capability, very low Modes 1 and 3 Baud Rate Generation baud rates are still possible. The baud rates in Modes 1 and 3 are determined by the over- Timer 2 is selected as the baud rate generator by setting the flow rate in Timer 1 or Timer 2, or in both (one for transmit TCLK and/or RCLK in T2CON. The baud rates for transmit and the other for receive). and receive can be simultaneously different. Setting RCLK and/ Timer 1 Generated Baud Rates or TCLK puts Timer 2 into its baud rate generator mode as shown in Figure 73. When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate In this case, the baud rate is given by the formula and the value of SMOD as follows: Modes 1 and 3 Baud Rate = Modes 1 and 3 Baud Rate = (2SMOD/32 × (Timer 1 Overflow Rate) (Core Clock)/(16 × [65536 − (RCAP 2H, RCAP 2L)]) TIMER 1 OVERFLOW 2 0 1 SMOD CORE CONTROL CLK* C/T2 = 0 TIMER 2 TL2 TH2 OVERFLOW 1 0 (8 BITS) (8 BITS) RCLK PTIN2 C/T2 = 1 16 RCXLOCK 1 0 TR2 TCLK NOTE: AVAILABILITY OF ADDITIONAL RELOAD EXTERNAL INTERRUPT 16 TX CLOCK RCAP2L RCAP2H T2PEINX EXF 2 TINIMTEERRR 2UPT CONTROL T*RDCAEOTNRESECI TCTILOOKNR IS DEFINED BY THEE XCEDN B2ITS IN PLLCON 03260-0-073 Figure 73. Timer 2, UART Baud Rates Rev. B | Page 75 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Timer 3 Generated Baud Rates The high integer dividers in a UART block mean that high The appropriate value to write to the DIV2-1-0 bits can be speed baud rates are not always possible using some particular calculated using the following formula where f is defined in CORE crystals. For example, using a 12 MHz crystal, a baud rate of PLLCON SFR. Note that the DIV value must be rounded down. 115200 is not possible. To address this problem, the part has  f  agdendeerda tai ndge dhiicgahtelyd a bcacuudra rtaet eb atuimd erra t(eTsi.m Teimr 3e)r s3p ceacnif ibcea lulys efodr DIV=log16l×ogBCa(O2uR)dERate instead of Timer 1 or Timer 2 for generating very accurate high speed UART baud rates including 115200 and 230400. Timer 3 T3FD is the fractional divider ratio required to achieve the also allows a much wider range of baud rates to be obtained. In required baud rate. The appropriate value for T3FD can be fact, every desired bit rate from 12 bit/s to 393216 bit/s can be calculated with the following formula: generated to within an error of ±0.8%. Timer 3 also frees up the 2× f other three timers, allowing them to be used for different T3FD= CORE −64 2DIV−1×Baud Rate applications. A block diagram of Timer 3 is shown in Figure 74. Note that T3FD should be rounded to the nearest integer. Once CORE 2 CLK the values for DIV and T3FD are calculated, the actual baud rate TIMER 1/TIMER 2 TX CLOCK can be calculated with the following formula: FRDAICVTIDIOENRAL (1 + T3FD/64) RTXI MCELRO C1/KTIMER 2 2× f Actual Baud Rate= CORE 1 0 2DIV−1×(T3FD+64) 2DIV RX CLOCK For example, to get a baud rate of 115200 while operating at 16 TC3L ROXC/TKX 1 0 T3EN TX CLOCK 03260-0-074 16.7 MDHIVz,= thloatg i(1s,6 C7D77 =21 06 /(16×115200))/log2=3.18=3 Figure 74. Timer 3, UART Baud Rates T3FD=(2×16777216)/(22×115200)−64=9=09H Two SFRs (T3CON and T3FD) are used to control Timer 3. Therefore, the actual baud rate is 114912 bit/s. T3CON is the baud rate control SFR, allowing Timer 3 to be used to set up the UART baud rate, and setting up the binary divider (DIV). Table 34. T3CON SFR Bit Designations Bit No. Name Description 7 T3BAUDEN T3UARTBAUD Enable. Set to enable Timer 3 to generate the baud rate. When set, PCON.7, T2CON.4, and T2CON.5 are ignored. Cleared to let the baud rate be generated as per a standard 8052. 6 Reserved. 5 Reserved. 4 Reserved. 3 Reserved. 2 DIV2 Binary Divider Factor. 1 DIV1 DIV2 DIV1 DIV0 Bin Divider 0 DIV0 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 Rev. B | Page 76 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Table 35. Commonly Used Baud Rates Using Timer 3 with the 16.777216 MHz PLL Clock Ideal Baud CD DIV T3CON T3FD % Error 230400 0 2 82H 09H 0.25 115200 0 3 83H 09H 0.25 115200 1 2 82H 09H 0.25 115200 2 1 81H 09H 0.25 57600 0 4 84H 09H 0.25 57600 1 3 83H 09H 0.25 57600 2 2 82H 09H 0.25 57600 3 1 81H 09H 0.25 38400 0 4 84H 2DH 0.2 38400 1 3 83H 2DH 0.2 38400 2 2 82H 2DH 0.2 38400 3 1 81H 2DH 0.2 19200 0 5 85H 2DH 0.2 19200 1 4 84H 2DH 0.2 19200 2 3 83H 2DH 0.2 19200 3 2 82H 2DH 0.2 19200 4 1 81H 2DH 0.2 9600 0 6 86H 2DH 0.2 9600 1 5 85H 2DH 0.2 9600 2 4 84H 2DH 0.2 9600 3 3 83H 2DH 0.2 9600 4 2 82H 2DH 0.2 9600 5 1 81H 2DH 0.2 Rev. B | Page 77 of 95

ADuC841/ADuC842/ADuC843 Data Sheet INTERRUPT SYSTEM The ADuC841/ADuC842/ADuC843 provide a total of nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt-related SFRs: IE Interrupt Enable Register IP Interrupt Priority Register IEIP2 Secondary Interrupt Enable Register IE Interrupt Enable Register SFR Address A8H Power-On Default 00H Bit Addressable Yes Table 36. IE SFR Bit Designations Bit No. Name Description 7 EA Set by the user to enable, or cleared to disable all interrupt sources. 6 EADC Set by the user to enable, or cleared to disable ADC interrupts. 5 ET2 Set by the user to enable, or cleared to disable Timer 2 interrupts. 4 ES Set by the user to enable, or cleared to disable UART serial port interrupts. 3 ET1 Set by the user to enable, or cleared to disable 0 Timer 1 interrupts. 2 EX1 Set by the user to enable, or cleared to disable External Interrupt 1. 1 ET0 Set by the user to enable, or cleared to disable Timer 0 interrupts. 0 EX0 Set by the user to enable, or cleared to disable External Interrupt 0 . IP Interrupt Priority Register SFR Address B8H Power-On Default 00H Bit Addressable Yes Table 37. IP SFR Bit Designations Bit No. Name Description 7 ---- Reserved. 6 PADC Written by the user to select the ADC interrupt priority (1 = High; 0 = Low). 5 PT2 Written by the user to select the Timer 2 interrupt priority (1 = High; 0 = Low). 4 PS Written by the user to select the UART serial port interrupt priority (1 = High; 0 = Low). 3 PT1 Written by the user to select the Timer 1 interrupt priority (1 = High; 0 = Low). 2 PX1 Written by the user to select External Interrupt 1 priority (1 = High; 0 = Low). 1 PT0 Written by the user to select the Timer 0 interrupt priority (1 = High; 0 = Low). 0 PX0 Written by the user to select External Interrupt 0 priority (1 = High; 0 = Low). Rev. B | Page 78 of 95

Data Sheet ADuC841/ADuC842/ADuC843 IEIP2 Secondary Interrupt Enable Register SFR Address A9H Power-On Default A0H Bit Addressable No Table 38. IEIP2 SFR Bit Designations Bit No. Name Description 7 ---- Reserved. 6 PTI Priority for time interval interrupt. 5 PPSM Priority for power supply monitor interrupt. 4 PSI Priority for SPI/I2C interrupt. 3 ---- This bit must contain zero. 2 ETI Set by the user to enable, or cleared to disable time interval counter interrupts. 1 EPSMI Set by the user to enable, or cleared to disable power supply monitor interrupts. 0 ESI Set by the user to enable, or cleared to disable SPI or I2C serial port interrupts. Interrupt Priority Interrupt Vectors The interrupt enable registers are written by the user to enable When an interrupt occurs, the program counter is pushed onto individual interrupt sources, while the interrupt priority regis- the stack, and the corresponding interrupt vector address is ters allow the user to select one of two priority levels for each loaded into the program counter. The interrupt vector addresses interrupt. An interrupt of a high priority may interrupt the are shown in Table 40. service routine of a low priority interrupt, and if two interrupts Table 40. Interrupt Vector Addresses of different priority occur at the same time, the higher level Source Vector Address interrupt is serviced first. An interrupt cannot be interrupted by IE0 0003H another interrupt of the same priority level. If two interrupts of TF0 000BH the same priority level occur simultaneously, a polling sequence IE1 0013H is observed as shown in Table 39. TF1 001BH Table 39. Priority within an Interrupt Level RI + TI 0023H Source Priority Description TF2 + EXF2 002BH PSMI 1 (Highest) Power Supply Monitor Interrupt. ADCI 0033H WDS 2 Watchdog Timer Interrupt. ISPI/I2CI 003BH IE0 2 External Interrupt 0. PSMI 0043H ADCI 3 ADC Interrupt. TII 0053H TF0 4 Timer/Counter 0 Interrupt. WDS 005BH IE1 5 External Interrupt 1. TF1 6 Timer/Counter 1 Interrupt. ISPI/I2CI 7 SPI Interrupt/I2C Interrupt. RI + TI 8 Serial Interrupt. TF2 + EXF2 9 Timer/Counter 2 Interrupt. TII 11(Lowest) Time Interval Counter Interrupt. Rev. B | Page 79 of 95

ADuC841/ADuC842/ADuC843 Data Sheet HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design ADuC842/ADuC843 considerations that must be addressed when integrating the EXTERNAL P3.4 TO INTERNAL ADuC841/ADuC842/ADuC843 into any hardware system. CLOCK TIMING CIRCUITS SOURCE Clock Oscillator The clock source for the parts can be generated by the internal PneLcLt oar 3 b2y.7 a6n8 ekxHtezr npaarl acllloecl kre isnopnuatn. tT cor uysstea tlh bee itnwteeernn aXl TPALLL,1 c aonnd- 03260-0-077 Figure 77. Connecting an External Clock Source (ADuC842/ADuC843) XTAL2, and connect a capacitor from each pin to ground as shown in Figure 75. The parts contain an internal capacitance of Whether using the internal PLL or an external clock source, the 18 pF on the XTAL1 and XTAL2 pins, which is sufficient for specified operational clock speed range of the devices is 400 kHz to most watch crystals. This crystal allows the PLL to lock correctly 16.777216 MHz, (20 MHz, ADuC841). The core itself is static, to give an fVCO of 16.777216 MHz. If no crystal is present, the and functions all the way down to dc. But at clock speeds slower PLL free runs, giving an fVCO of 16.7 MHz ±20%. In this mode, that 400 kHz, the ADC can no longer function correctly. There- the CD bits are limited to CD = 1, giving a max core clock of fore, to ensure specified operation, use a clock frequency of at 8.38 MHz. This is useful if an external clock input is required. least 400 kHz and no more than 20 MHz. The part powers up and the PLL free runs; the user then writes External Memory Interface to the CFG842 SFR in software to enable the external clock input In addition to its internal program and data memories, the parts on P3.4. Note that double the required clock must be provided can access up to 16 MBytes of external data memory (SRAM). externally since the part runs at CD = 1. A better solution is to use Note that the parts cannot access external program memory. the ADuC841 with the external clock. Figure 78 shows a hardware configuration for accessing up to For the ADuC841, connect the crystal in the same manner; 64 kBytes of external RAM. This interface is standard to any external capacitors should be connected as per the crystal 8051 compatible MCU. manufacturer’s recommendations. A minimum capacitance of 20 pF is recommended on XTAL1 and XTAL2. The ADuC841 does ADuC841/ SRAM not operate if no crystal is present. ADuC842/ D0–D7 ADuC843 P0 (DATA) An external clock may be connected as shown in Figure 76 and LATCH Figure 77. A0–A7 ALE ADuC841/ADuC842/ADuC843 XTAL1 P2 A8–A15 RD OE XTAL2 TTOIM IINNTGE CRINRACLUITS 03260-0-076 Figure 78. ExternWaRl Data Memory Interface (64 WkBEytes Address Spa03260-0-078ce ) Figure 75. External Parallel Resonant Crystal Connections ADuC841 EXTERNAL XTAL1 CLOCK SOURCE XTAL2 TO INTERNAL TIMING CIRCUITS 03260-0-075 Figure 76. Connecting an External Clock Source (ADuC841) Rev. B | Page 80 of 95

Data Sheet ADuC841/ADuC842/ADuC843 connected directly together, back-to-back Schottky diodes If access to more than 64 kBytes of RAM is desired, a feature should be connected between them, as shown in Figure 80. unique to the ADuC841/ADuC842/ADuC843 allows address- ing up to 16 MBytes of external RAM simply by adding an DIGITAL SUPPLY ANALOG SUPPLY additional latch as illustrated in Figure 79. 10µF 10µF +– +– ADuC841/ SRAM ADuC842/ D0–D7 ADuC843 P0 (DATA) DVDD AVDD 0.1µF ADuC841/ LATCH A0–A7 0.1µF ADuC842/ ALE ADuC843 AGND DGND P2 LATCH A8–A15 03260-0-080 A16–A23 Figure 80. External Dual-Supply Connections As an alternative to providing two separate power supplies, the WRDR OWEE 03260-0-079 uansedr/ ocra nfe hrreiltpe kbeeeapd AbVetDwDe qeuni eitt abnyd p DlaVciDnDg, aa nsdm tahlle nse drieecso ruepsilsintogr Figure 79. External Data Memory Interface (16 MBytes Address Space) AVDD separately to ground. An example of this configuration is shown in Figure 81. With this configuration, other analog In either implementation, Port 0 (P0) serves as a multiplexed circuitry (such as op amps and voltage reference) can be powered address/data bus. It emits the low byte of the data pointer (DPL) from the AV supply line as well. The user still needs to DD as an address, which is latched by a pulse of ALE prior to data include back-to-back Schottky diodes between AV and DV DD DD being placed on the bus by the ADuC841/ADuC842/ADuC843 to protect them from power-up and power-down transient (write operation) or by the SRAM (read operation). Port 2 (P2) conditions that could momentarily separate the two supply voltages. provides the data pointer page byte (DPP) to be latched by ALE, followed by the data pointer high byte (DPH). If no latch is connected to P2, DPP is ignored by the SRAM, and the 8051 DIGITAL SUPPLY standard of 64 kBytes external data memory access is maintained. 10µF BEAD 1.6Ω 10µF + Power Supplies – The operational power supply voltage of the parts depends on DVDD AVDD whether the part is the 3 V version or the 5 V version. The ADuC841/ 0.1µF 0.1µF ADuC842/ specifications are given for power supplies within 2.7 V to 3.6 V ADuC843 or ±5% of the nominal 5 V level. DGND AGND FNoort eth teh aCt SFPig puarcek 8a0g ea,n cdo nFnigeucrte t h8e1 erxefterar tDoV the ,P DQGFNP Dpa, cAkVage,. 03260-0-081 DD DD Figure 81. External Single-Supply Connections and AGND in the same manner. Also, the paddle on the bottom of the package should be soldered to a metal plate to provide Notice that in both Figure 80 and Figure 81, a large value mechanical stability. This metal plate should not be connected (10 µF) reservoir capacitor sits on DV and a separate 10 µF DD to ground. capacitor sits on AV . Also, local small-value (0.1 µF) capaci- DD tors are located at each V pin of the chip. As per standard DD Separate analog and digital power supply pins (AV and DV , DD DD design practice, be sure to include all of these capacitors, and respectively) allow AV to be kept relatively free of the noisy DD ensure the smaller capacitors are close to each AV pin with DD digital signals that are often present on the system DV line. DD trace lengths as short as possible. Connect the ground terminal However, though you can power AV and DV from two DD DD of each of these capacitors directly to the underlying ground separate supplies if desired, you must ensure that they remain plane. Finally, note that at all times, the analog and digital ground within ±0.3 V of one another at all times to avoid damaging the pins on the part must be referenced to the same system ground chip (as per the Absolute Maximum Ratings section). reference point. Therefore, it is recommended that unless AV and DV are DD DD Rev. B | Page 81 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Power Consumption power-down mode, the part consumes a total of approximately The currents consumed by the various sections of the part are 20 µA. There are five ways of terminating power-down mode: shown in Table 41. The core values given represent the current drawn by DV , while the rest (ADC, DAC, voltage ref) are Asserting the RESET Pin (Pin 15) DD pulled by the AV pin and can be disabled in software when DD Returns to normal mode. All registers are set to their default not in use. The other on-chip peripherals (such as the watchdog state and program execution starts at the reset vector once the timer and the power supply monitor) consume negligible RESET pin is de-asserted. current, and are therefore lumped in with the core operating Cycling Power current here. Of course, the user must add any currents sourced by the parallel and serial I/O pins, and sourced by the DAC, in All registers are set to their default state and program execution order to determine the total current needed at the supply pins. starts at the reset vector approximately 128 ms later. Also, current drawn from the DV supply increases by DD Time Interval Counter (TIC) Interrupt approximately 10 mA during Flash/EE erase and program cycles. Power-down mode is terminated, and the CPU services the TIC Table 41. Typical I of Core and Peripherals DD interrupt. The RETI at the end of the TIC ISR returns the core V = 5 V V = 3 V DD DD to the instruction after the one that enabled power-down. Core (Normal Mode) (2.2 nA × M ) (1.4 nA × M ) CLK CLK I2C or SPI Interrupt ADC 1.7 mA 1.7 mA DAC (Each) 250 µA 200 µA Power-down mode is terminated, and the CPU services the Voltage Ref 200 µA 150 µA I2C/SPI interrupt. The RETI at the end of the ISR returns the core to the instruction after the one that enabled power-down. Note that the I2C/SPI power-down interrupt enable bit (SERIPD) Since operating DV current is primarily a function of clock DD in the PCON SFR must be set to allow this mode of operation. speed, the expressions for core supply current in Table 41 are given as functions of M , the core clock frequency. Plug in a INT0 Interrupt CLK value for MCLK in hertz to determine the current consumed by Power-down mode is terminated, and the CPU services the the core at that oscillator frequency. Since the ADC and DACs INT0 interrupt. The RETI at the end of the ISR returns the core can be enabled or disabled in software, add only the currents to the instruction after the one that enabled power-down. The from the peripherals you expect to use. And again, do not forget INT0 pin must not be driven low during or within two machine to include current sourced by I/O pins, serial port pins, DAC cycles of the instruction that initiates power-down mode. Note outputs, and so forth, plus the additional current drawn during that the INT0 power-down interrupt enable bit (INT0PD) in Flash/EE erase and program cycles. A software switch allows the PCON SFR must be set to allow this mode of operation. the chip to be switched from normal mode into idle mode, and Power-On Reset (POR) also into full power-down mode. Brief descriptions of idle and power-down modes follow. An internal POR is implemented on the ADuC841/ADuC842/ Power Saving Modes ADuC843. In idle mode, the oscillator continues to run, but the core clock 3 V Part generated from the PLL is halted. The on-chip peripherals For DV below 2.45 V, the internal POR holds the part in reset. DD continue to receive the clock, and remain functional. The CPU As DV rises above 2.45 V, an internal timer times out for DD status is preserved with the stack pointer and program counter, approximately 128 ms before the part is released from reset. The and all other internal registers maintain their data during idle user must ensure that the power supply has reached a stable mode. Port pins and DAC output pins retain their states in this 2.7 V minimum level by this time. Likewise on power-down, mode. The chip recovers from idle mode upon receiving any the internal POR holds the part in reset until the power supply enabled interrupt, or upon receiving a hardware reset. has dropped below 1 V. Figure 82 illustrates the operation of the internal POR in detail. In full power-down mode, both the PLL and the clock to the core are stopped. The on-chip oscillator can be halted or can 2.45V TYP continue to oscillate, depending on the state of the oscillator DVDD 1.0V TYP 128ms TYP 128ms TYP 1.0V TYP power-down bit in the PLLCON SFR. The TIC, being driven directly from the oscillator, can also be enabled during power- down. All other on-chip peripherals are, however, shut down. Pouotrpt upti ngso erest taoin a thhiegihr liomgpice dleavneclse isnta tthei s(t mhroede-es, tbautet) t. hDeu DriAnCg full COINRTEE RRNEASLET 03260-0-082 Figure 82. Internal POR Operation Rev. B | Page 82 of 95

Data Sheet ADuC841/ADuC842/ADuC843 5 V Part reach their destinations. For example, do not power components on the analog side of Figure 84b with DV since that would For DV below 4.5 V, the internal POR holds the part in reset. DD DD force return currents from DV to flow through AGND. Also, As DV rises above 4.5 V, an internal timer times out for DD DD try to avoid digital currents flowing under analog circuitry, approximately 128 ms before the part is released from reset. The which could happen if the user places a noisy digital chip on the user must ensure that the power supply has reached a stable left half of the board in Figure 84c. Whenever possible, avoid 4.75 V minimum level by this time. Likewise on power-down, large discontinuities in the ground plane(s) (like those formed the internal POR holds the part in reset until the power supply by a long trace on the same layer), since they force return has dropped below 1 V. Figure 83 illustrates the operation of the signals to travel a longer path. And of course, make all connec- internal POR in detail. tions to the ground plane directly, with little or no trace separating 4.75V the pin from its via to ground. DVDD 1.0V TYP 1.0V 128ms 128ms If the user plans to connect fast logic signals (rise/fall time < 5 ns) to any of the part’s digital inputs, a series resistor should be added to each relevant line to keep rise and fall times longer COINRTEE RRNEASLET 03260-0-096 tuhsauna l5ly n ssu affti cthieen pt atrot ’ps rienvpeuntt p hinigsh. Asp veaeldu esi ognf 1al0s0 f rΩo mor c2o0u0p Ωlin igs capacitively into the part and from affecting the accuracy of Figure 83. Internal POR Operation ADC conversions. Grounding and Board Layout Recommendations As with all high resolution data converters, special attention must be paid to grounding and PC board layout of ADuC841/ a. PCLOAMCEP OANNEANLTOSG PCLOAMCPEO DNIGENITTASL ADuC842/ADuC843 based designs to achieve optimum HERE HERE performance from the ADC and the DACs. Although the parts AGND DGND have separate pins for analog and digital ground (AGND and DGND), the user must not tie these to two separate ground planes unless the two ground planes are connected together very close to the part, as illustrated in the simplified example of Figure 84a. In systems where digital and analog ground planes PLACE ANALOG PLACE DIGITAL are connected together somewhere else (for example, at the b. COMPONENTS COMPONENTS HERE HERE system’s power supply), they cannot be connected again near the part since a ground loop would result. In these cases, tie all AGND DGND the part’s AGND and DGND pins to the analog ground plane, as illustrated in Figure 84b. In systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and c. PLACE ANALOG PLACE DIGITAL vice versa. The part can then be placed between the digital and COMPONENTS COMPONENTS HERE HERE analog sections, as illustrated in Figure 84c. aInp pallilc oaft itohness,e k seceepn ianr imosi,n adn dth ien f mlowor eo fc coumrprelincta ftreodm re tahl-el isfue pplies GND 03260-0-083 Figure 84. System Grounding Schemes and back to ground. Make sure the return paths for all currents are as close as possible to the paths that the currents took to Rev. B | Page 83 of 95

ADuC841/ADuC842/ADuC843 Data Sheet DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) DVDD 1kΩ DVDD 1kΩ 2-PIN HEADER FOR EMULATION ACCESS 52 51 50 49 48 47 46 45 44 43 42 41 40 (NORMALLY OPEN) D D N A ANALOG INPUT ADC0 DVD DGN PSE E 39 38 37 ADuC841/ADuC842/ADuC843 AVDD 36 DVDD AVDD DGND 35 AGND DVDD 34 CREF XTAL2 33 11.0592MHz (ADuC841) VREF OUTPUT VREF XTAL1 32 32.768kHz (ADuC842/ADuC843) DAC0 31 DAC1 30 DAC OUTPUT 29 ADC7 RESET RXD TXD DVDD DGND 2287 NOT CONNECTED IN THIS EXAMPLE DVDD ADM202 DVDD 9-PIN D-SUB C1+ VCC FEMALE V+ GND 1 C1– T1OUT 2 C2+ R1IN 3 C2– R1OUT 4 V– T1IN 5 T2OUT T2IN 6 R2IN R2OUT 789 03260-0-084 Figure 85. Example System (PQFP Package), DACs Not Present on ADuC843 OTHER HARDWARE CONSIDERATIONS for a simple (and zero-cost-per-board) method of gaining in- To facilitate in-circuit programming, plus in-circuit debug and circuit serial download access to the part. emulation options, users need to implement some simple connection points in their hardware to allow easy access to In addition to the basic UART connections, users also need a download, debug, and emulation modes. way to trigger the chip into download mode. This is accom- In-Circuit Serial Download Access plished via a 1 kΩ pull-down resistor that can be jumpered onto Nearly all ADuC841/ADuC842/ADuC843 designs want to take the PSEN pin, as shown in Figure 85. To get the part into download advantage of the in-circuit reprogrammability of the chip. This mode, simply connect this jumper and power-cycle the device is accomplished by a connection to the ADuC841/ADuC842/ (or manually reset the device, if a manual reset button is available), ADuC843’s UART, which requires an external RS-232 chip for and it is then ready to serially receive a new program. With the level translation if downloading code from a PC. Basic configura- jumper removed, the device comes up in normal mode (and tion of an RS-232 connection is illustrated in Figure 85 with a runs the program) whenever power is cycled or RESET is toggled. simple ADM202 based circuit. If users would rather not design an RS-232 chip onto a board, refer to Application Note uC006, A 4-Wire UART-to-PC Interface, (at www.analog.com/microconverter) Rev. B | Page 84 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Note that PSEN is normally an output (as described in the QUICKSTART DEVELOPMENT SYSTEM External Memory Interface section) and is sampled as an input The QuickStart Development System is an entry-level, low cost only on the falling edge of RESET, that is, at power-up or upon development tool suite supporting the parts. The system an external manual reset. Note also that if any external circuitry consists of the following PC based (Windows® compatible) unintentionally pulls PSEN low during power-up or reset hardware and software development tools. events, it could cause the chip to enter download mode and Hardware Evaluation board and serial port therefore fail to begin user code execution as it should. To pre- programming cable. vent this, ensure that no external signals are capable of pulling the PSEN pin low, except for the external PSEN jumper itself. Software Serial download software. Embedded Serial Port Debugger Miscellaneous CD-ROM documentation and prototype device. From a hardware perspective, entry into serial port debug mode is identical to the serial download entry sequence described in A brief description of some of the software tools and the preceding section. In fact, both serial download and serial components in the QuickStart Development System follows. port debug modes can be thought of as essentially one mode of Download—In-Circuit Serial Downloader operation used in two different ways. Note that the serial port The serial downloader is a Windows application that allows the debugger is fully contained on the part (unlike ROM monitor user to serially download an assembled program (Intel® hexadeci- type debuggers), and therefore no external memory is needed to mal format file) to the on-chip program flash memory via the enable in-system debug sessions. serial COM1 port on a standard PC. Application Note uC004 Single-Pin Emulation Mode details this serial download protocol and is available from Also built into the part is a dedicated controller for single-pin www.analog.com/microconverter. in-circuit emulation (ICE) using standard production ADuC841/ ASPIRE—IDE ADuC842/ADuC843 devices. In this mode, emulation access is The ASPIRE integrated development environment is a gained by connection to a single pin, the EA pin. Normally, this Windows application that allows the user to compile, edit, and pin is hardwired either high or low to select execution from debug code in the same environment. The ASPIRE software internal or external program memory space, as described allows users to debug code execution on silicon using the earlier. To enable single-pin emulation mode, however, users MicroConverter UART serial port. The debugger provides need to pull the EA pin high through a 1 kΩ resistor, as shown access to all on-chip peripherals during a typical debug session in Figure 85. The emulator then connects to the 2-pin header as well as single step, animate, and break-point code execution also shown in Figure 85. To be compatible with the standard control. connector that comes with the single-pin emulator available from Accutron Limited (www.accutron.com), use a 2-pin Note that the ASPIRE IDE is also included as part of the 0.1 inch pitch friction lock header from Molex (www.molex.com) QuickStart Plus System. As part of the QuickStart Plus System, such as their part number 22-27-2021. Be sure to observe the the ASPIRE IDE also supports mixed level and C source debug. polarity of this header. As represented in Figure 85, when the This is not available in the QuickStart System, but there is an friction lock tab is at the right, the ground pin should be the example project that demonstrates this capability. lower of the two pins (when viewed from the top). QuickStart Plus Development System Typical System Configuration The QuickStart Plus Development System offers users enhanced The typical configuration shown in Figure 85 summarizes some nonintrusive debug and emulation tools. The system consists of of the hardware considerations that were discussed in previous the following PC based (Windows compatible) hardware and sections. software development tools. DEVELOPMENT TOOLS Hardware Prototype Board. Accutron Nonintrusive Single-Pin Emulator. There are two models of development tools available for the ADuC841/ADuC842/ADuC843: Software ASPIRE Integrated Development Environment. Features full C and assembly • QuickStart™—Entry-level development system emulation using the Accutron single pin emulator. • QuickStart Plus—Comprehensive development system Miscellaneous CD-ROM documentation. These systems are described briefly in the following sections. Rev. B | Page 85 of 95

ADuC841/ADuC842/ADuC843 Data Sheet TIMING SPECIFICATIONS1, 2, 3 Table 42. AV =2.7 V to 3.6 V or 4.75 V to 5.25 V, DV = 2.7 V to 3.6 V or 4.75 V to 5.25 V; all specifications T to T , DD DD MIN MAX unless otherwise noted Parameter 32.768 kHz External Crystal ADuC842/ADuC843 CLOCK INPUT (External Clock Driven XTAL1) Min Typ Max Unit t XTAL1 Period 30.52 µs CK t XTAL1 Width Low 6.26 µs CKL t XTAL1 Width High 6.26 µs CKH t XTAL1 Rise Time 9 ns CKR t XTAL1 Fall Time 9 ns CKF 1/t ADuC842/ADuC843 Core Clock Frequency4 0.131 16.78 MHz CORE t ADuC842/ADuC843 Core Clock Period5 0.476 µs CORE t ADuC842/ADuC843 Machine Cycle Time6 0.059 0.476 7.63 µs CYC 1 AC inputs during testing are driven at DVDD – 0.5 V for a Logic 1 and 0.45 V for Logic 0. Timing measurements are made at VIH min for Logic 1 and VIL max for Logic 0, as shown in Figure 87. 2 For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs, as shown in Figure 87. 3 CLOAD for all outputs = 80 pF, unless otherwise noted. 4 ADuC842/ADuC843 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 16.78 MHz internal clock for the system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR. 5 This number is measured at the default Core_Clk operating frequency of 2.09 MHz. 6 ADuC842/ADuC843 machine cycle time is nominally defined as 1/Core_CLK. Parameter Variable External Crystal ADuC841 CLOCK INPUT (External Clock Driven XTAL1) Min Typ Max Unit t XTAL1 Period 62.5 1000 ns CK t XTAL1 Width Low 20 ns CKL t XTAL1 Width High 20 ns CKH t XTAL1 Rise Time 20 ns CKR t XTAL1 Fall Time 20 ns CKF 1/t ADuC841 Core Clock Frequency 0.131 20 MHz CORE t ADuC841 Core Clock Period 0.476 µs CORE t ADuC841 Machine Cycle Time 0.05 0.476 7.63 µs CYC tCKH tCKR tCKL t tCKF 03260-0-085 CK Figure 86. XTAL1 Input DVDD–0 .04.55VV 00T..22EDDSVVTDD PDDO–+I N 00T..91SVV VLOADVVLLOOAADD –+ 00..11VV REPTFOIEMRININETGNSCE VVLLOOAADD–– 00..11VVVLOAD 03260-0-086 Figure 87. Timing Waveform Characteristics Rev. B | Page 86 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Parameter 16 MHz Core Clk 8 MHz Core Clock EXTERNAL DATA MEMORY READ CYCLE Min Max Min Max Unit tRLRH RD Pulse Width 60 125 ns t Address Valid after ALE Low 60 120 ns AVLL t Address Hold after ALE Low 145 290 ns LLAX tRLDV RD Low to Valid Data In 48 100 Ns tRHDX Data and Address Hold after RD 0 0 ns tRHDZ Data Float after RD 150 625 ns t ALE Low to Valid Data In 170 350 ns LLDV t Address to Valid Data In 230 470 ns AVDV tLLWL ALE Low to RD or WR Low 130 255 ns tAVWL Address Valid to RD or WR Low 190 375 ns tRLAZ RD Low to Address Float 15 35 ns tWHLH RD or WR High to ALE High 60 120 ns ALE (O) tWHLH PSEN (O) tLLDV tLLWL tRLRH RD (O) tAVWL tRLDV tRHDZ tAVLL tLLAX tRHDX tRLAZ PORT 0 (I/O) A0�A7 (OUT) DATA(IN) tAVDV PORT 2 (O) A16�A23 A8A15 03260-0-087 Figure 88. External Data Memory Read Cycle Rev. B | Page 87 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Parameter 16 MHz Core Clk 8 MHz Core Clock EXTERNAL DATA MEMORY WRITE CYCLE Min Max Min Max Unit tWLWH WR Pulse Width 65 130 ns t Address Valid after ALE Low 60 120 ns AVLL t Address Hold after ALE Low 65 135 ns LLAX tLLWL ALE Low to RD or WR Low 130 260 ns tAVWL Address Valid to RD or WR Low 190 375 ns tQVWX Data Valid to WR Transition 60 120 ns tQVWH Data Setup before WR 120 250 ns tWHQX Data and Address Hold after WR 380 755 ns tWHLH RD or WR High to ALE High 60 125 ns ALE (O) tWHLH PSEN (O) tLLWL tWLWH WR (O) tAVWL tAVLL tLLAX tQVWX tQVWH tWHQX A0�A7 DATA PORT 2 (O) A16�A23 V8 A15 03260-0-088 Figure 89. External Data Memory Write Cycle Rev. B | Page 88 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Parameter I2C COMPATIBLE INTERFACE TIMING Min Max Unit t SCLOCK Low Pulse Width 1.3 µs L t SCLOCK High Pulse Width 0.6 µs H t Start Condition Hold Time 0.6 µs SHD t Data Setup Time 100 µs DSU t Data Hold Time 0.9 µs DHD t Setup Time for Repeated Start 0.6 µs RSU t Stop Condition Setup Time 0.6 µs PSU t Bus Free Time between a Stop Conditionand a Start Condition 1.3 µs BUF t Rise Time of Both SCLOCK and SDATA 300 ns R t Fall Time of Both SCLOCK and SDATA 300 ns F t 1 Pulse Width of Spike Suppressed 50 ns SUP 1Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns. tBUF tSUP tR SDATA (I/O) MSB LSB ACK MSB tDSU tDHD tDSU tDHD tF tPSU tSHD tH tRSU tR SCLK (I) 1 2-7 8 9 1 COSNPTDOSITPION COSNTDAIRTTION tL tSUP RESPSTEA(RART)TED tF 03260-0-091 Figure 90. I2C Compatible Interface Timing Rev. B | Page 89 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Parameter SPI MASTER MODE TIMING (CPHA = 1) Min Typ Max Unit t SCLOCK Low Pulse Width1 476 ns SL t SCLOCK High Pulse Width1 476 ns SH t Data Output Valid after SCLOCK Edge 50 ns DAV t Data Input Setup Time before SCLOCK Edge 100 ns DSU t Data Input Hold Time after SCLOCK Edge 100 ns DHD t Data Output Fall Time 10 25 ns DF t Data Output Rise Time 10 25 ns DR t SCLOCK Rise Time 10 25 ns SR t SCLOCK Fall Time 10 25 ns SF 1 Characterized under the following conditions: a. Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1, respectively, that is, core clock frequency = 2.09 MHz. b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively. SCLOCK (CPOL = 0) t t SH SL t t SCLOCK SR SF (CPOL = 1) t DAV tDF tDR MOSI MSB BITS 6–1 LSB MISO MSB IN BITS 6–1 LSB IN tDSU tDHD 03260-0-092 Figure 91. SPI Master Mode Timing (CPHA = 1) Rev. B | Page 90 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Parameter SPI MASTER MODE TIMING (CPHA = 0) Min Typ Max Unit t SCLOCK Low Pulse Width1 476 ns SL t SCLOCK High Pulse Width1 476 ns SH t Data Output Valid after SCLOCK Edge 50 ns DAV t Data Output Setup before SCLOCK Edge 150 ns DOSU t Data Input Setup Time before SCLOCK Edge 100 ns DSU t Data Input Hold Time after SCLOCK Edge 100 ns DHD t Data Output Fall Time 10 25 ns DF t Data Output Rise Time 10 25 ns DR t SCLOCK Rise Time 10 25 ns SR t SCLOCK Fall Time 10 25 ns SF 1 Characterized under the following conditions: a. Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1, respectively, that is, core clock frequency = 2.09 MHz. b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively. SCLOCK (CPOL = 0) t t SH SL t t SCLOCK SR SF (CPOL = 1) t DAV t t t DOSU DF DR MOSI MSB BITS 6–1 LSB MISO MSB IN BITS 6–1 LSB IN tDSU tDHD 03260-0-093 Figure 92. SPI Master Mode Timing (CPHA = 0) Rev. B | Page 91 of 95

ADuC841/ADuC842/ADuC843 Data Sheet Parameter SPI SLAVE MODE TIMING (CPHA = 1) Min Typ Max Unit tSS SS to SCLOCK Edge 0 ns t SCLOCK Low Pulse Width 330 ns SL t SCLOCK High Pulse Width 330 ns SH t Data Output Valid after SCLOCK Edge 50 ns DAV t Data Input Setup Time before SCLOCK Edge 100 ns DSU t Data Input Hold Time after SCLOCK Edge 100 ns DHD t Data Output Fall Time 10 25 ns DF t Data Output Rise Time 10 25 ns DR t SCLOCK Rise Time 10 25 ns SR t SCLOCK Fall Time 10 25 ns SF tSFS SS High after SCLOCK Edge 0 ns SS t t SFS SS SCLOCK (CPOL = 0) tSH tSL tSR tSF SCLOCK (CPOL = 1) tDAV tDF tDR MISO MSB BITS 6–1 LSB MOSI t MSB ItN BITS 6–1 LSB IN 03260-0-094 DSU DHD Figure 93. SPI Slave Mode Timing (CPHA = 1) Rev. B | Page 92 of 95

Data Sheet ADuC841/ADuC842/ADuC843 Parameter SPI SLAVE MODE TIMING (CPHA = 0) Min Typ Max Unit tSS SS to SCLOCK Edge 0 ns t SCLOCK Low Pulse Width 330 ns SL t SCLOCK High Pulse Width 330 ns SH t Data Output Valid after SCLOCK Edge 50 ns DAV t Data Input Setup Time before SCLOCK Edge 100 ns DSU t Data Input Hold Time after SCLOCK Edge 100 ns DHD t Data Output Fall Time 10 25 ns DF t Data Output Rise Time 10 25 ns DR t SCLOCK Rise Time 10 25 ns SR t SCLOCK Fall Time 10 25 ns SF tDOSS Data Output Valid after SS Edge 20 ns tSFS SS High after SCLOCK Edge ns SS tSS tSFS SCLOCK (CPOL = 0) t t SH SL t t SR SF SCLOCK (CPOL = 1) t DAV t DOSS t t DF DR MISO MSB BITS 6–1 LSB MOSI MSB IN BITS 6–1 LSB IN tDSU tDHD 03260-0-095 Figure 94. SPI Slave Mode Timing (CPHA = 0) Rev. B | Page 93 of 95

ADuC841/ADuC842/ADuC843 Data Sheet OUTLINE DIMENSIONS 14.15 1.03 2.45 13.90 SQ 0.88 MAX 13.65 0.73 52 40 1.95 REF 1 39 SEATING PLANE 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9.80 2.10 2.00 0.23 1.95 0.11 13 27 0.25 7° 14 26 0.15 0° 0.10 0.10 0.38 COPLANARITY 0.22 VIEW A 0.65 BSC LEAD WIDTH LEAD PITCH ROTAVTEIEDW 90 A° CCW COMPLIANTTO JEDEC STANDARDS MO-112-AC-2 06-10-20014-B Figure 95. 52-Lead Plastic Quad Flat Package [MQFP] (S-52-2) Dimensions shown in millimeters 8.10 8.00 SQ 0.30 7.90 0.23 PIN 1 0.18 PIN 1 INDICATOR 43 56 INDICATOR 42 1 B0.S5C0 EXPPAODSED *6.25 6.10 SQ 5.95 29 14 TOP VIEW 0.50 28 BOTTOM VIEW 15 0.25 MIN 0.40 6.50 REF 0.30 0.80 FOR PROPER CONNECTION OF 0.75 0.05 MAX THE EXPOSED PAD, REFER TO 0.70 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. 0.08 SEATING 0.20 REF PKG-004356 PLANE *CWOITMHP ELXIACNETP TTOIO JNE TDOE CE XSPTOASNEDDA RPDASD MDOIM-2E2N0S-WIOLNL.D-2 08-23-2013-A Figure 96. 56-Lead Frame Chip Scale Package [LFCSP] 8 mm × 8 mm and 0.75 mm Package Height (CP-56-11) Dimensions shown in millimeters Rev. B | Page 94 of 95

Data Sheet ADuC841/ADuC842/ADuC843 ORDERING GUIDE Supply User Program Temperature Package Model1 Voltage V Code Space Range Package Description Option DD ADuC841BSZ62-5 5 62 –40°C to +85°C 52-Lead Plastic Quad Flat Package [MQFP] S-52-2 ADuC841BSZ62-3 3 62 –40°C to +85°C 52-Lead Plastic Quad Flat Package [MQFP] S-52-2 ADuC841BCPZ62-5 5 62 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 ADuC841BCPZ62-3 3 62 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 ADuC841BCPZ8-5 5 8 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 ADuC841BCPZ8-3 3 8 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 ADuC842BSZ62-5 5 62 –40°C to +85°C 52-Lead Plastic Quad Flat Package [MQFP] S-52-2 ADuC842BSZ62-3 3 62 –40°C to +85°C 52-Lead Plastic Quad Flat Package [MQFP] S-52-2 ADuC842BCPZ62-5 5 62 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 ADuC842BCPZ62-3 3 62 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 ADuC842BCPZ32-5 5 32 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 ADuC842BCPZ32-3 3 32 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 ADuC842BCPZ8-5 5 8 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 ADuC842BCPZ8-3 3 8 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 ADUC843BSZ62-5 5 62 –40°C to +85°C 52-Lead Plastic Quad Flat Package [MQFP] S-52-2 ADuC843BSZ62-3 3 62 –40°C to +85°C 52-Lead Plastic Quad Flat Package [MQFP] S-52-2 ADuC843BCP62Z-5 5 62 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 ADuC843BCPZ62-3 3 62 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 ADuC843BCP32Z-5 5 32 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 ADuC843BCPZ32-3 3 32 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 ADuC843BCPZ8-5 5 8 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 ADuC843BCPZ8-3 3 8 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 EVAL-ADuC841QSZ 5 QuickStart Development System for the ADuC841 EVAL-ADuC841QSPZ 5 QuickStart Plus Development System EVAL-ADuC842QSZ 5 QuickStart Development System for the ADuC842 and ADuC843 EVAL-ADuC842QSPZ 5 QuickStart Plus Development System USB-EA-CONVZ USB to EA Emulator 1 The only difference between the ADuC842 and ADuC843devices is the voltage output DACs on the ADuC842; thus, the evaluation system for the ADuC842 is also suitable for the ADuC843. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2003–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03260-06/17(B) Rev. B | Page 95 of 95