a MicroConverter®, Dual-Channel 16-Bit ADCs with Embedded Flash MCU ADuC816 FEATURES FUNCTIONAL BLOCK DIAGRAM High-Resolution Sigma-Delta ADCs Dual 16-Bit Independent ADCs AVDD ADuC816 AVDD Programmable Gain Front End AIN1 16-Bit No Missing Codes, Primary ADC AIN2 MUX BUF PGA 16-BPRITI M(cid:3)A-(cid:4)R AYDC CURRENT IEXC1 13-Bit p-p Resolution @ 20Hz, 20mV Range SOURCE MUX IEXC2 16-Bit p-p Resolution @ 20Hz, 2.56V Range AIN3 AGND Me8mKobryytes On-Chip Flash/EE Program Memory AAIINN54 MUX 16A-BUITX I(cid:3)L-IA(cid:4)R AYDC VOL1TD2A-ABGCIET O/P BUF DAC 640 Bytes On-Chip Flash/EE Data Memory 8051-BASED MCU WITH ADDITIONAL Flash/EE, 100Year Retention, 100Kcycles Endurance TEMP PERIPHERALS SENSOR 256 Bytes On-Chip Data RAM 8 KBYTES FLASH/EE PROGRAM MEMORY 640 BYTES FLASH/EE DATA MEMORY 8051-Based Core INTERNAL PROG. 256 BYTES USER RAM BANDGAP CLOCK 8051-Compatible Instruction Set (12.58MHz Max) VREF DIVIDER 3 (cid:2) 16 BIT ON-CHIP MONITORS TIMER/COUNTERS POWER SUPPLY 32kHz External Crystal, On-Chip Programmable PLL 1 (cid:2) TIME INTERVAL MONITOR COUNTER WATCHDOG TIMER Three 16-Bit Timer/Counters EXTERNAL OSC VREF & 4 (cid:2) PARALLEL I2C-COMPATIBLE 26 Programmable I/O Lines DETECT PLL PORTS UASRETR IAANLD I/ OSPI 11 Interrupt Sources, Two Priority Levels Power REFIN– REFIN+ XTAL1 XTAL2 Specified for 3V and 5V Operation Normal: 3mA @ 3V (Core CLK = 1.5MHz) intended for the measurement of wide dynamic range, low Power-Down: 20(cid:5)A (32kHz Crystal Running) frequency signals, such as those in weigh scale, strain gauge, On-Chip Peripherals pressure transducer, or temperature measurement applications. On-Chip Temperature Sensor The ADC output data rates are programmable and the ADC 12-Bit Voltage Output DAC output resolution will vary with the programmed gain and Dual Excitation Current Sources output rate. Reference Detect Circuit The device operates from a 32 kHz crystal with an on-chip PLL Time Interval Counter (TIC) generating a high-frequency clock of 12.58 MHz. This clock is, UART Serial I/O in turn, routed through a programmable clock divider from which I2C®-Compatible and SPI® Serial I/O the MCU core clock operating frequency is generated. The Watchdog Timer (WDT), Power Supply Monitor (PSM) microcontroller core is an 8052 and therefore 8051-instruction- set-compatible. The microcontroller core machine cycle consists APPLICATIONS of 12 core clock periods of the selected core operating frequency. Intelligent Sensors (IEEE1451.2-Compatible) 8 Kbytes of nonvolatile Flash/EE program memory are provided Weigh Scales on-chip. 640 bytes of nonvolatile Flash/EE data memory and Portable Instrumentation 256bytes RAM are also integrated on-chip. Pressure Transducers 4–20mA Transmitters The ADuC816 also incorporates additional analog functionality with a 12-bit DAC, current sources, power supply monitor, GENERAL DESCRIPTION and a bandgap reference. On-chip digital peripherals include a The ADuC816 is a complete smart transducer front-end, inte- watchdog timer, time interval counter, three timers/counters, grating two high-resolution sigma-delta ADCs, an 8-bit MCU, and three serial I/O ports (SPI, UART, and I2C-compatible). and program/data Flash/EE Memory on a single chip. This low On-chip factory firmware supports in-circuit serial download and power device accepts low-level signals directly from a transducer. debug modes (via UART), as well as single-pin emulation mode The two independent ADCs (Primary and Auxiliary) include a via the EA pin. A functional block diagram of the ADuC816 is temperature sensor and a PGA (allowing direct measurement of shown above with a more detailed block diagram shown in low-level signals). The ADCs with on-chip digital filtering are Figure 12. TThhee ppaarrtt ooppeerraatteess ffrroomm aa ssiinnggllee 33 VV oorr 55 VV ssuuppppllyy.. WWhheenn ooppeerraattiinngg MicroConverter is a registered trademark of Analog Devices, Inc. ffrroomm 33 VV ssuupppplliieess,, tthhee ppoowweerr ddiissssiippaattiioonn ffoorr tthhee ppaarrtt iiss bbeellooww SPI is a registered trademark of Motorola, Inc. 1100 mmWW.. TThhee AADDuuCC881166 iiss hhoouusseedd iinn 5a 25-2le-aleda dM MQQFPF Pan pda c5k6a-gleea.d I2C is a registered trademark of Philips Semiconductors, Inc. LFCSP packages. 0 World Wide Web Site: http:/ 3

ADuC816 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Using the Flash/EE Memory Interface . . . . . . . . . . . . . . . . . . . . 40 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Erase-All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Program a Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 USER INTERFACE TO OTHER ON-CHIP ADuC816 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . 18 PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . 19 On-Chip PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ADuC816 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Time Interval Counter (TIC) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 OVERVIEW OF MCU-RELATED SFRS . . . . . . . . . . . . . . . . . . 23 Power Supply Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Accumulator SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . . . . . . 48 B SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MISO (Master In, Slave Out Data I/O Pin), Pin 14 . . . . . . . . . 48 Stack Pointer SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MOSI (Master Out, Slave In Pin), Pin 27 . . . . . . . . . . . . . . . . . 48 Data Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SCLOCK (Serial Clock I/O Pin), Pin 26 . . . . . . . . . . . . . . . . . . 48 Program Status Word SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SS (Slave Select Input Pin), Pin 13 . . . . . . . . . . . . . . . . . . . . . . 48 Power Control SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Using the SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SPECIAL FUNCTION REGISTERS . . . . . . . . . . . . . . . . . . . . . 24 SPI Interface—Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SFR INTERFACE TO THE PRIMARY AND SPI Interface—Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 AUXILIARY ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I2C-COMPATIBLE INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . 50 8051-COMPATIBLE ON-CHIP PERIPHERALS . . . . . . . . . . . . 51 ADCSTAT (ADC Status Register) . . . . . . . . . . . . . . . . . . . . . . 25 Parallel I/O Ports 0–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ADCMODE (ADC Mode Register) . . . . . . . . . . . . . . . . . . . . . 26 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ADC0CON (Primary ADC Control Register) . . . . . . . . . . . . . . 27 TIMER/COUNTER 0 AND 1 OPERATING MODES . . . . . . . . 54 ADC1CON (Auxiliary ADC Control Register) . . . . . . . . . . . . . 28 Mode 0 (13-Bit Timer/Counter) . . . . . . . . . . . . . . . . . . . . . . . . 54 SF (Sinc Filter Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Mode 1 (16-Bit Timer/Counter) . . . . . . . . . . . . . . . . . . . . . . . . 54 ICON (Current Sources Control Register) . . . . . . . . . . . . . . . . 29 Mode 2 (8-Bit Timer/Counter with Autoreload) . . . . . . . . . . . . 54 ADC0H/ADC0M (Primary ADC Conversion Result Mode 3 (Two 8-Bit Timer/Counters) . . . . . . . . . . . . . . . . . . . . 54 Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Timer/Counter 2 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . 55 ADC1H/ADC1L (Auxiliary ADC Conversion Result TH2 and TL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 RCAP2H and RCAP2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 OF0H/OF0M (Primary ADC Offset Calibration Timer/Counter 2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . 56 Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 16-Bit Autoreload Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 OF1H/OF1L (Auxiliary ADC Offset Calibration 16-Bit Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 UART SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 GN0H/GN0M (Primary ADC Gain Calibration SBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Mode 0: 8-Bit Shift Register Mode . . . . . . . . . . . . . . . . . . . . . . 58 GN1H/GN1L (Auxiliary ADC Gain Calibration Mode 1: 8-Bit UART, Variable Baud Rate . . . . . . . . . . . . . . . . 58 Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Mode 2: 9-Bit UART with Fixed Baud Rate . . . . . . . . . . . . . . . 58 PRIMARY AND AUXILIARY ADC CIRCUIT Mode 3: 9-Bit UART with Variable Baud Rate . . . . . . . . . . . . . 58 DESCRIPTION OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . 31 UART Serial Port Baud Rate Generation . . . . . . . . . . . . . . . . . 58 Primary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Timer 1 Generated Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . 59 Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Timer 2 Generated Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . 59 PRIMARY AND AUXILIARY ADC NOISE INTERRUPT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 ADuC816 HARDWARE DESIGN CONSIDERATIONS . . . . . . 62 Primary and Auxiliary ADC Inputs . . . . . . . . . . . . . . . . . . . . . . 33 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Analog Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Bipolar/Unipolar Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Burnout Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Excitation Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Power-Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Grounding and Board Layout Recommendations . . . . . . . . . . . 64 Reference Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ADuC816 System Self-Identification . . . . . . . . . . . . . . . . . . . . . 65 Sigma-Delta Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 OTHER HARDWARE CONSIDERATIONS . . . . . . . . . . . . . . . 65 Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 In-Circuit Serial Download Access . . . . . . . . . . . . . . . . . . . . . . 65 ADC Chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Embedded Serial Port Debugger . . . . . . . . . . . . . . . . . . . . . . . . 65 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Single-Pin Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 NONVOLATILE FLASH/EE MEMORY . . . . . . . . . . . . . . . . . . 37 Enhanced-Hooks Emulation Mode . . . . . . . . . . . . . . . . . . . . . . 66 Flash/EE Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Typical System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Flash/EE Memory and the ADuC816 . . . . . . . . . . . . . . . . . . . . 37 QUICKSTART DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . 67 ADuC816 Flash/EE Memory Reliability . . . . . . . . . . . . . . . . . . 37 Download—In-Circuit Serial Downloader . . . . . . . . . . . . . . . . . 67 Using the Flash/EE Program Memory . . . . . . . . . . . . . . . . . . . . 38 DeBug—In-Circuit Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Flash/EE Program Memory Security . . . . . . . . . . . . . . . . . . . . . 38 ADSIM—Windows Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Using the Flash/EE Data Memory . . . . . . . . . . . . . . . . . . . . . . . 39 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ECON–Flash/EE Memory Control SFR . . . . . . . . . . . . . . . . . . 39 Flash/EE Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 –2– Rev. B

ADuC816 SPECIFICATIONS1 (AV = 2.7V to 3.6V or 4.75V to 5.25V, DV = 2.7V to 3.6V or 4.75V to 5.25V, DD DD REFIN(+) = 2.5V; REFIN(–) = AGND; AGND = DGND = 0V; XTAL1/XTAL2 = 32.768kHz Crystal; all specifications T to T unless otherwise noted.) MIN MAX Parameter ADuC816BS Unit Test Conditions/Comments ADC SPECIFICATIONS Conversion Rate 5.4 Hz min On Both Channels 105 Hz max Programmable in 0.732ms Increments Primary ADC No Missing Codes2 16 Bits min 20Hz Update Rate Resolution 13 Bits p-p typ Range = ±20mV, 20Hz Update Rate 16 Bits p-p typ Range = ±2.56V, 20Hz Update Rate p-p Resolution at this Range/Update Rate Setting Is Limited Only by the Number of Bits Available from ADC Output Noise See Table IX and X Output Noise Varies with Selected in ADC Description Update Rate and Gain Range Integral Nonlinearity ±1 LSB max Offset Error ±3 μV typ Offset Error Drift ±10 nV/°C typ Full-Scale Error3 ±10 μV typ Range = ±20 mV to ±640 mV 0.5 LSB typ Range = ±1.28 V to ±2.56 V Gain Error Drift4 ±0.5 ppm/°C typ ADC Range Matching ±0.5 LSB typ AIN = 18mV Power Supply Rejection (PSR) 95 dBs typ AIN = 7.8mV, Range = ±20mV 80 dBs typ AIN = 1V, Range = ±2.56V Common-Mode DC Rejection On AIN 95 dBs typ At DC, AIN = 7.8mV, Range = ±20mV 90 dBs typ At DC, AIN = 1V, Range = ±2.56V On REFIN 90 dBs typ At DC, AIN = 1V, Range = ±2.56V Common-Mode 50Hz/60Hz Rejection2 20Hz Update Rate On AIN 95 dBs typ 50Hz/60Hz ±1Hz, AIN = 7.8mV, Range = ±20mV 90 dBs typ 50Hz/60Hz ±1Hz, AIN = 1V, Range = ±2.56V On REFIN 90 dBs typ 50Hz/60Hz ±1Hz, AIN = 1V, Range = ±2.56V Normal Mode 50Hz/60Hz Rejection2 On AIN 60 dBs typ 50Hz/60Hz ±1Hz, 20Hz Update Rate On REFIN 60 dBs typ 50Hz/60Hz ±1Hz, 20Hz Update Rate Auxiliary ADC No Missing Codes2 16 Bits min Resolution 16 Bits p-p typ Range = ±2.5V, 20Hz Update Rate Output Noise See Table XI Output Noise Varies with Selected in ADC Description Update Rate Integral Nonlinearity ±1 LSB max Offset Error –2 LSB typ Offset Error Drift 1 μV/°C typ Full-Scale Error5 –2.5 LSB typ Gain Error Drift4 ±0.5 ppm/°C typ Power Supply Rejection (PSR) 80 dBs typ AIN = 1V, 20Hz Update Rate Normal Mode 50Hz/60Hz Rejection2 On AIN 60 dBs typ 50Hz/60Hz ±1Hz On REFIN 60 dBs typ 50Hz/60Hz ±1Hz, 20Hz Update Rate DAC PERFORMANCE DC Specifications6 Resolution 12 Bits Relative Accuracy ±3 LSB typ Differential Nonlinearity –1 LSB max Guaranteed 12-Bit Monotonic Offset Error ±50 mV max Gain Error7 ±1 % max AV Range DD ±1 % typ V Range REF AC Specifications2, 6 Voltage Output Settling Time 15 μs typ Settling Time to 1 LSB of Final Value Digital-to-Analog Glitch Energy 10 nVs typ 1 LSB Change at Major Carry Rev. B –3–

ADuC816–SPECIFICATIONS1 Parameter ADuC816BS Unit Test Conditions/Comments INTERNAL REFERENCE ADC Reference Reference Voltage 1.25 ± 1% V min/max Initial Tolerance @ 25°C, V = 5V DD Power Supply Rejection 45 dBs typ Reference Tempco 100 ppm/°C typ DAC Reference Reference Voltage 2.5 ± 1% V min/max Initial Tolerance @ 25°C, V = 5V DD Power Supply Rejection 50 dBs typ Reference Tempco ±100 ppm/°C typ ANALOG INPUTS/REFERENCE INPUTS Primary ADC Differential Input Voltage Ranges8, 9 External Reference Voltage = 2.5V RN2, RN1, RN0 of ADC0CON Set to Bipolar Mode (ADC0CON.3 = 0) ±20 mV 000 (Unipolar Mode 0 mV to 20mV) ±40 mV 001 (Unipolar Mode 0 mV to 40mV) ±80 mV 010 (Unipolar Mode 0 mV to 80mV) ±160 mV 011 (Unipolar Mode 0 mV to 160mV) ±320 mV 100 (Unipolar Mode 0 mV to 320mV) ±640 mV 101 (Unipolar Mode 0 mV to 640mV) ±1.28 V 110 (Unipolar Mode 0 V to 1.28V) ±2.56 V 111 (Unipolar Mode 0 V to 2.56V) Analog Input Current2 ±1 nA max Analog Input Current Drift ±5 pA/°C typ Absolute AIN Voltage Limits AGND + 100mV V min AV – 100mV V max DD Auxiliary ADC Input Voltage Range8, 9 0 to V V Unipolar Mode, for Bipolar Mode REF See Note 11 Average Analog Input Current 125 nA/V typ Input Current Will Vary with Input Average Analog Input Current Drift2 ±2 pA/V/°C typ Voltage on the Unbuffered Auxiliary ADC Absolute AIN Voltage Limits10 AGND – 30mV V min AV + 30mV V max DD External Reference Inputs REFIN(+) to REFIN(–) Range2 1 V min AV V max DD Average Reference Input Current 1 μA/V typ Both ADCs Enabled Average Reference Input Current Drift ±0.1 nA/V/°C typ “NO Ext. REF” Trigger Voltage 0.3 V min NOXREF Bit Active if V < 0.3V REF 0.65 V max NOXREF Bit Inactive if V > 0.65V REF ADC SYSTEM CALIBRATION Full-Scale Calibration Limit +1.05 × FS V max Zero-Scale Calibration Limit –1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max ANALOG (DAC) OUTPUTS Voltage Range 0 to V V typ DACRN = 0 in DACCON SFR REF 0 to AV V typ DACRN = 1 in DACCON SFR DD Resistive Load 10 kΩ typ From DAC Output to AGND Capacitive Load 100 pF typ From DAC Output to AGND Output Impedance 0.5 Ω typ I 50 μA typ SINK TEMPERATURE SENSOR Accuracy ±2 °C typ Thermal Impedance (θ ) 90 °C/W typ JA –4– Rev. B

ADuC816 Parameter ADuC816BS Unit Test Conditions/Comments TRANSDUCER BURNOUT CURRENT SOURCES AIN+ Current –100 nA typ AIN+ is the Selected Positive Input to the Primary ADC AIN– Current +100 nA typ AIN– is the Selected Negative Input the Auxiliary ADC Initial Tolerance @ 25°C Drift ±10 % typ Drift 0.03 %/°C typ EXCITATION CURRENT SOURCES Output Current –200 μA typ Available from Each Current Source Initial Tolerance @ 25°C ±10 % typ Drift 200 ppm/°C typ Initial Current Matching @ 25°C ±1 % typ Matching Between Both Current Sources Drift Matching 20 ppm/°C typ Line Regulation (AV ) 1 μA/V typ AV = 5V + 5% DD DD Load Regulation 0.1 μA/V typ Output Compliance AV – 0.6 V max DD AGND min LOGIC INPUTS All Inputs Except SCLOCK, RESET, and XTAL1 V , Input Low Voltage 0.8 V max DV = 5V INL DD 0.4 V max DV = 3V DD V , Input High Voltage 2.0 V min INH SCLOCK and RESET Only (Schmitt-Triggered Inputs)2 V 1.3/3 V min/V max DV = 5V T+ DD 0.95/2.5 V min/V max DV = 3V DD V 0.8/1.4 V min/V max DV = 5V T– DD 0.4/1.1 V min/V max DV = 3V DD V – V 0.3/0.85 V min/V max DV = 5V T+ T– DD 0.3/0.85 V min/V max DV = 3V DD Input Currents Port 0, P1.2–P1.7, EA ±10 μA max V = 0V or V IN DD SCLOCK, SDATA/MOSI, MISO, SS11 –10 min, –40 max μA min/μA max V = 0V, DV = 5V, Internal Pull-Up IN DD ±10 μA max V = V , DV = 5V IN DD DD RESET ±10 μA max V = 0V, DV = 5V IN DD 35 min, 105 max μA min/μA max V = V , DV = 5V, IN DD DD Internal Pull-Down P1.0, P1.1, Ports 2 and 3 ±10 μA max V = V , DV = 5V IN DD DD –180 μA min V = 2V, DV = 5V IN DD –660 μA max –20 μA min V = 450mV, DV = 5V IN DD –75 μA max Input Capacitance 5 pF typ All Digital Inputs CRYSTAL OSCILLATOR (XTAL1 AND XTAL2) Logic Inputs, XTAL1 Only V , Input Low Voltage 0.8 V max DV = 5V INL DD 0.4 V max DV = 3V DD V , Input High Voltage 3.5 V min DV = 5V INH DD 2.5 V min DV = 3V DD XTAL1 Input Capacitance 18 pF typ XTAL2 Output Capacitance 18 pF typ Rev. B –5–

ADuC816–SPECIFICATIONS1 Parameter ADuC816BS Unit Test Conditions/Comments LOGIC OUTPUTS (Not Including XTAL2)2 V , Output High Voltage 2.4 V min V = 5V, I = 80μA OH DD SOURCE 2.4 V min V = 3V, I = 20μA DD SOURCE V , Output Low Voltage12 0.4 V max I = 8mA, SCLOCK, SDATA/MOSI OL SINK 0.4 V max I = 10mA, P1.0 and P1.1 SINK 0.4 V I = 1.6mA, All Other Outputs max SINK Floating State Leakage Current ±10 μA max Floating State Output Capacitance 5 pF typ POWER SUPPLY MONITOR (PSM) AV Trip Point Selection Range 2.63 V min Four Trip Points Selectable in This Range DD 4.63 V max Programmed via TPA1–0 in PSMCON AV Power Supply Trip Point Accuracy ±3.5 % max DD DV Trip Point Selection Range 2.63 V min Four Trip Points Selectable in This Range DD 4.63 V max Programmed via TPD1–0 in PSMCON DV Power Supply Trip Point Accuracy ±3.5 % max DD WATCHDOG TIMER (WDT) Timeout Period 0 ms min Nine Timeout Periods in This Range 2000 ms max Programmed via PRE3–0 in WDCON MCU CORE CLOCK RATE Clock Rate Generated via On-Chip PLL MCU Clock Rate2 98.3 kHz min Programmable via CD2–0 Bits in PLLCON SFR 12.58 MHz max START-UP TIME At Power-On 300 ms typ From Idle Mode 1 ms typ From Power-Down Mode Oscillator Running OSC_PD Bit = 0 in PLLCON SFR Wake Up with INT0 Interrupt 1 ms typ Wake Up with SPI/I2C Interrupt 1 ms typ Wake Up with TIC Interrupt 1 ms typ Wake Up with External RESET 3.4 ms typ Oscillator Powered Down OSC_PD Bit = 1 in PLLCON SFR Wake Up with External RESET 0.9 sec typ After External RESET in Normal Mode 3.3 ms typ After WDT Reset in Normal Mode 3.3 ms typ Controlled via WDCON SFR FLASH/EE MEMORY RELIABILITY CHARACTERISTICS13 Endurance14 100,000 Cycles min Data Retention15 100 Years min POWER REQUIREMENTS DV and AV Can Be Set DD DD Independently Power Supply Voltage AV , 3V Nominal Operation 2.7 V min DD 3.6 V max AV , 5V Nominal Operation 4.75 V min DD 5.25 V max DV , 3V Nominal Operation 2.7 V min DD 3.6 V max DV , 5 V Nominal Operation 4.75 V min DD 5.25 V max –6– Rev. B

ADuC816 Parameter ADuC816BS Unit Test Conditions/Comments POWER REQUIREMENTS (continued) Power Supply Currents Normal Mode16, 17 DV Current 4 mA max DV = 4.75V to 5.25V, Core CLK = 1.57MHz DD DD 2.1 mA max DV = 2.7V to 3.6V, Core CLK = 1.57MHz DD AV Current 170 μA max AV = 5.25V, Core CLK = 1.57MHz DD DD DV Current 15 mA max DV = 4.75V to 5.25V, Core CLK = 12.58MHz DD DD 8 mA max DV = 2.7V to 3.6V, Core CLK = 12.58MHz DD AV Current 170 μA max AV = 5.25V, Core CLK = 12.58MHz DD DD Power Supply Currents Idle Mode16, 17 DV Current 1.2 mA max DV = 4.75V to 5.25V, Core CLK = 1.57MHz DD DD 750 μA typ DV = 2.7V to 3.6V, Core CLK = 1.57MHz DD AV Current 140 μA typ Measured @ AV = 5.25V, Core CLK = 1.57MHz DD DD DV Current 2 mA typ DV = 4.75V to 5.25V, Core CLK = 12.58MHz DD DD 1 mA typ DV = 2.7V to 3.6V, Core CLK = 12.58MHz DD AV Current 140 μA typ Measured at AV = 5.25V, Core CLK = 12.58MHz DD DD Power Supply Currents Power-Down Mode16, 17 Core CLK = 1.57MHz or 12.58MHz DV Current 50 μA max DV = 4.75V to 5.25V, Osc. On, TIC On DD DD 20 μA max DV = 2.7V to 3.6V, Osc. On, TIC On DD AV Current 1 μA max Measured at AV = 5.25V, Osc. On or Osc. Off DD DD DV Current 20 μA max DV = 4.75V to 5.25V, Osc. Off DD DD 5 μA typ DV = 2.7V to 3.6V, Osc. Off DD Typical Additional Power Supply Currents Core CLK = 1.57MHz, AV = DV = 5V DD DD (AI and DI ) DD DD PSM Peripheral 50 μA typ Primary ADC 1 mA typ Auxiliary ADC 500 μA typ DAC 150 μA typ Dual Current Sources 400 μA typ NOTES 1Temperature Range –40°C to +85°C. 2These numbers are not production tested but are guaranteed by Design and/or Characterization data on production release. 3The primary ADC is factory-calibrated at 25°C with AV = DV = 5 V yielding this full-scale error. If user power supply or temperature conditions are signifi- DD DD cantly different from these, an Internal Full-Scale Calibration will restore this error to this level. 4Gain Error Drift is a span drift. To calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input. 5The auxiliary ADC is factory-calibrated at 25°C with AV = DV = 5 V yielding this full-scale error of –2.5 LSB. A system zero-scale and full-scale calibration DD DD will remove this error altogether. 6DAC linearity and AC Specifications are calculated using: reduced code range of 48 to 4095, 0 to V REF reduced code range of 48 to 3995, 0 to V . DD 7Gain Error is a measure of the span error of the DAC. 8In general terms, the bipolar input voltage range to the primary ADC is given by Range = ±(V 2RN)/125, where: ADC REF V = REFIN(+) to REFIN(–) voltage and V = 1.25 V when internal ADC V is selected. REF REF REF RN = decimal equivalent of RN2, RN1, RN0, e.g., V = 2.5 V and RN2, RN1, RN0 = 1, 1, 0 the Range = ±1.28 V. REF ADC In unipolar mode the effective range is 0V to 1.28 V in our example. 91.25 V is used as the reference voltage to the ADC when internal V is selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON respectively. REF 10In bipolar mode, the Auxiliary ADC can only be driven to a minimum of A – 30 mV as indicated by the Auxiliary ADC absolute AIN voltage limits. The bipolar GND range is still –V to +V ; however, the negative voltage is limited to –30 mV. REF REF 11Pins configured in I2C-compatible mode or SPI mode, pins configured as digital inputs during this test. 12Pins configured in I2C-compatible mode only. 13Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory. 14Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40°C, +25°C and +85°C, typical endurance at 25°C is 700 Kcycles. 15Retention lifetime equivalent at junction temperature (T) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV J will derate with junction temperature as shown in Figure 27 in the Flash/EE Memory description section of this data sheet. 16Power Supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions: Normal Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop. Idle Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode. Power-Down Mode: Reset = 0.4 V, All P0 pins and P1.2–P1.7 pins = 0.4 V, All other digital I/O pins are open circuit, Core Clk changed via CD bits in PLLCON, PCON.1 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR. 17DV power supply current will typically increase by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle. DD Specifications subject to change without notice Rev. B –7–

ADuC816 TIMING SPECIFICATIONS1, 2, 3 (AVDD = 2.7V to 3.6V or 4.75V to 5.25V, DVDD = 2.7V to 3.6V or 4.75V to 5.25V; all specifications T to T unless otherwise noted.) MIN MAX 32.768kHz External Crystal Parameter Min Typ Max Unit Figure CLOCK INPUT (External Clock Driven XTAL1) t XTAL1 Period 30.52 μs 1 CK t XTAL1 Width Low 15.16 μs 1 CKL t XTAL1 Width High 15.16 μs 1 CKH t XTAL1 Rise Time 20 ns 1 CKR t XTAL1 Fall Time 20 ns 1 CKF 1/t ADuC816 Core Clock Frequency4 0.098 12.58 MHz CORE t ADuC816 Core Clock Period5 0.636 μs CORE t ADuC816 Machine Cycle Time6 0.95 7.6 122.45 μs CYC NOTES 1AC inputs during testing are driven at DV – 0.5V for a Logic 1, and 0.45V for a Logic 0. Timing measurements are made at V min for a Logic 1, and V max DD IH IL for a Logic 0 as shown in Figure 2. 2For timing purposes, a port pin is no longer floating when a 100mV change from load voltage occurs. A port pin begins to float when a 100mV change from the loaded V /V level occurs as shown in Figure 2. OH OL 3C for Port0, ALE, PSEN outputs = 100pF; C for all other outputs = 80pF unless otherwise noted. LOAD LOAD 4ADuC816 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a Stable 12.583 MHz internal clock for the system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR. 5This number is measured at the default Core_Clk operating frequency of 1.57MHz. 6ADuC816 Machine Cycle Time is nominally defined as 12/Core_CLK. Specifications subject to change without notice. tCHK tCKR t t CKL CKF t CK Figure 1.XTAL1 Input DVDD – 0.5V 0.2DVDD + 0.9V VLOAD – 0.1V TIMING VLOAD – 0.1V TEST POINTS VLOAD REFERENCE VLOAD 0.45V 0.2DVDD – 0.1V VLOAD + 0.1V POINTS VLOAD + 0.1V Figure 2.Timing Waveform Characteristics –8– Rev. B

ADuC816 12.58MHz Core_Clk Variable Core_Clk Parameter Min Max Min Max Unit Figure EXTERNAL PROGRAM MEMORY t ALE Pulsewidth 119 2t – 40 ns 3 LHLL CORE t Address Valid to ALE Low 39 t – 40 ns 3 AVLL CORE t Address Hold after ALE Low 49 t – 30 ns 3 LLAX CORE t ALE Low to Valid Instruction In 218 4t – 100 ns 3 LLIV CORE t ALE Low to PSEN Low 49 t – 30 ns 3 LLPL CORE t PSEN Pulsewidth 193 3t – 45 ns 3 PLPH CORE t PSEN Low to Valid Instruction In 133 3t – 105 ns 3 PLIV CORE t Input Instruction Hold after PSEN 0 0 ns 3 PXIX t Input Instruction Float after PSEN 54 t – 25 ns 3 PXIZ CORE t Address to Valid Instruction In 292 5t – 105 ns 3 AVIV CORE t PSEN Low to Address Float 25 25 ns 3 PLAZ t Address Hold after PSEN High 0 0 ns 3 PHAX CORE_CLK t LHLL ALE (O) tAVLL tLLPL tPLPH t LLIV t PLIV PSEN (O) t t PXIZ t PLAZ LLAX t PXIX PORT 0 (I/O) (OPCULT) INSTR(IUNC)TION t AVIV t PHAX PORT 2 (O) PCH Figure 3.External Program Memory Read Cycle Rev. B –9–

ADuC816 12.58MHz Core_Clk Variable Core_Clk Parameter Min Max Min Max Unit Figure EXTERNAL DATA MEMORY READ CYCLE t RD Pulsewidth 377 6t – 100 ns 4 RLRH CORE t Address Valid after ALE Low 39 t – 40 ns 4 AVLL CORE t Address Hold after ALE Low 44 t – 35 ns 4 LLAX CORE t RD Low to Valid Data In 232 5t – 165 ns 4 RLDV CORE t Data and Address Hold after RD 0 0 ns 4 RHDX t Data Float after RD 89 2t – 70 ns 4 RHDZ CORE t ALE Low to Valid Data In 486 8t – 150 ns 4 LLDV CORE t Address to Valid Data In 550 9t – 165 ns 4 AVDV CORE t ALE Low to RD Low 188 288 3t – 50 3t + 50 ns 4 LLWL CORE CORE t Address Valid to RD Low 188 4t – 130 ns 4 AVWL CORE t RD Low to Address Float 0 0 ns 4 RLAZ t RD High to ALE High 39 119 t – 40 t + 40 ns 4 WHLH CORE CORE CORE_CLK ALE (O) t WHLH PSEN (O) t LLDV t t LLWL RLRH RD (O) t AVWL t RLDV t t tLLAX tRHDX RHDZ AVLL t RLAZ A0 – A7 PORT 0 (I/O) (OUT) DATA (IN) t AVDV PORT 2 (O) A16 – A23 A8 – A15 Figure 4. External Data Memory Read Cycle –10– Rev. B

ADuC816 12.58MHz Core_Clk Variable Core_Clk Parameter Min Max Min Max Unit Figure EXTERNAL DATA MEMORY WRITE CYCLE t WR Pulsewidth 377 6t – 100 ns 5 WLWH CORE t Address Valid after ALE Low 39 t – 40 ns 5 AVLL CORE t Address Hold after ALE Low 44 t – 35 ns 5 LLAX CORE t ALE Low to WR Low 188 288 3t – 50 3t + 50 ns 5 LLWL CORE CORE t Address Valid to WR Low 188 4t – 130 ns 5 AVWL CORE t Data Valid to WR Transition 29 t – 50 ns 5 QVWX CORE t Data Setup before WR 406 7t – 150 ns 5 QVWH CORE t Data and Address Hold after WR 29 t – 50 ns 5 WHQX CORE t WR High to ALE High 39 119 t – 40 t + 40 ns 5 WHLH CORE CORE CORE_CLK ALE (O) t WHLH PSEN (O) t t LLWL WLWH WR (O) t AVWL t t t QVWX WHQX t LLAX AVLL t QVWH PORT 0 (O) A0 – A7 DATA PORT 2 (O) A16 – A23 A8 – A15 Figure 5.External Data Memory Write Cycle Rev. B –11–

ADuC816 12.58MHz Core_Clk Variable Core_Clk Parameter Min Typ Max Min Typ Max Unit Figure UART TIMING (Shift Register Mode) t Serial Port Clock Cycle Time 0.95 2t μs 6 XLXL CORE t Output Data Setup to Clock 662 10t – 133 ns 6 QVXH CORE t Input Data Setup to Clock 292 2t + 133 ns 6 DVXH CORE t Input Data Hold after Clock 0 0 ns XHDX t Output Data Hold after Clock 42 2t – 117 ns 6 XHQX CORE ALE (O) t XLXL TXD 01 67 (OUTPUT CLOCK) t SET RI QVXH OR t SET TI XHQX RXD MSB BIT 6 BIT 1 (OUTPUT DATA) t t DVXH XHDX RXD (INPUT DATA) MSB BIT 6 BIT 1 LSB Figure 6.UART Timing in Shift Register Mode –12– Rev. B

ADuC816 Parameter Min Max Unit Figure I2C-COMPATIBLE INTERFACE TIMING t SCLOCK Low Pulsewidth 4.7 μs 7 L t SCLOCK High Pulsewidth 4.0 μs 7 H t Start Condition Hold Time 0.6 μs 7 SHD t Data Setup Time 100 μs 7 DSU t Data Hold Time 0.9 μs 7 DHD t Setup Time for Repeated Start 0.6 μs 7 RSU t Stop Condition Setup Time 0.6 μs 7 PSU t Bus Free Time between a STOP 1.3 μs 7 BUF Condition and a START Condition t Rise Time of Both SCLOCK and SDATA 300 ns 7 R t Fall Time of Both SCLOCK and SDATA 300 ns 7 F t * Pulsewidth of Spike Suppressed 50 ns 7 SUP *Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50ns. t BUF t SUP t R SDATA (I/O) MSB LSB ACK MSB tDSU t tDSU t tF DHD DHD t tPSU tSHD tH tRSU R SCLK (I) 1 2-7 8 9 1 PS t S(R) t STOP START tL SUP REPEATED F CONDITION CONDITION START Figure 7.I2C-Compatible Interface Timing Rev. B –13–

ADuC816 Parameter Min Typ Max Unit Figure SPI MASTER MODE TIMING (CPHA = 1) t SCLOCK Low Pulsewidth* 630 ns 8 SL t SCLOCK High Pulsewidth* 630 ns 8 SH t Data Output Valid after SCLOCK Edge 50 ns 8 DAV t Data Input Setup Time before SCLOCK Edge 100 ns 8 DSU t Data Input Hold Time after SCLOCK Edge 100 ns 8 DHD t Data Output Fall Time 10 25 ns 8 DF t Data Output Rise Time 10 25 ns 8 DR t SCLOCK Rise Time 10 25 ns 8 SR t SCLOCK Fall Time 10 25 ns 8 SF *Characterized under the following conditions: a.Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1 respectively, i.e., core clock frequency = 1.57 MHz and b.SPI bit-rate selection bits SPR1 and SPR0 bits in SPICON SFR set to 0 and 0 respectively. SCLOCK (CPOL = 0) t t SH SL t t SCLOCK SR SF (CPOL = 1) tDAV tDF tDR MOSI MSB BITS 6 – 1 LSB MISO MSB IN BITS 6 – 1 LSB IN t t DSU DHD Figure 8.SPI Master Mode Timing (CPHA = 1) –14– Rev. B

ADuC816 Parameter Min Typ Max Unit Figure SPI MASTER MODE TIMING (CPHA = 0) t SCLOCK Low Pulsewidth* 630 ns 9 SL t SCLOCK High Pulsewidth* 630 ns 9 SH t Data Output Valid after SCLOCK Edge 50 ns 9 DAV t Data Output Setup before SCLOCK Edge 150 ns 9 DOSU t Data Input Setup Time before SCLOCK Edge 100 ns 9 DSU t Data Input Hold Time after SCLOCK Edge 100 ns 9 DHD t Data Output Fall Time 10 25 ns 9 DF t Data Output Rise Time 10 25 ns 9 DR t SCLOCK Rise Time 10 25 ns 9 SR t SCLOCK Fall Time 10 25 ns 9 SF *Characterized under the following conditions: a.Core clock divider bits CD2, CD1 and CD0 bits in PLLCON SFR set to 0, 1, and 1 respectively, i.e., core clock frequency = 1.57 MHz and b.SPI bit-rate selection bits SPR1 and SPR0 bits in SPICON SFR set to 0 and 0 respectively. SCLOCK (CPOL = 0) t t SH SL t t SCLOCK SR SF (CPOL = 1) t DAV t t t DOSU DF DR MOSI MSB BITS 6 – 1 LSB MISO MSB IN BITS 6 – 1 LSB IN t t DSU DHD Figure 9.SPI Master Mode Timing (CPHA = 0) Rev. B –15–

ADuC816 Parameter Min Typ Max Unit Figure SPI SLAVE MODE TIMING (CPHA = 1) t SS to SCLOCK Edge 0 ns 10 SS t SCLOCK Low Pulsewidth 330 ns 10 SL t SCLOCK High Pulsewidth 330 ns 10 SH t Data Output Valid after SCLOCK Edge 50 ns 10 DAV t Data Input Setup Time before SCLOCK Edge 100 ns 10 DSU t Data Input Hold Time after SCLOCK Edge 100 ns 10 DHD t Data Output Fall Time 10 25 ns 10 DF t Data Output Rise Time 10 25 ns 10 DR t SCLOCK Rise Time 10 25 ns 10 SR t SCLOCK Fall Time 10 25 ns 10 SF t SS High after SCLOCK Edge 0 ns 10 SFS SS t t SS SFS t SCLOCK DF (CPOL = 0) tSH tSL tSR tSF SCLOCK (CPOL = 1) tDAV tDF tDR MISO MSB BITS 6 – 1 LSB MOSI MSB IN BITS 6 – 1 LSB IN tDSU tDHD Figure 10.SPI Slave Mode Timing (CPHA = 1) –16– Rev. B

ADuC816 Parameter Min Typ Max Unit Figure SPI SLAVE MODE TIMING (CPHA = 0) t SS to SCLOCK Edge 0 ns 11 SS t SCLOCK Low Pulsewidth 330 ns 11 SL t SCLOCK High Pulsewidth 330 ns 11 SH t Data Output Valid after SCLOCK Edge 50 ns 11 DAV t Data Input Setup Time before SCLOCK Edge 100 ns 11 DSU t Data Input Hold Time after SCLOCK Edge 100 ns 11 DHD t Data Output Fall Time 10 25 ns 11 DF t Data Output Rise Time 10 25 ns 11 DR t SCLOCK Rise Time 10 25 ns 11 SR t SCLOCK Fall Time 10 25 ns 11 SF t SS to SCLOCK Edge 50 ns 11 SSR t Data Output Valid after SS Edge 20 ns 11 DOSS t SS High after SCLOCK Edge 0 ns 11 SFS SS tSS tSFS SCLOCK (CPOL = 0) t t SH SL t t SR SF SCLOCK (CPOL = 1) t DAV t DOSS t t DF DR MISO MSB BITS 6 – 1 LSB MOSI MSB IN BITS 6 – 1 LSB IN t t DSU DHD Figure 11.SPI Slave Mode Timing (CPHA = 0) Rev. B –17–

ADuC816 ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted) A Stresses above those listed under Absolute Maximum Ratings Parameter Ratings may cause permanent damage to the device. This is a stress AV to AGND −0.3 V to +7 V DD rating only; functional operation of the device at these or any AV to DGND −0.3 V to +7 V DD other conditions above those listed in the operational sections DV to AGND −0.3 V to +7 V DD of this specification is not implied. Exposure to absolute DV to DGND −0.3 V to +7 V DD maximum rating conditions for extended periods may affect AGND to DGND1 −0.3 V to +0.3 V device reliability. AV to DV −2 V to +5 V DD DD Analog Input Voltage to AGND2 −0.3 V to AV +0.3 V DD Reference Input Voltage to AGND −0.3 V to AV +0.3 V DD AIN/REFIN Current (Indefinite) 30 mA Digital Input Voltage to DGND −0.3 V to DV +0.3 V DD Digital Output Voltage to DGND −0.3 V to DV +0.3 V DD Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C (cid:537) Thermal Impedance (MQFP) 90°C/W JA (cid:537) Thermal Impedance (LFCSP 52°C/W JA Base Floating) Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 AGND and DGND are shorted internally on the ADuC816. 2 Applies to P1.2 to P1.7 pins operating in analog or digital input modes. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –18– Rev. B

ADuC816 PIN FUNCTION DESCRIPTIONS 52 40 1 39 56 43 PIN 1 1 PIN 1 42 INDICATOR ADuC816 ADuC816 TOP VIEW (Not to Scale) TOP VIEW (Not to Scale) 14 29 15 28 13 14 26 27 00436-001 N1 . O TUTHNEECS OENXPNOECSTEEDDP.ADDLE MUST BE LEFT00436-002 56-Lead MQFP 56-Lead LFCSP PIN FUNCTION DESCRIPTIONS Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic Type1 Description 1, 2 56, 1 P1.0/P1.1 I/O P1.0 and P1.1 can function as digital inputs or digital outputs and have a pull-up configuration as described for Port 3. P1.0 and P1.1 have an increased current drive sink capability of 10 mA. P1.0/T2 I/O P1.0 and P1.1 also have various secondary functions as described below. P1.0 can be used to provide a clock input to Timer 2. When enabled, Counter 2 is incremented in response to a negative transition on the T2 input pin. P1.1/T2EX I/O P1.1 can also be used to provide a control input to Timer 2.When enabled, a negative transition on the T2EX input pin will cause a Timer 2 capture or reload event. 3–4, 2–3, P1.2–P1.7 I Port 1.2 to Port 1.7 have no digital output driver; they can function as a digital input 9–12 11–14 P1.2/DAC/IEXC1 I/O for which 0 must be written to the port bit. As a digital input, these pins must be driven high or low externally. These pins also have the following analog functionality: The voltage output from the DAC or one or both current sources (200 µA or 2 × 200 µA) can be configured to appear at this pin. P1.3/AIN5/IEXC2 I/O Auxiliary ADC input or one or both current sources can be configured at this pin. P1.4/AIN1 I Primary ADC, Positive Analog Input P1.5/AIN2 I Primary ADC, Negative Analog Input P1.6/AIN3 I Auxiliary ADC Input or Muxed Primary ADC, Positive Analog Input P1.7/AIN4/DAC I/O Auxiliary ADC Input or Muxed Primary ADC, Negative Analog Input. The voltage output from the DAC can also be configured to appear at this pin. 5 4, 5 AVDD S Analog Supply Voltage, 3 V or 5 V 6 6, 7, 8 AGND S Analog Ground. Ground reference pin for the analog circuitry. 7 9 REFIN(–) I Reference Input, Negative Terminal 8 10 REFIN(+) I Reference Input, Positive Terminal 13 15 SS I Slave Select Input for the SPI Interface. A weak pull-up is present on this pin. 14 16 MISO I/O Master Input/Slave Output for the SPI Interface. A weak pull-up is present on this input pin 15 17 RESET I Reset Input. A high level on this pin for 16 core clock cycles while the oscillator is running resets the device. There is an internal weak pull-down and a Schmitt trigger input stage on this pin. 16–19, 18–21, P3.0–P3.7 I/O P3.0–P3.7 are bidirectional port pins with internal pull-up resistors. Port 3 pins that 22–25 24–27 P3.0/RXD I/O have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low will source current because of the internal pull-up resistors.When driving a 0-to-1 output transition, a strong pull-up is active for two core clock periods of the instruction cycle. Port 3 pins also have various secondary functions including: Receiver Data for UART Serial Port P3.1/TXD I/O Transmitter Data for UART Serial Port P3.2/INT0 I/O External Interrupt 0.This pin can also be used as a gate control input to Timer 0. P3.3/INT1 I/O External Interrupt 1.This pin can also be used as a gate control input to Timer 1. P3.4/T0 I/O Timer/Counter 0 External Input. P3.5/T1 I/O Timer/Counter 1 External Input P3.6/WR I/O External Data Memory Write Strobe. Latches the data byte from Port 0 into an external data memory. P3.7/RD I/O External Data Memory Read Strobe. Enables the data from an external data memory to Port 0. –19– Rev. B

ADuC816 Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic Type1 Description 20, 34, 48 22, 36, 51, DVDD S Digital Supply, 3 V or 5 V 21, 35, 47 23, 37, 38, 50 DGND S Digital Ground. Ground reference point for the digital circuitry. 26 SCLOCK I/O Serial Interface Clock for either the I2C or SPI Interface. As an input, this pin is a Schmitt-triggered input, and a weak internal pull-up is present on this pin unless it is outputting logic low. This pin can also be directly controlled in software as a digital output pin. 27 MOSI/SDATA I/O Serial Data I/O for the I2C Interface or Master Output/Slave Input for the SPI Interface. A weak internal pull-up is present on this pin unless it is outputting logic low. This pin can also be directly controlled in software as a digital output pin. 28–31 30–33 P2.0–P2.7 I/O Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to 36–39 39–42 (A8–A15) them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As (A16–A23) inputs, Port 2 pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24-bit external data memory space. 32 34 XTAL1 I Input to the Crystal Oscillator Inverter 33 35 XTAL2 O Output from the Crystal Oscillator Inverter. (See the ADuC816 Hardware Design Considerations section for description.) 40 43 EA I/O External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal program memory locations 0000h to F7FFh.When held low, this input enables the device to fetch all instructions from external program memory. To determine the mode of code execution, i.e., internal or external, the EA pin is sampled at the end of an external RESET assertion or as part of a device power cycle. EA may also be used as an external emulation I/O pin, and therefore the voltage level at this pin must not be changed during normal mode operation as it may cause an emulation interrupt that will halt code execution. 41 44 PSEN O Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution. PSEN can also be used to enable Serial Download mode when pulled low through a resistor at the end of an external RESET assertion or as part of a device power cycle. 42 45 ALE O Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for 24-bit data address space accesses) of the address to external memory during external code or data memory access cycles. It is activated every six oscillator periods except during an external data memory access. It can be disabled by setting the PCON.4 bit in the PCON SFR. 43–46 46–49 P0.0–P0.7 I/O These pins are part of Port 0, which is an 8-bit, open-drain, bidirectional I/O port. Port 0 pins that 49–52 52–55 (AD0–AD3) have 1s written to them float and in that state can be used (AD4–AD7)as high impedance inputs. An external pull-up resistor will be required on P0 outputs to force a valid logic high level externally. Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory. In this application, it uses strong internal pull-ups when emitting 1s. 1 I = Input, O = Output, S = Supply. –20– Rev. B

ADuC816 Figure 12. 52-MQFP Block Diagram –21– Rev. B

ADuC816 MEMORY ORGANIZATION DATA MEMORY SPACE As with all 8051-compatible devices, the ADuC816 has sepa- READ/WRITE rate address spaces for Program and Data memory as shown in 9FH (PAGE 159) FFFFFFH Figure 13 and Figure 14. 640 BYTES FLASH/EE DATA If the user applies power or resets the device while the EA pin is MEMORY pulled low, the part will execute code from the external pro- ACCESSED INDIRECTLY gram space, otherwise the part defaults to code execution VIA SFR CONTROL REGISTERS from its internal 8Kbyte Flash/EE program memory. This 00H (PAGE 0) internal code space can be downloaded via the UART serial EXTERNAL port while the device is in-circuit. DATA MEMORY INTERNAL SPACE DATA MEMORY (24-BIT PROGRAM MEMORY SPACE SPACE ADDRESS READ ONLY FFH SPECIAL FFH SPACE) FFFFH ACCESSIBLE FUNCTION UPPER BY REGISTERS 128 INDIRECT ACCESSIBLE EXTERNAL ADDRESSING BY DIRECT PROGRAM ONLY ADDRESSING MEMORY 80H ONLY 80H SPACE 7FH ACCESSIBLE LOWER BY 128 DIRECT AND INDIRECT ADDRESSING 2000H 00H 000000H Figure 14.Data Memory Map The lower 128 bytes of internal data memory are mapped as shown EA = 1 1FFFH EA = 0 in Figure 15. The lowest 32 bytes are grouped into four banks INTERNAL EXTERNAL 8 KBYTE PROGRAM of eight registers addressed as R0 through R7. The next 16 bytes FLASH/EE MEMORY (128 bits), locations 20Hex through 2FHex above the register PROGRAM SPACE MEMORY 0000H banks, form a block of directly addressable bit locations at bit addresses 00H through 7FH. The stack can be located anywhere Figure 13.Program Memory Map in the internal memory address space, and the stack depth can be The data memory address space consists of internal and exter- expanded up to 256 bytes. nal memory space. The internal memory space is divided into four physically separate and distinct blocks, namely the lower 128bytes of RAM, the upper 128 bytes of RAM, the 128 bytes 7FH of special function register (SFR) area, and a 640-byte Flash/EE GENERAL-PURPOSE AREA Data memory. While the upper 128 bytes of RAM, and the 30H SFR area share the same address locations, they are accessed 2FH through different address modes. BANKS BIT-ADDRESSABLE The lower 128 bytes of data memory can be accessed through SELECTED (BIT ADDRESSES) direct or indirect addressing, the upper 128 bytes of RAM can VIA 20H be accessed through indirect addressing, and the SFR area is BITS IN PSW 1FH 11 accessed through direct addressing. 18H Also, as shown in Figure 13, the additional 640 Bytes of 17H 10 Flash/EE Data Memory are available to the user and can be 10H FOUR BANKS OF EIGHT accessed indirectly via a group of control registers mapped into 0FH REGISTERS R0 R7 the Special Function Register (SFR) area. Access to the Flash/ 01 08H EE Data Memory is discussed in detail later as part of the Flash/ 07H RESET VALUE OF EE Memory section in this data sheet. 00 STACK POINTER 00H The external data memory area can be expanded up to 16MBytes. This is an enhancement of the 64KByte external data memory Figure 15.Lower 128 Bytes of Internal Data Memory space available on standard 8051-compatible cores. The external data memory is discussed in more detail in the ADuC816 Hardware Design Considerations section. –22– Rev. B

ADuC816 Reset initializes the stack pointer to location 07 hex and increments Program Status Word SFR it once to start from locations 08 hex which is also the first regis- The PSW register is the Program Status Word which contains ter (R0) of register bank 1. Thus, if one is going to use more several bits reflecting the current status of the CPU as detailed in than one register bank, the stack pointer should be initialized to an Table I. area of RAM not used for data storage. SFR Address D0H The SFR space is mapped to the upper 128 bytes of internal data Power ON Default Value 00H memory space and accessed by direct addressing only. It provides Bit Addressable Yes an interface between the CPU and all on-chip peripherals. A block diagram showing the programming model of the ADuC816 via CY AC F0 RS1 RS0 OV F1 P the SFR area is shown in Figure 16. A complete SFR map is shown in Figure 17. Table I. PSW SFR Bit Designations 640-BYTE 8 KBYTE ELECTRICALLY Bit Name Description ELECTRICALLY REPROGRAMMABLE REPROGRAMMABLE NONVOLATILE 7 CY Carry Flag NONVOLATILE FLASH/EE DATA FLASH/EE PROGRAM MEMORY 6 AC Auxiliary Carry Flag MEMORY 5 F0 General-Purpose Flag 4 RS1 Register Bank Select Bits DUAL 3 RS0 RS1 RS0 Selected Bank SIGMA-DELTA ADCs 128-BYTE 0 0 0 8051- SPECIAL COMPATIBLE FUNCTION 0 1 1 CORE REGISTER AREA 1 0 2 OTHER ON-CHIP PERIPHERALS 1 1 3 TEMPERATURE 2 OV Overflow Flag SENSOR CURRENT 1 F1 General-Purpose Flag 256 BYTES SOURCES RAM 12-BIT DAC 0 P Parity Bit SERIAL I/O WDT PSM Power Control SFR TIC PLL The Power Control (PCON) register contains bits for power- saving options and general-purpose status flags as shown in Figure 16.Programming Model Table II. SFR Address 87H OVERVIEW OF MCU-RELATED SFRS Power ON Default Value 00H Accumulator SFR Bit Addressable No ACC is the Accumulator register and is used for math operations including addition, subtraction, integer multiplication and division, and Boolean bit manipulations. The mnemonics for accumulator- SMOD SERIPD INT0PD ALEOFF GF1 GF0 PD IDL specific instructions refer to the Accumulator as A. B SFR Table II. PCON SFR Bit Designations The B register is used with the ACC for multiplication and divi- sion operations. For other instructions it can be treated as a Bit Name Description general-purpose scratchpad register. 7 SMOD Double UART Baud Rate Stack Pointer SFR 6 SERIPD I2C/SPI Power-Down Interrupt The SP register is the stack pointer and is used to hold an internal Enable RAM address that is called the “top of the stack.” The SP register 5 INT0PD INT0 Power-Down Interrupt is incremented before data is stored during PUSH and CALL Enable executions. While the Stack may reside anywhere in on-chip 4 ALEOFF Disable ALE Output RAM, the SP register is initialized to 07H after a reset. This causes 3 GF1 General-Purpose Flag Bit the stack to begin at location 08H. 2 GF0 General-Purpose Flag Bit Data Pointer 1 PD Power-Down Mode Enable The Data Pointer is made up of three 8-bit registers, named 0 IDL Idle Mode Enable DPP (page byte), DPH (high byte) and DPL (low byte). These are used to provide memory addresses for internal and external code access and external data access. It may be manipulated as a 16-bit register (DPTR = DPH, DPL), although INC DPTR instructions will automatically carry over to DPP, or as three independent 8-bit registers (DPP, DPH, DPL). Rev. B –23–

ADuC816 SPECIAL FUNCTION REGISTERS Figure 17 shows a full SFR memory map and SFR contents on All registers except the program counter and the four general- RESET; NOT USED indicates unoccupied SFR locations. Unoc- purpose register banks, reside in the SFR area. The SFR registers cupied locations in the SFR address space are not implemented; include control, configuration, and data registers that provide i.e., no register exists at this location. If an unoccupied location an interface between the CPU and all on-chip peripherals. is read, an unspecified value is returned. SFR locations reserved for future use are shaded (RESERVED) and should not be accessed by user software. ISPI WCOL SPE SPIM CPOL CPHA SPR1 SPR0 BITS SPICON RESERVED RESERVED DACL DACH DACCON RESERVED RESERVED FFH 0 FEH 0 FDH 0 FCH 0 FBH 0 FAH 1 F9H 0 F8H 0 F8H 04H FBH 00H FCH 00H FDH 00H B SPIDAT BITS RESERVED RESERVED NOT USED RESERVED RESERVED RESERVED F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H 0 F1H 0 F0H 0 F0H 00H F7H 00H I2CCON GN0M* GN0H* GN1L* GN1H* MDO MDE MCO MDI I2CM I2CRS I2CTX I2CI BITS RESERVED RESERVED RESERVED EFH 0 EEH 0 EDH 0 ECH 0 EBH 0 EAH 0 E9H 0 E8H 0 E8H 00H EAH 55H EBH 53H ECH 9AH EDH 59H ACC OF0M* OF0H* OF1L* OF1H* BITS RESERVED RESERVED RESERVED E7H 0 E6H 0 E5H 0 E4H 0 E3H 0 E2H 0 E1H 0 E0H 0 E0H 00H E2H 00H E3H 80H E4H 00H E5H 80H ADCSTAT ADC0M ADC0H ADC1L ADC1H PSMCON RDY0 RDY1 CAL NOXREF ERR0 ERR1 BITS RESERVED RESERVED DFH 0 DEH 0 DDH 0 DCH 0 DBH 0 DAH 0 D9H 0 D8H 0 D8H 00H DAH 00H DBH 00H DCH 00H DDH 00H DFH DEH CY AC F0 RSI RS0 OV FI P BITS PSW ADCMODE ADC0CON ADC1CON SF ICON RESERVED PLLCON D7H 0 D6H 0 D5H 0 D4H 0 D3H 0 D2H 0 D1H 0 D0H 0 D0H 00H D1H 00H D2H 07H D3H 00H D4H 45H D5H 00H D7H 03H TF2 EXF2 RCLK TCLK EXEN2 TR2 CNT2 CAP2 BITS T2CON RESERVED RCAP2L RCAP2H TL2 TH2 RESERVED RESERVED CFH 0 CEH 0 CDH 0 CCH 0 CBH 0 CAH 0 C9H 0 C8H 0 C8H 00H CAH 00H CBH 00H CCH 00H CDH 00H PRE3 PRE2 PRE1 PRE0 WDIR WDS WDE WDWR WDCON CHIPID EADRL BITS RESERVED RESERVED RESERVED RESERVED RESERVED C7H 0 C6H 0 C5H 0 C4H 1 C3H 0 C2H 0 C1H 0 C0H 0 C0H 10H C2H 16H C6H 00H PADC PT2 PS PT1 PX1 PT0 PX0 IP ECON EDATA1 EDATA2 EDATA3 EDATA4 BITS RESERVED RESERVED BFH 0 BEH 0 BDH 0 BCH 0 BBH 0 BAH B9H 0 B8H 0 B8H 00H B9H 00H BCH 00H BDH 00H BEH 00H BFH 00H RD WR T1 T0 INT1 INT0 TXD RXD BITS P3 NOT USED NOT USED NOT USED NOT USED RESERVED RESERVED NOT USED B7H 1 B6H 1 B5H 1 B4H 1 B3H 1 B2H 1 B1H 1 B0H 1 B0H FFH EA EADC ET2 ES ET1 EX1 ET0 EX0 IE IEIP2 BITS RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED AFH 0 AEH 0 ADH 0 ACH 0 ABH 0 AAH 0 A9H 0 A8H 0 A8H 00H A9H A0H P2 TIMECON HTHSEC SEC MIN HOUR INTVAL A7H 1 A6H 1 A5H 1 A4H 1 A3H 1 A2H 1 A1H 1 A0H 1 BITS A0H FFH A1H 00H A2H 00H A3H 00H A4H 00H A5H 00H A6H 00H NOT USED SM0 SM1 SM2 REN TB8 RB8 T1 R1 SCON SBUF I2CDAT I2CDAT BITS NOT USED NOT USED NOT USED NOT USED 9FH 0 9EH 0 9DH 0 9CH 0 9BH 0 9AH 0 99H 0 98H 0 98H 00H 99H 00H 9AH 00H 9BH 00H T2EX T2 P1 BITS NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED 97H 1 96H 1 95H 1 94H 1 93H 1 92H 1 91H 1 90H 1 90H FFH TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 BITS TCON TMOD TL0 TL1 TH0 TH1 RESERVED RESERVED 8FH 0 8EH 0 8DH 0 8CH 0 8BH 0 8AH 0 89H 0 88H 0 88H 00H 89H 00H 8AH 00H 8BH 00H 8CH 00H 8DH 00H P0 SP DPL DPH DPP PCON BITS RESERVED RESERVED 87H 1 86H 1 85H 1 84H 1 83H 1 82H 1 81H 1 80H 1 80H FFH 81H 07H 82H 00H 83H 00H 84H 00H 87H 00H *CALIBRATION COEFFICIENTS ARE PRECONFIGURED AT POWER-UP TO FACTORY-CALIBRATED VALUES. SFR MAP KEY: THESE BITS ARE CONTAINED IN THIS BYTE. BIT MNEMONIC IE0 IT0 TCON MNEMONIC BIT BIT ADDRESS 89H 0 88H 0 88H 00H DEFAULT VALUE DEFAULT BIT VALUE SFR ADDRESS SFR NOTE: SFRs WHOSE ADDRESSES END IN 0H OR 8H ARE BIT-ADDRESSABLE. Figure 17.Special Function Register Locations and Reset Values –24– Rev. B

ADuC816 SFR INTERFACE TO THE PRIMARY AND AUXILIARY ICON: Current Source Control Register. Allows ADCS user control of the various on-chip current Both ADCs are controlled and configured via a number of SFRs source options. that are mentioned here and described in more detail in the ADC0H/M*: Primary ADC 16-bit conversion result held in following pages. these two 8-bit registers. ADCSTAT: ADC Status Register. Holds general status of ADC1H/L: Auxiliary ADC 16-bit conversion result held the Primary and Auxiliary ADCs. in these two 8-bit registers. ADCMODE: ADC Mode Register. Controls general modes OF0H/M*: Primary ADC 16-bit Offset Calibration Coeffi- of operation for Primary and Auxiliary ADCs. cient held in these two 8-bit registers. ADC0CON: Primary ADC Control Register. Controls OF1H/L: Auxiliary ADC 16-bit Offset Calibration Coeffi- specific configuration of Primary ADC. cient held in these two 8-bit registers. ADC1CON: Auxiliary ADC Control Register. Controls GN0H/M*: Primary ADC 16-bit Gain Calibration Coeffi- specific configuration of Auxiliary ADC. cient held in these two 8-bit registers. SF: Sinc Filter Register. Configures the decimation GN1H/L: Auxiliary ADC 16-bit Gain Calibration Coeffi- factor for the Sinc3 filter and thus the Primary cient held in these two 8-bit registers. and Auxiliary ADC update rates. *To maintain code compatibility with the ADuC824, it is the low-byte SFR associated with these register groups that is omitted on the ADuC816. ADCSTAT (ADC Status Register) This SFR reflects the status of both ADCs including data ready, calibration and various (ADC-related) error and warning condi- tions including reference detect and conversion overflow/underflow flags. SFR Address D8H Power-On Default Value 00H Bit Addressable Yes RDY0 RDY1 CAL NOXREF ERR0 ERR1 --- --- Table III. ADCSTAT SFR Bit Designations Bit Name Description 7 RDY0 Ready Bit for Primary ADC. Set by hardware on completion of ADC conversion or calibration cycle. Cleared directly by the user or indirectly by write to the mode bits to start another Primary ADC conversion or calibration. The Primary ADC is inhibited from writing further results to its data or calibration registers until the RDY0 bit is cleared. 6 RDY1 Ready Bit for Auxiliary ADC. Same definition as RDY0 referred to the Auxiliary ADC. 5 CAL Calibration Status Bit. Set by hardware on completion of calibration. Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration. 4 NOXREF No External Reference Bit (only active if Primary or Auxiliary ADC is active). Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below a specified threshold. When Set conversion results are clamped to all ones,if using ext. reference. Cleared to indicate valid V . REF 3 ERR0 Primary ADC Error Bit. Set by hardware to indicate that the result written to the Primary ADC data registers has been clamped to all zeros or all ones. After a calibration this bit also flags error conditions that caused the calibration registers not to be written. Cleared by a write to the mode bits to initiate a conversion or calibration. 2 ERR1 Auxiliary ADC Error Bit. Same definition as ERR0 referred to the Auxiliary ADC. 1 --- Reserved for Future Use. 0 --- Reserved for Future Use. Rev. B –25–

ADuC816 ADCMODE (ADC Mode Register) Used to control the operational mode of both ADCs. SFR Address D1H Power-On Default Value 00H Bit Addressable No --- --- ADC0EN ADC1EN --- MD2 MD1 MD0 Table IV. ADCMODE SFR Bit Designations Bit Name Description 7 --- Reserved for Future Use. 6 --- Reserved for Future Use. 5 ADC0EN Primary ADC Enable. Set by the user to enable the Primary ADC and place it in the mode selected in MD2-MD0 below Cleared by the user to place the Primary ADC in power-down mode. 4 ADC1EN Auxiliary ADC Enable. Set by the user to enable the Auxiliary ADC and place it in the mode selected in MD2-MD0 below Cleared by the user to place the Auxiliary ADC in power-down mode. 3 --- Reserved for Future Use. 2 MD2 Primary and Auxiliary ADC Mode bits. 1 MD1 These bits select the operational mode of the enabled ADC as follows: 0 MD0 MD2 MD1 MD0 0 0 0 Power-Down Mode (Power-On Default) 0 0 1 Idle Mode In Idle Mode the ADC filter and modulator are held in a reset state although the modulator clocks are still provided. 0 1 0 Single Conversion Mode In Single Conversion Mode, a single conversion is performed on the enabled ADC. On completion of the conversion, the ADC data regis- ters (ADC0H/M and/or ADC1H/L) are updated, the relevant flags in the ADCSTAT SFR are written, and power-down is re-entered with the MD2–MD0 accordingly being written to 000. 0 1 1 Continuous Conversion In continuous conversion mode the ADC data registers are regularly updated at the selected update rate (see SF register) 1 0 0 Internal Zero-Scale Calibration Internal short automatically connected to the enabled ADC(s) 1 0 1 Internal Full-Scale Calibration Internal or External V (as determined by XREF0 and XREF1 bits REF in ADC0/1CON) is automatically connected to the ADC input for this calibration. 1 1 0 System Zero-Scale Calibration User should connect system zero-scale input to the ADC input pins as selected by CH1/CH0 and ACH1/ACH0 bits in the ADC0/1CON register. 1 1 1 System Full-Scale Calibration User should connect system full-scale input to the ADC input pins as selected by CH1/CH0 and ACH1/ACH0 bits in the ADC0/1CON register. NOTES 1. Any change to the MD bits will immediately reset both ADCs. A write to the MD2–0 bits with no change is also treated as a reset. (See exception to this in Note 3 below.) 2. If ADC0CON is written when AD0EN = 1, or if AD0EN is changed from 0 to 1, then both ADCs are also immediately reset. In other words, the Primary ADC is given priority over the Auxiliary ADC and any change requested on the primary ADC is immediately responded to. 3. On the other hand, if ADC1CON is written or if ADC1EN is changed from 0 to 1, only the Auxiliary ADC is reset. For example, if the Primary ADC is continuously converting when the Auxiliary ADC change or enable occurs, the primary ADC continues undisturbed. Rather than allow the Auxiliary ADC to operate with a phase difference from the primary ADC, the Auxiliary ADC will fall into step with the outputs of the primary ADC. The result is that the first conversion time for the Auxiliary ADC will be delayed up to three outputs while the Auxiliary ADC update rate is synchronized to the Primary ADC. 4. Once ADCMODE has been written with a calibration mode, the RDY0/1 bits (ADCSTAT) are immediately reset and the calibration commences. On completion, the appropriate calibration registers are written, the relevant bits in ADCSTAT are written, and the MD2–0 bits are reset to 000 to indicate the ADC is back in power-down mode. 5. Any calibration request of the Auxiliary ADC while the temperature sensor is selected will fail to complete. Although the RDY1 bit will be set at the end of the calibration cycle, no update of the calibration SFRs will take place and the ERR1 bit will be set. 6. Calibrations are performed at maximum SF (see SF SFR) value guaranteeing optimum calibration operation. –26– Rev. B

ADuC816 ADC0CON (Primary ADC Control Register) Used to configure the Primary ADC for range, channel selection, external Ref enable, and unipolar or bipolar coding. SFR Address D2H Power-On Default Value 07H Bit Addressable No --- XREF0 CH1 CH0 UNI0 RN2 RN1 RN0 Table V. ADC0CON SFR Bit Designations Bit Name Description 7 --- Reserved for Future Use. 6 XREF0 Primary ADC External Reference Select Bit. Set by user to enable the Primary ADC to use the external reference via REFIN(+)/REFIN(–). Cleared by user to enable the Primary ADC to use the internal bandgap reference (V = 1.25V). REF 5 CH1 Primary ADC Channel Selection Bits. 4 CH0 Written by the user to select the differential input pairs used by the Primary ADC as follows: CH1 CH0 Positive InputNegative Input 0 0 AIN1 AIN2 0 1 AIN3 AIN4 1 0 AIN2 AIN2 (Internal Short) 1 1 AIN3 AIN2 3 UNI0 Primary ADC Unipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in 000000 hex output. Cleared by user to enable bipolar coding, zero differential input will result in 800000 hex output. 2 RN2 Primary ADC Range Bits. 1 RN1 Written by the user to select the Primary ADC input range as follows: 0 RN0 RN2 RN1 RN0 Selected Primary ADC Input Range (V = 2.5V) REF 0 0 0 ±20mV 0 0 1 ±40mV 0 1 0 ±80mV 0 1 1 ±160mV 1 0 0 ±320mV 1 0 1 ±640mV 1 1 0 ±1.28V 1 1 1 ±2.56V Rev. B –27–

ADuC816 ADC1CON (Auxiliary ADC Control Register) Used to configure the Auxiliary ADC for channel selection, external Ref enable and unipolar or bipolar coding. It should be noted that the Auxiliary ADC only operates on a fixed input range of ±V . REF SFR Address D3H Power-On Default Value 00H Bit Addressable No --- XREF1 ACH1 ACH0 UNI1 --- --- --- Table VI. ADC1CON SFR Bit Designations Bit Name Description 7 --- Reserved for Future Use. 6 XREF1 Auxiliary ADC External Reference Bit. Set by user to enable the Auxiliary ADC to use the external reference via REFIN(+)/REFIN(–). Cleared by user to enable the Auxiliary ADC to use the internal bandgap reference. 5 ACH1 Auxiliary ADC Channel Selection Bits. 4 ACH0 Written by the user to select the single-ended input pins used to drive the Auxiliary ADC as follows: ACH1 ACH0 Positive Input Negative Input 0 0 AIN3 AGND 0 1 AIN4 AGND 1 0 Temp Sensor* AGND (Temp. Sensor routed to the ADC input) 1 1 AIN5 AGND 3 UNI1 Auxiliary ADC Unipolar Bit. Set by user to enable unipolar coding, i.e., zero input will result in 0000 hex output. Cleared by user to enable bipolar coding, zero input will result in 8000 hex output. 2 --- Reserved for Future Use. 1 --- Reserved for Future Use. 0 --- Reserved for Future Use. *NOTES 1.When the temperature sensor is selected, user code must select internal reference via XREF1 bit above and clear the UNI1 bit (ADC1CON.3) to select bipolar coding. 2.The temperature sensor is factory calibrated to yield conversion results 8000H at 0°C. 3.A +1°C change in temperature will result in a +1 LSB change in the ADC1H register ADC conversion result. SF (Sinc Filter Register) value for the SF register is 45 hex, resulting in a default ADC The number in this register sets the decimation factor and thus update rate of just under 20Hz. Both ADC inputs are chopped the output update rate for the Primary and Auxiliary ADCs. to minimize offset errors, which means that the settling time for This SFR cannot be written by user software while either ADC is a single conversion or the time to a first conversion result in active. The update rate applies to both Primary and Auxiliary continuous conversion mode is 2 × t . As mentioned earlier, ADC ADCs and is calculated as follows: all calibration cycles will be carried out automatically with a maximum, i.e., FFhex, SF value to ensure optimum calibra- 1 1 tion performance. Once a calibration cycle has completed, the f = · ·f ADC 3 8.SF MOD value in the SF register will be that programmed by user software. Where: f = ADC Output Update Rate ADC Table VII. SF SFR Bit Designations f = Modulator Clock Frequency = 32.768kHz MOD SF = Decimal Value of SF Register SF(dec) SF(hex) f (Hz) t (ms) ADC ADC The allowable range for SF is 0Dhex to FFhex. Examples of SF 13 0D 105.3 9.52 values and corresponding conversion update rate (f ) and con- 69 45 19.79 50.34 ADC version time (t ) are shown in Table VII, the power-on default 255 FF 5.35 186.77 ADC –28– Rev. B

ADuC816 ICON (Current Sources Control Register) Used to control and configure the various excitation and burnout current source options available on-chip. SFR Address D5H Power-On Default Value 00H Bit Addressable No --- BO ADC1IC ADC0IC I2PIN I1PIN I2EN I1EN Table VIII. ICON SFR Bit Designations Bit Name Description 7 --- Reserved for Future Use. 6 BO Burnout Current Enable Bit. Set by user to enable both transducer burnout current sources in the primary ADC signal paths. Cleared by user to disable both transducer burnout current sources. 5 ADC1IC Auxiliary ADC Current Correction Bit. Set by user to allow scaling of the Auxiliary ADC by an internal current source calibration word. 4 ADC0IC Primary ADC Current Correction Bit. Set by user to allow scaling of the Primary ADC by an internal current source calibration word. 3 I2PIN* Current Source-2 Pin Select Bit. Set by user to enable current source-2 (200μA) to external Pin 3 (P1.2/DAC/IEXC1). Cleared by user to enable current source-2 (200μA) to external Pin 4 (P1.3/AIN5/IEXC2). 2 I1PIN* Current Source-1 Pin Select Bit. Set by user to enable current source-1 (200μA) to external Pin 4 (P1.3/AIN5/IEXC2). Cleared by user to enable current source-1 (200μA) to external Pin 3 (P1.2/DAC/IEXC1). 1 I2EN Current Source-2 Enable Bit. Set by user to turn on excitation current source-2 (200μA). Cleared by user to turn off excitation current source-2 (200μA). 0 I1EN Current Source-1 Enable Bit. Set by user to turn on excitation current source-1 (200μA). Cleared by user to turn off excitation current source-1 (200μA). *Both current sources can be enabled to the same external pin, yielding a 400μA current source. ADC0H/ADC0M (Primary ADC Conversion Result Registers) These two 8-bit registers hold the 16-bit conversion result from the Primary ADC. SFR Address ADC0H High Data Byte DBH ADC0M Middle Data Byte DAH Power-On Default Value 00H Both Registers Bit Addressable No Both Registers ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers) These two 8-bit registers hold the 16-bit conversion result from the Auxiliary ADC. SFR Address ADC1H High Data Byte DDH ADC1L Low Data Byte DCH Power-On Default Value 00H Both Registers Bit Addressable No Both Registers Rev. B –29–

ADuC816 OF0H/OF0M (Primary ADC Offset Calibration Registers1) These two 8-bit registers hold the 16-bit offset calibration coefficient for the Primary ADC. These registers are configured at power- on with a factory default value of 8000Hex. However, these bytes will be automatically overwritten if an internal or system zero-scale calibration is initiated by the user via MD2–0 bits in the ADCMODE register. SFR Address OF0H Primary ADC Offset Coefficient High Byte E3H OF0M Primary ADC Offset Coefficient Middle Byte E2H Power-On Default Value 8000H OF0H and OF0M Respectively Bit Addressable No Both Registers OF1H/OF1L (Auxiliary ADC Offset Calibration Registers1) These two 8-bit registers hold the 16-bit offset calibration coefficient for the Auxiliary ADC. These registers are configured at power-on with a factory default value of 8000Hex. However, these bytes will be automatically overwritten if an internal or system zero-scale calibration is initiated by the user via the MD2–0 bits in the ADCMODE register. SFR Address OF1H Auxiliary ADC Offset Coefficient High Byte E5H OF1L Auxiliary ADC Offset Coefficient Low Byte E4H Power-On Default Value 8000H OF1H and OF1L Respectively Bit Addressable No Both Registers GN0H/GN0M (Primary ADC Gain Calibration Registers1) These two 8-bit registers hold the 16-bit gain calibration coefficient for the Primary ADC. These registers are configured at power-on with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via MD2–0 bits in the ADCMODE register. SFR Address GN0H Primary ADC Gain Coefficient High Byte EBH GN0M Primary ADC Gain Coefficient Middle Byte EAH Power-On Default Value Configured at factory final test, see notes above. Bit Addressable No Both Registers GN1H/GN1L (Auxiliary ADC Gain Calibration Registers1) These two 8-bit registers hold the 16-bit gain calibration coefficient for the Auxiliary ADC. These registers are configured at power- on with a factory calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via MD2–0 bits in the ADCMODE register. SFR Address GN1H Auxiliary ADC Gain Coefficient High Byte EDH GN1L Auxiliary ADC Gain Coefficient Low Byte ECH Power-On Default Value Configured at factory final test, see notes above. Bit Addressable No Both Registers NOTE 1These registers can be overwritten by user software only if Mode bits MD0–2 (ADCMODE SFR) are zero. –30– Rev. B

ADuC816 PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION the analog inputs if required. On-chip burnout currents can OVERVIEW also be turned on. These currents can be used to check that a The ADuC816 incorporates two independent sigma-delta ADCs transducer on the selected channel is still operational before (Primary and Auxiliary) with on-chip digital filtering intended attempting to take measurements. for the measurement of wide dynamic range, low frequency The ADC employs a sigma-delta conversion technique to realize signals such as those in weigh-scale, strain-gauge, pressure trans- up to 16 bits of no missing codes performance. The sigma-delta ducer or temperature measurement applications. modulator converts the sampled input signal into a digital pulse Primary ADC train whose duty cycle contains the digital information. A Sinc3 This ADC is intended to convert the primary sensor input. The programmable low-pass filter is then employed to decimate the input is buffered and can be programmed for one of 8 input ranges modulator output data stream to give a valid data conversion from ±20mV to ±2.56V being driven from one of three differ- result at programmable output rates from 5.35Hz (186.77ms) ential input channel options AIN1/2, AIN3/4, or AIN3/2. The to 105.03Hz (9.52ms). A Chopping scheme is also employed input channel is internally buffered allowing the part to handle to minimize ADC offset errors. A block diagram of the Primary significant source impedances on the analog input, allowing R/C ADC is shown in Figure 18. filtering (for noise rejection or RFI reduction) to be placed on DIFFERENTIAL REFERENCE PROGRAMMABLE GAIN AMPLIFIER THE EXTERNAL REFERENCE ANALOTHGE I NINPPUUTT SC AHROEPPING GATHINE A PMRPOLGIFRIEARM MALALBOLWES FIANCPDIULITIFT FTAEOTR ETESHN ERT AAIATDLIuO ACMN8E1DT6R ISIC STIGHME ASI-GDMEALT-DAE LATDAC OUTPUT AVERAGE ALTERNATELY REVERSED EIGHT UNIPOLAR AND OPERATION. THE EXTERNAL ARCHITECTURE ENSURES AS PART OF THE CHOPPING BURNOUT CURRENTS CONTVHERROSUIGOHN TCHYECLE. REAINGGHET SB FIPROOLMA R20 ImNPVU TTO SERLEEFCETREEDN VCIAE TVHOEL TXARGEEF 0IS BIT C16O BDIETSS. NTOHE M EISNSTIINRGE IMDPALTEAM EWNOTRADT IOOUNT, PEUATCH TWO 100nA BURNOUT CHOPPING YIELDS 2.56V (EXT VREF = +2.5V) IN ADC0CON. SIGMA-DELTA ADC IS FROM THE FILTER IS UCSUERRR TEON TESA SAILLLYO DWE TTEHCET EXCAENLDL OENFFTS AEDTC D ORFIFFTSET SEE PAGE 34 CIRCURITERFYE RTEENSTCSE FDOERT EOCPTEN OR CHODPPREIFDT TEOR RROEMROVE WSUITMHM IETSD APNRDE DAEVCEERSASGOERD IF A TRANSDUCER HAS PERFORMANCE SHORTED REFERENCES INPUTS TO NULL ADC CHANNEL BURNOEPDE NO-UCTIR OCRU IGTONE SEE PAGE 36 SEE PAGE 35 SEE PAGE 35 OFFSET ERRORS SEE PAGE 36 SEE PAGE 29 AND 34 REFIN(–)REFIN(+) AVDD SIGMA-DELTA A/D CONVERTER RDEIGSUTALTL WOURTITPTUETN TO ADC0H/M AAIINN12 MUX BUFFER PGA MOSDDIEUGLLMTAAAT-OR PROGDFRIIGLATIMTEAMRLABLE AOVUETRPAUGTE SOCUATLPIUNTG SFRs AIN3 AIN4 CHOP CHOP AGND OUTPUT SCALING THE OUPUT WORD FROM THE ANALOG MULTIPLEXER DIGITAL FILTER IS SCALED BY THE CALIBRATION FUALDLDAAYITL DDILOIIOFFNFFWAEESLRR ISEENENNTLTTEEIIRAACNLLT APMIOLAUN SILR HOT OOIFPP RLTTTEHI OXROENEPREST IAONND THBEU FBFUEFRFE ARM APMLPILFIIFEIRER THE MOSMDIGOUMDLAUATL-DOARET LOPTRRAOVIDES THE SPDIRNIOCG3GIT FRAIALLTM FEMIRLA TRBEELRMEOVES THCEOB EECIFONFNGICV PIEERRNOSTVISOID NBE ERDFE OASRSUELT (AIN2–AIN2).THE MULTIPLEXER IS PRESENTS A HIGH A HIGH-FREQUENCY 1-BIT QUANTIZATION NOISE INTRODUCED SEE PAGE 37 CONTROLLED VIA THE CHANNEL IMPEDANCE INPUT STAGE DATA STREAM (THE OUTPUT BY THE MODULATOR. THE UPDATE SELECTION BITS IN ADC0CON FOR THE ANALOG INPUTS, OF WHICH IS ALSO CHOPPED) RATE AND BANDWIDTH OF THIS SEE PAGES 27 AND 33 ALELXOTWEIRNNGA SLI GSONIUFRICCAENT THTEO D TUHTEY D CIGYCITLAEL OFFIL WTEHRIC,H FILTER VAIRAE T HPRE OSGF RSAFMRMABLE IMPEDANCES REPRESENTS THE SAMPLED SEE PAGE 35 ANALOG INPUT VOLTAGE SEE PAGE 33 SEE PAGE 35 Figure 18.Primary ADC Block Diagram Rev. B –31–

ADuC816 Auxiliary ADC (assuming an external 2.5V reference). The single-ended inputs The Auxiliary ADC is intended to convert supplementary inputs can be driven from AIN3, AIN4 or AIN5 pins or directly from such as those from a cold junction diode or thermistor. This ADC the on-chip temperature sensor voltage. A block diagram of the is not buffered and has a fixed input range of 0V to 2.5V Auxiliary ADC is shown in Figure 19. DIFFERENTIAL REFERENCE THE EXTERNAL REFERENCE INPUT TO THE ADuC816 IS DIFFERENTIAL AND FACILITATES RATIOMETRIC SIGMA-DELTA ADC OPERATION. THE EXTERNAL REFER- OUTPUT AVERAGE ENCE VOLTAGE IS SELECTED VIA THE THE SIGMA-DELTA ANALOG INPUT CHOPPING XREF1 BIT IN ADC1CON. REFERENCE ARCHITECTURE ENSURES AS PART OF THE CHOPPING DETECT CIRCUITRY TESTS FOR OPEN 16 BITS NO MISSING IMPLEMENTATION EACH THE INPUTS ARE ALTERNATELY OR SHORTED REFERENcES INPUTS CODES. THE ENTIRE DATA WORD OUTPUT REVERSED THROUGH THE SIGMA-DELTA ADC IS FROM THE FILTER IS CONVERSION CYCLE. CHOPPING CHOPPED TO REMOVE DRIFT SUMMED AND AVERAGED YIELDS EXCELLENT ADC SEE PAGE 35 ERRORS WITH ITS PREDECESSOR OFFSET AND OFFSET DRIFT TO NULL ADC CHANNEL PERFORMANCE SEE PAGE 35 OFFSET ERRORS SEE PAGE 36 SEE PAGE 36 REFIN(–) REFIN(+) SIGMA-DELTA A/D CONVERTER DIGTAL OUTPUT RESULT WRITTEN AAIINN34 MMUUX MOSDDIEUGLLMTAAAT-OR PDRIOGGITRAALM FMILATBELRE AOVUETRPAUGTE SOCUATLPIUNTG TO ADC1H/L SFRs AIN5 X ON-CHIP CHOP TEMPERATURE CHOP SENSOR OUTPUT SCALING THE OUPUT WORD FROM THE ANALOG MULTIPLEXER DIGITAL FILTER IS SCALED BY THE CALIBRATION TEHXETA AEMTL RHDULTNEILOHFA TEWF OILE PBCS NRSLIH -TSEIECNASEXNHGN LEITINLNEPRIA ECE A TIL LTSEDE IM NSCMOCDEU1ONPCLEL. N OETOSDTFCIE NPRI NTN LOTIPSEOHLUOXNRLTEREESR.DE OVRIA STTHHRIISGEE H AAM MLFOSSR M(DOTIEGUOH QCLEMDUHA OEUAOTNUOPL-DCTPRAPYEE TPU DL1ORT-)TB O RTOAIVOTFI D DTWEHAHSETI ACAH QBUYPRFA ATRTINLHTHOTTEEEIEG Z ASMRARIN NOTAADCIDRO M3BUEFN ALMF I PLNAINLARTOTDTOBOEIWESGRLRREIDR.E RITTAN EHDHMTME IRMOG OUOFAIVP DTBTEDUALHSAECILSTEED THCEOB EECSIFONFENGIECV P IEEPRRNAOSTVGISOIDE NBE E3RDF7E OASRSUELT SEE PAGE 28 AND 33 THE DDUITGYI TCAYLC FLIEL TOEFR W,HICH VIA THE SF SFR REPRESENTS THE SAMPLED SEE PAGE 35 ANALOG INPUT VOLTAGE SEE PAGE 35 Figure 19.Auxiliary ADC Block Diagram –32– Rev. B

ADuC816 PRIMARY AND AUXILIARY ADC NOISE are generated at a differential input voltage of 0 V. The output PERFORMANCE update rate is selected via the SF7–SF0 bits in the Sinc Filter Tables IX, X and XI below show the output rms noise in μV (SF) SFR. It is important to note that the peak-to-peak resolu- and output peak-to-peak resolution in bits (rounded to the tion figures represent the resolution for which there will be no nearest 0.5 LSB) for some typical output update rates on both code flicker within a six-sigma limit. the Primary and Auxiliary ADCs. The numbers are typical and Table IX. Primary ADC, Typical Output RMS Noise ((cid:5)V) Typical Output RMS Noise vs. Input Range and Update Rate; Output RMS Noise in (cid:5)V SF Data Update Input Range Word Rate (Hz) (cid:6)20mV (cid:6)40mV (cid:6)80mV (cid:6)160mV (cid:6)320mV (cid:6)640mV (cid:6)1.28V (cid:6)2.56V 13 105.3 1.50 1.50 1.60 1.75 3.50 4.50 6.70 11.75 69 19.79 0.60 0.65 0.65 0.65 0.65 0.95 1.40 2.30 255 5.35 0.35 0.35 0.37 0.37 0.37 0.51 0.82 1.25 Table X. Primary ADC, Peak-to-Peak Resolution (Bits) Peak-to-Peak Resolution vs. Input Range and Update Rate; Peak-to-Peak Resolution in Bits SF Data Update Input Range Word Rate (Hz) (cid:6)20mV (cid:6)40mV (cid:6)80mV (cid:6)160mV (cid:6)320mV (cid:6)640mV (cid:6)1.28V (cid:6)2.56V 13 105.3 12 13 14 15 15 15.5 16 16 69 19.79 13 14 15 16 161 161 161 161 255 5.35 14 15 16 161 161 161 161 161 NOTE 1Peak-to-peak resolution at these range/update rate settings is limited only by the number of bits available from the ADC. Effective resolution at these range/update rate settings is greater than 16 bits as indicated by the rms noise table shown in Table IX. Table XI. Auxiliary ADC Typical Output RMS Noise vs. Update Rate1 Peak-to-Peak Resolution vs. Update Rate1 Output RMS Noise in (cid:5)V Peak-to-Peak Resolution in Bits SF Data Update Input Range SF Data Update Input Range Word Rate (Hz) 2.5V Word Rate (Hz) 2.5V 13 105.3 10.75 13 105.3 162 69 19.79 2.00 69 19.79 16 255 5.35 1.15 255 5.35 16 NOTE NOTES 1ADC converting in bipolar mode. 1ADC converting in bipolar mode. 2In unipolar mode peak-to-peak resolution at 105 Hz is 15 bits. Analog Input Channels Primary and Auxiliary ADC Inputs The primary ADC has four associated analog input pins (labelled The output of the primary ADC multiplexer feeds into a high AIN1 to AIN4) which can be configured as two fully differential impedance input stage of the buffer amplifier. As a result, the input channels. Channel selection bits in the ADC0CON SFR primary ADC inputs can handle significant source impedances and detailed in Table V allow three combinations of differential pair are tailored for direct connection to external resistive-type sensors selection as well as an additional shorted input option (AIN2–AIN2). like strain gauges or Resistance Temperature Detectors (RTDs). The auxiliary ADC has three external input pins (labelled AIN3 The auxiliary ADC, however, is unbuffered resulting in higher to AIN5) as well as an internal connection to the internal on-chip analog input current on the auxiliary ADC. It should be noted that temperature sensor. All inputs to the auxiliary ADC are single- this unbuffered input path provides a dynamic load to the driving ended inputs referenced to the AGND on the part. Channel source. Therefore, resistor/capacitor combinations on the input selection bits in the ADC1CON SFR detailed previously in pins can cause dc gain errors depending on the output impedance Table VI allow selection of one of four inputs. of the source that is driving the ADC inputs. Two input multiplexers switch the selected input channel to the Analog Input Ranges on-chip buffer amplifier in the case of the primary ADC and The absolute input voltage range on the primary ADC is restricted directly to the sigma-delta modulator input in the case of the to between AGND + 100mV to AVDD – 100mV. Care must be auxiliary ADC. When the analog input channel is switched, the taken in setting up the common-mode voltage and input voltage settling time of the part must elapse before a new valid word is range so that these limits are not exceeded, otherwise there will available from the ADC. be a degradation in linearity performance. Rev. B –33–

ADuC816 The absolute input voltage range on the auxiliary ADC is restricted Burnout Currents to between AGND – 30mV to AVDD + 30mV. The slightly The primary ADC on the ADuC816 contains two 100 nA con- negative absolute input voltage limit does allow the possibility of stant current generators, one sourcing current from AVDD to monitoring small signal bipolar signals using the single-ended AIN(+), and one sinking from AIN(–) to AGND. The currents auxiliary ADC front end. are switched to the selected analog input pair. Both currents are either on or off, depending on the Burnout Current Enable Programmable Gain Amplifier (BO) bit in the ICON SFR (see Table VIII). These currents can The output from the buffer on the primary ADC is applied to the be used to verify that an external transducer is still operational input of the on-chip programmable gain amplifier (PGA). The before attempting to take measurements on that channel. Once PGA can be programmed through eight different unipolar input the burnout currents are turned on, they will flow in the exter- ranges and bipolar ranges. The PGA gain range is programmed nal transducer circuit, and a measurement of the input voltage via the range bits in the ADC0CON SFR. With the external refer- on the analog input channel can be taken. If the resultant volt- ence select bit set in the ADC0CON SFR and an external 2.5V age measured is full-scale, this indicates that the transducer has reference, the unipolar ranges are 0mV to +20mV, 0mV to gone open-circuit. If the voltage measured is 0 V, it indicates that 40mV, 0mV to 80mV, 0mV to 160mV, 0mV to 320mV, the transducer has short circuited. For normal operation, these 0mV to 640mV and 0V to 1.28V and 0 to 2.56V while the bipolar ranges are ±20mV, ±40mV, ±80mV, ±160mV, burnout currents are turned off by writing a 0 to the BO bit in ±320mV, ±640mV, ±1.28V and ±2.56V. These are the nominal the ICON SFR. The current sources work over the normal abso- lute input voltage range specifications. ranges that should appear at the input to the on-chip PGA. An ADC range matching specification of 0.5 LSB (typ) across all Excitation Currents ranges means that calibration need only be carried out at a single The ADuC816 also contains two identical, 200μA constant gain range and does not have to be repeated when the PGA current sources. Both source current from AVDD to Pin 3 gain range is changed. (IEXC1) or Pin 4 (IEXC2) These current sources are con- trolled via bits in the ICON SFR shown in Table VIII. They The auxiliary ADC does not incorporate a PGA and is configured can be configured to source 200μA individually to both pins or for a fixed single input range of 0 to V . REF a combination of both currents, i.e., 400μA to either of the Bipolar/Unipolar Inputs selected pins. These current sources can be used to excite exter- The analog inputs on the ADuC816 can accept either uni- nal resistive bridge or RTD sensors. polar or bipolar input voltage ranges. Bipolar input ranges Reference Input do not imply that the part can handle negative voltages with The ADuC816’s reference inputs, REFIN(+) and REFIN(–), respect to system AGND. provide a differential reference input capability. The common- Unipolar and bipolar signals on the AIN(+) input on the primary mode range for these differential inputs is from AGND to AVDD. ADC are referenced to the voltage on the respective AIN(–) input. The nominal reference voltage, VREF (REFIN(+) – REFIN(–)), For example, if AIN(–) is 2.5V and the primary ADC is config- for specified operation is 2.5V with the primary and auxil- ured for an analog input range of 0 mV to +20 mV, the input iary reference enable bits set in the respective ADC0CON voltage range on the AIN(+) input is 2.5V to 2.52V. If AIN(–) and/or ADC1CON SFRs. is 2.5V and the ADuC816 is configured for an analog input range The part is also functional (although not specified for perfor- of 1.28V, the analog input range on the AIN(+) input is 1.22V to 3.78V (i.e., 2.5V ± 1.28V). mance) when the XREF0 or XREF1 bits are “0,” which enables the on-chip internal bandgap reference. In this mode, the ADCs As mentioned earlier, the auxiliary ADC input is a single-ended will see the internal reference of 1.25 V, therefore halving all input with respect to the system AGND. In this context a bipolar input ranges. As a result of using the internal reference volt- signal on the auxiliary ADC can only span 30 mV negative age, a noticeable degradation in peak-to-peak resolution will with respect to AGND before violating the voltage input limits result. Therefore, for best performance, operation with an exter- for this ADC. nal reference is strongly recommended. Bipolar or unipolar options are chosen by programming the In applications where the excitation (voltage or current) for the Primary and Auxiliary Unipolar enable bits in the ADC0CON transducer on the analog input also drives the reference voltage and ADC1CON SFRs respectively. This programs the relevant for the part, the effect of the low-frequency noise in the excita- ADC for either unipolar or bipolar operation. Programming for tion source will be removed as the application is ratiometric. If the either unipolar or bipolar operation does not change any of the ADuC816 is not used in a ratiometric application, a low noise input signal conditioning; it simply changes the data output coding reference should be used. Recommended reference voltage sources and the points on the transfer function where calibrations occur. for the ADuC816 include the AD780, REF43, and REF192. When an ADC is configured for unipolar operation, the output It should also be noted that the reference inputs provide a high coding is natural (straight) binary with a zero differential input impedance, dynamic load. Because the input impedance of each voltage resulting in a code of 000...000, a midscale voltage reference input is dynamic, resistor/capacitor combinations on resulting in a code of 100...000, and a full-scale input voltage these inputs can cause dc gain errors depending on the output resulting in a code of 111...111. When an ADC is configured impedance of the source that is driving the reference inputs. for bipolar operation, the coding is offset binary with a negative Reference voltage sources, like those recommended above (e.g., full-scale voltage resulting in a code of 000...000, a zero AD780) will typically have low output impedances and therefore differential voltage resulting in a code of 100...000, and a decoupling capacitors on the REFIN(+) input would be recom- positive full-scale voltage resulting in a code of 111...111. –34– Rev. B

ADuC816 mended. Deriving the reference input voltage across an external frequency. In this manner, the 1-bit output of the comparator resistor, as shown in Figure 52, will mean that the reference is translated into a band-limited, low noise output from the input sees a significant external source impedance. External ADuC816 ADCs. decoupling on the REFIN(+) and REFIN(–) pins would not be The ADuC816 filter is a low-pass, Sinc3 or (sinx/x)3 filter whose recommended in this type of circuit configuration. primary function is to remove the quantization noise introduced Reference Detect at the modulator. The cutoff frequency and decimated output data The ADuC816 includes on-chip circuitry to detect if the part has a rate of the filter are programmable via the SF (Sinc Filter) SFR valid reference for conversions or calibrations. If the voltage as described in Table VII. between the external REFIN(+) and REFIN(–) pins goes below Figure 21 shows the frequency response of the ADC chan- 0.3V or either the REFIN(+) or REFIN(–) inputs is open circuit, nel at the default SF word of 69 dec or 45 hex, yielding an the ADuC816 detects that it no longer has a valid reference. In overall output update rate of just under 20Hz. this case, the NOXREF bit of the ADCSTAT SFR is set to a 1. If the ADuC816 is performing normal conversions and the NOXREF It should be noted that this frequency response allows frequency components higher than the ADC Nyquist frequency to pass bit becomes active, the conversion results revert to all 1s. Therefore, through the ADC, in some cases without significant attenuation. it is not necessary to continuously monitor the status of the These components may, therefore, be aliased and appear in-band NOXREF bit when performing conversions. It is only necessary after the sampling process. to verify its status if the conversion result read from the ADC Data Register is all 1s. It should also be noted that rejection of mains-related frequency components, i.e., 50Hz and 60Hz, is seen to be at level of If the ADuC816 is performing either an offset or gain calibration >65dB at 50Hz and >100dB at 60Hz. This confirms the and the NOXREF bit becomes active, the updating of the respec- data sheet specifications for 50Hz/60Hz Normal Mode Rejec- tive calibration registers is inhibited to avoid loading incorrect tion (NMR) at a 20Hz update rate. coefficients to these registers, and the appropriate ERR0 or ERR1 bits in the ADCSTAT SFR are set. If the user is concerned about verifying that a valid reference is in place every time a cali- 0 bration is performed, the status of the ERR0 or ERR1 bit should –10 be checked at the end of the calibration cycle. –20 Sigma-Delta Modulator –30 A sigma-delta ADC generally consists of two main blocks, an –40 analog modulator and a digital filter. In the case of the ADuC816 B–50 d ADCs, the analog modulators consist of a difference amplifier, N – –60 an integrator block, a comparator, and a feedback DAC as illus- GAI–70 trated in Figure 20. –80 –90 ANALOG DIFFERENCE COMPARATOR –100 INPUT AMP HIGH- FREQUENCY –110 INTEGRATOR BITSTREAM TO DIGITAL –120 0 10 20 30 40 50 60 70 80 90 100 110 FILTER FREQUENCY – Hz DAC Figure 21.Filter Response, SF = 69 dec The response of the filter, however, will change with SF word as Figure 20.Sigma-Delta Modulator Simplified Block Diagram can be seen in Figure 22, which shows >90dB NMR at 50Hz In operation, the analog signal sample is fed to the difference and >70dB NMR at 60Hz when SF = 255 dec. amplifier along with the output of the feedback DAC. The differ- ence between these two signals is integrated and fed to the 0 comparator. The output of the comparator provides the input to –10 the feedback DAC so the system functions as a negative feedback –20 loop that tries to minimize the difference signal. The digital data –30 that represents the analog input voltage is contained in the duty –40 cycle of the pulse train appearing at the output of the comparator. This duty cycle data can be recovered as a data word using a dB–50 subsequent digital filter stage. The sampling frequency of N – –60 AI the modulator loop is many times higher than the bandwidth of G–70 the input signal. The integrator in the modulator shapes the –80 quantization noise (which results from the analog-to-digital con- –90 version) so that the noise is pushed toward one-half of the –100 modulator frequency. –110 Digital Filter –120 0 10 20 30 40 50 60 70 80 90 100 The output of the sigma-delta modulator feeds directly into the FREQUENCY – Hz digital filter. The digital filter then band-limits the response to a Figure 22.Filter Response, SF = 255 dec frequency significantly lower than one-half of the modulator Rev. B –35–

ADuC816 Figures 23 and 24 show the NMR for 50Hz and 60Hz across Calibration the full range of SF word, i.e., SF = 13dec to SF = 255dec. The ADuC816 provides four calibration modes that can be pro- grammed via the mode bits in the ADCMODE SFR detailed in 0 Table IV. In fact, every ADuC816 has already been factory –10 calibrated. The resultant Offset and Gain calibration coefficients for both the primary and auxiliary ADCs are stored on-chip –20 in manufacturing-specific Flash/EE memory locations. At power- –30 on, these factory calibration coefficients are automatically –40 downloaded to the calibration registers in the ADuC816 SFR B–50 d space. Each ADC (primary and auxiliary) has dedicated calibration N – –60 SFRs, these have been described earlier as part of the general AI G–70 ADC SFR description. However, the factory calibration values –80 in the ADC calibration SFRs will be overwritten if any one of –90 the four calibration options are initiated and that ADC is enabled –100 via the ADC enable bits in ADCMODE. –110 Even though an internal offset calibration mode is described –120 below, it should be recognized that both ADCs are chopped. This 10 30 50 70 90 110 130 150 170 190 210 230 250 SF – Decimal chopping scheme inherently minimizes offset and means that an internal offset calibration should never be required. Also, because Figure 23.50Hz Normal Mode Rejection vs. SF factory 5V/25°C gain calibration coefficients are automatically present at power-on, an internal full-scale calibration will only 0 be required if the part is being operated at 3V or at temperatures –10 significantly different from 25°C. –20 The ADuC816 offers “internal” or “system” calibration facilities. –30 For full calibration to occur on the selected ADC, the calibration –40 logic must record the modulator output for two different input B–50 AIN – d–60 cpoonindtisti oanres .d Terhievseed a brey “pzeerrfoo-rsmcailneg” aa ncdo n“vfuelrls-isocnal eo”n ptohien tdsi.f Tfehreenset G–70 input voltages provided to the input of the modulator during –80 calibration. The result of the “zero-scale” calibration conversion –90 is stored in the Offset Calibration Registers for the appropri- –100 ate ADC. The result of the “full-scale” calibration conversion –110 is stored in the Gain Calibration Registers for the appropriate –120 ADC. With these readings, the calibration logic can calculate 10 30 50 70 90 110 130 150 170 190 210 230 250 the offset and the gain slope for the input-to-output transfer SF – Decimal function of the converter. Figure 24.60Hz Normal Mode Rejection vs. SF During an “internal” zero-scale or full-scale calibration, the ADC Chopping respective “zero” input and “full-scale” input are automatically Both ADCs on the ADuC816 implement a chopping scheme connected to the ADC input pins internally to the device. A whereby the ADC repeatability reverses its inputs. The deci- “system” calibration, however, expects the system zero-scale and mated digital output words from the Sinc3 filters therefore have a system full-scale voltages to be applied to the external ADC pins positive offset and negative offset term included. before the calibration mode is initiated. In this way external ADC As a result, a final summing stage is included in each ADC so that errors are taken into account and minimized as a result of system each output word from the filter is summed and averaged with the calibration. It should also be noted that to optimize calibration previous filter output to produce a new valid output result to be accuracy, all ADuC816 ADC calibrations are carried out auto- written to the ADC data SFRs. In this way, while the ADC matically at the slowest update rate. throughput or update rate is as discussed earlier and illustrated Internally in the ADuC816, the coefficients are normalized before in Table VII, the full settling time through the ADC (or the time being used to scale the words coming out of the digital filter. The to a first conversion result), will actually be given by 2 × t . ADC offset calibration coefficient is subtracted from the result prior to The chopping scheme incorporated in the ADuC816 ADC results the multiplication by the gain coefficient. All ADuC816 ADC in excellent dc offset and offset drift specifications and is specifications will only apply after a zero-scale and full-scale extremely beneficial in applications where drift, noise rejection, calibration at the operating point (supply voltage/temperature) and optimum EMI rejection are important factors. of interest. From an operational point of view, a calibration should be treated like another ADC conversion. A zero-scale calibration (if required) should always be carried out before a full-scale calibration. System software should monitor the relevant ADC RDY0/1 bit in the ADCSTAT SFR to determine end of calibration via a polling sequence or interrupt driven routine. –36– Rev. B

ADuC816 NONVOLATILE FLASH/EE MEMORY ADuC816 Flash/EE Memory Reliability Flash/EE Memory Overview The Flash/EE Program and Data Memory arrays on the ADuC816 The ADuC816 incorporates Flash/EE memory technology on-chip are fully qualified for two key Flash/EE memory characteristics, to provide the user with nonvolatile, in-circuit reprogrammable, namely Flash/EE Memory Cycling Endurance and Flash/EE code and data memory space. Memory Data Retention. Flash/EE memory is a relatively recent type of nonvolatile memory Endurance quantifies the ability of the Flash/EE memory to be technology and is based on a single transistor cell architecture. cycled through many Program, Read, and Erase cycles. In real terms, a single endurance cycle is composed of four independent, This technology is basically an outgrowth of EPROM technology sequential events. These events are defined as: and was developed through the late 1980s. Flash/EE memory takes the flexible in-circuit reprogrammable features of EEPROM and a.initial page erase sequence combines them with the space efficient/density features of EPROM b.read/verify sequence A single Flash/EE (see Figure 25). c.byte program sequence Memory d.second read/verify sequence Endurance Cycle Because Flash/EE technology is based on a single transistor cell architecture, a Flash memory array, like EPROM, can be imple- In reliability qualification, every byte in both the program and mented to achieve the space efficiencies or memory densities data Flash/EE memory is cycled from 00 hex to FFhex until a required by a given design. first fail is recorded signifying the endurance limit of the on-chip Flash/EE memory. Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased; the erase being per- As indicated in the specification pages of this data sheet, the formed in page blocks. Thus, Flash memory is often and more ADuC816 Flash/EE Memory Endurance qualification has been correctly referred to as Flash/EE memory. carried out in accordance with JEDEC Specification A117 over the industrial temperature range of –40°C, +25°C, and +85°C. The results allow the specification of a minimum endurance figure EPROM EEPROM TECHNOLOGY TECHNOLOGY over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25°C. SPACE EFFICIENT/ IN-CIRCUIT Retention quantifies the ability of the Flash/EE memory to retain DENSITY REPROGRAMMABLE its programmed data over time. Again, the ADuC816 has been FLASH/EE MEMORY qualified in accordance with the formal JEDEC Retention Life- TECHNOLOGY time Specification (A117) at a specific junction temperature (T = 55°C). As part of this qualification procedure, the Flash/EE Figure 25.Flash/EE Memory Development J memory is cycled to its specified endurance limit described above, Overall, Flash/EE memory represents a step closer to the ideal before data retention is characterized. This means that the Flash/ memory device that includes nonvolatility, in-circuit program- EE memory is guaranteed to retain its data for its full specified mability, high density and low cost. Incorporated in the ADuC816, retention lifetime every time the Flash/EE memory is repro- Flash/EE memory technology allows the user to update program grammed. It should also be noted that retention lifetime, based code space in-circuit, without the need to replace one-time on an activation energy of 0.6eV, will derate with T as shown programmable (OTP) devices at remote operating nodes. J in Figure 26. Flash/EE Memory and the ADuC816 The ADuC816 provides two arrays of Flash/EE memory for user 300 applications. 8K bytes of Flash/EE Program space are provided on-chip to facilitate code execution without any external discrete 250 ROM device requirements. The program memory can be pro- grammed using conventional third party memory programmers. This array can also be programmed in-circuit, using the serial Years200 ADI SPECIFICATION download mode provided. ON – 150 10A0T Y TEJA =R 5S5 M(cid:7)CIN. A 640-Byte Flash/EE Data Memory space is also provided on-chip. TI N This may be used as a general-purpose nonvolatile scratchpad TE E100 area. User access to this area is via a group of six SFRs. This space R can be programmed at a byte level, although it must first be erased 50 in 4-byte pages. 0 40 50 60 70 80 90 100 110 TJ JUNCTION TEMPERATURE – (cid:7)C Figure 26.Flash/EE Memory Data Retention Rev. B –37–

ADuC816 Using the Flash/EE Program Memory 5V The 8Kbyte Flash/EE Program Memory array is mapped VDD PROGRAM into the lower 8Kbytes of the 64Kbytes program space P0 DATA GND (D0–D7) addressable by the ADuC816, and is used to hold user code ADuC816 PROGRAM MODE in typical applications. (SEE TABLE XII) P3 P1 PROGRAM ADDRESS The program memory Flash/EE memory arrays can be pro- COMMAND (A0–A13) grammed in one of two modes, namely: ENABLE P3.0 P2 ((PP21..07 == AA01)3) NEGATIVE Serial Downloading (In-Circuit Programming) EDGE P3.6 As part of its factory boot code, the ADuC816 facilitates SEQUEENNTRCYE GND PSEN ALE WSTRRITOEB EENABLE serial code download via the standard UART serial port. VDD RESET Serial download mode is automatically entered on power-up if the external pin, PSEN, is pulled low through an external Figure 28.Flash/EE Memory Parallel Programming resistor as shown in Figure 27. Once in this mode, the user can download code to the program memory array while the device is Table XII. Flash/EE Memory Parallel Programming Modes sited in its target application hardware. A PC serial download executable is provided as part of the ADuC816 QuickStart devel- Port 3 Pins Programming opment system. The Serial Download protocol is detailed in a 0.7 0.6 0.5 0.4 0.3 0.2 0.1 Mode MicroConverter Applications Note uC004 available from the ADI X X X X0 0 0 E rase Flash/EE MicroConverter Website at www.analog.com/microconverter. Program, Data, and Security Modes X X X X0 0 1 R ead Device Signature/ID X X X 1 0 1 0 Program Code Byte X X X 0 0 1 0 Program Data Byte X X X 1 0 1 1 Read Code Byte X X X 0 0 1 1 Read Data Byte X X X X1 0 0 P rogram Security Modes X X X X1 0 1 R ead/Verify Security Modes All Other Codes Redundant Flash/EE Program Memory Security The ADuC816 facilitates three modes of Flash/EE program memory security. These modes can be independently activated, restricting access to the internal code space. These security PULL PSEN LOW DURING RESET modes can be enabled as part of the user interface available on all ADuC816 TO CONFIGURE THE ADuC816 FOR SERIAL DOWNLOAD MODE ADuC816 serial or parallel programming tools referenced on the PSEN MicroConverter web page at www.analog.com/microconverter. 1k(cid:8) The security modes available on the ADuC816 are described as follows: Lock Mode Figure 27.Flash/EE Memory Serial Download Mode This mode locks code in memory, disabling parallel program- Programming ming of the program memory although reading the memory in Parallel Programming parallel mode is still allowed. This mode is deactivated by initi- The parallel programming mode is fully compatible with conven- ating a “code-erase” command in serial download or parallel tional third party Flash or EEPROM device programmers. A programming modes. block diagram of the external pin configuration required to support Secure Mode parallel programming is shown in Figure 28. In this mode, Ports 0, This mode locks code in memory, disabling parallel programming 1, and 2 operate as the external data and address bus interface, (program and verify/read commands) as well as disabling the ALE operates as the Write Enable strobe, and Port 3 is used as a execution of a “MOVC” instruction from external memory, general configuration port that configures the device for various which is attempting to read the op codes from internal memory. program and erase operations during parallel programming. This mode is deactivated by initiating a “code-erase” command The high voltage (12V) supply required for Flash/EE program- in serial download or parallel programming modes. ming is generated using on-chip charge pumps to supply the high voltage program lines. –38– Rev. B

ADuC816 Serial Safe Mode FUNCTION: FUNCTION: This mode disables serial download capability on the device. If HOLDS THE 8-BIT PAGE HOLDS THE 4-BYTE Serial Safe mode is activated and an attempt is made to reset ADDRESS POINTER PAGE DATA the part into serial download mode, i.e., RESET asserted and 9FH BYTE 1 BYTE 2 BYTE 3 BYTE 4 deasserted with PSEN low, the part will interpret the serial download reset as a normal reset only. It will, therefore, not enter serial download mode but only execute a normal reset sequence. Serial Safe mode can only be disabled by initiating a EADRL EDATA1 (BYTE 1) EDATA2 (BYTE 2) code-erase command in parallel programming mode. EDATA3 (BYTE 3) Using the Flash/EE Data Memory EDATA4 (BYTE 4) The user Flash/EE data memory array consists of 640 bytes that 00H BYTE 1 BYTE 2 BYTE 3 BYTE 4 are configured into 160 (00H to 9FH) 4-byte pages as shown in Figure 29. ECON COMMAND INTERPRETER LOGIC 9FH BYTE 1 BYTE 2 BYTE 3 BYTE 4 FUNCTION: ECON F IUNNTCETRIPORNE:TS THE FLASH RECEIVES COMMAND DATA COMMAND WORD Figure 30.Flash/EE Data Memory Control and Configuration ECON—Flash/EE Memory Control SFR This SFR acts as a command interpreter and may be written with one of five command modes to enable various read, program and 00H BYTE 1 BYTE 2 BYTE 3 BYTE 4 erase cycles as detailed in Table XIII: Figure 29.Flash/EE Data Memory Configuration Table XIII. ECON–Flash/EE Memory Control Register As with other ADuC816 user-peripheral circuits, the interface to Command Modes this memory space is via a group of registers mapped in the SFR space. A group of four data registers (EDATA1–4) are used to Command hold 4-byte page data just accessed. EADRL is used to hold the Byte Command Mode 8-bit address of the page to be accessed. Finally, ECON is an 8- bit control register that may be written with one of five Flash/EE 01H READ COMMAND. memory access commands to trigger various read, write, erase, and Results in four bytes being read into EDATA1–4 verify functions. These registers can be summarized as follows: from memory page address contained in EADRL. 02H PROGRAM COMMAND. ECON: SFR Address: B9H Results in four bytes (EDATA1–4) being written Function: Controls access to 640 Bytes to memory page address in EADRL. This write Flash/EE Data Space. command assumes the designated “write” page has Default: 00H been pre-erased. EADRL: SFR Address: C6H 03H RESERVED FOR INTERNAL USE. Function: Holds the Flash/EE Data Page 03H should not be written to the ECON SFR. Address. (640 Bytes => 160 Page 04H VERIFY COMMAND. Addresses.) Allows the user to verify if data in EDATA1–4 is Default: 00H contained in page address designated by EADRL. EDATA 1–4: A subsequent read of the ECON SFR will result SFR Address: BCH to BFH respectively in a “zero” being read if the verification is valid, Function: Holds Flash/EE Data memory a nonzero value will be read to indicate an invalid page write or page read data bytes. verification. Default : EDATA1–2 –> 00H 05H ERASE COMMAND. EDATA3–4 –> 00H Results in an erase of the 4-byte page designated in EADRL. A block diagram of the SFR interface to the Flash/EE Data 06H ERASE-ALL COMMAND. Memory array is shown in Figure 30. Results in erase of the full Flash/EE Data memory 160-page (640 bytes) array. 07H to FFH RESERVED COMMANDS. Commands reserved for future use. Rev. B –39–

ADuC816 Flash/EE Memory Timing Erase-All The typical program/erase times for the Flash/EE Data Although the 640-byte User Flash/EE array is shipped from the Memory are: factory pre-erased, i.e., Byte locations set to FFH, it is nonethe- less good programming practice to include an erase-all routine as Erase Full Array (640 Bytes) – 2ms part of any configuration/setup code running on the ADuC816. Erase Single Page (4 Bytes) – 2ms Program Page (4 Bytes) – 250μs An “ERASE-ALL” command consists of writing “06H” to the ECON SFR, which initiates an erase of all 640 byte locations in Read Page (4 Bytes) – Within Single Instruction Cycle the Flash/EE array. This command coded in 8051 assembly would Using the Flash/EE Memory Interface appear as: As with all Flash/EE memory architectures, the array can be pro- MOV ECON, #06H ; Erase all Command grammed in-system at a byte level, although it must be erased ; 2ms Duration first; the erasure being performed in page blocks (4-byte pages in this case). Program a Byte In general terms, a byte in the Flash/EE array can only be pro- A typical access to the Flash/EE Data array will involve setting grammed if it has previously been erased. To be more specific, a up the page address to be accessed in the EADRL SFR, config- byte can only be programmed if it already holds the value FFH. uring the EDATA1–4 with data to be programmed to the array Because of the Flash/EE architecture, this erasure must happen (the EDATA SFRs will not be written for read accesses) and at a page level; therefore, a minimum of four bytes (1 page) will finally, writing the ECON command word which initiates one be erased when an erase command is initiated. of the six modes shown in Table XIII. A more specific example of the Program-Byte process is shown It should be noted that a given mode of operation is initiated as below. In this example the user writes F3H into the second soon as the command word is written to the ECON SFR. The byte on Page 03H of the Flash/EE Data Memory space while core microcontroller operation on the ADuC816 is idled until the preserving the other three bytes already in this page. As the user requested Program/Read or Erase mode is completed. is only required to modify one of the page bytes, the full page must In practice, this means that even though the Flash/EE memory be first read so that this page can then be erased without the exist- mode of operation is typically initiated with a two-machine cycle ing data being lost. MOV instruction (to write to the ECON SFR), the next instruc- This example, coded in 8051 assembly, would appear as: tion will not be executed until the Flash/EE operation is complete (250μs or 2 ms later). This means that the core will not respond MOV EADRL,#03H ; Set Page Address Pointer to Interrupt requests until the Flash/EE operation is complete, MOV ECON,#01H ; Read Page although the core peripheral functions like Counter/Timers will MOV EDATA2,#0F3H ; Write New Byte continue to count and time as configured throughout this period. MOV ECON,#05H ; Erase Page MOV ECON,#02H ; Write Page (Program Flash/EE) –40– Rev. B

ADuC816 USER INTERFACE TO OTHER ON-CHIP ADuC816 driving 10kΩ/100pF. It has two selectable ranges, 0V to V REF PERIPHERALS (the internal bandgap 2.5V reference) and 0V to AV . It can DD The following section gives a brief overview of the various operate in 12-bit or 8-bit mode. The DAC has a control regis- peripherals also available on-chip. A summary of the SFRs used ter, DACCON, and two data registers, DACH/L. The DAC to control and configure these peripherals is also given. output can be programmed to appear at Pin 3 or Pin 12. It should be noted that in 12-bit mode, the DAC voltage output DAC will be updated as soon as the DACL data SFR has been writ- The ADuC816 incorporates a 12-bit, voltage output DAC ten; therefore, the DAC data registers should be updated as on-chip. It has a rail-to-rail voltage output buffer capable of DACH first followed by DACL.5 DACCON DAC Control Register SFR Address FDH Power-On Default Value 00H Bit Addressable No --- --- --- DACPIN DAC8 DACRN DACCLR DACEN Table XIV. DACCON SFR Bit Designations Bit Name Description 7 --- Reserved for Future Use. 6 --- Reserved for Future Use. 5 --- Reserved for Future Use. 4 DACPIN DAC Output Pin Select. Set by the user to direct the DAC output to Pin 12 (P1.7/AIN4/DAC). Cleared by user to direct the DAC output to Pin 3 (P1.2/DAC/IEXC1). 3 DAC8 DAC 8-bit Mode Bit. Set by user to enable 8-bit DAC operation. In this mode the 8-bits in DACL SFR are routed to the 8MSBs of the DAC and the 4 LSBs of the DAC are set to zero. Cleared by user to operate the DAC in its normal 12-bit mode of operation. 2 DACRN DAC Output Range Bit. Set by user to configure DAC range of 0 – AV . DD Cleared by user to configure DAC range of 0 – 2.5V. 1 DACCLR DAC Clear Bit. Set to “1” by user to enable normal DAC operation. Cleared to “0” by user to reset DAC data registers DACl/H to zero. 0 DACEN DAC Enable Bit. Set to “1” by user to enable normal DAC operation. Cleared to “0” by user to power-down the DAC. DACH/L DAC Data Registers Function DAC Data Registers, written by user to update the DAC output. SFR Address DACL (DAC Data Low Byte) –>FBH DACH (DAC Data High Byte) –>FCH Power-On Default Value 00H –>Both Registers Bit Addressable No –>Both Registers The 12-bit DAC data should be written into DACH/L right-justified such that DACL contains the lower eight bits, and the lower nibble of DACH contains the upper four bits. Rev. B –41–

ADuC816 On-Chip PLL required. The default core clock is the PLL clock divided by The ADuC816 is intended for use with a 32.768kHz watch crys- 8 or 1.572864MHz. The ADC clocks are also derived from the tal. A PLL locks onto a multiple (384) of this to provide a stable PLL clock, with the modulator rate being the same as the crystal 12.582912MHz clock for the system. The core can operate at oscillator frequency. The above choice of frequencies ensures this frequency or at binary submultiples of it to allow power that the modulators and the core will be synchronous, regardless saving in cases where maximum core performance is not of the core clock rate. The PLL control register is PLLCON. PLLCON PLL Control Register SFR Address D7H Power-On Default Value 03H Bit Addressable No OSC_PD LOCK --- LTEA FINT CD2 CD1 CD0 Table XV. PLLCON SFR Bit Designations Bit Name Description 7 OSC_PD Oscillator Power-Down Bit. Set by user to halt the 32kHz oscillator in power-down mode. Cleared by user to enable the 32kHz oscillator in power-down mode. This feature allows the TIC to continue counting even in power-down mode. 6 LOCK PLL Lock Bit. This is a read only bit. Set automatically at power-on to indicate the PLL loop is correctly tracking the crystal clock. If the external crystal becomes subsequently disconnected the PLL will rail and the core will halt. Cleared automatically at power-on to indicate the PLL is not correctly tracking the crystal clock. This may be due to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output can be 12.58MHz ± 20%. 5 --- Reserved for future use; should be written with “0.” 4 LTEA Reading this bit returns the state of the external EA pin latched at reset or power-on. 3 FINT Fast Interrupt Response Bit. Set by user enabling the response to any interrupt to be executed at the fastest core clock frequency, regardless of the configuration of the CD2–0 bits (see below). Once user code has returned from an interrupt, the core resumes code execution at the core clock selected by the CD2–0 bits. Cleared by user to disable the fast interrupt response feature. 2 CD2 CPU (Core Clock) Divider Bits. 1 CD1 This number determines the frequency at which the microcontroller core will operate. 0 CD0 CD2 CD1 CD0 Core Clock Frequency (MHz) 0 0 0 12.582912 0 0 1 6.291456 0 1 0 3.145728 0 1 1 1.572864 (Default Core Clock Frequency) 1 0 0 0.786432 1 0 1 0.393216 1 1 0 0.196608 1 1 1 0.098304 –42– Rev. B

ADuC816 Time Interval Counter (TIC) overflow will clock the interval counter. When this counter is equal A time interval counter is provided on-chip for counting longer to the time interval value loaded in the INTVAL SFR, the TII intervals than the standard 8051-compatible timers are capable bit (TIMECON.2) is set and generates an interrupt if enabled of. The TIC is capable of timeout intervals ranging from 1/128th (See IEIP2 SFR description under Interrupt System later in this second to 255 hours. Furthermore, this counter is clocked by data sheet.) If the ADuC816 is in power-down mode, again the crystal oscillator rather than the PLL and thus has the with TIC interrupt enabled, the TII bit will wake up the device ability to remain active in power-down mode and time long and resume code execution by vectoring directly to the TIC power-down intervals. This has obvious applications for remote interrupt service vector address at 0053 hex. The TIC-related battery-powered sensors where regular widely spaced readings SFRs are described in Table XVI. Note also that the timebase are required. SFRs can be written initially with the current time, the TIC can then be controlled and accessed by user software. In effect, this Six SFRs are associated with the time interval counter, TIMECON facilitates the implementation of a real-time clock. A block being its control register. Depending on the configuration of the diagram of the TIC is shown in Figure 31. IT0 and IT1 bits in TIMECON, the selected time counter register TCEN 32.768kHz EXTERNAL CRYSTAL ITS0, 1 8-BIT PRESCALER HUNDREDTHS COUNTER HTHSEC INTERVAL TIMEBASE TIEN SELECTION SECOND COUNTER MUX SEC MINUTE COUNTER MIN HOUR COUNTER HOUR 8-BIT INTERVAL COUNTER INTERVAL TIMEOUT COMPARE TIME INTERVAL COUNTER COUNT = INTVAL? INTERRUPT TIME INTERVAL INTVAL Figure 31.TIC, Simplified Block Diagram Rev. B –43–

ADuC816 TIMECON TIC CONTROL REGISTER SFR Address A1H Power-On Default Value 00H Bit Addressable No --- --- ITS1 ITS0 STI TII TIEN TCEN Table XVI. TIMECON SFR Bit Designations Bit Name Description 7 --- Reserved for Future Use. 6 --- Reserved for Future Use. For future product code compatibility this bit should be written as a ‘1.’ 5 ITS1 Interval Timebase Selection Bits. 4 ITS0 Written by user to determine the interval counter update rate. ITS1 ITS0 Interval Timebase 0 0 1/128 Second 0 1 Seconds 1 0 Minutes 1 1 Hours 3 STI Single Time Interval Bit. Set by user to generate a single interval timeout. If set, a timeout will clear the TIEN bit. Cleared by user to allow the interval counter to be automatically reloaded and start counting again at each interval timeout. 2 TII TIC Interrupt Bit. Set when the 8-bit Interval Counter matches the value in the INTVAL SFR. Cleared by user software. 1 TIEN Time Interval Enable Bit. Set by user to enable the 8-bit time interval counter. Cleared by user to disable and clear the contents of the interval counter. 0 TCEN Time Clock Enable Bit. Set by user to enable the time clock to the time interval counters. Cleared by user to disable the clock to the time interval counters and clear the time interval SFRs. The time registers (HTHSEC, SEC, MIN and HOUR) can be written while TCEN is low. –44– Rev. B

ADuC816 INTVAL User Time Interval Select Register Function User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) bit is set and generates an interrupt if enabled. (See IEIP2 SFR description under Interrupt System later in this data sheet.) SFR Address A6H Power-On Default Value 00H Bit Addressable No Valid Value 0 to 255 decimal HTHSEC Hundredths Seconds Time Register Function This register is incremented in (1/128) second intervals once TCEN in TIMECON is active. The HTHSEC SFR counts from 0 to 127 before rolling over to increment the SEC time register. SFR Address A2H Power-On Default Value 00H Bit Addressable No Valid Value 0 to 127 decimal SEC Seconds Time Register Function This register is incremented in 1-second intervals once TCEN in TIMECON is active. The SEC SFR counts from 0 to 59 before rolling over to increment the MIN time register. SFR Address A3H Power-On Default Value 00H Bit Addressable No Valid Value 0 to 59 decimal MIN Minutes Time Register Function This register is incremented in 1-minute intervals once TCEN in TIMECON is active. The MIN counts from 0 to 59 before rolling over to increment the HOUR time register. SFR Address A4H Power-On Default Value 00H Bit Addressable No Valid Value 0 to 59 decimal HOUR Hours Time Register Function This register is incremented in 1-hour intervals once TCEN in TIMECON is active. The HOUR SFR counts from 0 to 23 before rolling over to 0. SFR Address A5H Power-On Default Value 00H Bit Addressable No Valid Value 0 to 23 decimal Rev. B –45–

ADuC816 Watchdog Timer (see PRE3–0 bits in WDCON). The watchdog timer itself is a The purpose of the watchdog timer is to generate a device reset or 16-bit counter that is clocked at 32.768kHz. The watchdog interrupt within a reasonable amount of time if the ADuC816 time-out interval can be adjusted via the PRE3–0 bits in WDCON. enters an erroneous state, possibly due to a programming error, Full Control and Status of the watchdog timer function can be electrical noise, or RFI. The Watchdog function can be disabled by controlled via the watchdog timer control SFR (WDCON). The clearing the WDE (Watchdog Enable) bit in the Watchdog Control WDCON SFR can only be written by user software if the double (WDCON) SFR. When enabled; the watchdog circuit will generate write sequence described in WDWR below is initiated on every a system reset or interrupt (WDS) if the user program fails to set write access to the WDCON SFR. the watchdog (WDE) bit within a predetermined amount of time WDCON Watchdog Timer Control Register SFR Address C0H Power-On Default Value 10H Bit Addressable Yes PRE3 PRE2 PRE1 PRE0 WDIR WDS WDE WDWR Table XVII. WDCON SFR Bit Designations Bit Name Description 7 PRE3 Watchdog Timer Prescale Bits. 6 PRE2 The Watchdog timeout period is given by the equation: t = (2PRE × (29/f )) WD PLL 5 PRE1 (0 ≤ PRE ≤ 7; f = 32.768kHz) PLL 4 PRE0 PRE3 PRE2 PRE1 PRE0Timout Period (ms) Action 0 0 0 0 15.6 Reset or Interrupt 0 0 0 1 31.2 Reset or Interrupt 0 0 1 0 62.5 Reset or Interrupt 0 0 1 1 125 Reset or Interrupt 0 1 0 0 250 Reset or Interrupt 0 1 0 1 500 Reset or Interrupt 0 1 1 0 1000 Reset or Interrupt 0 1 1 1 2000 Reset or Interrupt 1 0 0 0 0.0 Immediate Reset PRE3–0 > 1001 Reserved 3 WDIR Watchdog Interrupt Response Enable Bit. If this bit is set by the user, the watchdog will generate an interrupt response instead of a system reset when the watchdog timeout period has expired. This interrupt is not disabled by the CLR EA instruction and it is also a fixed, high-priority interrupt. If the watchdog is not being used to monitor the system, it can alternatively be used as a timer. The prescaler is used to set the timeout period in which an interrupt will be generated. (See also Note 1, Table XXXIV in the Interrupt System section.) 2 WDS Watchdog Status Bit. Set by the Watchdog Controller to indicate that a watchdog timeout has occurred. Cleared by writing a “0” or by an external hardware reset. It is not cleared by a watchdog reset. 1 WDE Watchdog Enable Bit. Set by user to enable the watchdog and clear its counters. If this bit is not set by the user within the watchdog timeout period, the watchdog will generate a reset or interrupt, depending on WDIR. Cleared under the following conditions, User writes “0,” Watchdog Reset (WDIR = “0”); Hardware Reset; PSM Interrupt. 0 WDWR Watchdog Write Enable Bit. To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the very next instruction must be a write instruction to the WDCON SFR. e.g., CLR EA ; disable interrupts while writing to WDT SETB WDWR ; allow write to WDCON MOV WDCON, #72h ; enable WDT for 2.0s timeout SET B EA ; enable interrupts again (if rqd) –46– Rev. B

ADuC816 Power Supply Monitor PSMCON SFR. This bit will not be cleared until the failing As its name suggests, the Power Supply Monitor, once enabled, power supply has returned above the trip point for at least monitors both supplies (AVDD or DVDD) on the ADuC816. It 250ms. This monitor function allows the user to save working will indicate when any of the supply pins drop below one of registers to avoid possible data loss due to the low supply condi- four user-selectable voltage trip points from 2.63V to 4.63V. tion, and also ensures that normal code execution will not For correct operation of the Power Supply Monitor function, resume until a safe supply level has been well established. The AV must be equal to or greater than 2.7V. Monitor function supply monitor is also protected against spurious glitches trig- DD is controlled via the PSMCON SFR. If enabled via the IEIP2 gering the interrupt circuit. SFR, the monitor will interrupt the core using the PSMI bit in the PSMCON Power Supply Monitor Control Register SFR Address DFH Power-On Default Value DEH Bit Addressable No CMPD CMPA PSMI TPD1 TPD0 TPA1 TPA0 PSMEN Table XVIII. PSMCON SFR Bit Designations Bit Name Description 7 CMPD DVDD Comparator Bit. This is a read-only bit and directly reflects the state of the DVDD comparator. Read “1” indicates the DVDD supply is above its selected trip point. Read “0” indicates the DVDD supply is below its selected trip point. 6 CMPA AVDD Comparator Bit. This is a read-only bit and directly reflects the state of the AVDD comparator. Read “1” indicates the AVDD supply is above its selected trip point. Read “0” indicates the AVDD supply is below its selected trip point. 5 PSMI Power Supply Monitor Interrupt Bit. This bit will be set high by the MicroConverter if either CMPA or CMPD are low, indicating low analog or digital supply. The PSMI bit can be used to interrupt the processor. Once CMPD and/or CMPA return (and remain) high, a 250ms counter is started. When this counter times out, the PSMI interrupt is cleared. PSMI can also be written by the user. However, if either com- parator output is low, it is not possible for the user to clear PSMI. 4 TPD1 DVDD Trip Point Selection Bits. 3 TPD0 These bits select the DVDD trip-point voltage as follows: TPD1 TPD0 Selected DVDD Trip Point (V) 0 0 4.63 0 1 3.08 1 0 2.93 1 1 2.63 2 TPA1 AVDD Trip Point Selection Bits. 1 TPA0 These bits select the AVDD trip-point voltage as follows: TPA1 TPA0 Selected AVDD Trip Point (V) 0 0 4.63 0 1 3.08 1 0 2.93 1 1 2.63 0 PSMEN Power Supply Monitor Enable Bit. Set to “1” by the user to enable the Power Supply Monitor Circuit. Cleared to “0” by the user to disable the Power Supply Monitor Circuit. Rev. B –47–

ADuC816 SERIAL PERIPHERAL INTERFACE each SCLOCK period. Therefore, a byte is transmitted/received The ADuC816 integrates a complete hardware Serial Peripheral after eight SCLOCK periods. The SCLOCK pin is configured Interface (SPI) interface on-chip. SPI is an industry standard syn- as an output in master mode and as an input in slave mode. In chronous serial interface that allows eight bits of data to be master mode the bit-rate, polarity and phase of the clock are synchronously transmitted and received simultaneously, i.e., full controlled by the CPOL, CPHA, SPR0 and SPR1 bits in the duplex. It should be noted that the SPI physical interface is shared SPICON SFR (see Table XIX below). In slave mode the with the I2C interface and therefore the user can only enable one SPICON register will have to be configured with the phase and or the other interface at any given time (see SPE in SPICON polarity (CPHA and CPOL) of the expected input clock. In below). The system can be configured for Master or Slave opera- both master and slave mode the data is transmitted on one edge tion and typically consists of four pins, namely: of the SCLOCK signal and sampled on the other. It is important therefore that the CPHA and CPOL are configured the same for the MISO (Master In, Slave Out Data I/O Pin), Pin 14 master and slave devices. The MISO (master in slave out) pin is configured as an input line in master mode and an output line in slave mode. The MISO SS (Slave Select Input Pin), Pin 13 line on the master (data in) should be connected to the MISO The Slave Select (SS) input pin is only used when the ADuC816 line in the slave device (data out). The data is transferred as is configured in slave mode to enable the SPI peripheral. This line byte wide (8-bit) serial data, MSB first. is active low. Data is only received or transmitted in slave mode when the SS pin is low, allowing the ADuC816 to be used in single MOSI (Master Out, Slave In Pin), Pin 27 master, multislave SPI configurations. If CPHA = 1 then the SS The MOSI (master out slave in) pin is configured as an output line input may be permanently pulled low. With CPHA = 0 then the in master mode and an input line in slave mode. The MOSI SS input must be driven low before the first bit in a byte wide line on the master (data out) should be connected to the MOSI transmission or reception and return high again after the last bit line in the slave device (data in). The data is transferred as byte in that byte wide transmission or reception. In SPI Slave Mode, wide (8-bit) serial data, MSB first. the logic level on the external SS pin (Pin 13), can be read via SCLOCK (Serial Clock I/O Pin), Pin 26 the SPR0 bit in the SPICON SFR. The master clock (SCLOCK) is used to synchronize the data The following SFR registers are used to control the SPI interface. being transmitted and received through the MOSI and MISO data lines. A single data bit is transmitted and received in SPICON: SPI Control Register SFR Address F8H Power-On Default Value 04H Bit Addressable Yes ISPI WCOL SPE SPIM CPOL CPHA SPR1 SPR0 Table XIX. SPICON SFR Bit Designations Bit Name Description 7 ISPI SPI Interrupt Bit. Set by MicroConverter at the end of each SPI transfer. Cleared directly by user code or indirectly by reading the SPIDAT SFR 6 WCOL Write Collision Error Bit. Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress. Cleared by user code. 5 SPE SPI Interface Enable Bit. Set by user to enable the SPI interface. Cleared by user to enable the I2C interface. 4 SPIM SPI Master/Slave Mode Select Bit. Set by user to enable Master Mode operation (SCLOCK is an output). Cleared by user to enable Slave Mode operation (SCLOCK is an input). 3 CPOL Clock Polarity Select Bit. Set by user if SCLOCK idles high. Cleared by user if SCLOCK idles low. 2 CPHA Clock Phase Select Bit. Set by user if leading SCLOCK edge is to transmit data. Cleared by user if trailing SCLOCK edge is to transmit data. –48– Rev. B

ADuC816 Table XIX. SPICON SFR Bit Designations (continued) Bit Name Description 1 SPR1 SPI Bit-Rate Select Bits. 0 SPR0 These bits select the SCLOCK rate (bit-rate) in Master Mode as follows: SPR1 SPR0 Selected Bit Rate 0 0 f /2 CORE 0 1 f /4 CORE 1 0 f /8 CORE 1 1 f /16 CORE In SPI Slave Mode, i.e., SPIM = 0, the logic level on the external SS pin (Pin 13), can be read via the SPR0 bit. NOTE The CPOL and CPHA bits should both contain the same values for master and slave devices. SPIDAT SPI Data Register Function The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read data just received by the SPI interface. SFR Address F7H Power-On Default Value 00H Bit Addressable No Using the SPI Interface SPI Interface—Master Mode Depending on the configuration of the bits in the SPICON SFR In master mode, the SCLOCK pin is always an output and gener- shown in Table XIX, the ADuC816 SPI interface will transmit ates a burst of eight clocks whenever user code writes to the or receive data in a number of possible modes. Figure 32 shows SPIDAT register. The SCLOCK bit rate is determined by all possible ADuC816 SPI configurations and the timing rela- SPR0 and SPR1 in SPICON. It should also be noted that the tionships and synchronization between the signals involved. SS pin is not used in master mode. If the ADuC816 needs to Also shown in this figure is the SPI interrupt bit (ISPI) and how assert the SS pin on an external slave device, a Port digital output it is triggered at the end of each byte-wide communication. pin should be used. In master mode a byte transmission or reception is initiated SCLOCK (CPOL = 1) by a write to SPIDAT. Eight clock periods are generated via the SCLOCK pin and the SPIDAT byte being transmitted via MOSI. With each SCLOCK period a data bit is also sampled via MISO. SCLOCK After eight clocks, the transmitted byte will have been completely (CPOL = 0) transmitted and the input byte will be waiting in the input shift SS register. The ISPI flag will be set automatically and an interrupt will occur if enabled. The value in the shift register will be latched SAMPLE INPUT into SPIDAT. DATA OUTPUT ? MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB (CPHA = 1) SPI Interface—Slave Mode In slave mode the SCLOCK is an input. The SS pin must ISPI FLAG also be driven low externally during the byte communication. SAMPLE INPUT Transmission is also initiated by a write to SPIDAT. In slave DATA OUTPUT MSB BIT 6 BIT 5BIT 4 BIT 3 BIT 2 BIT 1 LSB ? mode, a data bit is transmitted via MISO and a data bit is received (CPHA = 0) via MOSI through each input SCLOCK period. After eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register. The ISPI flag ISPI FLAG will be set automatically and an interrupt will occur if enabled. Figure 32.SPI Timing, All Modes The value in the shift register will be latched into SPIDAT only when the transmission/reception of a byte has been completed. The end of transmission occurs after the eighth clock has been received, if CPHA = 1 or when SS returns high if CPHA = 0. Rev. B –49–

ADuC816 I2C-COMPATIBLE INTERFACE SPICON previously). An Application Note describing the The ADuC816 supports a 2-wire serial interface mode which is operation of this interface as implemented is available from I2C compatible. The I2C-compatible interface shares its pins the MicroConverter Website at www.analog.com/microconverter. with the on-chip SPI interface and therefore the user can only This interface can be configured as a Software Master or Hard- enable one or the other interface at any given time (see SPE in ware Slave, and uses two pins in the interface. SDATA (Pin 27) Serial Data I/O Pin SCLOCK (Pin 26) Serial Clock Three SFRs are used to control the I2C-compatible interface. These are described below: I2CCON: I2C Control Register SFR Address E8H Power-On Default Value 00H Bit Addressable Yes MDO MDE MCO MDI I2CM I2CRS I2CTX I2CI Table XX. I2CCON SFR Bit Designations Bit Name Description 7 MDO I2C Software Master Data Output Bit (MASTER MODE ONLY). This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit will be output on the SDATA pin if the data output enable (MDE) bit is set. 6 MDE I2C Software Master Data Output Enable Bit (MASTER MODE ONLY). Set by user to enable the SDATA pin as an output (Tx). Cleared by the user to enable SDATA pin as an input (Rx). 5 MCO I2C Software Master Clock Output Bit (MASTER MODE ONLY). This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit will be outputted on the SCLOCK pin. 4 MDI I2C Software Master Data Input Bit (MASTER MODE ONLY). This data bit is used to implement a master I2C receiver interface in software. Data on the SDATA pin is latched into this bit on SCLOCK if the Data Output Enable (MDE) bit is ‘0.’ 3 I2CM I2C Master/Slave Mode Bit. Set by user to enable I2C software master mode. Cleared by user to enable I2C hardware slave mode. 2 I2CRS I2C Reset Bit (SLAVE MODE ONLY). Set by user to reset the I2C interface. Cleared by user code for normal I2C operation. 1 I2CTX I2C Direction Transfer Bit (SLAVE MODE ONLY). Set by the MicroConverter if the interface is transmitting. Cleared by the MicroConverter if the interface is receiving. 0 I2CI I2C Interrupt Bit (SLAVE MODE ONLY). Set by the MicroConverter after a byte has been transmitted or received. Cleared automatically when user code reads the I2CDAT SFR (see I2CDAT below). I2CADD I2C Address Register I2CDAT I2C Data Register Function Holds the I2C peripheral address for Function The I2CDAT SFR is written by the the part. It may be overwritten by user to transmit data over the I2C user code. Technical Note uC001 at interface or read by user code to read www.analog.com/microconverter data just received by the I2C interface describes the format of the I2C stan- Accessing I2CDAT automatically dard 7-bit address in detail. clears any pending I2C interrupt and SFR Address 9BH the I2CI bit in the I2CCON SFR. Power-On Default Value 55H User software should only access Bit Addressable No I2CDAT once per interrupt cycle. SFR Address 9AH Power-On Default Value 00H Bit Addressable No –50– Rev. B

ADuC816 8051-COMPATIBLE ON-CHIP PERIPHERALS address bytes during fetches from external program memory This section gives a brief overview of the various secondary periph- and middle and high order address bytes during accesses to the eral circuits are also available to the user on-chip. These remaining 16-bit external data memory space. functions are fully 8051-compatible and are controlled via standard Port 3 is a bidirectional port with internal pull-ups directly 8051 SFR bit definitions. controlled via the P2 SFR (SFR address = B0 hex). Port 3 pins Parallel I/O Ports 0–3 that have 1s written to them are pulled high by the internal pull- The ADuC816 uses four input/output ports to exchange data with ups and in that state they can be used as inputs. As inputs, Port external devices. In addition to performing general-purpose I/O, 3 pins being pulled externally low will source current because of some ports are capable of external memory operations; others are the internal pull-ups. Port 3 pins also have various secondary multiplexed with an alternate function for the peripheral features functions described in Table XXII. on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Table XXII. Port 3, Alternate Pin Functions Port 0 is an 8-bit open drain bidirectional I/O port that is directly Pin Alternate Function controlled via the Port 0 SFR (SFR address = 80 hex). Port 0 pins that have 1s written to them via the Port 0 SFR will be P3.0 RXD (UART Input Pin) configured as open drain and will therefore float. In that state, (or Serial Data I/O in Mode 0) Port 0 pins can be used as high impedance inputs. An external P3.1 TXD (UART Output Pin) pull-up resistor will be required on Port 0 outputs to force a (or Serial Clock Output in Mode 0) valid logic high level externally. Port 0 is also the multiplexed P3.2 INT0 (External Interrupt 0) low-order address and data bus during accesses to external pro- P3.3 INT1 (External Interrupt 1) gram or data memory. In this application it uses strong internal P3.4 T0 (Timer/Counter 0 External Input) pull-ups when emitting 1s. P3.5 T1 (Timer/Counter 1 External Input) P3.6 WR (External Data Memory Write Strobe) Port 1 is also an 8-bit port directly controlled via the P1 SFR P3.7 RD (External Data Memory Read Strobe) (SFR address = 90 hex). The Port 1 pins are divided into two distinct pin groupings. The alternate functions of P1.0, P1.1, and Port 3 pins can only be P1.0 and P1.1 pins on Port 1 are bidirectional digital I/O pins with activated if the corresponding bit latch in the P1 and P3 SFRs internal pull-ups. If P1.0 and P1.1 have 1s written to them via the contains a 1. Otherwise, the port pin is stuck at 0. P1 SFR, these pins are pulled high by the internal pull-up resis- Timers/Counters tors. In this state they can also be used as inputs; as input pins The ADuC816 has three 16-bit Timer/Counters: Timer 0, being externally pulled low, they will source current because of Timer 1, and Timer 2. The Timer/Counter hardware has been the internal pull-ups. With 0s written to them, both these pins included on-chip to relieve the processor core of the overhead will drive a logic low output voltage (VOL) and will be capable of inherent in implementing timer/counter functionality in soft- sinking 10mA compared to the standard 1.6mA sink capa- ware. Each Timer/Counter consists of two 8-bit registers THx and bility on the other port pins. These pins also have various TLx (x = 0, 1 and 2). All three can be configured to operate secondary functions described in Table XXI. either as timers or event counters. In “Timer” function, the TLx register is incremented every Table XXI. Port 1, Alternate Pin Functions machine cycle. Thus one can think of it as counting machine Pin Alternate Function cycles. Since a machine cycle consists of 12 core clock periods, the maximum count rate is 1/12 of the core clock frequency. P1.0 T2 (Timer/Counter 2 External Input) P1.1 T2EX (Timer/Counter 2 Capture/Reload Trigger) In “Counter” function, the TLx register is incremented by a 1-to-0 transition at its corresponding external input pin, T0, T1, The remaining Port 1 pins (P1.2–P1.7) can only be configured or T2. In this function, the external input is sampled during as Analog Input (ADC), Analog Output (DAC) or Digital Input S5P2 of every machine cycle. When the samples show a high in pins. By (power-on) default these pins are configured as Analog one cycle and a low in the next cycle, the count is incremented. Inputs, i.e., “1” written in the corresponding Port 1 register bit. The new count value appears in the register during S3P1 of the To configure any of these pins as digital inputs, the user should cycle following the one in which the transition was detected. Since write a “0” to these port bits to configure the corresponding pin it takes two machine cycles (16 core clock periods) to recognize a as a high impedance digital input. 1-to-0 transition, the maximum count rate is 1/16 of the core clock frequency. There are no restrictions on the duty cycle of Port 2 is a bidirectional port with internal pull-up resistors directly the external input signal, but to ensure that a given level is controlled via the P2 SFR (SFR address = A0 hex). Port 2 pins sampled at least once before it changes, it must be held for a mini- that have 1s written to them are pulled high by the internal pull-up mum of one full machine cycle. Remember that the core clock resistors and, in that state, they can be used as inputs. As inputs, frequency is programmed via the CD0–2 selection bits in the Port 2 pins being pulled externally low will source current because PLLCON SFR. of the internal pull-up resistors. Port 2 emits the high order Rev. B –51–

ADuC816 User configuration and control of all Timer operating modes is achieved via three SFRs namely: TMOD, TCON: Control and configuration for Timers 0 and 1. T2CON: Control and configuration for Timer 2. TMOD Timer/Counter 0 and 1 Mode Register SFR Address 89H Power-On Default Value 00H Bit Addressable No Gate C/T M1 M0 Gate C/T M1 M0 Table XXIII. TMOD SFR Bit Designations Bit Name Description 7 Gate Timer 1 Gating Control. Set by software to enable timer/counter 1 only while INT1 pin is high and TR1 control bit is set. Cleared by software to enable timer 1 whenever TR1 control bit is set. 6 C/T Timer 1 Timer or Counter Select Bit. Set by software to select counter operation (input from T1 pin). Cleared by software to select timer operation (input from internal system clock). 5 M1 Timer 1 Mode Select Bit 1 (Used with M0 Bit). 4 M0 Timer 1 Mode Select Bit 0. M1 M0 0 0 TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler. 0 1 16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler. 1 0 8-Bit Auto-Reload Timer/Counter. TH1 holds a value which is to be reloaded into TL1 each time it overflows. 1 1 Timer/Counter 1 Stopped. 3 Gate Timer 0 Gating Control. Set by software to enable timer/counter 0 only while INT0 pin is high and TR0 control bit is set. Cleared by software to enable Timer 0 whenever TR0 control bit is set. 2 C/T Timer 0 Timer or Counter Select Bit. Set by software to select counter operation (input from T0 pin). Cleared by software to select timer operation (input from internal system clock). 1 M1 Timer 0 Mode Select Bit 1. 0 M0 Timer 0 Mode Select Bit 0. M1 M0 0 0 TH0 operates as an 8-bit timer/counter. TL0 serves as 5-bit prescaler. 0 1 16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler 1 0 8-Bit Auto-Reload Timer/Counter. TH0 holds a value which is to be reloaded into TL0 each time it overflows. 1 1 TL0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. TH0 is an 8-bit timer only, controlled by Timer 1 control bits. –52– Rev. B

ADuC816 TCON: Timer/Counter 0 and 1 Control Register SFR Address 88H Power-On Default Value 00H Bit Addressable Yes TF1 TR1 TF0 TR0 IE11 IT11 IE01 IT01 NOTE 1These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins. Table XXIV. TCON SFR Bit Designations Bit Name Description 7 TF1 Timer 1 Overflow Flag. Set by hardware on a timer/counter 1 overflow. Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine. 6 TR1 Timer 1 Run Control Bit. Set by user to turn on timer/counter 1. Cleared by user to turn off timer/counter 1. 5 TF0 Timer 0 Overflow Flag. Set by hardware on a timer/counter 0 overflow. Cleared by hardware when the PC vectors to the interrupt service routine. 4 TR0 Timer 0 Run Control Bit. Set by user to turn on timer/counter 0. Cleared by user to turn off timer/counter 0. 3 IE1 External Interrupt 1 (INT1) Flag. Set by hardware by a falling edge or zero level being applied to external interrupt pin INT1, depend- ing on bit IT1 state. Cleared by hardware when the when the PC vectors to the interrupt service routine only if the inter- rupt was transition-activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip hardware. 2 IT1 External Interrupt 1 (IE1) Trigger Type. Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). Cleared by software to specify level-sensitive detection (i.e., zero level). 1 IE0 External Interrupt 0 (INT0) Flag. Set by hardware by a falling edge or zero level being applied to external interrupt pin INT0, depend- ing on bit IT0 state. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip hardware. 0 IT0 External Interrupt 0 (IE0) Trigger Type. Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). Cleared by software to specify level-sensitive detection (i.e., zero level). Timer/Counter 0 and 1 Data Registers Each timer consists of two 8-bit registers. These can be used as independent registers or combined to be a single 16-bit register depending on the timer mode configuration. TH0 and TL0 Timer 0 high byte and low byte. SFR Address = 8Chex, 8Ahex respectively. TH1 and TL1 Timer 1 high byte and low byte. SFR Address = 8Dhex, 8Bhex respectively. Rev. B –53–

ADuC816 TIMER/COUNTER 0 AND 1 OPERATING MODES Mode 2 (8-Bit Timer/Counter with Autoreload) The following paragraphs describe the operating modes for timer/ Mode 2 configures the timer register as an 8-bit counter (TL0) counters 0 and 1. Unless otherwise noted, it should be assumed with automatic reload, as shown in Figure 35. Overflow from TL0 that these modes of operation are the same for timer 0 as for timer 1. not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged. Mode 0 (13-Bit Timer/Counter) Mode 0 configures an 8-bit timer/counter with a divide-by-32 prescaler. Figure 33 shows mode 0 operation. CORE (cid:9) 12 CLK* C/T = 0 CCOLKR*E (cid:9) 12 (8 TBLIT0S) TF0 C/T = 0 C/T = 1 TL0 TH0 P3.4/T0 (5 BITS) (8 BITS) CONTROL C/T = 1 TR0 INTERRUPT P3.4/T0 INTERRUPT CONTROL TF0 RELOAD TR0 GATE TH0 P3.2/INT0 (8 BITS) *THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42. GATE P3.2/INT0 Figure 35.Timer/Counter 0, Mode 2 *THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42. Mode 3 (Two 8-Bit Timer/Counters) Figure 33.Timer/Counter 0, Mode 0 Mode 3 has different effects on timer 0 and timer 1. Timer 1 in Mode 3 simply holds its count. The effect is the same as setting In this mode, the timer register is configured as a 13-bit register. TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two As the count rolls over from all 1s to all 0s, it sets the timer overflow separate counters. This configuration is shown in Figure 36. TL0 flag TF0. The overflow flag, TF0, can then be used to request an uses the timer 0 control bits: C/T, Gate, TR0, INT0, and TF0. interrupt. The counted input is enabled to the timer when TR0 = 1 TH0 is locked into a timer function (counting machine cycles) and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the timer and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 to be controlled by external input INT0, to facilitate pulsewidth now controls the “timer 1” interrupt. Mode 3 is provided for measurements. TR0 is a control bit in the special function regis- applications requiring an extra 8-bit timer or counter. ter TCON; Gate is in TMOD. The 13-bit register consists of all eight bits of TH0 and the lower five bits of TL0. The upper three When timer 0 is in Mode 3, timer 1 can be turned on and off by bits of TL0 are indeterminate and should be ignored. Setting the switching it out of, and into, its own Mode 3, or can still be used by run flag (TR0) does not clear the registers. the serial interface as a Baud Rate Generator. In fact, it can be used, in any application not requiring an interrupt from timer 1 itself. Mode 1 (16-Bit Timer/Counter) Mode 1 is the same as Mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in Figure 34. CORE (cid:9) 12 CORE CLK* CLK/12 C/T = 0 CCOLKR*E (cid:9) 12 (8 TBLIT0S) C/T = 0 C/T = 1 TL0 TH0 P3.4/T0 INTERRUPT (8 BITS) (8 BITS) TR0 CONTROL TF0 C/T = 1 P3.4/T0 CONTROL TF0 INTERRUPT GATE TF1 INTERRUPT TR0 P3.2/INT0 GATE CORE TH0 P3.2/INT0 CLK/12 (8 BITS) *THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42. TR1 CONTROL Figure 34.Timer/Counter 0, Mode 1 *THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42. Figure 36.Timer/Counter 0, Mode 3 –54– Rev. B

ADuC816 T2CON Timer/Counter 2 Control Register SFR Address C8H Power-On Default Value 00H Bit Addressable Yes TF2 EXF2 RCLK TCLK EXEN2 TR2 CNT2 CAP2 Table XXV. T2CON SFR Bit Designations Bit Name Description 7 TF2 Timer 2 Overflow Flag. Set by hardware on a timer 2 overflow. TF2 will not be set when either RCLK or TCLK = 1. Cleared by user software. 6 EXF2 Timer 2 External Flag. Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. Cleared by user user software. 5 RCLK Receive Clock Enable Bit. Set by user to enable the serial port to use timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. Cleared by user to enable timer 1 overflow to be used for the receive clock. 4 TCLK Transmit Clock Enable Bit. Set by user to enable the serial port to use timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. Cleared by user to enable timer 1 overflow to be used for the transmit clock. 3 EXEN2 Timer 2 External Enable Flag. Set by user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. Cleared by user for Timer 2 to ignore events at T2EX. 2 TR2 Timer 2 Start/Stop Control Bit. Set by user to start timer 2. Cleared by user to stop timer 2. 1 CNT2 Timer 2 Timer or Counter Function Select Bit. Set by user to select counter function (input from external T2 pin). Cleared by user to select timer function (input from on-chip core clock). 0 CAP2 Timer 2 Capture/Reload Select Bit. Set by user to enable captures on negative transitions at T2EX if EXEN2 = 1. Cleared by user to enable auto-reloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow. Timer/Counter 2 Data Registers Timer/Counter 2 also has two pairs of 8-bit data registers associated with it. These are used as both timer data registers and timer capture/reload registers. TH2 and TL2 Timer 2, data high byte and low byte. SFR Address = CDhex, CChex respectively. RCAP2H and RCAP2L Timer 2, Capture/Reload byte and low byte. SFR Address = CBhex, CAhex respectively. Rev. B –55–

ADuC816 Timer/Counter 2 Operating Modes 16-Bit Capture Mode The following paragraphs describe the operating modes for timer/ In the “Capture” mode, there are again two options, which are counter 2. The operating modes are selected by bits in the T2CON selected by bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 SFR as shown in Table XXVI. is a 16-bit timer or counter which, upon overflowing, sets bit TF2, the Timer 2 overflow bit, which can be used to generate an inter- Table XXVI. TIMECON SFR Bit Designations rupt. If EXEN2 = 1, then Timer 2 still performs the above, but a l-to-0 transition on external input T2EX causes the current value RCLK (or) TCLK CAP2 TR2 MODE in the Timer 2 registers, TL2 and TH2, to be captured into regis- 0 0 1 16-Bit Autoreload ters RCAP2L and RCAP2H, respectively. In addition, the 0 1 1 16-Bit Capture transition at T2EX causes bit EXF2 in T2CON to be set, and 1 X 1 Baud Rate EXF2, like TF2, can generate an interrupt. The Capture Mode X X 0 OFF is illustrated in Figure 38. The baud rate generator mode is selected by RCLK = 1 and/or 16-Bit Autoreload Mode TCLK = 1. In “Autoreload” mode, there are two options, which are selected In either case if Timer 2 is being used to generate the baud rate, by bit EXEN2 in T2CON. If EXEN2 = 0, then when Timer 2 the TF2 interrupt flag will not occur. Hence Timer 2 interrupts rolls over it not only sets TF2 but also causes the Timer 2 registers will not occur so they do not have to be disabled. In this mode to be reloaded with the 16-bit value in registers RCAP2L and the EXF2 flag, however, can still cause interrupts and this can RCAP2H, which are preset by software. If EXEN2 = 1, then be used as a third external interrupt. Timer 2 still performs the above, but with the added feature that a 1-to-0 transition at external input T2EX will also trigger the Baud rate generation will be described as part of the UART 16-bit reload and set EXF2. The autoreload mode is illustrated serial port operation in the following pages. in Figure 37 below. CORE 12 CLK* C/T2 = 0 TL2 TH2 (8 BITS) (8 BITS) T2 C/T2 = 1 PIN CONTROL TR2 RELOAD TRANSITION DETECTOR RCAP2L RCAP2H TF2 TIMER INTERRUPT T2EX EXF2 PIN CONTROL EXEN2 *THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42. Figure 37.Timer/Counter 2, 16-Bit Autoreload Mode CORE 12 CLK* C/T2 = 0 TL2 TH2 (8 BITS) (8 BITS) TF2 T2 C/T2 = 1 PIN CONTROL TR2 CAPTURE TIMER TRANSITION INTERRUPT DETECTOR RCAP2L RCAP2H T2EX EXF2 PIN CONTROL EXEN2 *THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42. Figure 38.Timer/Counter 2, 16-Bit Capture Mode –56– Rev. B

ADuC816 UART SERIAL INTERFACE while the SFR interface to the UART is comprised of the fol- The serial port is full duplex, meaning it can transmit and receive lowing registers. simultaneously. It is also receive-buffered, meaning it can SBUF commence reception of a second byte before a previously received The serial port receive and transmit registers are both accessed byte has been read from the receive register. However, if the first through the SBUF SFR (SFR address = 99 hex). Writing to byte still has not been read by the time reception of the second SBUF loads the transmit register and reading SBUF accesses a byte is complete, the first byte will be lost. The physical interface physically separate receive register. to the serial data network is via Pins RXD(P3.0) and TXD(P3.1) SCON UART Serial Port Control Register SFR Address 98H Power-On Default Value 00H Bit Addressable Yes SM0 SM1 SM2 REN TB8 RB8 TI RI Table XXVII. SCON SFR Bit Designations Bit Name Description 7 SM0 UART Serial Mode Select Bits. 6 SM1 These bits select the Serial Port operating mode as follows: SM0 SM1 Selected Operating Mode 0 0 Mode 0: Shift Register, fixed baud rate (Core_Clk/2) 0 1 Mode 1: 8-bit UART, variable baud rate 1 0 Mode 2: 9-bit UART, fixed baud rate (Core_Clk/64) or (Core_Clk/32) 1 1 Mode 3: 9-bit UART, variable baud rate 5 SM2 Multiprocessor Communication Enable Bit. Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared. In Mode 1, if SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is cleared, RI will be set as soon as the byte of data has been received. In Modes 2 or 3, if SM2 is set, RI will not be activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI will be set as soon as the byte of data has been received. 4 REN Serial Port Receive Enable Bit. Set by user software to enable serial port reception. Cleared by user software to disable serial port reception. 3 TB8 Serial Port Transmit (Bit 9). The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3. 2 RB8 Serial port Receiver Bit 9. The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1 the stop bit is latched into RB8. 1 TI Serial Port Transmit Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3. TI must be cleared by user software. 0 RI Serial Port Receive Interrupt Flag. Set by hardware at the end of the eighth bit in mode 0, or halfway through the stop bit in Modes 1, 2, and 3. RI must be cleared by software. Rev. B –57–

ADuC816 Mode 0: 8-Bit Shift Register Mode Mode 2: 9-Bit UART with Fixed Baud Rate Mode 0 is selected by clearing both the SM0 and SM1 bits in Mode 2 is selected by setting SM0 and clearing SM1. In this the SFR SCON. Serial data enters and exits through RXD. TXD mode the UART operates in 9-bit mode with a fixed baud rate. outputs the shift clock. Eight data bits are transmitted or received. The baud rate is fixed at Core_Clk/64 by default, although by Transmission is initiated by any instruction that writes to SBUF. setting the SMOD bit in PCON, the frequency can be doubled to The data is shifted out of the RXD line. The eight bits are trans- Core_Clk/32. Eleven bits are transmitted or received, a start bit(0), mitted with the least-significant bit (LSB) first, as shown in eight data bits, a programmable ninth bit and a stop bit(1). The Figure 39. ninth bit is most often used as a parity bit, although it can be used for anything, including a ninth data bit if required. MACHINE MACHINE MACHINE MACHINE CYCLE 1 CYCLE 2 CYCLE 7 CYCLE 8 To transmit, the eight data bits must be written into SBUF. The S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S4 S5 S6 S1 S2 S3 S4 S5 S6 ninth bit must be written to TB8 in SCON. When transmission is CORE initiated the eight data bits (from SBUF) are loaded onto the CLK transmit shift register (LSB first). The contents of TB8 are loaded ALE into the ninth bit position of the transmit shift register. The trans- RXD mission will start at the next valid baud rate clock. The TI flag (DATA OUT) DATA BIT 0 DATA BIT 1 DATA BIT 6 DATA BIT 7 is set as soon as the stop bit appears on TXD. TXD (SHIFT CLOCK) Reception for Mode 2 is similar to that of Mode 1. The eight data bytes are input at RXD (LSB first) and loaded onto the Figure 39.UART Serial Port Transmission, Mode 0 receive shift register. When all eight bits have been clocked in, Reception is initiated when the receive enable bit (REN) is 1 and the following events occur: the receive interrupt bit (RI) is 0. When RI is cleared the data is The eight bits in the receive shift register are latched into SBUF clocked into the RXD line and the clock pulses are output from the TXD line. The ninth data bit is latched into RB8 in SCON Mode 1: 8-Bit UART, Variable Baud Rate The Receiver interrupt flag (RI) is set Mode 1 is selected by clearing SM0 and setting SM1. Each data if, and only if, the following conditions are met at the time the byte (LSB first) is preceded by a start bit(0) and followed by a stop final shift pulse is generated: bit(1). Therefore 10 bits are transmitted on TXD or received on RI = 0, and RXD. The baud rate is set by the Timer 1 or Timer 2 overflow rate, or a combination of the two (one for transmission and the Either SM2 = 0, or SM2 = 1 and the received stop bit = 1. other for reception). If either of these conditions is not met, the received frame is Transmission is initiated by writing to SBUF. The “write to irretrievably lost, and RI is not set. SBUF” signal also loads a 1 (stop bit) into the ninth bit position Mode 3: 9-Bit UART with Variable Baud Rate of the transmit shift register. The data is output bit by bit until Mode 3 is selected by setting both SM0 and SM1. In this mode the stop bit appears on TXD and the transmit interrupt flag (TI) the 8051 UART serial port operates in 9-bit mode with a variable is automatically set as shown in Figure 40. baud rate determined by either Timer 1 or Timer 2. The opera- START STOP BIT tion of the 9-bit UART is the same as for Mode 2 but the baud BIT D0 D1 D2 D3 D4 D5 D6 D7 rate can be varied as for Mode 1. TXD In all four modes, transmission is initiated by any instruction that TI (SCON.1) uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in SET INTERRUPT i.e., READY FOR MORE DATA the other modes by the incoming start bit if REN = 1. Figure 40.UART Serial Port Transmission, Mode 0 UART Serial Port Baud Rate Generation Reception is initiated when a 1-to-0 transition is detected on Mode 0 Baud Rate Generation RXD. Assuming a valid start bit was detected, character reception The baud rate in Mode 0 is fixed: continues. The start bit is skipped and the eight data bits are Mode 0 Baud Rate = (Core Clock Frequency1/12) clocked into the serial port shift register. When all eight bits have been clocked in, the following events occur: NOTE 1In these descriptions Core Clock Frequency refers to the core clock frequency The eight bits in the receive shift register are latched into SBUF selected via the CD0–2 bits in the PLLCON SFR. The ninth bit (Stop bit) is clocked into RB8 in SCON Mode 2 Baud Rate Generation The baud rate in Mode 2 depends on the value of the SMOD bit The Receiver interrupt flag (RI) is set in the PCON SFR. If SMOD = 0, the baud rate is 1/64 of the core if, and only if, the following conditions are met at the time the clock. If SMOD = 1, the baud rate is 1/32 of the core clock: final shift pulse is generated: Mode 2 Baud Rate = (2SMOD/64) × (Core Clock Frequency) RI = 0, and Modes 1 and 3 Baud Rate Generation Either SM2 = 0, or SM2 = 1 and the received stop bit = 1. The baud rates in Modes 1 and 3 are determined by the overflow If either of these conditions is not met, the received frame is rate in Timer 1 or Timer 2, or both (one for transmit and the irretrievably lost, and RI is not set. other for receive). –58– Rev. B

ADuC816 Timer 1 Generated Baud Rates Modes 1 and 3 Baud Rate = (1/16) × (Timer 2 Overflow Rate) When Timer 1 is used as the baud rate generator, the baud rates Therefore, when Timer 2 is used to generate baud rates, the timer in Modes 1 and 3 are determined by the Timer 1 overflow rate and increments every two clock cycles and not every core machine the value of SMOD as follows: cycle as before. Hence, it increments six times faster than Timer Modes 1 and 3 Baud Rate = (2SMOD/32) × (Timer 1 Overflow Rate) 1, and therefore baud rates six times faster are possible. Because Timer 2 has 16-bit autoreload capability, very low baud rates The Timer 1 interrupt should be disabled in this application. The are still possible. Timer itself can be configured for either timer or counter opera- tion, and in any of its three running modes. In the most typical Timer 2 is selected as the baud rate generator by setting the TCLK application, it is configured for timer operation, in the autoreload and/or RCLK in T2CON. The baud rates for transmit and receive mode (high nibble of TMOD = 0100Binary). In that case, the baud can be simultaneously different. Setting RCLK and/or TCLK puts rate is given by the formula: Timer 2 into its baud rate generator mode as shown in Figure 41. Modes 1 and 3 Baud Rate = In this case, the baud rate is given by the formula: (2SMOD/32) × (Core Clock/(12 × [256-TH1])) Modes 1 and 3 Baud Rate A very low baud rate can also be achieved with Timer 1 by leaving = (Core Clk)/(32 × [65536 – (RCAP2H, RCAP2L)]) the Timer 1 interrupt enabled, and configuring the timer to run Table XXIX shows some commonly used baud rates and how they as a 16-bit timer (high nibble of TMOD = 0100Binary), and using might be calculated from a core clock frequency of 1.5728MHz the Timer 1 interrupt to do a 16-bit software reload. Table XXVIII and 12.5829MHz. below, shows some commonly-used baud rates and how they might be calculated from a core clock frequency of 1.5728MHz Table XXIX. Commonly Used Baud Rates, Timer 2 and 12.58MHz. Generally speaking, a 5% error is tolerable using asynchronous (start/stop) communications. Ideal Core RCAP2H RCAP2L Actual % Baud CLK Value Value Baud Error Table XXVIII. Commonly-Used Baud Rates, Timer 1 19200 12.58 –1 (FFh) –20 (ECh) 19661 2.4 Ideal Core SMOD TH1-Reload Actual % 9600 12.58 –1 (FFh) –41 (D7h) 9591 0.1 Baud CLK Value Value Baud Error 2400 12.58 –1 (FFh) –164 (5Ch) 2398 0.1 1200 12.58 –2 (FEh) –72 (B8h) 1199 0.1 9600 12.58 1 –7 (F9h) 9362 2.5 9600 1.57 –1 (FFh) –5 (FBh) 9830 2.4 2400 12.58 1 –27 (E5h) 2427 1.1 2400 1.57 –1 (FFh) –20 (ECh) 2457 2.4 1200 12.58 1 –55 (C9h) 1192 0.7 1200 1.57 –1 (FFh) –41 (D7h) 1199 0.1 1200 1.57 1 –7 (F9h) 1170 2.5 Timer 2 Generated Baud Rates Baud rates can also be generated using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted/received. Because Timer 2 has a 16-bit autoreload mode a wider range of baud rates is possible using Timer 2. TIMER 1 OVERFLOW 2 NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12. 0 1 SMOD CCOLKR*E 2 C/T2 = 0 CONTROL TIMER 2 TL2 TH2 OVERFLOW 1 0 (8 BITS) (8 BITS) RCLK T2 C/T2 = 1 16 RX PIN CLOCK 1 0 TR2 TCLK RELOAD 16 TX CLOCK RCAP2L RCAP2H NOTE AVAILABILITY OF ADDITIONAL EXTERNAL INTERRUPT T2EX EXF TIMER 2 PIN 2 INTERRUPT CONTROL TRANSITION DETECTOR EXEN2 *THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42. Figure 41.Timer 2, UART Baud Rates Rev. B –59–

ADuC816 INTERRUPT SYSTEM The ADuC816 provides a total of twelve interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three Interrupt-related SFRs. IE: Interrupt Enable Register. IP: Interrupt Priority Register. IEIP2: Secondary Interrupt Priority-Interrupt Register. IE: Interrupt Enable Register SFR Address A8H Power-On Default Value 00H Bit Addressable Yes EA EADC ET2 ES ET1 EX1 ET0 EX0 Table XXX. IE SFR Bit Designations Bit Name Description 7 EA Written by User to Enable “1” or Disable “0” All Interrupt Sources 6 EADC Written by User to Enable “1” or Disable “0” ADC Interrupt 5 ET2 Written by User to Enable “1” or Disable “0” Timer 2 Interrupt 4 ES Written by User to Enable “1” or Disable “0” UART Serial Port Interrupt 3 ET1 Written by User to Enable “1” or Disable “0” Timer 1 Interrupt 2 EX1 Written by User to Enable “1” or Disable “0” External Interrupt 1 1 ET0 Written by User to Enable “1” or Disable “0” Timer 0 Interrupt 0 EX0 Written by User to Enable “1” or Disable “0” External Interrupt 0 IP: Interrupt Priority Register SFR Address B8H Power-On Default Value 00H Bit Addressable Yes --- PADC PT2 PS PT1 PX1 PT0 PX0 Table XXXI. IP SFR Bit Designations Bit Name Description 7 --- Reserved for Future Use. 6 PADC Written by User to Select ADC Interrupt Priority (“1” = High; “0” = Low) 5 PT2 Written by User to Select Timer 2 Interrupt Priority (“1” = High; “0” = Low) 4 PS Written by User to Select UART Serial Port Interrupt Priority (“1” = High; “0” = Low) 3 PT1 Written by User to Select Timer 1 Interrupt Priority (“1” = High; “0” = Low) 2 PX1 Written by User to Select External Interrupt 1 Priority (“1” = High; “0” = Low) 1 PT0 Written by User to Select Timer 0 Interrupt Priority (“1” = High; “0” = Low) 0 PX0 Written by User to Select External Interrupt 0 Priority (“1” = High; “0” = Low) –60– Rev. B

ADuC816 IEIP2: Secondary Interrupt Enable and Priority Register SFR Address A9H Power-On Default Value A0H Bit Addressable No --- PTI PPSM PSI --- ETI EPSM ESI Table XXXII. IEIP2 SFR Bit Designations Bit Name Description 7 --- Reserved for Future Use. 6 PTI Written by User to Select TIC Interrupt Priority (“1” = High; “0” = Low). 5 PPSM Written by User to Select Power Supply Monitor Interrupt Priority (“1” = High; “0” = Low). 4 PSI Written by User to Select SPI/I2C Serial Port Interrupt Priority (“1” = High; “0” = Low). 3 --- Reserved, This Bit Must Be “0.” 2 ETI Written by User to Enable “1” or Disable “0” TIC Interrupt. 1 EPSM Written by User to Enable “1” or Disable “0” Power Supply Monitor Interrupt. 0 ESI Written by User to Enable “1” or Disable “0” SPI/I2C Serial Port Interrupt. Interrupt Priority Table XXXIV. Interrupt Vector Addresses The Interrupt Enable registers are written by the user to enable Source Vector Address individual interrupt sources, while the Interrupt Priority registers allow the user to select one of two priority levels for each interrupt. IE0 0003 Hex An interrupt of a high priority may interrupt the service routine TF0 000B Hex of a low priority interrupt, and if two interrupts of different priority IE1 0013 Hex occur at the same time, the higher level interrupt will be serviced TF1 001B Hex first. An interrupt cannot be interrupted by another interrupt of RI + TI 0023 Hex the same priority level. If two interrupts of the same priority level TF2 + EXF2 002B Hex occur simultaneously, a polling sequence is observed as shown RDY0/RDY1 (ADC) 0033 Hex in Table XXXIII. II2C + ISPI 003B Hex PSMI 0043 Hex Table XXXIII. Priority within an Interrupt Level TII 0053 Hex WDS (WDIR = 1)* 005B Hex Source Priority Description *The watchdog can be configured to generate an interrupt instead of a reset when it PSMI 1 (Highest) Power Supply Monitor Interrupt times out. This is used for logging errors or to examine the internal status of the WDS 2 Watchdog Interrupt microcontroller core to understand, from a software debug point of view, why a IE0 3 External Interrupt 0 watchdog timeout occurred. The watchdog interrupt is slightly different from the normal interrupts in that its priority level is always set to 1 and it is not possible RDY0/RDY1 4 ADC Interrupt to disable the interrupt via the global disable bit (EA) in the IE SFR. This is TF0 5 Timer/Counter 0 Interrupt done to ensure that the interrupt will always be responded to if a watchdog IE1 6 External Interrupt 1 timeout occurs. The watchdog will only produce an interrupt if the watch- TF1 7 Timer/Counter 1 Interrupt dog timeout is greater than zero. I2CI + ISPI 8 I2C/SPI Interrupt RI + TI 9 Serial Interrupt TF2 + EXF2 10 Timer/Counter 2 Interrupt TII 11 (Lowest) Time Interval Counter Interrupt Interrupt Vectors When an interrupt occurs the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter. The interrupt vector addresses are shown in Table XXXIV. Rev. B –61–

ADuC816 ADuC816 HARDWARE DESIGN CONSIDERATIONS time that the low byte of the program counter is valid on P0, the This section outlines some of the key hardware design consider- signal ALE (Address Latch Enable) clocks this byte into an ations that must be addressed when integrating the ADuC816 address latch. Meanwhile, Port 2 (P2) emits the high byte of the into any hardware system. program counter (PCH), then PSEN strobes the EPROM and the code byte is read into the ADuC816. Clock Oscillator As described earlier, the core clock frequency for the ADuC816 is generated from an on-chip PLL that locks onto a multiple ADuC816 EPROM (384 times) of 32.768 kHz. The latter is generated from an inter- D0–D7 nal clock oscillator. To use the internal clock oscillator, connect P0 (INSTRUCTION) a 32.768 kHz parallel resonant crystal between XTAL1 and LATCH A0–A7 XTAL2 pins (32 and 33) as shown in Figure 42. ALE As shown in the typical external crystal connection diagram in Figure 42, two internal 12 pF capacitors are provided on-chip. These are connected internally, directly to the XTAL1 and P2 A8–A15 XTAL2 pins and the total input capacitances at both pins is PSEN OE detailed in the specification section of this data sheet. The value of the total load capacitance required for the external crystal should be the value recommended by the crystal manufacturer for use Figure 43.External Program Memory Interface with that specific crystal. In many cases, because of the on-chip capacitors, additional external load capacitors will not be required. Note that program memory addresses are always 16 bits wide, even in cases where the actual amount of program memory used is less than 64Kbytes. External program execution sacrifices two of the ADuC816 8-bit ports (P0 and P2) to the function of addressing the program XTAL1 memory. While executing from external program memory, Ports 32.768kHz 12pF 0 and 2 can be used simultaneously for read/write access to exter- nal data memory, but not for general-purpose I/O. TO INTERNAL Though both external program memory and external data memory XTAL2 12pF PLL are accessed by some of the same pins, the two are completely independent of each other from a software point of view. For Figure 42.External Parallel Resonant Crystal Connections example, the chip can read/write external data memory while executing from external program memory. External Memory Interface In addition to its internal program and data memories, the Figure 44 shows a hardware configuration for accessing up to ADuC816 can access up to 64Kbytes of external program memory 64Kbytes of external RAM. This interface is standard to any 8051 (ROM/PROM/etc.) and up to 16Mbytes of external data compatible MCU. memory (SRAM). To select from which code space (internal or external program ADuC816 SRAM memory) to begin executing instructions, tie the EA (external D0–D7 access) pin high or low, respectively. When EA is high (pulled up P0 (DATA) to V ), user program execution will start at address 0 of the LATCH DD A0–A7 internal 8Kbytes Flash/EE code space. When EA is low (tied to ALE ground) user program execution will start at address 0 of the external code space. In either case, addresses above 1FFF hex P2 A8–A15 (8K) are mapped to the external space. Note that a second very important function of the EA pin is RD OE described in the Single Pin Emulation Mode section of this WR WE data sheet. External program memory (if used) must be connected to the Figure 44.External Data Memory Interface (64K Address ADuC816 as illustrated in Figure 43. Note that 16 I/O lines Space) (Ports 0 and 2) are dedicated to bus functions during external If access to more than 64Kbytes of RAM is desired, a feature program memory fetches. Port 0 (P0) serves as a multiplexed unique to the ADuC816 allows addressing up to 16Mbytes address/data bus. It emits the low byte of the program counter of external RAM simply by adding an additional latch as illustrated (PCL) as an address, and then goes into a float state awaiting in Figure 45. the arrival of the code byte from the program memory. During the –62– Rev. B

ADuC816 ADuC816 SRAM ADuC816 POWER SUPPLY 20 D0–D7 P0 (DATA) 34DVDD LATCH 48 A0–A7 ALE POR (ACTIVE HIGH) 15 RESET P2 A8–A15 LATCH A16–A23 Figure 47.External Active High POR Circuit Some active-low POR chips, such as the ADM809 can be used with a manual push-button as an additional reset source as illustrated RD OE WR WE by the dashed line connection in Figure 48. Figure 45.External Data Memory Interface (16M Bytes ADuC816 POWER SUPPLY Address Space) 20 In either implementation, Port 0 (P0) serves as a multiplexed 1k(cid:8) 34DVDD address/data bus. It emits the low byte of the data pointer (DPL) as 48 POR an address, which is latched by a pulse of ALE prior to data being (ACTIVE LOW) placed on the bus by the ADuC816 (write operation) or the 15 RESET SRAM (read operation). Port 2 (P2) provides the data pointer OPTIONAL page byte (DPP) to be latched by ALE, followed by the data MANUAL RESET pointer high byte (DPH). If no latch is connected to P2, DPP is PUSH-BUTTON ignored by the SRAM, and the 8051 standard of 64Kbyte external Figure 48.External Active Low POR Circuit data memory access is maintained. Power Supplies Detailed timing diagrams of external program and data memory The ADuC816’s operational power supply voltage range is 2.7V read and write access can be found in the timing specification to 5.25V. Although the guaranteed data sheet specifications are sections of this data sheet. given only for power supplies within 2.7V to 3.6V or +5% of Power-On Reset Operation the nominal 5V level, the chip will function equally well at any External POR (power-on reset) circuitry must be implemented to power supply level between 2.7V and 5.25V. drive the RESET pin of the ADuC816. The circuit must hold Separate analog and digital power supply pins (AV and DV the RESET pin asserted (high) whenever the power supply DD DD respectively) allow AV to be kept relatively free of noisy digital (DV ) is below 2.5V. Furthermore, V must remain above DD DD DD signals often present on the system DVDD line. In this mode the 2.5V for at least 10ms before the RESET signal is deasserted part can also operate with split supplies; that is, using different (low) by which time the power supply must have reached at voltage supply levels for each supply. For example, this means that least a 2.7V level. The external POR circuit must be opera- the system can be designed to operate with a DV voltage level tional down to 1.2 V or less. The timing diagram of Figure 46 DD of 3V while the AV level can be at 5V or vice-versa if required. illustrates this functionality under three separate events: power- DD A typical split supply configuration is shown in Figure 49. up, brownout, and power-down. Notice that when RESET is asserted (high) it tracks the voltage on DV . DD DIGITAL SUPPLY ANALOG SUPPLY 10(cid:5)F 10(cid:5)F + + 2.5V MIN – – DVDD ADuC816 1.2V MAX 10ms 10ms 1.2V MAX 20 MIN MIN 34 DVDD AVDD 5 0.1(cid:5)F 48 0.1(cid:5)F RESET 21 AGND 6 35 DGND 47 Figure 46.External POR Timing The best way to implement an external POR function to meet the Figure 49.External Dual Supply Connections above requirements involves the use of a dedicated POR chip, such as the ADM809/ADM810 SOT-23 packaged PORs from Analog Devices. Recommended connection diagrams for both active-high ADM810 and active-low ADM809 PORs are shown in Figure 47 and Figure 48, respectively. Rev. B –63–

ADuC816 As an alternative to providing two separate power supplies, AV In power-down mode, both the PLL and the clock to the core DD quiet by placing a small series resistor and/or ferrite bead between are stopped. The on-chip oscillator can be halted or can continue it and DV , and then decoupling AV separately to ground. An to oscillate depending on the state of the oscillator power-down DD DD example of this configuration is shown in Figure 50. With this bit (OSC_PD) in the PLLCON SFR. The TIC, being driven configuration other analog circuitry (such as op amps, voltage directly from the oscillator, can also be enabled during power- reference, etc.) can be powered from the AV supply line as well. down. All other on-chip peripherals however, are shut down. DD Port pins retain their logic levels in this mode, but the DAC output DIGITAL SUPPLY goes to a high-impedance state (three-state) while ALE and +– 10(cid:5)F BEAD 1.6(cid:8) 10(cid:5)F PthSeE AND ouuCtp81u6ts caornes uhmeldes l oa wto. tDal uorfi n5gμ Afu ltly ppiocwalelyr.- dTohwenre m aroed feiv,e ADuC816 ways of terminating power-down mode: 20 34 DVDD AVDD 5 0.1(cid:5)F Asserting the RESET Pin (15) 48 Returns to normal mode all registers are set to their default state 0.1(cid:5)F and program execution starts at the reset vector once the Reset 21 pin is deasserted. 35 DGND 47 AGND 6 Cycling Power All registers are set to their default state and program execution starts at the reset vector. Figure 50.External Single Supply Connections Time Interval Counter (TIC) Interrupt Notice that in both Figure 49 and Figure 50, a large value (10μF) Power-down mode is terminated and the CPU services the TIC reservoir capacitor sits on DVDD and a separate 10μF capacitor interrupt, the RETI at the end of the TIC Interrupt Service sits on AVDD. Also, local small-value (0.1μF) capacitors are Routine will return the core to the instruction after that which located at each VDD pin of the chip. As per standard design prac- enabled power down. tice, be sure to include all of these capacitors, and ensure the I2C or SPI Interrupt smaller capacitors are closest to each AV pin with trace lengths DD Power-down mode is terminated and the CPU services the I2C/ as short as possible. Connect the ground terminal of each of these SPI interrupt. The RETI at the end of the ISR will return the capacitors directly to the underlying ground plane. Finally, it core to the instruction after that which enabled power down. It should also be noticed that, at all times, the analog and digital should be noted that the I2C/SPI power down interrupt enable ground pins on the ADuC816 should be referenced to the same bit (SERIPD) in the PCON SFR must first be set to allow this system ground reference point. mode of operation. Power Consumption INT0 Interrupt The “CORE” values given represent the current drawn by DV , DD Power-down mode is terminated and the CPU services the INT0 while the rest (“ADC” and “DAC”) are pulled by the AV pin DD interrupt. The RETI at the end of the ISR will return the core and can be disabled in software when not in use. The other to the instruction after that which enabled power-down. It on-chip peripherals (watchdog timer, power supply monitor, etc.) should be noted that the INT0 power-down interrupt enable bit consume negligible current and are therefore lumped in with the (INT0PD) in the PCON SFR must first be set to allow this “CORE” operating current here. Of course, the user must add mode of operation. any currents sourced by the parallel and serial I/O pins, and that sourced by the DAC, in order to determine the total current Grounding and Board Layout Recommendations needed at the ADuC816’s supply pins. Also, current draw from As with all high resolution data converters, special attention must the DVDD supply will increase by approximately 5mA during be paid to grounding and PC board layout of ADuC816-based Flash/EE erase and program cycles designs in order to achieve optimum performance from the ADCs and DAC. Power-Saving Modes Setting the Idle and Power-Down Mode bits, PCON.0 and Although the ADuC816 has separate pins for analog and digital PCON.1 respectively, in the PCON SFR described in Table II, ground (AGND and DGND), the user must not tie these to two allows the chip to be switched from normal mode into idle mode, separate ground planes unless the two ground planes are con- and also into full power-down mode. nected together very close to the ADuC816, as illustrated in the simplified example of Figure 51a. In systems where digital and In idle mode, the oscillator continues to run, but the core clock analog ground planes are connected together somewhere else generated from the PLL is halted. The on-chip peripherals con- (at the system’s power supply for example), they cannot be con- tinue to receive the clock, and remain functional. The CPU status nected again near the ADuC816 since a ground loop would result. is preserved with the stack pointer, program counter, and all other In these cases, tie the ADuC816’s AGND and DGND pins all internal registers maintain their data during idle mode. Port to the analog ground plane, as illustrated in Figure 51b. In systems pins and DAC output pins also retain their states, and ALE and PSEN outputs go high in this mode. The chip will recover with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the from idle mode upon receiving any enabled interrupt, or on board such that digital return currents do not flow near analog receiving a hardware reset. circuitry and vice versa. The ADuC816 can then be placed between the digital and analog sections, as illustrated in Figure 51c. –64– Rev. B

ADuC816 OTHER HARDWARE CONSIDERATIONS To facilitate in-circuit programming, plus in-circuit debug and emulation options, users will want to implement some simple A PLACE ANALOG PLACE DIGITAL connection points in their hardware that will allow easy access COMPONENTS HERE COMPONENTS HERE to download, debug, and emulation modes. In-Circuit Serial Download Access AGND DGND Nearly all ADuC816 designs will want to take advantage of the in-circuit reprogrammability of the chip. This is accomplished by a connection to the ADuC816’s UART, which requires an external RS-232 chip for level translation if downloading code from a PC. Basic configuration of an RS-232 connection is illustrated in B PLACE ANALOG PLACE DIGITAL Figure 52 with a simple ADM202-based circuit. If users would COMPONENTS COMPONENTS HERE HERE rather not design an RS-232 chip onto a board, refer to the appli- cation note “uC006–A 4-Wire UART-to-PC Interface”1 for a AGND DGND simple (and zero-cost-per-board) method of gaining in-circuit serial download access to the ADuC816. NOTE 1Application note uC006 is available at www.analog.com/microconverter In addition to the basic UART connections, users will also need a way to trigger the chip into download mode. This is accom- C PLACE ANALOG PLACE DIGITAL COMPONENTS COMPONENTS plished via a 1 kΩ pull-down resistor that can be jumpered HERE HERE onto the PSEN pin, as shown in Figure 52. To get the ADuC816 GND into download mode, simply connect this jumper and power- cycle the device (or manually reset the device, if a manual reset button is available) and it will be ready to receive a new program Figure 51.System Grounding Schemes serially. With the jumper removed, the device will come up in normal mode (and run the program) whenever power is cycled or In all of these scenarios, and in more complicated real-life appli- RESET is toggled. cations, keep in mind the flow of current from the supplies and back to ground. Make sure the return paths for all currents are Note that PSEN is normally an output (as described in the Exter- as close as possible to the paths the currents took to reach their nal Memory Interface section) and it is sampled as an input only destinations. For example, do not power components on the on the falling edge of RESET (i.e., at power-up or upon an analog side of Figure 51b with DV since that would force external manual reset). Note also that if any external circuitry DD return currents from DV to flow through AGND. Also, try to unintentionally pulls PSEN low during power-up or reset events, it DD avoid digital currents flowing under analog circuitry, which could could cause the chip to enter download mode and therefore fail to happen if the user placed a noisy digital chip on the left half begin user code execution as it should. To prevent this, ensure of the board in Figure 51c. Whenever possible, avoid large that no external signals are capable of pulling the PSEN pin low, discontinuities in the ground plane(s) (such as are formed by a except for the external PSEN jumper itself. long trace on the same layer), since they force return signals to Embedded Serial Port Debugger travel a longer path. And of course, make all connections to the From a hardware perspective, entry to serial port debug mode is ground plane directly, with little or no trace separating the pin identical to the serial download entry sequence described above. from its via to ground. In fact, both serial download and serial port debug modes can be If the user plans to connect fast logic signals (rise/fall time < 5ns) thought of as essentially one mode of operation used in two to any of the ADuC816’s digital inputs, add a series resistor to different ways. each relevant line to keep rise and fall times longer than 5ns at Note that the serial port debugger is fully contained on the the ADuC816 input pins. A value of 100Ω or 200Ω is usually ADuC816 device, (unlike “ROM monitor” type debuggers) and sufficient to prevent high-speed signals from coupling capacitively therefore no external memory is needed to enable in-system into the ADuC816 and affecting the accuracy of ADC conversions. debug sessions. ADuC816 System Self-Identification Single-Pin Emulation Mode In some hardware designs it may be an advantage for the soft- Also built into the ADuC816 is a dedicated controller for ware running on the ADuC816 target to identify the host Micro- single-pin in-circuit emulation (ICE) using standard production Converter. For example, code running on the ADuC816 may be ADuC816 devices. In this mode, emulation access is gained by used at future date to run on an ADuC816 MicroConverter host connection to a single pin, the EA pin. Normally, this pin is hard- and the code may be required to operate differently. wired either high or low to select execution from internal or The CHIPID SFR is a read-only register located at SFR address external program memory space, as described earlier. To enable C2 hex. The top nibble of this byte is set to “1” to designate single-pin emulation mode, however, users will need to pull the an ADuC824 host. For an ADuC824 host, the CHIPID SFR EA pin high through a 1kΩ resistor as shown in Figure 52. The will contain the value “0” in the upper nibble. emulator will then connect to the 2-pin header also shown in Figure 52. To be compatible with the standard connector that Rev. B –65–

ADuC816 DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) DVDD 1k(cid:8) DVDD 1k(cid:8) 2-PIN HEADER FOR EMULATION ACCESS 52 51 50 49 48 47 46 45 44 43 42 41 40 (NORMALLY OPEN) D D N A DVD DGN PSE E 39 38 P1.2IEXC1/DAC 37 AVDD 36 DVDD 200(cid:5)A/400(cid:5)A AVDD DGND 35 ECXUCRIRTEANTTION AGND ADuC816 DVDD 34 REFIN– XTAL2 33 VREF + REFIN+ XTAL1 32 R1 5.6k(cid:8) VREF – P1.4/AIN1 31 32.766kHz AIN + P1.5/AIN2 30 29 RTD 510R(cid:8)2 AIN – RESET RXD TXD DVDD DGND 2278 DVDD ADM810 NOT CONNECTED IN THIS EXAMPLE VCC RST DVDD GND ADM202 DVDD 9-PIN D-SUB C1+ VCC FEMALE V+ GND 1 C1– T1OUT 2 C2+ R1IN 3 C2– R1OUT 4 V– T1IN 5 T2OUT T2IN 6 R2IN R2OUT 7 8 9 Figure 52.Typical System Configuration comes with the single-pin emulator available from Accutron Limited Typical System Configuration (www.accutron.com), use a 2-pin 0.1-inch pitch “Friction Lock” A typical ADuC816 configuration is shown in Figure 52. It sum- header from Molex (www.molex.com) such as their part number marizes some of the hardware considerations discussed in the 22-27-2021. Be sure to observe the polarity of this header. As previous paragraphs. represented in Figure 52, when the Friction Lock tab is at the Figure 52 also includes connections for a typical analog measure- right, the ground pin should be the lower of the two pins (when ment application of the ADuC816, namely an interface to an viewed from the top). RTD (Resistive Temperature Device). The arrangement shown Enhanced-Hooks Emulation Mode is commonly referred to as a 4-wire RTD configuration. ADuC816 also supports enhanced-hooks emulation mode. An Here, the on-chip excitation current sources are enabled to excite enhanced-hooks-based emulator is available from Metalink Corpo- the sensor. An external differential reference voltage is generated ration (www.metaice.com). No special hardware support for these by the current sourced through resistor R1. This current also flows emulators needs to be designed onto the board since these are directly through the RTD, which generates a differential voltage “pod-style” emulators where users must replace the chip on directly proportional to temperature. This differential voltage is their board with a header device that the emulator pod plugs routed directly to the positive and negative inputs of the primary into. The only hardware concern is then one of determining if ADC (AIN1, AIN2 respectively). A second external resistor, R2, is adequate space is available for the emulator pod to fit into the used to ensure that absolute analog input voltage on the negative system enclosure. input to the primary ADC stays within that specified for the ADuC816, i.e., AGND + 100mV. –66– Rev. B

ADuC816 It should also be noted that variations in the excitation current do Download—In-Circuit Serial Downloader not affect the measurement system, as the input voltage from The Serial Downloader is a software program that allows the user the RTD and reference voltage across R1 vary ratiometrically with to serially download an assembled program (Intel Hex format file) the excitation current. Resistor R1 must, however, have a low to the on-chip program FLASH memory via the serial COM1 temperature coefficient to avoid errors in the reference volt- port on a standard PC. An Application Note (uC004) detailing age over temperature. this serial download protocol is available from www.analog.com/ microconverter. QUICKSTART DEVELOPMENT SYSTEM DeBug—In-Circuit Debugger The QuickStart Development System is a full featured, low cost The Debugger is a Windows application that allows the user to development tool suite supporting the ADuC816. The system debug code execution on silicon using the MicroConverter UART consists of the following PC-based (Windows-compatible) hard- serial port. The debugger provides access to all on-chip periph- ware and software development tools. erals during a typical debug session as well as single-step and Hardware: ADuC816 Evaluation Board, Plug-In break-point code execution control. Power Supply and Serial Port Cable ADSIM—Windows Simulator Code Development: 8051 Assembler C Compiler The Simulator is a Windows application that fully simulates all (2Kcode Limited) the MicroConverter functionality including ADC and DAC peripherals. The simulator provides an easy-to-use, intuitive, inter- Code Functionality: ADSIM, Windows MicroConverter face to the MicroConverter functionality and integrates many Code Simulator standard debug features; including multiple breakpoints, single In-Circuit Code Download: Serial Downloader stepping; and code execution trace capability. This tool can be In-Circuit Debugger: Serial Port Debugger used both as a tutorial guide to the part as well as an efficient way to prove code functionality before moving to a hardware platform. Misc. Other: CD-ROM Documentation and Two Additional Prototype Devices The QuickStart development tool-suite software is freely available at the Analog Devices MicroConverter Website Figures 53 shows the typical components of a QuickStart Devel- www.analog.com/microconverter. opment System while Figure 54 shows a typical debug session. A brief description of some of the software tools’ components in the QuickStart Development System is given below. Figure 54.Typical Debug Session Figure 53.Components of the QuickStart Development System Rev. B –67–

ADuC816 OUTLINE DIMENSIONS Figure 55. 52-Lead Metric Quad Flat Package [MQFP] (S-52-2) Dimensions shown in millimeters Figure 56. 56-Lead Lead Frame Chip Scale Package [LFCSP] 8 mm × 8 mm Body and 0.75 mm Package Height (CP-56-11) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option Ordering Quantity ADuC816BSZ –40°C to +85°C 52-Lead Metric Quad Flat Package [MQFP] S-52-2 ADuC816BSZ-REEL –40°C to +85°C 52-Lead Metric Quad Flat Package [MQFP] S-52-2 1,000 ADuC816BCPZ –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 ADuC816BCPZ-REEL –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-11 1,000 1 Z = RoHS Compliant Part. –68– Rev. B

Data Sheet ADuC816 REVISION HISTORY 8/2016—Rev. A to Rev. B Updated Outline Dimensions ....................................................... 68 Changes to Ordering Guide ......................................................... 68 ©2001–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00436-0-8/16(B)

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADUC816BCPZ ADUC816BSZ ADUC816BSZ-REEL