Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler Data Sheet ADuC7124/ADuC7126 FEATURES On-chip peripherals Analog input/output 2× fully I2C-compatible channels Multichannel, 12-bit, 1 MSPS ADC SPI (20 MBPS in master mode, 10 MBPS in slave mode) Up to 16 ADC channels With 4-byte FIFO on input and output stages Fully differential and single-ended modes 2× UART channels 0 V to V analog input range With 16-byte FIFO on input and output stages REF 12-bit voltage output DACs Up to 40 GPIO port 4 DAC outputs available All GPIOs are 5 V tolerant On-chip voltage reference 4× general-purpose timers On-chip temperature sensor (±3°C) Watchdog timer (WDT) and wake-up timer Voltage comparator Programmable logic array (PLA) Microcontroller 16 PLA elements ARM7TDMI core, 16-bit/32-bit RISC architecture 16-bit, 6-channel PWM JTAG port supports code download and debug Power supply monitor Clocking options Power Trimmed on-chip oscillator (±3%) Specified for 3 V operation External watch crystal Active mode: 11.6 mA at 5 MHz, 33.3 mA at 41.78 MHz External clock source up to 41.78 MHz Packages and temperature range 41.78 MHz PLL with programmable divider Fully specified for −40°C to +125°C operation Memory 64-lead LFCSP (ADuC7124) and 80-lead LQFP (ADuC7126) 126 kB Flash/EE memory, 32 kB SRAM Tools In-circuit download, JTAG-based debug Low cost QuickStart development system Software-triggered in-circuit reprogrammability Full third-party support Vectored interrupt controller for FIQ and IRQ APPLICATIONS 8 priority levels for each interrupt type Industrial control and automation systems Interrupt on edge or level external pin inputs Smart sensors, precision instrumentation Base station systems, optical networking Patient monitoring FUNCTIONAL BLOCK DIAGRAM ADC0 12-BIT DAC0 DAC MUX 1MSPS 12-BIT ADC ADC15 12-BIT DAC1 DAC TEMP SENSOR ADuC7124/ADuC7126 12-BIT DAC2 CMP0 DAC CMP1 BANRDE FGAP 1D2-ABCIT DAC3 CMPOUT VECTORED INTERRUPT VREF CONTROLLER OSC ARM7TDMI-BASED MCUWITH XCLKI AND PLL ADDITIONAL PERIPHERALS XCLKO PSM PLA 8k × 32 SRAM GPIO 63k × 16 FLASH/EEPROM EXTERNAL PWM MEMORY RST POR PUR4 PGOESNEE RTIAMLE-RS S2P I×, 2U A× RI2TC, JTAG INTERFACE 09123-001 Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADuC7124/ADuC7126 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Band Gap Reference ................................................................... 45 Applications ....................................................................................... 1 Nonvolatile Flash/EE Memory ..................................................... 46 Functional Block Diagram .............................................................. 1 Programming .............................................................................. 46 Revision History ............................................................................... 3 Flash/EE Memory Security ....................................................... 47 General Description ......................................................................... 5 Flash/EE Control Interface ....................................................... 47 Specifications ..................................................................................... 6 Execution Time from SRAM and Flash/EE ............................ 50 Timing Specifications .................................................................. 9 Reset and Remap ........................................................................ 50 Absolute Maximum Ratings .......................................................... 14 Other Analog Peripherals .............................................................. 53 ESD Caution ................................................................................ 14 DAC .............................................................................................. 53 Pin Configurations and Function Descriptions ......................... 15 Power Supply Monitor ............................................................... 55 Typical Performance Characteristics ........................................... 24 Comparator ................................................................................. 55 Terminology .................................................................................... 27 Oscillator and PLL—Power Control ........................................ 56 ADC Specifications .................................................................... 27 Digital Peripheral ........................................................................... 60 DAC Specifications..................................................................... 27 General-Purpose Input/Output................................................ 60 Overview of the ARM7TDMI Core ............................................. 28 Serial Port Mux ........................................................................... 62 Thumb Mode (T) ........................................................................ 28 UART Serial Interface ................................................................ 62 Long Multiply (M) ...................................................................... 28 Serial Peripheral Interface ......................................................... 68 EmbeddedICE (I) ....................................................................... 28 I2C ................................................................................................. 72 Exceptions ................................................................................... 28 PWM General Overview ........................................................... 80 ARM Registers ............................................................................ 28 Programmable Logic Array (PLA)........................................... 83 Interrupt Latency ........................................................................ 29 Processor Reference Peripherals ................................................... 86 Memory Organization ................................................................... 30 Interrupt System ......................................................................... 86 Memory Access ........................................................................... 30 IRQ ............................................................................................... 86 Flash/EE Memory ....................................................................... 30 Fast Interrupt Request (FIQ) .................................................... 87 SRAM ........................................................................................... 30 Vectored Interrupt Controller (VIC) ....................................... 88 Memory Mapped Registers ....................................................... 30 Timers .......................................................................................... 93 ADC Circuit Overview .................................................................. 38 External Memory Interfacing ................................................... 99 Transfer Function ....................................................................... 38 Hardware Design Considerations .............................................. 103 Typical Operation ....................................................................... 39 Power Supplies .......................................................................... 103 MMRs Interface .......................................................................... 39 Grounding and Board Layout Recommendations ............... 104 Converter Operation .................................................................. 41 Clock Oscillator ........................................................................ 104 Driving the Analog Inputs ........................................................ 43 Power-On Reset Operation ..................................................... 105 Calibration ................................................................................... 44 Outline Dimensions ..................................................................... 106 Temperature Sensor ................................................................... 44 Ordering Guide ........................................................................ 107 Rev. D | Page 2 of 110

Data Sheet ADuC7124/ADuC7126 REVISION HISTORY 10/14—Rev. C to Rev. D Changes to Figure 7 and Table 9 ................................................... 14 Added Figure 8 and Table 10; Renumbered Sequentially .......... 18 Change CONVSTART To CONVSTART ............................................................. Universal Change to Figure 17 Caption ......................................................... 25 Changes to Features Section ............................................................ 1 Change to Memory Mapped Registers Section ........................... 29 Changes to Pin 17 and Pin 30 Descriptions; Table 10 ................ 19 Change to Figure 26 ........................................................................ 30 Changes to Flash/EE Memory Section and SRAM Section....... 30 Changes to Table 18 ........................................................................ 32 Changes to Table 13 ........................................................................ 32 Changes to Table 21 ........................................................................ 33 Changes to Flash/EE Memory Section, Programming Section, Changes to Table 22 ........................................................................ 34 and Serial Downloading (In-Circuit Programming) Section ... 46 Moved Table 25 ................................................................................ 35 Changes to Flash/EE Memory Security Section.......................... 47 Change to Table 25 .......................................................................... 35 Changes to Table 56 and Table 57 ................................................. 50 Added Table 26 ................................................................................ 35 Changes to Table 69 ........................................................................ 56 Change to Table 27 .......................................................................... 36 Changes to Table 78 ........................................................................ 60 Changes to Temperature Sensor Section ..................................... 42 Changes to I2C Section ................................................................... 72 Deleted Table 59; Renumbered Sequentially ............................... 43 Update Table 102 ............................................................................. 73 Added Downloading (In-Circuit Programming) via I2 Update Table 109 ............................................................................. 76 C Section .......................................................................................... 44 Changes to Table 110 ...................................................................... 77 Change to JTAG Access Section and Table 37............................. 45 Changes to T1CAP Register .......................................................... 96 Changes to Table 45 ........................................................................ 46 5/12—Rev. B to Rev. C Changes to RSTCFG Register Section .......................................... 49 Changed bit to byte in General Description Section .................... 4 Deleted Table 72 and Table 75 ....................................................... 49 Changes to Table 2 and Table 3 ....................................................... 8 Deleted Table 78 .............................................................................. 50 Changes to Table 4 and to Figure 2 and Figure 3 .......................... 9 Changes to DAC Section, Table 62, and Table 64 ....................... 51 Changes to Table 5 and Figure 4.................................................... 10 Changes to References to ADC and the DACs Setion, Table 66, Changes to Table 6 and Figure 5.................................................... 11 Configuring DAC Buffers in Op Amp Mode Section, Changes Table 7 and Figure 6 ........................................................ 12 DACBCFG Register Section, and Table 67 .................................. 52 Changes to Pin 50 and Pin 51 in Table 9 ...................................... 14 Added DACBKEY1 Register Section and DACBKEY2 Register Changes to Serial Downloading (In-Circuit Programming) Section .............................................................................................. 53 Section...............................................................................................4 4 Changes to Table 69 and Figure 45 ............................................... 54 Changes to Table 77 ........................................................................ 59 Changes to and External Crystal Selection and External Clock Changes to Table 78 ........................................................................ 58 Selection ........................................................................................... 55 Changes to Table 90 ........................................................................ 60 Changes to PLLCON Register and POWCON0 Register Changes to Normal 450 UART Baud Rate Generation Section .............................................................................................. 56 Section...............................................................................................6 1 Changes to Table 78 ........................................................................ 58 Changes to Serial Peripheral Interface Section ........................... 66 Changes to Table 81 ........................................................................ 59 Added equation to Timers Section and added Hr: Min: Sec Changes to Table 84 and Table 90 ................................................. 60 1/128 Format Section ...................................................................... 91 Changes to Table 93, COM0FCR Register Section, COM1FCR Changes to Figure 69 ................................................................... 103 Register Section, and Table 94 ....................................................... 63 Updated Outline Dimensions ..................................................... 104 Changes to Serial Peripheral Interface Section ........................... 66 Changes to Ordering Guide ........................................................ 105 Change to SPI Registers Section.................................................... 67 Changes to SPIDIV Register Section and Table 101 .................. 68 1/11—Rev A to Rev B Change to I2C Master Transmit Register Section ....................... 73 Changes to Table 1 ............................................................................ 5 Change to Table 109 ........................................................................ 74 10/10—Rev. 0 to Rev. A Change to I2C Slave Status Registers Section............................... 75 Change to Table 113 ........................................................................ 79 Added ADuC7126 .............................................................. Universal Changes to Table 114 Title and Figure 50 .................................... 80 Changes to Features Section ............................................................ 1 Change to IRQCLRE Register Register ....................................... 90 Moved Figure 1 .................................................................................. 1 Change to Figure 54 ........................................................................ 92 Changes to Figure 1 ........................................................................... 1 Changes to Table 141, T1CLRI Register Section, and T1CAP Changes to General Description Section ....................................... 4 Register Section ............................................................................... 93 Changes to Voltage Output at 25°C, Voltage TC, IOV Current DD Changes to Table 143 ...................................................................... 94 in Active Mode, and IOV Current in Pause Mode Parameters, DD Added External Memory Interfacting Section, Table 145, Table 1 ................................................................................................. 5 Table 146, and Figure 57 ................................................................. 96 Change to Table 8 ............................................................................ 13 Changed REFGND to GND ...................................................... 13 REF Rev. D | Page 3 of 110

ADuC7124/ADuC7126 Data Sheet Added XMCFG Register Section, Table 147, Table 148, Change to Power-On Reset Operation Section and Table 149, and Table 150 ................................................................ 97 Figure 69 ........................................................................................ 102 Added Figure 58 and Figure 59..................................................... 98 Added Figure 71 ........................................................................... 103 Added Figure 60 and Figure 61..................................................... 99 Changes to Ordering Guide ........................................................ 104 Changes to Figure 62 to Figure 65 .............................................. 100 9/10—Revision 0: Initial Version Changes to Figure 67 and Figure 68 ........................................... 101 Rev. D | Page 4 of 110

Data Sheet ADuC7124/ADuC7126 GENERAL DESCRIPTION The ADuC7124/ADuC7126 are fully integrated, 1 MSPS, The ADuC7124/ADuC7126 contain an advanced interrupt 12-bit data acquisition system incorporating high performance controller. The vectored interrupt controller (VIC) allows every multichannel ADCs, 16-bit/32-bit MCUs, and Flash/EE memory interrupt to be assigned a priority level. It also supports nested on a single chip. interrupts to a maximum level of eight per IRQ and FIQ. When IRQ and FIQ interrupt sources are combined, a total of 16 The ADC consists of up to 12 single-ended inputs. An additional nested interrupt levels are supported. four inputs are available but are multiplexed with the four DAC output pins. The ADC can operate in single-ended or differen- On-chip factory firmware supports in-circuit download via the tial input mode. The ADC input voltage range is 0 V to VREF. UART serial interface port or the I2C port, while nonintrusive A low drift band gap reference, temperature sensor, and voltage emulation is also supported via the JTAG interface. These fea- comparator complete the ADC peripheral set. tures are incorporated into a low cost QuickStart™ development system supporting this MicroConverter® family. The DAC output range is programmable to one of three voltage ranges. The DAC outputs have an enhanced feature of being The parts contain a 16-bit PWM with six output signals. able to retain their output voltage during a watchdog or soft- For communication purposes, the parts contain 2× I2C channels ware reset sequence. that can be individually configured for master or slave mode. The devices operate from an on-chip oscillator and a PLL An SPI interface supporting both master and slave modes is generating an internal high frequency clock of 41.78 MHz. also provided. Thirdly, 2× UART channels are provided. Each This clock is routed through a programmable clock divider UART contains a configurable 16-byte FIFO with receive and from which the MCU core clock operating frequency is transmit buffers. generated. The microcontroller core is an ARM7TDMI®, The parts operate from 2.7 V to 3.6 V and is specified over an 16-bit/32-bit RISC machine, which offers up to 41 MIPS of industrial temperature range of −40°C to +125°C. When operat- peak performance. Thirty-two kilobytes of SRAM and 126 kB ing at 41.78 MHz, the power dissipation is typically 120 mW. of nonvolatile Flash/EE memory are provided on-chip. The The ADuC7124 is available in a 64-lead LFCSP package. The ARM7TDMI core views all memory and registers as a single ADuC7126 is available in a 80-lead LQFP package. linear array. Rev. D | Page 5 of 110

ADuC7124/ADuC7126 Data Sheet SPECIFICATIONS AV = IOV = 2.7 V to 3.6 V, V = 2.5 V internal reference, f = 41.78 MHz, T = −40°C to +125°C, unless otherwise noted. DD DD REF CORE A Table 1. Parameter Min Typ Max Unit Test Conditions/Comments ADC CHANNEL SPECIFICATIONS Eight acquisition clocks and f /2 ADC ADC Power-Up Time 5 μs DC Accuracy1, 2 Resolution 12 Bits Integral Nonlinearity ±0.6 ±1.5 LSB 2.5 V internal reference ±1.0 LSB 1.0 V external reference Differential Nonlinearity3, 4 ±0.5 +1/−0.9 LSB 2.5 V internal reference +0.7/−0.6 LSB 1.0 V external reference DC Code Distribution 1 LSB ADC input is a dc voltage ENDPOINT ERRORS5 Offset Error ±1 ±2 LSB Offset Error Match ±1 LSB Gain Error ±2 ±5 LSB Gain Error Match ±1 LSB DYNAMIC PERFORMANCE f = 10 kHz sine wave, f = 1 MSPS IN SAMPLE Signal-to-Noise Ratio (SNR) 69 dB Includes distortion and noise components Total Harmonic Distortion (THD) −78 dB Peak Harmonic or Spurious Noise −75 dB Channel-to-Channel Crosstalk −90 dB Measured on adjacent channels; input channels not being sampled have a 25 kHz sine wave connected to them ANALOG INPUT Input Voltage Ranges4 Differential Mode V 6 ± V /2 V CM REF Single-Ended Mode 0 to V V REF Leakage Current ±1 ±6 µA Input Capacitance 24 pF During ADC acquisition ON-CHIP VOLTAGE REFERENCE 0.47 µF from V to AGND REF Output Voltage 2.5 V Accuracy ±5 mV T = 25°C A Reference Temperature Coefficient ±15 ppm/°C Power Supply Rejection Ratio 80 dB Output Impedance 45 Ω T = 25°C A Internal V Power-On Time 1 ms REF EXTERNAL REFERENCE INPUT Input Voltage Range 0.625 AV V DD DAC CHANNEL SPECIFICATIONS R = 5 kΩ, C = 100 pF L L DC Accuracy7 Resolution 12 Bits Relative Accuracy ±2 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic Offset Error 10 mV 2.5 V internal reference Gain Error8 1.0 % Gain Error Mismatch 0.1 % % of full scale on DAC0 Rev. D | Page 6 of 110

Data Sheet ADuC7124/ADuC7126 Parameter Min Typ Max Unit Test Conditions/Comments ANALOG OUTPUTS Output Voltage Range 0 0 to DAC V DAC range: DACGND to DACV REF REF DD Output Voltage Range 1 0 to 2.5 V Output Voltage Range 2 0 to DACV V DD Output Impedance 0.5 Ω DAC IN OP AMP MODE DAC Output Buffer in Op Amp Mode Input Offset Voltage ±0.4 mV Input Offset Voltage Drift 4 µV/°C Input Offset Current 2 nA Input Bias Current 2.5 nA Gain 70 dB 5 kΩ load Unity Gain Frequency 4.5 MHz R = 5 kΩ, C = 100 pF L L CMRR 78 dB Settling Time 12 µs R = 5 kΩ, C = 100 pF L L Output Slew Rate 3.2 V/µs R = 5 kΩ, C = 100 pF L L PSRR 75 dB DAC AC CHARACTERISTICS Voltage Output Settling Time 10 µs Digital-to-Analog Glitch Energy ±10 nV-sec 1 LSB change at major carry (where maximum number of bits simultaneously change in the DACxDAT register) COMPARATOR Input Offset Voltage ±15 mV Input Bias Current 1 µA Input Voltage Range AGND AV – 1.2 V DD Input Capacitance 8.5 pF Hysteresis4, 6 2 15 mV Hysteresis can be turned on or off via the CMPHYST bit in the CMPCON register Response Time 4 µs 100 mV overdrive and configured with CMPRES = 11 TEMPERATURE SENSOR Voltage Output at 25°C 1.415 V ADuC7124 1.392 V ADuC7126 Voltage Temperature Coefficient 3.914 mV/°C ADuC7124 4.52 mV/°C ADuC7126 Accuracy ±3 °C A single point calibration is required θ Thermal Impedance JA 64-Lead LFCSP 24 °C/W POWER SUPPLY MONITOR (PSM) IOV Trip Point Selection 2.79 V Two selectable trip points DD 3.07 V Power Supply Trip Point Accuracy ±2.5 % Of the selected nominal trip point voltage POWER-ON RESET 2.41 V WATCHDOG TIMER (WDT) Timeout Period 0 512 sec FLASH/EE MEMORY Endurance9 10,000 Cycles Data Retention10 20 Years T = 85°C J DIGITAL INPUTS All digital inputs excluding XCLKI and XCLKO Logic 1 Input Current ±0.2 ±1 µA V = V or V = 5 V IH DD IH Logic 0 Input Current −40 −60 µA V = 0 V; except TDI, TDO, and RTCK IL −80 −120 µA V = 0 V; TDI, TDO, and RTCK IL Input Capacitance 5 pF Rev. D | Page 7 of 110

ADuC7124/ADuC7126 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS3 All logic inputs excluding XCLKI V , Input Low Voltage 0.8 V INL V , Input High Voltage 2.0 V INH LOGIC OUTPUTS All digital outputs excluding XCLKO V , Output High Voltage 2.4 V I = 1.6 mA OH SOURCE V , Output Low Voltage11 0.4 V I = 1.6 mA OL SINK CRYSTAL INPUTS XCLKI and XCLKO Logic Inputs, XCLKI Only V , Input Low Voltage 0.8 V INL V , Input High Voltage 1.6 V INH XCLKI Input Capacitance 20 pF XCLKO Output Capacitance 20 pF INTERNAL OSCILLATOR 32.768 kHz ±3 % MCU CLOCK RATE4 From 32 kHz Internal Oscillator 326 kHz CD = 7 From 32 kHz External Crystal 41.78 MHz CD = 0 Using an External Clock 0.05 44 MHz T = 85°C A 0.05 41.78 MHz T = 125°C A START-UP TIME Core clock = 41.78 MHz At Power-On 66 ms From Pause/Nap Mode 2.6 µs CD = 0 247 µs CD = 7 From Sleep Mode 1.58 ms From Stop Mode 1.7 ms PROGRAMMABLE LOGIC ARRAY (PLA) Pin Propagation Delay 12 ns From input pin to output pin Element Propagation Delay 2.5 ns POWER REQUIREMENTS12, 13 Power Supply Voltage Range AV to AGND and IOV to IOGND 2.7 3.6 V DD DD Analog Power Supply Currents AV Current 165 µA ADC in idle mode DD DACV Current14 0.02 µA DD Digital Power Supply Current IOV Current in Active Mode Code executing from Flash/EE DD 8.1 12.5 mA CD = 7 11.6 17 mA CD = 3 33.3 50 mA CD = 0 (41.78 MHz clock) IOV Current in Pause Mode 20.6 30 mA CD = 0 (41.78 MHz clock) DD IOV Current in Sleep Mode 110 µA T = 85°C DD A 600 680 µA T = 125°C A Additional Power Supply Currents ADC 1.26 mA At 1 MSPS 0.7 mA At 62.5 kSPS DAC 315 µA Per DAC Rev. D | Page 8 of 110

Data Sheet ADuC7124/ADuC7126 Parameter Min Typ Max Unit Test Conditions/Comments ESD TESTS 2.5 V reference, T = 25°C A HBM Passed Up To 3 kV FICDM Passed Up To 1.5 kV 1 All ADC channel specifications are guaranteed during normal core operation. 2 Apply to all ADC input channels. 3 Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN). 4 Not production tested but supported by design and/or characterization data on production release. 5 Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 37. Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section). 6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified. 7 DAC linearity is calculated using a reduced code range of 100 to 3995. 8 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF. 9 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 10 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature. 11 Test carried out with a maximum of eight I/Os set to a low output level. 12 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with 3.6 V supply, and sleep mode with 3.6 V supply. 13 IOVDD power supply current increases typically by 2 mA during a Flash/EE erase cycle. 14 This current must be added to the AVDD current. TIMING SPECIFICATIONS I2C Timing Table 2. I2C Timing in Fast Mode (400 kHz) Slave Master Parameter Description Min Max Typ Unit t SCL low pulse width 200 1360 ns L t SCL high pulse width 100 1140 ns H t Start condition hold time 300 ns SHD t Data setup time 100 740 ns DSU t Data hold time 0 400 ns DHD t Setup time for repeated start 100 ns RSU t Stop condition setup time 100 800 ns PSU t Bus-free time between a stop condition and a start condition 1.3 µs BUF t Rise time for both SCL and SDA 300 200 ns R t Fall time for both SCL and SDA 300 ns F Table 3. I2C Timing in Standard Mode (100 kHz) Slave Parameter Description Min Max Unit t SCL low pulse width 4.7 µs L t SCL high pulse width 4.0 ns H t Start condition hold time 4.0 µs SHD t Data setup time 250 ns DSU t Data hold time 0 3.45 µs DHD t Setup time for repeated start 4.7 µs RSU t Stop condition setup time 4.0 µs PSU t Bus-free time between a stop condition and a start condition 4.7 µs BUF t Rise time for both SCL and SDA 1 µs R t Fall time for both SCL and SDA 300 ns F Rev. D | Page 9 of 110

ADuC7124/ADuC7126 Data Sheet tBUF tR SDA (I/O) MSB LSB ACK MSB tPSU tDSU tDHD tDSU tDHD tF tSHD tH tRSU tR SCL (I) 1 2–7 8 9 1 COSNTDOIPTPION COSNTSDAIRTITON tL RESPSTEA(RAR)TTED tF 09123-029 Figure 2. I2C-Compatible Interface Timing SPI Timing Table 4. SPI Master Mode Timing (Phase Mode = 1) Parameter Description Min Typ Max Unit t SCLK low pulse width1 (SPIDIV + 1) × t ns SL UCLK t SCLK high pulse width1 (SPIDIV + 1) × t ns SH UCLK t Data output valid after SCLK edge 25 ns DAV t Data input setup time before SCLK edge1 1 × t ns DSU UCLK t Data input hold time after SCLK edge1 2 × t ns DHD UCLK t Data output fall time 5 12.5 ns DF t Data output rise time 5 12.5 ns DR t SCLK rise time 5 12.5 ns SR t SCLK fall time 5 12.5 ns SF 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. SCLK (POLARITY = 0) tSH tSL SCLK tSR tSF (POLARITY = 1) tDAV tDF tDR MOSI MSB BIT 6 TO BIT 1 LSB MISO MSB IN BIT 6 TO BIT 1 LSB IN tDSU tDHD 09123-030 Figure 3. SPI Master Mode Timing (Phase Mode = 1) Rev. D | Page 10 of 110

Data Sheet ADuC7124/ADuC7126 Table 5. SPI Master Mode Timing (Phase Mode = 0) Parameter Description Min Typ Max Unit t SCLK low pulse width1 (SPIDIV + 1) × t ns SL UCLK t SCLK high pulse width1 (SPIDIV + 1) × t ns SH UCLK t Data output valid after SCLK edge 25 ns DAV t Data output setup before SCLK edge 75 ns DOSU t Data input setup time before SCLK edge1 1 × t ns DSU UCLK t Data input hold time after SCLK edge1 2 × t ns DHD UCLK t Data output fall time 5 12.5 ns DF t Data output rise time 5 12.5 ns DR t SCLK rise time 5 12.5 ns SR t SCLK fall time 5 12.5 ns SF 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. SCLK (POLARITY = 0) tSH tSL tSR tSF SCLK (POLARITY = 1) tDAV tDOSU tDF tDR MOSI MSB BIT 6 TO BIT 1 LSB MISO MSB IN BIT 6 TO BIT 1 LSB IN tDSU tDHDFigure 4. SPI Master Mode Timing (Phase Mode = 0) 09123-031 Rev. D | Page 11 of 110

ADuC7124/ADuC7126 Data Sheet Table 6. SPI Slave Mode Timing (Phase Mode = 1) Parameter Description Min Typ Max Unit t CS to SCLK edge 200 ns CS t SCLK low pulse width (SPIDIV + 1) × t ns SL HCLK t SCLK high pulse width (SPIDIV + 1) × t ns SH HCLK t Data output valid after SCLK edge 25 ns DAV t Data input setup time before SCLK edge1 1 × t ns DSU UCLK t Data input hold time after SCLK edge1 2 × t ns DHD UCLK t Data output fall time 5 12.5 ns DF t Data output rise time 5 12.5 ns DR t SCLK rise time 5 12.5 ns SR t SCLK fall time 5 12.5 ns SF t CS high after SCLK edge 0 ns SFS 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. CS tCS tSFS SCLK (POLARITY = 0) tSH tSL tSR tSF SCLK (POLARITY = 1) tDAV tDF tDR MISO MSB BIT 6 TO BIT 1 LSB MOSI MSB IN BIT 6 TO BIT 1 LSB IN tDSU tDHD 09123-132 Figure 5. SPI Slave Mode Timing (Phase Mode = 1) Rev. D | Page 12 of 110

Data Sheet ADuC7124/ADuC7126 Table 7. SPI Slave Mode Timing (Phase Mode = 0) Parameter Description Min Typ Max Unit t CS to SCLK edge 200 ns CS t SCLK low pulse width (SPIDIV + 1) × t ns SL HCLK t SCLK high pulse width (SPIDIV + 1) × t ns SH HCLK t Data output valid after SCLK edge 25 ns DAV t Data input setup time before SCLK edge1 1 × t ns DSU UCLK t Data input hold time after SCLK edge1 2 × t ns DHD UCLK t Data output fall time 5 12.5 ns DF t Data output rise time 5 12.5 ns DR t SCLK rise time 5 12.5 ns SR t SCLK fall time 5 12.5 ns SF t Data output valid after CS edge 25 ns DOCS t CS high after SCLK edge 0 ns SFS 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. CS tCS tSFS SCLK (POLARITY = 0) tSH tSL tSR tSF SCLK (POLARITY = 1) tDAV tDOCS tDF tDR MISO MSB BIT 6 TO BIT 1 LSB MOSI MSB IN BIT 6 TO BIT 1 LSB IN tDSU tDHD 09123-033 Figure 6. SPI Slave Mode Timing (Phase Mode = 0) Rev. D | Page 13 of 110

ADuC7124/ADuC7126 Data Sheet ABSOLUTE MAXIMUM RATINGS AGND = GND = DACGND = GND , T = 25°C, unless Stresses above those listed under Absolute Maximum Ratings REF REF A otherwise noted. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 8. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute AV to IOV −0.3 V to +0.3 V DD DD maximum rating conditions for extended periods may affect AGND to DGND −0.3 V to +0.3 V device reliability. IOV to IOGND, AV to AGND −0.3 V to +6 V DD DD Only one absolute maximum rating can be applied at any one time. Digital Input Voltage to IOGND −0.3 V to +5.3 V Digital Output Voltage to IOGND −0.3 V to IOV + 0.3 V ESD CAUTION DD V to AGND −0.3 V to AV + 0.3 V REF DD Analog Inputs to AGND −0.3 V to AVDD + 0.3 V Analog Outputs to AGND −0.3 V to AV + 0.3 V DD Operating Temperature Range, Industrial –40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 64-Lead LFCSP 24°C/W 80-Lead LQFP 38°C/W Peak Solder Reflow Temperature SnPb Assemblies (10 sec to 30 sec) 240°C RoHS Compliant Assemblies 260°C (20 sec to 40 sec) Rev. D | Page 14 of 110

Data Sheet ADuC7124/ADuC7126 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS P1P0 O[12]O[11]O[10]PM0/SIN0/I2C0SCL/PLAI[0]1/SOUT0/I2C0SDA/PLAI[1]2/RTS/I2C1SCL/PLAI[2] ADC3/CMADC2/CMADC1ADC0GNDREFAGNDAVDDDACREFVREFRTCKP4.4/PLAP4.3/PLAP4.2/PLAP1.0/T1/SP1.1/SPMP1.2/SPM 4321098765432109 6666655555555554 ADC4 1 PIN 1 48P1.3/SPM3/CTS/I2C1SDA/PLAI[3] ADC5 2 INDICATOR 47P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2 ADC6 3 46P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3 ADC7 4 45P4.1/PLAO[9]/SOUT1 ADC8 5 44P4.0/PLAO[8]/SIN1 ADC9 6 43P1.6/SPM6/PLAI[6] ADCNEG 7 ADuC7124 42P1.7/SPM7/DTR/SPICS/PLAO[0] DACGND 8 41P3.7/PWMSYNC/PLAI[15] DACVDD 9 TOP VIEW 40P3.6/PWMTRIP/PLAI[14] DAC0/ADC12 10 (Not to Scale) 39IOVDD DAC1/ADC13 11 38IOGND TMS12 37P0.7/ECLK/XCLK/SPM8/PLAO[4]/SIN0 TDI13 36P2.0/SPM9/PLAO[5]/CONVSTART/SOUT0 XCLKO14 35IRQ1/P0.5/ADCBUSY/PLAO[2] XCLKI15 34IRQ0/P0.4/PWMTRIP/PLAO[1] BM/P0.0/CMPOUT/PLAI[7]16 33RST NC = NO CONNECT 7890123456789012 1112222222222333 DGNDLVDDIOVDDIOGNDP4.6/PLAO[14]P4.7/PLAO[15]0.6/T1/MRST/PLAO[3]TCKTDOP3.0/PWM0/PLAI[8]P3.1/PWM1/PLAI[9]P3.2/PWM2/PLAI[10]P3.3/PWM3/PLAI[11]P0.3/TRST/ADCBUSYP3.4/PWM4/PLAI[12]P3.5/PWM5/PLAI[13] P N1 . O THTHEEEAS TE XDPISOSSIPEADT PIOAND,D NLOE IMSEU,S ATN BDE M SEOCLHDAENRIECDA LT OST TRHEEN PGCTBH TBOE NEENFSIUTSR.E PROPER 09123-107 Figure 7. ADuC7124 Pin Configuration Table 9. Pin Function Descriptions (ADuC7124 64-Lead LFCSP) Pin No. Mnemonic Description 0 Exposed Paddle Exposed Paddle. The LFCSP_VQ has an exposed paddle that must be left unconnected. 1 ADC4 Single-Ended or Differential Analog Input 4. 2 ADC5 Single-Ended or Differential Analog Input 5. 3 ADC6 Single-Ended or Differential Analog Input 6. 4 ADC7 Single-Ended or Differential Analog Input 7. 5 ADC8 Single-Ended or Differential Analog Input 8. 6 ADC9 Single-Ended or Differential Analog Input 9. 7 ADCNEG Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected to the ground of the signal to convert. This bias point must be between 0 V and 1 V. 8 DACGND Ground for the DAC. Typically connected to AGND. 9 DACV 3.3 V Power Supply for the DACs. Must be connected to AV . DD DD 10 DAC0/ADC12 DAC0 Voltage Output (DAC0). Single-Ended or Differential Analog Input 12 (ADC12). 11 DAC1/ADC13 DAC1 Voltage Output (DAC1). Single-Ended or Differential Analog Input 13 (ADC13). 12 TMS JTAG Test Port Input, Test Mode Select. Debug and download access. 13 TDI JTAG Test Port Input, Test Data In. Rev. D | Page 15 of 110

ADuC7124/ADuC7126 Data Sheet Pin No. Mnemonic Description 14 XCLKO Output from the Crystal Oscillator Inverter. 15 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. 16 BM/P0.0/CMP /PLAI[7] Multifunction I/O Pin. OUT Boot mode (BM). The ADuC7124 enters download mode if BM is low at reset and executes code if BM is pulled high at reset through a 1 kΩ resistor. General-Purpose Input and Output Port 0.0 (P0.0). Voltage Comparator Output (CMP ) OUT Programmable Logic Array Input Element 7 (PLAI[7]). 17 DGND Ground for Core Logic. 18 LV 2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a DD 0.47 μF capacitor to DGND only. 19 IOV 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. DD 20 IOGND Ground for GPIO. Typically connected to DGND. 21 P4.6/PLAO[14] General-Purpose Input and Output Port 4.6 (P4.6). Programmable Logic Array Output Element 14 (PLAO[14]). 22 P4.7/PLAO[15] General-Purpose Input and Output Port 4.7 (P4.7). Programmable Logic Array Output Element 15 (PLAO[15]). 23 P0.6/T1/MRST/PLAO[3] Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6 (P0.6). Timer1 Input (T1). Power-On Reset Output (MRST). Programmable Logic Array Output Element 3 (PLAO[3]). 24 TCK JTAG Test Port Input, Test Clock. Debug and download access. 25 TDO JTAG Test Port Output, Test Data Out. 26 P3.0/PWM0/PLAI[8] General-Purpose Input and Output Port 3.0 (P3.0). PWM Phase 0 (PWM0). Programmable Logic Array Input Element 8 (PLAI[8]). 27 P3.1/PWM1/PLAI[9] General-Purpose Input and Output Port 3.1 (P3.1). PWM Phase 1 (PWM1). Programmable Logic Array Input Element 9 (PLAI[9]). 28 P3.2/PWM2/PLAI[10] General-Purpose Input and Output Port 3.2 (P3.2). PWM Phase 2 (PWM2). Programmable Logic Array Input Element 10 (PLAI[10]). 29 P3.3/PWM3/PLAI[11] General-Purpose Input and Output Port 3.3 (P3.3). PWM Phase 3 (PWM3). Programmable Logic Array Input Element 11 (PLAI[11]). 30 P0.3/TRST/ADC General-Purpose Input and Output Port 0.3 (P0.3). BUSY JTAG Test Port Input, Test Reset (TRST). JTAG reset input. Debug and download access. If this pin is held low, JTAG access is not possible because the JTAG interface is held in reset and P0.1/P0.2/P0.3 are configured as GPIO pins. ADC Signal Output (ADC ). BUSY BUSY 31 P3.4/PWM4/PLAI[12] General-Purpose Input and Output Port 3.4 (P3.4). PWM Phase 4 (PWM4). Programmable Logic Array Input 12 (PLAI[12]). 32 P3.5/PWM5/PLAI[13] General-Purpose Input and Output Port 3.5 (P3.5). PWM Phase 5 (PWM5). Programmable Logic Array Input Element 13 (PLAI[13]). 33 RST Reset Input, Active Low. 34 IRQ0/P0.4/PWM /PLAO[1] Multifunction I/O Pin. TRIP External Interrupt Request 0, Active High (IRQ0). General-Purpose Input and Output Port 0.4 (P0.4). PWM Trip External Input (PWM ). TRIP Programmable Logic Array Output Element 1 (PLAO[1]). Rev. D | Page 16 of 110

Data Sheet ADuC7124/ADuC7126 Pin No. Mnemonic Description 35 IRQ1/P0.5/ADC /PLAO[2] Multifunction I/O Pin. BUSY External Interrupt Request 1, Active High (IRQ1). General-Purpose Input and Output Port 0.5 (P0.5). ADC Signal Output (ADC ). BUSY BUSY Programmable Logic Array Output Element 2 (PLAO[2]). 36 P2.0/SPM9/PLAO[5]/CONV /SOUT0 General-Purpose Input and Output Port 2.0 (P2.0). START Serial Port Multiplexed (SPM9). Programmable Logic Array Output Element 5 (PLAO[5]). Start Conversion Input Signal for ADC (CONV ). START UART0 Output (SOUT0). 37 P0.7/ECLK/XCLK/SPM8/PLAO[4]/SIN0 General-Purpose Input and Output Port 0.7 (P0.7). Output for External Clock Signal (ECLK). Input to the Internal Clock Generator Circuits (XCLK). Serial Port Multiplexed (SPM8). Programmable Logic Array Output Element 4 (PLAO[4]). UART0 Input (SIN0). 38 IOGND Ground for GPIO. Typically connected to DGND. 39 IOV 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. DD 40 P3.6/PWM /PLAI[14] General-Purpose Input and Output Port 3.6 (P3.6). TRIP PWM Safety Cutoff (PWM ). TRIP Programmable Logic Array Input Element 14 (PLAI[14]). 41 P3.7/PWM /PLAI[15] General-Purpose Input and Output Port 3.7 (P3.7). SYNC PWM Synchronization Input/Output (PWM ). SYNC Programmable Logic Array Input Element 15 (PLAI[15]). 42 P1.7/SPM7/DTR/SPICS/PLAO[0] General-Purpose Input and Output Port 1.7 (P1.7). Serial Port Multiplexed. UART, SPI (SPM7). Data Terminal Ready (DTR). Chip Select (SPICS). Programmable Logic Array Output Element 0 (PLAO[0]). 43 P1.6/SPM6/PLAI[6] General-Purpose Input and Output Port 1.6 (P1.6). Serial Port Multiplexed (SPM6). Programmable Logic Array Input Element 6 (PLAI[6]). 44 P4.0/PLAO[8]/SIN1 General-Purpose Input and Output Port 4.0 (P4.0). Programmable Logic Array Output Element 8 (PLAO[8]). UART1 Input (SIN1). 45 P4.1/PLAO[9]/SOUT1 General-Purpose Input and Output Port 4.1 (P4.1). Programmable Logic Array Output Element 9 (PLAO[9]). UART1 Output (SOUT1). 46 P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3 General-Purpose Input and Output Port 1.5 (P1.5). Serial Port Multiplexed. UART, SPI (SPM5). Data Carrier Detect (DCD). Master Input, Slave Output (SPI MISO). Programmable Logic Array Input Element 5 (PLAI[5]). External Interrupt Request 3, Active High (IRQ3). 47 P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2 General-Purpose Input and Output Port 1.4 (P1.4). Serial Port Multiplexed. UART, SPI (SPM4). Ring Indicator (RI). Serial Clock Input/Output (SPI SCLK). Programmable Logic Array Input Element 4 (PLAI[4]). External Interrupt Request 2, Active High (IRQ2). 48 P1.3/SPM3/CTS/I2C1SDA/PLAI[3] General-Purpose Input and Output Port 1.3 (P1.3). Serial Port Multiplexed. UART, I2C1 (SPM3). Clear to Send (CTS). I2C1 (I2C1SDA). Programmable Logic Array Input Element 3 (PLAI[3]). 49 P1.2/SPM2/RTS/I2C1SCL/PLAI[2] General-Purpose Input and Output Port 1.2 (P1.2). Serial Port Multiplexed (SPM2). Ready to Send (RTS). I2C1 (I2C1SCL). Programmable Logic Array Input Element 2 (PLAI[2]). Rev. D | Page 17 of 110

ADuC7124/ADuC7126 Data Sheet Pin No. Mnemonic Description 50 P1.1/SPM1/SOUT0/I2C0SDA/PLAI[1] General-Purpose Input and Output Port 1.1 (P1.1). Serial Port Multiplexed (SPM1). UART download pin, UART0 Output (SOUT0). I2C0 (I2C0SDA). Programmable Logic Array Input Element 1 (PLAI[1]). 51 P1.0/T1/SPM0/SIN0/I2C0SCL/PLAI[0] General-Purpose Input and Output Port 1.0 (P1.0). Timer1 Input (T1). Serial Port Multiplexed (SPM0). UART download pin, UART0 Input (SIN0). I2C0 (I2C0SCL). Programmable Logic Array Input Element 0 (PLAI[0]). 52 P4.2/PLAO[10] General-Purpose Input and Output Port 4.2 (P4.2). Programmable Logic Array Output Element 10 (PLAO[10]). 53 P4.3/PLAO[11] General-Purpose Input and Output Port 4.3 (P4.3). Programmable Logic Array Output Element 11 (PLAO[11]). 54 P4.4/PLAO[12] General-Purpose Input and Output Port 4.4 (P4.4). Programmable Logic Array Output Element 12 (PLAO[12]). 55 RTCK JTAG Test Port Output, JTAG Return Test Clock. 56 V 2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using REF the internal reference. 57 DAC External Voltage Reference for the DACs. Range: DACGND to DACV . REF DD 58 AV 3.3 V Analog Power. DD 59 AGND Analog Ground. Ground reference point for the analog circuitry. 60 GND Ground Voltage Reference for the ADC. For optimal performance, the analog power REF supply should be separated from IOGND and DGND. 61 ADC0 Single-Ended or Differential Analog Input 0. 62 ADC1 Single-Ended or Differential Analog Input 1. 63 ADC2/CMP0 Single-Ended or Differential Analog Input 2 (ADC2). Comparator Positive Input (CMP0). 64 ADC3/CMP1 Single-Ended or Differential Analog Input 3 (ADC3). Comparator Negative Input (CMP1). Rev. D | Page 18 of 110

Data Sheet ADuC7124/ADuC7126 ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 ADC11 GNDREFAGND AGND AVDDDACREFVREF IOGND IOVDD P4.5/AD13/PLAO[13]/RTCK P4.4/AD12/PLAO[12] P4.3/AD11/PLAO[11] P4.2/AD10/PLAO[10] P1.0/T1/SPM0/SIN0/I2C0SCL/PLAI[0] P1.1/SPM1/SOUT0/I2C0SDA/PLAI[1] P1.2/SPM2/RTS/I2C1SCL/PLAI[2] 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ADC4 1 60 P1.3/SPM3/CTS/I2C1SDA/PLAI[3] ADC5 2 PIN 1 59 P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2 ADC6 3 58 P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3 ADC7 4 57 P4.1/SPM11/SOUT1/AD9/PLAO[9] ADC8 5 56 P4.0/SPM10/SIN1/AD8/PLAO[8] ADC9 6 55 P1.6/SPM6/PLAI[6] ADC10 7 54 P1.7/SPM7/DTR/SPICS/PLAO[0] ADCNEG 8 53 P3.7/AD7/PWMSYNC/PLAI[15] DACGND 9 ADuC7126 52 P3.6/AD6/PWMTRIP/PLAI[14] DACVDD 10 TOP VIEW 51 P2.2/RS/PWM1/PLAO[7] DAC0/ADC12 11 50 P2.1/WS/PWM0/PLAO[6] DAC1/ADC13 12 49 P2.3/SPM12/AE/SIN1 DAC2/ADC14 13 48 IOVDD DAC3/ADC15 14 47 IOGND TMS 15 46 P0.7/SPM8/ECLK/XCLK/PLAO[4]/SIN0 TDI 16 45 P2.0/SPM9/PLAO[5]/CONVSTART/SOUT0 P0.1/PWM4/BLE 17 44 P2.7/PWM3/MS3 XCLKO 18 43 IRQ1/P0.5/ADCBUSY/PLAO[2]/MS2 XCLKI 19 42 IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1 BM/P0.0/CMPOUT/PLAI[7]/MS0 20 41 RST 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DGND LVDDIOVDD IOGND P4.6/AD14/PLAO[14] P4.7/AD15/PLAO[15] P0.6/T1/MRST/PLAO[3]/MS3 TCK TDO P0.2/PWM5/BHE P3.0/AD0/PWM0/PLAI[8] P3.1/AD1/PWM1/PLAI[9] P3.2/AD2/PWM2/PLAI[10] P3.3/AD3/PWM3/PLAI[11] P2.4/SPM13/PWM0/MS0/SOUT1 P0.3/TRST/A16/ADCBUSYP2.5/PWM1/MS1 P2.6/PWM2/MS2 P3.4/AD4/PWM4/PLAI[12] P3.5/AD5/PWM5/PLAI[13] 09123-108 Figure 8. ADuC7126 Pin Configuration Table 10. Pin Function Descriptions (ADuC7126 80-Lead LQFP) Pin No. Mnemonic Description 1 ADC4 Single-Ended or Differential Analog Input 4. 2 ADC5 Single-Ended or Differential Analog Input 5. 3 ADC6 Single-Ended or Differential Analog Input 6. 4 ADC7 Single-Ended or Differential Analog Input 7. 5 ADC8 Single-Ended or Differential Analog Input 8. 6 ADC9 Single-Ended or Differential Analog Input 9. 7 ADC10 Single-Ended or Differential Analog Input 10. 8 ADCNEG Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected to the ground of the signal to convert. This bias point must be between 0 V and 1 V. 9 DACGND Ground for the DAC. Typically connected to AGND. 10 DACV 3.3 V Power Supply for the DACs. Must be connected to AV . DD DD Rev. D | Page 19 of 110

ADuC7124/ADuC7126 Data Sheet Pin No. Mnemonic Description 11 DAC0/ADC12 DAC0 Voltage Output (DAC0). Single-Ended or Differential Analog Input 12 (ADC12). 12 DAC1/ADC13 DAC1 Voltage Output (DAC1). Single-Ended or Differential Analog Input 13 (ADC13). 13 DAC2/ADC14 DAC2 Voltage Output (DAC2). Single-Ended or Differential Analog Input 14 (ADC14). 14 DAC3/ADC15 DAC3 Voltage Output (DAC3). Single-Ended or Differential Analog Input 15 (ADC15). 15 TMS JTAG Test Port Input, Test Mode Select. Debug and download access. 16 TDI JTAG Test Port Input, Test Data In. Debug and download access. 17 P0.1/PWM4/BLE General-Purpose Input and Output Port 0.1 (P0.1). PWM Phase 4 (PWM4). External Memory Byte Low Enable (BLE). This pin does not work as GPIO on I2C versions of the chip. 18 XCLKO Output from the Crystal Oscillator Inverter. 19 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. 20 BM/P0.0/CMP /PLAI[7]/MS0 Multifunction I/O Pin. OUT Boot Mode Entry Pin (BM). The ADuC7126 enters UART download mode if BM is low at reset and executes code if BM is pulled high at reset through a 1 kΩ resistor.. The ADuC7126 enters I2C download mode in I2C version parts if BM is low at reset with a flash address of 0x800014 = 0xFFFFFFFFF. The ADuC7126 executes code if BM is pulled high at reset or if BM is low at reset with a flash address 0x800014 ≠ 0xFFFFFFFFF. General-Purpose Input and Output Port 0.0 (P0.0). Voltage Comparator Output/Programmable Logic Array Input Element 7 (CMP ). OUT External Memory Select 0 (MS0). By default, this pin is configured as GPIO. 21 DGND Ground for Core Logic. 22 LV 2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 DD μF capacitor to DGND only. 23 IOV 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. DD 24 IOGND Ground for GPIO. Typically connected to DGND. 25 P4.6/AD14/PLAO[14] General-Purpose Input and Output Port 4.6 (P4.6). External Memory Interface (AD14). Programmable Logic Array Output Element 14 (PLAO[14]). 26 P4.7/AD15/PLAO[15] General-Purpose Input and Output Port 4.7 (P4.7). External Memory Interface (AD15). Programmable Logic Array Output Element 15 (PLAO[15]). 27 P0.6/T1/MRST/PLAO[3]/MS3 Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6 (P0.6). Timer1 Input (T1). Power-On Reset Output (MRST). Programmable Logic Array Output Element 3 (PLAO[3]). External Memory Select 3 (MS3). 28 TCK JTAG Test Port Input, Test Clock. Debug and download access. 29 TDO JTAG Test Port Output, Test Data Out. Debug and download access. 30 P0.2/PWM5/BHE General-Purpose Input and Output Port 0.2 (P0.2). PWM Phase 5 (PWM5). External Memory Byte High Enable (BHE). This pin does not work as GPIO on I2C versions of the chip. 31 P3.0/AD0/PWM0/PLAI[8] General-Purpose Input and Output Port 3.0 (P3.0). External Memory Interface (AD0). PWM Phase 0 (PWM0). Programmable Logic Array Input Element 8 (PLAI[8]). 32 P3.1/AD1/PWM1/PLAI[9] General-Purpose Input and Output Port 3.1 (P3.1). External Memory Interface (AD1). PWM Phase 1 (PWM1). Programmable Logic Array Input Element 9 (PLAI[9]). Rev. D | Page 20 of 110

Data Sheet ADuC7124/ADuC7126 Pin No. Mnemonic Description 33 P3.2/AD2/PWM2/PLAI[10] General-Purpose Input and Output Port 3.2 (P3.2). External Memory Interface (AD2). PWM Phase 2 (PWM2). Programmable Logic Array Input Element 10 (PLAI[10]). 34 P3.3/AD3/PWM3/PLAI[11] General-Purpose Input and Output Port 3.3 (P3.3). External Memory Interface (AD3). PWM Phase 3 (PWM3). Programmable Logic Array Input Element 11 (PLAI[11]). 35 P2.4/SPM13/PWM0/MS0/SOUT1 General-Purpose Input and Output Port 2.4 (P2.4). Serial Port Multiplexed (SPM13) PWM Phase 0 (PWM0). External Memory Select 0 (MS0). UART1 Output (SOUT1). 36 P0.3/TRST/A16/ADC General-Purpose Input and Output Port 0.3 (P0.3). BUSY JTAG Test Port Input, Test Reset (TRST).JTAG Reset Input. Debug and download access. If this pin is held low, JTAG access is not possible because the JTAG interface is held in reset and P0.1/P0.2/P0.3 are configured as GPIO pins. Address Line (A16). ADC Signal Output (ADC ). BUSY BUSY 37 P2.5/PWM1/MS1 General-Purpose Input and Output Port 2.5 (P2.5). PWM Phase 1 (PWM1). External Memory Select 1 (MS1). 38 P2.6/PWM2/MS2 General-Purpose Input and Output Port 2.6 (P2.6). PWM Phase 2 (PWM2). External Memory Select 2 (MS2). 39 P3.4/AD4/PWM4/PLAI[12] General-Purpose Input and Output Port 3.4 (P3.4). External Memory Interface (AD4). PWM Phase 4 (PWM4). Programmable Logic Array Input 12 (PLAI[12]). 40 P3.5/AD5/PWM5/PLAI[13] General-Purpose Input and Output Port 3.5 (P3.5). External Memory Interface (AD5). PWM Phase 5 (PWM5). Programmable Logic Array Input Element 13 (PLAI[13]). 41 RST Reset Input, Active Low. 42 IRQ0/P0.4/PWM /PLAO[1]/MS1 Multifunction I/O Pin. TRIP External Interrupt Request 0, Active High (IRQ0). General-Purpose Input and Output Port 0.4 (P0.4). PWM Trip External Input (PWM ). TRIP Programmable Logic Array Output Element 1 (PLAO[1]). External Memory Select 1 (MS1).. 43 IRQ1/P0.5/ADC /PLAO[2]/MS2 Multifunction I/O Pin. BUSY External Interrupt Request 1, Active High (IRQ1). General-Purpose Input and Output Port 0.5 (P0.5). ADC Signal Output (ADC ). BUSY BUSY Programmable Logic Array Output Element 2 (PLAO[2]). External Memory Select 2 (MS2). 44 P2.7/PWM3/MS3 General-Purpose Input and Output Port 2.7 (P2.7). PWM Phase 3 (PWM3). External Memory Select 3 (MS3). 45 P2.0/SPM9/PLAO[5]/CONV /SOUT0 General-Purpose Input and Output Port 2.0 (P2.0). START Serial Port Multiplexed (SPM9). Programmable Logic Array Output Element 5 (PLAO[5]). Start Conversion Input Signal for ADC (CONV ). START UART0 Output (SOUT0). 46 P0.7/SPM8/ECLK/XCLK/PLAO[4]/SIN0 General-Purpose Input and Output Port 0.7 (P0.7). Serial Port Multiplexed (SPM8). Output for External Clock Signal (ECLK). Input to the Internal Clock Generator Circuits (XCLK). Programmable Logic Array Output Element 4 (PLAO[4]). UART0 Input (SIN0). 47 IOGND Ground for GPIO. Typically connected to DGND. Rev. D | Page 21 of 110

ADuC7124/ADuC7126 Data Sheet Pin No. Mnemonic Description 48 IOV 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. DD 49 P2.3/SPM12/AE/SIN1 General-Purpose Input and Output Port 2.3 (P2.3). Serial Port Multiplexed (SPM12). External Memory Access Enable (AE). UART1 Input (SIN1). 50 P2.1/WS/PWM0/PLAO[6] General-Purpose Input and Output Port 2.1 (P2.1). External Memory Write Strobe (WS). PWM Phase 0 (PWM0). Programmable Logic Array Output Element 6 (PLAO[6]). 51 P2.2/RS/PWM1/PLAO[7] General-Purpose Input and Output Port 2.2 (P2.2). External Memory Read Strobe (RS). PWM Phase 1 (PWM1). Programmable Logic Array Output Element 7 (PLAO[7]). 52 P3.6/AD6/PWM /PLAI[14] General-Purpose Input and Output Port 3.6 (P3.6). TRIP External Memory Interface (AD6). PWM Safety Cutouff (PWM ). TRIP Programmable Logic Array Input Element 14 (PLAI[14]). 53 P3.7/AD7/PWM /PLAI[15] General-Purpose Input and Output Port 3.7 (P3.7). SYNC External Memory Interface (AD7). PWM Synchronization (PWM ). SYNC Programmable Logic Array Input Element 15 (PLAI[15]). 54 P1.7/SPM7/DTR/SPICS/PLAO[0] General-Purpose Input and Output Port 1.7 (P1.7). Serial Port Multiplexed (SPM7). Data Terminal Ready (DTR). Chip Select (SPICS). Programmable Logic Array Output Element 0 (PLAO[0]). 55 P1.6/SPM6/PLAI[6] General-Purpose Input and Output Port 1.6 (P1.6). Serial Port Multiplexed (SPM6). Programmable Logic Array Input Element 6 (PLAI[6]). 56 P4.0/SPM10/SIN1/AD8/PLAO[8] General-Purpose Input and Output Port 4.0 (P4.0). Serial Port Multiplexed (SPM10). UART1 Input (SIN1). External Memory Interface (AD8). Programmable Logic Array Output Element 8 (PLAO[8]). 57 P4.1/SPM11/SOUT1/AD9/PLAO[9] General-Purpose Input and Output Port 4.1 (P4.1). Serial Port Multiplexed (SPM11). UART1 Output (SOUT1). External Memory Interface (AD9). Programmable Logic Array Output Element 9 (PLAO[9]). 58 P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3 General-Purpose Input and Output Port 1.5 (P1.5). Serial Port Multiplexed (SPM5). Data Carrier Detect (DCD). Master Input, Slave Output (SPI MISO). Programmable Logic Array Input Element 5 (PLAI[5]). External Interrupt Request 3, Active High (IRQ3). 59 P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2 General-Purpose Input and Output Port 1.4 (P1.4). Serial Port Multiplexed (SPM4). Ring Indicator (RI). Serial Clock Input/Output (SPI SCLK). Programmable Logic Array Input Element 4 (PLAI[4]). External Interrupt Request 2, Active High (IRQ2). 60 P1.3/SPM3/CTS/I2C1SDA/PLAI[3] General-Purpose Input and Output Port 1.3 (P1.3). Serial Port Multiplexed (SPM3). Clear to Send (CTS). I2C1 (I2C1SDA). Programmable Logic Array Input Element 3 (PLAI[3]). 61 P1.2/SPM2/RTS/I2C1SCL/PLAI[2] General-Purpose Input and Output Port 1.2 (P1.2). Serial Port Multiplexed (SPM2). Ready to Send (RTS). I2C1 (I2C1SCL). Programmable Logic Array Input Element 2 (PLAI[2]). Rev. D | Page 22 of 110

Data Sheet ADuC7124/ADuC7126 Pin No. Mnemonic Description 62 P1.1/SPM1/SOUT0/I2C0SDA/PLAI[1] General-Purpose Input and Output Port 1.1 (P1.1). Serial Port Multiplexed (SPM1). UART0 Output (SOUT0). I2C0 (I2C0SDA). Programmable Logic Array Input Element 1 (PLAI[1]). 63 P1.0/T1/SPM0/SIN0/I2C0SCL/PLAI[0] General-Purpose Input and Output Port 1.0 (P1.0). Timer1 Input (T1). Serial Port Multiplexed (SPM0). UART0 Input (SIN0). I2C0 (I2C0SCL). Programmable Logic Array Input Element 0 (PLAI[0]). 64 P4.2/AD10/PLAO[10] General-Purpose Input and Output Port 4.2 (P4.2). External Memory Interface (AD10). Programmable Logic Array Output Element 10 (PLAO[10]). 65 P4.3/AD11/PLAO[11] General-Purpose Input and Output Port 4.3 (P4.3). External Memory Interface (AD11). Programmable Logic Array Output Element 11 (PLAO[11]). 66 P4.4/AD12/PLAO[12] General-Purpose Input and Output Port 4.4 (P4.4). External Memory Interface (AD12). Programmable Logic Array Output Element 12 (PLAO[12]). 67 P4.5/AD13/PLAO[13]/RTCK General-Purpose Input and Output Port 4.5 (P4.5). External Memory Interface (AD13). Programmable Logic Array Output Element 13 (PLAO[13]). JTAG Return Test Clock (RTCK). 68 IOV 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. DD 69 IOGND Ground for GPIO. Typically connected to DGND. 70 V 2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using REF the internal reference. 71 DAC External Voltage Reference for the DACs. Range: DACGND to DACV . REF DD 72 AV 3.3 V Analog Power. DD 73, 74 AGND Analog Ground. Ground reference point for the analog circuitry. 75 GND Ground Voltage Reference for the ADC. For optimal performance, the analog power REF supply should be separated from IOGND and DGND. 76 ADC11 Single-Ended or Differential Analog Input 11. 77 ADC0 Single-Ended or Differential Analog Input 0. 78 ADC1 Single-Ended or Differential Analog Input 1. 79 ADC2/CMP0 Single-Ended or Differential Analog Input 2 (ADC2). Comparator Positive Input (CMP0). 80 ADC3/CMP1 Single-Ended or Differential Analog Input 3 (ADC3). Comparator Negative Input (CMP1). Rev. D | Page 23 of 110

ADuC7124/ADuC7126 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.4 0.3 0.3 0.2 0.2 DNL (LSB) 0.1 DNL (LSB) 0.10 0 –0.1 –0.1 –0.2 09123-208 –0.2 09123-210 0 500 1000 1500 2000 2500 3000 3500 40004095 0 500 1000 1500 2000 2500 3000 3500 40004095 ADC CODES ADC CODES Figure 9. Typical DNL Error, Figure 11. Typical DNL Error, Temperature 25°C, VREF = Internal 2.5 V, Single-Ended Mode Temperature 25°C, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC0, ADCCN = ADC0, Sampling Rate = 345 kHz ADCCP = DAC1/ADC13, ADCCN = ADC0, Sampling Rate = 345 kHz Worst Case Positive = 0.38 LSB, Code 1567 Worst Case Positive = 0.40 LSB, Code 607 Worst Case Negative= −0.24 LSB, Code 4094 Worst Case Negative= −0.27 LSB, Code 2486 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 INL (LSB)–00..110 INL (LSB)–00..110 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 ––00..56 09123-209 ––00..56 09123-211 0 500 1000 1500 2000 2500 3000 3500 40004095 0 500 1000 1500 2000 2500 3000 3500 40004095 ADC CODES ADC CODES Figure 10. Typical INL Error, Figure 12. Typical INL Error, Temperature 25°C, VREF = Internal 2.5 V, Single-Ended Mode Temperature 25°C, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC0, ADCCN = ADC0, Sampling Rate = 345 kHz ADCCP = DAC1/ADC13, ADCCN = ADC0, Sampling Rate = 345 kHz Worst Case Positive = 0.60 LSB, Code 1890 Worst Case Positive = 0.58 LSB, Code 480 Worst Case Negative= −0.54 LSB, Code 3485 Worst Case Negative= −0.54 LSB, Code 3614 Rev. D | Page 24 of 110

Data Sheet ADuC7124/ADuC7126 0.4 0.4 0.3 0.3 0.2 0.2 B) B) LS 0.1 LS 0.1 L ( L ( N N D 0 D 0 –0.1 –0.1 ––00..23 09123-212 –0.2 09123-214 0 0 0 0 0 0 0 0 05 0 0 0 0 0 0 0 0 05 0 0 0 0 0 0 0 09 0 0 0 0 0 0 0 09 5 0 5 0 5 0 5 00 5 0 5 0 5 0 5 00 1 1 2 2 3 3 44 1 1 2 2 3 3 44 ADC CODES ADC CODES Figure 13. Typical DNL Error, Figure 15. Typical DNL Error, Temperature 25°C, VREF = Internal 2.5 V, Single-Ended Mode Temperature 25°C, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC8, ADCCN = ADC0, Sampling Rate = 345 kHz ADCCP = DAC3/ADC15, ADCCN = ADC0, Sampling Rate = 345 kHz Worst-Case Positive = 0.42 LSB, Code 3583 Worst-Case Positive = 0.41 LSB, Code 2016 Worst-Case Negative = −0.32 LSB, Code 3073 Worst-Case Negative = −0.26 LSB, Code 3841 0.8 0.6 0.5 0.6 0.4 0.4 0.3 0.2 0.2 B) B) 0.1 S S L (L 0 L (L 0 IN IN–0.1 –0.2 –0.2 –0.4 –0.3 –0.4 ––00..68 09123-213 –––000...566 09123-215 0 500 1000 1500 2000 2500 3000 3500 40004095 0 500 1000 1500 2000 2500 3000 3500 40004095 ADC CODES ADC CODES Figure 14. Typical INL Error, Figure 16. Typical INL Error, Temperature 25°C, VREF = Internal 2.5 V, Single-Ended Mode Temperature 25°C, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC8, ADCCN = ADC0, Sampling Rate = 345 kHz ADCCP = DAC3/ADC15, ADCCN = ADC0, Sampling Rate = 345 kHz Worst-Case Positive = 0.64 LSB, Code 802 Worst-Case Positive = 0.55 LSB, Code 738 Worst-Case Negative = −0.69 LSB, Code 3485 Worst-Case Negative = −0.68 LSB, Code 3230 Rev. D | Page 25 of 110

ADuC7124/ADuC7126 Data Sheet 20 20 SNR: 69.85dB SNR: 65.97dB dB) 0 TPHHDS:N –: 7–98.29.19d3BdB, 29.771kHz dB) 0 PTHHDS:N –: 7–87.76.38d3BdB, 146.6038kHz DC ( –20 DC ( –20 A A F F O –40 O –40 N N S S H H P –60 P –60 D D N N A A D, –80 D, –80 H H T T D, –100 D, –100 A A N N SI––112400 09123-216 SI––112400 09123-219 0 50 100 150 174.1 0 50 100 150 174.1 FREQUENCY (kHz) FREQUENCY (kHz) Figure 17. SINAD, THD, and PHSN of ADC, Figure 20. SINAD, THD, and PHSN of ADC, VREF = Internal 2.5 V, Single-Ended Mode VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC0 ADCCP = ADC15/DAC3, ADCCN = ADC0 20 0.2 SNR: 67.10dB DAC0 dB) 0 TPHHDS:N –: 7–97.67.91d4BdB, 54.9738kHz DAC1 DC ( –20 0.1 A F O –40 N B) AND PHS –60 DNL (LS 0 D, –80 H T D, –100 –0.1 A N SI––112400 09123-217 –0.2 09123-220 0 50 100 150 174.1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 05 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 09 FREQUENCY (kHz) 2 5 7 10 12 15 17 20 22 25 27 30 32 35 37 4040 ADC CODES Figure 18. SINAD, THD, and PHSN of ADC, Figure 21. DAC DNL Error, VREF = Internal 2.5 V, Single-Ended Mode DAC0 Max Positive DNL: 0.188951, DAC1 Max Positive DNL: 0.190343 ADCCP = DAC1/ADC13, ADCCN = ADC0 DAC0 Max Negative DNL: −0.120081, DAC1 Max Negative DNL: −0.15697 20 2.0 SNR: 67.44dB DAC0 dB) 0 TPHHDS:N –: 8–27.93.33d1BdB, 54.9738kHz 1.5 DAC1 DC ( –20 1.0 A F 0.5 O –40 ND PHSN –60 NL (LSB)–0.50 A I HD, –80 –1.0 T AD, –100 –1.5 N SI––112400 09123-218 ––22..05 09123-221 0 50 100 150 174.1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 05 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 09 FREQUENCY (kHz) 2 5 7 10 12 15 17 20 22 25 27 30 32 35 37 4040 ADC CODES Figure 19. SINAD, THD, and PHSN of ADC, Figure 22. DAC INL Error, VREF = Internal 2.5 V, Single-Ended Mode DAC0 Max Positive INL: 1.84106, DAC1 Max Positive INL: 1.75312 ADCCP = ADC8, ADCCN = ADC0 DAC0 Max Negative INL: −0.887319, DAC1 Max Negative INL: −2.23708 Rev. D | Page 26 of 110

Data Sheet ADuC7124/ADuC7126 TERMINOLOGY ADC SPECIFICATIONS The ratio is dependent upon the number of quantization levels in the digitization process; the more levels there are, the smaller Integral Nonlinearity (INL) the quantization noise becomes. The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The theoretical signal to (noise + distortion) ratio for an ideal The endpoints of the transfer function are zero scale, a point N-bit converter with a sine wave input is given by ½ LSB below the first code transition, and full scale, a point Signal to (Noise + Distortion) = (6.02 N + 1.76) dB ½ LSB above the last code transition. Thus, for a 12-bit converter, this is 74 dB. Differential Nonlinearity (DNL) Total Harmonic Distortion The difference between the measured and the ideal 1 LSB The ratio of the rms sum of the harmonics to the fundamental. change between any two adjacent codes in the ADC. DAC SPECIFICATIONS Offset Error The deviation of the first code transition (0000…000) to Relative Accuracy (0000…001) from the ideal, that is, ½ LSB. Otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing Gain Error through the endpoints of the DAC transfer function. It is The deviation of the last code transition from the ideal AIN measured after adjusting for zero error and full-scale error. voltage (full scale − 1.5 LSB) after the offset error has been adjusted out. Voltage Output Settling Time The amount of time it takes the output to settle to within a Signal to (Noise + Distortion) Ratio 1 LSB level for a full-scale input change. The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f/2), excluding dc. S Rev. D | Page 27 of 110

ADuC7124/ADuC7126 Data Sheet OVERVIEW OF THE ARM7TDMI CORE The ARM7® core is a 32-bit reduced instruction set computer EXCEPTIONS (RISC). It uses a single 32-bit bus for instruction and data. The ARM supports five types of exceptions and a privileged length of the data can be eight bits, 16 bits, or 32 bits. The processing mode for each type. The five types of exceptions are length of the instruction word is 32 bits.  Normal interrupt or IRQ. This is provided to service The ARM7TDMI is an ARM7 core with four additional general-purpose interrupt handling of internal and features. external events.  T support for the Thumb® (16-bit) instruction set.  Fast interrupt or FIQ. This is provided to service data  D support for debug. transfers or communication channels with low latency. FIQ  M support for long multiplications. has priority over IRQ.  I includes the EmbeddedICE module to support embedded  Memory abort. system debugging.  Attempted execution of an undefined instruction.  Software interrupt instruction (SWI). This can be used to THUMB MODE (T) make a call to an operating system. An ARM instruction is 32 bits long. The ARM7TDMI Typically, the programmer defines an interrupt as IRQ, but for processor supports a second instruction set that has been higher priority interrupt, that is, faster response time, the compressed into 16 bits, called the Thumb instruction set. programmer can define an interrupt as FIQ. Faster execution from 16-bit memory and greater code density can usually be achieved by using the Thumb instruction set ARM REGISTERS instead of the ARM instruction set, which makes the ARM7TDMI has a total of 37 registers: 31 general-purpose ARM7TDMI core particularly suitable for embedded registers and six status registers. Each operating mode has applications. dedicated banked registers. However, the Thumb mode has two limitations: When writing user-level programs, 15 general-purpose, 32-bit  Thumb code typically requires more instructions for the registers (R0 to R14), the program counter (R15), and the current same job. As a result, ARM code is usually best for program status register (CPSR) are usable. The remaining maximizing the performance of time-critical code. registers are only used for system-level programming and  The Thumb instruction set does not include some of the exception handling. instructions needed for exception handling, which When an exception occurs, some of the standard registers are automatically switches the core to ARM code for exception replaced with registers specific to the exception mode. All excep- handling. tion modes have replacement banked registers for the stack pointer See the ARM7TDMI user guide for details on the core (R13) and the link register (R14), as represented in Figure 23. architecture, the programming model, and both the ARM The fast interrupt mode has more registers (R8 to R12) for fast and ARM Thumb instruction sets. interrupt processing. This means that the interrupt processing can begin without the need to save or restore these registers, and LONG MULTIPLY (M) therefore, save critical time in the interrupt handling process. The ARM7TDMI instruction set includes four extra instruc- R0 USABLE IN USER MODE tions that perform 32-bit by 32-bit multiplication with a 64-bit R1 SYSTEM MODES ONLY result and 32-bit by 32-bit multiplication-accumulation (MAC) R2 with a 64-bit result. These results are achieved in fewer cycles R3 R4 than required on a standard ARM7 core. R5 EmbeddedICE (I) R6 R7 R8_FIQ EmbeddedICE provides integrated on-chip support for the core. R8 R9_FIQ R9 The EmbeddedICE module contains the breakpoint and watch- R10_FIQ R10 point registers that allow code to be halted for debugging purposes. R11 R11_FIQ R13_IRQ R13_UND R12_FIQ R13_ABT R14_UND These registers are controlled through the JTAG test port. R12 R13_SVC R14_IRQ R13_FIQ R14_ABT R13 R14_SVC When a breakpoint or watchpoint is encountered, the processor R14 R14_FIQ halts and enters debug state. Once in a debug state, the proces- R15 (PC) sor registers can be inspected as well as the Flash/EE, SRAM, SPSR_UND SPSR_IRQ SPSR_ABT and memory mapped registers. CPSR SPSR_SVC SPSR_FIQ USER MODE MFOIQDE MSOVDCE AMBOODRET MIORQDE UNDMEOFDINEED 09123-007 Figure 23. Register Organization Rev. D | Page 28 of 110

Data Sheet ADuC7124/ADuC7126 More information relative to the model of the programmer and At the end of this time, the ARM7TDMI executes the instruction the ARM7TDMI core architecture can be found in the at 0x1C (FIQ interrupt vector address). The maximum total following materials from ARM: time is 50 processor cycles, which is just under 1.2 µs in a system using a continuous 41.78 MHz processor clock. • DDI0029G, ARM7TDMI Technical Reference Manual • DDI-0100, ARM Architecture Reference Manual The maximum interrupt request (IRQ) latency calculation is similar but must allow for the fact that FIQ has higher priority INTERRUPT LATENCY and can delay entry into the IRQ handling routine for an The worst-case latency for a fast interrupt request (FIQ) arbitrary length of time. This time can be reduced to 42 cycles if consists of the following: the LDM command is not used. Some compilers have an option to compile without using this command. Another option is to run • The longest time the request can take to pass through the the part in Thumb mode where the time is reduced to 22 cycles. synchronizer • The time for the longest instruction to complete (the The minimum latency for FIQ or IRQ interrupts is a total of longest instruction is an LDM) that loads all the registers five cycles, which consist of the shortest time the request can including the PC take through the synchronizer plus the time to enter the • The time for the data abort entry exception mode. • The time for the FIQ entry Note that the ARM7TDMI always runs in ARM (32-bit) mode when in privileged modes, for example, when executing interrupt service routines. Rev. D | Page 29 of 110

ADuC7124/ADuC7126 Data Sheet MEMORY ORGANIZATION The ADuC7124/ADuC7126 incorporate three separate blocks FLASH/EE MEMORY of memory: 32 kB of SRAM and two 64 kB blocks of on-chip The 128 kB of Flash/EE are organized as two banks of 32 k × Flash/EE memory. There are 126 kB of on-chip Flash/EE memory 16 bits. Block 0 starts at Address 0x90000 and finishses at available to the user, and the remaining 2 kB are reserved for the Address 0x9F700. In this block, 31 k × 16 bits is user space and system kernel. These blocks are mapped as shown in Figure 24. 1 k × 16 bits is reserved for the factory-configured boot page. Note that, by default, after a reset, the Flash/EE memory is The page size of this Flash/EE memory is 512 bytes. mirrored at Address 0x00000000. It is possible to remap the Block 1 starts at Address 0x80000 and finishses at Address SRAM at Address 0x00000000 by clearing Bit 0 of the REMAP 0x90000. In this block, all 64 kB are available as user space. The MMR. This remap function is described in more detail in the block is arranged in 32 k × 16 bits. Flash/EE memory chapter. The 126 kB of Flash/EE are available to the user as code and 0xFFFFFFFF nonvolatile data memory. There is no distinction between data MMRs 0xFFFF0000 and program because ARM code shares the same space. The RESERVED real width of the Flash/EE memory is 16 bits, meaning that, in ARM mode (32-bit instruction), two accesses to the Flash/EE 0x0009F800 are necessary for each instruction fetch. Therefore, it is recom- FLASH/EE mended that Thumb mode be used when executing from 0x00080000 Flash/EE memory for optimum access speed. The maximum RESERVED access speed for the Flash/EE memory is 41.78 MHz in Thumb 0x00047FFF SRAM mode and 20.89 MHz in full ARM mode (see the Execution 0x00040000 Time from SRAM and Flash/EE section). RESERVED 0x0001FFFF SRAM REMAPPABLE MEMORY SPACE 0x00000000 (FLASH/EE OR SRAM) 09123-025 T8 hke × 3 322 k bBi tos,f tShRatA isM, 1 a6r ke wavoaridlasb. AleR toM t hcoe dues cear,n o rrugnan diizreedct lays f rom Figure 24. Physical Memory Map SRAM at 41.78 MHz, given that the SRAM array is configured as a 32-bit wide memory array (see the Execution Time from MEMORY ACCESS SRAM and Flash/EE section). The ARM7 core sees memory as a linear array of a 232 byte MEMORY MAPPED REGISTERS location where the different blocks of memory are mapped as outlined in Figure 24. The memory mapped register (MMR) space is mapped into the upper two pages of the memory array and accessed by indirect The ADuC7124/ADuC7126 memory organization is configured addressing through the ARM7 banked registers. in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest The MMR space provides an interface between the CPU and byte address. all on-chip peripherals. All registers except the core registers reside in the MMR area. All shaded locations shown in Figure 26 BIT 31 BIT 0 are unoccupied or reserved locations and should not be BYTE 3 BYTE 2 BYTE 1 BYTE 0 . . . . . . . . 0xFFFFFFFF accessed by user software. Table 11 to Table 29 show the full . . . . MMR memory map. B A 9 8 7 6 5 4 0x00000004 The access time reading or writing a MMR depends on the 3 232 BITS1 0 0x00000000 09123-026 atod vaacncecsesd t mhei cpreorcipohnetrroalll.e Tr hbeu sp raorcchesitseocrt uhraes (tAwoM ABMA)B bAu sb uusseesd: Figure 25. Little Endian Format the advanced high performance bus (AHB) used for system modules, and the advanced peripheral bus (APB) used for the lower performance peripheral. Access to the AHB is one cycle, and access to the APB is two cycles. All peripherals on the ADuC7124/ADuC7126 are on the APB except the Flash/EE memory and the GPIOs. Rev. D | Page 30 of 110

Data Sheet ADuC7124/ADuC7126 0xFFFFFFFF FLASHCONTROL INTERFACE1 0xFFFFF880 FLASHCONTROL INTERFACE0 0xFFFFF800 GPIO 0xFFFFF400 EXTERNAL MEMORY 0xFFFFF000 PWM 0xFFFF0F80 PLA 0xFFFF0B00 SPI 0xFFFF0A00 I2C1 0xFFFF0900 I2C0 0xFFFF0800 UART1 0xFFFF0740 UART0 0xFFFF0700 DAC 0xFFFF0600 ADC 0xFFFF0500 BAND GAP REFERENCE 0xFFFF048C POWERSUPPLY MONITOR 0xFFFF0440 PLLAND OSCILLATORCONTROL 0xFFFF0404 WATCHDOG TIMER 0xFFFF0360 WAKE-UP TIMER 0xFFFF0340 GENERAL-PURPOSE TIMER 0xFFFF0320 TIMER0 0xFFFF0300 REMAPAND SYSTEMCONTROL 0xFFFF0220 0xFFFF0000 CIONNTTERRORULLPETR 09123-010 Figure 26. Memory Mapped Registers Rev. D | Page 31 of 110

ADuC7124/ADuC7126 Data Sheet Table 11. IRQ Base Address = 0xFFFF0000 Address Name Byte Access Type 0xFFFF0000 IRQSTA 4 R 0xFFFF0004 IRQSIG 4 R 0xFFFF0008 IRQEN 4 R/W 0xFFFF000C IRQCLR 4 W 0xFFFF0010 SWICFG 4 W 0xFFFF0014 IRQBASE 4 R/W 0xFFFF001C IRQVEC 4 R 0xFFFF0020 IRQP0 4 R/W 0xFFFF0024 IRQP1 4 R/W 0xFFFF0028 IRQP2 4 R/W 0xFFFF002C IRQP3 4 R/W 0xFFFF0030 IRQCONN 1 R/W 0xFFFF0034 IRQCONE 4 R/W 0xFFFF0038 IRQCLRE 1 W 0xFFFF003C IRQSTAN 1 R/W 0xFFFF0100 FIQSTA 4 R 0xFFFF0104 FIQSIG 4 R 0xFFFF0108 FIQEN 4 R/W 0xFFFF010C FIQCLR 4 W 0xFFFF011C FIQVEC 4 R 0xFFFF013C FIQSTAN 1 R/W Table 12. System Control Base Address = 0xFFFF0200 Address Name Byte Access Type 0xFFFF0220 REMAP 1 R/W 0xFFFF0230 RSTSTA 1 R 0xFFFF0234 RSTCLR 1 W 0xFFFF0248 RSTKEY0 1 W 0xFFFF024C RSTCFG 1 R/W 0xFFFF0250 RSTKEY1 1 W Table 13. Timer Base Address = 0xFFFF0300 Address Name Byte Access Type 0xFFFF0300 T0LD 2 R/W 0xFFFF0304 T0VAL 2 R 0xFFFF0308 T0CON 2 R/W 0xFFFF030C T0CLRI 1 W 0xFFFF0320 T1LD 4 R/W 0xFFFF0324 T1VAL 4 R 0xFFFF0328 T1CON 2 R/W 0xFFFF032C T1CLRI 1 W 0xFFFF0330 T1CAP 4 R 0xFFFF0340 T2LD 4 R/W 0xFFFF0344 T2VAL 4 R 0xFFFF0348 T2CON 2 R/W 0xFFFF034C T2CLRI 1 W 0xFFFF0360 T3LD 2 R/W 0xFFFF0364 T3VAL 2 R 0xFFFF0368 T3CON 2 R/W 0xFFFF036C T3CLRI 1 W Rev. D | Page 32 of 110

Data Sheet ADuC7124/ADuC7126 Table 14. PLL/PSM Base Address = 0xFFFF0400 Address Name Byte Access Type 0xFFFF0404 POWKEY1 2 W 0xFFFF0408 POWCON0 1 R/W 0xFFFF040C POWKEY2 2 W 0xFFFF0410 PLLKEY1 4 W 0xFFFF0414 PLLCON 1 R/W 0xFFFF0418 PLLKEY2 4 W 0xFFFF0434 POWKEY3 2 W 0xFFFF0438 POWCON1 2 R/W 0xFFFF043C POWKEY4 2 W Table 15. PSM Base Address = 0xFFFF0440 Address Name Byte Access Type 0xFFFF0440 PSMCON 2 R/W 0xFFFF0444 CMPCON 2 R/W Table 16. Reference Base Address = 0xFFFF0480 Address Name Byte Access Type 0xFFFF048C REFCON 1 R/W Table 17. ADC Base Address = 0xFFFF0500 Address Name Byte Access Type 0xFFFF0500 ADCCON 2 R/W 0xFFFF0504 ADCCP 1 R/W 0xFFFF0508 ADCCN 1 R/W 0xFFFF050C ADCSTA 1 R 0xFFFF0510 ADCDAT 4 R 0xFFFF0514 ADCRST 1 R/W 0xFFFF0530 ADCGN 2 R/W 0xFFFF0534 ADCOF 2 R/W 0xFFFF0544 TSCON 1 R/W 0xFFFF0548 TEMPREF 2 R/W Table 18. DAC Address Base = 0xFFFF0600 Address Name Byte Access Type 0xFFFF0600 DAC0CON 1 R/W 0xFFFF0604 DAC0DAT 4 R/W 0xFFFF0608 DAC1CON 1 R/W 0xFFFF060C DAC1DAT 4 R/W 0xFFFF0610 DAC2CON 1 R/W 0xFFFF0614 DAC2DAT 4 R/W 0xFFFF0618 DAC3CON 1 R/W 0xFFFF061C DAC3DAT 4 R/W 0xFFFF0650 DACBKEY1 2 W 0xFFFF0654 DACBCFG 1 R/W 0xFFFF0658 DACBKEY2 2 W Rev. D | Page 33 of 110

ADuC7124/ADuC7126 Data Sheet Table 19. UART0 Base Address = 0xFFFF0700 Address Name Byte Access Type Cycle 0xFFFF0700 COM0TX 1 R/W 2 0xFFFF0700 COM0RX 1 R 2 0xFFFF0700 COM0DIV0 1 R/W 2 0xFFFF0704 COM0IEN0 1 R/W 2 0xFFFF0704 COM0DIV1 1 R/W 2 0xFFFF0708 COM0IID0 1 R 2 0xFFFF0708 COM0FCR 1 R/W 2 0xFFFF070C COM0CON0 1 R/W 2 0xFFFF0710 COM0CON1 1 R/W 2 0xFFFF0714 COM0STA0 2 R 2 0xFFFF0718 COM0STA1 2 R 2 0xFFFF072C COM0DIV2 2 R/W 2 Table 20. UART1 Base Address = 0xFFFF0740 Address Name Byte Access Type Cycle 0xFFFF0740 COM1TX 1 R/W 2 0xFFFF0740 COM1RX 1 R 2 0xFFFF0740 COM1DIV0 1 R/W 2 0xFFFF0744 COM1IEN0 1 R/W 2 0xFFFF0744 COM1DIV1 1 R/W 2 0xFFFF0748 COM1IID0 1 R 2 0xFFFF0748 COM1FCR 1 R/W 0xFFFF074C COM1CON0 1 R/W 2 0xFFFF0750 COM1CON1 1 R/W 2 0xFFFF0754 COM1STA0 2 R 2 0xFFFF0758 COM1STA1 2 R 2 0xFFFF076C COM1DIV2 2 R/W 2 Table 21. I2C0 Base Address = 0xFFFF0800 Address Name Byte Access Type Cycle 0xFFFF0800 I2C0MCON 2 R/W 2 0xFFFF0804 I2C0MSTA 2 R 2 0xFFFF0808 I2C0MRX 1 R 2 0xFFFF080C I2C0MTX 2 R/W 2 0xFFFF0810 I2C0MCNT0 2 R/W 2 0xFFFF0814 I2C0MCNT1 1 R 2 0xFFFF0818 I2C0ADR0 1 R/W 2 0xFFFF081C I2C0ADR1 1 R/W 2 0xFFFF0824 I2C0DIV 2 R/W 2 0xFFFF0828 I2C0SCON 2 R/W 2 0xFFFF082C I2C0SSTA 2 R 2 0xFFFF0830 I2C0SRX 1 R 2 0xFFFF0834 I2C0STX 1 W 2 0xFFFF0838 I2C0ALT 1 R/W 2 0xFFFF083C I2C0ID0 1 R/W 2 0xFFFF0840 I2C0ID1 1 R/W 2 0xFFFF0844 I2C0ID2 1 R/W 2 0xFFFF0848 I2C0ID3 1 R/W 2 0xFFFF084C I2C0FSTA 1 R/W 2 Rev. D | Page 34 of 110

Data Sheet ADuC7124/ADuC7126 Table 22. I2C1 Base Address = 0xFFFF0900 Address Name Byte Access Type Cycle 0xFFFF0900 I2C1MCON 2 R/W 2 0xFFFF0904 I2C1MSTA 2 R 2 0xFFFF0908 I2C1MRX 1 R 2 0xFFFF090C I2C1MTX 2 R/W 2 0xFFFF0910 I2C1MCNT0 2 R/W 2 0xFFFF0914 I2C1MCNT1 1 R 2 0xFFFF0918 I2C1ADR0 1 R/W 2 0xFFFF091C I2C1ADR1 1 R/W 2 0xFFFF0924 I2C1DIV 2 R/W 2 0xFFFF0928 I2C1SCON 2 R/W 2 0xFFFF092C I2C1SSTA 2 R 2 0xFFFF0930 I2C1SRX 1 R 2 0xFFFF0934 I2C1STX 1 W 2 0xFFFF0938 I2C1ALT 1 R/W 2 0xFFFF093C I2C1ID0 1 R/W 2 0xFFFF0940 I2C1ID1 1 R/W 2 0xFFFF0944 I2C1ID2 1 R/W 2 0xFFFF0948 I2C1ID3 1 R/W 2 0xFFFF094C I2C1FSTA 1 R/W 2 Table 23. SPI Base Address = 0xFFFF0A00 Address Name Byte Access Type Cycle 0xFFFF0A00 SPISTA 2 R 2 0xFFFF0A04 SPIRX 1 R 2 0xFFFF0A08 SPITX 1 W 2 0xFFFF0A0C SPIDIV 1 R/W 2 0xFFFF0A10 SPICON 2 R/W 2 Table 24. PLA Base Address = 0xFFFF0B00 Address Name Byte Access Type Cycle 0xFFFF0B00 PLAELM0 2 R/W 2 0xFFFF0B04 PLAELM1 2 R/W 2 0xFFFF0B08 PLAELM2 2 R/W 2 0xFFFF0B0C PLAELM3 2 R/W 2 0xFFFF0B10 PLAELM4 2 R/W 2 0xFFFF0B14 PLAELM5 2 R/W 2 0xFFFF0B18 PLAELM6 2 R/W 2 0xFFFF0B1C PLAELM7 2 R/W 2 0xFFFF0B20 PLAELM8 2 R/W 2 0xFFFF0B24 PLAELM9 2 R/W 2 0xFFFF0B28 PLAELM10 2 R/W 2 0xFFFF0B2C PLAELM11 2 R/W 2 0xFFFF0B30 PLAELM12 2 R/W 2 0xFFFF0B34 PLAELM13 2 R/W 2 0xFFFF0B38 PLAELM14 2 R/W 2 0xFFFF0B3C PLAELM15 2 R/W 2 0xFFFF0B40 PLACLK 1 R/W 2 0xFFFF0B44 PLAIRQ 2 R/W 2 0xFFFF0B48 PLAADC 4 R/W 2 0xFFFF0B4C PLADIN 4 R/W 2 0xFFFF0B50 PLADOUT 4 R 2 0xFFFF0B54 PLALCK 1 W 2 Rev. D | Page 35 of 110

ADuC7124/ADuC7126 Data Sheet Table 25. PWM Base Address = 0xFFFF0F80 Address Name Byte Access Type Cycle 0xFFFF0F80 PWMCON0 2 R/W 2 0xFFFF0F84 PWM0COM0 2 R/W 2 0xFFFF0F88 PWM0COM1 2 R/W 2 0xFFFF0F8C PWM0COM2 2 R/W 2 0xFFFF0F90 PWM0LEN 2 R/W 2 0xFFFF0F94 PWM1COM0 2 R/W 2 0xFFFF0F98 PWM1COM1 2 R/W 2 0xFFFF0F9C PWM1COM2 2 R/W 2 0xFFFF0FA0 PWM1LEN 2 R/W 2 0xFFFF0FA4 PWM2COM0 2 R/W 2 0xFFFF0FA8 PWM2COM1 2 R/W 2 0xFFFF0FAC PWM2COM2 2 R/W 2 0xFFFF0FB0 PWM2LEN 2 R/W 2 0xFFFF0FB4 PWMCON1 2 R/W 2 0xFFFF0FB8 PWMCLRI 2 W 2 Table 26. External Memory Base Address = 0xFFFFF000 Address Name Byte Access Type Cycle 0xFFFFF000 XMCFG 1 R/W 2 0xFFFFF010 XM0CON 1 R/W 2 0xFFFFF014 XM1CON 1 R/W 2 0xFFFFF018 XM2CON 1 R/W 2 0xFFFFF01C XM3CON 1 R/W 2 0xFFFFF020 XM0PAR 2 R/W 2 0xFFFFF024 XM1PAR 2 R/W 2 0xFFFFF028 XM2PAR 2 R/W 2 0xFFFFF02C XM3PAR 2 R/W 2 Rev. D | Page 36 of 110

Data Sheet ADuC7124/ADuC7126 Table 27. GPIO Base Address = 0xFFFF0400 Address Name Byte Access Type Cycle 0xFFFFF400 GP0CON 4 R/W 1 0xFFFFF404 GP1CON 4 R/W 1 0xFFFFF408 GP2CON 4 R/W 1 0xFFFFF40C GP3CON 4 R/W 1 0xFFFFF410 GP4CON 4 R/W 1 0xFFFFF420 GP0DAT 4 R/W 1 0xFFFFF424 GP0SET 1 W 1 0xFFFFF428 GP0CLR 1 W 1 0xFFFFF42C GP0PAR 4 R/W 1 0xFFFFF430 GP1DAT 4 R/W 1 0xFFFFF434 GP1SET 1 W 1 0xFFFFF438 GP1CLR 1 W 1 0xFFFFF43C GP1PAR 4 R/W 1 0xFFFFF440 GP2DAT 4 R/W 1 0xFFFFF444 GP2SET 1 W 1 0xFFFFF448 GP2CLR 1 W 1 0xFFFFF44C GP2PAR 4 R/W 1 0xFFFFF450 GP3DAT 4 R/W 1 0xFFFFF454 GP3SET 1 W 1 0xFFFFF458 GP3CLR 1 W 1 0xFFFFF45C GP3PAR 4 R/W 1 0xFFFFF460 GP4DAT 4 R/W 1 0xFFFFF464 GP4SET 1 W 1 0xFFFFF468 GP4CLR 1 W 1 0xFFFFF46C GP4PAR 4 R/W 1 Table 28. Flash/EE Block 0 Base Address = 0xFFFFF800 Address Name Byte Access Type Cycle 0xFFFFF800 FEE0STA 1 R 1 0xFFFFF804 FEE0MOD 1 R/W 1 0xFFFFF808 FEE0CON 1 R/W 1 0xFFFFF80C FEE0DAT 2 R/W 1 0xFFFFF810 FEE0ADR 2 R/W 1 0xFFFFF818 FEE0SGN 3 R 1 0xFFFFF81C FEE0PRO 4 R/W 1 0xFFFFF820 FEE0HID 4 R/W 1 Table 29. Flash/EE Block 1 Base Address = 0xFFFFF880 Address Name Byte Access Type Cycle 0xFFFFF880 FEE1STA 1 R 1 0xFFFFF884 FEE1MOD 1 R/W 1 0xFFFFF888 FEE1CON 1 R/W 1 0xFFFFF88C FEE1DAT 2 R/W 1 0xFFFFF890 FEE1ADR 2 R/W 1 0xFFFFF898 FEE1SGN 3 R 1 0xFFFFF89C FEE1PRO 4 R/W 1 0xFFFFF8A0 FEE1HID 4 R/W 1 Rev. D | Page 37 of 110

ADuC7124/ADuC7126 Data Sheet ADC CIRCUIT OVERVIEW The analog-to-digital converter is a fast, multichannel, 12-bit The ideal code transitions occur midway between successive ADC. It can operate from 2.7 V to 3.6 V supplies and is capable integer LSB values (that is, ½ LSB, 3⁄2 LSB, 5⁄2 LSB, … , of providing a throughput of up to 1 MSPS when the clock source FS − 3/2 LSB). The ideal input/output transfer characteristic is 41.78 MHz. This block provides the user with a multichannel is shown in Figure 28. multiplexer, a differential track-and-hold, an on-chip reference, and an ADC. 1111 1111 1111 The ADC consists of a 12-bit successive approximation con- 1111 1111 1110 verter based around two capacitor DACs. Depending on the 1111 1111 1101 E input signal configuration, the ADC can operate in one of OD1111 1111 1100 FULL- C SCALE three different modes. UT 1LSB = 4096 P T  Fully differential mode, for small and balanced signals OU  Single-ended mode, for any single-ended signals 0000 0000 0011  Pseudo differential mode, for any single-ended signals, 0000 0000 0010 taking advantage of the common-mode rejection offered 0000 0000 0001 The cboyn tvheer tpesre aucdceop dtsif afenr eanntailaolg i ninppuut t range of 0 V to V when 0000 0000 00000V1LSB VOLTAGE INPUT +FS – 1LSB 09123-012 REF Figure 28. ADC Transfer Function in Pseudo Differential or Single-Ended Mode operating in single-ended or pseudo differential mode. In fully differential mode, the input signal must be balanced around a Fully Differential Mode common-mode voltage (VCM) in the 0 V to AVDD range with a The amplitude of the differential signal is the difference between maximum amplitude of 2 × VREF (see Figure 27). the signals applied to the VIN+ and VIN– pins (that is, VIN+ – VIN–). V is selected by the ADCCP register, and V is selected by IN+ IN− AVDD the ADCCN register. The maximum amplitude of the differential VCM 2VREF signal is, therefore, –VREF to +VREF p-p (that is, 2 × VREF). This is VCM 2VREF regardless of the common mode (CM). The common mode is the average of the two signals, for example, (V + V )/2, and IN+ IN– is, therefore, the voltage that the two inputs are centered on. 0 VCM 2VREF 09123-011 vTohlitsa grees mulutss ti nb eth see ts puapn e oxtfe erancahll iyn, panudt bitesi nragn CgMe v ±ar VieRsE wF/2it.h T Vhis Figure 27. Examples of Balanced Signals in Fully Differential Mode REF (see the Driving the Analog Inputs section). A high precision, low drift, factory calibrated, 2.5 V reference is The output coding is twos complement in fully differential mode provided on chip. An external reference can also be connected as with 1 LSB = 2 × V /4096, or 2 × 2.5 V/4096 = 1.22 mV when described in the Band Gap Reference section. REF V = 2.5 V. The output result is ±11 bits, but this is shifted by REF Single or continuous conversion modes can be initiated in the one to the right. This allows the result in ADCDAT to be declared software. An external CONVSTART pin, an output generated from as a signed integer when writing C code. The designed code the on-chip PLA, or a Timer0 or Timer1 overflow can also be transitions occur midway between successive integer LSB values used to generate a repetitive trigger for ADC conversions. (that is, ½ LSB, 3⁄2 LSB, 5⁄2 LSB, … , FS − 3⁄2 LSB). The ideal A voltage output from an on-chip band gap reference propor- input/output transfer characteristic is shown in Figure 29. tional to absolute temperature can also be routed through the SIGN BIT front-end ADC multiplexer, effectively an additional ADC channel 0 1111 1111 1110 input. This facilitates an internal temperature sensor channel 0 1111 1111 1100 1LSB =2 ×4 0V9R6EF that measures die temperature. 0 1111 1111 1010 E D TRANSFER FUNCTION O C T 0 0000 0000 0010 Pseudo Differential and Single-Ended Modes U P0 0000 0000 0000 T U In pseudo differential or single-ended mode, the input range is O1 1111 1111 1110 0 V to V . The output coding is straight binary in pseudo REF differential and single-ended modes with 1 0000 0000 0100 1 0000 0000 0010 1 LSB = Full-Scale/4096, or 1 0000 0000 0000 261.50 V μ/V4 0w9h6e =n 0V.6RE1F m= V2.,5 o Vr –VREF + 1LSBVOLTAGE0 ILNSPBUT (VIN+ – VIN+–V)REF – 1LSB 09123-013 Figure 29. ADC Transfer Function in Differential Mode Rev. D | Page 38 of 110

Data Sheet ADuC7124/ADuC7126 TYPICAL OPERATION MMRS INTERFACE Once configured via the ADC control and channel selection The ADC is controlled and configured via the eight MMRs. registers, the ADC converts the analog input and provides a ADCCON Register 12-bit result in the ADC data register. Name: ADCCON The top four bits are the sign bits. The 12-bit result is placed in Bit 16 to Bit 27 as shown in Figure 30. Again, it should be noted Address: 0xFFFF0500 that in fully differential mode, the result is represented in twos Default Value: 0x0600 complement format. In pseudo differential and single-ended modes, the result is represented in straight binary format. Access: Read/write 31 27 1615 0 ADCCON is an ADC control register that allows the program- SIGN BITS 12-BIT ADC RESULT 09123-014 mof etrh teo A eDnaCb l(ee itthhee rA iDn Csi npgelreip-ehnedraedl, smeloedcte ,t hpese mudood ed iofff eorpeenrtaiatilo n Figure 30. ADC Result Format mode, or fully differential mode), and select the conversion The same format is used in DACxDAT, simplifying the software. type. This MMR is described in Table 30. Current Consumption Table 30. ADCCON MMR Bit Descriptions The ADC in standby mode, that is, powered up but not Bit Value Description converting, typically consumes 640 μA. The internal reference [15:14] Reserved. adds 140 μA. During conversion, the extra current is 0.3 μA 13 Set by the user to enable edge trigger mode. multiplied by the sampling frequency (in kHz). Cleared by the user to enable level trigger Timing mode. [12:10] ADC clock speed. Figure 31 gives details of the ADC timing. The user controls the 000 f /1. This divider is provided to obtain ADC clock speed and the number of acquisition clocks in the ADC 1 MSPS ADC with an external clock <41.78 MHz. ADCCON MMR. By default, the acquisition time is eight 001 f /2 (default value). ADC clocks, and the clock divider is two. The number of extra clocks 010 f /4. (such as bit trial or write) is set to 19, which gives a sampling ADC 011 f /8. rate of 774 kSPS. For conversion on temperature sensor, the ADC 100 f /16. ADC acquisition time is automatically set to 16 clocks, and the ADC 101 f /32. ADC clock divider is set to 32. When using multiple channels ADC [9:8] ADC acquisition time. including the temperature sensor, the timing settings revert to 00 Two clocks. the user-defined settings after reading the temperature sensor channel. 01 Four clocks. 10 Eight clocks (default value). ACQ BIT TRIAL WRITE 11 16 clocks. 7 Enable start conversion. ADC CLOCK Set by the user to start any type of conversion command. Cleared by the user to disable a start CONVSTART conversion (clearing this bit does not stop the ADC when continuously converting). 6 Enable ADC . ADCBUSY BUSY Set by the user to enable the ADC pin. BUSY Cleared by the user to disable the ADC pin. BUSY ADCDAT DATA 5 ADC power control. Set by the user to place the ADC in normal ADCSTA = 0 ADCSTA = 1 mode (the ADC must be powered up for at least ADC INTERRUPT 09123-015 5C lμesa rbeedf obrye tiht eco unsveer rttos pcolarcreec tthlye) .A DC in power- Figure 31. ADC Timing down mode. [4:3] Conversion mode. 00 Single-ended mode. 01 Differential mode. 10 Pseudo differential mode. 11 Reserved. Rev. D | Page 39 of 110

ADuC7124/ADuC7126 Data Sheet Bit Value Description Table 31. ADCCP1 MMR Bit Designation [2:0] Conversion type. Bit Value Description 000 Enable CONV pin as a conversion input. START [7:5] Reserved. 001 Enable Timer1 as a conversion input. [4:0] Positive channel selection bits. 010 Enable Timer0 as a conversion input. 00000 ADC0. 011 Single software conversion. Sets to 000 after 00001 ADC1. conversion (note that Bit 7 of ADCCON MMR 00010 ADC2. should be cleared after starting a single software conversion to avoid further 00011 ADC3. conversions triggered by the CONVSTART pin). 00100 ADC4. 100 Continuous software conversion. 00101 ADC5. 101 PLA conversion. 00110 ADC6. Other Reserved. 00111 ADC7. 01000 ADC8. ADCCP Register 01001 ADC9. Name: ADCCP 01010 ADC10. 01011 ADC11. Address: 0xFFFF0504 01100 DAC0/ADC12. Default Value: 0x00 01101 DAC1/ADC13. 01110 DAC2/ADC14. Access: Read/write 01111 DAC3/ADC15. ADCCP is an ADC positive channel selection register. This 10000 Temperature sensor. MMR is described in Table 31. 10001 AGND (self-diagnostic feature). 10010 Internal reference (self-diagnostic feature). 10011 AV /2. DD Others Reserved. 1 ADC and DAC channel availability depends on part model. See the Ordering Guide for details. Rev. D | Page 40 of 110

Data Sheet ADuC7124/ADuC7126 ADCCN Register on P0.5 (see the General-Purpose Input/Output section) if enabled in the ADCCON register. Name: ADCCN ADCDAT Register Address: 0xFFFF0508 Name: ADCDAT Default Value: 0x01 Address: 0xFFFF0510 Access: Read/write Default Value: 0x00000000 ADCCN is an ADC negative channel selection register. This Access: Read only MMR is described in Table 32. ADCDAT is an ADC data result register that holds the 12-bit Table 32. ADCCN MMR Bit Designation ADC result, as shown in Figure 30. Bit Value Description ADCRST Register [7:5] Reserved. [4:0] Negative channel selection bits. Name: ADCRST 00000 ADC0. Address: 0xFFFF0514 00001 ADC1. 00010 ADC2. Default Value: 0x00 00011 ADC3. Access: Read/write 00100 ADC4. 00101 ADC5. ADCRST resets the digital interface of the ADC. Writing any value 00110 ADC6. to this register resets all the ADC registers to their default values. 00111 ADC7. ADCGN Register 01000 ADC8. Name: ADCGN 01001 ADC9. 01010 ADC10. Address: 0xFFFF0530 01011 ADC11. 01100 DAC0/ADC12. Default Value: 0x0200 01101 DAC1/ADC13. Access: Read/write 01110 DAC2/ADC14. 01111 DAC3/ADC15. ADCGN is a 10-bit gain calibration register. 10000 Reserved. ADCOF Register 10001 AGND. Name: ADCOF 10010 Reserved. 10011 Reserved. Address: 0xFFFF0534 Others Reserved. Default Value: 0x0200 ADCSTA Register Name: ADCSTA Access: Read/write Address: 0xFFFF050C ADCOF is a 10-bit offset calibration register. CONVERTER OPERATION Default Value: 0x00 The ADC incorporates a successive approximation (SAR) Access: Read only architecture involving a charge-sampled input stage. This architecture can operate in three different modes: differential, ADCSTA is an ADC status register that indicates when an ADC pseudo differential, and single-ended. conversion result is ready. The ADCSTA register contains only one bit, ADCReady (Bit 0), representing the status of the ADC. Differential Mode This bit is set at the end of an ADC conversion, generating an The ADuC7124/ADuC7126 each contains a successive approx- ADC interrupt. It is cleared automatically by reading the imation ADC based on two capacitive DACs. Figure 32 and ADCDAT MMR. When the ADC is performing a conversion, Figure 33 show simplified schematics of the ADC in acquisition the status of the ADC can be read externally via the ADCBUSY and conversion phases, respectively. The ADC comprises con- pin. This pin is high during a conversion. When the conversion trol logic, a SAR, and two capacitive DACs. In Figure 32 (the is finished, ADCBUSY goes back low. This information is available acquisition phase), SW3 is closed and SW1 and SW2 are in Rev. D | Page 41 of 110

ADuC7124/ADuC7126 Data Sheet Position A. The comparator is held in a balanced condition, and Single-Ended Mode the sampling capacitor arrays acquire the differential signal on In single-ended mode, SW2 is always connected internally to the input. ground. The V pin can be floating. The input signal range on IN− V is 0 V to V . IN+ REF CAPACITIVE DAC AIN0 CHANNEL+ B CS COMPARATOR CAPDAACCITIVE MUX ASW1 SW3 CONTROL AIN0 CHANNEL+ B CS COMPARATOR CHANNEL– ASW2 CS LOGIC ASW1 AIN11 MUX SW3 CONTROL B CS LOGIC AIN11 CHANNEL– FiguVreR E3F2. ADC Acquisition Phase CAPDAACCITIVE 09123-017 CAPDAACCITIVE 09123-020 When the ADC starts a conversion, as shown in Figure 33, SW3 Figure 35. ADC in Single-Ended Mode opens, and then SW1 and SW2 move to Position B. This causes Analog Input Structure the comparator to become unbalanced. Both inputs are discon- Figure 36 shows the equivalent circuit of the analog input structure nected once the conversion begins. The control logic and the of the ADC. The four diodes provide ESD protection for the analog charge redistribution DACs are used to add and subtract fixed inputs. Care must be taken to ensure that the analog input amounts of charge from the sampling capacitor arrays to bring signals never exceed the supply rails by more than 300 mV; this the comparator back into a balanced condition. When the can cause these diodes to become forward-biased and start comparator is rebalanced, the conversion is complete. The conducting into the substrate. These diodes can conduct up to control logic generates the ADC output code. The output 10 mA without causing irreversible damage to the part. impedances of the sources driving the V and V pins must IN+ IN– be matched; otherwise, the two inputs have different settling The C1 capacitors in Figure 36 are typically 4 pF and can be times, resulting in errors. primarily attributed to pin capacitance. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 Ω. CAPACITIVE DAC The C2 capacitors are the sampling capacitors of the ADC and AIN0 CHANNEL+ B CS COMPARATOR typically have a capacitance of 16 pF. MUX ASW1 SW3 CONTROL AVDD CHANNEL– ASW2 CS LOGIC AIN11 D B R1 C2 VREF CAPDAACCITIVE 09123-018 C1 D Figure 33. ADC Conversion Phase AVDD Pseudo Differential Mode In pseudo differential mode, Channel− is linked to the D R1 C2 ADCNEG pin of the ADuC7124/ADuC7126. In Figure 34, C1 D ADCNEG is represented as V . SW2 switches between A t(oC hgraonunnedl− o) ra tnod a B l o(wV RvEoF)l.t aTghee. I TNA−hDe CinNpEuGt s piginna ml ounst V be c ocannn ethcteend 09123-021 IN+ Figure 36. Equivalent Analog Input Circuit Conversion Phase: Switches Open, vary from VIN− to VREF + VIN−. Note that VIN− must be chosen so Track Phase: Switches Closed that V + V do not exceed AV . REF IN− DD CAPACITIVE DAC AIN0 CHANNEL+ B CS COMPARATOR ASW1 MUX SW3 CONTROL SW2 CS LOGIC A AIN11 B VIN– CHANNEL– VREF CAPDAACCITIVE 09123-019 Figure 34. ADC in Pseudo Differential Mode Rev. D | Page 42 of 110

Data Sheet ADuC7124/ADuC7126 For ac applications, removing high frequency components from ADuC7124/ the analog input signal is recommended by using an RC low- ADuC7126 pass filter on the relevant analog input pins. In applications ADC0 where harmonic distortion and signal-to-noise ratio are critical, VREF tshoeu racnea. lLoagr ignep suotu srhcoeu imldp beed danricveesn s firgonmifi caa lnotwly i amffpeecdt atnhec ea c ADC1 09123-062 performance of the ADC. This can necessitate the use of an Figure 38. Buffering Differential Inputs input buffer amplifier. The choice of the op amp is a function of When no amplifier is used to drive the analog input, the source the particular application. Figure 37 and Figure 38 give an impedance should be limited to values lower than 1 kΩ. The example of the ADC front end. maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD ADuC7124/ increases as the source impedance increases and the performance ADuC7126 degrades. 10Ω ADC0 0.01µF 09123-061 DInRteIrVnaINl oGr eTxHterEn Aal NreAfeLreOnGce sI NcaPnU bTe Sus ed for the ADC. In Figure 37. Buffering Single-Ended/Pseudo Differential Input differential mode of operation, there are restrictions on the common-mode input signal (V ), which is dependent upon CM the reference value and supply voltage used to ensure that the signal remains within the supply rails. Table 33 gives some calculated V minimum and V maximum values. CM CM Table 33. V Ranges CM AV V V Minimum V Maximum Signal Peak-to-Peak DD REF CM CM 3.3 V 2.5 V 1.25 V 2.05 V 2.5 V 2.048 V 1.024 V 2.276 V 2.048 V 1.25 V 0.75 V 2.55 V 1.25 V 3.0 V 2.5 V 1.25 V 1.75 V 2.5 V 2.048 V 1.024 V 1.976 V 2.048 V 1.25 V 0.75 V 2.25 V 1.25 V Rev. D | Page 43 of 110

ADuC7124/ADuC7126 Data Sheet CALIBRATION K is the gain of the ADC in temperature sensor mode as determined by characterization data. K = 0.2555°C/mV By default, the factory-set values written to the ADC offset for ADuC7124. K = 0.2212°C/mV for ADuC7126. This (ADCOF) and gain coefficient registers (ADCGN) yield opti- corresponds to the 1/voltage temperature coefficient mum performance in terms of end-point errors and linearity specification from Table 1. for standalone operation of the part (see the Specifications section). If system calibration is required, it is possible to Using the default values from Table 1 and without any modify the default offset and gain coefficients to improve end- calibration, this equation becomes point errors, but note that any modification to the factory-set T − 25°C = (V − 1415) × 0.2555 for ADuC7124 ADC ADCOF and ADCGN values can degrade ADC linearity T − 25°C = (V −1392) × 0.2212 for ADuC7126 performance. ADC where V is in mV. For system offset error correction, the ADC channel input stage ADC must be tied to AGND. A continuous software ADC conversion For better accuracy, the user should perform a single point loop must be implemented by modifying the value in ADCOF calibration at a controlled temperature value. until the ADC result (ADCDAT) reads Code 0 to Code 1. If the For the calculation with no calibration, use 25°C and 1415 mV ADCDAT value is greater than 1, ADCOF should be decremented for the ADuC7124 and 1392mV for the ADuC7126. The idea until ADCDAT reads Code 0 to Code 1. Offset error correction of a single point calibration is to use other known (T , V ) REF TREF is done digitally and has a resolution of 0.25 LSB and a range of values to replace the common T = 25°C and 1415 mV for the ±3.125% of V . REF ADuC7124 and 1392 mV for the ADuC7126 for every part. For system gain error correction, the ADC channel input stage For some users, it is not possible to obtain such a known pair. must be tied to V . A continuous software ADC conversion REF For such cases, the ADuC7124/ADuC7126 comes with a single loop must be implemented to modify the value in ADCGN until point calibration value loaded in the TEMPREF register. For the ADC result (ADCDAT) reads Code 4094 to Code 4095. If the more details on this register, see Table 35. During production ADCDAT value is less than 4094, ADCGN should be incremented testing of the ADuC7124/ADuC7126, the TEMPREF register is until ADCDAT reads Code 4094 to Code 4095. Similar to the loaded with an offset adjustment factor. Each part has a offset calibration, the gain calibration resolution is 0.25 LSB different value in the TEMPREF register. Using this single point with a range of ±3% of V . REF calibration, the same formula is still used. TEMPERATURE SENSOR T – T = (V – V ) × K REF ADC TREF The ADuC7124/ADuC7126 provide voltage outputs from an where: on-chip band gap reference that is proportional to absolute T = 25°C but is not guaranteed. temperature. This voltage output can also be routed through the REF V can be calculated using the TEMPREF register. front-end ADC multiplexer (effectively, an additional ADC TREF channel input), facilitating an internal temperature sensor TSCON Register channel, measuring die temperature. Name: TSCON An ADC temperature sensor conversion differs from a standard Address: 0xFFFF0544 ADC voltage. The ADC performance specifications do not apply to the temperature sensor. Default Value: 0x00 Chopping of the internal amplifier must be enabled using the Access: Read/write TSCON register. To enable this mode, the user must set Bit 0 of TSCON. The user must also take two consecutive ADC readings Table 34. TSCON MMR Bit Descriptions and average them in this mode. Bit Description [7:1] Reserved. The ADCCON register must be configured to 0x37A3. 0 Temperature sensor chop enable bit. This bit must To calculate die temperature, use the following formula: be set. T – T = (V – V ) × K This bit is set to 1 to enable chopping of the internal REF ADC TREF amplifier to the ADC. where: This bit is cleared to disable chopping. This results in T is the temperature result. incorrect temperature sensor readings. TREF = 25°C. This bit is cleared by default. For the ADuC7124, V = 1.415 V and for the ADuC7126, TREF V = 1.392 V, which corresponds to T = 25°C, as described TREF REF in Table 1. V is the average ADC result from two consecutive ADC conversions. Rev. D | Page 44 of 110

Data Sheet ADuC7124/ADuC7126 TEMPREF Register response during ADC conversions. This reference can also be connected to an external pin (V ) and used as a reference REF Name: TEMPREF for other circuits in the system. An external buffer is required Address: 0xFFFF0548 because of the low drive capability of the VREF output (<5 µA). A programmable option also allows an external reference input Default Value: 0xXXXX on the V pin. Note that it is not possible to disable the REF internal reference. Therefore, the external reference source must Access: Read/write be capable of overdriving the internal reference source. REFCON Register Table 35. TEMPREF MMR Bit Descriptions Bit Description Name: REFCON [15:9] Reserved. Address: 0xFFFF048C 8 Temperature reference voltage sign bit. [7:0] Temperature sensor offset calibration voltage. Default Value: 0x00 To calculate the V from the TEMPREF register, TEMP perform the following calculation: Access: Read/write If TEMPREF sign is negative, C = 2292 − TEMPREF[7:0] The band gap reference interface consists of an 8-bit MMR TREF where TEMPREF[8] = 1 REFCON, described in Table 36. Or If TEMPREF sign is positive, Table 36. REFCON MMR Bit Descriptions C = TEMPREF[7:0] + 2292 Bit Description TREF where TEMPREF[8] = 0. [7:2] Reserved. Finally, 1 Internal reference power-down bit. VTREF = ((CTREF × VREF)/4096) × 1000 Set this bit to 1 to power down the internal reference Insert VTREF into source. This bit should be set when connecting an T − TREF = (VADC − VTREF) × K external reference source. Note that the ADC Code Value 2292 is a default value Clear this bit to enable the internal reference. when using the TEMPREF register. It is not an exact This bit is cleared by default. value and must only be used with the TEMPREF 0 Internal reference output enable. register. Set by the user to connect the internal 2.5 V reference to the VREF pin. The reference can be used for an external component but must be buffered. BAND GAP REFERENCE Cleared by the user to disconnect the reference from Each ADuC7124/ADuC7126 provides on-chip band gap the VREF pin. references of 2.5 V, which can be used for the ADC and DAC. To connect an external reference source to the ADuC7124/ This internal reference also appears on the VREF pin. When using ADuC7126, configure REFCON = 0x00. ADC and the DACs the internal reference, a 0.47 µF capacitor must be connected from can be configured to use same or a different reference resource the external VREF pin to AGND to ensure stability and fast (see Table 66). Rev. D | Page 45 of 110

ADuC7124/ADuC7126 Data Sheet NONVOLATILE FLASH/EE MEMORY The ADuC7124/ADuC7126 incorporate Flash/EE memory Retention quantifies the ability of the Flash/EE memory to technology on-chip to provide the user with nonvolatile, in- retain its programmed data over time. Again, the parts are circuit reprogrammable memory space. qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature Like EEPROM, flash memory can be programmed in-system (T = 85°C). As part of this qualification procedure, the Flash/EE at a byte level, although it must first be erased. The erase is J memory is cycled to its specified endurance limit (see the performed in page blocks. As a result, flash memory is often Flash/EE Memory section) before data retention is character- and more correctly referred to as Flash/EE memory. ized. This means that the Flash/EE memory is guaranteed to Overall, Flash/EE memory represents a step closer to the retain its data for its fully specified retention lifetime every time ideal memory device that includes nonvolatility, in-circuit the Flash/EE memory is reprogrammed. In addition, note that programmability, high density, and low cost. Incorporated in retention lifetime, based on the activation energy of 0.6 eV, the ADuC7124/ADuC7126, Flash/EE memory technology derates with T as shown in Figure 39. J allows the user to update program code space in-circuit, without the need to replace one-time programmable (OTP) devices at remote operating nodes. 600 Flash/EE Memory The ADuC7124/ADuC7126 contain two 64 kB arrays of Flash/EE ars)450 memory. In flash Block 0, the lower 62 kB is available to the Ye user, and the upper 2 kB of this Flash/EE program memory ON ( array contain permanently embedded firmware, allowing in-circuit NTI300 E T serial download. The 2 kB of embedded firmware also contain a E R power-on configuration routine that downloads factory cali- 150 brated coefficients to the various calibrated peripherals (band ghaidpd reenfe frreonmc euss earn cdo sdoe .o Int )is. Tnohti sp 2o sksBib elem fboer dthdee du sfierrm tow raeraed i,s write, 0 09123-085 30 40 55 70 85 100 125 135 150 or erase this page. In flash Block 1, all 64 kB of Flash/EE memory JUNCTION TEMPERATURE (°C) are available to the user. Figure 39. Flash/EE Memory Data Retention The 126 kB of Flash/EE memory can be programmed in-circuit, PROGRAMMING using the serial download mode or the JTAG mode provided. The 126 kB of Flash/EE memory can be programmed in-circuit, Flash/EE Memory Reliability using the serial download mode or the provided JTAG mode. The Flash/EE memory arrays on the parts are fully qualified for Serial Downloading (In-Circuit Programming) two key Flash/EE memory characteristics: Flash/EE memory The ADuC7124/ADuC7126 facilitate code download via the cycling endurance and Flash/EE memory data retention. standard UART serial port. It is only available on UART0 Endurance quantifies the ability of the Flash/EE memory to be (P1.0 and P1.1). The parts enter serial download mode after cycled through many program, read, and erase cycles. A single a reset or power cycle if the BM pin is pulled low through endurance cycle is composed of four independent, sequential an external 1 kΩ resistor. When in serial download mode, events, defined as the user can download code to the full 126 kB of Flash/EE 1. Initial page erase sequence. memory while the device is in-circuit in its target application 2. Read/verify sequence (single Flash/EE). hardware. An executable PC serial download is provided as 3. Byte program sequence memory. part of the development system for serial downloading via 4. Second read/verify sequence (endurance cycle). the UART. The AN-724 application note describes the UART download protocol. In reliability qualification, every half word (16-bit wide) Downloading (In-Circuit Programming) via I2C location of the three pages (top, middle, and bottom) in the Flash/EE memory is cycled 10,000 times from 0x0000 to The ADuC7126BSTZ126I and ADuC7126BSTZ126IRL models 0xFFFF. As indicated in Table 1, the Flash/EE memory facilitate code download via the the I2C port. The models enter endurance qualification is carried out in accordance with download mode after a reset or power cycle if the BM pin is JEDEC Retention Lifetime Specification A117 over the pulled low through an external 1 kΩ resistor and Flash Address industrial temperature range of −40° to +125°C. The results 0x80014 = 0xFFFFFFFF. Once in download mode, the user can allow the specification of a minimum endurance figure over a download code to the full 126 kB of Flash/EE memory while the supply temperature of 10,000 cycles. device is in-circuit in its target application hardware. An executable PC I2C download is provided as part of the development system Rev. D | Page 46 of 110

Data Sheet ADuC7124/ADuC7126 for serial downloading via the I2C. A USB-to-I2C download To remove or modify the protection, the same sequence is used dongle can be purchased from Analog Devices, Inc. This board with a modified value of FEExPRO. If the key chosen is the connects to the USB port of a PC and to the I2C port of the value 0xDEAD, the memory protection cannot be removed. Only a ADuC7126. The part number is USB-I2C/LIN-CONV-Z. mass erase unprotects the part, but it also erases all user code. The AN-806 Application Note describes the protocol for serial The sequence to write the key is illustrated in the following downloading via the I2C in more detail. example (this protects writing Page 4 to Page 7 of the Flash): JTAG Access FEExPRO=0xFFFFFFFD; //Protect Page 4 to 7 FEExMOD=0x48; //Write key enable The JTAG protocol uses the on-chip JTAG interface to facilitate FEExADR=0x1234; //16 bit key value code download and debug. FEExDAT=0x5678; //16 bit key value To access the part via the JTAG interface, the P0.0/BM pin must FEExCON= 0x0C; //Write key command be set high. The same sequence should be followed to protect the part permanently with FEExADR = 0xDEAD and FEExDAT = When debugging, user code should not write to the P0.1, P0.2, 0xDEAD. and P0.3 pins. If user code toggles any of these pins, JTAG debug pods are not able to connect to the ADuC7124/ADuC7126. FLASH/EE CONTROL INTERFACE If this happens, mass erase the part using the UART/I2C Table 37. FEE0STA Register downloader. Name Address Default Value Access FLASH/EE MEMORY SECURITY FEE0STA 0xFFFFF800 0x0000 R The 126 kB of Flash/EE memory available to the user can be Table 38. FEE0MOD Register read and write protected. Bit 31 of the FEE0PRO/FEE0HID Name Address Default Value Access MMR protects the 62 kB of Block 0 from being read through JTAG and in UART programming mode. The other 31 bits of this FEE0MOD 0xFFFFF804 0x80 R/W register protect writing to the Flash/EE memory; each bit protects Table 39. FEE0CON Register four pages, that is, 2 kB. Write protection is activated for all access Name Address Default Value Access types. FEE1PRO and FEE1HID, similarly, protect flash Block 1. FEE0CON 0xFFFFF808 0x00 R/W Bit 31 of the FEE1PRO/FEE1HID MMR protects the 64 kB of Block 1 from being read through JTAG. Bit 30 protects writing to Table 40. FEE0DAT Register the top 8 pages of Block 1. The other 30 bits of this register Name Address Default Value Access protect writing to the Flash/EE memory; each bit protects four FEE0DAT 0xFFFFF80C 0xXXXX R/W pages, that is, 2 kB FEE0DAT is a 16-bit data register. Three Levels of Protection • Protection can be set and removed by writing directly into Table 41. FEE0ADR Register FEExHID MMR. This protection does not remain after reset. Name Address Default Value Access • Protection can be set by writing into FEExPRO MMR. It FEE0ADR 0xFFFFF810 0x0000 R/W takes effect only after a save protection command (0x0C) FEE0ADR is a 16-bit address register. and a reset. The FEExPRO MMR is protected by a key to avoid direct access. The key is saved once and must be Table 42. FEE0SGN Register entered again to modify FEExPRO. A mass erase sets the Name Address Default Value Access key back to 0xFFFF but also erases all the user code. FEE0SGN 0xFFFFF818 0xFFFFFF R • Flash can be permanently protected by using the FEExPRO FEE0SGN is a 24-bit code signature. MMR and a particular key value of 0xDEADDEAD. Entering the key again to modify the FEExPRO register is Table 43. FEE0PRO Register not allowed. Name Address Default Value Access FEE0PRO 0xFFFFF81C 0x00000000 R/W Sequence to Write the Key FEE0PRO provides protection following subsequent reset MMR. 1. Write the bit in FEExPRO corresponding to the page to be It requires a software key (see Table 56). protected. 2. Enable key protection by setting Bit 6 of FEExMOD (Bit 5 Table 44. FEE0HID Register must equal 0). Name Address Default Value Access 3. Write a 32-bit key in FEExADR and FEExDAT. FEE0HID 0xFFFFF820 0xFFFFFFFF R/W 4. Run the write key command 0x0C in FEExCON; wait for the read to be successful by monitoring FEExSTA. FEE0HID provides immediate protection MMR. It does not 5. Reset the part. require any software keys (see Table 56). Rev. D | Page 47 of 110

ADuC7124/ADuC7126 Data Sheet Table 45. FEE1STA Register Table 49. FEE1ADR Register Name Address Default Value Access Name Address Default Value Access FEE1STA 0xFFFFF880 0x0000 R FEE1ADR 0xFFFFF890 0x0000 R/W Table 46. FEE1MOD Register FEE1ADR is a 16-bit address register. Name Address Default Value Access Table 50. FEE1SGN Register FEE1MOD 0xFFFFF884 0x80 R/W Name Address Default Value Access Table 47. FEE1CON Register FEE1SGN 0xFFFFF898 0xFFFFFF R Name Address Default Value Access FEE1SGN is a 24-bit code signature. FEE1CON 0xFFFFF888 0x00 R/W Table 51. FEE1PRO Register Table 48. FEE1DAT Register Name Address Default Value Access Name Address Default Value Access FEE1PRO 0xFFFFF89C 0x00000000 R/W FEE1DAT 0xFFFFF88C 0xXXXX R/W FEE1PRO provides protection following subsequent reset MMR. FEE1DAT is a 16-bit data register. It requires a software key (see Table 57). Table 52. FEE1HID Register Name Address Default Value Access FEE1HID 0xFFFFF8A0 0xFFFFFFFF R/W FEE1HID provides immediate protection MMR. It does not require any software keys (see Table 57). Command Sequence for Executing a Mass Erase FEE0DAT = 0x3CFF; FEE0ADR = 0xFFC3; FEE0MOD = FEE0MOD|0x8; //Erase key enable FEE0CON = 0x06; //Mass erase command Table 53. FEExSTA MMR Bit Descriptions Bit Description [15:6] Reserved. 5 Reserved. 4 Reserved. 3 Flash/EE interrupt status bit. Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the FEExMOD register is set. Cleared when reading the FEExSTA register. 2 Flash/EE controller busy. Set automatically when the controller is busy. Cleared automatically when the controller is not busy. 1 Command fail. Set automatically when a command completes unsuccessfully. Cleared automatically when reading the FEExSTA register. 0 Command complete. Set by MicroConverter when a command is complete. Cleared automatically when reading the FEExSTA register. Rev. D | Page 48 of 110

Data Sheet ADuC7124/ADuC7126 Table 54. FEExMOD MMR Bit Descriptions Bit Description [7:5] Reserved. 4 Flash/EE interrupt enable. Set by the user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete. Cleared by the user to disable the Flash/EE interrupt. 3 Erase/write command protection. Set by the user to enable the erase and write commands. Cleared to protect the Flash/EE memory against the erase/write command. 2 Reserved. Should always be set to 0 by the user. [1:0] Flash/EE wait states. Both Flash/EE blocks must have the same wait state value for any change to take effect. Table 55. Command Codes in FEExCON Code Command Description 0x001 Null Idle state. 0x011 Single read Load FEExDAT with the 16-bit data indexed by FEExADR. 0x021 Single write Write FEExDAT at the address pointed to by FEExADR. This operation takes 50 µs. 0x031 Erase/write Erase the page indexed by FEExADR and write FEExDAT at the location pointed to by FEExADR. This operation takes 20 ms. 0x041 Single verify Compare the contents of the location pointed to by FEExADR to the data in FEExDAT. The result of the comparison is returned in FEExSTA, Bit 1. 0x051 Single erase Erase the page indexed by FEExADR. 0x061 Mass erase Erase user space. The 2 kB of kernel are protected in Block 0. This operation takes 2.48 sec. To prevent accidental execution, a command sequence is required to execute this instruction. 0x07 Reserved Reserved. 0x08 Reserved Reserved. 0x09 Reserved Reserved. 0x0A Reserved Reserved. 0x0B Signature Gives a signature of the 64 kB of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32,778 clock cycles. 0x0C Protect This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase (0x06) or with the key. 0x0D Reserved Reserved. 0x0E Reserved Reserved. 0x0F Ping No operation, interrupt generated. 1 The FEExCON register always reads 0x07 immediately after execution of any of these commands. Rev. D | Page 49 of 110

ADuC7124/ADuC7126 Data Sheet is needed to decode the new address of the program counter, Table 56. FEE0PRO and FEE0HID MMR Bit Descriptions and then four cycles are needed to fill the pipeline. A data pro- Bit Description cessing instruction involving only the core register does not 31 Read protection. require any extra clock cycles. However, if it involves data in Cleared by the user to protect Block 0. Flash/EE, an extra clock cycle is needed to decode the address Set by the user to allow reading of Block 0. of the data, and two cycles are needed to get the 32-bit data from [30:0] Write protection for Page 123 to Page 0. Each bit Flash/EE. An extra cycle must also be added before fetching protects protects a group of 4 pages. another instruction. Data transfer instructions are more complex Cleared by the user to protect the pages when writing and are summarized in Table 58. to flash. Thus preventing an accidental write to specific pages in flash. Table 58. Execution Cycles in ARM/Thumb Mode Set by the user to allow writing to the pages. Fetch Dead Dead Table 57. FEE1PRO and FEE1HID MMR Bit Descriptions Instructions Cycles Time Data Access Time Bit Description LD1 2/1 1 2 1 31 Read protection. LDH 2/1 1 1 1 Cleared by the user to protect Block 1. LDM/PUSH 2/1 N2 2 × N2 N1 Set by the user to allow reading of Block 1. STR1 2/1 1 2 × 20 ns 1 30 Write protection for Page 127 to Page 120. STRH 2/1 1 20 ns 1 Cleared by the user to protect the pages when writing STRM/POP 2/1 N1 2 × N × 20 ns1 N1 to flash. Thus preventing an accidental write to specific 1 The SWAP instruction combines an LD and STR instruction with only one pages in flash. fetch, giving a total of eight cycles + 40 ns. 2 N is the number of data bytes to load or store in the multiple load/store Set by the user to allow writing to the pages. instruction (1 < N ≤ 16). [29:0] Write protection for Page 119 to Page 116 and for Page 0 RESET AND REMAP to Page 3. Cleared by the user to protect the pages in writing. The ARM exception vectors are all situated at the bottom of the Set by the user to allow writing to the pages. memory array, from Address 0x00000000 to Address 0x00000020, as shown in Figure 40. EXECUTION TIME FROM SRAM AND FLASH/EE 0xFFFFFFFF This section describes SRAM and Flash/EE access times during execution for applications where execution time is critical. Execution from SRAM Fetching instructions from SRAM takes one clock cycle because KERNEL 0x0009F800 the access time of the SRAM is 2 ns, and a clock cycle is 24 ns FLASH/EE minimum. However, if the instruction involves reading or INTERRUPT SERVICE ROUTINES 0x00080000 writing data to memory, one extra cycle must be added if the data is in SRAM (or three cycles if the data is in Flash/EE): one cycle to execute the instruction and two cycles to get the 32-bit 0x00047FFF data from Flash/EE. A control flow instruction (a branch INTERRUPT SRAM SERVICE ROUTINES 0x00040000 instruction, for example) takes one cycle to fetch but also takes two cycles to fill the pipeline with the new instructions. MIRROR SPACE EBxeceacuustei othne f Frolamsh F/ElaEs whi/dEtEh is 16 bits and access time for 16-bit AVERCMT EOXRC AEDPDTIROENSSES 00xx0000000000000200 0x00000000 09123-027 Figure 40. Remap for Exception Execution words is 22 ns, execution from Flash/EE cannot be done in one cycle (as can be done from SRAM when the CD bit = 0). By default, and after any reset, the Flash/EE is mirrored at the Also, some dead times are needed before accessing data for any bottom of the memory array. The remap function allows the value of the CD bits. programmer to mirror the SRAM at the bottom of the memory array, which facilitates execution of exception routines from In ARM mode, where instructions are 32 bits, two cycles are SRAM instead of from Flash/EE. This means exceptions are needed to fetch any instruction when CD = 0. In Thumb mode, executed twice as fast, being executed in 32-bit ARM mode with where instructions are 16 bits, one cycle is needed to fetch any 32-bit wide SRAM instead of 16-bit wide Flash/EE memory. instruction. Timing is identical in both modes when executing instructions that involve using the Flash/EE for data memory. If the instruc- tion to be executed is a control flow instruction, an extra cycle Rev. D | Page 50 of 110

Data Sheet ADuC7124/ADuC7126 Table 59. REMAP MMR Bit Descriptions Table 60. RSTSTA MMR Bit Descriptions (Address = 0xFFFF0220. Default Value = 0x00) Bit Description Bit Name Description [7:3] Reserved. 0 Remap Remap bit. 2 Software reset. Set by the user to remap the SRAM to Address Set by the user to force a software reset. 0x00000000. Cleared by setting the corresponding bit in RSTCLR. Cleared automatically after reset to remap the 1 Watchdog timeout. Flash/EE memory to Address 0x00000000. Set automatically when a watchdog timeout occurs. Remap Operation Cleared by setting the corresponding bit in RSTCLR. 0 Power-on reset. When a reset occurs on the ADuC7124/ADuC7126, execution Set automatically when a power-on reset occurs. automatically starts in factory programmed, internal Cleared by setting the corresponding bit in RSTCLR. configuration code. This kernel is hidden and cannot be accessed by user code. If the part is in normal mode (BM pin is high), it RSTCLR Register executes the power-on configuration routine of the kernel and Name: RSTCLR then jumps to the reset vector address, 0x00000000, to execute the reset exception routine of the user. Address: 0xFFFF0234 Because the Flash/EE is mirrored at the bottom of the memory Default Value: 0x00 array at reset, the reset interrupt routine must always be written in Flash/EE. Access: Write only The remap is done from Flash/EE by setting Bit 0 of the REMAP Note that to clear the RSTSTA register, users must write the register. Caution must be taken to execute this command from Value 0x07 to the RSTCLR register. Flash/EE, above Address 0x00080020, and not from the bottom of the array, because this is replaced by the SRAM. RSTCFG Register This operation is reversible. The Flash/EE can be remapped at Name: RSTCFG Address 0x00000000 by clearing Bit 0 of the REMAP MMR. Address: 0xFFFF024C Caution must again be taken to execute the remap function from outside the mirrored area. Any type of reset remaps the Default Value: 0x05 Flash/EE memory at the bottom of the array. Reset Operation Access: Read/write There are four kinds of reset: external, power-on, watchdog Table 61. RSTCFG MMR Bit Descriptions expiation, and software force. The RSTSTA register indicates Bit Description the source of the last reset, and RSTCLR allows clearing of the RSTSTA register. These registers can be used during a reset [7:3] Reserved. Always set to 0. exception service routine to identify the source of the reset. 2 This bit is set to 1 to configure the DAC outputs to retain their state after a watchdog or software reset. If RSTSTA is null, the reset is external. This bit is cleared for the DAC pins and registers to The RSTCFG register allows different peripherals to retain their return to their default state. state after a watchdog or software reset. 1 Reserved. Always set to 0. RSTSTA Register 0 This bit is set to 1 to configure the GPIO pins to retain their state after a watchdog or software reset. Name: RSTSTA This bit is cleared for the GPIO pins and registers to return to their default state. Address: 0xFFFF0230 The RSTCFG write sequence is as follows: Default Value: 0x01 1. Write Code 0x76 to Register RSTKEY1. Access: Read only 2. Write user value to Register RSTCFG. 3. Write Code 0xB1 to Register RSTKEY2. Rev. D | Page 51 of 110

ADuC7124/ADuC7126 Data Sheet RSTKEY0 Register RSTKEY1 Register Name: RSTKEY0 Name: RSTKEY1 Address: 0xFFFF0248 Address: 0xFFFF0250 Default Value: N/A Default Value: N/A Access Write only Access: Write only Rev. D | Page 52 of 110

Data Sheet ADuC7124/ADuC7126 OTHER ANALOG PERIPHERALS DAC Table 65. DAC0DAT MMR Bit Descriptions The ADuC7124/ADuC7126 incorporate two, or four, 12-bit Bit Description voltage output DACs on chip, depending on the model. Each [31:28] Reserved. DAC has a rail-to-rail voltage output buffer capable of driving [27:16] 12-bit data for DAC0. 5 kΩ/100 pF. [15:0] Reserved. Each DAC has three selectable ranges: 0 V to V (internal REF Using the DACs band gap 2.5 V reference), 0 V to DAC , and 0 V to AV . REF DD The on-chip DAC architecture consists of a DAC resistor string DAC is equivalent to an external reference for the DAC. REF followed by an output buffer amplifier. The functional equivalent The signal range is 0 V to AV . DD is shown in Figure 41. MMRs Interface Each DAC is independently configurable through a control AVDD register and a data register. These two registers are identical for VREF the four DACs. Only DAC0CON (see Table 63) and DAC0DAT DACREF R (see Table 65) are described in detail in this section. R Table 62. DACxCON Registers DAC0 Name Address Default Value Access R DAC0CON 0xFFFF0600 0x00 R/W DAC1CON 0xFFFF0608 0x00 R/W DAC2CON 0xFFFF0610 0x00 R/W R DAC3CON 0xFFFF0618 0x00 R/W R TBiatb le 6V3a. lDueA C0NCaOmNe MMRD eBsictr Dipetsiocrni ptions 09123-023 [7:6] Reserved. Figure 41. DAC Structure 5 DACCLK DAC update rate. As illustrated in Figure 41, the reference source for each DAC is Set by the user to update the DAC user selectable in software. It can be either AV , V , or DAC . using Timer1. DD REF REF In 0 V-to-AV mode, the DAC output transfer function spans Cleared by the user to update the DD from 0 V to the voltage at the AV pin. In 0 V-to-DAC mode, DAC using HCLK (core clock). DD REF the DAC output transfer function spans from 0 V to the voltage at 4 DACCLR DAC clear bit. Set by the user to enable normal the DACREF pin. In 0 V-to-VREF mode, the DAC output transfer DAC operation. function spans from 0 V to the internal 2.5 V reference, VREF. Cleared by the user to reset the data The DAC output buffer amplifier features a true, rail-to-rail register of the DAC to 0. output stage implementation. This means that, when unloaded, 3 Reserved. This bit should be left at 0. each output is capable of swinging to within less than 5 mV of 2 Reserved. This bit should be left at 0. both AV and ground. Moreover, the DAC linearity specification DD [1:0] DAC range bits. (when driving a 5 kΩ resistive load to ground) is guaranteed 00 Power-down mode. The DAC output through the full transfer function except the 0 to 100 codes, is in tristate. and, in 0 V-to-AV mode only, Code 3995 to Code 4095. 01 0 V to DAC range. DD REF 10 0 V to VREF (2.5 V) range. Linearity degradation near ground and VDD is caused by satu- 11 0 V to AV range. ration of the output amplifier, and a general representation of its DD effects (neglecting offset and gain error) is illustrated in Figure 42. Table 64. DACxDAT Registers The dotted line in Figure 42 indicates the ideal transfer function, Name Address Default Value Access and the solid line represents what the transfer function may DAC0DAT 0xFFFF0604 0x00000000 R/W look like with endpoint nonlinearities due to saturation of the DAC1DAT 0xFFFF060C 0x00000000 R/W output amplifier. Note that Figure 42 represents a transfer function DAC2DAT 0xFFFF0614 0x00000000 R/W in 0 V-to-AV mode only. In 0 V-to-V or 0 V-to-DAC DD REF REF DAC3DAT 0xFFFF061C 0x00000000 R/W mode (with V < AV or DAC < AV ), the lower nonlinear- REF DD REF DD ity is similar. However, the upper portion of the transfer function follows the ideal line right to the end (V in this case, not AV ), REF DD showing no signs of endpoint linearity errors. Rev. D | Page 53 of 110

ADuC7124/ADuC7126 Data Sheet Configuring DAC Buffers in Op Amp Mode AVDD AVDD– 100mV In op amp mode, the DAC output buffers are used as an op amp with the DAC itself disabled. If DACBCFG Bit 0 is set, ADC0 is the positive input to the op amp, ADC1 is the negative input, and DAC0 is the output. In this mode, the DAC should be powered down by clearing Bit 0 and Bit 1 of DAC0CON. If DACBCFG Bit 1 is set, ADC2 is the positive input to the op amp, ADC3 is the negative input, and DAC1 is the output. In 100mV 0x00000000 0x0FFF0000 09123-024 tahnids mBiot d1e o, ft hDeA DCA1CC OshNo.u ld be powered down by clearing Bit 0 Figure 42. Endpoint Nonlinearities Due to Amplifier Saturation If DACBCFG Bit 2 is set, ADC4 is the positive input to the op The endpoint nonlinearities conceptually illustrated in Figure 42 amp, ADC5 is the negative input, and DAC2 is the output. In becomes worse as a function of output loading. Most of the this mode, the DAC should be powered down by clearing Bit 0 ADuC7124/ADuC7126 data sheet specifications assume a 5 kΩ and Bit 1 of DAC2CON. resistive load to ground at the DAC output. As the output is If DACBCFG Bit 3 is set, ADC8 is the positive input to the op forced to source or sink more current, the nonlinear regions at amp, ADC9 is the negative input, and DAC3 is the output. In the top or bottom (respectively) of Figure 42 become larger. this mode, the DAC should be powered down by clearing Bit 0 With larger current demands, this can significantly limit output and Bit 1 of DAC3CON. voltage swing. DACBCFG Register References to ADC and the DACs Name: DACBCFG The ADC and DACs can be configured to use the internal V REF or an external reference as a reference source. The internal VREF Address: 0xFFFF0654 must work with an external 0.47 µF capacitor. Default Value: 0x00 Table 66. Reference Source Selection for the ADC and DACs Access: Read/write REFCON[0] DACxCON[1:0] Description 0 00 ADC works with an external reference. DACs are powered Table 67. DACBCFG MMR Bit Descriptions down. Bit Description 0 01 ADC works with an external [7:4] Reserved. Always set to 0. reference. DAC works with 3 Set this bit to 1 to configure the DAC3 output DACREF. buffer in op amp mode. 0 10 Reserved. Clear this bit for the DAC buffer to operate as 0 11 ADC works with an external normal. reference. DACs work with 2 Set this bit to 1 to configure the DAC2 output internal AVDD. buffer in op amp mode. 1 00 ADC works with an internal VREF. Clear this bit for the DAC buffer to operate as DACs are powered down. normal. 1 01 ADC works with an external 1 Set this bit to 1 to configure the DAC1 output reference. DACs work with buffer in op amp mode. DACREF. Clear this bit for the DAC buffer to operate as 1 10 ADC and DACs work with an normal. internal VREF. 0 Set this bit to 1 to configure the DAC0 output 1 11 ADC works with an internal VREF. buffer in op amp mode. DACs work with an internal Clear this bit for the DAC buffer to operate as AVDD. normal. Note that if REFCON[1] = 1, the internal V powers down REF The DACBCFG write sequence is as follows: and the ADC cannot use the internal V . REF 1. Write Code 0x9A to Register DACBKEY1. 2. Write user value to Register DACBCFG. 3. Write Code 0x0C to Register DACBKEY2. Rev. D | Page 54 of 110

Data Sheet ADuC7124/ADuC7126 DACBKEY1 Register Table 68. PSMCON MMR Bit Descriptions Name: DACBKEY1 Bit Name Description Address: 0xFFFF0650 3 CMP Comparator bit. This is a read-only bit that directly reflects the state of the comparator. Default Value: 0x0000 Read 1 indicates that the IOVDD supply is above its selected trip point or that the PSM is in Access: Write power-down mode. Read 0 indicates that the IOV supply is below its selected trip point. This DD bit should be set before leaving the interrupt DACBKEY2 Register service routine. Name: DACBKEY2 2 TP Trip point selection bits. 0 = 2.79 V, 1 = 3.07 V. Address: 0xFFFF0658 1 PSMEN Power supply monitor enable bit. Set to 1 to enable the power supply monitor Default Value: 0x0000 circuit. Clear to 0 to disable the power supply monitor Access: Write circuit. POWER SUPPLY MONITOR 0 PSMI Power supply monitor interrupt bit. This bit is set high by the MicroConverter when CMP goes low, The power supply monitor regulates the IOVDD supply on the indicating low I/O supply. The PSMI bit can be ADuC7124/ADuC7126. It indicates when the IOV supply pin used to interrupt the processor. When CMP DD drops below one of two supply trip points. The monitor returns high, the PSMI bit can be cleared by writing a 1 to this location. A 0 write has no function is controlled via the PSMCON register. If enabled in effect. There is no timeout delay; PSMI can be the IRQEN or FIQEN register, the monitor interrupts the core immediately cleared when CMP goes high. using the PSMI bit in the PSMCON MMR. This bit is immediately cleared when CMP goes high. COMPARATOR This monitor function allows the user to save working registers The ADuC7124/ADuC7126 integrate a voltage comparator. The to avoid possible data loss due to low supply or brown-out positive input is multiplexed with ADC2, and the negative input conditions. It also ensures that normal code execution does not has two options: ADC3 or DAC0. The output of the comparator resume until a safe supply level is established. can be configured to generate a system interrupt, be routed PSMCON Register directly to the programmable logic array, start an ADC conver- sion, or be on an external pin, CMP , as shown in Figure 43. Name: PSMCON OUT Address: 0xFFFF0440 ADC2/CMP0 IRQ Default Value: 0x0008 MUX ADC3/CMP1 Access: Read/write MUX DAC0 P0.0/CMPOUT 09123-225 Figure 43. Comparator Hysteresis Figure 44 shows how the input offset voltage and hysteresis terms are defined. Input offset voltage (V ) is the difference OS between the center of the hysteresis range and the ground level. This can either be positive or negative. The hysteresis voltage (V ) is ½ the width of the hysteresis range. H CMPOUT VH VH VOS COMP0 09123-063 Figure 44. Comparator Hysteresis Transfer Function Rev. D | Page 55 of 110

ADuC7124/ADuC7126 Data Sheet Comparator Interface Bit Value Name Description The comparator interface consists of a 16-bit MMR, CMPCON, 1 CMPORI Comparator output rising edge interrupt. which is described in Table 69. Set automatically when a rising CMPCON Register edge occurs on the monitored voltage (CMP0). Name: CMPCON Cleared by user by writing a 1 to this bit. Address: 0xFFFF0444 0 CMPOFI Comparator output falling edge Default Value: 0x0000 interrupt. Set automatically when a falling Access: Read/write edge occurs on the monitored voltage (CMP0). Table 69. CMPCON MMR Bit Descriptions Cleared by user by writing a 1 to this bit. Bit Value Name Description [15:11] Reserved. OSCILLATOR AND PLL—POWER CONTROL 10 CMPEN Comparator enable bit. Clocking System Set by the user to enable the The ADuC7124/ADuC7126 integrate a 32.768 kHz ± 3% oscilla- comparator. Cleared by the user to disable the tor, a clock divider, and a PLL. The PLL locks onto a multiple comparator. (1275) of the internal oscillator or an external 32.768 kHz crystal to [9:8] CMPIN Comparator negative input select provide a stable 41.78 MHz clock (UCLK) for the system. To allow bits. power saving, the core can operate at this frequency or at binary 00 AV /2. submultiples of it. The actual core operating frequency, UCLK/2CD, DD 01 ADC3 input. is referred to as HCLK. The default core clock is the PLL clock 10 DAC0 output. divided by 8 (CD = 3) or 5.22 MHz. The core clock frequency 11 Reserved. can also come from an external clock on the ECLK pin as [7:6] CMPOC Comparator output configuration shown in Figure 45. The core clock can be output on ECLK bits. when using an internal oscillator or external crystal. 00 Reserved. Note that, when the ECLK pin is used to output the core clock, 01 Reserved. the output signal is not buffered and is not suitable for use as a 10 Output on CMPOUT. clock source to an external device without an external buffer. 11 IRQ. 5 CMPOL Comparator output logic state bit. When low, the comparator output WATCHDOG INT. 32kHz* CRYSTAL XCLKO TIMER OSCILLATOR OSCILLATOR XCLKI is high if the positive input (CMP0) is above the negative OCLK WAKEUP input (CMP1). When high, the TIMER comparator output is high if the AT POWER UP positive input is below the 32.768kHz negative input. 41.78MHz [4:3] CMPRES Response time. PLL XCLK 00 5 µs response time typical for MDCLK l1a7r gµes sreigsnpaolns s(2e. 5ti mV ed itfyfepriecnalt ifaolr). I2C UCLK PERAINPAHLEORGALS small signals (0.65 mV differential). CD /2CD 11 4 µs typical. CORE HCLK 2 0 1/10 CMPHYST RCeosmerpvaerdat. or hysteresis sit. *32.768kHz ±3% ECLK 09123-126 Set by user to have a hysteresis of Figure 45. Clocking System about 7.5 mV. The selection of the clock source is in the PLLCON register. By Cleared by user to have no default, the part uses the internal oscillator feeding the PLL. hysteresis. Rev. D | Page 56 of 110

Data Sheet ADuC7124/ADuC7126 External Crystal Selection External Clock Selection To switch to an external crystal, the user must follow this To switch to an external clock on P0.7, configure P0.7 in procedure: Mode 1. The external clock can be up to 41.78 MHz, providing the tolerance is 1%. 1. Enable the Timer2 interrupt and configure it for a timeout period of >120 µs. Example source code: 2. Follow the write sequence to the PLLCON register, setting T2LD = 5; the MDCLK bits to 01 and clearing the OSEL bit. T2CON = 0x480; 3. Force the part into nap mode by following the correct write sequence to the POWCON0 register. IRQEN = 0x10; 4. When the part is interrupted from nap mode by the //enable T2 interrupt Timer2 interrupt source, the clock source has switched to PLLKEY1 = 0xAA; the external clock. PLLCON = 0x03; //Select external clock Example source code: PLLKEY2 = 0x55; T2LD = 5; POWKEY1 = 0x01; POWCON0 = 0x27; // T2CON = 0x480; Set core into nap mode IRQEN = 0x10; POWKEY2 = 0xF4; //enable T2 interrupt Power Control System PLLKEY1 = 0xAA; A choice of operating modes is available on the ADuC7124/ PLLCON = 0x01; PLLKEY2 = 0x55; ADuC7126. Table 70 describes what part is powered on in the different modes and indicates the power-up time. POWKEY1 = 0x01; Table 71 gives some typical values of the total current POWCON0 = 0x27; // Set core into nap mode POWKEY2 = 0xF4; consumption (analog + digital supply currents) in the different In noisy environments, noise can couple to the external crystal modes, depending on the clock divider bits. The AC, DAC, I2C, pins, and PLL may lose lock momentarily. A PLL interrupt is and SPI are turned off. provided in the interrupt controller. The core clock is immediately halted, and this interrupt is serviced only when the lock is restored. In case of crystal loss, the watchdog timer should be used. During initialization, a test on the RSTSTA can determine if the reset came from the watchdog timer. Table 70. Operating Modes Mode Core Peripherals PLL XTAL/T2/T3 IRQ0 to IRQ3 Start-Up/Power-On Time Active On On On On On 66 ms at CD = 0 Pause On On On On 2.6 µs at CD = 0; 247 µs at CD = 7 Nap On On On 2.6 µs at CD = 0; 247 µs at CD = 7 Sleep On On 1.58 ms Stop On 1.7 ms Table 71. Typical Current Consumption at 25°C in mA, V = 3.3 V DD Mode CD = 0 CD = 1 CD = 2 CD = 3 CD = 4 CD = 5 CD = 6 CD = 7 Active 33.3 23.1 15.4 11.6 9.7 8.8 8.3 8.1 Pause 20.6 12.7 8.8 6.8 5.8 5.3 5.1 4.9 Nap 4.6 4.6 4.6 4.6 4.6 4.6 4.6 4.6 Sleep 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 Stop 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 Rev. D | Page 57 of 110

ADuC7124/ADuC7126 Data Sheet MMRs and Keys POWCON0 Register The operating mode, clocking mode, and programmable clock Name: POWCON0 divider are controlled via three MMRs, PLLCON (see Table 73), Address: 0xFFFF0408 and POWCONx. PLLCON controls the operating mode of the clock system, POWCON0 controls the core clock frequency and Default Value: 0x0003 the power-down mode, and POWCON1 controls the clock frequency to I2C and SPI. Access: Read/write Table 72. PLLKEYx Registers Table 75. POWCON0 MMR Bit Descriptions Name Address Default Value Access Bit Value Name Description PLLKEY1 0xFFFF0410 0x0000 W 7 Reserved. PLLKEY2 0xFFFF0418 0x0000 W [6:4] PC Operating modes. 000 Active mode. PLLCON Register 001 Pause mode. Name: PLLCON 010 Nap mode. Address: 0xFFFF0414 011 Sleep mode. IRQ0 to IRQ3 and Timer2 can wake up the part. Default Value: 0x21 100 Stop mode. IRQ0 to IRQ3 can wake up the part. Access: Read/write Others Reserved. 3 Reserved. Table 73. PLLCON MMR Bit Descriptions [2:0] CD CPU clock divider bits. Bit Value Name Description 000 41.78 MHz. [7:6] Reserved. 001 20.89 MHz. 5 OSEL 32 kHz PLL input selection. 010 10.44 MHz. Set by the user to select the internal 011 5.22 MHz. 32 kHz oscillator. Set by default. Cleared by the user to select the 100 2.61 MHz. external 32 kHz crystal. 101 1.31 MHz. [4:2] Reserved. 110 653 kHz. [1:0] MDCLK Clocking modes. 111 326 kHz. 00 Reserved. To prevent accidental programming, a certain sequence must be 01 PLL. Default configuration. followed to write to the POWCONx register. The POWCON0 10 Reserved. write sequence is as follows: 11 External clock on the P0.7 Pin. 1. Write Code 0x01 to Register POWKEY1. To prevent accidental programming, a certain sequence must be 2. Write a user value to Register POWCON0. followed to write to the PLLCON register.The PLLCON write 3. Write Code 0xF4 to Register POWKEY2. sequence is as follows: Table 76. POWKEYx Registers 1. Write Code 0xAA to Register PLLKEY1. Name Address Default Value Access 2. Write user value to Register PLLCON. POWKEY3 0xFFFF0434 0x0000 W 3. Write Code 0x55 to Register PLLKEY2. POWKEY4 0xFFFF043C 0x0000 W Table 74. POWKEYx Registers POWKEY3 and POWKEY4 are used to prevent accidental Name Address Default Value Access programming to POWCON1. POWKEY1 0xFFFF0404 0x0000 W POWCON1 Register POWKEY2 0xFFFF040C 0x0000 W Name: POWCON1 POWKEY1 and POWKEY2 are used to prevent accidental programming to POWCON0. Address: 0xFFFF0438 Default Value: 0x124 Access: Read/write Rev. D | Page 58 of 110

Data Sheet ADuC7124/ADuC7126 Table 77. POWCON1 MMR Bit Descriptions1 The POWCON1 write sequence is as follows: Bit Value Name Description 1. Write Code 0x76 to Register POWKEY3. [15:12] Reserved. 2. Write user value to Register POWCON1. 11 1 PWMPO Clearing this bit powers 3. Write Code 0xB1 to Register POWKEY4. down the PWM. Always clear to 00. [10:9] 00 PWMCLKDIV 8 SPIPO Clearing this bit powers down the SPI. [7:6] SPICLKDIV SPI block driving clock divider bits. 00 41.78 MHz. 01 20.89 MHz. 10 10.44 MHz. 11 5.22 MHz. 5 I2C1PO Clearing this bit powers down I2C1. [4:3] I2C1CLKDIV I2C0 block driving clock divider bits. 00 41.78 MHz. 01 10.44 MHz. 10 5.22 MHz. 11 1.31 MHz. 2 I2C0PO Clearing this bit powers down I2C0. [1:0] I2C0CLKDIV I2C1 block driving clock divider bits. 00 41.78 MHz. 01 10.44 MHz. 10 5.22 MHz. 11 1.31 MHz. 1 Divided clock for SPI/I2C0/I2C1 must be greater than or equal to the CPU clock as selected by POWCON0 [2:0]. Rev. D | Page 59 of 110

ADuC7124/ADuC7126 Data Sheet DIGITAL PERIPHERAL GENERAL-PURPOSE INPUT/OUTPUT Table 78. GPIO Pin Function Descriptions The ADuC7124/ADuC7126 provide 40 general-purpose, Configuration bidirectional I/O (GPIO) pins. All I/O pins are 5 V tolerant, Port Pin 00 01 10 11 meaning the GPIOs support an input voltage of 5 V. 0 BM/P0.0 GPIO CMP MS0 PLAI[7] TDI/P0.11 GPIO/JTAG PWM4 BLE4 In general, many of the GPIO pins have multiple functions (see TDO/P0.21 GPIO/JTAG PWM5 BHE4 the Pin Configurations and Function Descriptions section for TRST/P0.31 GPIO/JTAG TRST A164 ADCBUSY pin function definitions). By default, the GPIO pins are configured P0.4 GPIO/IRQ0 PWMTRIP MS14 PLAO[1] in GPIO mode. P0.5 GPIO/IRQ1 ADCBUSY MS24 PLAO[2] All GPIO pins have an internal pull-up resistor (of about 100 kΩ), P0.6 GPIO MRST MS34 PLAO[3] P0.7 GPIO ECLK/XCLK2 SIN0 PLAO[4] and their drive capability is 1.6 mA. Note that a maximum of 1 P1.0 GPIO/T1 SIN0 SCL03 PLAI[0] 20 GPIOs can drive 1.6 mA at the same time. Using the GPxPAR P1.1 GPIO SOUT0 SDA03 PLAI[1] registers, it is possible to enable/disable the pull-up resistors for P1.2 GPIO RTS3 SCL13 PLAI[2] the following ports: P0.0, P0.4, P0.5, P0.6, P0.7, and the eight P1.3 GPIO CTS3 SDA13 PLAI[3] GPIOs of P1. P1.4 GPIO/IRQ2 RI3 SCLK3 PLAI[4] The 40 GPIOs are grouped in five ports, Port 0 to Port 4 (Port x). P1.5 GPIO/IRQ3 DCD3 MISO3 PLAI[5] Each port is controlled by four or five MMRs. P1.6 GPIO DSR3 MOSI3 PLAI[6] P1.7 GPIO DTR3 CS3 PLAO[0] Note that the kernel changes P0.6 from its default configuration at reset (MRST) to GPIO mode. If MRST is used for external 2 P2.0 GPIO CONVSTART SOUT0 PLAO[5] P2.1 GPIO PWM0 WS4 PLAO[6] circuitry, an external pull-up resistor should be used to ensure P2.2 GPIO PWM1 RS4 PLAO[7] that the level on P0.6 does not drop when the kernel switches P2.3 GPIO AE4 SIN1 mode. Otherwise, P0.6 goes low for the reset period. For example, P2.4 GPIO PWM0 MS04 SOUT1 if MRST is required for power-down, it can be reconfigured in P2.5 GPIO PWM1 MS14 GP0CON MMR. P2.6 GPIO PWM2 MS24 The input level of any GPIO can be read at any time in the P2.7 GPIO PWM3 MS34 3 P3.0 GPIO PWM0 AD04 PLAI[8] GPxDAT MMR, even when the pin is configured in a mode P3.1 GPIO PWM1 AD14 PLAI[9] other than GPIO. The PLA input is always active. P3.2 GPIO PWM2 AD24 PLAI[10] When the ADuC7124/ADuC7126 enter a power-saving mode, P3.3 GPIO PWM3 AD34 PLAI[11] the GPIO pins retain their state. Also, note that, by setting P3.4 GPIO PWM4 AD44 PLAI[12] RSTCFG Bit 0, the GPIO pins can retain their state during a P3.5 GPIO PWM5 AD54 PLAI[13] watchdog or software reset. P3.6 GPIO PWMTRIP AD64 PLAI[14] P3.7 GPIO PWMSYNC AD74 PLAI[15] 4 P4.0 GPIO SIN1 AD84 PLAO[8] P4.1 GPIO SOUT1 AD94 PLAO[9] P4.2 GPIO AD104 PLAO[10] P4.3 GPIO AD114 PLAO[11] P4.4 GPIO AD124 PLAO[12] P4.5 GPIO/RTCK5 AD134 PLAO[13] P4.6 GPIO AD144 PLAO[14] P4.7 GPIO AD154 PLAO[15] 1 These pins should not be used by user code . 2 When configured in Mode 1, P0.7 is ECLK by default, or core clock output. To configure it as a clock input, the MDCLK bits in PLLCON must be set to 11. 3 See Table 90 for SPM configurations. 4 External Memory Interface signals are only available on ADuC7126. 5 In debug mode, the RTCK mode cannot be disabled. Rev. D | Page 60 of 110

Data Sheet ADuC7124/ADuC7126 Table 79. GPxCON Registers Bit Description Name Address Default Value Access 16 Pull-up disable Px.4. GP0CON 0xFFFFF400 0x00000000 R/W 15 Reserved. GP1CON 0xFFFFF404 0x00000000 R/W [14:13] Drive strength Px.3. GP2CON 0xFFFFF408 0x00000000 R/W 12 Pull-up disable Px.3. GP3CON 0xFFFFF40C 0x00000000 R/W 11 Reserved. GP4CON 0xFFFFF410 0x00000000 R/W [10:9] Drive strength Px.2. GPxCON are the Port x control registers that select the function 8 Pull-up disable Px.2. of each pin of Port x, as described in Table 80. 7 Reserved. [6:5] Drive strength Px.1. Table 80. GPxCON MMR Bit Descriptions 4 Pull-up disable Px.1. Bit Description 3 Reserved. [31:30] Reserved. [2:1] Drive strength Px.0. [29:28] Select function of Px.7 pin. 0 Pull-up disable Px.0. [27:26] Reserved. [25:24] Select function of Px.6 pin. Table 83. GPIO Drive Strength Control Bits Descriptions [23:22] Reserved. Control Bits Value Description [21:20] Select function of Px.5 pin. 00 Medium drive strength. [19:18] Reserved. 01 Low drive strength. [17:16] Select function of Px.4 pin. 1x High drive strength. [15:14] Reserved. [13:12] Select function of Px.3 pin. 3.6 [11:10] Reserved. [9:8] Select function of Px.2 pin. 3.4 HIGH DRIVE STRENGTH MEDIUM DRIVE STRENGTH [7:6] Reserved. 3.2 LOW DRIVE STRENGTH [[53::42]] SReelseecrtv feudn. ction of Px.1 pin. AGE (V) 3.0 T L [1:0] Select function of Px.0 pin. O 2.8 V Y L Table 81. GPxPAR Registers PP 2.6 U S Name Address Default Value Access 2.4 GP0PAR 0xFFFFF42C 0x20000000 R/W GGPP12PPAARR 00xxFFFFFFFFFF4443CC 00xx000000000000F0F0 RR//WW 22..02 09123-148 GP3PAR 0xFFFFF45C 0x00222222 R/W –24 –18 –12 –6 0 6 12 18 24 SINK/SOURCE CURRENT (mA) GP4PAR 0xFFFFF46C 0x00000000 R/W Figure 46. Programmable Strength for High Level The GPxPAR registers program the parameters for Port 0, Port 1, 0.5 Port 2, Port 3, and Port 4. Note that the GPxDAT MMR must 0.4 HIGH DRIVE STRENGTH always be written after changing the GPxPAR MMR. MEDIUM DRIVE STRENGTH 0.3 LOW DRIVE STRENGTH Table 82. GPxPAR MMR Bit Descriptions V) Bit Description GE ( 0.2 A T 0.1 31 Reserved. L O V [30:29] Drive strength Px.7. Y 0 L P 28 Pull-up disable Px.7. UP–0.1 S 27 Reserved. –0.2 [26:25] Drive strength Px.6. 2243 PRueslle-urvpe ddi.s able Px.6. ––00..43 09123-149 –24 –18 –12 –6 0 6 12 18 24 [22:21] Drive strength Px.5. SINK/SOURCE CURRENT (mA) 20 Pull-up disable Px.5. Figure 47. Programmable Strength for Low Level 19 Reserved. [18:17] Drive strength Px.4. Rev. D | Page 61 of 110

ADuC7124/ADuC7126 Data Sheet The drive strength bits can be written only once after reset. Table 89. GPxCLR MMR Bit Descriptions Additional writing to related bits has no effect on drive strength. Bit Description The GPIO drive strength and pull-up disable are not always [31:24] Reserved. adjustable for GPIO port. Some control bits cannot be changed. [23:16] Data Port x clear bit. See Table 78 for details. Set to 1 by the user to clear a bit on Port x; also clears the corresponding bit in the GPxDAT MMR. Table 84. GPxDAT Registers Cleared to 0 by the user; does not affect the data out. Name Address Default Value Access [15:0] Reserved. GP0DAT 0xFFFFF420 0x000000XX R/W SERIAL PORT MUX GP1DAT 0xFFFFF430 0x000000XX R/W GP2DAT 0xFFFFF440 0x000000XX R/W The serial port mux multiplexes the serial port peripherals GP3DAT 0xFFFFF450 0x000000XX R/W (an SPI, UART, and two I2Cs) and the programmable logic array GP4DAT 0xFFFFF460 0x000000XX R/W (PLA) to a set of 10 GPIO pins. Each pin must be configured to one of its specific I/O functions as described in Table 90. The GPxDAT are Port x configuration and data registers. They configure the direction of the GPIO pins of Port x, set the Table 90. SPM Configuration output value for the pins configured as output, and store the GPIO UART UART/I2C/SPI PLA input value of the pins configured as input. SPM (00) (01) (10) (11) SPM0 P1.0 SIN0 I2C0SCL PLAI[0] Table 85. GPxDAT MMR Bit Descriptions SPM1 P1.1 SOUT0 I2C0SDA PLAI[1] Bit Description SPM2 P1.2 RTS I2C1SCL PLAI[2] [31:24] Direction of the data. SPM3 P1.3 CTS I2C1SDA PLAI[3] Set to 1 by the user to configure the GPIO pin as an output. SPM4 P1.4 RI SCLK PLAI[4] Cleared to 0 by the user to configure the GPIO pin SPM5 P1.5 DCD MISO PLAI[5] as an input. SPM6 P1.6 DSR MOSI PLAI[6] [23:16] Port x data output. SPM7 P1.7 DTR CS PLAO[0] [15:8] Reflect the state of Port x pins at reset (read only). SPM8 P0.7 ECLK/XCLK SIN0 PLAO[4] [7:0] Port x data input (read only). SPM9 P2.0 CONV SOUT0 PLAO[5] START SPM10 P4.0 SIN1 AD8 PLAO[8] Table 86. GPxSET Registers SPM11 P4.1 SOUT1 AD9 PLAO[9] Name Address Default Value Access SPM12 P2.3 N/A AE SIN1 GP0SET 0xFFFFF424 0x000000XX W SPM13 P2.4 PWM0 MSO SOUT1 GP1SET 0xFFFFF434 0x000000XX W Table 90 also details the mode for each of the SPMMUX pins. GP2SET 0xFFFFF444 0x000000XX W This configuration has to be done via the GP0CON, GP1CON, GP3SET 0xFFFFF454 0x000000XX W and GP2CON MMRs. By default, these 10 pins are configured GP4SET 0xFFFFF464 0x000000XX W as GPIOs. The GPxSET are data set Port x registers. UART SERIAL INTERFACE Table 87. GPxSET MMR Bit Descriptions The UART peripheral is a full-duplex, universal, asynchronous Bit Description receiver/transmitter. The UART performs serial-to-parallel conver- [31:24] Reserved. sions on data characters received from a peripheral device and [23:16] Data Port x set bit. parallel-to-serial conversions on data characters received from Set to 1 by the user to set a bit on Port x; also sets the the CPU. The ADuC7124/ADuC7126 has been equipped with corresponding bit in the GPxDAT MMR. two industry standard 16,450 type UARTs (UART0 and UART1). Cleared to 0 by the user; does not affect the data output. Each UART features a fractional divider that facilitates high accu- [15:0] Reserved. racy baud rate generation and is equipped with a 16-byte FIFO for the transmitter and a 16-byte FIFO for the receiver. Both Table 88. GPxCLR Registers UARTs can be configured as FIFO mode and non-FIFO mode. Name Address Default Value Access The serial communication adopts an asynchronous protocol, GP0CLR 0xFFFFF428 0x000000XX W which supports various word lengths, stop bits, and parity GP1CLR 0xFFFFF438 0x000000XX W generation options selectable in the configuration register. GP2CLR 0xFFFFF448 0x000000XX W GP3CLR 0xFFFFF458 0x000000XX W GP4CLR 0xFFFFF468 0x000000XX W The GPxCLR are data clear Port x registers. Rev. D | Page 62 of 110

Data Sheet ADuC7124/ADuC7126 Baud Rate Generation Error is 0%, compared to 6.25% with the normal baud rate generator. There are two ways of generating the UART baud rate, using normal 450 UART baud rate generation and using the fractional UART Register Definitions divider. COM0TX Register Normal 450 UART Baud Rate Generation Name: COM0TX The baud rate is a divided version of the core clock using the value Address: 0xFFFF0700 in the COMxDIV0 and COMxDIV1 MMRs (16-bit value, DL). 41.78MHz Default Value: 0x00 BaudRate= 2CD×16×2×DL Access: Read/write Table 91 gives some common baud rate values. COM0TX is an 8-bit transmit register for UART0. Table 91. Baud Rate Using the Normal Baud Rate Generator COM1TX Register Baud Rate CD DL Actual Baud Rate % Error Name: COM1TX 9600 0 0x88 9600 0 19,200 0 0x44 19,200 0 Address: 0xFFFF0740 115,200 0 0x0B 118,691 3 9600 3 0x11 9600 0 Default Value: 0x00 19,200 3 0x08 20,400 6.25 Access: Read/write 115,200 3 0x01 163,200 41.67 The Fractional Divider COM1TX is an 8-bit transmit register for UART1. COM0RX Register The fractional divider, combined with the normal baud rate generator, produces a wider range of more accurate baud rates. Name: COM0RX CCLOOCRKE ÷ 2 FBEN Address: 0xFFFF0700 ÷ (M + N ÷ 2048) ÷ 16DL UART 09123-032 DAcecfaeusslt: Value: 0Rxe0a0d only Figure 48. Baud Rate Generation Options COM0RX is an 8-bit receive register for UART0. Calculation of the baud rate using fractional divider is as follows: 41.78MHz COM1RX Register Baud Rate=  N  Name: COM1RX 2CD×16×DL×2×M+   2048 Address: 0xFFFF0740 N 41.78MHz M+ = Default Value: 0x00 2048 Baud Rate × 2CD×16×DL×2 Access: Read only For example, generation of 19,200 baud with CD bits = 3 (Table 91 gives DL = 0x08) is COM1RX is an 8-bit receive register for UART1. M+ N = 41.78MHz COM0DIV0 Register 2048 19,200 ×23×16×8×2 Name: COM0DIV0 N M+ =1.06 Address: 0xFFFF0700 2048 where: Default Value: 0x00 M = 1. Access: Read/write N = 0.06 × 2048 = 128. 41.78MHz COM0DIV0 is a low byte divisor latch for UART0. COM0TX, BaudRate= COM0RX, and COM0DIV0 share the same address location.  128  23×16×8×2×  COM0TX and COM0RX can be accessed when Bit 7 in the 2048 COM0CON0 register is cleared. COM0DIV0 can be accessed where: when Bit 7 of COM0CON0 is set. Baud Rate = 19,200 bps. Rev. D | Page 63 of 110

ADuC7124/ADuC7126 Data Sheet COM1DIV0 Register COM0DIV1 Register Name: COM1DIV0 Name: COM0DIV1 Address: 0xFFFF0740 Address: 0xFFFF0704 Default Value: 0x00 Default Value: 0x00 Access: Read/write Access: Read/write COM1DIV0 is a low byte divisor latch for UART1. COM1TX, COM0DIV1 is a divisor latch (high byte) register for UART0. COM1RX, and COM1DIV0 share the same address location. COM1DIV1 Register COM1TX and COM1RX can be accessed when Bit 7 in Name: COM1DIV1 COM1CON0 register is cleared. COM1DIV0 can be accessed when Bit 7 of COM1CON0 is set. Address: 0xFFFF0744 COM0IEN0 Register Default Value: 0x00 Name: COM0IEN0 Access: Read/write Address: 0xFFFF0704 COM1DIV1 is a divisor latch (high byte) register for UART1. Default Value: 0x00 COM0IID0 Register Access: Read/write Name: COM0IID0 COM0IEN0 is the interrupt enable register for UART0. Address: 0xFFFF0708 COM1IEN0 Register Default Value: 0x01 Name: COM1IEN0 Access: Read only Address: 0xFFFF0744 COM0IID0 is the interrupt identification register for UART0. It Default Value: 0x00 also indicates if the UART is in FIFO mode. Access: Read/write COM1IID0 Register Name: COM1IID0 COM1IEN0 is the interrupt enable register for UART1. Address: 0xFFFF0748 Table 92. COMxIEN0 MMR Bit Descriptions Bit Name Description Default Value: 0x01 [7:4] Reserved. 3 EDSSI Modem status interrupt enable bit. Access: Read only Set by the user to enable generation of an interrupt if any of COMXSTA1[3:1] are set. COM1IID0 is the interrupt identification register for UART1. It Cleared by the user. also indicates if the UART is in FIFO mode. 2 ELSI Rx status interrupt enable bit. Set by the user to enable generation of an interrupt if any of COMxSTA0[3:0] are set. Cleared by the user. 1 ETBEI Enable transmit buffer empty interrupt. Set by the user to enable interrupt when the buffer is empty during a transmission. Cleared by the user. 0 ERBFI Enable receive buffer full interrupt. In non-FIFO mode, set by the user to enable an interrupt when buffer is full during a reception. Cleared by the user. In FIFO mode, set by the user to enable an interrupt when trigger level is reached. It also controls the character receive timeout interrupt. Cleared by the user. Rev. D | Page 64 of 110

Data Sheet ADuC7124/ADuC7126 Table 93. COMxIID0 MMR Bit Descriptions COM1FCR Register Bit Name Description Name: COM1FCR [7:6] FIFOMODE FIFO mode flag. 0x0: non-FIFO mode. Address: 0xFFFF0748 0x1: reserved. Default Value: 0x00 0x2: reserved. 0x3: FIFO mode. Set automatically if Access: Read/write FIFOEN is set. [5:4] Reserved The FIFO control register (FCR) is a write-only register at the [3:1] STATUS[2:0] Interrupt status bits that work only when same address as the interrupt identification register (IIR), which NINT is set. is a read-only register. [000]: modem status interrupt. Cleared by reading COMxSTA1. Priority 4. Table 94. COMxFCR MMR Bit Descriptions [001]: for non-FIFO mode, transmit buffer Bit Name Description empty interrupt. [7:5] RXFIFOTL Receiver FIFO trigger level. RXFIFOTL sets the For FIFO mode, Tx FIFO is empty. trigger level for the receiver FIFO. When the Cleared by writing COMxTX or reading trigger level is reached, a receiver data-ready COMxIID0. Priority 3. interrupt is generated (if the interrupt [010]: non-FIFO mode. Receive buffer data request is enabled). When the FIFO drops ready interrupt. Cleared automatically by below the trigger level, the interrupt is reading COMxRX. cleared. For FIFO mode, set trigger level reached. 0x0: one byte. Cleared automatically when FIFO drops 0x1: two bytes. below the trigger level. Priority 2. 0x2: four bytes. [011]: receive line status error interrupt. Cleared by reading COMxSTA0. Priority 1. 0x3: six bytes. [110]: Rx FIFO timeout interrupt (FIFO 0x4: eight bytes. mode only). Set automatically if there is at 0x5: 10 bytes. least one byte in the Rx FIFO, and there is 0x6: 12 bytes. no access to the Rx FIFO in the next four- 0x7: 14 bytes. frames accessing cycle. Cleared by reading COMxRX, setting RXRST, or when a new [4:3] Reserved byte arrives in the Rx FIFO1. Priority 2. 2 TXRST Tx FIFO reset. Writing a 1 flushes the Tx FIFO. [Other state]: reserved. Does not affect shift register. Note that TXRST should be cleared manually to make 0 NINT Set to disable interrupt flags by Tx FIFO work after flushing. STATUS[2:0]. Clear to enable interrupt. 1 RXRST Rx FIFO reset. Writing a 1 flushes the Rx FIFO. 1 A frame time is the time allotted for one start bit, n data bits, one parity bit, Does not affect shift register. Note that and one stop bit. Here, n is the word length selected with the WLS bits in RXRST should be cleared manually to make COMxCON0. the Rx FIFO work after flushing. WLS[1:0] = 00: timeout threshold = time for 32 bits = (1 + 5 + 1 + 1) × 4. WLS[1:0] = 01: timeout threshold = time for 36 bits = (1 + 6 + 1 + 1) × 4. 0 FIFOEN Transmitter and receiver FIFOs mode enable. WLS[1:0] = 10: timeout threshold = time for 40 bits = (1 + 7 + 1 + 1) × 4. FIFOEN must be set before other FCR bits are WLS[1:0] = 11: timeout threshold = time for 44 bits = (1 + 8 + 1 + 1) × 4. written to. Set for FIFO mode. The transmitter COM0FCR Register and receiver FIFOs are enabled. Cleared for non-FIFO mode; the transmitter and receiver Name: COM0FCR FIFOs are disabled, and the FIFO pointers are cleared. Address: 0xFFFF0708 COM0CON0 Register Default Value: 0x00 Name: COM0CON0 Access: Read/write Address: 0xFFFF070C The FIFO control register (FCR) is a write-only register at the same address as the interrupt identification register (IIR), which Default Value: 0x00 is a read-only register. Access: Read/write COM0CON0 is the line control register for UART0. Rev. D | Page 65 of 110

ADuC7124/ADuC7126 Data Sheet COM1CON0 Register COM1CON1 Register Name: COM1CON0 Name: COM1CON1 Address: 0xFFFF074C Address: 0xFFFF0750 Default Value: 0x00 Default Value: 0x00 Access: Read/write Access: Read/write COM1CON0 is the line control register for UART1. COM1CON1 is the modem control register for UART1. Table 95. COMxCON0 MMR Bit Descriptions Table 96. COMxCON1 MMR Bit Descriptions Bit Name Description Bit Name Description 7 DLAB Divisor latch access. [7:5] Reserved. Set by the user to enable access to the 4 LOOPBACK Loop back. COMxDIV0 and COMxDIV1 registers. Set by the user to enable loopback mode. Cleared by the user to disable access to In loopback mode, SOUTx is forced high. COMxDIV0 and COMxDIV1 and enable access to The modem signals are also directly con- COMxRX and COMxTX. nected to the status inputs (RTS to CTS and 6 BRK Set break. DTR to DSR). Set by the user to force SOUTx to 0. Cleared by the user to be in normal mode. Cleared to operate in normal mode. 3 PEN Parity enable bit. 5 SP Stick parity. Set by the user to transmit and check the parity bit. Set by the user to force parity to defined values: 1 if EPS = 1 and PEN = 1, 0 if EPS = 0 and PEN = 1. Cleared by the user for no parity transmission or checking. 4 EPS Even parity select bit. 2 Stop Stop bit. Set for even parity. Set by the user to transmit 1½ stop bits if Cleared for odd parity. the word length is five bits or two stop bits 3 PEN Parity enable bit. if the word length is six bits, seven bits, or Set by the user to transmit and check the eight bits. The receiver checks the first stop parity bit. bit only, regardless of the number of stop Cleared by the user for no parity transmission or bits selected. checking. Cleared by the user to generate one stop 2 Stop Stop bit. bit in the transmitted data. Set by the user to transmit 1½ stop bits if the word 1 RTS Request to send. length is five bits or two stop bits if the word Set by the user to force the RTS output to 0. length is six bits, seven bits, or eight bits. The Cleared by the user to force the RTS output receiver checks the first stop bit only, regardless to 1. of the number of stop bits selected. 0 DTR Data terminal ready. Cleared by the user to generate one stop bit in Set by the user to force the DTR output to the transmitted data. 0. [1:0] WLS Word length select: Cleared by the user to force the DTR output 00 = five bits, 01 = six bits, 10 = seven bits, 11 = to 1. eight bits. COM0CON1 Register COM0STA0 Register Name: COM0CON1 Name: COM0STA0 Address: 0xFFFF0710 Address: 0xFFFF0714 Default Value: 0x00 Default Value: 0xE0 Access: Read/write Access: Read only COM0CON1 is the modem control register for UART0. COM0STA0 is the line status register for UART0. Rev. D | Page 66 of 110

Data Sheet ADuC7124/ADuC7126 COM1STA0 Register Bit Name Description Name: COM1STA0 1 OE Overrun error. For non-FIFO mode, set automatically if Address: 0xFFFF0754 data is overwritten before being read. Cleared automatically. Default Value: 0xE0 For FIFO mode, set automatically if an overrun error has been detected. An Access: Read only overrun error occurs only after the FIFO is full and the next character has been COM1STA0 is the line status register for UART1. completely received in the shift register. The new character overwrites the Table 97. COMxSTA0 MMR Bit Descriptions character in the shift register, but it is Bit Name Description not transferred to the FIFO. 11 RX_error Set automatically if PE, FE, or BI is set. 0 DR Data ready. Cleared automatically when PE, FE, and For non-FIFO mode, set automatically BI are cleared . when COMxRX is full. Cleared by reading COMxRX. 10 RX_timeout Only for FIFO mode. Set automatically if there is at least one byte in the Rx FIFO For FIFO mode, set automatically when and there is no access to the Rx FIFO in there is at least one unread byte in the the next 4-byte accessing cycle. COMxRX. 9 RX_triggered Only for FIFO mode. Set automatically if COM0STA1 Register the Rx FIFO number exceeds the trigger Name: COM0STA1 level, which is configured by the FIFO control register COMxFCR[7:5]. Cleared Address: 0xFFFF0718 automatically when the Rx FIFO number is equal to or less than the trigger level. Default Value: 0x00 8 TX_full Only for FIFO mode. Set automatically if Tx FIFO is full. Cleared automatically Access: Read only when Tx FIFO is not full. 7 TX_half_empty Only for FIFO mode. Set automatically if COM0STA1 is a modem status register. the Tx FIFO is half empty (number of COM1STA1 Register bytes in Tx FIFO ≤ 8). Cleared automati- cally when the Tx FIFO received bytes is Name: COM1STA1 more than eight bytes. 6 TEMT COMxTX empty status bit. Address: 0xFFFF0758 For non-FIFO mode, both THR and TSR are empty. Default Value: 0x00 For FIFO mode, both Tx FIFO and TSR are Access: Read only empty. 5 THRE COMxTX and transmitter shift register COM1STA1 is a modem status register. empty. For non-FIFO mode, transmitter hold Table 98. COMxSTA1 MMR Bit Descriptions register (THR) empty or the content of Bit Name Description THR has been transferred to the transmitter shift register (TSR). 7 DCD Data carrier detect. For FIFO mode, Tx FIFO is empty, or the 6 RI Ring indicator. last character in the FIFO has been 5 DSR Data set ready. transferred to the transmitter shift 4 CTS Clear to send. register (TSR). 3 DDCD Delta DCD. Set automatically if DCD changed 4 BI Break error. state since last COMxSTA1 read. Cleared Set when SINx is held low for more than automatically by reading COMxSTA1. the maximum word length. 2 TERI Trailing edge RI. Set if RI changed from 0 to 1 Cleared automatically. since COMxSTA1 last read. Cleared automatically 3 FE Framing error. by reading COMxSTA1. Set when an invalid stop bit occurs. 1 DDSR Delta DSR. Set automatically if DSR changed state Cleared automatically. since COMxSTA1 last read. Cleared automatically 2 PE Parity error. by reading COMxSTA1. Set when a parity error occurs. 0 DCTS Delta CTS. Set automatically if CTS changed state Cleared automatically. since COMxSTA1 last read. Cleared automatically by reading COMxSTA1. Rev. D | Page 67 of 110

ADuC7124/ADuC7126 Data Sheet COM0DIV2 Register (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as byte wide (8-bit) Name: COM0DIV2 serial data, MSB first. Address: 0xFFFF072C SCLK (Serial Clock I/O) Pin Default Value: 0x0000 The master serial clock (SCLK) synchronizes the data being transmitted and received through the MOSI SCLK period. Access: Read/write Therefore, a byte is transmitted/received after eight SCLK periods. The SCLK pin is configured as an output in master COM0DIV2 is a 16-bit fractional baud divide register for mode and as an input in slave mode. UART0. COM1DIV2 Register In master mode, polarity and phase of the clock are controlled by the SPICON register, and the bit rate is defined in the Name: COM1DIV2 SPIDIV register as follows: Address: 0xFFFF076C f f  UCLK SERIALCLOCK 2(1SPIDIV) Default Value: 0x0000 The maximum speed of the SPI clock is independent of the Access: Read/write clock divider bits. COM1DIV2 is a 16-bit fractional baud divide register for UART1. In slave mode, the SPICON register must be configured with the phase and polarity of the expected input clock. The slave Table 99. COMxDIV2 MMR Bit Descriptions accepts data from an external master up to 10 Mbps. Bit Name Description In both master and slave modes, data is transmitted on one edge 15 FBEN Fractional baud rate generator enable bit. of the SCLK signal and sampled on the other. Therefore, it is Set by the user to enable the fractional baud rate generator. important that the polarity and phase be configured the same Cleared by the user to generate the baud for the master and slave devices. rate using the standard 450 UART baud CS (SPI Chip Select Input) Pin rate generator. [14:13] Reserved. In SPI slave mode, a transfer is initiated by the assertion of CS, [12:11] FBM[1:0] M if FBM = 0, M = 4 (see The Fractional which is an active low input signal. The SPI port then transmits Divider section). and receives 8-bit data until the transfer is concluded by deasser- [10:0] FBN[10:0] N (see The Fractional Divider section). tion of CS. In slave mode, CS is always an input. In SPI master mode, the CS is an active low output signal. It SERIAL PERIPHERAL INTERFACE asserts itself automatically at the beginning of a transfer and deasserts itself upon completion. The ADuC7124/ADuC7126 integrate a complete hardware serial peripheral interface (SPI) on chip. SPI is an industry standard, Configuring External Pins for SPI functionality synchronous serial interface that allows eight bits of data to be The SPI pins of the ADuC7124/ADuC7126 device are P1.4 to synchronously transmitted and simultaneously received, that is, P1.7. full duplex up to a maximum bit rate of 20 Mbps. P1.7 is the slave chip select pin. In slave mode, this pin is an The SPI port can be configured for master or slave operation input and must be driven low by the master. In master mode, and typically consists of four pins: MISO, MOSI, SCLK, and CS. this pin is an output and goes low at the beginning of a transfer MISO (Master In, Slave Out) Pin and high at the end of a transfer. The MISO pin is configured as an input line in master mode P1.4 is the SCLK pin. and an output line in slave mode. The MISO line on the master P1.5 is the master in, slave out (MISO) pin. (data in) should be connected to the MISO line in the slave P1.6 is the master out, slave in (MOSI) pin. device (data out). The data is transferred as byte wide (8-bit) To configure P1.4 to P1.7 for SPI mode, see the General- serial data, MSB first. Purpose Input/Output section. MOSI (Master Out, Slave In) Pin The MOSI pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on the master Rev. D | Page 68 of 110

Data Sheet ADuC7124/ADuC7126 SPI Registers The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON. SPI Status Register Name: SPISTA Address: 0xFFFF0A00 Default Value: 0x0000 Access: Read only Function: This 32-bit MMR contains the status of the SPI interface in both master and slave modes. Table 100. SPISTA MMR Bit Descriptions Bit Name Description [15:12] Reserved. 11 SPIREX SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the SPIMDE bits in SPICON This bit is cleared when the number of bytes in the FIFO is equal to or less than the number in SPIMDE. [10:8] SPIRXFSTA[2:0] SPI Rx FIFO status bits. [000] = Rx FIFO is empty. [001] = one valid byte in the FIFO. [010] = two valid bytes in the FIFO. [011] = three valid bytes in the FIFO. [100] = four valid bytes in the FIFO. 7 SPIFOF SPI Rx FIFO overflow status bit. Set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt except when SPIRFLH is set in SPICON. Cleared when the SPISTA register is read. 6 SPIRXIRQ SPI Rx IRQ status bit. Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required number of bytes has been received. Cleared when the SPISTA register is read. 5 SPITXIRQ SPI Tx IRQ status bit. Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number of bytes has been transmitted. Cleared when the SPISTA register is read. 4 SPITXUF SPI Tx FIFO underflow. This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when SPITFLH is set in SPICON. Cleared when the SPISTA register is read. [3:1] SPITXFSTA[2:0] SPI Tx FIFO status bits. [000] = Tx FIFO is empty. [001] = one valid byte in the FIFO. [010] = two valid bytes in the FIFO. [011] = three valid bytes in the FIFO. [100] = four valid bytes in the FIFO. 0 SPIISTA SPI interrupt status bit. Set to 1 when an SPI-based interrupt occurs. Cleared after reading SPISTA. Rev. D | Page 69 of 110

ADuC7124/ADuC7126 Data Sheet SPIRX Register SPIDIV Register Name: SPIRX Name: SPIDIV Address: 0xFFFF0A04 Address: 0xFFFF0A0C Default Value: 0x00 Default Value: 0x00 Access: Read only Access: Read/write Function: This 8-bit MMR is the SPI receive register. Function: This 8-bit MMR is the SPI baud rate selection register. SPITX Register SPICON Register Name: SPITX Name: SPICON Address: 0xFFFF0A08 Address: 0xFFFF0A10 Default Value: 0x00 Default Value: 0x0000 Access: Write only Access: Read/write Function: This 8-bit MMR is the SPI transmit register. Function: This 16-bit MMR configures the SPI peripheral in both master and slave modes. Table 101. SPICON MMR Bit Descriptions Bit Name Description [15:14] SPIMDE SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer. [00] = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have been received into the FIFO. [01] = Tx interrupt occurs when two bytes have been transferred. Rx interrupt occurs when two or more bytes have been received into the FIFO. [10] = Tx interrupt occurs when three bytes have been transferred. Rx interrupt occurs when three or more bytes have been received into the FIFO. [11] = Tx interrupt occurs when four bytes have been transferred. Rx interrupt occurs when the Rx FIFO is full or four bytes are present. 13 SPITFLH SPI Tx FIFO flush enable bit. Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted, depending on the SPIZEN bit. Any writes to the Tx FIFO are ignored while this bit is set. Clear this bit to disable Tx FIFO flushing. 12 SPIRFLH SPI Rx FIFO flush enable bit. Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is set incoming, data is ignored and no interrupts are generated. If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer. Clear this bit to disable Rx FIFO flushing. 11 SPICONT Continuous transfer enable. Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the SPITX register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until SPITX is empty. Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle. 10 SPILP Loopback enable bit. Set by the user to connect MISO to MOSI and test software. Cleared by the user to be in normal mode. Rev. D | Page 70 of 110

Data Sheet ADuC7124/ADuC7126 Bit Name Description 9 SPIOEN Slave MISO output enable bit. Set this bit for MISO to operate as normal. Clear this bit to disable the output driver on the MISO pin. The MISO pin is open-drain when this bit is cleared. 8 SPIROW SPIRX overflow overwrite enable. Set by the user, the valid data in the SPIRX register is overwritten by the new serial byte received. Cleared by the user, the new serial byte received is discarded. 7 SPIZEN SPI transmits zeros when Tx FIFO is empty. Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO. Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO. 6 SPITMDE SPI transfer and interrupt mode. Set by the user to initiate transfer with a write to the SPITX register. Interrupt occurs only when SPITX is empty. Cleared by the user to initiate transfer with a read of the SPIRX register. Interrupt occurs only when SPIRX is full. 5 SPILF LSB first transfer enable bit. Set by the user, the LSB is transmitted first. Cleared by the user, the MSB is transmitted first. 4 SPIWOM SPI wire-OR’ed mode enable bit. Set to 1 enable open-drain data output. External pull-ups required on data output pins. Cleared for normal output levels. 3 SPICPO Serial clock polarity mode bit. Set by the user, the serial clock idles high. Cleared by the user, the serial clock idles low. 2 SPICPH Serial clock phase mode bit. Set by the user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by the user, the serial clock pulses at the end of each serial bit transfer. 1 SPIMEN Master mode enable bit. Set by the user to enable master mode. Cleared by the user to enable slave mode. 0 SPIEN SPI enable bit. Set by the user to enable the SPI. Cleared by the user to disable the SPI. Rev. D | Page 71 of 110

ADuC7124/ADuC7126 Data Sheet I2C Configuring External Pins for I2C Functionality The ADuC7124/ADuC7126 incorporate two I2C peripherals The I2C pins of the ADuC7124/ADuC7126 device are P1.0 and that can be configured as a fully I2C-compatible I2C bus master P1.1 for I2C0 and P1.2 and P1.3 for I2C1. device or as a fully I2C bus compatible slave device. Both I2C P1.0 and P1.2 are the I2C clock signals, and P1.1 and P1.3 are channels are identical. Therefore, the following descriptions the I2C data signals. For instance, to configure I2C0 pins (SCL0, apply to both channels. SDA0), Bit 0 and Bit 4 of the GP1CON register must be set to 1 The two pins used for data transfer, SDA and SCL, are configured to enable I2C mode. On the other hand, to configure I2C1 pins in a wire-AND’ed format that allows arbitration in a multimaster (SCL1, SDA1), Bit 8 and Bit 12 of the GP1CON register must system. These pins require external pull-up resistors. Typical be set to 1 to enable I2C mode, as shown in the General-Purpose pull-up values are between 4.7 kΩ and 10 kΩ. Input/Output section. The I2C bus peripheral address in the I2C bus system is Serial Clock Generation programmed by the user. This ID can be modified any time a The I2C master in the system generates the serial clock for a transfer is not in progress. The user can configure the interface transfer. The master channel can be configured to operate in to respond to four slave addresses. fast mode (400 kHz) or standard mode (100 kHz). The transfer sequence of an I2C system consists of a master The bit rate is defined in the I2CxDIV MMR as follows: device initiating a transfer by generating a start condition while f the bus is idle. The master transmits the slave device address f = UCLK SERIALCLOCK (2+DIVH) + (2 + DIVL) and the direction of the data transfer (read or/write) during the initial address transfer. If the master does not lose arbitration where: and the slave acknowledges, the data transfer is initiated. This fUCLK is the clock before the clock divider. continues until the master issues a stop condition and the bus DIVH is the high period of the clock. becomes idle. DIVL is the low period of the clock. The I2C peripheral can only be configured as a master or slave at Therefore, for 100 kHz operation, any given time. The same I2C channel cannot simultaneously DIVH = DIVL = 0xCF support master and slave modes. and for 400 kHz The I2C interface on the ADuC7124/ADuC7126 includes the DIVH = 0x28, DIVL = 0x3C following features: The I2CxDIV register corresponds to DIVH:DIVL. • Support for repeated start conditions. In master mode, the ADuC7124/ADuC7126 can be programmed to generate a I2C Bus Addresses repeated start. In slave mode, the ADuC7124/ADuC7126 Slave Mode recognizes repeated start conditions. In slave mode, the I2CxID0, I2CxID1, I2CxID2, and I2CxID3 • In master and slave mode, the part recognizes both 7-bit registers contain the device IDs. The device compares the four and 10-bit bus addresses. I2CxIDx registers to the address byte received from the bus • In I2C master mode, the ADuC7124/ADuC7126 supports master. To be correctly addressed, the seven MSBs of either ID continuous reads from a single slave up to 512 bytes in a register must be identical to the seven MSBs of the first received single transfer sequence. address byte. The LSB of the ID registers (the transfer direction • Clock stretching can be enabled by other devices on the bit) is ignored in the process of address recognition. bus without causing any issues with the ADuC7124/ The ADuC7124/ADuC7126 also support 10-bit addressing ADuC7126. However, the ADuC7124/ADuC7126 cannot mode. When Bit 1 of I2CxSCON (ADR10EN bit) is set to 1, one enable clock stretching. 10-bit address is supported in slave mode and is stored in the • In slave mode, the ADuC7124/ADuC7126 can be pro- I2CxID0 and I2CxID1 registers. The 10-bit address is derived as grammed to return a NACK. This allows the validiation of follows: checksum bytes at the end of I2C transfers. • Bus arbitration in master mode is supported. I2CxID0[0] is the read/write bit and is not part of the I2C • Internal and external loopback modes are supported for address. I2C hardware testing in loopback mode. I2CxID0[7:1] = Address Bits[6:0]. • The transmit and receive circuits in both master and slave I2CxID1[2:0] = Address Bits[9:7]. mode contain 2-byte FIFOs. Status bits are available to the I2CxID1[7:3] must be set to 11110b. user to control these FIFOs. Rev. D | Page 72 of 110

Data Sheet ADuC7124/ADuC7126 Master Mode I2C Master Registers In master mode, the I2CxADR0 register is programmed with I2C Master Control Register the I2C address of the device. Name: I2C0MCON, I2C1MCON In 7-bit address mode, I2CxADR0[7:1] are set to the device Address: 0xFFFF0800, 0xFFFF0900 address. I2CxADR0[0] is the read/write bit. In 10-bit address mode, the 10-bit address is created as follows: Default 0x0000, 0x0000 Value: I2CxADR0[7:3] must be set to 11110b. I2CxADR0[2:1] = Address Bits[9:8]. Access: Read/write I2CxADR1[7:0] = Address Bits[7:0]. Function: This 16-bit MMR configures the I2C peripheral in I2CxADR0[0] is the read/write bit. master mode. I2C Registers The I2C peripheral interfaces consists of a number of MMRs. These are described in the I2C Master Registers section. Table 102. I2CxMCON MMR Bit Descriptions Bit Name Description [15:9] Reserved. These bits are reserved and should not be written to. 8 I2CMCENI I2C transmission complete interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this bit to clear the interrupt source. 7 I2CNACKENI I2C no acknowledge (NACK) received interrupt enable bit. Set this bit to enable interrupts when the I2C master receives a NACK. Clear this bit to clear the interrupt source. 6 I2CALENI I2C arbitration lost interrupt enable bit. Set this bit to enable interrupts when the I2C master is unable to gain control of the I2C bus. Clear this bit to clear the interrupt source. 5 I2CMTENI I2C transmit interrupt enable bit. Set this bit to enable interrupts when the I2C master has transmitted a byte. Clear this bit to clear the interrupt source. 4 I2CMRENI I2C receive interrupt enable bit. Set this bit to enable interrupts when the I2C master receives data. Cleared by user to disable interrupts when the I2C master is receiving data. 3 RESERVED Reserved. A value of 0 should be written to this bit. 2 I2CILEN I2C internal loopback enable. Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their respective input signals. Cleared by the user to disable loopback mode. 1 I2CBD I2C master backoff disable bit. Set this bit to allow the device to compete for control of the bus even if another device is currently driving a start condition. Clear this bit to wait until the I2C bus becomes free. 0 I2CMEN I2C master enable bit. Set by the user to enable I2C master mode. Clear this bit to disable I2C master mode. Rev. D | Page 73 of 110

ADuC7124/ADuC7126 Data Sheet I2C Master Status Register Name: I2C0MSTA, I2C1MSTA Address: 0xFFFF0804, 0xFFFF0904 Default Value: 0x0000, 0x0000 Access: Read only Function: This 16-bit MMR is the I2C status register in master mode. Table 103. I2CxMSTA MMR Bit Descriptions Bit Name Description [15:11] Reserved. 10 I2CBBUSY I2C bus busy status bit. This bit is set to 1 when a start condition is detected on the I2C bus. This bit is cleared when a stop condition is detected on the bus. 9 I2CMRxFO Master Rx FIFO overflow. This bit is set to 1 when a byte is written to the Rx FIFO when it is already full. This bit is cleared in all other conditions. 8 I2CMTC I2C transmission complete status bit. This bit is set to 1 when a transmission is complete between the master and the slave it was communicating with. If the I2CMCENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. Clear this bit to clear the interrupt source. 7 I2CMNA I2C master NACK data bit. This bit is set to 1 when a NACK condition is received by the master in response to a data write transfer. If the I2CNACKENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 6 I2CMBUSY I2C master busy status bit. Set to 1 when the master is busy processing a transaction. Cleared if the master is ready or if another master device has control of the bus. 5 I2CAL I2C arbitration lost status bit. This bit is set to 1 when the I2C master is unable to gain control of the I2C bus. If the I2CALENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 4 I2CMNA I2C master NACK address bit. This bit is set to 1 when a NACK condition is received by the master in response to an address. If the I2CNACKENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 3 I2CMRXQ I2C master receive request bit. This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2CxMCON is set, an interrupt is generated. This bit is cleared in all other conditions. 2 I2CMTXQ I2C master transmit request bit. This bit goes high if the Tx FIFO is empty or contains only one byte and the master has transmitted an address + write. If the I2CMTENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. [1:0] I2CMTFSTA I2C master Tx FIFO status bits. 00 = I2C master Tx FIFO empty. 01 = one byte in master Tx FIFO. 10 = one byte in master Tx FIFO. 11 = I2C master Tx FIFO full. Rev. D | Page 74 of 110

Data Sheet ADuC7124/ADuC7126 I2C Master Receive Register I2C Master Current Read Count Register Name: I2C0MRX, I2C1MRX Name: I2C0MCNT1, I2C1MCNT1 Address: 0xFFFF0808, 0xFFFF0908 Address: 0xFFFF0814, 0xFFFF0914 Default Value: 0x00 Default Value: 0x00, 0x00 Access: Read only Access: Read only Function: This 8-bit MMR is the I2C master receive Function: This 8-bit MMR holds the number of bytes register. received so far during a read sequence with a slave device. I2C Master Transmit Register I2C Address 0 Register Name: I2C0MTX, I2C1MTX Name: I2C0ADR0, I2C1ADR0 Address: 0xFFFF080C 0xFFFF090C Address: 0xFFFF0818, 0xFFFF0918 Default Value: 0x00, 0x00 Default Value: 0x00 Access: Read/write Access: Read/write Function: This 8-bit MMR is the I2C master transmit register. Function: This 8-bit MMR holds the 7-bit slave address + the read/write bit when the master begins I2C Master Read Count Register communicating with a slave. Name: I2C0MCNT0, I2C1MCNT0 Table 105. I2CxADR0 MMR in 7-Bit Address Mode Address: 0xFFFF0810, 0xFFFF0910 Bit Name Description Default Value: 0x0000, 0x0000 [7:1] I2CADR These bits contain the 7-bit address of the required slave device. Access: Read/write 0 R/W Bit 0 is the read/write bit. When this bit = 1, a read sequence is Function: This 16-bit MMR holds the required number requested. of bytes when the master begins a read When this bit = 0, a write sequence is sequence from a slave device. requested. Table 104. I2CxMCNT0 MMR Bit Descriptions Table 106. I2CxADR0 MMR in 10-Bit Address Mode Bit Name Description Bit Name Description [15:9] Reserved. [7:3] These bits must be set to [11110b] in 10-bit address mode. 8 I2CRECNT Set this bit if more than 256 bytes are required from the slave. [2:1] I2CMADR These bits contain ADDR[9:8] in 10-bit addressing mode. Clear this bit when reading 256 bytes or less. 0 R/W Read/write bit. [7:0] I2CRCNT These eight bits hold the number of bytes When this bit = 1, a read sequence is required during a slave read sequence, requested. minus 1. If only a single byte is required, When this bit = 0, a write sequence is these bits should be set to 0. requested. Rev. D | Page 75 of 110

ADuC7124/ADuC7126 Data Sheet I2C Address 1 Register Table 108. I2CxDIV MMR Bit Name Description Name: I2C0ADR1, I2C1ADR1 [15:8] DIVH These bits control the duration of the high Address: 0xFFFF081C, 0xFFFF091C period of SCL. [7:0] DIVL These bits control the duration of the low Default Value: 0x00 period of SCL. Access: Read/write I2C Slave Registers Function: This 8-bit MMR is used in 10-bit addressing I2C Slave Control Register mode only. This register contains the least Name: I2C0SCON, I2C1SCON significant byte of the address. Address: 0xFFFF0828, 0xFFFF0928 Table 107. I2CxADR1 MMR in 10-Bit Address Mode Bit Name Description Default Value: 0x0000 [7:0] I2CLADR These bits contain ADDR[7:0] in 10-bit Access: Read/write addressing mode. I2C Master Clock Control Register Function: This 16-bit MMR configures the I2C peripheral in slave mode. Name: I2C0DIV, I2C1DIV Address: 0xFFFF0824, 0xFFFF0924 Default Value: 0x1F1F Access: Read/write Function: This MMR controls the frequency of the I2C clock generated by the master on to the SCL pin. For further details, see the I2C section. Table 109. I2CxSCON MMR Bit Descriptions Bit Name Description [15:11] Reserved. 10 I2CSTXENI Slave transmit interrupt enable bit. Set this bit to enable an interrupt after a slave transmits a byte. Clear this interrupt source. 9 I2CSRXENI Slave receive interrupt enable bit. Set this bit to enable an interrupt after the slave receives data. Clear this interrupt source. 8 I2CSSENI I2C stop condition detected interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this interrupt source. 7 I2CNACKEN I2C NACK enable bit. Set this bit to NACK the next byte in the transmission sequence. Clear this bit to let the hardware control the ACK/NACK sequence. 6 RESERVED Reserved. A value of 0 should be written to this bit. 5 I2CSETEN I2C early transmit interrupt enable bit. Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit transmission. Clear this bit to enable a transmit request interrupt just after the negative edge of SCL during the read bit transmission. 4 I2CGCCLR I2C general call status and ID clear bit. Writing a 1 to this bit clears the general call status (I2CGC) and ID (I2CGCID[1:0]) bits in the I2CxSSTA register. Clear this bit at all other times. Rev. D | Page 76 of 110

Data Sheet ADuC7124/ADuC7126 Bit Name Description 3 I2CHGCEN I2C hardware general call enable. When this bit and Bit 2 are set, and having received a general call (Address 0x00) and a data byte, the device checks the contents of the I2CxALT against the receive register. If the contents match, the device has received a hardware general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a broadcast message to all master devices on the bus. The ADuC7124/ ADuC7126 watch for these addresses. The device that requires attention embeds its own address into the message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately. The LSB of the I2CxALT register should always be written to 1, as per the I2C January 2000 bus specification. Set this bit and I2CGCEN to enable hardware general call recognition in slave mode. Clear this bit to disable recognition of hardware general call commands. 2 I2CGCEN I2C general call enable. Set this bit to enable the slave device to acknowledge an I2C general call, Address 0x00 (write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave address by hard- ware) as the data byte, the I2C interface resets as per the I2C January 2000 bus specification. This command can be used to reset an entire I2C system. If it receives a 0x04 (write programmable part of the slave address by hardware) as the data byte, the general call interrupt status bit sets on any general call. The user must take corrective action by reprogramming the device address. Set this bit to allow the slave ACK I2C general call commands. Clear this bit to disable recognition of general call commands. 1 ADR10EN I2C 10-bit address mode. Set to 1 to enable 10-bit address mode. Clear to 0 to enable normal address mode. 0 I2CSEN I2C slave enable bit. Set by the user to enable I2C slave mode. Clear this bit to disable I2C slave mode. I2C Slave Status Registers Name: I2C0SSTA, I2C1SSTA Address: 0xFFFF082C, 0xFFFF092C Default Value: 0x0000, 0x0000 Access: Read only Function: This 16-bit MMR is the I2C status register in slave mode. Table 110. I2CxSSTA MMR Bit Descriptions Bit Name Description 15 Reserved. 14 I2CSTA This bit is set to 1 if a start condition followed by a matching address is detected, a start byte (0x01) is received, or general calls are enabled and a general call code of (0x00) is received. This bit is cleared on receiving a stop condition. 13 I2CREPS This bit is set to 1 if a repeated start condition is detected. This bit is cleared on receiving a stop condition. A read of the I2CxSSTA register also clears this bit. [12:11] I2CID[1:0] I2C address matching register. These bits indicate which I2CxIDx register matches the received address. [00] = received address matches I2CxID0. [01] = received address matches I2CxID1. [10] = received address matches I2CxID2. [11] = received address matches I2CxID3. 10 I2CSS I2C stop condition after start detected bit. This bit is set to 1 when a stop condition is detected after a previous start and matching address. When the I2CSSENI bit in I2CxSCON is set, an interrupt is generated. This bit is cleared by reading this register. Rev. D | Page 77 of 110

ADuC7124/ADuC7126 Data Sheet Bit Name Description [9:8] I2CGCID[1:0] I2C general call ID bits. [00] = no general call received. [01] = general call reset and program address. [10] = general program address. [11] = general call matching alternative ID. Note that these bits are not cleared by a general call reset command. Clear these bits by writing a 1 to the I2CGCCLR bit in I2CxSCON. 7 I2CGC I2C general call status bit. This bit is set to 1 if the slave receives a general call command of any type. If the command received is a reset command, then all registers return to their default states. If the command received is a hardware general call, the Rx FIFO holds the second byte of the command and this can be compared with the I2CxALT register. Clear this bit by writing a 1 to the I2CGCCLR bit in I2CxSCON. 6 I2CSBUSY I2C slave busy status bit. Set to 1 when the slave receives a start condition. Cleared by hardware if the received address does not match any of the I2CxIDx registers, the slave device receives a stop condition, or a repeated start address does not match any of the I2CxIDx registers. 5 I2CSNA I2C slave NACK data bit. This bit is set to 1 when the slave responds to a bus address with a NACK. This bit is asserted if a NACK was returned because there was no data in the Tx FIFO or the I2CNACKEN bit was set in the I2CxSCON register. This bit is cleared in all other conditions. 4 I2CSRxFO Slave Rx FIFO overflow. This bit is set to 1 when a byte is written to the Rx FIFO when it is already full. This bit is cleared in all other conditions. 3 I2CSRXQ I2C slave receive request bit. This bit is set to 1 when the slave Rx FIFO is not empty. This bit causes an interrupt to occur when the I2CSRXENI bit in I2CxSCON is set. The Rx FIFO must be read or flushed to clear this bit. 2 I2CSTXQ I2C slave transmit request bit. This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in I2CxSCON = 0, this bit goes high just after the negative edge of SCL during the read bit transmission. If the I2CSETEN bit in I2CxSCON = 1, this bit goes high just after the positive edge of SCL during the read bit transmission. This bit causes an interrupt to occur when the I2CSTXENI bit in I2CxSCON is set. This bit is cleared in all other conditions. 1 I2CSTFE I2C slave FIFO underflow status bit. This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at the rising edge of SCL during the read bit. This bit is cleared in all other conditions. 0 I2CETSTA I2C slave early transmit FIFO status bit. If the I2CSETEN bit in I2CxSCON = 0, this bit goes high if the slave Tx FIFO is empty. If the I2CSETEN bit in I2CxSCON = 1, this bit goes high just after the positive edge of SCL during the write bit transmission. This bit asserts once only for a transfer. This bit is cleared after being read. Rev. D | Page 78 of 110

Data Sheet ADuC7124/ADuC7126 I2C Slave Receive Registers I2C Common Registers Name: I2C0SRX, I2C1SRX I2C FIFO Status Register Address: 0xFFFF0830, 0xFFFF0930 Name: I2C0FSTA, I2C1FSTA Default Value: 0x00 Address: 0xFFFF084C, 0xFFFF094C Access: Read Default Value: 0x0000 Function: This 8-bit MMR is the I2C slave receive register. Access: Read/write Function: These 16-bit MMRs contain the status of the I2C Slave Transmit Registers Rx/Tx FIFOs in both master and slave modes. Name: I2C0STX, I2C1STX Table 111. I2CxFSTA MMR Bit Descriptions Address: 0xFFFF0834, 0xFFFF0934 Bit Name Description Default Value: 0x00 [15:10] Reserved. 9 I2CFMTX Set this bit to 1 to flush the master Tx Access: Write FIFO. 8 I2CFSTX Set this bit to 1 to flush the slave Tx FIFO. Function: This 8-bit MMR is the I2C slave transmit register. [7:6] I2CMRXSTA I2C master receive FIFO status bits. I2C Hardware General Call Recognition Registers [00] = FIFO empty. [01] = byte written to FIFO. Name: I2C0ALT, I2C1ALT [10] = one byte in FIFO. Address: 0xFFFF0838, 0xFFFF0938 [11] = FIFO full. [5:4] I2CMTXSTA I2C master transmit FIFO status bits. Default Value: 0x00 [00] = FIFO empty. [01] = byte written to FIFO. Access: Read/write [10] = one byte in FIFO. Function: This 8-bit MMR is used with hardware general [11] = FIFO full. calls when I2CxSCON Bit 3 is set to 1. This [3:2] I2CSRXSTA I2C slave receive FIFO status bits. register is used in cases where a master is unable [00] = FIFO empty. to generate an address for a slave, and instead, the [01] = byte written to FIFO. slave must generate the address for the master. [10] = one byte in FIFO. [11] = FIFO full. I2C Slave Device ID Registers [1:0] I2CSTXSTA I2C slave transmit FIFO status bits. Name: I2C0IDx, I2C1IDx [00] = FIFO empty. [01] = byte written to FIFO. Addresses: 0xFFFF093C = I2C1ID0 [10] = one byte in FIFO. 0xFFFF083C = I2C0ID0 [11] = FIFO full. 0xFFFF0940 = I2C1ID1 0xFFFF0840 = I2C0ID1 0xFFFF0944 = I2C1ID2 0xFFFF0844 = I2C0ID2 0xFFFF0948 = I2C1ID3 0xFFFF0848 = I2C0ID3 Default Value: 0x00 Access: Read/write Function: These 8-bit MMRs are programmed with I2C bus IDs of the slave. See the I2C Bus Addresses section for further details. Rev. D | Page 79 of 110

ADuC7124/ADuC7126 Data Sheet PWM GENERAL OVERVIEW In all modes, the PWMxCOMx MMRs control the point at The ADuC7124/ADuC7126 integrate a 6-channel PWM which the PWM outputs change state. An example of the first pair interface (PWM0 to PWM5). The PWM outputs can be of PWM outputs (PWM0 and PWM1) is shown in Figure 49. configured to drive an H-bridge or can be used as standard PWM outputs. On power-up, the PWM outputs default to H-bridge HIGH SIDE mode. This ensures that the motor is turned off by default. In (PWM0) standard PWM mode, the outputs are arranged as three pairs of PWM pins. The user has control over the period of each pair of LOW SIDE outputs and over the duty cycle of each individual output. (PWM1) Table 112. PWM MMRs Name Function PWM0COM2 PWMCON0 PWM control. PWM0COM1 PWM0COM0 Compare Register 0 for PWM Output 0 and PWM Output 1. PWM0COM0 PWM0COM1 CPWomMp Oaruet pRuegt 1is.t er 1 for PWM Output 0 and PWM0LEN 09123-120 PWM0COM2 Compare Register 2 for PWM Output 0 and Figure 49. PWM Timing PWM Output 1. The PWM clock is selectable via PWMCON with one of the PWM0LEN Frequency control for PWM Output 0 and following values: UCLK divided by 2, 4, 8, 16, 32, 64, 128, or PWM Output 1. 256. The length of a PWM period is defined by PWMxLEN. PWM1COM0 Compare Register 0 for PWM Output 2 and PWM Output 3. The PWM waveforms are set by the count value of the 16-bit PWM1COM1 Compare Register 1 for PWM Output 2 and timer and the compare registers contents, as shown with the PWM Output 3. PWM0 and PWM1 waveforms in Figure 49. PWM1COM2 Compare Register 2 for PWM Output 2 and PWM Output 3. The low-side waveform, PWM1, goes high when the timer PWM1LEN Frequency control for PWM Output 2 and count reaches PWM0LEN, and it goes low when the timer PWM Output 3. count reaches the value held in PWM0COM2 or when the PWM2COM0 Compare Register 0 for PWM Output 4 and high-side waveform (PWM0) goes low. Output 5 The high-side waveform, PWM0, goes high when the timer PWM2COM1 Compare Register 1 for PWM Output 4 and count reaches the value held in PWM0COM0, and it goes low Output 5 when the timer count reaches the value held in PWM0COM1. PWM2COM2 Compare Register 2 for PWM Output 4 and Output 5 PWM2LEN Frequency control for PWM Output 4 and PWM Output 5. PWMCON1 PWM control register PWMCLRI PWM interrupt clear. Rev. D | Page 80 of 110

Data Sheet ADuC7124/ADuC7126 Table 113. PWMCON0 MMR Bit Descriptions Bit Name Description 14 SYNC Enables PWM synchronization. Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low transition on the P3.7/PWM pin. SYNC Cleared by the user to ignore transitions on the P3.7/PWM pin. SYNC 13 PWM5INV Set to 1 by the user to invert PWM5. Cleared by the user to use PWM5 in normal mode. 12 PWM3INV Set to 1 by the user to invert PWM3. Cleared by the user to use PWM3 in normal mode. 11 PWM1INV Set to 1 by the user to invert PWM1. Cleared by the user to use PWM1 in normal mode. 10 PWMTRIP Set to 1 by the user to enable PWM trip interrupt. When the PWM trip input (Pin P3.6/PWM or Pin P0.4/PWM ) TRIP TRIP is low, the PWMEN bit is cleared and an interrupt is generated. Cleared by the user to disable the PWMTRIP interrupt. 9 ENA If HOFF = 0 and HMODE = 1; note that, if not in H-bridge mode, this bit has no effect. Set to 1 by the user to enable PWM outputs. Cleared by the user to disable PWM outputs. If HOFF = 1 and HMODE = 1, see Table 114. [8:6] PWMCP[2:0] PWM clock prescaler bits. Sets the UCLK divider. [000] = UCLK/2. [001] = UCLK/4. [010] = UCLK/8. [011] = UCLK/16. [100] = UCLK/32. [101] = UCLK/64. [110] = UCLK/128. [111] = UCLK/256. 5 POINV Set to 1 by the user to invert all PWM outputs. Cleared by the user to use PWM outputs as normal. 4 HOFF High side off. Set to 1 by the user to force PWM0 and PWM2 outputs high. This also forces PWM1 and PWM3 low. Cleared by the user to use the PWM outputs as normal. 3 LCOMP Load compare registers. Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of the PWM timer from 0x00 to 0x01. Cleared by the user to use the values previously stored in the internal compare registers. 2 DIR Direction control. Set to 1 by the user to enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low. Cleared by the user to enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low. 1 HMODE Enables H-bridge mode.1 Set to 1 by the user to enable H-bridge mode and Bit 1 to Bit 5 of PWMCON. Cleared by the user to operate the PWMs in standard mode. 0 PWMEN Set to 1 by the user to enable all PWM outputs. Cleared by the user to disable all PWM outputs. 1 In H-bridge mode, HMODE = 1. See Table 114 to determine the PWM outputs. Rev. D | Page 81 of 110

ADuC7124/ADuC7126 Data Sheet Table 114. PWM Output Selection, HMODE = 1 Table 116. PWMCON1 MMR Bit Descriptions (Address = PWMCON0 MMR1 PWM Outputs2 0xFFFF0FB4; Default Value = 0x00) ENA HOFF POINV DIR PWM0 PWM1 PWM2 PWM3 Bit Value Name Description 0 0 X X 1 1 1 1 7 CSEN Set to 1 by the user to enable the PWM X 1 X X 1 0 1 0 to generate a convert start signal. 1 0 0 0 0 0 HS LS Cleared by user to disable the PWM 1 0 0 1 HS LS 0 0 convert start signal. 1 0 1 0 HS LS 1 1 [3:0] CSD3 Convert start delay. Delays the convert 1 0 1 1 1 1 HS LS start signal by a number of clock pulses. 1 X = don’t care. 2 HS = high side, LS = low side. CSD2 On power-up, PWMCON0 defaults to 0x12 (HOFF = 1 and CSD1 HMODE = 1). All GPIO pins associated with the PWM are CSD0 configured in PWM mode by default (see Table 115). 0000 Four clock pulses. 0001 Eight clock pulses. Table 115. Compare Registers 0010 12 clock pulses. Name Address Default Value Access 0011 16 clock pulses. PWM0COM0 0xFFFF0F84 0x0000 R/W 0100 20 clock pulses. PWM0COM1 0xFFFF0F88 0x0000 R/W 0101 24 clock pulses. PWM0COM2 0xFFFF0F8C 0x0000 R/W 0110 28 clock pulses. PWM1COM0 0xFFFF0F94 0x0000 R/W 0111 32 clock pulses. PWM1COM1 0xFFFF0F98 0x0000 R/W 1000 36 clock pulses. PWM1COM2 0xFFFF0F9C 0x0000 R/W 1001 40 clock pulses. PWM2COM0 0xFFFF0FA4 0x0000 R/W 1010 44 clock pulses. PWM2COM1 0xFFFF0FA8 0x0000 R/W 1011 48 clock pulses. PWM2COM2 0xFFFF0FAC 0x0000 R/W 1100 52 clock pulses. The PWM trip interrupt can be cleared by writing any value to 1101 56 clock pulses. the PWMCLRI MMR. Note that, when using the PWM trip 1110 60 clock pulses. interrupt, users should make sure that the PWM interrupt 1111 64 clock pulses. has been cleared before exiting the ISR. This prevents generation of multiple interrupts. When calculating the time from the convert start delay to the start of an ADC conversion, the user must take account of PWM Convert Start Control internal delays. The following example shows the case of a delay The PWM can be configured to generate an ADC convert start of four clocks. One additional clock is required to pass the signal after the active low side signal goes high. There is a convert start signal to the ADC logic. Once the ADC logic programmable delay between the time that the low-side signal receives the convert start signal, an ADC conversion begins on goes high and the convert start signal is generated. the next ADC clock edge (see Figure 50). This is controlled via the PWMCON1 MMR. If the delay selected is higher than the width of the PWM pulse, the UCLK interrupt remains low. LOW SIDE COUNT PWM SIGNAL TO CONVST SITGON AALD CP ALSOSGEIDC 09123-045 Figure 50. ADC Conversion Rev. D | Page 82 of 110

Data Sheet ADuC7124/ADuC7126 PROGRAMMABLE LOGIC ARRAY (PLA) PLA MMRs Interface The PLA peripheral interface consists of the 22 MMRs. Every ADuC7124/ADuC7126 integrates a fully programmable logic array (PLA) that consists of two independent but Table 118. PLAELMx Registers interconnected PLA blocks. Each block consists of eight PLA Name Address Default Value Access elements, giving each part a total of 16 PLA elements. PLAELM0 0xFFFF0B00 0x0000 R/W PLAELM1 0xFFFF0B04 0x0000 R/W Each PLA element contains a two-input look up table that can PLAELM2 0xFFFF0B08 0x0000 R/W be configured to generate any logic output function based on PLAELM3 0xFFFF0B0C 0x0000 R/W two inputs and a flip-flop. This is represented in Figure 51. PLAELM4 0xFFFF0B10 0x0000 R/W PLAELM5 0xFFFF0B14 0x0000 R/W PLAELM6 0xFFFF0B18 0x0000 R/W 0 4 PLAELM7 0xFFFF0B1C 0x0000 R/W A 2 PLAELM8 0xFFFF0B20 0x0000 R/W LOOK-UP TABLE PLAELM9 0xFFFF0B24 0x0000 R/W B 3 PLAELM10 0xFFFF0B28 0x0000 R/W 1 PLAELM11 0xFFFF0B2C 0x0000 R/W 09123-133 PPLLAAEELLMM1123 00xxFFFFFFFF00BB3304 00xx00000000 RR//WW Figure 51. PLA Element PLAELM14 0xFFFF0B38 0x0000 R/W PLAELM15 0xFFFF0B3C 0x0000 R/W In total, 40 GPIO pins are available on the ADuC7124/ADuC7126 for the PLA. These include 16 input pins and 16 output pins that The PLAELMx are Element 0 to Element 15 control registers. must be configured in the GPxCON register as PLA pins before They configure the input and output mux of each element, using the PLA. Note that the comparator output is also included select the function in the look up table, and bypass/use the flip- as one of the 16 input pins. flop (see Table 119 and Table 122). The PLA is configured via a set of user MMRs. The output(s) of Table 119. PLAELMx MMR Bit Descriptions the PLA can be routed to the internal interrupt system, to the Bit Value Description CONVSTART signal of the ADC, to an MMR, or to any of the 16 [31:11] Reserved. PLA output pins. [10:9] Mux 0 control (see Table 122). The two blocks can be interconnected as follows: [8:7] Mux 1 control (see Table 122). 6 Mux 2 control.  Output of Element 15 (Block 1) can be fed back to Input 0 of Set by the user to select the output of Mux 0. Cleared Mux 0 of Element 0 (Block 0). by the user to select the bit value from PLADIN. 5 Mux 3 control.  Output of Element 7 (Block 0) can be fed back to Input 0 of Set by the user to select the input pin of the particular Mux 0 of Element 8 (Block 1). element. Cleared by the user to select the output of Mux 1. Table 117. Element Input/Output1 [4:1] Look-up table control. PLA Block 0 PLA Block 1 0000 0. Element Input Output Element Input Output 0001 NOR. 0 P1.0 P1.7 8 P3.0 P4.0 0010 B AND NOT A. 1 P1.1 P0.4 9 P3.1 P4.1 0011 NOT A. 2 P1.2 P0.5 10 P3.2 P4.2 0100 A AND NOT B. 0101 NOT B. 3 P1.3 P0.6 11 P3.3 P4.3 0110 EXOR. 4 P1.4 P0.7 12 P3.4 P4.4 0111 NAND. 5 P1.5 P2.0 13 P3.5 P4.5 1000 AND. 6 P1.6 P2.1 14 P3.6 P4.6 1001 EXNOR. 7 P0.0 P2.2 15 P3.7 P4.7 1010 B. 1 Not all pins in this table are connected to external pins. However, they may 1011 NOT A OR B. be routed internally via the PLA. See Table 122 for further details. 1100 A. 1101 A OR NOT B. 1110 OR. 1111 1. 0 Mux 4 control. Set by the user to bypass the flip-flop. Cleared by the user to select the flip-flop (cleared by default). Rev. D | Page 83 of 110

ADuC7124/ADuC7126 Data Sheet PLACLK Register PLAIRQ Register Name: PLACLK Name: PLAIRQ Address: 0xFFFF0B40 Address: 0xFFFF0B44 Default Value: 0x00 Default Value: 0x00000000 Access: Read/write Access: Read/write PLACLK is the clock selection for the flip-flops of Block 0 and PLAIRQ enables IRQ0 and/or IRQ1 and selects the source Block 1. Note that the maximum frequency when using the of the IRQ. GPIO pins as the clock input for the PLA blocks is 41.78 MHz. Table 121. PLAIRQ MMR Bit Descriptions Table 120. PLACLK MMR Bit Descriptions Bit Value Description Bit Value Description [15:13] Reserved. 7 Reserved. 12 PLA IRQ1 enable bit. [6:4] Block 1 clock source selection. Set by the user to enable IRQ1 output from PLA. 000 GPIO clock on P0.5. Cleared by the user to disable IRQ1 output 001 GPIO clock on P0.0. from PLA. 010 GPIO clock on P0.7. [11:8] PLA IRQ1 source. 011 HCLK. 0000 PLA Element 0. 100 OCLK (32.768 kHz). 0001 PLA Element 1. 101 Timer1 overflow. 1111 PLA Element 15. 110 UCLK. [7:5] Reserved. 111 Internal 32,768 oscillator. 4 PLA IRQ0 enable bit. 3 Reserved. Set by the user to enable IRQ0 output from [2:0] Block 0 clock source selection. PLA. 000 GPIO clock on P0.5. Cleared by the user to disable IRQ0 output 001 GPIO clock on P0.0. from PLA. 010 GPIO clock on P0.7. [3:0] PLA IRQ0 source. 011 HCLK. 0000 PLA Element 0. 100 OCLK (32.768 kHz). 0001 PLA Element 1. 101 Timer1 overflow. 1111 PLA Element 15. Other Reserved. Table 122. Feedback Configuration Bit Value PLAELM0 PLAELM1 to PLAELM7 PLAELM8 PLAELM9 to PLAELM15 [10:9] 00 Element 15 Element 0 Element 7 Element 8 01 Element 2 Element 2 Element 10 Element 10 10 Element 4 Element 4 Element 12 Element 12 11 Element 6 Element 6 Element 14 Element 14 [8:7] 00 Element 1 Element 1 Element 9 Element 9 01 Element 3 Element 3 Element 11 Element 11 10 Element 5 Element 5 Element 13 Element 13 11 Element 7 Element 7 Element 15 Element 15 Rev. D | Page 84 of 110

Data Sheet ADuC7124/ADuC7126 PLAADC Register Table 124. PLADIN MMR Bit Descriptions Name: PLAADC Bit Description [31:16] Reserved. Address: 0xFFFF0B48 [15:0] Input bit to Element 15 to Element 0. Default Value: 0x00000000 PLADOUT Register Access: Read/write Name: PLADOUT PLAADC is the PLA source for the ADC start conversion signal. Address: 0xFFFF0B50 Table 123. PLAADC MMR Bit Descriptions Default Value: 0x00000000 Bit Value Description Access: Read only [31:5] Reserved. 4 ADC start conversion enable bit. PLADOUT is a data output MMR for PLA. This register is Set by the user to enable ADC start always updated. conversion from PLA. Cleared by the user to disable ADC start Table 125. PLADOUT MMR Bit Descriptions conversion from PLA. Bit Description [3:0] ADC start conversion source. [31:16] Reserved. 0000 PLA Element 0. [15:0] Output bit from Element 15 to Element 0. 0001 PLA Element 1. 1111 PLA Element 15. PLALCK Register Name: PLALCK PLADIN Register Address: 0xFFFF0B54 Name: PLADIN Default Value: 0x00 Address: 0xFFFF0B4C Access: Write only Default Value: 0x00000000 PLALCK is a PLA lock option. Bit 0 is written only once. When Access: Read/write set, it does not allow modification of any of the PLA MMRs, PLADIN is a data input MMR for PLA. except PLADIN. A PLA tool is provided in the development system to easily configure the PLA. Rev. D | Page 85 of 110

ADuC7124/ADuC7126 Data Sheet PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM Bit Description Comments 21 PLA IRQ0 PLA Block 0 IRQ bit. There are 25 interrupt sources on the ADuC7124/ADuC7126 22 XIRQ2 (GPIO IRQ2 ) External Interrupt 2. that are controlled by the interrupt controller. All interrupts 23 XIRQ3 (GPIO IRQ3) External Interrupt 3. are generated from the on-chip peripherals, except for the 24 PLA IRQ1 PLA Block 1 IRQ bit. software interrupt (SWI), which is programmable by the user. 25 PWM PWM trip interrupt source bit. The ARM7TDMI CPU core recognizes interrupts as one of IRQ two types: a normal interrupt request (IRQ) and a fast interrupt request (FIQ). All the interrupts can be masked separately. The IRQ is the exception signal to enter the IRQ mode of the The control and configuration of the interrupt system is processor. It services general-purpose interrupt handling of managed through a number of interrupt-related registers. The internal and external events. bits in each IRQ and FIQ register represent the same interrupt All 32 bits are logically OR’ed to create a single IRQ signal to the source as described in Table 126. ARM7TDMI core. Descriptions of the four 32-bit registers The ADuC7124/ADuC7126 contain a vectored interrupt control- dedicated to IRQ follow. ler (VIC) that supports nested interrupts up to eight levels. The IRQSTA Register VIC also allows the programmer to assign priority levels to all IRQSTA is a read-only register that provides the current-enabled interrupt sources. Interrupt nesting must be enabled by setting IRQ source status (effectively a logic AND of the IRQSIG and the ENIRQN bit in the IRQCONN register. A number of extra IRQEN bits). When set to 1, that source generates an active IRQ MMRs are used when the full-vectored interrupt controller is request to the ARM7TDMI core. There is no priority encoder enabled. or interrupt vector generation. This function is implemented in IRQSTA/FIQSTA should be saved immediately upon entering software in a common interrupt handler routine. the interrupt service routine (ISR) to ensure that all valid IRQSTA Register interrupt sources are serviced. Name: IRQSTA Table 126. IRQ/FIQ MMRs Bit Descriptions Bit Description Comments Address: 0xFFFF0000 0 All interrupts OR’ed This bit is set if any FIQ is active. Default Value: 0x00000000 (FIQ only) 1 Software interrupt User programmable interrupt Access: Read only source. 2 Timer0 General-Purpose Timer 0. IRQSIG Register 3 Timer1 General-Purpose Timer 1. IRQSIG reflects the status of the various IRQ sources. If a periph- 4 Timer2 or wake-up General-Purpose Timer 2 or eral generates an IRQ signal, the corresponding bit in the timer wake-up timer. IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear 5 Timer3 or watchdog General-Purpose Timer 3 or when the interrupt in the particular peripheral is cleared. All timer watchdog timer. IRQ sources can be masked in the IRQEN MMR. IRQSIG is 6 Flash Control 0 Flash controller for Block 0 read only. This register should not be used in an interrupt interrupt. service routine for determining the source of an IRQ exception; 7 Flash Control 1 Flash controller for Block 1 interrupt. IRQSTA should only be used for this purpose. 8 ADC ADC interrupt source bit. IRQSIG Register 9 UART0 UART0 interrupt source bit. Name: IRQSIG 10 UART1 UART1 interrupt source bit. 11 PLL lock PLL lock bit. Address: 0xFFFF0004 12 I2C0 master IRQ I2C master interrupt source bit. 13 I2C0 slave IRQ I2C slave interrupt source bit. Default Value: 0x00000000 14 I2C1 master IRQ I2C master interrupt source bit. Access: Read only 15 I2C1 slave IRQ I2C slave interrupt source bit. 16 SPI SPI interrupt source bit. 17 XIRQ0 (GPIO IRQ0 ) External Interrupt 0. 18 Comparator Voltage comparator source bit. 19 PSM Power supply monitor. 20 XIRQ1 (GPIO IRQ1) External Interrupt 1. Rev. D | Page 86 of 110

Data Sheet ADuC7124/ADuC7126 IRQEN Register Likewise, a bit set to 1 in IRQEN clears, as a side effect, the same bit in FIQEN. An interrupt source can be disabled in both IRQEN provides the value of the current enable mask. When a the IRQEN and FIQEN masks. bit is set to 1, the corresponding source request is enabled to create an IRQ exception. When a bit is set to 0, the correspond- FIQSIG ing source request is disabled or masked, which does not create FIQSIG reflects the status of the different FIQ sources. If a an IRQ exception. The IRQEN register cannot be used to peripheral generates an FIQ signal, the corresponding bit in disable an interrupt. the FIQSIG is set; otherwise, it is cleared. The FIQSIG bits are IRQEN Register cleared when the interrupt in the particular peripheral is cleared. All FIQ sources can be masked in the FIQEN MMR. Name: IRQEN FIQSIG is read only. Address: 0xFFFF0008 FIQSIG Register Default Value: 0x00000000 Name: FIQSIG Access: Read/write Address: 0xFFFF0104 IRQCLR Register Default Value: 0x00000000 IRQCLR is a write-only register that allows the IRQEN register Access: Read only to clear to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the IRQEN register without FIQEN affecting the remaining bits. The pair of registers, IRQEN and FIQEN provides the value of the current enable mask. When a IRQCLR, allow independent manipulation of the enable mask bit is set to 1, the corresponding source request is enabled to without requiring an atomic read-modify-write. create an FIQ exception. When a bit is set to 0, the correspond- This register should be used to disable an interrupt source only ing source request is disabled or masked, which does not create during the following conditions: an FIQ exception. The FIQEN register cannot be used to disable an • In the interrupt sources interrupt service routine. interrupt. • When the peripheral is temporarily disabled by its own FIQEN Register control register. Name: FIQEN This register should not be used to disable an IRQ source if that Address: 0xFFFF0108 IRQ source has an interrupt pending or may have an interrupt pending. Default Value: 0x00000000 IRQCLR Register Access: Read/write Name: IRQCLR FIQCLR Address: 0xFFFF000C FIQCLR is a write-only register that allows the FIQEN register Default Value: 0x00000000 to clear to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the FIQEN register without Access: Write only affecting the remaining bits. The pair of registers, FIQEN and FIQCLR, allows independent manipulation of the enable mask FAST INTERRUPT REQUEST (FIQ) without requiring an atomic read-modify-write. The fast interrupt request (FIQ) is the exception signal to enter This register should be used to disable an interrupt source only the FIQ mode of the processor. It is provided to service data during the following conditions: transfer or communication channel tasks with low latency. The FIQ interface is identical to the IRQ interface and provides the • In the interrupt sources interrupt service routine. second level interrupt (highest priority). Four 32-bit registers • The peripheral is temporarily disabled by its own control are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA. register. Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ This register should not be used to disable an IRQ source if that signal to the core and to Bit 0 of both the FIQ and IRQ registers IRQ source has an interrupt pending or may have an interrupt (FIQ source). pending. The logic for FIQEN and FIQCLR does not allow an interrupt source to be enabled in both IRQ and FIQ masks. A bit set to 1 in FIQEN clears, as a side effect, the same bit in IRQEN. Rev. D | Page 87 of 110

ADuC7124/ADuC7126 Data Sheet FIQCLR Register PROGRAMMABLE PRIORITY PER INTERRUT (IRQP0/IRQP1/IRQP2/IRQP3) Name: FIQCLR Address: 0xFFFF010C IRQ_SOURCE INTERNAL POINTER ARBITER FUNCTION Default Value: 0x00000000 FIQ_SOURCE LOGIC (IRQVEC) Access: Write only INTERRUPT VECTOR FIQSTA FIQSTA is a read-only register that provides the current enabled BITS[31:23] BITS[22:7] BITS[6:2] BITS[1:0] FFIIQQE sNou brcites )s.t aWtuhse (ne fsfeetc ttoiv 1el,y t haa lto sgoicu rAcNe gDe noef rtahtee sF aInQ SaIcGtiv aen FdI Q UNUSED (IRQBASE) APHCRITGIIOVHREE ISITRTYQ LSBs 09123-054 request to the ARM7TDMI core. There is no priority encoder Figure 52. Interrupt Structure or interrupt vector generation. This function is implemented in VECTORED INTERRUPT CONTROLLER (VIC) software in a common interrupt handler routine. The ADuC7124/ADuC7126 incorporate an enhanced interrupt FIQSTA Register control system or (vectored interrupt controller). The vectored Name: FIQSTA interrupt controller for IRQ interrupt sources is enabled by set- ting Bit 0 of the IRQCONN register. Similarly, Bit 1 of IRQCONN Address: 0xFFFF0100 enables the vectored interrupt controller for the FIQ interrupt Default Value: 0x00000000 sources. The vectored interrupt controller provides the following enhancements to the standard IRQ/FIQ interrupts: Access: Read only  Vectored interrupts—allows a user to define separate Programmed Interrupts interrupt service routine addresses for every interrupt source. This is achieved by using the IRQBASE and Because the programmed interrupts are not maskable, they are IRQVEC registers. controlled by another register (SWICFG) that writes into the IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG  IRQ/FIQ interrupts—can be nested up to eight levels registers at the same time. depending on the priority settings. An FIQ still has a higher priority than an IRQ. Therefore, if the VIC is The 32-bit register dedicated to software interrupt is SWICFG enabled for both the FIQ and IRQ and prioritization is (described in Table 127). This MMR allows control of a pro- maximized, it is possible to have 16 separate interrupt grammed source interrupt. levels. Table 127. SWICFG MMR Bit Descriptions  Programmable interrupt priorities—using the IRQP0 to Bit Description IRQP3 registers, an interrupt source can be assigned an interrupt priority level value between 0 and 7. [31:3] Reserved. 2 Programmed interrupt FIQ. Setting/clearing this bit VIC MMRs corresponds to setting/clearing Bit 1 of FIQSTA and FIQSIG. IRQBASE Register 1 Programmed interrupt IRQ. Setting/clearing this bit The vector base register, IRQBASE, is used to point to the start corresponds to setting/clearing Bit 1 of IRQSTA and address of memory used to store 32 pointer addresses. These IRQSIG. pointer addresses are the addresses of the individual interrupt 0 Reserved. service routines. Any interrupt signal must be active for at least the minimum Name: IRQBASE interrupt latency time to be detected by the interrupt controller and to be detected by the user in the IRQSTA/FIQSTA register. Address: 0xFFFF0014 Default Value: 0x00000000 Access: Read/write Table 128. IRQBASE MMR Bit Descriptions Bit Type Initial Value Description [31:16] Read only Reserved Always read as 0. [15:0] R/W 0 Vector base address. Rev. D | Page 88 of 110

Data Sheet ADuC7124/ADuC7126 IRQVEC Register Bit Name Description The IRQ interrupt vector register, IRQVEC points to a memory [18:16] T2PI A priority level of 0 to 7 can be set for Timer2. address containing a pointer to the interrupt service routine of 15 Reserved. the currently active IRQ. This register should only be read when [14:12] T1PI A priority level of 0 to 7 can be set for an IRQ occurs and IRQ interrupt nesting has been enabled by Timer1. setting Bit 0 of the IRQCONN register. 11 Reserved. Name: IRQVEC [10:8] T0PI A priority level of 0 to 7 can be set for Timer0. Address: 0xFFFF001C 7 Reserved. [6:4] SWINTP A priority level of 0 to 7 can be set for the Default Value: 0x00000000 software interrupt source. Access: Read only [3:0] Interrupt 0 cannot be prioritized. IRQP1 Register Table 129. IRQVEC MMR Bit Descriptions Name: IRQP1 Initial Bit Type Value Description Address: 0xFFFF0024 [31:23] R 0 Always read as 0. [22:7] R/W 0 IRQBASE register value. Default Value: 0x00000000 [6:2] R 0 Highest priority source. This is a Access: Read/write value between 0 and 27 represent- ing the possible interrupt sources. For example, if the highest currently Table 131. IRQP1 MMR Bit Descriptions active IRQ is Timer 2, then these bits Bit Name Description are [00100]. 31 Reserved. [1:0] Reser 0 Reserved bits. [30:28] I2C1SPI A priority level of 0 to 7 can be set for the ved I2C1 slave. Priority Registers 27 Reserved. The IRQ interrupt vector register, IRQVEC points to a memory [26:24] I2C1MPI A priority level of 0 to 7 can be set for the I2C1 master. address containing a pointer to the interrupt service routine of 23 Reserved. the currently active IRQ. This register should only be read when an IRQ occurs and IRQ interrupt nesting has been enabled by [22:20] I2C0SPI A priority level of 0 to 7 can be set for the I2C0 slave. setting Bit 0 of the IRQCONN register. 19 Reserved. IRQP0 Register [18:16] I2C0MPI A priority level of 0 to 7 can be set for the Name: IRQP0 I2C 0 master. 15 Reserved. Address: 0xFFFF0020 [14:12] PLLPI A priority level of 0 to 7 can be set for the PLL lock interrupt. Default Value: 0x00000000 11 Reserved. Access: Read/write [10:8] UART1PI A priority level of 0 to 7 can be set for UART1. Table 130. IRQP0 MMR Bit Descriptions 7 Reserved. Bit Name Description [6:4] UART0PI A priority level of 0 to 7 can be set for UART0. 31 Reserved. 5 Reserved. [30:28] Flash1PI A priority level of 0 to 7 can be set for the Flash Block 1 controller interrupt source. [2:0] ADCPI A priority level of 0 to 7 can be set for the ADC interrupt source. 27 Reserved. [26:24] Flash0PI A priority level of 0 to 7 can be set for the Flash Block 0 controller interrupt source. 23 Reserved. [22:20] T3PI A priority level of 0 to 7 can be set for Timer 3. 19 Reserved. Rev. D | Page 89 of 110

ADuC7124/ADuC7126 Data Sheet IRQP2 Register interrupt source priority level. In this default state, an FIQ does have a higher priority than an IRQ. Name: IRQP2 Name: IRQCONN Address: 0xFFFF0028 Address: 0xFFFF0030 Default Value: 0x00000000 Default Value: 0x00000000 Access: Read/write Access: Read/write Table 132. IRQP2 MMR Bit Descriptions Bit Name Description Table 134. IRQCONN MMR Bit Descriptions 31 Reserved. Bit Name Description [30:28] IRQ3PI A priority level of 0 to 7 can be set for IRQ3. 31:2 Reserved. These bits are reserved and should 27 Reserved. not be written to. [26:24] IRQ2PI A priority level of 0 to 7 can be set for IRQ2. 1 ENFIQN Setting this bit to 1 enables nesting of FIQ 23 Reserved. interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. [22:20] PLA0PI A priority level of 0 to 7 can be set for PLA IRQ0. 0 ENIRQN Setting this bit to 1 enables nesting of IRQ interrupts. Clearing this bit means no nesting 19 Reserved. or prioritization of IRQs is allowed. [18:16] IRQ1PI A priority level of 0 to 7 can be set for IRQ1. 15 Reserved. IRQSTAN Register [14:12] PSMPI A priority level of 0 to 7 can be set for the power supply monitor interrupt source. If IRQCONN Bit 0 is asserted and IRQVEC is read, one of the 11 Reserved. IRQSTAN[7:0] bits is asserted. The bit that asserts depends on the priority of the IRQ. If the IRQ is of Priority 0, then Bit 0 [10:8] COMPI A priority level of 0 to 7 can be set for the comparator. asserts, if Priority 1, then Bit 1 asserts, and so on. When a bit is 7 Reserved. set in this register, all interrupts of that priority and lower are [6:4] IRQ0PI A priority level of 0 to 7 can be set for IRQ0. blocked. 3 Reserved. To clear a bit in this register, all bits of a higher priority must be [2:0] SPIPI A priority level of 0 to 7 can be set for SPI. cleared first. It is only possible to clear one bit at a time. For example, if this register is set to 0x09, writing 0xFF changes the IRQP3 Register register to 0x08, and writing 0xFF a second time changes the Name: IRQP3 register to 0x00. Address: 0xFFFF002C Name: IRQSTAN Default Value: 0x00000000 Address: 0xFFFF003C Access: Read/write Default Value: 0x00000000 Table 133. IRQP3 MMR Bit Descriptions Access: Read/write Bit Name Description [31:7] Reserved. Table 135. IRQSTAN MMR Bit Descriptions [6:4] PWMPI A priority level of 0 to 7 can be set for PWM. Bit Name Description 3 Reserved. 31:8 Reserved. These bits are reserved and should not be written to. [2:0] PLA1PI A priority level of 0 to 7 can be set for PLA IRQ1. 7:0 Setting these bits to 1 enables nesting of FIQ interrupts. Clearing these bits means no IRQCONN Register nesting or prioritization of FIQs is allowed. The IRQCONN register is the IRQ and FIQ control register. It contains two active bits: the first to enable nesting and prioritiza- tion of IRQ interrupts and the other to enable nesting and prioritization of FIQ interrupts. If these bits are cleared, FIQs and IRQs can still be used, but it is not possible to nest IRQs or FIQs, nor is it possible to set an Rev. D | Page 90 of 110

Data Sheet ADuC7124/ADuC7126 FIQVEC Register changes the register to 0x08 and writing 0xFF a second time changes the register to 0x00. The FIQ interrupt vector register, FIQVEC, points to a memory address containing a pointer to the interrupt service routine of Name: FIQSTAN the currently active FIQ. This register should be read only when an FIQ occurs and FIQ interrupt nesting has been enabled by Address: 0xFFFF013C setting Bit 1 of the IRQCONN register. Default Value: 0x00000000 Name: FIQVEC Access: Read/write Address: 0xFFFF011C Table 137. FIQSTAN MMR Bit Descriptions Default Value: 0x00000000 Bit Name Description Access: Read only 31:8 Reserved. These bits are reserved and should not be written to. 7:0 Setting this bit to 1 enables nesting of FIQ Table 136. FIQVEC MMR Bit Descriptions interrupts. Clearing this bit means no nesting Initial or prioritization of FIQs is allowed. Bit Type Value Description [31:23] R 0 Always read as 0. External Interrupts and PLA interrupts [22:7] R/W 0 IRQBASE register value. The ADuC7124/ADuC7126 provide up to four external [6:2] 0 Highest priority source. This is a value between 0 and 27, interrupt sources and two PLA interrupt sources. These representing the currently active external interrupts can be individually configured as level or interrupt source. The interrupts are rising/falling edge triggered. listed in Table 126. For example, if the highest currently active FIQ is To enable the external interrupt source or the PLA interrupt Timer2, then these bits are [00100]. source, the appropriate bit must first be set in the FIQEN or [1:0] 0 Reserved. IRQEN register. To select the required edge or level to trigger on, the IRQCONE register must be appropriately configured. FIQSTAN Register To properly clear an edge-based external IRQ interrupt or an If IRQCONN Bit 1 is asserted and FIQVEC is read, one of the edge-based PLA interrupt, set the appropriate bit in the IRQCLRE FIQSTAN[7:0] bits is asserted. The bit that asserts depends on register. the priority of the FIQ. If the FIQ is of Priority 0, Bit 0 asserts, if IRQCONE Register Priority 1, Bit 1 asserts, and so forth. Name: IRQCONE When a bit is set in this register all interrupts of that priority and lower are blocked. Address: 0xFFFF0034 To clear a bit in this register, all bits of a higher priority must be Default Value: 0x00000000 cleared first. It is possible to clear only one bit at a time. For example, if this register is set to 0x09, then writing 0xFF Access: Read/write Table 138. IRQCONE MMR Bit Descriptions Bit Value Name Description [31:12] Reserved. These bits are reserved and should not be written to. [11:10] 11 PLA1SRC[1:0] PLA IRQ1 triggers on falling edge. 10 PLA IRQ1 triggers on rising edge. 01 PLA IRQ1 triggers on low level. 00 PLA IRQ1 triggers on high level. [9:8] 11 IRQ3SRC[1:0] External IRQ3 triggers on falling edge. 10 External IRQ3 triggers on rising edge. 01 External IRQ3 triggers on low level. 00 External IRQ3 triggers on high level. Rev. D | Page 91 of 110

ADuC7124/ADuC7126 Data Sheet Bit Value Name Description [7:6] 11 IRQ2SRC[1:0] External IRQ2 triggers on falling edge. 10 External IRQ2 triggers on rising edge. 01 External IRQ2 triggers on low level. 00 External IRQ2 triggers on high level. [5:4] 11 PLA0SRC[1:0] PLA IRQ0 triggers on falling edge. 10 PLA IRQ0 triggers on rising edge. 01 PLA IRQ0 triggers on low level. 00 PLA IRQ0 triggers on high level. [3:2] 11 IRQ1SRC[1:0] External IRQ1 triggers on falling edge. 10 External IRQ1 triggers on rising edge. 01 External IRQ1 triggers on low level. 00 External IRQ1 triggers on high level. [1:0] 11 IRQ0SRC[1:0] External IRQ0 triggers on falling edge. 10 External IRQ0 triggers on rising edge. 01 External IRQ0 triggers on low level. 00 External IRQ0 triggers on high level. IRQCLRE Register Name: IRQCLRE Address: 0xFFFF0038 Default Value: 0x00000000 Access: Write only Table 139. IRQCLRE MMR Bit Descriptions Bit Name Description [31:25] Reserved. These bits are reserved and should not be written to. 24 PLA1CLRI A 1 must be written to this bit in the PLA IRQ1 interrupt service routine to clear an edge- triggered PLA IRQ1 interrupt. 23 IRQ3CLRI A 1 must be written to this bit in the external IRQ3 interrupt service routine to clear an edge- triggered IRQ3 interrupt. 22 IRQ2CLRI A 1 must be written to this bit in the external IRQ2 interrupt service routine to clear an edge- triggered IRQ2 interrupt. 21 PLA0CLRI A 1 must be written to this bit in the PLA IRQ0 interrupt service routine to clear an edge- triggered PLA IRQ0 interrupt. 20 IRQ1CLRI A 1 must be written to this bit in the external IRQ1 interrupt service routine to clear an edge- triggered IRQ1 interrupt. [19:18] Reserved. These bits are reserved and should not be written to. 17 IRQ0CLRI A 1 must be written to this bit in the external IRQ0 interrupt service routine to clear an edge triggered IRQ0 interrupt. [16:0] Reserved. These bits are reserved and should not be written to. Rev. D | Page 92 of 110

Data Sheet ADuC7124/ADuC7126 TIMERS In normal mode, an IRQ is generated each time the value of the counter reaches zero when counting down. It is also generated The ADuC7124/ADuC7126 have four general-purpose each time the counter value reaches full scale when counting timers/counters. up. An IRQ can be cleared by writing any value to clear the • Timer0 register of that particular timer (TxCLRI). • Timer1 When using an asynchronous clock-to-clock timer, the • Timer2 or wake-up timer interrupt in the timer block can take more time to clear than the time it takes for the code in the interrupt routine to • Timer3 or watchdog timer execute. Ensure that the interrupt signal is cleared before These four timers in their normal mode of operation can be leaving the interrupt service routine. This can be done by either free running or periodic. checking the IRQSTA MMR. In free-running mode, the counter decreases from the maxi- Hr: Min: Sec: 1/128 Format mum value until zero scale is reached and starts again at the Timer 1 and Timer 2 have an Hr: Min: Sec: hundreds format. minimum value. It also increases from the minimum value until To use the timer in Hr: Min: Sec: hundreds format, the full scale is reached and starts again at the maximum value. 32768 kHz clock and prescaler of 256 should be selected. The In periodic mode, the counter decrements/increments from the hundreds field does not represent milliseconds, but 1/128 of a value in the load register (TxLD MMR) until zero/full scale is second (256/32768).The bits representing the hour, minute, reached and starts again at the value stored in the load register. and second are not consecutive in the register. This arrange- ment applies to TxLD and TxVAL when using the Hr: Min: Sec: The timer interval is calculated as follows: hundreds format as set in TxCON[5:4]. See Table 140 for more If the timer is set to count down, then details. (TxLD)×Prescaler Interval= Table 140. Hr: Min: Sec: Hundreds Format SourceClock Bit Value Description If the timer is set to count up, then [31:24] 0 to 23 or 0 to 255 hours (FullScale -TxLD)×Prescaler [23:22] 0 reserved Interval= [21:16] 0 to 59 minutes SourceClock [15:14] 0 reserved The value of a counter can be read at any time by accessing [13:8] 0 to 59 seconds its value register (TxVAL). Note that, when a timer is being 7 0 reserved clocked from a clock other than a core clock, an incorrect [6:0] 0 to 127 1/128 of second value may be read (due to asynchronous clock system). In this configuration, TxVAL should always be read twice. If the two readings are different, it should be read a third time to obtain the correct value. Timers are started by writing in the control register of the corresponding timer (TxCON). Rev. D | Page 93 of 110

ADuC7124/ADuC7126 Data Sheet Timer0 (RTOS Timer) T0VAL Register Timer0 is a general-purpose, 16-bit timer (count down) with a Name: T0VAL programmable prescaler. The prescaler source is the core clock frequency (HCLK) and can be scaled by a factor of 1, 16, or 256. Address: 0xFFFF0304 Timer0 can be used to start ADC conversions, as shown in the Default Value: 0xFFFF block diagram in Figure 53. Access: Read only 16-BIT LOAD T0VAL is a 16-bit read-only register representing the current 32.768kHz OSCILLATOR state of the counter. UCLK ÷P1R, 1E6S,C OARL E25R6 D16O-BWINT TIMER0 IRQ COUNTER ADC CONVERSION T0CON Register HCLK TVIAMLEURE0 09123-036 Name: T0CON Figure 53. Timer0 Block Diagram Address: 0xFFFF0308 The Timer0 interface consists of four MMRs: T0LD, T0VAL, Default Value: 0x0000 T0CON, and T0CLRI. Access: Read/write T0LD Register Name: T0LD T0CON is the configuration MMR described in Table 141. Address: 0xFFFF0300 Default Value: 0x0000 Access: Read/write T0LD is a 16-bit load register. Rev. D | Page 94 of 110

Data Sheet ADuC7124/ADuC7126 Table 141. T0CON MMR Bit Descriptions 32-BIT LOAD Bit Value Description 32kHz OSCILLATOR [31:8] Reserved. HCLK PRESCALER 32-BIT UCLK ÷1, 16, 256, UP/DOWN TIMER1 IRQ 7 Timer0 enable bit. P1.0 OR 32,768 COUNTER ADC CONVERSION Set by the user to enable Timer0. TIMER1 Cleared by the user to disable Timer0 by VALUE default. 6 Timer0 mode. IRQ[19:0] CAPTURE 09123-137 Set by the user to operate in periodic mode. Figure 54. Timer1 Block Diagram Cleared by the user to operate in free-running mode. Default mode. [5:4] Clock select bits. The Timer1 interface consists of five MMRs: T1LD, T1VAL, 00 HCLK. T1CON, T1CLRI, and T1CAP. 01 UCLK. T1LD Register 10 32.768 kHz. Name: T1LD 11 Reserved. [3:2] Prescale. Address: 0xFFFF0320 00 Core clock/1. Default value. 01 Core clock/16. Default Value: 0x00000000 10 Core clock/256. Access: Read/write 11 Undefined. Equivalent to 00. [1:0] Reserved. T1LD is a 32-bit load register. T0CLRI Register T1VAL Register Name: T0CLRI Name: T1VAL Address: 0xFFFF030C Address: 0xFFFF0324 Default Value: 0xFF Default Value: 0xFFFFFFFF Access: Write only Access: Read only T0CLRI is an 8-bit register. Writing any value to this register T1VAL is a 32-bit read-only register that represents the current clears the interrupt. state of the counter. Timer1 (General-Purpose Timer) T1CON Register Timer1 is a general-purpose, 32-bit timer (count down or count Name: T1CON up) with a programmable prescaler. The source can be the 32 kHz external crystal, the undivided system, the core clock, or P1.1 Address: 0xFFFF0328 (maximum frequency 41.78 MHz). This source can be scaled by Default Value: 0x0000 a factor of 1, 16, 256, or 32,768. The counter can be formatted as a standard 32-bit value or as Access: Read/write hours: minutes: seconds: hundredths. T1CON is the configuration MMR described in Table 142. Timer1 has a capture register (T1CAP) that can be triggered by a selected IRQ source initial assertion. This feature can be used to determine the assertion of an event more accurately than the precision allowed by the RTOS timer when the IRQ is serviced. Timer1 can be used to start ADC conversions. Rev. D | Page 95 of 110

ADuC7124/ADuC7126 Data Sheet T1CAP Register Table 142. T1CON MMR Bit Descriptions Bit Value Description Name: T1CAP [31:18] Reserved. Address: 0xFFFF0330 17 Event select bit. Set by user to enable time capture of an event. Default Value: 0x00000000 Cleared by the user to disable time capture of an event. Access: Read [16:12] Event select range, 0 to 25. These events are as described in Table 126. All events are offset by T1CAP is a 32-bit register. It holds the value contained in two, that is, Event 2 in Table 126 becomes Event T1VAL when a particular event occurrs. This event must be 0 for the purposes of Timer0. selected in T1CON. [11:9] Clock select. Timer2 (Wake-Up Timer) 000 Core clock (41 MHz/2CD). 001 32.768 kHz. Timer2 is a 32-bit wake-up timer, count down or count up, with 010 UCLK. a programmable prescaler. The prescaler is clocked directly from one of four clock sources, including the core clock (default selec- 011 P1.0 raising edge triggered. tion), the internal 32.768 kHz oscillator, the external 32.768 kHz 8 Count up. watch crystal, or the PLL undivided clock. The selected clock Set by the user for Timer1 to count up. Cleared by the user for Timer1 to count down source can be scaled by a factor of 1, 16, 256, or 32,768. The by default. wake-up timer continues to run when the core clock is disabled. 7 Timer1 enable bit. This gives a minimum resolution of 22 ns when the core is Set by the user to enable Timer1. operating at 41.78 MHz and with a prescaler of 1. Capture of Cleared by the user to disable Timer1 by default. the current timer value is enabled if the Timer2 interrupt is 6 Timer1 mode. enabled via IRQEN[4] (see Table 126). Set by the user to operate in periodic mode. The counter can be formatted as a plain 32-bit value or as Cleared by the user to operate in free-running hours: minutes: seconds: hundredths. mode. Default mode. [5:4] Format. Timer2 reloads the value from T2LD either when Timer2 00 Binary. overflows or immediately when T2CLRI is written. 01 Reserved. The Timer2 interface consists of four MMRs, shown in 10 Hr: min: sec: hundredths (23 hours to 0 hour). Table 143. 11 Hr: min: sec: hundredths (255 hours to 0 hour). [3:0] Prescale. Table 143. Timer2 Interface Registers Register Description 0000 Source clock/1. T2LD 32-bit register. Holds 32-bit unsigned integers. 0100 Source clock/16. T2VAL 32-bit register. Holds 32-bit unsigned integers. This 1000 Source clock/256. register is read only. 1111 Source clock/32,768. T2CLRI 8-bit register. Writing any value to this register clears T1CLRI Register the Timer2 interrupt. T2CON Configuration MMR. Name: T1CLRI Timer2 Load Registers Address: 0xFFFF032C Name: T2LD Default Value: 0xFF Address: 0xFFFF0340 Access: Write only Default Value: 0x00000 T1CLRI is an 8-bit register. Writing any value to this register Access: Read/write clears the Timer1 interrupt. T2LD is a 32-bit register, which holds the 32-bit value that is loaded into the counter. Rev. D | Page 96 of 110

Data Sheet ADuC7124/ADuC7126 Timer2 Clear Register Timer2 Value Register Name: T2CLRI Name: T2VAL Address: 0xFFFF034C Address: 0xFFFF0344 Default Value: 0x00 Default Value: 0x0000 Access: Write only Access: Read only This 8-bit write-only MMR is written (with any value) by user T2VAL is a 32-bit register that holds the current value of Timer2. code to refresh (reload) Timer2. Timer2 Control Register Name: T2CON Address: 0xFFFF0348 Default Value: 0x0000 Access: Read/write This 32-bit MMR configures the mode of operation for Timer2. Table 144. T2CON MMR Bit Descriptions Bit Value Description [31:11] Reserved. 10:9] Clock source select. 00 External 32.768 kHz watch crystal (default). 01 External 32.768 kHz watch crystal. 10 Internal 32.768 kHz oscillator. 11 HCLK. 8 Count up. Set by the user for Timer2 to count up. Cleared by the user for Timer2 to count down (default). 7 Timer2 enable bit. Set by the user to enable Timer2. Cleared by the user to disable Timer2 (default). 6 Timer2 mode. Set by the user to operate in periodic mode. Cleared by the user to operate in free-running mode (default). [5:4] Format. 00 Binary (default). 01 Reserved. 10 Hr: min: sec: hundredths (23 hours to 0 hours). 11 Hr: min: sec: hundredths (255 hours to 0 hours). [3:0] Prescaler. 0000 Source clock/1 (default). 0100 Source clock/16. 1000 Source clock/256. 1111 Source clock/32,768. Rev. D | Page 97 of 110

ADuC7124/ADuC7126 Data Sheet Timer3 (Watchdog Time) T3VAL Register Timer3 has two modes of operation: normal mode and Name: T3VAL watchdog mode. The watchdog timer is used to recover from Address: 0xFFFF0364 an illegal software state. Once enabled, it requires periodic servicing to prevent it from forcing a processor reset. Default Value: 0xFFFF Normal Mode Access: Read only Timer3 in normal mode is identical to Timer0, except for the clock source and the count-up functionality. The clock source is T3VAL is a 16-bit read-only register that represents the current 32 kHz from the PLL and can be scaled by a factor of 1, 16, or state of the counter. 256 (see Figure 55). T3CON Register 16-BIT Name: T3CON LOAD Address: 0xFFFF0368 WATCHDOG 32.768kHz PRESCALER UP1/6D-BOIWTN RESET ÷ 1, 16 OR 256 COUNTER TIMER3 IRQ Default Value: 0x0000 TVIAMLEURE3 09123-037 Access: Read/write Figure 55. Timer3 Block Diagram T3CON is the configuration MMR described in Table 145. Watchdog Mode Table 145. T3CON MMR Bit Descriptions Watchdog mode is entered by setting Bit 5 in the T3CON MMR. Bit Value Description Timer3 decreases from the value present in the T3LD register [31:9] Reserved. until 0 is reached. T3LD is used as the timeout. The maximum 8 Count up. timeout can be 512 sec using the prescaler/256 and full scale in Set by the user for Timer3 to count up. Cleared by the user for Timer3 to count down T3LD. Timer3 is clocked by the internal 32 kHz crystal when by default. operating in the watchdog mode. Note that, to enter watchdog 7 Timer3 enable bit. mode successfully, Bit 5 in the T3CON MMR must be set after Set by the user to enable Timer3. writing to the T3LD MMR. Cleared by the user to disable Timer3 by If the timer reaches 0, a reset or an interrupt occurs, depending default. on Bit 1 in the T3CON register. To avoid reset or interrupt, any 6 Timer3 mode. value must be written to T3CLRI before the expiration period. Set by the user to operate in periodic mode. Cleared by the user to operate in free-running This reloads the counter with T3LD and begins a new timeout mode (default mode). period. 5 Watchdog mode enable bit. When watchdog mode is entered, T3LD and T3CON are write- Set by the user to enable watchdog mode. protected. These two registers cannot be modified until a reset Cleared by the user to disable watchdog clears the watchdog enable bit, which causes Timer3 to exit mode by default. watchdog mode. 4 Secure clear bit. Set by the user to use the secure clear option. The Timer3 interface consists of four MMRs: T3LD, T3VAL, Cleared by the user to disable the secure clear T3CON, and T3CLRI. option by default. T3LD Register [3:2] Prescale. Name: T3LD 00 Source clock/1 by default. 01 Source clock/16. Address: 0xFFFF0360 10 Source clock/256. 11 Undefined. Equivalent to 00. Default Value: 0x0000 1 Watchdog IRQ option bit. Access: Read/write Set by the user to produce an IRQ instead of a reset when the watchdog reaches 0. T3LD is a 16-bit load register. Cleared by the user to disable the IRQ option. 0 Reserved. Rev. D | Page 98 of 110

Data Sheet ADuC7124/ADuC7126 T3CLRI Register The memory interface can address up to four 128 kB of asynchronous memory (SRAM or/and EEPROM). Name: T3CLRI The pins required for interfacing to an external memory are Address: 0xFFFF036C shown in Table 146. Default Value: 0x00 Table 146. External Memory Interfacing Pins Access: Write only Pin Function AD[15:0] Address/data bus. T3CLRI is an 8-bit register. Writing any value to this register on A16 Extended addressing for 8-Bit memory only. successive occassions clears the Timer3 interrupt in normal MS[3:0] Memory select. mode or resets a new timeout period in watchdog mode. WS Write strobe. Note that the user must perform successive writes to this RS Read strobe. register to ensure resetting the timeout period. AE Address latch enable. BHE, BLE Byte write capability. Secure Clear Bit (Watchdog Mode Only) The secure clear bit is provided for a higher level of protection. There are four external memory regions available as described When set, a specific sequential value must be written to T3CLRI in Table 147. Associated with each region are the MS[3:0] pins. to avoid a watchdog reset. The value is a sequence generated These signals allow access to the particular region of external by the 8-bit linear feedback shift register (LFSR) polynomial = memory. The size of each memory region can be 128 kB maxi- X + X + X + X + 1, as shown in Figure 56. mum, 64 k × 16 or 128 kB × 8. To access 128 kB with an 8-bit 8 6 5 memory, an extra address line (A16) is provided (see the example in Figure 57). The four regions are configured independently. Q D Q D Q D Q D Q D Q D Q D Q D CLOCK 7 6 5 4 3 2 1 0 09123-038 TAdabdlree 1ss4 7S.t aMrte mory ARdedgiroensss End Contents Figure 56. 8-Bit LFSR 0x10000000 0x1000FFFF External Memory 0 The initial value or seed is written to T3CLRI before entering 0x20000000 0x2000FFFF External Memory 1 watchdog mode. After entering watchdog mode, a write to 0x30000000 0x3000FFFF External Memory 2 T3CLRI must match this expected value. If it matches, the LFSR 0x40000000 0x4000FFFF External Memory 3 is advanced to the next state when the counter reload occurs. If Each external memory region can be controlled through three it fails to match the expected state, a reset is immediately MMRs: XMCFG, XMxCON, and XMxPAR. generated, even if the count has not yet expired. ADuC7126 EEPROM The value 0x00 should not be used as an initial seed due to the 64k × 16-BIT properties of the polynomial. The value 0x00 is always guaran- A16 teed to force an immediate reset. The value of the LFSR cannot AD15:AD0 D0:D15 be read; it must be tracked/generated in software. LATCH A0:A15 Example of a sequence: AE 1. Enter initial seed, 0xAA, in T3CLRI before starting Timer3 MS0 CS MS1 in watchdog mode. WS WE 2. Enter 0xAA in T3CLRI; Timer3 is reloaded. RS OE 3. Enter 0x37 in T3CLRI; Timer3 is reloaded. RAM 4. Enter 0x6E in T3CLRI; Timer3 is reloaded. 128k × 8-BIT D0:D7 5. Enter 0x66. 0xDC was expected; the watchdog resets the chip. A16 EXTERNAL MEMORY INTERFACING A0:A15 CS Tinhteer AfaDceu. CT7h1e2 e4x/tAerDnuaCl m71e2m6 ofreyat iunrtee rafna ceex treerqnuailr ems eam laorrgye r WOEE 09123-039 number of pins. The XMCFG MMR must be set to 1 to use the Figure 57. Interfacing to External EEPROM/RAM external port. Although 32-bit addresses are supported internally, only the lower 16 bits of the address are on external pins. Rev. D | Page 99 of 110

ADuC7124/ADuC7126 Data Sheet XMCFG Register XMxPAR are registers that define the protocol used for Name: XMCFG accessing the external memory for each memory region. Address: 0xFFFFF000 Table 151. XMxPAR MMR Bit Descriptions Bit Description Default Value: 0x00 15 Enable byte write strobe. This bit is only used for two 8-bit memory blocks sharing the same memory region. Access: Read/write Set by the user to gate the A0 output with the WS XMCFG is set to 1 to enable external memory access. This must output. This allows byte write capability without using BHE and BLE signals. be set to 1 before any port pins can function as external memory Cleared by user to use BHE and BLE signals. access pins. The port pins must also be individually enabled via the GPxCON MMR. [14:12] Number of wait states on the address latch enable strobe. 11 Reserved. Table 148. XMxCON Registers 10 Extra address hold time. Name Address Default Value Access Set by the user to disable extra hold time. XM0CON 0xFFFFF010 0x00 R/W Cleared by the user to enable one clock cycle of hold XM1CON 0xFFFFF014 0x00 R/W on the address in read and write. XM2CON 0xFFFFF018 0x00 R/W 9 Extra bus transition time on read. XM3CON 0xFFFFF01C 0x00 R/W Set by the user to disable extra bus transition time. Cleared by the user to enable one extra clock before XMxCON are the control registers for each memory region. and after the read strobe (RS). They allow the enabling/disabling of a memory region and 8 Extra bus transition time on write. control the data bus width of the memory region. Set by the user to disable extra bus transition time. Cleared by the user to enable one extra clock before and Table 149. XMxCON MMR Bit Descriptions after the write strobe (WS). Bit Description [7:4] Number of write wait states. 1 Selects data bus width. Select the number of wait states added to the length of Set by the user to select a 16-bit data bus. the WS pulse. 0x0 is 1 clock; 0xF is 16 clock cycles (default Cleared by the user to select an 8-bit data bus. value). 0 Enables memory region. [3:0] Number of read wait states. Set by the user to enable memory region. Select the number of wait states added to the length of Cleared by the user to disable the memory region. the RS pulse. 0x0 is 1 clock; 0xF is 16 clock cycles (default value). Table 150. XMxPAR Registers Figure 58, Figure 59, Figure 60, and Figure 61 show the timing Name Address Default Value Access for a read cycle, a read cycle with address hold and bus turn XM0PAR 0xFFFFF020 0x70FF R/W cycles, a write cycle with address and write hold cycles, and a XM1PAR 0xFFFFF024 0x70FF R/W write cycle with wait sates, respectively. XM2PAR 0xFFFFF028 0x70FF R/W XM3PAR 0xFFFFF02C 0x70FF R/W Rev. D | Page 100 of 110

Data Sheet ADuC7124/ADuC7126 MCLK AD[15:0] ADDRESS DATA MSx AE RS 09123-040 Figure 58. External Memory Read Cycle MCLK AD[15:0] ADDRESS DATA EXTRA ADDRESS HOLD TIME XMxPAR(BIT 10) MSx AE RS BUS TUR(BNI TO U9)T CYCLE BUS TUR(BNI TO U9)T CYCLE 09123-041 Figure 59. External Memory Read Cycle with Address Hold and Bus Turn Cycles Rev. D | Page 101 of 110

ADuC7124/ADuC7126 Data Sheet MCLK AD[15:0] ADDRESS DATA EXTRA ADDRESS HOLD TIME (BIT 10) MSx AE WS WRAINTDE DHA(OBTLIATD C8A)YDCDLREESSS WRAINTDE DHA(OBTLIATD C8A)YDCDLREESSS 09123-042 Figure 60. External Memory Write Cycle with Address and Write Hold Cycles MCLK AD[15:0] ADDRESS DATA MSx AE 1 ADDRESS WAIT STATE (BIT 14 TO BIT 12) WS 1 WRITE(B SITT R7O TBOE B WITA 4IT) STATE 09123-043 Figure 61. External Memory Write Cycle with Wait States Rev. D | Page 102 of 110

Data Sheet ADuC7124/ADuC7126 HARDWARE DESIGN CONSIDERATIONS POWER SUPPLIES Finally, note that the analog and digital ground pins on the ADuC7124/ADuC7126 must be referenced to the same system The ADuC7124/ADuC7126 operational power supply voltage ground reference point at all times. range is 2.7 V to 3.6 V. Separate analog and digital power supply IOV Supply Sensitivity pins (AV and IOV , respectively) allow AV to be kept DD DD DD DD relatively free of noisy digital signals often present on the The IOVDD supply is sensitive to high frequency noise because it system IOV line. In this mode, the part can also operate with is the supply source for the internal oscillator and PLL circuits. DD split supplies; that is, it can use different voltage levels for each When the internal PLL loses lock, the clock source is removed supply. For example, the system can be designed to operate by a gating circuit from the CPU, and the ARM7TDMI core with an IOV voltage level of 3.3 V while the AV level can be stops executing code until the PLL regains lock. This feature DD DD at 3 V or vice versa. A typical split supply configuration is ensures that no flash interface timings or ARM7TDMI timings shown in Figure 62. are violated. DIGITAL ANALOG Typically, frequency noise greater than 50 kHz and 50 mV p-p SUPPLY SUPPLY on top of the supply causes the core to stop working. +– 10µF ADuC7124/ 10µF +– ADuC7126 If decoupling values recommended in the Power Supplies section do not sufficiently dampen all noise sources below AVDD IOVDD 50 mV on IOVDD, a filter such as the one shown in Figure 64 is DACVDD recommended. 0.1µF 0.1µF 1µH GNDREF DACGND DIGITAL + 10µF ADuC7124/ IOGND AGND 09123-044 SUPPLY – IOVADDDuC7126 Figure 62. External Dual Supply Connections 0.1µF 0.1µF As an alternative to providing two separate power supplies, the user can reduce noise on AV by placing a small series resistor DD aAnVdD/oDr s feeprarirtaet beleya dto b gertwoueennd .A AVnD De xanamd IpOleV oDfD t ahnisd ctohnenfi gduercaotuiopnlin igs IOGND 09123-087 shown in Figure 63. With this configuration, other analog circuitry Figure 64. Recommended IOVDD Supply Filter (such as op amps, voltage reference, or any other analog circuitry) Linear Voltage Regulator can be powered from the AV supply line as well. DD The ADuC7124/ADuC7126 require a single 3.3 V supply, but DIGITAL SUPPLY BEAD ANALOG SUPPLY the core logic requires a 2.6 V supply. An on-chip linear regulator generates the 2.6 V from IOV for the core logic. The +– 10µF ADuC7124/ 10µF DD LV pin is the 2.6 V supply for the core logic. An external ADuC7126 DD IOVDD compensation capacitor of 0.47 µF must be connected between IOVDD AVDD 0.1µF LVDD and DGND (as close as possible to these pins) to act as a tank of charge as shown in Figure 65. IOVDD 0.1µF DGND ADuC7124/ ADuC7126 DGND AGND DGND 09123-145 0.47µF LDVGDNDD Figure 63. External Single Supply Connections Notice that in both Figure 62 and Figure 63, a large value (10 µF) rseitsse ornvo AirV cDaDp. aInci taodrd sititios no,n l oIcOaVl sDmD,a alln-vda alu see p(0a.r1a tµeF 1) 0c aµpFa cciatporasc iatroer 09123-046 located at each AV and IOV pin of the chip. As per standard Figure 65. Voltage Regulator Connections DD DD design practice, be sure to include all of these capacitors and ensure The LV pin should not be used for any other chip. It is also DD that the smaller capacitors are close to each AV pin with trace DD recommended to use excellent power supply decoupling on lengths as short as possible. Connect the ground terminal of IOV to help improve line regulation performance of the on- DD each of these capacitors directly to the underlying ground plane. chip voltage regulator. Rev. D | Page 103 of 110

ADuC7124/ADuC7126 Data Sheet GROUNDING AND BOARD LAYOUT For example, do not power components on the analog side (as RECOMMENDATIONS seen in Figure 66b) with IOV because that forces return DD currents from IOV to flow through AGND. Avoid digital As with all high resolution data converters, special attention DD currents flowing under analog circuitry, which can occur if a must be paid to grounding and PC board layout of the noisy digital chip is placed on the left half of the board (shown ADuC7124/ADuC7126-based designs to achieve optimum in Figure 66c). If possible, avoid large discontinuities in the performance from the ADCs and DAC. ground plane(s), such as those formed by a long trace on the same Although the part has separate pins for analog and digital ground layer, because they force return signals to travel a longer path. (AGND and IOGND), the user must not tie these to two sepa- In addition, make all connections to the ground plane directly, rate ground planes unless the two ground planes are connected with little or no trace separating the pin from its via to ground. very close to the part. This is illustrated in the simplified example When connecting fast logic signals (rise/fall time < 5 ns) to any of shown in Figure 66a. In systems where digital and analog the ADuC7124/ADuC7126 digital inputs, add a series resistor ground planes are connected together somewhere else (at the to each relevant line to keep rise and fall times longer than 5 ns power supply of the system, for example), the planes cannot be at the input pins of the part. A value of 100 Ω or 200 Ω is reconnected near the part because a ground loop results. In these usually sufficient to prevent high speed signals from coupling cases, tie all the ADuC7124/ADuC7126 AGND and IOGND capacitively into the part and affecting the accuracy of ADC pins to the analog ground plane, as illustrated in Figure 66b. conversions. In systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate CLOCK OSCILLATOR halves of the board so that digital return currents do not flow The clock source for the ADuC7124/ADuC7126 can be gener- near analog circuitry (and vice versa). ated by the internal PLL or by an external clock input. To use The ADuC7124/ADuC7126 can then be placed between the the internal PLL, connect a 32.768 kHz parallel resonant crystal digital and analog sections, as illustrated in Figure 66c. between XCLKI and XCLKO, and connect a capacitor from each pin to ground as shown in Figure 67. The crystal allows the PLL to lock correctly to give a frequency of 41.78 MHz. If no external crystal is present, the internal oscillator is used to give PLACE ANALOG PLACE DIGITAL a typical frequency of 32.768 kHz ± 3%. a. COMPONENTS HERE COMPONENTS HERE ADuC7124/ ADuC7126 AGND DGND XCLKI 12pF 32.768kHz TO PLACE ANALOG PLACE DIGITAL 12pF XCLKO IPNLTLERNAL 09123-048 b. COMPONENTS COMPONENTS HERE Figure 67. External Parallel Resonant Crystal Connections HERE To use an external source clock input instead of the PLL (see AGND DGND Figure 68), Bit 1 and Bit 0 of PLLCON must be modified. The external clock uses P0.7 and XCLK. ADuC7124/ ADuC7126 XCLKO PLACE ANALOG PLACE DIGITAL XCLKI c. COMPONENTS HERE COMPONENTS HERE EXTERNAL TO DGND 09123-047 FigSuCOrLeUO 6RC8CK.E ConneXcCtiLnKg an ExterFDnRIaVElI DCQElUoREcNkC SYourc09123-049e Figure 66. System Grounding Schemes Using an external clock source, the ADuC7124/ADuC7126 In all of these scenarios, and in more complicated real-life specified operational clock speed range is 50 kHz to 41.78 MHz applications, the users should pay particular attention to the ± 1%, which ensures correct operation of the analog peripherals flow of current from the supplies and back to ground. Make and Flash/EE. sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. Rev. D | Page 104 of 110

Data Sheet ADuC7124/ADuC7126 POWER-ON RESET OPERATION 3.3V An internal power-on reset (POR) is implemented on the IOVDD ADuC7124/ADuC7126. For LV below 2.40 V typical, the DD 2.6V internal POR holds the part in reset. As LVDD rises above 2.41 V, 2.41V TYP 2.41V TYP an internal timer times out for typically 128 ms before the part LVDD is released from reset. The user must ensure that the power supply, IOVDD, reaches a stable 2.7 V minimum level by this 128ms TYP time. Likewise, on power-down, the internal POR holds the part in reset until LV drops below 2.40 V. Figure 69 illustrates the DD POR operation of the internal POR in detail. 0.12ms TYP MRST 09123-050 Figure 69. Internal Power-On Reset Operation Rev. D | Page 105 of 110

ADuC7124/ADuC7126 Data Sheet OUTLINE DIMENSIONS 9.10 9.00 SQ 0.60 MAX 8.90 0.60 MAX PIN 1 49 64 INDICATOR 48 1 PIN 1 INDICATOR 8.85 0.50 EXPOSED *4.85 8.75 SQ BSC PAD 4.70 SQ 8.65 4.55 0.50 0.40 33 16 32 17 0.30 TOP VIEW BOTTOM VIEW 0.25 MIN 7.50 REF 1.00 12° MAX 0.80 MAX 0.85 0.65 TYP FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 0.80 0.02 NOM THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SEATING 0.30 SECTION OF THIS DATA SHEET. PLANE 0.23 0.20 REF 0.18* ECXOCMEPPLTI AFNOTR T EOX PJEODSEECD SPTAADN DDIAMREDNSS IMOON-220-VMMD-4 06-13-2012-A Figure 70. 64-Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Quad (CP-64-1) Dimensions shown in millimeters 14.20 14.00 SQ 0.75 13.80 0.60 1.60 0.45 MAX 80 61 1 60 PIN 1 12.20 12.00 SQ 1.45 (TPIONPS DVOIEWWN) 11.80 0.20 1.40 0.09 1.35 7° 3.5° 00..1055 SEATING 0.08 0° 2021 4041 PLANE COPLANARITY VIEW A 0.50 0.27 VIEW A LEABDS PCITCH 00..2127 ROTATED 90° CCW COMPLIANTTO JEDEC STANDARDS MS-026-BDD 051706-A Figure 71. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-1) Dimensions shown in millimeters Rev. D | Page 106 of 110

Data Sheet ADuC7124/ADuC7126 ORDERING GUIDE ADC DAC Temperature Package Package Ordering Model1 Channels Channels Flash/RAM GPIO Downloader Range Description Option Quantity ADuC7124BCPZ126 10 2 126 kB/32 kB 30 UART −40°C to +125°C 64-Lead CP-64-1 260 LFCSP_VQ ADuC7124BCPZ126-RL 10 2 126 kB/32 kB 30 UART −40°C to +125°C 64-Lead CP-64-1 2500 LFCSP_VQ ADuC7126BSTZ126 12 4 126 kB/32 kB 40 UART −40°C to +125°C 80-Lead LQFP ST-80-1 119 ADuC7126BSTZ126-RL 12 4 126 kB/32 kB 40 UART −40°C to +125°C 80-Lead LQFP ST-80-1 1000 ADuC7126BSTZ126I 12 4 126 kB/32 kB 40 I2C −40°C to +125°C 80-Lead LQFP ST-80-1 119 ADuC7126BSTZ126IRL 12 4 126 kB/32 kB 40 I2C −40°C to +125°C 80-Lead LQFP ST-80-1 1000 EVAL-ADuC7124QSPZ ADuC7124 QuickStart Development System EVAL-ADuC7126QSPZ ADuC7126 QuickStart Development System 1 Z = RoHS Compliant Part. Rev. D | Page 107 of 110

ADuC7124/ADuC7126 Data Sheet NOTES Rev. D | Page 108 of 110

Data Sheet ADuC7124/ADuC7126 NOTES Rev. D | Page 109 of 110

ADuC7124/ADuC7126 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09123-0-10/14(D) Rev. D | Page 110 of 110