Low Power, Precision Analog Microcontroller, Dual Sigma-Delta ADCs, Flash/EE, ARM7TDMI Data Sheet ADuC7060/ADuC7061 FEATURES Packages and temperature range Fully specified for −40°C to +125°C operation Analog input/output 32-lead LFCSP (5 mm × 5 mm) Dual (24-bit) ADCs 48-lead LFCSP and LQFP Single-ended and differential inputs Derivatives Programmable ADC output rate (4 Hz to 8 kHz) 32-lead LFCSP (ADuC7061) Programmable digital filters 48-lead LQFP and 48-lead LFCSP (ADuC7060) Built-in system calibration Low power operation mode APPLICATIONS Primary (24-bit) ADC channel Industrial automation and process control 2 differential pairs or 4 single-ended channels Intelligent, precision sensing systems, 4 mA to 20 mA PGA (1 to 512) input stage loop-based smart sensors Selectable input range: ±2.34 mV to ±1.2 V 30 nV rms noise GENERAL DESCRIPTION Auxiliary (24-bit) ADC: 4 differential pairs or 7 single- The ADuC7060/ADuC7061 series are fully integrated, 8 kSPS, ended channels 24-bit data acquisition systems incorporating high performance On-chip precision reference (±10 ppm/°C) multichannel sigma-delta (Σ-Δ) analog-to-digital converters Programmable sensor excitation current sources (ADCs), 16-bit/ 32-bit ARM7TDMI® MCU, and Flash/EE memory 200 μA to 2 mA current source range on a single chip. Single 14-bit voltage output DAC Microcontroller The ADCs consist of a primary ADC with two differential pairs or ARM7TDMI core, 16-/32-bit RISC architecture four single-ended channels and an auxiliary ADC with up to seven JTAG port supports code download and debug channels. The ADCs operate in single-ended or differential input Multiple clocking options mode. A single-channel buffered voltage output DAC is available Memory on chip. The DAC output range is programmable to one of four 32 kB (16 kB × 16) Flash/EE memory, including 2 kB kernel voltage ranges. 4 kB (1 kB × 32) SRAM The devices operate from an on-chip oscillator and a PLL gene- Tools rating an internal high frequency clock up to 10.24 MHz. The In-circuit download, JTAG based debug microcontroller core is an ARM7TDMI, 16-bit/32-bit RISC Low cost, QuickStart™ development system machine offering up to 10 MIPS peak performance; 4 kB of SRAM Communications interfaces and 32 kB of nonvolatile Flash/EE memory are provided on chip. SPI interface (5 Mbps) The ARM7TDMI core views all memory and registers as a single 4-byte receive and transmit FIFOs linear array. UART serial I/O and I2C (master/slave) The ADuC7060/ADuC7061 contains four timers. Timer1 is a On-chip peripherals wake-up timer with the ability to bring the part out of power saving 4× general-purpose (capture) timers including mode. Timer2 is configurable as a watchdog timer. A 16-bit PWM Wake-up timer with six output channels is also provided. The ADuC7060/ Watchdog timer ADuC7061 contains an advanced interrupt controller. The Vectored interrupt controller for FIQ and IRQ vectored interrupt controller (VIC) allows every interrupt to be 8 priority levels for each interrupt type assigned a priority level. It also supports nested interrupts to a Interrupt on edge or level external pin inputs maximum level of eight per IRQ and FIQ. When IRQ and FIQ 16-bit, 6-channel PWM interrupt sources are combined, a total of 16 nested interrupt levels General-purpose inputs/outputs is supported. On-chip factory firmware supports in-circuit serial Up to 14 GPIO pins that are fully 3.3 V compliant download via the UART serial interface ports and nonintrusive Power emulation via the JTAG interface. The parts operate from 2.375 V AVDD/DVDD specified for 2.5 V (±5%) to 2.625 V over an industrial temperature range of −40°C to Active mode: 2.74 mA (@ 640 kHz, ADC0 active) +125°C. 10 mA (@ 10.24 MHz, both ADCs active) Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADuC7060/ADuC7061 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 MMR Interface ........................................................................... 57 Applications ....................................................................................... 1 Using the DAC ............................................................................ 58 General Description ......................................................................... 1 Nonvolatile Flash/EE Memory ..................................................... 59 Revision History ............................................................................... 3 Flash/EE Memory Reliability .................................................... 59 Functional Block Diagram .............................................................. 5 Programming .............................................................................. 59 Specifications ..................................................................................... 6 Processor Reference Peripherals ................................................... 60 Electrical Specifications ............................................................... 6 Interrupt System ......................................................................... 60 Timing Specifications ................................................................ 11 IRQ ............................................................................................... 60 Absolute Maximum Ratings .......................................................... 15 Fast Interrupt Request (FIQ) .................................................... 61 ESD Caution ................................................................................ 15 Programmed Interrupts............................................................. 62 Pin Configurations and Function Descriptions ......................... 16 Vectored Interrupt Controller (VIC) ....................................... 62 Terminology .................................................................................... 21 VIC MMRs .................................................................................. 62 Overview of the ARM7TDMI Core ............................................. 22 Timers .............................................................................................. 67 Thumb Mode (T) ........................................................................ 22 HR:MIN:SEC: 1/128 Format .................................................... 67 Multiplier (M) ............................................................................. 22 Timer0.......................................................................................... 68 EmbeddedICE (I) ....................................................................... 22 Timer1 or Wake-Up Timer ....................................................... 70 ARM Registers ............................................................................ 22 Timer2 or Watchdog Timer ...................................................... 72 Interrupt Latency ........................................................................ 23 Timer3.......................................................................................... 74 Memory Organization ............................................................... 23 Pulse-Width Modulator ................................................................. 76 Flash/EE Control Interface ........................................................ 24 Pulse-Width Modulator General Overview ........................... 76 Memory Mapped Registers ....................................................... 28 UART Serial Interface .................................................................... 81 Complete MMR Listing ............................................................. 29 Baud Rate Generation ................................................................ 81 Reset ............................................................................................. 34 UART Register Definitions ....................................................... 81 Oscillator, PLL, and Power Control ............................................. 35 I2C ..................................................................................................... 87 Clocking System ......................................................................... 35 Configuring External Pins for I2C Functionality ................... 87 Power Control System ................................................................ 35 Serial Clock Generation ............................................................ 88 ADC Circuit Information .............................................................. 39 I2C Bus Addresses ....................................................................... 88 Reference Sources ....................................................................... 40 I2C Registers ................................................................................ 88 Diagnostic Current Sources ...................................................... 40 Serial Peripheral Interface ............................................................. 97 Sinc3 Filter ................................................................................... 41 MISO (Master In, Slave Out) Pin ............................................. 97 ADC Chopping ........................................................................... 41 MOSI (Master Out, Slave In) Pin ............................................. 97 Programmable Gain Amplifier ................................................. 41 SCLK (Serial Clock I/O) Pin ..................................................... 97 Excitation Sources ...................................................................... 41 Slave Select (P0.0/SSE) Input Pin ............................................... 97 ADC Low Power Mode .............................................................. 41 Configuring External Pins for SPI Functionality ................... 97 ADC Comparator and Accumulator ....................................... 42 SPI Registers ................................................................................ 98 Temperature Sensor ................................................................... 42 General-Purpose I/O ................................................................... 102 ADC MMR Interface ................................................................. 42 GPxCON Registers................................................................... 102 Example Application Circuits ................................................... 55 GPxDAT Registers ................................................................... 103 DAC Peripherals ............................................................................. 57 GPxSET Registers ..................................................................... 103 DAC .............................................................................................. 57 GPxCLR Registers .................................................................... 103 Rev. F | Page 2 of 107

Data Sheet ADuC7060/ADuC7061 GPxPAR Registers .................................................................... 103 Outline Dimensions ...................................................................... 106 Hardware Design Considerations .............................................. 105 Ordering Guide ......................................................................... 107 Power Supplies .......................................................................... 105 REVISION HISTORY 2/2017—Rev. E to Rev. F Add Temporary Protection Section and Keyed Permanent Changed CP-32-4 to CP-32-11 .................................... Throughout Protection Section ........................................................................... 25 Changed CP-48-3 to CP-48-5 ...................................... Throughout Added Permanent Protection Section and Sequence to Write the Changes to Table 5 .......................................................................... 13 Software Protection Key and Set Permanent Protection Section ... 26 Changes to Table 6 .......................................................................... 14 Changes to Power Control System Section .................................. 35 Changes to Serial Peripheral Interface ......................................... 97 Changes to Bit 9:6, Table 43 ........................................................... 45 Changes to Figure 30 and Figure 31 ...........................................106 Changes to Primary Channel ADC Data Register Section and Updated Outline Dimensions ......................................................106 Table 49 ............................................................................................. 50 Changes to Ordering Guide .........................................................107 Changes to IRQEN Section and IRQCLR Section ..................... 59 Changes to Timer1 or Wake-Up Timer Section ......................... 69 10/2014—Rev. D to Rev. E Changes to Table 108 .................................................................... 101 Changes to Table 1 ............................................................................ 6 Changed FEESIGN to FEESIG (Throughout) ............................. 25 2/2010—Rev. A to Rev. B Changed FEEHIDE to FEEHID (Throughout) .......................... 26 Changes to Features Section ............................................................ 1 Changes to Table 36 ........................................................................ 40 Changes to Table 1 ............................................................................ 4 Changes to Sinc3 Filter Section ..................................................... 41 Changes to Digital I/O Voltage to DGND Parameter ................ 14 Changes to Table 43 ........................................................................ 46 Changes to Pin 19, Pin 20, and Pin 45 Descriptions (Table 8).. 16 Changes to ADC Filter Register Section ...................................... 48 Changes to Pin 13, Pin 14, and Pin 29 Descriptions (Table 9).. 18 Changes to Table 94 ........................................................................ 85 Changes to Bit 8 in Table 14 .......................................................... 23 Changes to I2C Section ................................................................... 87 Changes to Table 20 ........................................................................ 28 Changes to Table 97 ........................................................................ 89 Changes to Power Control System Section .................................. 34 Changed Register I2CMSTA, Bit 7 from I2CMNA to I2CMND; Added Table 32 ................................................................................ 35 Table 98 ............................................................................................. 90 Changes to Endnote 2 and Endnote 3 of Table 34 ...................... 36 Changes to Table 104. ..................................................................... 93 Changes to Table 42 ........................................................................ 42 Changes to Table 105 ...................................................................... 94 Changes to Bit 12 and Bits[3:0] in Table 43 ................................. 44 Updated Figure 31, Outline Dimensions ...................................106 Changes to Bit 12 in Table 44 ........................................................ 45 Changes to Endnote 2 in Table 45 ................................................ 47 4/2012—Rev. C to Rev. D Changes to Bit 5 in Table 63 .......................................................... 55 Changes to Table 1 ............................................................................ 6 Changes to Serial Downloading (In-Circuit Programming) Changes to Table 7 .......................................................................... 14 Section .............................................................................................. 57 Changes to Table 16 ........................................................................ 25 Changes to Priority Registers Section .......................................... 61 Change to Command Sequence for Executing a Mass Erase Changes to GPxPAR Registers Section ...................................... 101 Section ............................................................................................... 26 Changes to Table 19 ........................................................................ 29 6/2009—Rev. 0 to Rev. A Changes to Power and Clock Control Registers Section ........... 35 Added ADuC7061 .............................................................. Universal Changes to Figure 20 ...................................................................... 55 Added New Package CP-32-4 ........................................... Universal Changes to Bit 5 in Table 63 ........................................................... 57 Changes to Features Section ............................................................ 1 Changes to Timers Section; Added Hr:Min:Sec: 1/128 Format Changes to General Description Section ....................................... 1 Section and Table 79, Renumbered Sequenitially ....................... 67 Changes to Figure 1 .......................................................................... 4 Changes to Timer1 or Wake-Up Timer Section ......................... 70 Changes to Table 1 ............................................................................ 7 Changes to Timer2 Load Register Section and Timer2 Value Deleted Endnote to Table 2 ............................................................ 10 Register Section ............................................................................... 71 Changes to Endnotes, Table 3 and Table 4 ................................... 11 Added Table 108 .............................................................................. 98 Changes to Endnotes, Table 5 ........................................................ 12 Updated Outline Dimensions ......................................................105 Changes to Endnotes, Table 6 ........................................................ 13 Changes to Figure 7 and Table 8 ................................................... 15 5/2011—Rev. B to Rev. C Added Figure 8 and Table 9, Renumbered Sequentially ............ 18 Change to Figure 1 ............................................................................ 4 Changes to Flash EE/Control Interface Section .......................... 23 Changes to Table 1 ............................................................................ 6 Change to Code 0x04 Description, Table 15 ............................... 24 Change to Bit 31 Description, Table 16 ........................................ 25 Rev. F | Page 3 of 107

ADuC7060/ADuC7061 Data Sheet Changes to Table 17 ........................................................................ 27 Changes to Figure 23 ...................................................................... 65 Changes to Table 19 T0CLRI and Table 20 ................................. 28 Changes Table 78 ............................................................................ 66 Changes to Endnote, Table 21 ....................................................... 29 Changes to Figure 24 and Table 79 .............................................. 68 Change to SPITX Default Value, Table 25 ................................... 30 Changes to Timer2 Interface Section and Figure 25 ................. 69 Changes to External Clock Selection Section ............................. 33 Changes to Timer3 Capture Register Section ............................. 71 Changes to ADC Circuit Information Section ........................... 36 Change to Bits[16:12] Description, Table 81 .............................. 72 Change to Column Heading Table 35 .......................................... 37 Changes Pulse-Width Modulator General Overview Section, Change to Bit 6 Description, Table 39 ......................................... 40 Table 82, and Figure 26 .................................................................. 73 Change to Bit 12 Description, Table 43 ....................................... 44 Changes to Table 84 Column Headings ...................................... 75 Changes to Primary Channel ADC Data Register Section Changes to Table 92 ....................................................................... 82 and Auxiliary Channel ADC Data Register Section .................. 48 Changes to Bit 1, Table 102 ........................................................... 90 Change to Table 59 and Figure 17 ................................................ 51 Changes to Bit 11 Description, Table 105 ................................... 95 Changes to Using the DAC Section ............................................. 55 Changes to SPIMDE Bit Description, Table 106 ........................ 97 Changes to Nonvolatile Flash/EE Memory Section and Updated Outline Dimensions ..................................................... 103 Programming Section .................................................................... 56 Changes to Ordering Guide ........................................................ 104 Changes to Vectored Interrupt Controller (VIC) Section ........ 59 Changes to Priority Registers Section .......................................... 60 4/2009—Revision 0: Initial Version Change to Table 73 ......................................................................... 61 Rev. F | Page 4 of 107

Data Sheet ADuC7060/ADuC7061 FUNCTIONAL BLOCK DIAGRAM PRECISION ANALOG PERIPHERALS ADC0 MEMORY POR 32kB FLASH RESET ADC1 24-BIT 4kB RAM MUX PGA Σ-∆ADC ADC2 ARMM7CTUDMI ON-CHIP XTALI ADC3 OSC (3%) XTALO AADDCC54 MUX BUF 24Σ--B∆IT 10MHz PLL ADC6 ADC ADC7 ADC8 4× TIMERS GPIO PORT WDT UART PORT ADC9 W/U TIMER SPI PORT PRECISION PWM I2C PORT REFERENCE IEXC0 IEXC1 VIC (VECTORED DAC0 BUF 1D4-ABCIT SETNEMSOPR COINNTTERRORLULPETR) VREF+ VREF– GND_SW AADDuuCC77006601/ 07079-001 Figure 1. Rev. F | Page 5 of 107

ADuC7060/ADuC7061 Data Sheet SPECIFICATIONS ELECTRICAL SPECIFICATIONS V = 2.5 V ± 5%, VREF+ = 1.2 V, VREF− = GND, f = 10.24 MHz driven from an external 32.768 kHz watch crystal or on-chip oscillator, all DD CORE specifications T = −40°C to +125°C, unless otherwise noted. Output noise specifications can be found in Table 36 (primary ADC) and A Table 38 (ADC auxiliary channel). Table 1. ADuC7060/ADuC7061 Specifications Parameter Test Conditions/Comments Min Typ Max Unit ADC SPECIFICATIONS For all ADC specifications, assume normal operating mode unless specifically stated otherwise Conversion Rate1 Chop off, ADC normal operating 50 8000 Hz mode Chop on, ADC normal operating 4 2600 Hz mode Chop on, ADC low power mode 1 650 Hz Main Channel No Missing Codes1 Chop off (f ≤ 1 kHz) 24 Bits ADC Chop on (f ≤ 666 Hz) 24 Bits ADC Integral Nonlinearity1, 2 Gain = 4 ±15 ppm of FSR Offset Error3, 4 Chop off, offset error is in the −27 ±8 +27 μV order of the noise for the pro- grammed gain and update rate following calibration Offset Error1, 3, 4 Chop on −2.7 ±0.5 +2.7 μV Offset Error Drift vs. Chop off (with gain ≤ 64) 650/PGA_GAIN nV/°C Temperature5 Chop on (with gain ≤ 64) 10 nV/°C Full-Scale Error1, 6, 7, 8 Normal mode −1 ±0.5 +1 mV Full-Scale Error 6, 8 Low power mode −2 ±1.0 +2 mV Gain Drift vs. Temperature9 5 ppm/°C PGA Gain Mismatch Error ±0.1 % Power Supply Rejection1 Chop on, ADC = 1 V (gain = 1) 65 dB Chop on, ADC = 7.8 mV (gain = 128) 84.7 113 dB Chop off, ADC = 1 V (gain = 1) 56 65 dB Auxiliary Channel No Missing Codes1 Chop off (f ≤ 1 kHz) 24 Bits ADC Chop on (f ≤ 666 Hz) 24 Bits ADC Integral Nonlinearity1 ±15 ppm of FSR Offset Error4 Chop off −120 ±30 +100 μV Offset Error1, 4 Chop on −1.5 ±0.5 +3.2 μV Offset Error Drift vs. Chop off 200 nV/°C Temperature5 Chop on 10 nV/°C Full-Scale Error1, 6, 7, 8 Normal mode −1 ±0.5 +1 mV Full-Scale Error1, 6, 8 Low power mode −2 ±1.0 +2 mV Gain Drift vs. Temperature9 3 ppm/°C Power Supply Rejection1 Chop on, ADC = 1 V 55 65 dB Chop off, ADC = 1 V 53 65 dB Rev. F | Page 6 of 107

Data Sheet ADuC7060/ADuC7061 Parameter Test Conditions/Comments Min Typ Max Unit ADC SPECIFICATIONS: ANALOG Internal V = 1.2 V REF INPUT Main Channel Absolute Input Voltage Range Applies to both VIN+ and VIN− 0.1 V − 0.7 V DD Input Voltage Range Gain = 11 0 1.2 V (Differential Voltage Between Gain = 21 0 600 mV AIN+ and AIN–) Gain = 41 0 300 mV Gain = 81 0 150 mV Gain = 161 0 75 mV Gain = 321 0 37.5 mV Gain = 641 0 18.75 mV Gain = 1281 0 9.375 mV Common Mode Voltage, V 10 V = (AIN(+) + AIN(−))/2, 0.5 V CM CM gain = 4 to 128 Input Leakage Current1 ADC0 and ADC1 10 181 nA ADC2, ADC3, ADC4, and ADC5 15 301 nA ADC6, ADC7, ADC8, and ADC9, 15 251 nA VREF+, VREF− Measurements are taken when the ADC is not opearating Common-Mode Rejection DC1 On ADC Input ADC = 7.8 mV 113 dB ADC = 1 V1 95 dB Common-Mode Rejection 50 Hz/60 Hz ± 1 Hz, 16.6 Hz and 50 Hz/60 Hz1 50 Hz update rate, chop on ADC = 7.8 mV, range ± 20 mV 95 dB ADC = 1 V, range ± 1.2 V 90 dB Normal-Mode Rejection 50 Hz/60 Hz1 On ADC Input 50 Hz/60 Hz ± 1 Hz, 16.6 Hz f , 75 dB ADC chop on 50 Hz/60 Hz ± 1 Hz, 16.6 Hz f , 67 dB ADC chop off Auxiliary Channel Absolute Input Voltage Buffer enabled 0.1 AVDD − 0.1 V Range1 Buffer disabled AGND AVDD V Input Voltage Range Range-based reference source 0 1.2 V Common-Mode Rejection DC1 On ADC Input ADC = 1 V1 87 dB Common-Mode Rejection 50 Hz/60 Hz ± 1 Hz, 16.6 Hz and 50 Hz/60 Hz1 50 Hz update rate, chop on ADC = 1 V, range ± 1.2 V 90 dB Normal-Mode Rejection 50 Hz/60 Hz1 On ADC Input 50 Hz/60 Hz ± 1 Hz, 16.6 Hz f , 75 dB ADC chop on 50 Hz/60 Hz ± 1 Hz, 16.6 Hz f , 67 dB ADC chop off VOLTAGE REFERENCE ADC Precision Reference Internal V 1.2 V REF Initial Accuracy Measured at T = 25°C −0.1 +0.1 % A Reference Temperature −20 ±10 +20 ppm/°C Coefficient (Tempco)1, 11 Power Supply Rejection1 70 dB External Reference Input Range12 0.1 AVDD V V Divide-by-2 Initial Error1 0.1 % REF Rev. F | Page 7 of 107

ADuC7060/ADuC7061 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit DAC CHANNEL SPECIFICATIONS R = 5 kΩ, C = 100 pF L L Voltage Range 0 V V REF 0 AVDD − 0.2 V DAC 12-BIT MODE DC Specifications13 Resolution 12 Bits Relative Accuracy ±2 LSB Differential Nonlinearity Guaranteed monotonic ±0.2 ±1 LSB Offset Error 1.2 V internal reference ±2 ±15 mV Gain Error V range (reference = 1.2 V) ±1 % REF AVDD range ±1 % Gain Error Mismatch 0.1 % of full scale on DAC DAC 16-BIT MODE1 Only monotonic to 14 bits DC Specifications14 Resolution 14 Bits Relative Accuracy For 14-bit resolution ±3 LSB Differential Nonlinearity Guaranteed monotonic (14 bits) ±0.5 ±1 LSB Offset Error 1.2 V internal reference ±2 ±15 mV Gain Error V range (reference = 1.2 V) ±1 % REF AVDD range ±1 % Gain Error Mismatch 0.1 % of full scale on DAC DAC AC CHARACTERISTICS Voltage Output Settling Time 10 µs Digital-to-Analog Glitch Energy 1 LSB change at major carry ±20 nV-sec (where maximum number of bits simultaneously change in the DAC0DAT register) TEMPERATURE SENSOR1, 15 After user calibration Accuracy MCU in power-down or standby ±4 °C mode Voltage Output at 0°C Typical value 96 mV Voltage Tempco Typical value 0.28 mV/°C Thermal Impedance 48-lead LFCSP 27 °C/W 48-lead LQFP 55 °C/W 32-lead LFCSP 30 °C/W GROUND SWITCH1 R 10 Ω ON Input Leakage 15 nA POWER-ON RESET (POR) POR Trip Level1 Refers to voltage at DVDD pin Power-on level 2.0 V Power-down level 2.25 V Maximum supply ramp between 128 ms RESET Timeout from POR 1.8 V and 2.25 V; after POR trip, DVDD must reach 2.25 V within this time limit Rev. F | Page 8 of 107

Data Sheet ADuC7060/ADuC7061 Parameter Test Conditions/Comments Min Typ Max Unit EXCITATION CURRENT SOURCES Output Current Available from each current 200 1000 μA source Initial Tolerance at 25°C ±5 % Drift1 0.06 %/°C Initial Current Matching at 25°C Matching between both current ±0.5 % sources Drift Matching1 20 ppm/°C Line Regulation (AVDD)1 AVDD = 2.5 V ± 5% 0.2 %/V Output Compliance1 AGND − 30 mV AVDD − 0.7 V V WATCHDOG TIMER (WDT) Timeout Period1 32.768 kHz clock, 256 prescale 0.008 512 sec Timeout Step Size 7.8 ms FLASH/EE MEMORY1 Endurance16 10,000 Cycles Data Retention17 20 Years DIGITAL INPUTS All digital inputs except NTRST Input Leakage Current Input (high) = DVDD ±1 ±10 µA Input Pull-Up Current Input (low) = 0 V 10 20 80 µA Input Capacitance 10 pF Input Leakage Current NTRST only: input (low) = 0 V ±1 ±10 µA Input Pull-Down Current NTRST only: input (high) = DVDD 30 55 100 µA LOGIC INPUTS1 All logic inputs Input Low Voltage (VINL) 0.4 V Input High Voltage (VINH) 2.0 V LOGIC OUTPUTS1 All logic outputs except XTALO Output Low Voltage (VOL) I = 1.6 mA 0.6 V SOURCE Output High Voltage (VOH) I = 1.6 mA 2.0 V SOURCE CRYSTAL OSCILLATOR1 Logic Inputs, XTALI Only Input Low Voltage (VINL) 0.8 V Input High Voltage (VINH) 1.7 V XTALI Capacitance 12 pF XTALO Capacitance 12 pF ON-CHIP OSCILLATORS Oscillator 32,768 kHz Accuracy −3 +3 % MCU CLOCK RATE Eight programmable core clock 0.08 1.28 10.24 MHz selections within this range: binary divisions 1, 2, 4, 8 . . . 64, 128 Using an External Clock to 0.08 10.24 MHz P2.0/EXTCLK Pin MCU START-UP TIME At Power-On Includes kernel power-on 134 ms execution time After Reset Event Includes kernel power-on 5 ms execution time From MCU Power-Down PLL On Wake-Up from Interrupt CD = 0 4.8 μs PLL Off Wake-Up from Interrupt CD = 0 66 μs Internal PLL Lock Time 1 ms Rev. F | Page 9 of 107

ADuC7060/ADuC7061 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit POWER REQUIREMENTS Power Supply Voltages DVDD (±5%) 2.375 2.5 2.625 V AVDD (±5%) 2.375 2.5 2.625 V Power Consumption I (MCU Normal Mode)18 MCU clock rate = 10.24 MHz, 6 10 mA DD ADC0 on MCU clock rate = 640 kHz, ADC0 on, G = 4, ADC1/DAC off, SPI on; POWCON1 = 0x4 Full temperature range 3.1 mA Reduced temperature range 2.74 mA −40°C to +85°C1 I (MCU Powered Down)1 Full temperature range 55 350 µA DD Reduced temperature range 55 120 µA −40°C to +85°C I (Primary ADC) PGA enabled, normal mode/low 0.6/0.3 mA DD power mode; current is dependent on gain setting ADC0 on, G = 1, normal mode 0.03 mA ADC0 on, G = 4, normal mode 0.44 mA ADC0 on, G = >128, normal mode 0.63 mA I (Auxiliary ADC) Normal mode/low power mode 0.35/0.1 mA DD I (DAC) DAC0CON = 0x10 0.33 mA DD PWM 0.34 mA 1 These numbers are not production tested but are guaranteed by design and/or characterization data at production release. 2 Valid for primary ADC gain setting of PGA = 4 to 64. 3 Tested at gain range = 4 after initial offset calibration. 4 Measured with an internal short. A system zero-scale calibration removes this error. ADC factory calibration done with chop off. 5 Measured with an internal short. 6 These numbers do not include internal reference temperature drift. 7 Factory calibrated at gain = 1. 8 System calibration at a specific gain range removes the error at this gain range. ADC factory calibration done with chop off. 9 Measured using an external reference. 10 Ensure common mode voltage is set so VIN*Gain setting, which is the PGA output voltage, is between 0.1V and VDD – 0.7V. 900 mV is an optimum value for the common mode voltage across all gains. 11 Measured using the box method. 12 References up to AVDD are accommodated by setting ADC0CON Bit 12. 13 Reference DAC linearity is calculated using a reduced code range of 171 to 4095. 14 Reference DAC linearity is calculated using a reduced code range of 2731 to 65,535. 15 Die temperature. 16 Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles. 17 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature. 18 Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively. Rev. F | Page 10 of 107

Data Sheet ADuC7060/ADuC7061 TIMING SPECIFICATIONS I2C Timing Table 2. I2C® Timing in Standard Mode (100 kHz) Slave Parameter Description Min Max Unit t SCLOCK low pulse width 4.7 µs L t SCLOCK high pulse width 4.0 ns H t Start condition hold time 4.0 µs SHD t Data setup time 250 ns DSU t Data hold time 0 3.45 µs DHD t Setup time for repeated start 4.7 µs RSU t Stop condition setup time 4.0 µs PSU t Bus-free time between a stop condition and a start condition 4.7 µs BUF t Rise time for both CLOCK and SDATA 1 µs R t Fall time for both CLOCK and SDATA 300 ns F tBUF tR SDATA (I/O) MSB LSB ACK MSB tPSU tDSU tDHD tDSU tDHD tF tSHD tH tRSU tR SCLK (I) 1 2–7 8 9 1 COSNTDOIPTPION COSNTSDAIRTITON tL RESPSTEA(RAR)TTED tF 07079-029 Figure 2. I2C Compatible Interface Timing Rev. F | Page 11 of 107

ADuC7060/ADuC7061 Data Sheet SPI Timing Table 3. SPI Master Mode Timing (Phase Mode = 1) Parameter Description Min Typ Max Unit t SCLOCK low pulse width (SPIDIV + 1) × t ns SL HCLK t SCLOCK high pulse width (SPIDIV + 1) × t ns SH HCLK t Data output valid after SCLOCK edge 25 ns DAV t Data input setup time before SCLOCK edge1 1 × t ns DSU UCLK t Data input hold time after SCLOCK edge1 2 × t ns DHD UCLK t Data output fall time 30 40 ns DF t Data output rise time 30 40 ns DR t SCLOCK rise time 30 40 ns SR t SCLOCK fall time 30 40 ns SF 1 tUCLK = 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL. SCLOCK (POLARITY = 0) tSH tSL SCLOCK tSR tSF (POLARITY = 1) tDAV tDF tDR MOSI MSB BITS 6 TO 1 LSB MISO MSB IN BITS 6 TO 1 LSB IN tDSU tDHD 07079-030 Figure 3. SPI Master Mode Timing (Phase Mode = 1) Table 4. SPI Master Mode Timing (Phase Mode = 0) Parameter Description Min Typ Max Unit t SCLOCK low pulse width (SPIDIV + 1) × t ns SL HCLK t SCLOCK high pulse width (SPIDIV + 1) × t ns SH HCLK t Data output valid after SCLOCK edge 25 ns DAV t Data output setup before SCLOCK edge 90 ns DOSU t Data input setup time before SCLOCK edge1 1 × t ns DSU UCLK t Data input hold time after SCLOCK edge1 2 × t ns DHD UCLK t Data output fall time 30 40 ns DF t Data output rise time 30 40 ns DR t SCLOCK rise time 30 40 ns SR t SCLOCK fall time 30 40 ns SF 1 tUCLK = 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL. Rev. F | Page 12 of 107

Data Sheet ADuC7060/ADuC7061 SCLOCK (POLARITY = 0) tSH tSL tSR tSF SCLOCK (POLARITY = 1) tDAV tDOSU tDF tDR MOSI MSB BITS 6 TO 1 LSB MISO MSB IN BITS 6 TO 1 LSB IN tDSU tDHD 07079-031 Figure 4. SPI Master Mode Timing (Phase Mode = 0) Table 5. SPI Slave Mode Timing (Phase Mode = 1) Parameter Description Min Typ Max Unit t CS to SCLOCK edge1 (2 × t ) + (2 × t ) ns CS HCLK UCLK t SCLOCK low pulse width 2 × t ns SL UCLK t SCLOCK high pulse width 2 × t ns SH UCLK t Data output valid after SCLOCK edge 40 ns DAV t Data input setup time before SCLOCK edge1 1 × t ns DSU UCLK t Data input hold time after SCLOCK edge1 2 × t ns DHD UCLK t Data output fall time 30 40 ns DF t Data output rise time 30 40 ns DR t SCLOCK rise time 1 ns SR t SCLOCK fall time 1 ns SF t CS high after SCLOCK edge 0 ns SFS 1 tUCLK = 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL. CS tCS tSFS SCLOCK (POLARITY = 0) tSH tSL tSR tSF SCLOCK (POLARITY = 1) tDAV tDF tDR MISO MSB BITS 6 TO 1 LSB MOSI MSB IN BITS 6 TO 1 LSB IN tDSU tDHD 07079-032 Figure 5. SPI Slave Mode Timing (Phase Mode = 1) Rev. F | Page 13 of 107

ADuC7060/ADuC7061 Data Sheet Table 6. SPI Slave Mode Timing (Phase Mode = 0) Parameter Description Min Typ Max Unit t CS to SCLOCK edge1 (2 × t ) + (2 × t ) ns CS HCLK UCLK t SCLOCK low pulse width 2 × t ns SL UCLK t SCLOCK high pulse width 2 × t ns SH UCLK t Data output valid after SCLOCK edge 40 ns DAV t Data input setup time before SCLOCK edge1 1 × t ns DSU UCLK t Data input hold time after SCLOCK edge1 2 × t ns DHD UCLK t Data output fall time 30 40 ns DF t Data output rise time 30 40 ns DR t SCLOCK rise time 1 ns SR t SCLOCK fall time 1 ns SF t Data output valid after CS edge 10 ns DOCS t CS high after SCLOCK edge 0 ns SFS 1 tUCLK = 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL. CS tCS tSFS SCLOCK (POLARITY = 0) tSH tSL tSR tSF SCLOCK (POLARITY = 1) tDAV tDOCS tDF tDR MISO MSB BITS 6 TO 1 LSB MOSI MSB IN BITS 6 TO 1 LSB IN tDSU tDHD 07079-033 Figure 6. SPI Slave Mode Timing (Phase Mode = 0) Rev. F | Page 14 of 107

Data Sheet ADuC7060/ADuC7061 ABSOLUTE MAXIMUM RATINGS T = −40°C to +125°C, unless otherwise noted. A Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 7. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational AGND to DGND to AVDD to DVDD −0.3 V to +0.3 V section of this specification is not implied. Operation beyond Digital I/O Voltage to DGND −0.3 V to +3.6 V the maximum operating conditions for extended periods may VREF± to AGND −0.3 V to AVDD + 0.3 V affect product reliability. ADC Inputs to AGND −0.3 V to AVDD + 0.3 V ESD (Human Body Model) Rating ESD CAUTION All Pins ±2 kV Storage Temperature 125°C Junction Temperature Transient 150°C Continuous 130°C Lead Temperature Soldering Reflow (15 sec) 260°C Rev. F | Page 15 of 107

ADuC7060/ADuC7061 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS K L C T X E 5 0/1 M MM W WW TCKTDITDOMB/TSRTNDVDDDGNDP2.1/IRQ3/PP1.6/PWM4P1.5/PWM3P1.4/PWM2P2.0/IRQ2/PP0.4/IRQ0/P 876543210987 444444444333 RESET 1 36 XTALI PIN 1 TMS 2 INDICATOR 35 XTALO P1.0/IRQ1/SIN/T0 3 34 P0.3/MOSI/SDA P1.1/SOUT 4 33 P0.2/MISO P1.2/SYNC 5 32 P0.1/SCLK/SCL P1.3/TRIP 6 ADuC7060 31 P0.0/SS P0.5/CTS 7 30 DVDD TOP VIEW P0.6/RTS 8 (Not to Scale) 29 DGND DVDD 9 28 ADC9 DGND 10 27 ADC8 DAC0 11 26 ADC7 ADC5/EXT_REF2IN− 12 25 ADC6 345678901234 111111122222 EF2IN+ADC3ADC2IEXC1IEXC0ND_SWADC1ADC0VREF+VREF−AGNDAVDD R G _ T X E 4/ C D A N1.OTTTHHEEISS L DFOCESSP _NVOQT O ANPLPYL YH ATSO ATNH EE XLPQOFSPE.D PADDLE THAT MUST BE LEFT UNCONNECTED. 07079-002 Figure 7. 48-Lead LQFP and 48-Lead LFCSP_VQ Pin Configuration Table 8. ADuC7060 Pin Function Descriptions Pin No. Mnemonic Type1 Description 0 EP Exposed Paddle. The LFCSP_VQ only has an exposed paddle that must be left unconnected. This does not apply to the LQFP. 1 RESET I Reset. Input pin, active low. An external 1 kΩ pull-up resistor is recommended with this pin. 2 TMS I JTAG Test Mode Select. Input pin used for debug and download. An external pull-up resistor (~100 kΩ) should be added to this pin. 3 P1.0/IRQ1/SIN/T0 I/O General-Purpose Input and General Purpose Output P1.0/External Interrupt Request 1/Serial Input/Timer0 Input. This is a multifunction input/output pin offering four functions. 4 P1.1/SOUT I/O General-Purpose Input and General-Purpose Output P1.1/Serial Output. This is a dual function input/output pin. 5 P1.2/SYNC I/O General-Purpose Input and General-Purpose Output P1.2/PWM External Sync Input. This is a dual function input/output pin. 6 P1.3/TRIP I/O General-Purpose Input and General-Purpose Output P1.3/PWM External Trip Input. This is a dual function input/output pin. 7 P0.5/CTS I/O General-Purpose Input and General-Purpose Output P0.5/Clear-to-Send Signal in UART Mode. 8 P0.6/RTS I/O General-Purpose Input and General-Purpose Output P0.6/Request-to-Send Signal in UART Mode. 9 DVDD S Digital Supply Pin. 10 DGND S Digital Ground. 11 DAC0 O DAC Output. Analog output pin. Rev. F | Page 16 of 107

Data Sheet ADuC7060/ADuC7061 Pin No. Mnemonic Type1 Description 12 ADC5/EXT_REF2IN− I Single-Ended or Differential Analog Input 5/External Reference Negative Input. This is a dual function analog input pin. ADC5 serves as the analog input for the auxiliary ADC. EXT_REF2IN− serves as the external reference negative input by ADC for the auxiliary channel. 13 ADC4/EXT_REF2IN+ I Multifunction Analog Input Pin. This pin can be used for the single-ended or differential Analog Input 4, which is the analog input for the auxiliary ADC, or it can be used for the external reference positive input for the auxiliary channel. 14 ADC3 I Single-Ended or Differential Analog Input 3. Analog input for the primary and auxiliary ADCs. 15 ADC2 I Single-Ended or Differential Analog Input 2. Analog input for the primary and auxiliary ADCs. 16 IEXC1 O Programmable Current Source. Analog output pin. 17 IEXC0 O Programmable Current Source. Analog output pin. 18 GND_SW I Switch to Internal Analog Ground Reference. When this input pin is not used, connect it directly to the AGND system ground. 19 ADC1 I Single-Ended or Differential Analog Input 1. Analog input for the primary ADC. Negative differential input for primary ADC. 20 ADC0 I Single-Ended or Differential Analog Input 0. Analog input for the primary ADC. Positive differential input for primary ADC. 21 VREF+ I External Reference Positive Input for the Primary Channel. Analog input pin. 22 VREF− I External Reference Negative Input for the Primary Channel. Analog input pin. 23 AGND S Analog Ground. 24 AVDD S Analog Supply Pin. 25 ADC6 I Analog Input 6 for Auxiliary ADC. Single-ended or differential Analog Input 6. 26 ADC7 I Analog Input 7 for Auxiliary ADC. Single-ended or differential Analog Input 7. 27 ADC8 I Analog Input 8 for Auxiliary ADC. Single-ended or differential Analog Input 8. 28 ADC9 I Analog Input 9 for Auxiliary ADC. Single-ended or differential Analog Input 9. 29 DGND S Digital Ground. 30 DVDD S Digital Supply Pin. 31 P0.0/SS I/O General-Purpose Input and General-Purpose Output P0.0/SPI Slave Select Pin (Active Low). This is a dual function input/output pin. 32 P0.1/SCLK/SCL I/O General-Purpose Input and General-Purpose Output P0.1/SPI Clock Pin/I2C Clock Pin. This is a triple function input/output pin. 33 P0.2/MISO I/O General-Purpose Input and General-Purpose Output P0.2/SPI Master Input Slave Output. This is a dual function input/output pin. 34 P0.3/MOSI/SDA I/O General-Purpose Input and General-Purpose Output P0.3/SPI Master Output Slave Input/I2C Data Pin. This is a triple function input/output pin. 35 XTALO O External Crystal Oscillator Output Pin. 36 XTALI I External Crystal Oscillator Input Pin. 37 P0.4/IRQ0/PWM1 I/O General-Purpose Input and General-Purpose Output P0.4/External Interrupt Request 0/PWM1 Output. This is a triple function input/output pin. 38 P2.0/IRQ2/PWM0/EXTCLK I/O General-Purpose Input and General-Purpose Output P2.0/External Interrupt Request 2/PWM0 Output/External Clock Input. This is a multifunction input/output pin. 39 P1.4/PWM2 I/O General-Purpose Input and General-Purpose Output P1.4/PWM2 Output. This is a dual function input/output pin. 40 P1.5/PWM3 I/O General-Purpose Input and General-Purpose Output P1.5/PWM3 Output. This is a dual function input/output pin. 41 P1.6/PWM4 I/O General-Purpose Input and General-Purpose Output P1.6/PWM4 Output. This is a dual function input/output pin. 42 P2.1/IRQ3/PWM5 I/O General-Purpose Input and General-Purpose Output P2.1/External Interrupt Request 3/PWM5 Output. This is a triple function input/output pin. Rev. F | Page 17 of 107

ADuC7060/ADuC7061 Data Sheet Pin No. Mnemonic Type1 Description 43 DGND S Digital Ground. 44 DVDD S Digital Supply Pin. 45 NTRST/BM I JTAG Reset/Boot Mode. Input pin used for debug and download only and boot mode (BM). The ADuC7060 enters serial download mode if BM is low at reset and executes code if BM is pulled high at reset through a 13 kΩ resistor. 46 TDO O JTAG Data Out. Output pin used for debug and download only. 47 TDI I JTAG Data In. Input pin used for debug and download only. Add an external pull-up resistor (~100 kΩ) to this pin. 48 TCK I JTAG Clock Pin. Input pin used for debug and download only. Add an external pull-up resistor (~100 kΩ) to this pin. 1 I = input, O = output, I/O = input/output, and S = supply. Rev. F | Page 18 of 107

Data Sheet ADuC7060/ADuC7061 01 MM WW KCTIDTODTMB/TSRTNDDVDDNGDP/2QRI/0.2PP/0QRI/4.0P 21098765 33322222 RESET 1 PIN 1 24 XTALI INDICATOR TMS 2 23 XTALO P1.0/IRQ1/SIN/T0 3 22 P0.3/MOSI/SDA/ADC9 P1.1/SOUT 4 ADuC7061 21 P0.2/MISO/ADC8 DAC0 5 TOP VIEW 20 P0.1/SCLK/SCL/ADC7 ADC5/EXT_REF2IN− 6 (Not to Scale) 19 P0.0/SS/ADC6 ADC4/EXT_REF2IN+ 7 18 VREF– ADC3 8 17 VREF+ 90123456 1111111 2CDA1CXEI0CXEIWS_DN1CDA0CDADNGADDVA G N1 . O TPTHAEEDS D32L-EL EMAUDS LTF BCES LPE_VFQT UHNACSO ANNN EEXCPTOEDS.ED PADDLE. THIS EXPOSED 07079-003 Figure 8. 32-Lead LFCSP Pin Configuration Table 9. ADuC7061 Pin Function Descriptions Pin No. Mnemonic Type1 Description 0 EP Exposed Paddle. The 32-lead LFCSP_VQ has an exposed paddle that must be left unconnected. 1 RESET I Reset Pin. Input pin, active low. An external 1 kΩ pull-up resistor is recommended with this pin. 2 TMS I JTAG Test Mode Select. Input pin used for debug and download. An external pull-up resistor (~100 kΩ) should be added to this pin. 3 P1.0/IRQ1/SIN/T0 I/O General-Purpose Input and General-Purpose Output P1.0/External Interrupt Request 1/Serial Input/Timer0 Input. This is a multifunction input/output pin offering four functions. 4 P1.1/SOUT I/O General-Purpose Input and General-Purpose Output P1.1/Serial Output. This is a dual function input/output pin. 5 DAC0 O DAC Output. Analog output pin. 6 ADC5/EXT_REF2IN− I Single-Ended or Differential Analog Input 5/External Reference Negative Input. This is a dual function analog input pin. The ADC5 serves as the analog input for the auxiliary ADC. The EXT_REF2IN− serves as the external reference negative input by ADC for the auxiliary channel. 7 ADC4/EXT_REF2IN+ I Multifunction Analog Input Pin. This pin can be used for the single-ended or differential Analog Input 4, which is the analog input for the auxiliary ADC, or it can be used for the external reference positive input for the auxiliary channel. 8 ADC3 I Single-Ended or Differential Analog Input 3. Analog input for primary and auxiliary ADCs. 9 ADC2 I Single-Ended or Differential Analog Input 2. Analog input for primary and auxiliary ADCs. 10 IEXC1 O Programmable Current Source. Analog output pin. 11 IEXC0 O Programmable Current Source. Analog output pin. 12 GND_SW I Switch to Internal Analog Ground Reference. When this input pin is not used, connect it directly to the AGND system ground. 13 ADC1 I Single-Ended or Differential Analog Input 1. Analog input for the primary ADC. Negative differential input for primary ADC. 14 ADC0 I Single-Ended or Differential Analog Input 0. Analog input for the primary ADC. Positive differential input for primary ADC. 15 AGND S Analog Ground. 16 AVDD S Analog Supply Pin. 17 VREF+ I External Reference Positive Input for the Primary Channel. Analog input pin. 18 VREF− I External Reference Negative Input for the Primary Channel. Analog input pin. 19 P0.0/SS/ADC6 I/O General-Purpose Input and General-Purpose Output P0.0/SPI Slave Select (Active Low)/Input to Auxiliary ADC6. This is a multifunction input/output pin. Single-ended or differential Analog Input 6. Analog input for the auxiliary ADC. 20 P0.1/SCLK/SCL/ADC7 I/O General-Purpose Input and General-Purpose Output P0.1/SPI Clock/I2C Clock/Input to Auxiliary ADC7. This is a multifunction input/output pin. Single-ended or differential Analog Input 7. Analog input for the auxiliary ADC. Rev. F | Page 19 of 107

ADuC7060/ADuC7061 Data Sheet Pin No. Mnemonic Type1 Description 21 P0.2/MISO/ADC8 I/O General-Purpose Input and General-Purpose Output P0.2/SPI Master Input Slave Output/Auxiliary ADC8 Input. This is a triple function input/output pin. Single-ended or differential Analog Input 8. Analog input for the auxiliary ADC. 22 P0.3/MOSI/SDA/ADC9 I/O General-Purpose Input and General-Purpose Output P0.3/SPI Master Output Slave Input/I2C Data Pin/Auxiliary ADC9 Input. This is a multifunction input/output pin. Single-ended or differential Analog Input 9. Analog input for the auxiliary ADC. 23 XTALO O External Crystal Oscillator Output Pin. 24 XTALI I External Crystal Oscillator Input Pin. 25 P0.4/IRQ0/PWM1 I/O General-Purpose Input and General-Purpose Output P0.4/External Interrupt Request 0/PWM1 Output. This is a triple function input/output pin. 26 P2.0/IRQ2/PWM0 I/O General-Purpose Input and General-Purpose Output P2.0/External Interrupt Request 2/PWM0 Output. This is a triple function input/output pin. 27 DGND S Digital Ground. 28 DVDD S Digital Supply Pin. 29 NTRST/BM I JTAG Reset/Boot Mode. Input pin used for debug and download only and boot mode (BM). The ADuC7061 enters serial download mode if BM is low at reset and executes code if BM is pulled high at reset through a 13 kΩ resistor. 30 TDO O JTAG Data Out. Output pin used for debug and download only. 31 TDI I JTAG Data In. Input pin used for debug and download only. Add an external pull-up resistor (~100 kΩ) to this pin. 32 TCK I JTAG Clock. Input pin used for debug and download only. Add an external pull-up resistor (~100 kΩ) to this pin. 1 I = input, O = output, I/O = input/output, and S = supply. Rev. F | Page 20 of 107

Data Sheet ADuC7060/ADuC7061 TERMINOLOGY Conversion Rate Output Noise The conversion rate specifies the rate at which an output result The output noise is specified as the standard deviation (or 1 × is available from the ADC, when the ADC has settled. Sigma) of the distribution of the ADC output codes collected when the ADC input voltage is at a dc voltage. It is expressed as The sigma-delta (Σ-Δ) conversion techniques used on this part micro root mean square. The output, or root mean square (rms) mean that whereas the ADC front-end signal is oversampled at noise, can be used to calculate the effective resolution of the a relatively high sample rate, a subsequent digital filter is used to ADC as defined by the following equation: decimate the output, giving a valid 24-bit data conversion result at output rates from 1 Hz to 8 kHz. Effective Resolution = log2(Full-Scale Range/rms Noise) bits Note that, when software switches from one input to another The peak-to-peak noise is defined as the deviation of codes that (on the same ADC), the digital filter must first be cleared and fall within 6.6 × Sigma of the distribution of ADC output codes then allowed to average a new result. Depending on the con- collected when the ADC input voltage is at dc. The peak-to-peak figuration of the ADC and the type of filter, this can take noise is, therefore, calculated as multiple conversion cycles. 6.6 × rms Noise Integral Nonlinearity (INL) The peak-to-peak noise can be used to calculate the ADC INL is the maximum deviation of any code from a straight line (noise free code) resolution for which there is no code flicker passing through the endpoints of the transfer function. The end- within a 6.6-Sigma limit as defined by the following equation: points of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB Noise Free Code Resolution = log2 Full−ScaleRange bits above the last code transition (111 . . . 110 to 111 . . . 111). Peak−to−PeakNoise The error is expressed as a percentage of full scale. Data Sheet Acronyms No Missing Codes ADC analog-to-digital converter No missing codes is a measure of the differential nonlinearity ARM advanced RISC machine of the ADC. The error is expressed in bits and specifies the JTAG joint test action group number of codes (ADC results) as 2N bits, where N is no LSB least significant byte/bit missing codes guaranteed to occur through the full ADC LVF low voltage flag input range. MCU microcontroller Offset Error MMR memory mapped register Offset error is the deviation of the first code transition ADC MSB most significant byte/bit input voltage from the ideal first code transition. PID protected identifier Offset Error Drift POR power-on reset Offset error drift is the variation in absolute offset error with PSM power supply monitor respect to temperature. This error is expressed as least rms root mean square significant bits per degree Celsius. Gain Error Gain error is a measure of the span error of the ADC. It is a measure of the difference between the measured and the ideal span between any two points in the transfer function. Rev. F | Page 21 of 107

ADuC7060/ADuC7061 Data Sheet OVERVIEW OF THE ARM7TDMI CORE The ARM7® core is a 32-bit, reduced instruction set computer ARM7 Exceptions (RISC), developed by ARM® Ltd. The ARM7TDMI is a The ARM7 supports five types of exceptions, with a privileged von Neumann-based architecture, meaning that it uses a single processing mode associated with each type. The five types of 32-bit bus for instruction and data. The length of the data can exceptions are as follows: be 8, 16, or 32 bits, and the length of the instruction word is Type 1: normal interrupt or IRQ. This is provided to service either 16 bits or 32 bits, depending on the mode in which the general-purpose interrupt handling of internal and external core is operating. events. Note that the ADuC7060/ADuC7061 supports eight The ARM7TDMI is an ARM7 core with four additional configurable priority levels for all IRQ sources. features, as listed in Table 10. Type 2: fast interrupt or FIQ. This is provided to service data Table 10. ARM7TDMI Features transfer or a communication channel with low latency. FIQ Feature Description has priority over IRQ. Note that the ADuC7060/ADuC7061 T Support for the Thumb® (16-bit) instruction set supports eight configurable priority levels for all FIQ sources. D Support for debug Type 3: memory abort (prefetch and data). M Enhanced multiplier Type 4: attempted execution of an undefined instruction. I Includes the EmbeddedICE® module to support embedded system debugging Type 5: software interrupts (SWI) instruction that can be used THUMB MODE (T) to make a call to an operating system. Typically, the programmer defines interrupts as IRQ, but for An ARM instruction is 32 bits long. The ARM7TDMI processor higher priority interrupts, the programmer can define supports a second instruction set compressed into 16 bits, the interrupts as the FIQ type. Thumb instruction set. Faster code execution from 16-bit memory and greater code density is achieved by using the Thumb instruc- The priority of these exceptions and vector addresses are listed tion set, making the ARM7TDMI core particularly suited for in Table 11. embedded applications. Table 11. Exception Priorities and Vector Addresses However, the Thumb mode has three limitations. Priority Exception Address • Relative to ARM, the Thumb code usually requires more 1 Hardware reset 0x00 instructions to perform the same task. Therefore, ARM 2 Memory abort (data) 0x10 code is best for maximizing the performance of time- 3 FIQ 0x1C critical code in most applications. 4 IRQ 0x18 • The Thumb instruction set does not include some 5 Memory abort (prefetch) 0x0C instructions that are needed for exception handling, so 6 Software interrupt1 0x08 ARM code can be required for exception handling. 6 Undefined instruction1 0x04 • When an interrupt occurs, the core vectors to the interrupt 1 A software interrupt and an undefined instruction exception have the same location in memory and executes the code present at that priority and are mutually exclusive. address. The first command is required to be in ARM code. The exceptions listed in Table 11 are located from 0x00 to 0x1C, with a reserved location at 0x14. MULTIPLIER (M) ARM REGISTERS The ARM7TDMI instruction set includes an enhanced multiplier, with four extra instructions to perform 32-bit by The ARM7TDMI has 16 standard registers. R0 to R12 are for 32-bit multiplication with a 64-bit result, and 32-bit by 32-bit data manipulation, R13 is the stack pointer, R14 is the link multiplication-accumulation (MAC) with a 64-bit result. register, and R15 is the program counter that indicates the instruction currently being executed. The link register contains EmbeddedICE (I) the address from which the user has branched (when using the The EmbeddedICE module provides integrated on-chip debug branch and link command) or the command during which an support for the ARM7TDMI. The EmbeddedICE module exception occurred. contains the breakpoint and watchpoint registers that allow The stack pointer contains the current location of the stack. nonintrusive user code debugging. These registers are con- Generally, on an ARM7TDMI, the stack starts at the top of the trolled through the JTAG test port. When a breakpoint or available RAM area and descends using the area as required. A watchpoint is encountered, the processor halts and enters the separate stack is defined for each of the exceptions. The size of debug state. When in a debug state, the processor registers can each stack is user configurable and is dependent on the target be interrogated, as can the Flash/EE, SRAM, and memory application. When programming using high level languages, mapped registers. Rev. F | Page 22 of 107

Data Sheet ADuC7060/ADuC7061 such as C, it is necessary to ensure that the stack does not overflow. Note that the ARM7TDMI initially (first instruction) runs in This is dependent on the performance of the compiler that is used. ARM (32-bit) mode when an exception occurs. The user can immediately switch from ARM mode to Thumb mode if required, When an exception occurs, some of the standard registers are for example, when executing interrupt service routines. replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the MEMORY ORGANIZATION stack pointer (R13) and the link register (R14) as represented The ARM7, a von Neumann architecture MCU core, sees in Figure 9. The FIQ mode has more registers (R8 to R12) memory as a linear array of 232-byte locations. As shown in supporting faster interrupt processing. With the increased Figure 10, the ADuC7060/ADuC7061 maps this into four number of noncritical registers, the interrupt can be processed distinct user areas: a memory area that can be remapped, an without the need to save or restore these registers, thereby SRAM area, a Flash/EE area, and a memory mapped register reducing the response time of the interrupt handling process. (MMR) area. More information relative to the programmer’s model and the The first 30 kB of this memory space is used as an area into ARM7TDMI core architecture can be found in ARM7TDMI which the on-chip Flash/EE or SRAM can be remapped. Any technical and ARM architecture manuals available directly from access, either reading or writing, to an area not defined in the ARM Ltd. memory map results in a data abort exception. R0 USABLE IN USER MODE Memory Format R1 SYSTEM MODES ONLY The ADuC7060/ADuC7061 memory organization is configured R2 R3 in little endian format: the least significant byte is located in the R4 lowest byte address and the most significant byte in the highest R5 byte address (see Figure 11). R6 R7 R8_FIQ 0xFFFFFFFF R8 MMRs R9_FIQ R9 0xFFFF0000 R10_FIQ R10 R11_FIQ R13_UND RESERVED R11 R13_IRQ R12 R12_FIQ R13_SVC R13_ABT R14_IRQ R14_UND 0x00087FFF R13_FIQ R14_ABT FLASH/EE R13 R14_FIQ R14_SVC 0x00080000 R14 RESERVED R15 (PC) SPSR_UND 0x00040FFF SPSR_ABT SPSR_IRQ SRAM CPSR SPSR_SVC 0x00040000 SPSR_FIQ USER MODE FMigFOuIQDreE 9. RegMSiOsVtDCeEr OrgAaMBnOOizDRaETtion MIORQDE UNDMEOFDINEED 07079-004 0x000000000x00007FFF R(RFEELMSAEASRPHVP/EEAEDB OLER MSREMAMO)RY SPACE 07079-005 INTERRUPT LATENCY Figure 10. Memory Map The worst-case latency for an FIQ consists of the longest time BIT 31 BIT 0 that the request can take to pass through the synchronizer, plus BYTE 3 BYTE 2 BYTE 1 BYTE 0 . . . . the time for the longest instruction to complete (the longest . . . . 0xFFFFFFFF . . . . instruction is an LDM) that loads all the registers including the B A 9 8 PC, plus the time for the data abort entry, plus the time for FIQ 7 6 5 4 0x00000004 einnsttrryu. cAtito tnh ea te 0nxd1 Cof (tFhIiQs tiinmteer,r tuhpet AveRcMtor7 aTdDdMresIs )is. Texheec mutaixnigm tuhme 3 232 BITS1 0 0x00000000 07079-006 Figure 11. Little Endian Format total time is 50 processor cycles, or just over 4.88 μs in a system using a continuous 10.24 MHz processor clock. The maximum SRAM IRQ latency calculation is similar but must allow for the FIQ The ADuC7060/ADuC7061 features 4 kB of SRAM, organized having higher priority, which can delay entry into the IRQ as 1024 × 32 bits, that is, 1024 words located at 0x40000. The handling routine for an arbitrary length of time. This time can be RAM space can be used as data memory as well as volatile reduced to 42 cycles if the LDM command is not used; some program space. compilers have an option to compile without using this command. ARM code can run directly from SRAM at full clock speed Another option is to run the part in Thumb mode where this given that the SRAM array is configured as a 32-bit wide memory time is reduced to 22 cycles. array. SRAM is read/writable in 8-, 16-, and 32-bit segments. The minimum latency for FIQ or IRQ interrupts is five cycles. This consists of the shortest time that the request can take through the synchronizer plus the time to enter the exception mode. Rev. F | Page 23 of 107

ADuC7060/ADuC7061 Data Sheet Remap FLASH/EE CONTROL INTERFACE The ARM exception vectors are all situated at the bottom of the Serial and JTAG programming use the Flash/EE control memory array, from Address 0x00000000 to Address 0x00000020. interface, which includes the eight MMRs outlined in this By default, after a reset, the Flash/EE memory is logically section. Note that the flash page size is 512 bytes. mapped to Address 0x00000000. It is possible to logically remap FEESTA Register the SRAM to Address 0x00000000 by setting Bit 0 of the remap FEESTA is a read-only register that reflects the status of the MMR located at 0xFFFF0220. To revert Flash/EE to 0x00000000, flash control interface as described in Table 13. Bit 0 of remap is cleared. It is sometimes desirable to remap RAM to 0x00000000 to optimize Name: FEESTA the interrupt latency of the ADuC7060/ADuC7061 because code Address: 0xFFFF0E00 can run in full 32-bit ARM mode and at maximum core speed. Note that, when an exception occurs, the core defaults to ARM Default value: 0x0020 mode. Access: Read Remap Operation When a reset occurs on the ADuC7060/ADuC7061, execution Table 13. FEESTA MMR Bit Designations starts automatically in the factory programmed internal Bit Description configuration code. This so-called kernel is hidden and cannot 15:6 Reserved. be accessed by user code. If the ADuC7060/ADuC7061 is in 5 Reserved. normal mode, it executes the power-on configuration routine of 4 Reserved. the kernel and then jumps to the reset vector, 3 Flash interrupt status bit. Set automatically when an Address 0x00000000, to execute the user’s reset exception routine. interrupt occurs, that is, when a command is complete Because the Flash/EE is mirrored at the bottom of the memory and the Flash/EE interrupt enable bit in the FEEMOD array at reset, the reset routine must always be written in register is set. Cleared when reading the FEESTA register. Flash/EE. 2 Flash/EE controller busy. Set automatically when the The remap command must be executed from the absolute Flash/EE controller is busy. Cleared automatically when the address and not from the mirrored, remapped segment of memory, controller is not busy. because this may be replaced by SRAM. If a remap operation is 1 Command fail. Set automatically when a command executed while operating code from the mirrored location, pre- completes unsuccessfully. Cleared automatically when reading the FEESTA register. fetch/data aborts can occur, or the user can observe abnormal 0 Command pass. Set by the MicroConverter® when a program operation. Any kind of reset logically remaps the Flash/EE command completes successfully. Cleared memory to the bottom of the memory array. automatically when reading the FEESTA register. Remap Register FEEMOD Register Name: Remap FEEMOD sets the operating mode of the flash control interface. Address: 0xFFFF0220 Table 14 lists FEEMOD MMR bit designations. Default value: 0x0000 Name: FEEMOD Access: Read and write Address: 0xFFFF0E04 Function: This 8-bit register allows user code to remap Default value: 0x0000 either RAM or Flash/EE space into the bottom Access: Read and write of the ARM memory space starting at Address 0x00000000. Table 12. Remap MMR Bit Designations Bit Description 7:1 Reserved. These bits are reserved and should be written as 0 by user code. 0 Remap bit. Set by user to remap the SRAM to 0x00000000. Cleared automatically after reset to remap the Flash/EE memory to 0x00000000. Rev. F | Page 24 of 107

Data Sheet ADuC7060/ADuC7061 Table 14. FEEMOD MMR Bit Designations FEECON Register Bit Description FEECON is an 8-bit command register. The commands are 15:9 Reserved. described in Table 15. 8 Reserved. Always set this bit to 1. Name: FEECON 7:5 Reserved. Always set these bits to 0 except when writing keys. Address: 0xFFFF0E08 4 Flash/EE interrupt enable. Set by user to enable the Flash/EE interrupt. The Default value: 0x07 interrupt occurs when a command is complete. Cleared by user to disable the Flash/EE interrupt. Access: Read and write 3 Erase/write command protection. Set by user to enable the erase and write commands. Cleared to protect the Flash/EE against the erase/write command. 2:0 Reserved. Always set these bits to 0. Table 15. Command Codes in FEECON Code Command Description 0x001 Null Idle state. 0x011 Single read Load FEEDAT with the 16-bit data. Indexed by FEEADR. 0x021 Single write Write FEEDAT at the address pointed to by FEEADR. This operation takes 50 μs. 0x031 Erase/write Erase the page indexed by FEEADR and write FEEDAT at the location pointed to by FEEADR. This operation takes approximately 24 ms. 0x041 Single verify Compare the contents of the location pointed to by FEEADR to the data in FEEDAT. The result of the comparison is returned in FEESTA Bit 0 and Bit 1. 0x051 Single erase Erase the page indexed by FEEADR. 0x061 Mass erase Erase 30 kB of user space. The 2 kB of kernel are protected. To prevent accidental execution, a command sequence is required to execute this instruction. See the Command Sequence for Executing a Mass Erase section. 0x07 Reserved Reserved. 0x08 Reserved Reserved. 0x09 Reserved Reserved. 0x0A Reserved Reserved. 0x0B Signature This command results in a 24-bit LFSR-based signature being generated and loaded into the FEESIG MMR. This operation takes 16,389 clock cycles. 0x0C Protect This command can run only once. The value of FEEPRO is saved and is removed only with a mass erase (0x06) or the key. 0x0D Reserved Reserved. 0x0E Reserved Reserved. 0x0F Ping No operation; interrupt generated. 1 The FEECON register always reads 0x07 immediately after execution of any of these commands. Rev. F | Page 25 of 107

ADuC7060/ADuC7061 Data Sheet FEEDAT Register FEEHID Register FEEDAT is a 16-bit data register. This register holds the data The FEEHID MMR provides immediate protection. It does not value for flash read and write commands. require any software key. Note that the protection settings in FEEHID are cleared by a reset (see Table 16). Name: FEEDAT Name: FEEHID Address: 0xFFFF0E0C Address: 0xFFFF0E20 Default value: 0xXXXX Default value: 0xFFFFFFFF Access: Read and write Access: Read and write FEEADR Register Table 16. FEEPRO and FEEHID MMR Bit Designations FEEADR is a 16-bit address register used for accessing Bit Description individual pages of the 32 kB flash block. The valid address range for a user is: 0x0000 to 0x77FF. This represents the 30 kB 31 Read protection. Cleared by user to protect all code. No JTAG read flash user memory space. A read or write access outside this accesses for protected pages if this bit is cleared. boundary causes a data abort exception to occur. Set by the user to allow reading the code via JTAG. Name: FEEADR 30 Protection for Page 59 (0x00087600 to 0x000877FF). Set by the user to allow writing to Page 59. Cleared to Address: 0xFFFF0E10 protect Page 59. 29 Protection for Page 58 (0x00087400 to 0x000875FF). Default value: 0x0000 Set by the user to allow writing to Page 58. Cleared to protect Page 58. Access: Read and write 28:0 Write protection for Page 57 to Page 0. Each bit represents two pages. Each page is 512 bytes in size. Bit 0 is protection for Page 0 and Page 1 (0x00080000 FEESIG Register to 0x000803FF). Set by the user to allow writing Page 0 The FEESIG register is a 24-bit MMR. This register is updated and Page 1. Cleared to protect Page 0 and Page 1. with the 24-bit signature value after the signature command is Bit 1 is protection for Page 2 and Page 3 (0x00080400 executed. This value is the result of the linear feedback shift to 0x000807FF. Set by the user to allow writing Page 2 and Page 3. Cleared to protect Page 2 and Page 3. register (LFSR) operation initiated by the signature command. … Name: FEESIG … Bit 27 is protection for page 54 and page 55 (0x86C00 Address: 0xFFFF0E18 to 0x86FFF). Set by the user to allow writing to Page 54 and Page 55. Cleared to protect Page 54 and Page Default value: 0xFFFFFF 55. Bit 28 is protection for page 56 and page 57 (0x87000 Access: Read to 0x873FF). Set by the user to allow writing to Page 56 and Page 57. Cleared to protect Page 56 and Page 57. FEEPRO Register Temporary Protection The FEEPRO MMR provides protection following a subsequent Temporary protection can be set and removed by writing reset of the MMR. It requires a software key (see Table 16). directly into the FEEHID MMR. This register is volatile and, Name: FEEPRO therefore, protection is only in place for as long as the part remains powered on. The protection setting is not reloaded Address: 0xFFFF0E1C after a power cycle. Default value: 0x00000000 Keyed Permanent Protection Keyed permanent protection can be set via FEEPRO to lock the Access: Read and write protection configuration. The software key used at the start of the required FEEPRO write sequence is saved one time only and must be used for any subsequent access of the FEEHID or FEEPRO MMRs. A mass erase sets the software protection key back to 0xFFFF but also erases the entire user code space. Rev. F | Page 26 of 107

Data Sheet ADuC7060/ADuC7061 Permanent Protection Command Sequence for Executing a Mass Erase Permanent protection can be set via FEEPRO, similar to how FEEDAT = 0x3CFF; keyed permanent protection is set, with the only difference FEEADR = 0xFFC3; being that the software key used is 0xDEADDEAD. When the FEEMOD = FEEMOD|0x8; //Erase key enable FEECON = 0x06; //Mass erase command FEEPRO write sequence is saved, only a mass erase sets the software protection key back to 0xFFFFFFFF. This also erases the entire user code space. Sequence to Write the Software Protection Key and Set Permanent Protection 1. Write in FEEPRO corresponding to the pages to be protected. 2. Write the new (user-defined) 32-bit software protection key in FEEADR (Bits[31:16]) and FEEDAT (Bits[15:0]). 3. Write 10 in FEEMOD (Bits[6:5]) and set FEEMOD (Bit 3). 4. Run the protect command (Code 0x0C) in FEECON. To remove or modify the protection, the same sequence can be used with a modified value of FEEPRO. The previous sequence for writing the key and setting permanent protection is illustrated in the following example, this protects writing Page 4 and Page 5 of the Flash/EE: Int a = FEESTA; // Ensure FEESTA is cleared FEEPRO = 0xFFFFFFFB; // Protect Page 4 and Page 5 FEEADR = 0x66BB; // 32-bit key value (Bits[31:16]) FEEDAT = 0xAA55; // 32-bit key value (Bits[15:0]) FEEMOD = 0x0048 // Lock security sequence FEECON = 0x0C; // Write key command while (FEESTA & 0x04){} // Wait for command to finish Rev. F | Page 27 of 107

ADuC7060/ADuC7061 Data Sheet MEMORY MAPPED REGISTERS 0xFFFFFFFF The memory mapped register (MMR) space is mapped into the 0xFFFF0FC0 upper two pages of the memory array and is accessed by PWM 0xFFFF0F80 indirect addressing through the ARM7 banked registers. 0xFFFF0E24 FLASH CONTROL INTERFACE The MMR space provides an interface between the CPU and all 0xFFFF0E00 on-chip peripherals. All registers, except the core registers, reside 0xFFFF0D50 GPIO in the MMR area. All shaded locations shown in Figure 12 are 0xFFFF0D00 unoccupied or reserved locations and should not be accessed by 0xFFFF0A14 SPI user software. Figure 12 shows the full MMR memory map. 0xFFFF0A00 0xFFFF0948 The access time for reading from or writing to an MMR I2C 0xFFFF0900 depends on the advanced microcontroller bus architecture 0xFFFF0730 (AMBA) bus used to access the peripheral. The processor has UART 0xFFFF0700 two AMBA buses: the advanced high performance bus (AHB) 0xFFFF0620 used for system modules and the advanced peripheral bus DAC 0xFFFF0600 (APB) used for a lower performance peripheral. Access to the 0xFFFF0570 AHB is one cycle, and access to the APB is two cycles. All ADC 0xFFFF0500 peripherals on the ADuC7060/ADuC7061 are on the APB 0xFFFF0490 BAND GAP except for the Flash/EE memory, the GPIOs, and the PWM. REFERENCE 0xFFFF048C 0xFFFF0470 SPI/I2C SELECTION 0xFFFF0450 0xFFFF0420 PLL AND OSCILLATOR CONTROL 0xFFFF0404 0xFFFF0394 GENERAL-PURPOSE TIMER 0xFFFF0380 0xFFFF0370 WATCHDOG TIMER 0xFFFF0360 0xFFFF0350 WAKE-UP TIMER 0xFFFF0340 0xFFFF0334 GENERAL-PURPOSE TIMER 0xFFFF0320 0xFFFF0238 REMAP AND SYSTEM CONTROL 0xFFFF0220 00xxFFFFFFFF00104000 CIONNTTERRORULLPETR 07079-007 Figure 12. Memory Mapped Registers Rev. F | Page 28 of 107

Data Sheet ADuC7060/ADuC7061 COMPLETE MMR LISTING In the following MMR tables, addresses are listed in hexadecimal code. Access types include R for read, W for write, and R/W for read and write. Table 17. IRQ Address Base = 0xFFFF0000 Access Address Name Bytes Type Default Value Description 0x0000 IRQSTA 4 R 0x00000000 Active IRQ source status. 0x0004 IRQSIG 4 R Current state of all IRQ sources (enabled and disabled). 0x0008 IRQEN 4 R/W 0x00000000 Enabled IRQ sources. 0x000C IRQCLR 4 W 0x00000000 MMR to disable IRQ sources. 0x0010 SWICFG 4 W 0x00000000 Software interrupt configuration MMR. 0x0014 IRQBASE 4 R/W 0x00000000 Base address of all vectors. Points to the start of the 64-byte memory block, which can contain up to 32 pointers to separate subroutine handlers. 0x001C IRQVEC 4 R 0x00000000 This register contains the subroutine address for the currently active IRQ source. 0x0020 IRQP0 4 R/W 0x00000000 Contains the interrupt priority setting for Interrupt Source 1 to Interrupt Source 7. An interrupt can have a priority setting of 0 to 7. 0x0024 IRQP1 4 R/W 0x00000000 Contains the interrupt priority setting for Interrupt Source 8 to Interrupt Source 15. 0x0028 IRQP2 4 R/W 0x00000000 Contains the interrupt priority setting for Interrupt Source 16 to Interrupt Source 19. 0x0030 IRQCONN 4 R/W 0x00000000 Used to enable IRQ and FIQ interrupt nesting. 0x0034 IRQCONE 4 R/W 0x00000000 Configures the external interrupt sources as rising edge, falling edge, or level triggered. 0x0038 IRQCLRE 4 R/W 0x00000000 Used to clear an edge-level-triggered interrupt source. 0x003C IRQSTAN 4 R/W 0x00000000 This register indicates the priority level of an interrupt that has just caused an interrupt exception. 0x0100 FIQSTA 4 R 0x00000000 Active FIQ source status. 0x0104 FIQSIG 4 R Current state of all FIQ sources (enabled and disabled). 0x0108 FIQEN 4 R/W 0x00000000 Enabled FIQ sources. 0x010C FIQCLR 4 W 0x00000000 MMR to disable FIQ sources. 0x011C FIQVEC 4 R 0x00000000 This register contains the subroutine address for the currently active FIQ source. 0x013C FIQSTAN 4 R/W 0x00000000 Indicates the priority level of an FIQ that has just caused an FIQ exception. Table 18. System Control Address Base = 0xFFFF0200 Access Address Name Bytes Type Default Value Description 0x0220 REMAP1 1 R/W 0x00 Remap control register. See the Remap Operation section. 0x0230 RSTSTA 1 R/W 0x01 RSTSTA status MMR. See the Reset section. 0x0234 RSTCLR 1 W 0x00 Register for clearing the RSTSTA register. 1 Updated by the kernel. Rev. F | Page 29 of 107

ADuC7060/ADuC7061 Data Sheet Table 19. Timer Address Base = 0xFFFF0300 Access Address Name Bytes Type Default Value Description 0x0320 T0LD 4 R/W 0x00000000 Timer0 load register. 0x0324 T0VAL 4 R 0xFFFFFFFF Timer0 value register. 0x0328 T0CON 4 R/W 0x01000000 Timer0 control MMR. 0x032C T0CLRI 1 W N/A Timer0 interrupt clear register. 0x0330 T0CAP 4 R 0x00000000 Timer0 capture register. 0x0340 T1LD 4 R/W 0x00000000 Timer1 load register. 0x0344 T1VAL 4 R 0xFFFFFFFF Timer1 value register. 0x0348 T1CON 2 R/W 0x0000 Timer1 control MMR. 0x034C T1CLRI 1 W N/A Timer1 interrupt clear register. 0x0360 T2LD 2 R/W 0x3BF8 Timer2 load register. 0x0364 T2VAL 2 R 0x3BF8 Timer2 value register. 0x0368 T2CON 2 R/W 0x0000 Timer2 control MMR. 0x036C T2CLRI 1 W N/A Timer2 interrupt clear register. 0x0380 T3LD 2 R/W 0x0000 Timer3 load register. 0x0384 T3VAL 2 R 0xFFFF Timer3 value register. 0x0388 T3CON 4 R/W 0x00000000 Timer3 control MMR. 0x038C T3CLRI 1 W N/A Timer3 interrupt clear register. 0x0390 T3CAP 2 R 0x0000 Timer3 capture register. Table 20. PLL Base Address = 0xFFFF0400 Access Address Name Bytes Type Default Value Description 0x0404 POWKEY1 2 W 0xXXXX POWCON0 prewrite key. 0x0408 POWCON0 1 R/W 0x7B Power control and core speed control register. 0x040C POWKEY2 2 W 0xXXXX POWCON0 postwrite key. 0x0410 PLLKEY1 2 W 0xXXXX PLLCON prewrite key. 0x0414 PLLCON 1 R/W 0x00 PLL clock source selection MMR. 0x0418 PLLKEY2 2 W 0xXXXX PLLCON postwrite key. 0x0434 POWKEY3 2 W 0xXXXX POWCON1 prewrite key. 0x0438 POWCON1 2 R/W 0x124 Power control register. 0x043C POWKEY4 2 W 0xXXXX POWCON1 postwrite key. 0x0464 GP0KEY1 2 W 0xXXXX GP0CON1 prewrite key. 0x0468 GP0CON1 1 R/W 0x00 Configures P0.0, P0.1, P0.2, and P0.3 as analog inputs or digital I/Os. Also enables SPI or I2C mode. 0x046C GP0KEY2 2 W 0xXXXX GP0CON1 postwrite key. Rev. F | Page 30 of 107

Data Sheet ADuC7060/ADuC7061 Table 21. ADC Address Base = 0xFFFF0500 Access Address Name Bytes Type Default Value Description 0x0500 ADCSTA 2 R 0x0000 ADC status MMR. 0x0504 ADCMSKI 2 R/W 0x0000 ADC interrupt source enable MMR. 0x0508 ADCMDE 1 R/W 0x03 ADC mode register. 0x050C ADC0CON 2 R/W 0x8000 Primary ADC control MMR. 0x0510 ADC1CON 2 R/W 0x0000 Auxiliary ADC control MMR. 0x0514 ADCFLT 2 R/W 0x0007 ADC filter control MMR. 0x0518 ADCCFG 1 R/W 0x00 ADC configuration MMR. 0x051C ADC0DAT 4 R 0x00000000 Primary ADC result MMR. 0x0520 ADC1DAT 4 R 0x00000000 Auxiliary ADC result MMR 0x0524 ADC0OF1 2 R/W 0x0000, part specific, factory Primary ADC offset calibration setting. programmed 0x0528 ADC1OF1 2 R/W 0x0000, part specific, factory Auxiliary ADC offset MMR. programmed 0x052C ADC0GN1 2 R/W 0x5555 Primary ADC offset MMR. 0x0530 ADC1GN1 2 R/W 0x5555 Auxiliary ADC offset MMR. See the ADC operation mode configuration bit (ADCLPMCFG[1:0]) in Table 42. 0x0534 ADC0RCR 2 R/W 0x0001 Primary ADC result counter/reload MMR. 0x0538 ADC0RCV 2 R 0x0000 Primary ADC result counter MMR. 0x053C ADC0TH 2 R/W 0x0000 Primary ADC 16-bit comparator threshold MMR. 0x0540 ADC0THC 2 R/W 0x0001 Primary ADC 16-bit comparator threshold counter limit. 0x0544 ADC0THV 2 R 0x0000 ADC0 8-bit threshold exceeded counter register 0x0548 ADC0ACC 4 R 0x00000000 Primary ADC accumulator. 0x054C ADC0ATH 4 R/W 0x00000000 Primary ADC 32-bit comparator threshold MMR. 0x0570 IEXCON 1 R/W 0x00 Excitation current sources control register. 1 Updated by the kernel to part specific calibration value. Table 22. DAC Control Address Base = 0xFFFF0600 Access Address Name Bytes Type Default Value Description 0x0600 DAC0CON 2 R/W 0x0200 DAC control register. 0x0604 DAC0DAT 4 R/W 0x00000000 DAC output data register. Table 23. UART Base Address = 0xFFFF0700 Access Address Name Bytes Type Default Value Description 0x0700 COMTX 1 W N/A UART transmit register. 0x0700 COMRX 1 R 0x00 UART receive register. 0x0700 COMDIV0 1 R/W 0x00 UART Standard Baud Rate Generator Divisor Value 0. 0x0704 COMIEN0 1 R/W 0x00 UART Interrupt Enable MMR 0. 0x0704 COMDIV1 1 R/W 0x00 UART Standard Baud Rate Generator Divisor Value 1. 0x0708 COMIID0 1 R 0x01 UART Interrupt Identification 0. 0x070C COMCON0 1 R/W 0x00 UART Control Register 0. 0x0710 COMCON1 1 R/W 0x00 UART Control Register 1. 0x0714 COMSTA0 1 R 0x60 UART Status Register 0. 0x0718 COMSTA1 1 R 0x00 UART Status Register 1. 0X072C COMDIV2 2 R/W 0x0000 UART fractional divider MMR. Rev. F | Page 31 of 107

ADuC7060/ADuC7061 Data Sheet Table 24. I2C Base Address = 0xFFFF0900 Address Name Bytes Access Type Default Value Description 0x0900 I2CMCON 2 R/W 0x0000 I2C master control register. 0x0904 I2CMSTA 2 R 0x0000 I2C master status register. 0x0908 I2CMRX 1 R 0x00 I2C master receive register. 0x090C I2CMTX 1 W 0x00 I2C master transmit register. 0x0910 I2CMCNT0 2 R/W 0x0000 I2C master read count register. Write the number of required bytes into this register prior to reading from a slave device. 0x0914 I2CMCNT1 1 R 0x00 I2C master current read count register. This register contains the number of bytes already received during a read from slave sequence. 0x0918 I2CADR0 1 R/W 0x00 Address byte register. Write the required slave address here prior to communications. 0x091C I2CADR1 1 R/W 0x00 Address byte register. Write the required slave address here prior to communications. Only used in 10-bit mode. 0x0924 I2CDIV 2 R/W 0x1F1F I2C clock control register. Used to configure the SCLK frequency. 0x0928 I2CSCON 2 R/W 0x0000 I2C slave control register. 0x092C I2CSSTA 2 R/W 0x0000 I2C slave status register. 0x0930 I2CSRX 1 R 0x00 I2C slave receive register. 0x0934 I2CSTX 1 W 0x00 I2C slave transmit register. 0x0938 I2CALT 1 R/W 0x00 I2C hardware general call recognition register. 0x093C I2CID0 1 R/W 0x00 I2C Slave ID0 register. Slave bus ID register. 0x0940 I2CID1 1 R/W 0x00 I2C Slave ID1 register. Slave bus ID register. 0x0944 I2CID2 1 R/W 0x00 I2C Slave ID2 register. Slave bus ID register. 0x0948 I2CID3 1 R/W 0x00 I2C Slave ID3 register. Slave bus ID register. 0x094C I2CFSTA 2 R/W 0x0000 I2C FIFO status register. Used in both master and slave modes. Table 25. SPI Base Address = 0xFFFF0A00 Access Address Name Bytes Type Default Value Description 0x0A00 SPISTA 4 R 0x00000000 SPI status MMR. 0x0A04 SPIRX 1 R 0x00 SPI receive MMR. 0x0A08 SPITX 1 W 0x00 SPI transmit MMR. 0x0A0C SPIDIV 1 W 0x1B SPI baud rate select MMR. 0x0A10 SPICON 2 R/W 0x0000 SPI control MMR. Table 26. GPIO Base Address = 0xFFFF0D00 Access Address Name Bytes Type Default Value Description 0x0D00 GP0CON0 4 R/W 0x00000000 GPIO Port 0 control MMR. 0x0D04 GP1CON 4 R/W 0x00000000 GPIO Port 1 control MMR. 0x0D08 GP2CON 4 R/W 0x00000000 GPIO Port 2 control MMR. 0x0D20 GP0DAT 4 R/W 0x000000XX GPIO Port 0 data control MMR. 0x0D24 GP0SET 4 W 0x000000XX GPIO Port 0 data set MMR. 0x0D28 GP0CLR 4 W 0x000000XX GPIO Port 0 data clear MMR. 0x0D2C GP0PAR 4 R/W 0x00000000 GPIO Port 0 pull-up disable MMR. 0x0D30 GP1DAT 4 R/W 0x000000XX GPIO Port 1 data control MMR. 0x0D34 GP1SET 4 W 0x000000XX GPIO Port 1 data set MMR. 0x0D38 GP1CLR 4 W 0x000000XX GPIO Port 1 data clear MMR. 0x0D3C GP1PAR 4 R/W 0x00000000 GPIO Port 1 pull-up disable MMR. 0x0D40 GP2DAT 4 R/W 0x000000XX GPIO Port 2 data control MMR. 0x0D44 GP2SET 4 W 0x000000XX GPIO Port 2 data set MMR. 0x0D48 GP2CLR 4 W 0x000000XX GPIO Port 2 data clear MMR. 0x0D4C GP2PAR 4 R/W 0x00000000 GPIO Port 2 pull-up disable MMR. Rev. F | Page 32 of 107

Data Sheet ADuC7060/ADuC7061 Table 27. Flash/EE Base Address = 0xFFFF0E00 Access Address Name Bytes Type Default Value Description 0x0E00 FEESTA 2 R 0x20 Flash/EE status MMR. 0x0E04 FEEMOD 2 R/W 0x0000 Flash/EE control MMR. 0x0E08 FEECON 1 R/W 0x07 Flash/EE control MMR. 0x0E0C FEEDAT 2 R/W 0xXXXX Flash/EE data MMR. 0x0E10 FEEADR 2 R/W 0x0000 Flash/EE address MMR. 0x0E18 FEESIG 3 R 0xFFFFFF Flash/EE LFSR MMR. 0x0E1C FEEPRO 4 R/W 0x00000000 Flash/EE protection MMR. 0x0E20 FEEHID 4 R/W 0xFFFFFFFF Flash/EE protection MMR. Table 28. PWM Base Address = 0xFFFF0F80 Access Address Name Bytes Type Default Value Description 0x0F80 PWMCON 2 R/W 0x0012 PWM control register. See the Pulse-Width Modulator section for full details. 0x0F84 PWM0COM0 2 R/W 0x0000 Compare Register 0 for PWM Output 0 and PWM Output 1. 0x0F88 PWM0COM1 2 R/W 0x0000 Compare Register 1 for PWM Output 0 and PWM Output 1. 0x0F8C PWM0COM2 2 R/W 0x0000 Compare Register 2 for PWM Output 0 and PWM Output 1. 0x0F90 PWM0LEN 2 R/W 0x0000 Frequency control for PWM Output 0 and PWM Output 1. 0x0F94 PWM1COM0 2 R/W 0x0000 Compare Register 0 for PWM Output 2 and PWM Output 3. 0x0F98 PWM1COM1 2 R/W 0x0000 Compare Register 1 for PWM Output 2 and PWM Output 3. 0x0F9C PWM1COM2 2 R/W 0x0000 Compare Register 2 for PWM Output 2 and PWM Output 3. 0x0FA0 PWM1LEN 2 R/W 0x0000 Frequency control for PWM Output 2 and PWM Output 3. 0x0FA4 PWM2COM0 2 R/W 0x0000 Compare Register 0 for PWM Output 4 and PWM Output 5. 0x0FA8 PWM2COM1 2 R/W 0x0000 Compare Register 1 for PWM Output 4 and PWM Output 5. 0x0FAC PWM2COM2 2 R/W 0x0000 Compare Register 2 for PWM Output 4 and PWM Output 5. 0x0FB0 PWM2LEN 2 R/W 0x0000 Frequency control for PWM Output 4 and PWM Output 5. 0x0FB8 PWMCLRI 2 W 0x0000 PWM interrupt clear register. Writing any value to this register clears a PWM interrupt source. Rev. F | Page 33 of 107

ADuC7060/ADuC7061 Data Sheet RESET RSTCLR Register There are four kinds of resets: external reset, power-on reset, Name: RSTCLR watchdog reset, and software reset. The RSTSTA register indicates the source of the last reset and can be written by user Address: 0xFFFF0234 code to initiate a software reset event. Access: Write only The bits in this register can be cleared to 0 by writing to the RSTCLR MMR at 0xFFFF0234. The bit designations in Function: This 8-bit write only register clears the corres- RSTCLR mirror those of RSTSTA. These registers can be used ponding bit in RSTSTA. during a reset exception service routine to identify the source of the reset. The implications of all four kinds of reset events are Table 29. RSTSTA/RSTCLR MMR Bit Designations tabulated in Table 30. Bit Description 7:4 Not used. These bits are not used and always RSTSTA Register read as 0. Name: RSTSTA 3 External reset. Automatically set to 1 when an external reset Address: 0xFFFF0230 occurs. This bit is cleared by setting the corresponding bit Default value: Depends on type of reset in RSTCLR. Access: Read and write 2 Software reset. This bit is set to 1 by user code to generate a soft- Function: This 8-bit register indicates the source of the ware reset. last reset event and can be written by user code This bit is cleared by setting the corresponding bit to initiate a software reset. in RSTCLR.1 1 Watchdog timeout. Automatically set to 1 when a watchdog timeout occurs. Cleared by setting the corresponding bit in RSTCLR. 0 Power-on reset. Automatically set when a power-on reset occurs. Cleared by setting the corresponding bit in RSTCLR. 1 If the software reset bit in RSTSTA is set, any write to RSTCLR that does not clear this bit generates a software reset. Table 30. Device Reset Implications Reset Reset All RSTSTA External Pins to Kernel External MMRs Peripherals Watchdog RAM (Status After RESET Default State Executed (Excluding RSTSTA) Reset Timer Reset Valid Reset Event) POR Yes Yes Yes Yes Yes Yes/No RSTSTA[0] = 1 Watchdog Yes Yes Yes Yes No Yes RSTSTA[1] = 1 Software Yes Yes Yes Yes No Yes RSTSTA[2] = 1 External Pin Yes Yes Yes Yes No Yes RSTSTA[3] = 1 Rev. F | Page 34 of 107

Data Sheet ADuC7060/ADuC7061 OSCILLATOR, PLL, AND POWER CONTROL CLOCKING SYSTEM In case of crystal loss, the watchdog timer should be used. During initialization, a test on the RSTSTA can determine if the reset came The ADuC7060/ADuC7061 integrates a 32.768 kHz ±3% oscillator, a from the watchdog timer. clock divider, and a PLL. The PLL locks onto a multiple of the inter- nal oscillator or an external 32.768 kHz crystal to provide a stable External Clock Selection 10.24 MHz clock (UCLK) for the system. To allow power saving, To switch to an external clock on P2.0, configure P2.0 in Mode 0. the core can operate at this frequency or at binary submultiples The external clock can be up to 20.48 MHz, provided that the toler- of it. The actual core operating frequency, UCLK/2CD, is refered ance is 1%. The external clock is divided by 2 internally on the part. to as HCLK. The default core clock is the PLL clock divided by 8 Example source code (CD = 3) or 1.28 MHz. T1LD = 0x80; WATTICMHEDROG OSINCTIL. L32AkTHOzR* OSCCRIYLSLTAATLOR XXCCLLKKOI T1CON = 0xC0; IRQEN |= 0x10; // Enable Timer1 interrupt WAKE-UP OCLK PLLKEY1 = 0xAA; // Switch to external clock TIMER PLLCON = 0x4; 32.768kHz PLLKEY2 = 0x55; 10.24MHz PLL P2.0/EXTCLK POWKEY1 = 0x1; // Enter NAP mode I2C UCLK PERAINPAHLEORGALS POWCON0 = 0x73; POWKEY2 = 0xF4; CD /2CD The selection of the clock source is in the PLLCON register. By CORE HCLK default, the part uses the internal oscillator feeding the PLL. *32.768kHz±3% 07079-008 POWER CONTROL SYSTEM Figure 13. Clocking System The core clock frequency is changed by writing to the POWCON0 External Crystal Selection register. This is a key protected register; therefore, Register POWKEY1 To switch to an external crystal, users must follow this procedure: and Register POWKEY2 must be written to immediately before and after configuring the POWCON0 register. The following is a simple 1. Enable the Timer1 interrupt and configure it for a timeout example showing how to configure the core clock for 10.24 MHz: period of >120 µs. 2. Follow the write sequence to the PLLCON register, setting the POWKEY1 = 0x1; OSEL bits to [10] and clearing the EXTCLK bit. POWCON0 = 0x78; //Set core to max CPU 3. Force the part into nap mode by following the correct write //speed of 10.24 MHz sequence to the POWCON register. POWKEY2 = 0xF4; 4. When the part is interrupted from nap mode by the Timer1 A choice of operating modes is available on the ADuC7060/ interrupt source, the clock source has switched to the external ADuC7061. Table 33 describes what part is powered on in the crystal. different modes and indicates the power-up time. Example source code Table 34 gives some typical values for the total current consumption (analog + digital supply currents) in the different modes, depending T1LD = 0x80; // 32,768 clock ticks on the clock divider bits. The ADC is turned off. Note that these T1CON = 0xC0; // Periodic mode, enable values also include the current consumption of the regulator and // timer, 32,768 Hz clock/1 other parts on the test board where these values are measured. IRQEN |= 0x10; // Enable Timer1 interrupt // source PLLKEY1 = 0xAA; // Switch to external crystal PLLCON = 0x2; PLLKEY2 = 0x55; POWKEY1 = 0x1; // Enter nap mode POWCON0 = 0x73; POWKEY2 = 0xF4; Rev. F | Page 35 of 107

ADuC7060/ADuC7061 Data Sheet By writing to POWCON1, it is possible to further reduce power Power and Clock Control Registers consumption in active mode by powering down the UART, PWM POWKEY1 Register or I2C/SPI blocks. To access POWCON1, POWKEY3 must be set to Name: POWKEY1 0x76 in the instruction immediately before accessing POWCON1 and POWKEY4 must be set to 0xB1 in the instruction immediately Address: 0xFFFF0404 after. Default value: 0xXXXX For example, the following code enables the SPI/I2C blocks but, powers down the PWM and UART blocks. Access: Write POWKEY3 =0x76; Function: When writing to POWCON0, the value of 0x01 POWCON1 =0x4; //0x100 PWM; 0x20 must be written to this register in the instruction Uart; 0x4 SPI/I2C immediately before writing to POWCON0. POWKEY4 =0xB1; POWCON0 Register Name: POWCON0 Address: 0xFFFF0408 Default value: 0x7B Access: Read and write Function: This register controls the clock divide bits controlling the CPU clock (HCLK). Table 31. POWCON0 MMR Bit Designations Bit Name Description 7 Reserved This bit must always be set to 0. 6 XPD XTAL power-down. Cleared by user to power down the external crystal circuitry. Set by user to enable the external crystal circuitry. 5 PLLPD PLL power-down. Timer peripherals power down if driven from the PLL output clock. Timers driven from an active clock source remain in normal power mode. This bit is cleared to 0 to power down the PLL. The PLL cannot be powered down if either the core or peripherals are enabled; Bit 3, Bit 4, and Bit 5 must be cleared simultaneously. Set by default, and set by hardware on a wake-up event. 4 PPD Peripherals power-down. The peripherals that are powered down by this bit are as follows: SRAM, Flash/EE memory and GPIO interfaces, and SPI/I2C and UART serial ports. Cleared to power down the peripherals. The peripherals cannot be powered down if the core is enabled; Bit 3 and Bit 4 must be cleared simultaneously. Set by default and/or by hardware on a wake-up event. Wake-up timer (Timer1) can remain active. 3 COREPD Core power-down. If user code powers down the MCU, include a dummy MCU cycle after the power-down command is written to POWCON0. Cleared to power down the ARM core. Set by default and set by hardware on a wake-up event. 2:0 CD[2:0] Core clock depends on CD setting: [000] = 10.24 MHz [001] = 5.12 MHz [010] = 2.56 MHz [011] = 1.28 MHz [default value] [100] = 640 kHz [101] = 320 kHz [110] = 160 kHz [111] = 80 kHz Rev. F | Page 36 of 107

Data Sheet ADuC7060/ADuC7061 POWKEY2 Register POWCON1 Register Name: POWKEY2 Name: POWCON1 Address: 0xFFFF040C Address: 0xFFFF0438 Default value: 0xXXXX Default value: 0x124 Access: Write Access: Read and write Function: When writing to POWCON0, Function: This register controls the clock signal to the the value of 0xF4 must be PWM, UART and I2C/SPI blocks. written to this register in the By disabling the clock to these blocks, power instruction immediately consumption is reduced. before writing to POWCON0. POWKEY4 Register POWKEY3 Register Name: POWKEY4 Name: POWKEY3 Address: 0xFFFF043C Address: 0xFFFF0434 Default value: 0xXXXX Default value: 0xXXXX Access: Write Access: Write Function: When writing to POWCON1, the value of Function: When writing to POWCON1, the value of 0xB1 must be written to this register in the 0x76 must be written to this register in the instruction immediately after writing to instruction immediately before writing to POWCON1. POWCON1. Table 32. POWCON1 MMR Bit Designations Bit Name Description 15:9 Reserved This bit must always be set to 0. 8 PWMOFF PWM power-down bit. Set by user to 1 to enable the PWM block. This bit is set by default. Cleared by user to 0 to power down the PWM block. 7:6 Reserved Reserved bits. Always clear these bits to 0. 5 UARTOFF UART power-down bit. Set by user to 1 to enable the UART block. This bit is set by default. Cleared by user to 0 to power down the UART block. 4:3 Reserved Reserved bits. Always clear these bits to 0. 2 I2CSPIOFF I2C/SPI power-down bit. Set by user to 1 to enable the I2C/SPI blocks. This bit is set by default. Cleared by user to 0 to power down the I2C/SPI blocks. 1:0 Reserved Reserved Bits. Always clear these bits to 0. Table 33. ADuC7060/ADuC7061 Power Saving Modes POWCON0[6:3] Mode Core Peripherals PLL XTAL/T1/T2 IRQ0 to IRQ3 Start-Up/Power-On Time 1111 Active Yes Yes Yes Yes Yes 130 ms at CD = 0 1110 Pause Yes Yes Yes Yes 4.8 μs at CD = 0; 660 μs at CD = 7 1100 Nap Yes Yes Yes 4.8 μs at CD = 0; 660 μs at CD = 7 1000 Sleep Yes Yes 66 μs at CD = 0; 900 μs at CD = 7 0000 Stop Yes 66 μs at CD = 0; 900 μs at CD = 7 Rev. F | Page 37 of 107

ADuC7060/ADuC7061 Data Sheet Table 34. Typical Current Consumption at 25°C in mA1 POWCON0[6:3] Mode CD = 0 CD = 1 CD = 2 CD = 3 CD = 4 CD = 5 CD = 6 CD = 7 1111 Active2 5.22 4.04 2.69 2.01 1.67 1.51 1.42 1.38 1110 Pause3 2.6 1.95 1.6 1.49 1.4 1.33 1.31 1.3 1100 Nap3 1.33 1.29 1.29 1.29 1.29 1.29 1.29 1.29 1000 Sleep3 0.085 0.085 0.085 0.085 0.085 0.085 0.085 0.085 0000 Stop3 0.055 0.055 0.055 0.055 0.055 0.055 0.055 0.055 1 All values listed in Table 34 have been taken with both ADCs turned off. 2 In active mode, GP0PAR bit 7 =1. 3 The values for pause, nap, sleep, and stop modes are measured with the NTRST pin low. To minimize IDD due to nTRST in all modes, set GP0PAR Bit 7 =1. This disables the internal pull-down on the nTRST pin and means there is no ground path for the external pull-up resistor through the nTRST pin. By default, GP0PAR Bit 7 = 0, therefore, setting this bit in user code will not affect the BMoperation. Table 35. PLLCON MMR Bit Designations Name: PLLKEY1 Bit Name Description Address: 0xFFFF0410 7:3 Reserved These bits must always be set to 0. 2 EXTCLK Set this bit to 1 to select external clock input Default value: 0xXXXX from P2.0. Clear this bit to disable the external clock. Access: Write 1:0 OSEL Oscillator selection bits. Function: When writing to the PLLCON register, the [00] = internal 32,768 Hz oscillator. value of 0xAA must be written to this register [01] = internal 32,768 Hz oscillator. in the instruction immediately before writing [10] = external crystal. to PLLCON. [11] = internal 32,768 Hz oscillator. Name: PLLCON Name: PLLKEY2 Address: 0xFFFF0414 Address: 0xFFFF0418 Default value: 0x00 Default value: 0xXXXX Access: Read and write Access: Write Function: This register selects the clock input to the PLL. Function: When writing to PLLCON, the value of 0x55 must be written to this register in the instruction immediately after writing to PLLCON. Rev. F | Page 38 of 107

Data Sheet ADuC7060/ADuC7061 ADC CIRCUIT INFORMATION AVDD VREF+ VREF– DAC0 INTERNAL BUF IEXC0 REFERENCE DAC CONVERSION AVDD COUNTER IEXC1 50µA O/C DETECT AUX_REFP ADC0 AUX_REFM OVERRANGE ADC1 0.5Hz TO 8kHz Σ-∆ PROGRAMMABLE MODULATOR FILTER PGA CHOP INTERFACE MUX 0.2mA TO 1mA AND CONTROL TO ARM 0.2Hz TO 8kHz BUF MODUΣ-L∆ATOR PROGFRILATMEMRABLE ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 INTEGRATOR COMPARATORS ACCUMULATOR ADC8 ADC9 CHOP GND_SW MUX 50Ω AGND TEMPERATURE SENSOR 07079-009 Figure 14. Analog Block Diagram The ADuC7060/ADuC7061 incorporates two independent measurement of a wide dynamic range and low frequency multichannel Σ-Δ ADCs. The primary ADC is a 24-bit, signals such as those in pressure sensor, temperature sensor, 4-channel ADC. The auxiliary ADC is a 24-bit Σ-Δ ADC, weigh scale, or strain gage type applications. with up to seven single-ended input channels. The ADuC7060/ADuC7061 auxiliary ADC can be configured The primary ADC input has a mux and a programmable gain as four fully differential input channels or as seven single-ended amplifier on its input stage. The mux on the primary channel input channels. can be configured as two fully differential input channels or as Because of internal buffering, the internal channels can convert four single-ended input channels. signals directly from sensors without the need for external The auxiliary ADC incorporates a buffer on its input stage. signal conditioning. Digital filtering is present on both ADCs, which allows Rev. F | Page 39 of 107

ADuC7060/ADuC7061 Data Sheet Table 36. Primary ADC—Typical Output RMS Noise in Normal Mode (μV)1 Selectable Input Range ADC Data (PGA Settings) Register Update ±1.2 V ±600 mV ±300 mV ±150 mV ±75 mV ±37.5 mV ±18.75 mV ±9.375 mV ±4.68 mV ±2.34 mV Status Rate (PGA = 1) (PGA = 2) (PGA = 4) (PGA = 8) (PGA = 16) (PGA = 32) (PGA = 64) (PGA = 128) (PGA = 256) (PGA = 512) Chop On 4 Hz 0.62 μV 0.648 μV 0.175 μV 0.109 μV 0.077 μV 0.041 μV 0.032 μV 0.0338 μV 0.032 μV 0.033 μV Chop Off 50 Hz 1.97 μV 1.89 μV 0.570 μV 0.38 μV 0.27 μV 0.147 μV 0.123 μV 0.12 μV 0.098 μV 0.098 μV Chop Off 1 kHz 8.54 μV 8.4 μV 2.55 μV 1.6 μV 1.17 μV 0.658 μV 0.53 μV 0.55 μV 0.56 μV 0.52 μV Chop Off 8 kHz 54.97 μV 55.54 μV 14.30 μV 7.88 μV 4.59 μV 2.5 μV 1.71 μV 1.75 μV 0.915 μV 0.909 μV 1 The input voltage range is centered around the common-mode voltage and should meet the input voltage range specified in the Electrical Specifications section. Table 37. Primary ADC—Typical Output RMS Effective Number of Bits in Normal Mode (Peak-to-Peak Bits in Parentheses) ADC Data Input Voltage Noise (mV) Register Update ±1.2 V ±600 mV ±300 mV ±150 mV ±75 mV ±37.5 mV ±18.75 mV ±9.375 mV ±4.68 mV ±2.34 mV Status Rate (PGA = 1) (PGA = 2) (PGA = 4) (PGA = 8) (PGA = 16) (PGA = 32) (PGA = 64) (PGA = 128) (PGA = 256) (PGA = 512) Chop On 4 Hz 21.9 20.8 21.7 21.4 20.9 20.8 20.2 19.1 18.2 17.1 (19.1 p-p) (18.1 p-p) (19.0 p-p) (18.7 p-p) (18.2 p-p) (18.1 p-p) (17.4 p-p) (16.4 p-p) (15.4 p-p) (14.4 p-p) Chop Off 50 Hz 20.2 19.3 20.0 19.6 19.1 19.0 18.2 17.3 16.6 15.5 (17.5 p-p) (16.6 p-p) (17.3 p-p) (16.9 p-p) (16.4 p-p) (16.2 p-p) (15.5 p-p) (14.6 p-p) (13.8 p-p) (12.8 p-p) Chop Off 1 kHz 18.1 17.1 17.8 17.5 17.0 16.8 16.1 15.1 14.0 13.1 (15.3 p-p) (14.4 p-p) (15.1 p-p) (14.8 p-p) (14.2 p-p) (14.1 p-p) (13.4 p-p) (12.3 p-p) (11.3 p-p) (10.4 p-p) Chop Off 8 kHz 15.4 14.4 15.4 15.2 15.0 14.9 14.4 13.4 13.3 12.3 (12.7 p-p) (11.7 p-p) (12.6 p-p) (12.5 p-p) (12.3 p-p) (12.2 p-p) (11.7 p-p) (10.7 p-p) (10.6 p-p) (9.6 p-p) Table 38. Auxilary ADC—Typical Output RMS Noise Similarly, if an external reference source of greater than 1.35 V Data is used for ADC1, the HIGHEXTREF1 bit must be set in ADC Register Update Rate RMS Value ADC1CON. Chop On 4 Hz 0.633 μV DIAGNOSTIC CURRENT SOURCES Chop On 10 Hz 0.810 μV Chop Off 1 kHz 7.4 μV To detect a connection failure to an external sensor, the Chop Off 8 kHz 54.18 μV ADuC7060/ADuC7061 incorporates a 50 μA constant current source on the selected analog input channels to both the REFERENCE SOURCES primary and auxiliary ADCs. Both the primary and auxiliary ADCs have the option of using The diagnostic current sources for the primary ADC analog the internal reference voltage or one of two external differential inputs are controlled by the ADC0DIAG[1:0] bits in the reference sources. The first external reference is applied to the ADC0CON register. VREF+/VREF− pins. The second external reference is applied Similarly, the diagnostic current sources for the auxiliary ADC to the ADC4/EXT_REF2IN+ and ADC5/EXT_REF2IN− pins. analog inputs are controlled by the ADC1DIAG[1:0] bits in the By default, each ADC uses the internal 1.2 V reference source. ADC1CON register. For details on how to configure the external reference source for the primary ADC, see the description of the ADC0REF[1:0] bits in the ADC0 control register, ADC0CON. A B ADC0 (+) For details on how to configure the external reference source for AVDD R1 VIN = ADC0, the auxiliary ADC, see the description of the ADC1REF[2:0] ADC1 bits in the ADC1 control register, ADC1CON. A B ADC1 (–) R2 Ifof ra nA eDxCte0r,n tahle r eHfeIGreHncEeX sTouRrEcFe 0o fb igtr meautesrt bthea sne t1 i.n35 A VD iCs 0nCeeOdNed. 07079-010 Figure 15. Example Circuit Using Diagnostic Current Sources Rev. F | Page 40 of 107

Data Sheet ADuC7060/ADuC7061 Table 39. Example Scenarios for Using Diagnostic Current Sources Diagnostic Test Detected Measurement Register Setting Description Normal Result Fault Result for Fault ADC0DIAG[1:0] = 0 Convert ADC0/ADC1 as normal with Expected differential result Short circuit. Primary ADC reading ≈ 0 diagnostic currents disabled. across ADC0/ADC1. V regardless of PGA setting. ADC0DIAG[1:0] = 1 Enable a 50 μA diagnostic current Main ADC changes by Short circuit Primary ADC reading ≈ 0 source on ADC0 by setting ΔV = +50 μA × R1. For between ADC0 V regardless of PGA ADC0DIAG[1:0] = 1. Convert ADC0 and example, ~100 mV for R1 = and ADC1. setting. ADC1. 2 kΩ. Short circuit between R1_a and R1_b. Convert ADC0 in single-ended mode Expected voltage on ADC0. ADC0 open Primary ADC reading = with diagnostic currents disabled. circuit or R1 +full scale, even on the open circuit. lowest PGA setting. ADC0DIAG[1:0] = 3 Enable a 50 μA diagnostic current Primary ADC changes by ΔV R1 does not Primary ADC reading > source on both ADC0 and ADC1 by = 50 μA × (R1 − R2), that is, match R2. 10 mV. setting ADC0DIAG[1:0] = 3. Convert ~10 mV for 10% tolerance. ADC0 and ADC1. SINC3 FILTER a current range of 200 μA to 1 mA. The current step sizes are 200 μA. These current sources can be used to excite an external The number entered into Bits[6:0] of the ADCFLT register sets resistive bridge or RTD sensors. The IEXCON MMR controls the decimation factor of the sinc3 filter. See Table 46 and Table 47 the excitation current sources. Bit 6 of IEXCON must be set to for further details on the decimation factor values. enable Excitation Current Source 0. Similarly, Bit 7 must be set The range of operation of the sinc3 filter (SF) word depends on to enable Excitation Current Source 1. The output current of whether the chop function is enabled. With chopping disabled, each current source is controlled by the IOUT[3:0] bits of this the minimum SF word allowed is 0 and the maximum is 127, register. giving an ADC throughput range of 50 Hz to 8 kHz. It is also possible to configure the excitation current sources to For details on how to calculate the ADC sampling frequency output current to a single output pin, either IEXC0 or IEXC1, based on the value programmed to the SF[6:0] bits in the by using the IEXC0_DIR and IEXC1_DIR bits of IEXCON. This ADCFLT register, refer to Table 46. When changing conversions allows up to 2 mA to output current on a single excitation pin. speeds, put ADC into idle mode before restarting. ADC LOW POWER MODE ADC CHOPPING The ADuC7060/ADuC7061 allows the primary and auxiliary ADCs to be placed in low power operating mode. When The ADCs on the ADuC7060/ADuC7061 implements a configured for this mode, the ADC throughput time is reduced, chopping scheme whereby the ADC repeatedly reverses its but the power consumption of the primary ADC is reduced by a inputs. Therefore, the decimated digital output values from the factor of about 4; the auxiliary ADC power consumption is sinc3 filter have a positive and negative offset term associated reduced by a factor of roughly 3. The maximum ADC with them. This results in the ADC including a final summing conversion rate in low power mode is 2 kHz. The operating stage that sums and averages each value from the filter with mode of the ADCs is controlled by the ADCMDE register. This previous filter output values. This new value is then sent to the register configures the part for either normal mode (default), ADC data MMR. This chopping scheme results in excellent dc low power mode, or low power plus mode. Low power plus offset and offset drift specifications and is extremely beneficial mode is the same as low power mode except that the PGA is in applications where drift and noise rejection are required. disabled. To place the ADCs into low power mode, the PROGRAMMABLE GAIN AMPLIFIER following steps must be completed: The primary ADC incorporates an on-chip programmable gain • ADCMDE[4:3]—Setting these bits enables normal mode, amplifier (PGA). The PGA can be programmed through 10 low power mode, or low power plus mode. different settings giving a range of 1 to 512. The gain is • ADCMDE[5]—Setting this bit configures the part for low controlled by the ADC0PGA[3:0] bits in the ADC0CON MMR. power mode. EXCITATION SOURCES • ADCMDE[7]—Clearing this bit further reduces power The ADuC7060/ADuC7061 contains two matched software consumption by reducing the frequency of the ADC clock. configurable current sources. These excitation currents are sourced from AVDD. They are individually configurable to give Rev. F | Page 41 of 107

ADuC7060/ADuC7061 Data Sheet ADC COMPARATOR AND ACCUMULATOR ADC MMR INTERFACE Every primary ADC result can be compared to a preset The ADCs are controlled and configured through a number of threshold level (ADC0TH) as configured via ADCCFG[4:3]. An MMRs that are described in detail in the following sections. MCU interrupt is generated if the absolute (sign independent) In response to an ADC interrupt, user code should interrogate value of the ADC result is greater than the preprogrammed the ADCSTA MMR to determine the source of the interrupt. comparator threshold level. An extended function of this Each ADC interrupt source can be individually masked via the comparator function allows user code to configure a threshold ADCMSKI MMR described in Table 41. counter (ADC0THV) to monitor the number of primary ADC All primary ADC result ready bits are cleared by a read of the results that have occurred above or below the preset threshold ADC0DAT MMR. If the primary channel ADC is not enabled, level. Again, an ADC interrupt is generated when the threshold all ADC result ready bits are cleared by a read of the ADC1DAT counter reaches a preset value (ADC0RCR). MMR. To ensure that primary ADC and auxiliary ADC Finally, a 32-bit accumulator (ADC0ACC) function can be conversion data are synchronous, user code should first read configured (ADCCFG[6:5]) allowing the primary ADC to add the ADC1DAT MMR and then the ADC0DAT MMR. New (or subtract) multiple primary ADC sample results. User code ADC conversion results are not written to the ADCxDAT can read the accumulated value directly (ADC0ACC) without MMRs unless the respective ADC result ready bits are first any further software processing. cleared. The only exception to this rule is the data conversion TEMPERATURE SENSOR result updates when the ARM core is powered down. In this mode, ADCxDAT registers always contain the most recent The ADuC7060/ADuC7061 provides a voltage output from an ADC conversion result even though the ready bits are not on-chip band gap reference proportional to absolute cleared. temperature. This voltage output can also be routed through the front-end auxiliary ADC multiplexer (effectively, an additional ADC Status Register ADC channel input), facilitating an internal temperature sensor Name: ADCSTA channel that measures die temperature. Address: 0xFFFF0500 The internal temperature sensor is not designed for use as an absolute ambient temperature calculator. It is intended Default value: 0x0000 for use as an approximate indicator of the temperature of the ADuC7060/ADuC7061 die. Access: Read only The typical temperature coefficient is 0.28 mV/°C. Function: This read-only register holds general status 140 information related to the mode of operation or current status of the ADuC7060/ADuC7061 120 ADCs. 100 V) m T ( 80 U P T U O 60 C D A 40 20 0 –60 –40 –20 0 TE2M0PERA40TURE60(°C) 80 100 120 140 07079-034 Figure 16. ADC Output vs. Temperature Rev. F | Page 42 of 107

Data Sheet ADuC7060/ADuC7061 Table 40. ADCSTA MMR Bit Designations Bit Name Description 15 ADCCALSTA ADC calibration status. This bit is set automatically in hardware to indicate that an ADC calibration cycle has been completed. This bit is cleared after ADCMDE is written to. 14 Not used. This bit is reserved for future functionality. 13 ADC1CERR Auxiliary ADC conversion error. This bit is set automatically in hardware to indicate that an auxiliary ADC conversion overrange or underrange has occurred. The conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case. This bit is cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register. 12 ADC0CERR Primary ADC conversion error. This bit is set automatically in hardware to indicate that a primary ADC conversion overrange or underrange has occurred. The conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case. This bit is cleared when a valid (in-range) conversion result is written to the ADC0DAT register. 11:7 Not used. These bits are reserved for future functionality and should not be monitored by user code. 6 ADC0ATHEX ADC0 accumulator comparator threshold exceeded. This bit is set when the ADC0 accumulator value in ADC0ACC exceeds the threshold value programmed in the ADC0 comparator threshold register, ADC0ATH. This bit is cleared when the value in ADC0ACC does not exceed the value in ADC0ATH. 5 Not used. This bit is reserved for future functionality and should not be monitored by user code. 4 ADC0THEX Primary channel ADC comparator threshold. This bit is valid only if the primary channel ADC comparator is enabled via the ADCCFG MMR. This bit is set by hardware if the absolute value of the primary ADC conversion result exceeds the value written in the ADC0TH MMR. If the ADC threshold counter is used (ADC0RCR), this bit is set only when the specified number of primary ADC conversions equals the value in the ADC0THV MMR. Otherwise, this bit is cleared. 3 ADC0OVR Primary channel ADC overrange bit. If the overrange detect function is enabled via the ADCCFG MMR, this bit is set by hardware if the primary ADC input is grossly (>30% approximate) overrange. This bit is updated every 125 µs. After it is set, this bit can be cleared only by software when ADCCFG[2] is cleared to disable the function, or the ADC gain is changed via the ADC0CON MMR. 2 Not used. This bit is reserved for future functionality and should not be monitored by user code. 1 ADC1RDY Auxiliary ADC result ready bit. If the auxiliary channel ADC is enabled, this bit is set by hardware as soon as a valid conversion result is written in the ADC1DAT MMR. It is also set at the end of a calibration sequence. This bit is cleared by reading ADC1DAT followed by reading ADC0DAT. ADC0DAT must be read to clear this bit, even if the primary ADC is not enabled. 0 ADC0RDY Primary ADC result ready bit. If the primary channel ADC is enabled, this bit is set by hardware as soon as a valid conversion result is written in the ADC0DAT MMR. It is also set at the end of a calibration sequence. This bit is cleared by reading ADC0DAT. Rev. F | Page 43 of 107

ADuC7060/ADuC7061 Data Sheet ADC Interrupt Mask Register Name: ADCMSKI Address: 0xFFFF0504 Default value: 0x0000 Access: Read and write Function: This register allows the ADC interrupt sources to be enabled individually. The bit positions in this register are the same as the lower eight bits in the ADCSTA MMR. If a bit is set by user code to 1, the respective interrupt is enabled. By default, all bits are 0, meaning all ADC interrupt sources are disabled. Table 41. ADCMSKI MMR Bit Designations Bit Name Description 7 Not used. This bit is reserved for future functionality and should not be monitored by user code. 6 ADC0ATHEX_INTEN ADC0 accumulator comparator threshold exceeded interrupt enable bit. When set to 1, this bit enables an interrupt when the ADC0ATHEX bit in the ADCSTA register is set. When this bit is cleared, this interrupt source is disabled. 5 Not used. This bit is reserved for future functionality and should not be monitored by user code. 4 ADC0THEX_INTEN Primary channel ADC comparator threshold exceeded interrupt enable bit. When set to 1, this bit enables an interrupt when the ADC0THEX bit in the ADCSTA register is set. When this bit is cleared, this interrupt source is disabled. 3 ADC0OVR_INTEN When set to 1, this bit enables an interrupt when the ADC0OVR bit in the ADCSTA register is set. When this bit is cleared, this interrupt source is disabled. 2 Not used. This bit is reserved for future functionality and should not be monitored by user code. 1 ADC1RDY_INTEN Auxiliary ADC result ready bit. When set to 1, this bit enables an interrupt when the ADC1RDY bit in the ADCSTA register is set. When this bit is cleared, this interrupt source is disabled. 0 ADC0RDY_INTEN Primary ADC result ready bit. When set to 1, this bit enables an interrupt when the ADC0RDY bit in the ADCSTA register is set. When this bit is cleared, this interrupt source is disabled. ADC Mode Register Name: ADCMDE Address: 0xFFFF0508 Default value: 0x03 Access: Read and write Function: The ADC mode MMR is an 8-bit register that configures the mode of operation of the ADC subsystem. Table 42. ADCMDE MMR Bit Designations Bit Name Description 7 ADCCLKSEL Set this bit to 1 to enable ADCCLK = 512 kHz. This bit should be set for normal ADC operation. Clear this bit to enable ADCCLK = 131 kHz. This bit should be cleared for low power ADC operation. 6 Not used. This bit is reserved for future functionality and should not be monitored by user code. 5 ADCLPMEN Enable low power mode. This bit has no effect if ADCMDE[4:3] = 00 (ADC is in normal mode). This bit must be set to 1 in low power mode. Clearing this bit in low power mode results in erratic ADC results. Rev. F | Page 44 of 107

Data Sheet ADuC7060/ADuC7061 Bit Name Description 4:3 ADCLPMCFG[1:0] ADC power mode configuration. [00] = ADC normal mode. If enabled, the ADC operates with normal current consumption yielding optimum electrical performance. [01] = ADC low power mode. [10] = ADC normal mode, same as [00]. [11] = ADC low power plus mode (low power mode and PGA off). 2:0 ADCMD[2:0] ADC operation mode configuration. [000] = ADC power-down mode. All ADC circuits and the input amplifier are powered down. [001] = ADC continuous conversion mode. In this mode, any enabled ADC continuously converts at a frequency equal to f . ADCxRDY must be cleared to enable new data to be written to ADC0DAT/ADC1DAT. ADC [010] = ADC single conversion mode. In this mode, any enabled ADC performs a single conversion. The ADC enters idle mode when the single shot conversion is complete. A single conversion takes two to three ADC clock cycles, depending on the chop mode. [011] = ADC idle mode. In this mode, the ADC is fully powered on but is held in reset. The part enters this mode after calibration. [100] = ADC self-offset calibration. In this mode, an offset calibration is performed on any enabled ADC using an internally generated 0 V. The calibration is carried out at the user-programmed ADC settings; therefore, as with a normal single ADC conversion, it takes two to three ADC conversion cycles before a fully settled calibration result is ready. The calibration result is automatically written to the ADCxOF MMR of the respective ADC. The ADC returns to idle mode, and the calibration and conversion ready status bits are set at the end of an offset calibration cycle. Note: Always use ADC0 for single-ended self-calibration cycles on the primary ADC. Always use ADC0/ADC1 when self-calibrating for a differential input to the primary ADC. [101] = ADC self-gain calibration. In this mode, a gain calibration against an internal reference voltage is performed on all enabled ADCs. A gain calibration is a two-stage process and takes twice the time of an offset calibration. The calibration result is automatically written to the ADCxGN MMR of the respective ADC. The ADC returns to idle mode and the calibration and conversion ready status bits are set at the end of a gain calibration cycle. An ADC self-gain calibration should only be carried out on the primary channel ADC. Note that self-gain calibration works only when the gain = 1; do not use it when the gain > 1. [110] = ADC system zero-scale calibration. In this mode, a zero-scale calibration is performed on enabled ADC channels against an external zero-scale voltage driven at the ADC input pins. To do this, short the channel externally. [111] = ADC system full-scale calibration. In this mode, a full-scale calibration is performed on enabled ADC channels against an external full-scale voltage driven at the ADC input pins. The ADCxGN register is updated after a full-scale calibration sequence. Primary ADC Control Register Name: ADC0CON Address: 0xFFFF050C Default value: 0x8000 Access: Read and write Function: The primary channel ADC control MMR is a 16-bit register. If the primary ADC is reconfigured via ADC0CON, the auxiliary ADC is also reset. Rev. F | Page 45 of 107

ADuC7060/ADuC7061 Data Sheet Table 43. ADC0CON MMR Bit Designations Bit Name Description 15 ADC0EN Primary channel ADC enable. This bit is set to 1 by user code to enable the primary ADC. Clearing this bit to 0 powers down the primary ADC and resets the respective ADC ready bit in the ADCSTA MMR to 0. 14:13 ADC0DIAG[1:0] Diagnostic current source enable bits. [00] = current sources off. [01] = enables a 50 μA current source on the selected positive input (for example, ADC0). [10] = enables a 50 μA current source on the selected negative input (for example, ADC1). [11] = enables a 50 μA current source on both selected inputs (for example, ADC0 and ADC1). 12 HIGHEXTREF0 This bit must be set high if the external reference for ADC0 exceeds 1.35 V. This results in the reference source being divided by 2. Clear this bit when using the internal reference or an external reference of less than 1.35 V. 11 AMP_CM This bit is set to 1 by user to set the PGA output common-mode voltage to AVDD/2. This bit is cleared to 0 by user code to set the PGA output common-mode voltage to the PGA input common- mode voltage level. 10 ADC0CODE Primary channel ADC output coding. This bit is set to 1 by user code to configure primary ADC output coding as unipolar. This bit is cleared to 0 by user code to configure primary ADC output coding as twos complement. 9:6 ADC0CH[3:0] Primary channel ADC input select. Note that single-ended channels are selected with respect to ADC5. Bias ADC5 to a minimum level of 0.1 V. [0000] = ADC0/ADC1 (differential mode). [0001] = ADC0/ADC5 (single-ended mode). [0010] = ADC1/ADC5 (single-ended mode). [0011] = VREF+, VREF−. Note: This is the reference selected by the ADC0REF bits. [0100] = Not used. This bit combination is reserved for future functionality and should not be written. [0101] = ADC2/ADC3 (differential mode). [0110] = ADC2/ADC5 (single-ended mode). [0111] = ADC3/ADC5 (single-ended mode). [1000] = internal short to ADC1. [1001] = internal short to ADC1. 5:4 ADC0REF[1:0] Primary channel ADC reference select. [00] = internal reference selected. In ADC low power mode, the voltage reference selection is controlled by ADCMDE[5]. [01] = external reference inputs (VREF+, VREF−) selected. Set the HIGHEXTREF0 bit if the reference voltage exceeds 1.3 V. [10] = auxiliary external reference inputs (ADC4/EXT_REF2IN+, ADC5/EXT_REF2IN−) selected. Set the HIGHEXTREF0 bit if the reference voltage exceeds 1.3 V. [11] = (AVDD, AGND) divide-by-two selected. 3:0 ADC0PGA[3:0]. Primary channel ADC gain select. Note, nominal primary ADC full-scale input voltage = (VREF/gain). [0000] = ADC0 gain of 1. Buffer of negative input is bypassed. [0001] = ADC0 gain of 2. [0010] = ADC0 gain of 4 (default value). Enables the in-amp. [0011] = ADC0 gain of 8. [0100] = ADC0 gain of 16. [0101] = ADC0 gain of 32. [0110] = ADC0 gain of 64 (maximum PGA gain setting). [0111] = ADC0 gain of 128 (extra gain implemented digitally). [1000] = ADC0 gain of 256. [1001] = ADC0 gain of 512. [1XXX] = ADC0 gain is undefined. Rev. F | Page 46 of 107

Data Sheet ADuC7060/ADuC7061 Auxiliary ADC Control Register Name: ADC1CON Address: 0xFFFF0510 Default value: 0x0000 Access: Read and write Function: The auxiliary ADC control MMR is a 16-bit register. Table 44. ADC1CON MMR Bit Designations Bit Name Description 15 ADC1EN Auxiliary channel ADC enable. This bit is set to 1 by user code to enable the auxiliary ADC. Clearing this bit to 0 powers down the auxiliary ADC. 14:13 ADC1DIAG[1:0] Diagnostic current source enable bits. This is the same current source as that used on ADC0DIAG[1:0]. The ADCs cannot enable the diagnostic current sources at the same time. [00]= current sources off. [01] = enables a 50 μA current source on selected positive input (for example, ADC2). [10] = enables a 50 μ A current source on selected negative input (for example, ADC3). [11] = enables a 50 μ A current source on both selected inputs (for example, ADC2 and ADC3). 12 HIGHEXTREF1 This bit must be set high if the external reference for ADC1 exceeds 1.35 V. This results in the reference source being divided by 2. Clear this bit when using the internal reference or an external reference of less than 1.35 V. 11 ADC1CODE Auxiliary channel ADC output coding. This bit is set to 1 by user code to configure auxiliary ADC output coding as unipolar. This bit is cleared to 0 by user code to configure auxiliary ADC output coding as twos complement. 10:7 ADC1CH[3:0] Auxiliary channel ADC input select. Note: Single-ended channels are selected with respect to ADC5. Bias ADC5 to a minimum level of 0.1 V. [0000] = ADC2/ADC3 (differential mode). [0001] = ADC4/ADC5 (differential mode). [0010] = ADC6/ADC7 (differential mode). [0011] = ADC8/ADC9 (differential mode). [0100] = ADC2/ADC5 (single-ended mode). [0101] = ADC3/ADC5 (single-ended mode). [0110] = ADC4/ADC5 (single-ended mode). [0111] = ADC6/ADC5 (single-ended mode). [1000] = ADC7/ADC5 (single-ended mode). [1001] = ADC8/ADC5 (single-ended mode). [1010] = ADC9/ADC5 (single-ended mode). [1011] = internal temperature sensor+/internal temperature sensor−. [1100] = VREF+, VREF−. Note: This is the reference selected by the ADC1REF bits. [1101] = DAC_OUT/AGND. [1110] = undefined. [1111] = internal short to ADC3. Rev. F | Page 47 of 107

ADuC7060/ADuC7061 Data Sheet Bit Name Description 6:4 ADC1REF[2:0] Auxiliary channel ADC reference select. [000] = internal reference selected. In ADC low power mode, the voltage reference selection is controlled by ADCMODE[5]. [001] = external reference inputs (VREF+, VREF−) selected. Set the HIGHEXTREF1 bit if reference voltage exceeds 1.3 V. [010] = auxiliary external reference inputs (ADC4/EXT_REF2IN+, ADC5/EXT_REF2IN−) selected. Set the HIGHEXTREF1 bit if reference voltage exceeds 1.35 V. [011] = (AVDD, AGND) divide-by-2 selected. If this configuration is selected, the HIGHEXTREF1 bit is set automatically. [100] = (AVDD, ADC3). ADC3 can be used as the negative input terminal for the reference source. [101] to [111] = reserved. 3:2 BUF_BYPASS[1:0] Buffer bypass. [00] = full buffer on. Both positive and negative buffer inputs active. [01] = negative buffer is bypassed, positive buffer is on. [10] = negative buffer is on, positive buffer is bypassed. [11] = full buffer bypass. Both positive and negative buffer inputs are off. 1:0 Digital gain. Select for auxiliary ADC inputs. [00] = ADC1 gain = 1. [01] = ADC1 gain = 2. [10] = ADC1 gain = 4. [11] = ADC1 gain = 8. ADC Filter Register Name: ADCFLT Address: 0xFFFF0514 Default value: 0x0007 Access: Read and write Function: The ADC filter MMR is a 16-bit register that controls the speed and resolution of both the on-chip ADCs. Note that, if ADCFLT is modified, the primary and auxiliary ADCs are reset. When changing conversions speeds, put the ADC into idle mode before restarting. Table 45. ADCFLT MMR Bit Designations Bit Name Description 15 CHOPEN Chop enable. Set by user to enable system chopping of all active ADCs. When this bit is set, the ADC has very low offset errors and drift, but the ADC output rate is reduced by a factor of 3 if AF = 0 (see sinc3 decimation factor, Bits[6:0] in this table). If AF > 0, then the ADC output update rate is the same with chop on or off. When chop is enabled, the settling time is two output periods. 14 RAVG2 Running average-by-2 enable bit. Set by user to enable a running-average-by-2 function, reducing ADC noise. This function is automatically enabled when chopping is active. It is an optional feature when chopping is inactive, and if enabled (when chopping is inactive), does not reduce the ADC output rate but does increase the settling time by one conversion period. Cleared by user to disable the running average function. 13:8 AF[5:0] Averaging factor (AF). The values written to these bits are used to implement a programmable first-order sinc3 post filter. The averaging factor can further reduce ADC noise at the expense of output rate as described in Bits[6:0] (sinc3 decimation factor) in this table. Rev. F | Page 48 of 107

Data Sheet ADuC7060/ADuC7061 Bit Name Description 7 NOTCH2 Sinc3 modify. Set by user to modify the standard sinc3 frequency response to increase the filter stop-band rejection by approximately 5 dB. This is achieved by inserting a second notch (NOTCH2) at f = 1.333 × f NOTCH2 NOTCH where f is the location of the first notch in the response. NOTCH 6:0 SF[6:0] Sinc3 decimation factor (SF).1 The value (SF) written in these bits controls the oversampling (decimation factor) of the sinc3 filter. The output rate from the sinc3 filter is given by f = (512,000/([SF + 1] × 64)) Hz2 ADC when the chop bit (Bit 15, chop enable) = 0 and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125. For SF = 126, f is forced to 60 Hz. ADC For SF = 127, f is forced to 50 Hz. ADC For information on calculating the f for SF (other than 126 and 127) and AF values, refer to Table 46. ADC 1 Due to limitations on the digital filter internal data path, there are some limitations on the combinations of the sinc3 decimation factor (SF) and averaging factor (AF) that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in normal power mode to 4 Hz or 1 Hz in lower power mode. 2 In low power mode, the ADC is driven directly by the low power oscillator (131 kHz) and not 512 kHz. All fADC calculations should be divided by 4 (approximately). Table 46. ADC Conversion Rates and Settling Times Chop Averaging Running Enabled Factor Average f Normal Mode f Low Power Mode t 1 ADC ADC SETTLING No No No 512,000 131,072 3 [SF+1]×64 [SF+1]×64 fADC No No Yes 512,000 131,072 4 [SF+1]×64 [SF+1]×64 fADC No Yes No 512,000 131,072 1 [SF+1]×64×[3+AF] [SF+1]×64×[3+AF] fADC No Yes Yes 512,000 131,072 2 [SF+1]×64×[3+AF] [SF+1]×64×[3+AF] fADC Yes N/A N/A 512,000 131,072 2 [SF+1]×64×[3+AF]+3 [SF+1]×64×[3+AF]+3 fADC 1 An additional time of approximately 60 µs per ADC is required before the first ADC is available. Table 47. Allowable Combinations of SF and AF AF Range SF 0 1 to 7 8 to 63 0 to 31 Yes Yes Yes 32 to 63 Yes Yes No 64 to 127 Yes No No Rev. F | Page 49 of 107

ADuC7060/ADuC7061 Data Sheet ADC Configuration Register Name: ADCCFG Address: 0xFFFF0518 Default value: 0x00 Access: Read and write Function: The 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs. Table 48. ADCCFG MMR Bit Designations Bit Name Description 7 GNDSW_EN Analog ground switch enable. This bit is set to 1 by user software to connect the external GND_SW pin to an internal analog ground reference point. This bit can be used to connect and disconnect external circuits and components to ground under program control and thereby minimize dc current consumption when the external circuit or component is not being used. This bit is used in conjunction with ADCCFG[1] to select a 20 kΩ resistor to ground. When this bit is cleared, the analog ground switch is disconnected from the external pin. 6:5 ADC0ACCEN[1:0] Primary channel (32-bit) accumulator enable. [00] = accumulator disabled and reset to 0. The accumulator must be disabled for a full ADC conversion (ADCSTA[0] set twice) before the accumulator can be re-enabled to ensure that the accumulator is reset. [01] = accumulator active. Positive current values are added to the accumulator total; the accumulator can overflow if allowed to run for >65,535 conversions. Negative current values are subtracted from the accumulator total; the accumulator is clamped to a minimum value of 0. [10] = accumulator active. Same as [01] except that there is no clamp. Positive current values are added to the accumulator total; the accumulator can overflow if allowed to run for >65,535 conversions. The absolute values of negative current are subtracted from the accumulator total; the accumulator in this mode continues to accumulate negatively, below 0. [11] = accumulator and comparator active. This causes an ADC0 interrupt if ADCMSKI[6] is set. 4:3 ADC0CMPEN[1:0] Primary ADC comparator enable bits. [00] = comparator disabled. [01] = comparator active. Interrupt asserted if absolute value of ADC0 conversion result |I| ≥ ADC0TH. [10] = comparator count mode active. Interrupt asserted if absolute value of ADC0 conversion result |I| ≥ ADC0TH for the number of ADC0THC conversions. A conversion value |I| < ADC0TH resets the threshold counter value (ADC0THV) to 0. [11] = comparator count mode active, interrupt asserted if absolute value of ADC0 conversion result |I| ≥ ADC0TH for the number of ADC0THC conversions. A conversion value |I| < ADC0TH decrements the threshold counter value (ADC0THV) toward 0. 2 ADC0OREN ADC0 overrange enable. Set by the user to enable a coarse comparator on the primary channel ADC. If the reading is grossly (>30% approximate) overrange for the active gain setting, the overrange bit in the ADCSTA MMR is set. The ADC reading must be outside this range for greater than 125 µs for the flag to be set. Do not use this feature in ADC low power mode. 1 GNDSW_RES_EN Set to 1 to enable a 20 kΩ resistor in series with the ground switch. Clear this bit to disable this resistor. 0 ADCRCEN ADC result counter enable. Set by user to enable the result count mode. ADC interrupts occur if ADC0RCR = ADC0RCV. Cleared to disable the result counter. ADC interrupts occur after every conversion. Rev. F | Page 50 of 107

Data Sheet ADuC7060/ADuC7061 Primary Channel ADC Data Register Primary Channel ADC Offset Calibration Register Name: ADC0DAT Name: ADC0OF Address: 0xFFFF051C Address: 0xFFFF0524 Default value: 0x00000000 Default value: Part specific, factory programmed Access: Read only Access: Read and write Function: This ADC data MMR holds the 24-bit Function: This ADC offset MMR holds a 16-bit offset conversion result from the primary ADC. The calibration coefficient for the primary ADC. ADC does not update this MMR if the ADC0 The register is configured at power-on with a conversion result ready bit (ADCSTA[0]) is factory default value. However, this register set. A read of this MMR by the MCU clears automatically overwrites if an offset all asserted ready flags (ADCSTA[1:0]). calibration of the primary ADC is initiated by the user via bits in the ADCMDE MMR. User code can write to this calibration register only Table 49. ADC0DAT MMR Bit Designations if the ADC is in idle mode. An ADC must be Bit Description enabled and in idle mode before being 23:0 ADC0 24-bit conversion result. written to any offset or gain register. The ADC must be in idle mode for at least 23 µs. Auxiliary Channel ADC Data Register Name: ADC1DAT Table 51. ADC0OF MMR Bit Designations Bit Description Address: 0xFFFF0520 15:0 ADC0 16-bit offset calibration value. Default value: 0x00000000 Auxiliary Channel ADC Offset Calibration Register Access: Read only Name: ADC1OF Function: This ADC data MMR holds the 24-bit Address: 0xFFFF0528 conversion result from the auxiliary ADC. The ADC does not update this MMR if the Default value: Part specific, factory programmed ADC0 conversion result ready bit (ADCSTA[1]) is set. Access: Read and write Function: This offset MMR holds a 16-bit offset Table 50. ADC1DAT MMR Bit Designations calibration coefficient for the auxiliary Bit Description channel. The register is configured at power- 23:0 ADC1 24-bit conversion result. on with a factory default value. However, this register is automatically overwritten if an offset calibration of the auxiliary channel is initiated by the user via bits in the ADCMDE MMR. User code can write to this calibration register only if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 µs. Table 52. ADC1OF MMR Bit Designations Bit Description 15:0 ADC1 16-bit offset calibration value. Rev. F | Page 51 of 107

ADuC7060/ADuC7061 Data Sheet Primary Channel ADC Gain Calibration Register Primary Channel ADC Result Counter Limit Register Name: ADC0GN Name: ADC0RCR Address: 0xFFFF052C Address: 0xFFFF0534 Default value: Part specific, factory programmed Default value: 0x0001 Access: Read and write Access: Read and write Function: This gain MMR holds a 16-bit gain Function: This 16-bit MMR sets the number of calibration coefficient for scaling the primary conversions required before an ADC ADC conversion result. The register is interrupt is generated. By default, this configured at power-on with a factory default register is set to 0x01. The ADC counter value. However, this register is automatically function must be enabled via the ADC result overwritten if a gain calibration of the counter enable bit in the ADCCFG MMR. primary ADC is initiated by the user via bits Table 55. ADC0RCR MMR Bit Designations in the ADCMDE MMR. User code can write Bits Description to this calibration register only if the ADC is 15:0 ADC0 result counter limit/reload register. in idle mode. An ADC must be enabled and in idle mode before being written to any Primary Channel ADC Result Counter Register offset or gain register. The ADC must be in idle mode for at least 23 μs. Name: ADC0RCV Table 53. ADC0GN MMR Bit Designations Address: 0xFFFF0538 Bits Description 15:0 ADC0 16-bit calibration gain value. Default value: 0x0000 Access: Read only Auxiliary Channel Gain Calibration Register Name: ADC1GN Function: This 16-bit, read-only MMR holds the current number of primary ADC conversion Address: 0xFFFF0530 results. It is used in conjunction with ADC0RCR to mask primary channel ADC Default value: Part specific, factory programmed interrupts, generating a lower interrupt rate. Access: Read and write When ADC0RCV = ADC0RCR, the value in ADC0RCV resets to 0 and recommences Function: This gain MMR holds a 16-bit gain calibra- counting. It can also be used in conjunction tion coefficient for scaling an auxiliary channel with the accumulator (ADC0ACC) to allow conversion result. The register is configured an average calculation to be taken. The at power-on with a factory default value. result counter is enabled via ADCCFG[0]. However, this register is automatically over- This MMR is also reset to 0 when the written if a gain calibration of the auxiliary primary ADC is reconfigured, that is, when channel is initiated by the user via bits in the the ADC0CON or ADCMDE is written. ADCMDE MMR. User code can write to this calibration register only if the ADC is in idle Table 56. ADC0RCV MMR Bit Designations mode. An ADC must be enabled and in idle Bits Description mode before being written to any offset or gain 15:0 ADC0 result counter register. register. The ADC must be in idle mode for at least 23 µs. Table 54. ADC1GN MMR Bit Designations Bits Description 15:0 ADC1 16-bit gain calibration value. Rev. F | Page 52 of 107

Data Sheet ADuC7060/ADuC7061 Primary Channel ADC Threshold Register Primary Channel ADC Threshold Counter Register Name: ADC0TH Name: ADC0THV Address: 0xFFFF053C Address: 0xFFFF0544 Default value: 0x0000 Default value: 0x0000 Access: Read and write Access: Read only Function: This 16-bit MMR sets the threshold against Function: This 8-bit MMR is incremented every time which the absolute value of the primary ADC the absolute value of a primary ADC conversion result is compared. In unipolar conversion result |Result| ≥ ADC0TH. This mode, ADC0TH[15:0] are compared, and in register is decremented or reset to 0 every twos complement mode, ADC0TH[14:0] are time the absolute value of a primary ADC compared. conversion result |Result| < ADC0TH. The configuration of this function is enabled via Table 57. ADC0TH MMR Bit Designations the primary channel ADC comparator bits in Bit Description the ADCCFG MMR. 15:0 ADC0 16-bit comparator threshold register. Table 59. ADC0THV MMR Bit Designations Primary Channel ADC Threshold Counter Limit Register Bit Description Name: ADC0THC 7:0 ADC0 8-bit threshold exceeded counter register. Address: 0xFFFF0540 Primary Channel ADC Accumulator Register Name: ADC0ACC Default value: 0x0001 Address: 0xFFFF0548 Access: Read and write Default value: 0x00000000 Function: This 8-bit MMR determines how many cumulative (values below the threshold Access: Read only decrement or reset the count to 0) primary ADC conversion result readings above Function: This 32-bit MMR holds the primary ADC ADC0TH must occur before the primary accumulator value. The primary ADC ready bit ADC comparator threshold bit is set in the in the ADCSTA MMR should be used to ADCSTA MMR, generating an ADC determine when it is safe to read this MMR. interrupt. The primary ADC comparator The MMR value is reset to 0 by disabling the threshold bit is asserted as soon as accumulator in the ADCCFG MMR or by ADC0THV = ADC0RCR. reconfiguring the primary channel ADC. Table 60. ADC0ACC MMR Bit Designations Table 58. ADC0THC MMR Bit Designations Bit Description Bit Description 31:0 ADC0 32-bit accumulator register. 15:8 Reserved. 7:0 ADC0 8-bit threshold counter limit register. Rev. F | Page 53 of 107

ADuC7060/ADuC7061 Data Sheet Primary Channel ADC Comparator Threshold Register Table 61. ADC0ATH MMR Bit Designations Bit Description Name: ADC0ATH 31:0 ADC0 32-bit comparator threshold register of the Address: 0xFFFF054C accumulator. Default value: 0x00000000 Access: Read and write Function: This 32-bit MMR holds the threshold value for the accumulator comparator of the primary channel. When the accumulator value in ADC0ACC exceeds the value in ADC0ATH, the ADC0ATHEX bit in ADCSTA is set. This causes an interrupt if the corresponding bit in ADCMSKI is also enabled. INTERRUPT (ADC0OVR) FAST OVERRANGE (READABLE) ADC0 PRIMARY 16 ADC0ACC 32 ADC1 ADC fADC ACCUMULATOR ≥ INTERRUPT fADC (READABLE) (ADC0ATHEX) ADC0ATH |ABSVAL| ADC0RCV CLEAR COUNTER fADC ≥ I(NATDECR0RRDUYP)T ≥ fADC UAPD/CD0OTWHVN (DEAFDACU0RLTC R= 1) ADC0TH OPTION: UP/RESET ≥ I(NATDECR0RTHUEPXT) ADC0THC 07079-011 Figure 17. Primary ADC Accumulator/Comparator/Counter Block Diagram Rev. F | Page 54 of 107

Data Sheet ADuC7060/ADuC7061 Excitation Current Sources Control Register Name: IEXCON Address: 0xFFFF0570 Default value: 0x00 Access: Read and write Function: This 8-bit MMR controls the two excitation current sources, IEXC0 and IEXC1. Table 62. IEXCON MMR Bit Designations Bit Name Description 7 IEXC1_EN Enable bit for IEXC1 current source. Set this bit to 1 to enable Excitation Current Source 1. Clear this bit to disable Excitation Current Source 1. 6 IEXC0_EN Enable bit for IEXC0 current source. Set this bit to 1 to enable Excitation Current Source 0. Clear this bit to disable Excitation Current Source 0. 5 IEXC1_DIR Set this bit to 1 to direct Excitation Current Source 1 to the IEXC0 pin. Set this bit to 0 to direct Excitation Current Source 1 to the IEXC1 pin. 4 IEXC0_DIR Set this bit to 1 to direct Excitation Current Source 0 to the IEXC1 pin. Set this bit to 0 to direct Excitation Current Source 0 to the IEXC0 pin. 3:1 IOUT[3:1] These bits control the excitation current level for each source. IOUT[3:1] = 000, excitation current = 0 μA + (IOUT[0] × 10 μA). IOUT[3:1] = 001, excitation current = 200 μA + (IOUT[0] × 10 μA). IOUT[3:1] = 010, excitation current = 400 μA + (IOUT[0] × 10 μA). IOUT[3:1] = 011, excitation current = 600 μA + (IOUT[0] × 10 μA). IOUT[3:1] = 100, excitation current = 800 μA + (IOUT[0] × 10 μA). IOUT[3:1] = 101, excitation current = 1 mA + (IOUT[0] × 10 μA). All other values are undefined. 0 IOUT[0] Set this bit to 1 to enable 10 μA diagnostic current source. Clear this bit to 0 to disable 10 μA diagnostic current source. EXAMPLE APPLICATION CIRCUITS In Figure 19, the AD592 is an external temperature sensor used to Figure 18 shows a simple bridge sensor interface to the measure the thermocouple cold junction, and its output is con- ADuC7060/ADuC7061, including the RC filters on the analog nected to the auxiliary channel. The ADR280 is an external 1.2 V input channels. Notice that the sense lines from the bridge reference part—alternatively, the internal reference can be used. (connecting to the reference inputs) are wired separately from Here, the thermocouple is connected to the primary ADC as the excitation lines (going to DVDD/AVDD and ground). This a differential input to ADC0/ADC1. Note the resistor between results in a total of six wires going to the bridge. This 6-wire VREF+ and ADC1 to bias the ADC inputs above 100 mV. connection scheme is a feature of most off-the-shelf bridge Figure 20 shows a simple 4-wire RTD interface circuit. As with transducers (such as load cells) that helps to minimize errors the bridge transducer implementation in Figure 18, if a power that would otherwise result from wire impedances. supply and a serial connection to the outside world are added, Figure 20 represents a complete system. Rev. F | Page 55 of 107

ADuC7060/ADuC7061 Data Sheet ADuC7060/ ADuC7060/ ADuC7061 ADuC7061 +2.5V +2.5V AVDD/DVDD IEXC1 AVDD/DVDD VREF+ ADC0 SPI SPI ADC0 I2C RTD I2C UART UART ADC1 GPIO ADC1 GPIO VREF– VREF+ AGND/DGND 07079-012 VREF– AGND/DGND 07079-014 Figure 18. Bridge Interface Circuit Figure 20. Example of an RTD Interface Circuit ADuC7060/ ADuC7061 +2.5V ADC0 AVDD/DVDD ADC1 SPI I2C UART AD592 ADC4 GPIO ADR280 VREF+ VREF– AGND/DGND 07079-013 Figure 19. Example of a Thermocouple Interface Circuit Rev. F | Page 56 of 107

Data Sheet ADuC7060/ADuC7061 DAC PERIPHERALS Op Amp Mode DAC As an option, the DAC can be disabled and its output buffer The ADuC7060/ADuC7061 incorporates a voltage output DAC used as an op amp. on chip. In normal mode, the DAC resolution is 12-bits. In interpolation, the DAC resolution is 16 bits with 14 effective MMR INTERFACE bits. The DAC has a rail-to-rail voltage output buffer capable of The DAC is configurable through a control register and a data driving 5 kΩ/100 pF. register. The DAC has four selectable ranges. DAC0CON Register • 0 V to VREF (internal band gap 1.2 V reference) Name: DAC0CON • VREF− to VREF+ • ADC5/EXT_REF2IN− to ADC4/EXT_REF2IN+ Address: 0xFFFF0600 • 0 V to AVDD Default value: 0x0200 The maximum signal range is 0 V to AVDD. Access: Read and write Table 63. DAC0CON MMR Bit Designations Bit Name Description 15:10 Reserved. 9 DACPD Set to 1 to power down DAC output (DAC output is tristated). Clear this bit to enable the DAC. 8 DACBUFLP Set to 1 to place the DAC output buffer in low power mode. See the Normal DAC Mode and Op Amp Mode sections for further details on electrical specifications. Clear this bit to enable the DAC buffer. 7 OPAMP Set to 1 to place the DAC output buffer in op amp mode. Clear this bit to enable the DAC output buffer for normal DAC operation. 6 DACBUFBYPASS Set to 1 to bypass the output buffer and send the DAC output directly to the output pin. Clear this bit to buffer the DAC output. 5 DACCLK Cleared to 0 to update the DAC on the negative edge of HCLK. Set to 1 to update the DAC on the negative edge of Timer0. This mode is ideally suited for waveform generation where the next value in the waveform is written to DAC0DAT at regular intervals of Timer0. 4 DACCLR Set to 1 for normal DAC operation. Set to 0 to clear the DAC output and to set DAC0DAT to 0. Writing to this bit has an immediate effect on the DAC output. 3 DACMODE Set to 1 to enable the DAC in 16-bit interpolation mode. Set to 0 to enable the DAC in normal 12-bit mode. 2 Rate Used with interpolation mode. Set to 1 to configure the interpolation clock as UCLK/16. Set to 0 to configure the interpolation clock as UCLK/32. 1:0 DAC range bits [11] = 0 V to AVDD range. [10] = ADC5/EXT_REF2IN− to ADC4/EXT_REF2IN+. [01] = VREF− to VREF+. [00] = 0 V to V (1.2 V) range. Internal reference source. REF Rev. F | Page 57 of 107

ADuC7060/ADuC7061 Data Sheet DAC0DAT Register Code 4095. Linearity degradation near ground and AVDD is caused by saturation of the output amplifier, and a general Name: DAC0DAT representation of its effects (neglecting offset and gain error) is Address: 0xFFFF0604 illustrated in Figure 21. The dotted line in Figure 21 indicates the ideal transfer function, and the solid line represents what the Default value: 0x00000000 transfer function may look like with endpoint nonlinearities due Access: Read and write to saturation of the output amplifier. Note that Figure 21 repre- sents a transfer function in 0-to-AVDD mode only. In 0-to-V Function: This 32-bit MMR contains the DAC output REF or, VREF±, and ADCx/EXT_REF2IN± modes (with V < AVDD value. REF or ADCx/EXT_REF2IN± < AVDD), the lower nonlinearity is Table 64. DAC0DAT MMR Bit Designations similar. However, the upper portion of the transfer function Bit Description follows the ideal line all the way to the end (VREF in this case, not 31:28 Reserved. AVDD), showing no signs of endpoint linearity errors. 27:16 12-bit data for DAC0. 15:12 Extra four bits used in interpolation mode. AVDD AVDD– 100mV 11:0 Reserved. USING THE DAC The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier. The reference source for the DAC is user selectable in software. It can be AVDD, VREF±, or ADCx/EXT_REF2IN±.  In 0-to-AVDD mode, the DAC output transfer function 100mV  sInp aVnRs EfrFo±m a 0n dV A toD tChxe /vEoXltTa_gRe EatF t2hIeN A±V mDoDd epsi,n t.h e DAC 0x00000000 0x0FFF0000 07079-015 Figure 21. Endpoint Nonlinearities Due to Amplifier Saturation output transfer function spans from negative input voltage to the voltage positive input pin. Note that these voltages The endpoint nonlinearities conceptually illustrated in Figure 21 must never go below 0 V or above AVDD. worsen as a function of output loading. Most of the  In 0-to-VREF mode, the DAC output transfer function spans ADuC7060/ADuC7061 data sheet specifications in normal from 0 V to the internal 1.2 V reference, V . mode assume a 5 kΩ resistive load to ground at the DAC REF output. As the output is forced to source or sink more current, The DAC can be configured in three different user modes: the nonlinear regions at the top or bottom (respectively) of normal mode, DAC interpolation mode, and op amp mode. Figure 21 become larger. With larger current demands, this can Normal DAC Mode significantly limit output voltage swing. In this mode of operation, the DAC is configured as a 12-bit DAC Interpolation Mode voltage output DAC. By default, the DAC buffer is enabled, but In interpolation mode, a higher DAC output resolution of 16 bits the output buffer can be disabled. If the DAC output buffer is is achieved with a longer update rate than normal mode. The disabled, the DAC is capable of driving a capacitive load of only update rate is controlled by the interpolation clock rate selected 20 pF. The DAC buffer is disabled by setting the DACBUFBYPASS in the DAC0CON register. In this mode, an external RC filter is bit in DAC0CON. required to create a constant voltage. The DAC output buffer amplifier features a true, rail-to-rail Op Amp Mode output stage implementation. This means that when unloaded, In op amp mode, the DAC output buffer is used as an op amp each output is capable of swinging to within less than 5 mV of with the DAC itself disabled. both AVDD and ground. Moreover, the linearity specification of the DAC (when driving a 5 kΩ resistive load to ground) is guar- ADC6 is the positive input to the op amp, ADC7 is the negative anteed through the full transfer function except for Code 0 input, and ADC8 is the output. In this mode, the DAC should to Code 100 and, in 0-to- AVDD mode only, Code 3995 to be powered down by setting Bit 9 of DAC0CON. Rev. F | Page 58 of 107

Data Sheet ADuC7060/ADuC7061 NONVOLATILE FLASH/EE MEMORY The ADuC7060/ADuC7061 incorporates Flash/EE memory Retention quantifies the ability of the Flash/EE memory to technology on chip to provide the user with nonvolatile, in-circuit retain its programmed data over time. Again, the parts are reprogrammable memory space. qualified in accordance with the formal JEDEC Retention Lifetime Specification A117 at a specific junction temperature Like EEPROM, flash memory can be programmed in-system (T = 85°C). As part of this qualification procedure, the Flash/ at a byte level, although it must first be erased. The erase is J EE memory is cycled to its specified endurance limit, described performed in page blocks. As a result, flash memory is often previously, before data retention is characterized. This means and, more correctly, referred to as Flash/EE memory. that the Flash/EE memory is guaranteed to retain its data for its Overall, Flash/EE memory represents a step closer to the fully specified retention lifetime every time that the Flash/EE ideal memory device that includes nonvolatility, in-circuit memory is reprogrammed. Also note that retention lifetime, programmability, high density, and low cost. Incorporated in based on activation energy of 0.6 eV, derates with T, as shown J the ADuC7060/ADuC7061, Flash/EE memory technology in Figure 22. allows the user to update program code space in-circuit, without the need to replace one time programmable (OTP) devices at remote operating nodes. 600 The ADuC7060/ADuC7061 contains a 32 kB array of Flash/EE memory. The lower 30 kB are available to the user and the s) ar450 upper 2 kB contain permanently embedded firmware, allowing Ye N ( in-circuit serial download. These 2 kB of embedded firmware O TI also contain a power-on configuration routine that downloads N300 E T factory-calibrated coefficients to the various calibrated E R peripherals (such as ADC, temperature sensor, and band gap 150 references). This 2 kB embedded firmware is hidden from user code. FTLheA FSlaHs/hE/EEE M mEeMmoOryR aYr rRayEsL oInA tBhIeL pIaTrYts are fully qualified for 0 30 40 J5U5NCTIO70N TEM85PERA1T0U0RE (1°2C5) 135 150 07079-016 Figure 22. Flash/EE Memory Data Retention two key Flash/EE memory characteristics: Flash/EE memory PROGRAMMING cycling endurance and Flash/EE memory data retention. Endurance quantifies the ability of the Flash/EE memory to be The 30 kB of Flash/EE memory can be programmed in-circuit, cycled through many program, read, and erase cycles. A single using the serial download mode or the provided JTAG mode. endurance cycle is composed of four independent, sequential Serial Downloading (In-Circuit Programming) events, defined as The ADuC7060/ADuC7061 facilitates code download via the • Initial page erase sequence standard UART serial port. The parts enter serial download • Read/verify sequence for a single Flash/EE mode after a reset or power cycle if the NTRST/BM pin is • Byte program sequence memory pulled low through an external 1 kΩ resistor. When in serial • Second read/verify sequence endurance cycle download mode, the user can download code to the full 30 kB of Flash/EE memory while the device is in-circuit in its target In reliability qualification, every half word (16-bit wide) application hardware. An executable PC serial download is location of the three pages (top, middle, and bottom) in the provided as part of the development system for serial Flash/EE memory is cycled 10,000 times from 0x0000 to downloading via the UART. 0xFFFF. The Flash/EE memory endurance qualification is When the ADuC7060/ADuC7061 enters download mode, the carried out in accordance with JEDEC Retention Lifetime user should be aware that the internal watchdog is enabled with Specification A117 over the industrial temperature range of a time-out period of 2 minutes. If the flash erase/write sequence −40°C to +125°C. The results allow the specification of a is not completed in this period, a reset occurs. minimum endurance figure over a supply temperature of 10,000 cycles. JTAG Access The JTAG protocol uses the on-chip JTAG interface to facilitate code download and debug. Rev. F | Page 59 of 107

ADuC7060/ADuC7061 Data Sheet PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM IRQ There are 15 interrupt sources on the ADuC7060/ADuC7061 The IRQ is the exception signal to enter the IRQ mode of the that are controlled by the interrupt controller. All interrupts are processor. It services general-purpose interrupt handling of generated from the on-chip peripherals, except for the software internal and external events. interrupt (SWI), which is programmable by the user. The All 32 bits are logically OR’ed to create a single IRQ signal to ARM7TDMI CPU core recognizes interrupts as one of two the ARM7TDMI core. The four 32-bit registers dedicated to types only: a normal interrupt request (IRQ) or a fast interrupt IRQ are described in the following sections. request (FIQ). All the interrupts can be masked separately. IRQSIG The control and configuration of the interrupt system are managed through a number of interrupt related registers. The IRQSIG reflects the status of the different IRQ sources. If a bits in each IRQ and FIQ register represent the same interrupt peripheral generates an IRQ signal, the corresponding bit in source, as described in Table 65. the IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear when the interrupt in the particular peripheral is cleared. All Each ADuC7060/ADuC7061 contains a vectored interrupt IRQ sources can be masked in the IRQEN MMR. IRQSIG is controller (VIC) that supports nested interrupts up to eight read only. levels. The VIC also allows the programmer to assign priority levels to all interrupt sources. Interrupt nesting needs to be IRQSIG Register enabled by setting the ENIRQN bit in the IRQCONN register. Name: IRQSIG A number of extra MMRs are used when the full vectored interrupt controller is enabled. Address: 0xFFFF0004 Immediately save IRQSTA/FIQSTA upon entering the interrupt Default value: Undefined service routine (ISR) to ensure that all valid interrupt sources are serviced. Access: Read only Table 65. IRQ/FIQ MMR Bit Designations IRQEN Bit Description Comments IRQEN provides the value of the current enable mask. When a 0 All interrupts OR’ed This bit is set if any FIQ is active bit is set to 1, the corresponding source request is enabled (FIQ only) to create an IRQ exception. The IRQEN register cannot be used 1 Software interrupt User programmable interrupt to disable an interrupt. Clear to 0 has no effect. source 2 Undefined This bit is not used IRQEN Register 3 Timer0 General-Purpose Timer0 Name: IRQEN 4 Timer1 or wake-up General-Purpose Timer1 or timer wake-up timer Address: 0xFFFF0008 5 Timer2 or watchdog General-Purpose Timer2 or timer watchdog timer Default value: 0x00000000 6 Timer3 or STI timer General-Purpose Timer3 Access: Read and write 7 Undefined This bit is not used 8 Undefined This bit is not used IRQCLR 9 Undefined This bit is not used IRQCLR is a write-only register that allows the IRQEN register 10 ADC ADC interrupt source bit to clear to mask an interrupt source. Each bit that is set to 1 11 UART UART interrupt source bit clears the corresponding bit in the IRQEN register without 12 SPI SPI interrupt source bit affecting the remaining bits. The pair of registers, IRQEN and 13 XIRQ0 (GPIO IRQ0) External Interrupt 0 IRQCLR, allows independent manipulation of the enable mask 14 XIRQ1 (GPIO IRQ1) External Interrupt 1 without requiring an atomic read-modify-write. Clear to 0 has 15 I2C master IRQ I2C master interrupt source bit no effect. 16 I2C slave IRQ I2C slave interrupt source bit 17 PWM PWM trip interrupt source bit 18 XIRQ2 (GPIO IRQ2) External Interrupt 2 19 XIRQ3 (GPIO IRQ3) External Interrupt 3 Rev. F | Page 60 of 107

Data Sheet ADuC7060/ADuC7061 IRQCLR Register FIQSIG Register Name: IRQCLR Name: FIQSIG Address: 0xFFFF000C Address: 0xFFFF0104 Default value: 0x00000000 Default value: Undefined Access: Write only Access: Read only IRQSTA FIQEN IRQSTA is a read-only register that provides the current FIQEN provides the value of the current enable mask. When a enabled IRQ source status (effectively a logic AND of the bit is set to 1, the corresponding source request is enabled IRQSIG and IRQEN bits). When set to 1, that source generates to create an FIQ exception. When a bit is set to 0, the corre- an active IRQ request to the ARM7TDMI core. There is no sponding source request is disabled or masked, which does not priority encoder or interrupt vector generation. This function is create an FIQ exception. The FIQEN register cannot be used to implemented in software in a common interrupt handler disable an interrupt. routine. FIQEN Register IRQSTA Register Name: FIQEN Name: IRQSTA Address: 0xFFFF0108 Address: 0xFFFF0000 Default value: 0x00000000 Default value: 0x00000000 Access: Read and write Access: Read only FIQCLR FAST INTERRUPT REQUEST (FIQ) FIQCLR is a write-only register that allows the FIQEN register to clear in order to mask an interrupt source. Each bit that is set The fast interrupt request (FIQ) is the exception signal to enter to 1 clears the corresponding bit in the FIQEN register without the FIQ mode of the processor. It is provided to service data affecting the remaining bits. The pair of registers, FIQEN and transfer or communication channel tasks with low latency. The FIQCLR, allows independent manipulation of the enable mask FIQ interface is identical to the IRQ interface and provides the without requiring an atomic read-modify-write. second level interrupt (highest priority). Four 32-bit registers FIQCLR Register are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA. Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ Name: FIQCLR signal to the core and to Bit 0 of both the FIQ and IRQ registers Address: 0xFFFF010C (FIQ source). The logic for FIQEN and FIQCLR does not allow an interrupt Default value: 0x00000000 source to be enabled in both IRQ and FIQ masks. A bit set to 1 Access: Write only in FIQEN clears, as a side effect, the same bit in IRQEN. Likewise, a bit set to 1 in IRQEN clears, as a side effect, the FIQSTA same bit in FIQEN. An interrupt source can be disabled in both FIQSTA is a read-only register that provides the current enabled IRQEN and FIQEN masks. FIQ source status (effectively a logic AND of the FIQSIG and FIQSIG FIQEN bits). When set to 1, that source generates an active FIQ FIQSIG reflects the status of the different FIQ sources. If a request to the ARM7TDMI core. There is no priority encoder peripheral generates an FIQ signal, the corresponding bit in or interrupt vector generation. This function is implemented in the FIQSIG is set; otherwise, it is cleared. The FIQSIG bits are software in a common interrupt handler routine. cleared when the interrupt in the particular peripheral is cleared. All FIQ sources can be masked in the FIQEN MMR. FIQSIG is read only. Rev. F | Page 61 of 107

ADuC7060/ADuC7061 Data Sheet FIQSTA Register • Vectored interrupts—allows a user to define separate interrupt service routine addresses for every interrupt Name: FIQSTA source. This is achieved by using the IRQBASE and Address: 0xFFFF0100 IRQVEC registers. Default value: 0x00000000 • IRQ/FIQ interrupts—can be nested up to eight levels depending on the priority settings. An FIQ still has a Access: Read only higher priority than an IRQ. Therefore, if the VIC is enabled for both the FIQ and IRQ and prioritization is PROGRAMMED INTERRUPTS maximized, it is possible to have 16 separate interrupt Because the programmed interrupts are not maskable, they are levels. controlled by another register (SWICFG) that writes into both • Programmable interrupt priorities—using the IRQP0 to IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG IRQP2 registers, an interrupt source can be assigned an registers at the same time. interrupt priority level value from 0 to 7. SWICFG VIC MMRS SWICFG is a 32-bit register dedicated to software interrupt, IRQBASE described in Table 66. This MMR allows control of a pro- The vector base register, IRQBASE, is used to point to the start grammed source interrupt. address of memory used to store 32 pointer addresses. These SWICFG Register pointer addresses are the addresses of the individual interrupt Name: SWICFG service routines. IRQBASE Register Address: 0xFFFF0010 Name: IRQBASE Default value: 0x00000000 Address: 0xFFFF0014 Access: Write only Default value: 0x00000000 Table 66. SWICFG MMR Bit Designations Access: Read and write Bit Description 31:3 Reserved. Table 67. IRQBASE MMR Bit Designations 2 Programmed interrupt FIQ. Setting/clearing this bit corresponds to setting/clearing Bit 1 of FIQSTA and Bit Access Initial Value Description FIQSIG. 31:16 Read only Reserved Always read as 0. 1 Programmed interrupt IRQ. Setting/clearing this bit 15:0 R/W 0 Vector base address. corresponds to setting/clearing Bit 1 of IRQSTA and IRQSIG. IRQVEC 0 Reserved. The IRQ interrupt vector register, IRQVEC, points to a memory Any interrupt signal must be active for at least the minimum address containing a pointer to the interrupt service routine of interrupt latency time to be detected by the interrupt controller the currently active IRQ. This register should be read only when and to be detected by the user in the IRQSTA/FIQSTA register. an IRQ occurs and IRQ interrupt nesting has been enabled by VECTORED INTERRUPT CONTROLLER (VIC) setting Bit 0 of the IRQCONN register. Each ADuC7060/ADuC7061 incorporates an enhanced IRQVEC Register interrupt control system or vectored interrupt controller. The Name: IRQVEC vectored interrupt controller for IRQ interrupt sources is enabled by setting Bit 0 of the IRQCONN register. Similarly, Bit Address: 0xFFFF001C 1 of IRQCONN enables the vectored interrupt controller for the Default value: 0x00000000 FIQ interrupt sources. The vectored interrupt controller provides the following enhancements to the standard IRQ/FIQ Access: Read only interrupts: Rev. F | Page 62 of 107

Data Sheet ADuC7060/ADuC7061 Table 68. IRQVEC MMR Bit Designations IRQP1 Register Initial Bit Access Value Description Name: IRQP1 31:23 Read 0 Always read as 0. Address: 0xFFFF0024 only 22:7 Read 0 IRQBASE register value. Default value: 0x00000000 only 6:2 Read 0 Highest priority IRQ source. This Access: Read and write only is a value between 0 to 19 repre- senting the possible interrupt Table 70. IRQP1 MMR Bit Designations sources. For example, if the highest Bit Name Description currently active IRQ is Timer1, then these bits are [01000]. 31 Reserved Reserved bit. 1:0 Reserved 0 Reserved bits. 30:28 I2CMPI A priority level of 0 to 7 can be set for I2C master. Priority Registers 27 Reserved Reserved bit. The interrupt priority registers, IRQP0, IRQP1, and IRQP2, 26:24 IRQ1PI A priority level of 0 to 7 can be set for IRQ1. allow each interrupt source to have its priority level configured 23 Reserved Reserved bit. for a level between 0 and 7. Level 0 is the highest priority level. 22:20 IRQ0PI A priority level of 0 to 7 can be set for IRQ0. 19 Reserved Reserved bit. IRQP0 Register 18:16 SPIMPI A priority level of 0 to 7 can be set for SPI Name: IRQP0 master. 15 Reserved Reserved bit. Address: 0xFFFF0020 14:12 UARTPI A priority level of 0 to 7 can be set for UART. Default value: 0x00000000 11 Reserved Reserved bit. 10:8 ADCPI A priority level of 0 to 7 can be set for the Access: Read and write ADC interrupt source. 7:0 Reserved Reserved bits. Table 69. IRQP0 MMR Bit Designations IRQP2 Register Bit Name Description 31:27 Reserved Reserved bits. Name: IRQP2 26:24 T3PI A priority level of 0 to 7 can be set for Address: 0xFFFF0028 Timer3. 23 Reserved Reserved bit. Default value: 0x00000000 22:20 T2PI A priority level of 0 to 7 can be set for Timer2. Access: Read and write 19 Reserved Reserved bit. 18:16 T1PI A priority level of 0 to 7 can be set for Table 71. IRQP2 MMR Bit Designations Timer1. Bit Name Description 15 Reserved Reserved bit. 31:15 Reserved Reserved bit. 14:12 T0PI A priority level of 0 to 7 can be set for 14:12 IRQ3PI A priority level of 0 to 7 can be set for IRQ3. Timer0. 11 Reserved Reserved bit. 11:7 Reserved Reserved bits. 10:8 IRQ2PI A priority level of 0 to 7 can be set for IRQ2. 6:4 SWINTP A priority level of 0 to 7 can be set for the 7 Reserved Reserved bit. software interrupt source. 6:4 SPISPI A priority level of 0 to 7 can be set for SPI 3:0 Reserved Interrupt 0 cannot be prioritized. slave. 3 Reserved Reserved bit. 2:0 I2CSPI A priority level of 0 to 7 can be set for I2C slave. Rev. F | Page 63 of 107

ADuC7060/ADuC7061 Data Sheet IRQCONN IRQSTAN Register The IRQCONN register is the IRQ and FIQ control register. It Name: IRQSTAN contains two active bits: the first to enable nesting and Address: 0xFFFF003C prioritization of IRQ interrupts, and the other to enable nesting and prioritization of FIQ interrupts. Default value: 0x00000000 If these bits are cleared, FIQs and IRQs can still be used, but it is Access: Read and write not possible to nest IRQs or FIQs. Neither is it possible to set an interrupt source priority level. In this default state, an FIQ does Table 73. IRQSTAN MMR Bit Designations have a higher priority than an IRQ. Bit Name Description IRQCONN Register 31:8 Reserved These bits are reserved and should not be written to. Name: IRQCONN 7:0 Setting this bit to 1 enables nesting of FIQ Address: 0xFFFF0030 interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. Default value: 0x00000000 FIQVEC Access: Read and write The FIQ interrupt vector register, FIQVEC, points to a memory address containing a pointer to the interrupt service routine of Table 72. IRQCONN MMR Bit Designations the currently active FIQ. This register should be read only when Bit Name Description an FIQ occurs and FIQ interrupt nesting has been enabled by 31:2 Reserved These bits are reserved and should not be setting Bit 1 of the IRQCONN register. written to. FIQVEC Register 1 ENFIQN Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit means no nesting Name: FIQVEC or prioritization of FIQs is allowed. 0 ENIRQN Setting this bit to 1 enables nesting of IRQ Address: 0xFFFF011C interrupts. Clearing this bit means no nesting or prioritization of IRQs is allowed. Default value: 0x00000000 Access: Read only IRQSTAN If IRQCONN[0] is asserted and IRQVEC is read, then one of Table 74. FIQVEC MMR Bit Designations these bits is asserted. The bit that asserts depends on the Initial priority of the IRQ. If the IRQ is of Priority 0, then Bit 0 asserts; Bit Access Value Description Priority 1, then Bit 1 asserts; and so forth. When a bit is set in 31:23 Read only 0 Always read as 0. this register, all interrupts of that priority and lower are blocked. 22:7 Read only 0 IRQBASE register value. To clear a bit in this register, all bits of a higher priority must be 6:2 0 Highest priority FIQ source. This is cleared first. It is possible to clear only one bit at a time. For a value between 0 to 19 that represents the possible interrupt example, if this register is set to 0x09, writing 0xFF changes the sources. For example, if the register to 0x08, and writing 0xFF a second time changes the highest currently active FIQ is register to 0x00. Timer1, then these bits are [01000]. 1:0 Reserved 0 Reserved bits. Rev. F | Page 64 of 107

Data Sheet ADuC7060/ADuC7061 FIQSTAN External Interrupts (IRQ0 to IRQ3) If IRQCONN[1] is asserted and FIQVEC is read, then one of The ADuC7060/ADuC7061 provides up to four external these bits asserts. The bit that asserts depends on the priority of interrupt sources. These external interrupts can be individually the FIQ. If the FIQ is of Priority 0, Bit 0 asserts; Priority 1, Bit 1 configured as level triggered or rising/falling edge triggered. asserts; and so forth. To enable the external interrupt source, the appropriate bit must When a bit is set in this register, all interrupts of that priority first be set in the FIQEN or IRQEN register. To select the and lower are blocked. required edge or level to trigger on, the IRQCONE register must be appropriately configured. To clear a bit in this register, all bits of a higher priority must be cleared first. It is possible to clear only one bit as a time. For To properly clear an edge based external IRQ interrupt, set the example, if this register is set to 0x09, writing 0xFF changes the appropriate bit in the IRQCLRE register. register to 0x08, and writing 0xFF a second time changes the IRQCONE Register register to 0x00. Name: IRQCONE FIQSTAN Register Name: FIQSTAN Address: 0xFFFF0034 Address: 0xFFFF013C Default value: 0x00000000 Default value: 0x00000000 Access: Read and write Access: Read and write Table 75. FIQSTAN MMR Bit Designations Bit Name Description 31:8 Reserved These bits are reserved and should not be written to. 7:0 Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. Table 76. IRQCONE MMR Bit Designations Bit Name Description 31:8 Reserved These bits are reserved and should not be written to. 7:6 IRQ3SRC[1:0] [11] = External IRQ3 triggers on falling edge. [10] = External IRQ3 triggers on rising edge. [01] = External IRQ3 triggers on low level. [00] = External IRQ3 triggers on high level. 5:4 IRQ2SRC[1:0] [11] = External IRQ2 triggers on falling edge. [10] = External IRQ2 triggers on rising edge. [01] = External IRQ2 triggers on low level. [00] = External IRQ2 triggers on high level. 3:2 IRQ1SRC[1:0] [11] = External IRQ1 triggers on falling edge. [10] = External IRQ1 triggers on rising edge. [01] = External IRQ1 triggers on low level. [00] = External IRQ1 triggers on high level. 1:0 IRQ0SRC[1:0] [11] = External IRQ0 triggers on falling edge. [10] = External IRQ0 triggers on rising edge. [01] = External IRQ0 triggers on low level. [00] = External IRQ0 triggers on high level. Rev. F | Page 65 of 107

ADuC7060/ADuC7061 Data Sheet IRQCLRE Register Table 77. IRQCLRE MMR Bit Designations Bit Name Description Name: IRQCLRE 31:20 Reserved These bits are reserved and should not be Address: 0xFFFF0038 written to. 19 IRQ3CLRI A 1 must be written to this bit in the IRQ3 Default value: 0x00000000 interrupt service routine to clear an edge triggered IRQ3 interrupt. Access: Read and write 18 IRQ2CLRI A 1 must be written to this bit in the IRQ2 interrupt service routine to clear an edge triggered IRQ2 interrupt. 17:15 Reserved These bits are reserved and should not be written to. 14 IRQ1CLRI A 1 must be written to this bit in the IRQ1 interrupt service routine to clear an edge triggered IRQ1 interrupt. 13 IRQ0CLRI A 1 must be written to this bit in the IRQ0 interrupt service routine to clear an edge triggered IRQ0 interrupt. 12:0 Reserved These bits are reserved and should not be written to. Rev. F | Page 66 of 107

Data Sheet ADuC7060/ADuC7061 TIMERS The ADuC7060/ADuC7061 features four general-purpose timer/counters. HR:MIN:SEC: 1/128 FORMAT • Timer0 To use the timer in Hr : Min : Sec : hundreds format the 32768 • Timer1 or wake-up timer kHz clock and prescaler of 256 should be selected. The • Timer2 or watchdog timer hundreds field does not represent milliseconds but 1/128 of a • Timer3 second (256/32768).The bits representing the Hour, minute and second are not consecutive in the register. This arrangement The four timers in their normal mode of operation can be either applies to TxLd and TxVAL when using the Hr : Min : Sec : free running or periodic. hundreds format as set in TxCON[5:4]. See Table 79 for more In free running mode, the counter decrements/increments from details. the maximum or minimum value until zero/full scale and starts Table 79. Hr:Min:Sec: hundreds format again at the maximum or minimum value. Bit Value Description In periodic mode, the counter decrements/increments from the 31:24 0 to 23 or 0 to 255 Hours value in the load register (TxLD MMR) until zero/full scale and 23:22 0 Reserved starts again at the value stored in the load register. Note that the 21:16 0 to 59 Minutes TxLD MMR should be configured before the TxCON MMR. 15:14 0 Reserved The timer interval is calculated as follows: 13:8 0 to 59 Seconds If the timer is set to count down then 7 0 Reserved 6:0 0 to 127 1/128 of second Interval = (TxLD x Prescaler) / Source Clock If the timer is set to count up then Interval = ((Full Scale - TxLD) x Prescaler) / Source Clock. The value of a counter can be read at any time by accessing its value register (TxVAL). Timers are started by writing in the control register of the corresponding timer (TxCON). In normal mode, an IRQ is generated each time that the value of the counter reaches zero (if counting down) or full scale (if counting up). An IRQ can be cleared by writing any value to the clear register of the particular timer (TxCLRI). Table 78. Timer Event Capture Bit Description 0 Reserved 1 Timer0 2 Timer1 or wake-up timer 3 Timer2 or watchdog timer 4 Timer3 5 Reserved 6 Reserved 7 Reserved 8 ADC 9 UART 10 SPI 11 XIRQ0 12 XIRQ1 13 I2C master 14 I2C slave 15 PWM 16 XIRQ2 (GPIO IRQ2) 17 XIRQ3 (GPIO IRQ3) Rev. F | Page 67 of 107

ADuC7060/ADuC7061 Data Sheet TIMER0 Timer0 Load Registers Timer0 is a 32-bit, general-purpose timer, count down or count Name: T0LD up, with a programmable prescaler. The prescaler source can be Address: 0xFFFF0320 the low power 32.768 kHz oscillator, the core clock, or from one of two external GPIOs. This source can be scaled by a factor of Default value: 0x00000000 1, 16, 256, or 32,768. This gives a minimum resolution of 97.66 ns with a prescaler of 1 (ignoring the external GPIOs). Access: Read and write The counter can be formatted as a standard 32-bit value or as Function: T0LD is a 32-bit register that holds the 32-bit hours:minutes:seconds:hundredths. value that is loaded into the counter. Timer0 has a capture register (T0CAP) that is triggered by a Timer0 Clear Register selected IRQ source initial assertion. When triggered, the current timer value is copied to T0CAP, and the timer continues to run. Name: T0CLRI Use this feature to determine the assertion of an event with Address: 0xFFFF032C increased accuracy. Note that only peripherals that have their IRQ source enabled can be used with the timer capture feature. Access: Write only The Timer0 interface consists of five MMRS: T0LD, T0VAL, Function: This 8-bit, write-only MMR is written T0CAP, T0CLRI, and T0CON. (with any value) by user code to clear the • T0LD, T0VAL, and T0CAP are 32-bit registers and hold interrupt. 32-bit, unsigned integers of which T0VAL and T0CAP are read only. Timer0 Value Register • T0CLRI is an 8-bit register and writing any value to this Name: T0VAL register clears the Timer0 interrupt. • T0CON is the configuration MMR, which is described in Address: 0xFFFF0324 Table 80. Default value: 0xFFFFFFFF Timer0 features a postscaler that allows the user to count between Access: Read only 1 and 256 the number of Timer0 timeouts. To activate the post- scaler, the user sets Bit 18 and writes the desired number to count Function: T0VAL is a 32-bit register that holds the into Bits[24:31] of T0CON. When that number of timeouts is current value of Timer0. reached, Timer0 can generate an interrupt if T0CON[18] is set. Note that, if the part is in a low power mode and Timer0 is clocked from the GPIO or low power oscillator source, Timer0 continues to operate. Timer0 reloads the value from T0LD when Timer0 overflows. 32-BIT LOAD 32.768kHz OSCILLATOR CORE CLOCK FREQUENCY/CD PRESCALER 32-BIT 8-BIT 1, 16, 256, OR 32,768 UP/DOWN COUNTER POSTSCALER CORE CLOCK TIMER0 IRQ FREQUENCY GPIO TIMER0 VALUE IRQ[31:0] CAPTURE 07079-017 Figure 23. Timer0 Block Diagram Rev. F | Page 68 of 107

Data Sheet ADuC7060/ADuC7061 Timer0 Capture Register Name: T0CAP Address: 0xFFFF0330 Default value: 0x00000000 Access: Read only Function: This 32-bit register holds the 32-bit value captured by an enabled IRQ event. Timer0 Control Register Name: T0CON Address: 0xFFFF0328 Default value: 0x01000000 Access: Read and write Function: This 32-bit MMR configures the mode of operation of Timer0. Table 80. T0CON MMR Bit Designations Bit Name Description 31:24 T0PVAL 8-bit postscaler. By writing to these eight bits, a value is written to the postscaler. Writing 0 is interpreted as a 1. By reading these eight bits, the current value of the counter is read. 23 T0PEN Timer0 enable postscaler. Set to enable the Timer0 postscaler. If enabled, interrupts are generated after T0CON[31:24] periods as defined by T0LD. Cleared to disable the Timer0 postscaler. 22:20 Reserved. These bits are reserved and should be written as 0 by user code. 19 T0PCF Postscaler compare flag; read only. Set if the number of Timer0 overflows is equal to the number written to the postscaler. 18 T0SRCI Timer0 interrupt source. Set to select interrupt generation from the postscaler counter. Cleared to select interrupt generation directly from Timer0. 17 T0CAPEN Event enable bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16:12 T0CAPSEL Event Select Bits[17:0]. The events are described in Table 78. 11 Reserved bit. 10:9 T0CLKSEL Clock select. [00] = 32.768 kHz. [01] = 10.24 MHz/CD. [10] = 10.24 MHz. [11] = P1.0. 8 T0DIR Count up. Set by user for Timer0 to count up. Cleared by user for Timer0 to count down (default). 7 T0EN Timer0 enable bit. Set by user to enable Timer0. Cleared by user to disable Timer0 (default). 6 T0MOD Timer0 mode. Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default). Rev. F | Page 69 of 107

ADuC7060/ADuC7061 Data Sheet Bit Name Description 5:4 T0FORMAT Format. [00] = binary (default). [01] = reserved. [10] = hours:minutes:seconds:hundredths (23 hours to 0 hours). [11] = hours:minutes:seconds:hundredths (255 hours to 0 hours). 3:0 T0SCALE Prescaler. [0000] = source clock/1 (default). [0100] = source clock/16. [1000] = source clock/256. [1111] = source clock/32,768. Note that all other values are undefined. TIMER1 OR WAKE-UP TIMER Timer1 Load Registers Name: T1LD Timer1 is a 32-bit wake-up timer, count down or count up, with a programmable prescaler. The prescaler is clocked directly from Address: 0xFFFF0340 one of four clock sources, namely, the core clock (which is the default selection), external 32.768 kHz watch crystal, or the Default value: 0x00000000 32.768 kHz oscillator. The selected clock source can be scaled Access: Read and write by a factor of 1, 16, 256, or 32,768. The wake-up timer continues to run when the core clock is disabled. This gives a Function: T1LD is a 32-bit register that holds the 32-bit minimum resolution of 97.66 ns when operating at CD zero, the value that is loaded into the counter. core is operating at 10.24 MHz, and with a prescaler of 1 (ignoring the external GPIOs). Timer1 Clear Register The counter can be formatted as a plain 32-bit value or as Name: T1CLRI hours:minutes:seconds:hundredths. Timer1 reloads the value from T1LD either when Timer1 Address: 0xFFFF034C overflows or immediately when T1LD is written. Access: Write only The Timer1 interface consists of four MMRS. Function: This 8-bit, write-only MMR is written (with • T1LD and T1VAL are 32-bit registers and hold 32-bit, any value) by user code to clear the interrupt. unsigned integers. T1VAL is read only. • T1CLRI is an 8-bit register. Writing any value to this Timer1 Value Register register clears the Timer1 interrupt. • T1CON is the configuration MMR, described in Table 81. Name: T1VAL Address: 0xFFFF0344 Default value: 0xFFFFFFFF Access: Read only Function: T1VAL is a 32-bit register that holds the current value of Timer1. Rev. F | Page 70 of 107

Data Sheet ADuC7060/ADuC7061 32-BIT LOAD 32.768kHz OSCILLATOR CORE CLOCK FREQUENCY/CD PRESCALER 32-BIT CORE 1, 16, 256, OR 32,768 UP/DOWN COUNTER TIMER1 IRQ CLOCK EXTERNAL 32.768kHz WATCH CRYSTAL TVIAMLEURE1 07079-018 Figure 24. Timer1 Block Diagram Timer1 Control Register Name: T1CON Address: 0xFFFF0348 Default value: 0x0000 Access: Read and write Function: This 16-bit MMR configures the mode of operation of Timer1. Table 81. T1CON MMR Bit Designations Bit Name Description 15:11 Reserved. 10: 9 T1CLKSEL Clock source select. [00] = 32.768 kHz oscillator. [01] = 10.24 MHz/CD. [10] = XTALI. [11] = 10.24 MHz. 8 T1DIR Count up. Set by user for Timer1 to count up. Cleared by user for Timer1 to count down (default). 7 T1EN Timer1 enable bit. Set by user to enable Timer1. Cleared by user to disable Timer1 (default). 6 T1MOD Timer1 mode. Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default). 5:4 T1FORMAT Format. [00] = binary (default). [01] = reserved. [10] = hours:minutes:seconds:hundredths (23 hours to 0 hours). This is only valid with a 32 kHz clock. [11] = hours:minutes:seconds:hundredths (255 hours to 0 hours). This is only valid with a 32 kHz clock. 3:0 T1SCALE Prescaler. [0000] = source clock/1 (default). [0100] = source clock/16. [1000] = source clock/256. This setting should be used in conjunction with Timer1 in the format hours:minutes:seconds:hundredths. See Format 10 and Format 11 listed with Bits[5:4] in this table (Table 81). [1111] = source clock/32,768. Rev. F | Page 71 of 107

ADuC7060/ADuC7061 Data Sheet TIMER2 OR WATCHDOG TIMER Timer2 Interface Timer2 has two modes of operation, normal mode and The Timer2 interface consists of four MMRs. watchdog mode. The watchdog timer is used to recover • T2CON is the configuration MMR, described in (Table 82). from an illegal software state. When enabled, it requires • T2LD and T2VAL are 16-bit registers (Bit 0 to Bit 15) and periodic servicing to prevent it from forcing a reset of the hold 16-bit, unsigned integers. T2VAL is read only. processor. • T2CLRI is an 8-bit register. Writing any value to this Timer2 reloads the value from T2LD either when Timer2 register clears the Timer2 interrupt in normal mode or overflows or immediately when T2CLRI is written. resets a new timeout period in watchdog mode. Normal Mode Timer2 Load Register Timer2 in normal mode is identical to Timer0 in the 16-bit Name: T2LD mode of operation, except for the clock source. The clock source is the low power, 32.768 kHz oscillator scalable by a Address: 0xFFFF0360 factor of 1, 16, or 256. Default value: 0x3BF8 Watchdog Mode Access: Read and write Watchdog mode is entered by setting T2CON[Bit 5]. Timer2 decrements from the timeout value present in the T2LD register Function: This 16-bit MMR holds the Timer2 until zero. The maximum timeout is 512 seconds, using a reload value. maximum prescaler/256 and full scale in T2LD. User software should not configure a timeout period of less Timer2 Clear Register than 30 ms. This is to avoid any conflict with Flash/EE memory Name: T2CLRI page erase cycles that require 20 ms to complete a single page erase cycle and kernel execution. Address: 0xFFFF036C If T2VAL reaches 0, a reset or an interrupt occurs, depending Access: Write only on T2CON[1]. To avoid a reset or an interrupt event, any value must be written to T2CLRI before T2VAL reaches zero. This Function: This 8-bit, write-only MMR is written (with reloads the counter with T2LD and begins a new timeout period. any value) by user code to refresh (reload) When watchdog mode is entered, T2LD and T2CON are Timer2 in watchdog mode to prevent a write protected. These two registers cannot be modified until watchdog timer reset event. a power-on reset event resets the watchdog timer. After any other reset event, the watchdog timer continues to count. To Timer2 Value Register avoid an infinite loop of watchdog resets, configure the Name: T2VAL watchdog timer in the initial lines of user code. User software should configure a minimum timeout period of 30 ms only. Address: 0xFFFF0364 Timer2 halts automatically during JTAG debug access and only Default value: 0x3BF8 recommences counting after JTAG relinquishes control of the ARM7 core. By default, Timer2 continues to count during Access: Read only power-down. To disable this, set Bit 0 in T2CON. It is recommended that the default value be used, that is, that the Function: This 16-bit, read-only MMR holds the watchdog timer continues to count during power-down. current Timer2 count value. 16-BIT LOAD PRESCALER 16-BIT WATCHDOG RESET 32.768kHz 1, 16, 256 UP/DOWN COUNTER TIMER2 IRQ TVIAMLEURE2 07079-019 Figure 25. Timer2 Block Diagram Rev. F | Page 72 of 107

Data Sheet ADuC7060/ADuC7061 Timer2 Control Register Name: T2CON Address: 0xFFFF0368 Default value: 0x0000 Access: Read and write Function: This 16-bit MMR configures the mode of operation of Timer2, as described in detail in Table 82. Table 82. T2CON MMR Bit Designations Bit Name Description 15:9 Reserved. These bits are reserved and should be written as 0 by user code. 8 T2DIR Count up/count down enable. Set by user code to configure Timer2 to count up. Cleared by user code to configure Timer2 to count down. 7 T2EN Timer2 enable. Set by user code to enable Timer2. Cleared by user code to disable Timer2. 6 T2MOD Timer2 operating mode. Set by user code to configure Timer2 to operate in periodic mode. Cleared by user to configure Timer2 to operate in free running mode. 5 WDOGMDEN Watchdog timer mode enable. Set by user code to enable watchdog mode. Cleared by user code to disable watchdog mode. 4 Reserved. This bit is reserved and should be written as 0 by user code. 3:2 T2SCALE Timer2 clock (32.768 kHz) prescaler. 00 = 32.768 kHz (default). 01 = source clock/16. 10 = source clock/256. 11 = reserved. 1 WDOGENI Watchdog timer IRQ enable. Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0. Cleared by user code to disable the IRQ option. 0 T2PDOFF Stop Timer2 when power-down is enabled. Set by user code to stop Timer2 when the peripherals are powered down using Bit 4 in the POWCON0 MMR. Cleared by user code to enable Timer2 when the peripherals are powered down using Bit 4 in the POWCON0 MMR. Rev. F | Page 73 of 107

ADuC7060/ADuC7061 Data Sheet TIMER3 Timer3 Value Register Timer3 is a general-purpose, 16-bit, count up/count down Name: T3VAL timer with a programmable prescaler. Timer3 can be clocked from the core clock or the low power 32.768 kHz oscillator with Address: 0xFFFF0384 a prescaler of 1, 16, 256, or 32,768. Default value: 0xFFFF Timer3 has a capture register (T3CAP) that can be triggered by a selected IRQ source initial assertion. Once triggered, the Access: Read only current timer value is copied to T3CAP, and the timer continues Function: T3VAL is a 16-bit register that holds the to run. This feature can be used to determine the assertion of an current value of Timer3. event with increased accuracy. The Timer3 interface consists of five MMRs. Time3 Capture Register • T3LD, T3VAL, and T3CAP are 16-bit registers and hold Name: T3CAP 16-bit, unsigned integers. T3VAL and T3CAP are read Address: 0xFFFF0390 only. • T3CLRI is an 8-bit register. Writing any value to this Default value: 0x0000 register clears the interrupt. • T3CON is the configuration MMR, described in Table 83. Access: Read only Timer3 Load Registers Function: This is a 16-bit register that holds the 16-bit value captured by an enabled IRQ event. Name: T3LD Timer3 Control Register Address: 0xFFFF0380 Name: T3CON Default value: 0x0000 Address: 0xFFFF0388 Access: Read and write Default value: 0x00000000 Function: T3LD is a 16-bit register that holds the 16-bit value that is loaded into the counter. Access: Read and write Timer3 Clear Register Function: This 32-bit MMR configures the mode of operation of Timer3. Name: T3CLRI Address: 0xFFFF038C Access: Write only Function: This 8-bit, write-only MMR is written (with any value) by user code to clear the interrupt. Rev. F | Page 74 of 107

Data Sheet ADuC7060/ADuC7061 Table 83. T3CON MMR Bit Designations Bit Name Description 31:18 Reserved. 17 T3CAPEN Event enable bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16:12 T3CAPSEL Event select range, 0 to 17. The events are described in Table 78. 11 Reserved. 10:9 T3CLKSEL Clock select. [00] = 32.768 kHz oscillator. [01] = 10.24 MHz/CD. [10] = 10.24 MHz. [11] = reserved. 8 T3DIR Count up. Set by user for Timer3 to count up. Cleared by user for Timer3 to count down (default). 7 T3EN Timer3 enable bit. Set by user to enable Timer3. Cleared by user to disable Timer3 (default). 6 T3MOD Timer3 mode. Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default mode). 5:4 Reserved. 3:0 T3SCALE Prescaler. [0000] = source clock/1 (default). [0100] = source clock/16. [1000] = source clock/256. [1111] = source clock/32,768. Rev. F | Page 75 of 107

ADuC7060/ADuC7061 Data Sheet PULSE-WIDTH MODULATOR PULSE-WIDTH MODULATOR GENERAL OVERVIEW In all modes, the PWMxCOMx MMRs control the point at Each ADuC7060/ADuC7061 integrates a 6-channel pulse- which the PWM outputs change state. An example of the first width modulator (PWM) interface. The PWM outputs can be pair of PWM outputs (PWM0 and PWM1) is shown in Figure 26. configured to drive an H-bridge or can be used as standard PWM outputs. On power-up, the PWM outputs default to H- HIGH SIDE bridge mode. This ensures that the motor is turned off by (PWM0) default. In standard PWM mode, the outputs are arranged as three pairs of PWM pins. Users have control over the period of LOW SIDE each pair of outputs and over the duty cycle of each individual (PWM1) output. Table 84. PWM MMRs PWM0COM2 MMR Name Description PWM0COM1 PWMCON PWM control. PWM0COM0 Compare Register 0 for PWM Output 0 and PWM0COM0 PWM0COM1 PCWomMp Oaruet pRuegt 1is.t er 1 for PWM Output 0 and PWM0LEN 07079-020 PWM Output 1. Figure 26. PWM Timing PWM0COM2 Compare Register 2 for PWM Output 0 and The PWM clock is selectable via PWMCON with one of the PWM Output 1. following values: UCLK divided by 2, 4, 8, 16, 32, 64, 128, or PWM0LEN Frequency control for PWM Output 0 and PWM 256. The length of a PWM period is defined by PWMxLEN. Output 1. PWM1COM0 Compare Register 0 for PWM Output 2 and The PWM waveforms are set by the count value of the 16-bit PWM Output 3. timer and the compare registers contents, as shown with the PWM1COM1 Compare Register 1 for PWM Output 2 and PWM0 and PWM1 waveforms in Figure 26. PWM Output 3. The low-side waveform, PWM1, goes high when the timer PWM1COM2 Compare Register 2 for PWM Output 2 and count reaches PWM0LEN, and it goes low when the timer PWM Output 3. count reaches the value held in PWM0COM2 or when the PWM1LEN Frequency control for PWM Output 2 and PWM Output 3. high-side waveform (PWM0) goes low. PWM2COM0 Compare Register 0 for PWM Output 4 and The high-side waveform, PWM0, goes high when the timer PWM Output 5. count reaches the value held in PWM0COM0, and it goes low PWM2COM1 Compare Register 1 for PWM Output 4 and when the timer count reaches the value held in PWM0COM1. PWM Output 5. PWM2COM2 Compare Register 2 for PWM Output 4 and PWMCON Control Register PWM Output 5. Name: PWMCON PWM2LEN Frequency control for PWM Output 4 and PWM Output 5. Address: 0xFFFF0F80 PWMCLRI PWM interrupt clear. Default value: 0x0012 Access: Read and write Function: This is a 16-bit MMR that configures the PWM outputs. Rev. F | Page 76 of 107

Data Sheet ADuC7060/ADuC7061 Table 85. PWMCON MMR Bit Designations Bit Name Description 15 Reserved This bit is reserved. Do not write to this bit. 14 Sync Enables PWM synchronization. Set to 1 by user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low transition on the P1.2/SYNC pin. Cleared by user to ignore transitions on the P1.2/SYNC pin. 13 PWM5INV Set to 1 by user to invert PWM5. Cleared by user to use PWM5 in normal mode. 12 PWM3INV Set to 1 by user to invert PWM3. Cleared by user to use PWM3 in normal mode. 11 PWM1INV Set to 1 by user to invert PWM1. Cleared by user to use PWM1 in normal mode. 10 PWMTRIP Set to 1 by user to enable PWM trip interrupt. When the PWM trip input (Pin P1.3/TRIP) is low, the PWMEN bit is cleared and an interrupt is generated. Cleared by user to disable the PWMTRIP interrupt. 9 ENA If HOFF = 0 and HMODE = 1. Note that, if not in H-bridge mode, this bit has no effect. Set to 1 by user to enable PWM outputs. Cleared by user to disable PWM outputs. If HOFF = 1 and HMODE = 1, see Table 86. 8:6 PWMCP[2:0] PWM clock prescaler bits. Sets the UCLK divider. [000] = UCLK/2. [001] = UCLK/4. [010] = UCLK/8. [011] = UCLK/16. [100] = UCLK/32. [101] = UCLK/64. [110] = UCLK/128. [111] = UCLK/256. 5 POINV Set to 1 by user to invert all PWM outputs. Cleared by user to use PWM outputs as normal. 4 HOFF High side off. Set to 1 by user to force PWM0 and PWM2 outputs high. This also forces PWM1 and PWM3 low. Cleared by user to use the PWM outputs as normal. 3 LCOMP Load compare registers. Set to 1 by user to load the internal compare registers with the values in PWMxCOMx on the next transition of the PWM timer from 0x00 to 0x01. Cleared by user to use the values previously stored in the internal compare registers. 2 DIR Direction control. Set to 1 by user to enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low. Cleared by user to enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low. 1 HMODE Enables H-bridge mode.1 Set to 1 by user to enable H-bridge mode and Bit 1 to Bit 5 of PWMCON. Cleared by user to operate the PWMs in standard mode. 0 PWMEN Set to 1 by user to enable all PWM outputs. Cleared by user to disable all PWM outputs. 1 In H-bridge mode, HMODE = 1. See Table 86 to determine the PWM outputs. Rev. F | Page 77 of 107

ADuC7060/ADuC7061 Data Sheet On power-up, PWMCON defaults to 0x0012 (HOFF = 1 and MMR. Note that when using the PWM trip interrupt, clear the HMODE = 1). All GPIO pins associated with the PWM are PWM interrupt before exiting the ISR. This prevents generation configured in PWM mode by default (seeTable 86). Clear the of multiple interrupts. PWM trip interrupt by writing any value to the PWMCLRI Table 86. PWM Output Selection PWMCON MMR1 PWM Outputs2 ENA HOFF POINV DIR PWM0 PWM1 PWM2 PWM3 0 0 X X 1 1 1 1 X 1 X X 1 0 1 0 1 0 0 0 0 0 HS1 LS1 1 0 0 1 HS1 LS1 0 0 1 0 1 0 HS1 LS1 1 1 1 0 1 1 1 1 HS1 LS1 1 X is don’t care. 2 HS = high side, LS = low side. Table 87. Compare Registers Name Address Default Value Access PWM0COM0 0xFFFF0F84 0x0000 R/W PWM0COM1 0xFFFF0F88 0x0000 R/W PWM0COM2 0xFFFF0F8C 0x0000 R/W PWM1COM0 0xFFFF0F94 0x0000 R/W PWM1COM1 0xFFFF0F98 0x0000 R/W PWM1COM2 0xFFFF0F9C 0x0000 R/W PWM2COM0 0xFFFF0FA4 0x0000 R/W PWM2COM1 0xFFFF0FA8 0x0000 R/W PWM2COM2 0xFFFF0FAC 0x0000 R/W Rev. F | Page 78 of 107

Data Sheet ADuC7060/ADuC7061 PWM0COM0 Compare Register PWM1COM0 Compare Register Name: PWM0COM0 Name: PWM1COM0 Address: 0xFFFF0F84 Address: 0xFFFF0F94 Default value: 0x0000 Default value: 0x0000 Access: Read and write Access: Read and write Function: PWM0 output pin goes high when the PWM Function: PWM2 output pin goes high when the PWM timer reaches the count value stored in this timer reaches the count value stored in this register. register. PWM0COM1 Compare Register PWM1COM1 Compare Register Name: PWM0COM1 Name: PWM1COM1 Address: 0xFFFF0F88 Address: 0xFFFF0F98 Default value: 0x0000 Default value: 0x0000 Access: Read and write Access: Read and write Function: PWM0 output pin goes low when the PWM Function: PWM2 output pin goes low when the PWM timer reaches the count value stored in this timer reaches the count value stored in this register. register. PWM0COM2 Compare Register PWM1COM2 Compare Register Name: PWM0COM2 Name: PWM1COM2 Address: 0xFFFF0F8C Address: 0xFFFF0F9C Default value: 0x0000 Default value: 0x0000 Access: Read and write Access: Read and write Function: PWM1 output pin goes low when the PWM Function: PWM3 output pin goes low when the PWM timer reaches the count value stored in this timer reaches the count value stored in this register. register. PWM0LEN Register PWM1LEN Register Name: PWM0LEN Name: PWM1LEN Address: 0xFFFF0F90 Address: 0xFFFF0FA0 Default value: 0x0000 Default value: 0x0000 Access: Read and write Access: Read and write Function: PWM1 output pin goes high when the PWM Function: PWM3 output pin goes high when the PWM timer reaches the value stored in this register. timer reaches the value stored in this register. Rev. F | Page 79 of 107

ADuC7060/ADuC7061 Data Sheet PWM2COM0 Compare Register PWM2LEN Register Name: PWM2COM0 Name: PWM2LEN Address: 0xFFFF0FA4 Address: 0xFFFF0FB0 Default value: 0x0000 Default value: 0x0000 Access: Read and write Access: Read and write Function: PWM4 output pin goes high when the PWM Function: PWM5 output pin goes high when the PWM timer reaches the count value stored in this timer reaches the value stored in this register. register. PWMCLRI Register PWM2COM1 Compare Register Name: PWMCLRI Name: PWM2COM1 Address: 0xFFFF0FB8 Address: 0xFFFF0FA8 Default value: 0x0000 Default value: 0x0000 Access: Write only Access: Read and write Function: Write any value to this register to clear a Function: PWM4 output pin goes low when the PWM PWM interrupt source. This register must be timer reaches the count value stored in this written to before exiting a PWM interrupt register. service routine; otherwise, multiple interrupts occur. PWM2COM2 Compare Register Name: PWM2COM2 Address: 0xFFFF0FAC Default value: 0x0000 Access: Read and write Function: PWM5 output pin goes low when the PWM timer reaches the count value stored in this register. Rev. F | Page 80 of 107

Data Sheet ADuC7060/ADuC7061 UART SERIAL INTERFACE Each ADuC7060/ADuC7061 features a 16450-compatible Calculation of the baud rate using a fractional divider is as UART. The UART is a full-duplex, universal, asynchronous follows: receiver/transmitter. A UART performs serial-to-parallel 10.24MHz conversion on data characters received from a peripheral device BaudRate= (2) N and parallel-to-serial conversion on data characters received from 16×DL×2×(M+ ) 2048 the ARM7TDMI. The UART features a fractional divider that facilitates high accuracy baud rate generation and a network N 10.24MHz M+ = addressable mode. The UART functionality is available on the 2048 Baud Rate×16×DL×2 P1.0/IRQ1/SIN/T0 and P1.1/SOUT pins of the ADuC7060/ ADuC7061. Table 89 lists common baud rate values. The serial communication adopts an asynchronous protocol Table 89. Baud Rate Using the Fractional Baud Rate Generator that supports various word lengths, stop bits, and parity genera- Baud Rate DL M N Actual Baud Rate % Error tion options selectable in the configuration register. 9600 0x21 1 21 9598.55 0.015% BAUD RATE GENERATION 19,200 0x10 1 85 19,203 0.015% 115,200 0x2 1 796 115,218 0.015% The ADuC7060/ADuC7061 features two methods of generating the UART baud rate: normal 450 UART baud rate generation and ADuC7060/ADuC7061 fractional divider. UART REGISTER DEFINITIONS Normal 450 UART Baud Rate Generation The UART interface consists of the following 11 registers: The baud rate is a divided version of the core clock using the COMTX: 8-bit transmit register value in COMDIV0 and COMDIV1 MMRs (16-bit value, COMRX: 8-bit receive register divisor latch (DL)). The standard baud rate generator formula is COMDIV0: divisor latch (low byte) COMDIV1: divisor latch (high byte) 10.24MHz BaudRate= (1) COMCON0: line control register 16×2×DL COMCON1: line control register Table 88 lists common baud rate values. COMSTA0: line status register COMSTA1: line status register Table 88. Baud Rate Using the Standard Baud Rate Generator COMIEN0: interrupt enable register Baud Rate DL Actual Baud Rate % Error COMIID0: interrupt identification register 9600 0x21 9696 1.01% COMDIV2: 16-bit fractional baud divide register 19,200 0x11 18,824 1.96% 115,200 0x3 106,667 7.41% COMTX, COMRX, and COMDIV0 share the same address location. COMTX and COMRX can be accessed when Bit 7 in ADuC7060/ADuC7061 Fractional Divider the COMCON0 register is cleared. COMDIV0 or COMDIV1 The fractional divider combined with the normal baud rate can be accessed when Bit 7 of COMCON0 or COMCON1, generator allows the generation of accurate high speed baud rates. respectively, is set. FBEN CORE /2 CLOCK /(M + N/2048) /16DL UART 07079-021 Figure 27. Fractional Divider Baud Rate Generation Rev. F | Page 81 of 107

ADuC7060/ADuC7061 Data Sheet UART Transmit Register UART Divisor Latch Register 1 Write to this 8-bit register (COMTX) to transmit data using This 8-bit register contains the most significant byte of the the UART. divisor latch that controls the baud rate at which the UART operates. COMTX Register COMDIV1 Register Name: COMTX Name: COMDIV1 Address: 0xFFFF0700 Address: 0xFFFF0704 Access: Write only Default value: 0x00 UART Receive Register Access: Read and write This 8-bit register (COMRX) is read to receive data transmitted using the UART. UART Control Register 0 COMRX Register This 8-bit register (COMCON0) controls the operation of the Name: COMRX UART in conjunction with COMCON1. COMCON0 Register Address: 0xFFFF0700 Name: COMCON0 Default value: 0x00 Address: 0xFFFF070C Access: Read only Default value: 0x00 UART Divisor Latch Register 0 Access: Read and write This 8-bit register (COMDIV0) contains the least significant byte of the divisor latch that controls the baud rate at which the UART operates. COMDIV0 Register Name: COMDIV0 Address: 0xFFFF0700 Default value: 0x00 Access: Read and write Rev. F | Page 82 of 107

Data Sheet ADuC7060/ADuC7061 Table 90. COMCON0 MMR Bit Designations Bit Name Description 7 DLAB Divisor latch access. Set by user to enable access to the COMDIV0 and COMDIV1 registers. Cleared by user to disable access to COMDIV0 and COMDIV1 and enable access to COMRX, COMTX, and COMIEN0. 6 BRK Set break. Set by user to force transmit to 0. Cleared to operate in normal mode. 5 SP Stick parity. Set by user to force parity to defined values. 1 if EPS = 1 and PEN = 1. 0 if EPS = 0 and PEN = 1. 4 EPS Even parity select bit. Set for even parity. Cleared for odd parity. 3 PEN Parity enable bit. Set by user to transmit and check the parity bit. Cleared by user for no parity transmission or checking. 2 Stop Stop bit. Set by user to transmit 1.5 stop bits if the word length is 5 bits, or 2 stop bits if the word length is 6 bits, 7 bits, or 8 bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected. Cleared by user to generate one stop bit in the transmitted data. 1:0 WLS Word length select. [00] = 5 bits. [01] = 6 bits. [10] = 7 bits. [11] = 8 bits. Rev. F | Page 83 of 107

ADuC7060/ADuC7061 Data Sheet UART Control Register 1 Table 92. COMSTA0 MMR Bit Designations This 8-bit register controls the operation of the UART in Bit Name Description conjunction with COMCON0. 7 Reserved. COMCON1 Register 6 TEMT COMTX and shift register empty status bit. Name: COMCON1 Set automatically if COMTX and the shift register are empty. This bit indicates that Address: 0xFFFF0710 the data has been transmitted, that is, no more data is present in the shift register. Default value: 0x00 Cleared automatically when writing to COMTX. Access: Read and write 5 THRE COMTX empty status bit. Set automatically if COMTX is empty. Table 91. COMCON1 MMR Bit Designations COMTX can be written as soon as this bit Bit Name Description is set; the previous data might not have 7:5 Reserved bits. Not used. been transmitted yet and can still be present in the shift register. 4 LOOPBACK Loopback. Set by user to enable loopback mode. In loopback mode, Cleared automatically when writing to the transmit pin is forced high. COMTX. 3:2 Reserved bits. Not used. 4 BI Break indicator. 1 RTS Request to send. Set when P1.0/IRQ1/SIN/T0 pin is held low for more than the maximum word Set by user to force the RTS output to 0. length. Cleared by user to force the RTS Cleared automatically. output to 1. 3 FE Framing error. 0 DTR Data terminal ready. Set when the stop bit is invalid. Set by user to force the DTR output to 0. Cleared automatically. Cleared by user to force the DTR output to 1. 2 PE Parity error. Set when a parity error occurs. UART Status Register 0 Cleared automatically. 1 OE Overrun error. COMSTA0 Register Set automatically if data is overwritten Name: COMSTA0 before being read. Cleared automatically. Address: 0xFFFF0714 0 DR Data ready. Default value: 0x60 Set automatically when COMRX is full. Cleared by reading COMRX. Access: Read only Function: This 8-bit read-only register reflects the current status on the UART. Rev. F | Page 84 of 107

Data Sheet ADuC7060/ADuC7061 UART Status Register 1 Table 94. COMIEN0 MMR Bit Designations COMSTA1 Register Bit Name Description Name: COMSTA1 7:4 Reserved. Not used. 3 EDSSI Modem status interrupt enable bit. Address: 0xFFFF0718 Set by user to enable generation of an Default value: 0x00 interrupt if COMSTA1[4] or COMSTA1[0] are set. Cleared by user. Access: Read only 2 ELSI Receive status interrupt enable bit. Set by user to enable generation of an Function: COMSTA1 is a modem status register. interrupt if any of the COMSTA0[3:1] register bits are set. Table 93. COMSTA1 MMR Bit Designations Cleared by user. Bit Name Description 1 ETBEI Enable transmit buffer empty interrupt. 7:5 Reserved. Not used. Set by user to enable an interrupt when the 4 CTS Clear to send. buffer is empty during a transmission; that is, 3:1 Reserved. Not used. when COMSTA0[5] is set. 0 DCTS Delta CTS. Cleared by user. Set automatically if CTS changed state since 0 ERBFI Enable receive buffer full interrupt. COMSTA1 was last read. Set by user to enable an interrupt when the Cleared automatically by reading COMSTA1. buffer is full during a reception. Cleared by user. UART Interrupt Enable Register 0 UART Interrupt Identification Register 0 COMIEN0 Register COMIID0 Register Name: COMIEN0 Name: COMIID0 Address: 0xFFFF0704 Address: 0xFFFF0708 Default value: 0x00 Default value: 0x01 Access: Read and write Access: Read only Function: This 8-bit register enables and disables the individual UART interrupt sources. Function: This 8-bit register reflects the source of the UART interrupt. Rev. F | Page 85 of 107

ADuC7060/ADuC7061 Data Sheet Table 95. COMIID0 MMR Bit Designations Table 96. COMDIV2 MMR Bit Designations Status Clearing Bit Name Description Bits[2:1] Bit 0 Priority Definition Operation 15 FBEN Fractional baud rate generator enable bit. 00 1 No interrupt Set by user to enable the fractional baud 11 0 1 Receive line Read rate generator. status COMSTA0 Cleared by user to generate the baud rate interrupt using the standard 450 UART baud rate 10 0 2 Receive Read COMRX generator. buffer full 14:13 Reserved. interrupt 12:11 FBM[1:0] M. If FBM = 0, M = 4. See Equation 2 for the 01 0 3 Transmit Write data to calculation of the baud rate using a buffer empty COMTX or fractional divider and Table 88 for common interrupt read COMIID0 baud rate values. 00 0 4 Modem Read 10:0 FBN[10:0] N. See Equation 2 for the calculation of the status COMSTA1 baud rate using a fractional divider and interrupt register Table 88 for common baud rate values. UART Fractional Divider Register This 16-bit register (COMDIV2) controls the operation of the fractional divider for the ADuC7060/ADuC7061. COMDIV2 Register Name: COMDIV2 Address: 0xFFFF072C Default value: 0x0000 Access: Read and write Rev. F | Page 86 of 107

Data Sheet ADuC7060/ADuC7061 I2C Each ADuC7060/ADuC7061 incorporates an I2C peripheral • In I2C master mode, the ADuC7060/ADuC7061 supports that can be configured as a fully I2C-compatible I2C bus master continuous reads from a single slave up to 512 bytes in a device or as a fully I2C bus-compatible slave device. The two single transfer sequence. pins used for data transfer, SDA and SCL, are configured in a • Clock stretching can be enabled by other devices on wire-AND’ed format that allows arbitration in a multimaster the bus without causing any issues with the ADuC7060/ system. These pins require external pull-up resistors. Typical ADuC7061. However, the ADuC7060/ADuC7061 cannot pull-up resistor values are between 4.7 kΩ and 10 kΩ. enable clock stretching. Users program the I2C bus peripheral (addressed in the I2C bus • In slave mode, the ADuC7060/ADuC7061 can be system). This ID can be modified any time that a transfer is not programmed to return a no acknowledge (NACK). This in progress. The user can configure the interface to respond to allows the validation of checksum bytes at the end of I2C four slave addresses. transfers. • Bus arbitration in master mode is supported. The transfer sequence of an I2C system consists of a master • Internal and external loopback modes are supported for device initiating a transfer by generating a start condition while I2C hardware testing. the bus is idle. The master transmits the slave device address • The transmit and receive circuits in both master and slave and the direction of the data transfer (read or write) during the modes contain 2-byte FIFOs. Status bits are available to the initial address transfer. If the master does not lose arbitration user to control these FIFOs. and the slave acknowledges, the data transfer is initiated. This continues until the master issues a stop condition and the bus CONFIGURING EXTERNAL PINS FOR I2C becomes idle. FUNCTIONALITY The I2C peripheral can be configured only as a master or a slave The I2C functions of the P0.1/SCLK/SCL and P0.3/MOSI/SDA at any given time. The same I2C channel cannot simultaneously pins of the ADuC7060/ADuC7061 device are P0.1 and P0.3. support master and slave modes. The function of P0.1 is the I2C clock signal (SCL) and the The I2C interface on the ADuC7060/ADuC7061 includes the function of P0.3 is the I2C data signal (SDA). To configure P0.1 following features: and P0.3 for I2C mode, Bit 4 and Bit 12 of the GP0CON0 register must be set to 1. Bit 1 of the GP0CON1 register must • Support for repeated start conditions. In master mode, the also be set to 1 to enable I2C mode. ADuC7060/ADuC7061 can be programmed to generate a repeated start. In slave mode, the ADuC7060/ADuC7061 Note that, to write to GP0CON1, the GP0KEY1 register must recognizes repeated start conditions. be set to 0x7 immediately before writing to GP0CON1. Also, • In master and slave modes, the part recognizes both 7-bit the GP0KEY2 register must be set to 0x13 immediately after and 10-bit bus addresses. writing to GP0CON1. The following code example shows this in detail: GP0CON0 = BIT4 + BIT12; // Select SPI/I2C alternative function for P0.1 and P0.3 GP0KEY1 = 0x7; // Write to GP0KEY1 GP0CON1 = BIT1; // Select I2C functionality for P0.1 and P0.3 GP0KEY2 = 0x13; // Write to GP0KEY2 Rev. F | Page 87 of 107

ADuC7060/ADuC7061 Data Sheet SERIAL CLOCK GENERATION I2CID0[7:1] = Address Bits[6:0]. The I2C master in the system generates the serial clock for a I2CID1[2:0] = Address Bits[9:7]. transfer. The master channel can be configured to operate in I2CID1[7:3] must be set to 11110b. fast mode (400 kHz) or standard mode (100 kHz). Master Mode The bit rate is defined in the I2CDIV MMR as follows: In master mode, the I2CADR0 register is programmed with the f I2C address of the device. f = UCLK SERIALCLOCK (2+DIVH) + (2 + DIVL) In 7-bit address mode, I2CADR0[7:1] are set to the device where: address. I2CADR0[0] is the read/write bit. fUCLK is the clock before the clock divider. In 10-bit address mode, the 10-bit address is created as follows: DIVH is the high period of the clock. I2CADR0[7:3] must be set to 11110b. DIVL is the low period of the clock. I2CADR0[2:1] = Address Bits[9:8]. Thus, for 100 kHz operation I2CADR1[7:0] = Address Bits[7:0]. DIVH = DIVL = 0x33 I2CADR0[0] is the read/write bit. and for 400 kHz I2C REGISTERS DIVH = 0x0A, DIVL = 0x0F The I2C peripheral interface consists overall of 19 MMRs. Nine The I2CDIV register corresponds to DIVH:DIVL. of these are master related only, nine are slave related only, and I2C BUS ADDRESSES one MMR is common to both master and slave modes. Slave Mode I2C Master Registers In slave mode, the I2CID0, I2CID1, I2CID2, and I2CID3 I2C Master Control, I2CMCON Register registers contain the device IDs. The device compares the four Name: I2CMCON I2CIDx registers to the address byte received from the bus master. To be correctly addressed, the 7 MSBs of any ID register Address: 0xFFFF0900 must be identical to the 7 MSBs of the first received address byte. The least significant bit of the ID registers (the transfer Default 0x0000 direction bit) is ignored in the process of address recognition. value: The ADuC7060/ADuC7061 also supports 10-bit addressing Access: Read and write mode. When Bit 1 of I2CSCON (ADR10EN bit) is set to 1, then one 10-bit address is supported in slave mode and is stored in Function: This 16-bit MMR configures the I2C peripheral in the I2CID0 and I2CID1 registers. The 10-bit address is derived master mode. as follows: I2CID0[0] is the read/write bit and is not part of the I2C address. Rev. F | Page 88 of 107

Data Sheet ADuC7060/ADuC7061 Table 97. I2CMCON MMR Bit Designations Bit Name Description 15:9 Reserved. These bits are reserved and should not be written to. 8 I2CMCENI I2C transmission complete interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this interrupt source. 7 I2CNACKENI I2C no acknowledge (NACK) received interrupt enable bit. Set this bit to enable interrupts when the I2C master receives a no acknowledge. Clear this interrupt source. 6 I2CALENI I2C arbitration lost interrupt enable bit. Set this bit to enable interrupts when the I2C master did not gain control of the I2C bus. Clear this interrupt source. 5 I2CMTENI I2C transmit interrupt enable bit. Set this bit to enable interrupts when the I2C master has transmitted a byte. Clear this interrupt source. 4 I2CMRENI I2C receive interrupt enable bit. Set this bit to enable interrupts when the I2C master receives data. Cleared by user to disable interrupts when the I2C master is receiving data. 3 Reserved. A value of 0 should be written to this bit. 2 I2CILEN I2C internal loopback enable. Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their respective input signals. Cleared by user to disable loopback mode. 1 I2CBD I2C master backoff disable bit. Set this bit to allow the device to compete for control of the bus even if another device is currently driving a start condition. Clear this bit to back off until the I2C bus becomes free. 0 I2CMEN I2C master enable bit. Set by user to enable the I2C master mode. Cleared to disable the I2C master mode. Rev. F | Page 89 of 107

ADuC7060/ADuC7061 Data Sheet I2C Master Status, I2CMSTA, Register Name: I2CMSTA Address: 0xFFFF0904 Default value: 0x0000 Access: Read only Function: This 16-bit MMR is the I2C status register in master mode. Table 98. I2CMSTA MMR Bit Designations Bit Name Description 15:11 Reserved. These bits are reserved. 10 I2CBBUSY I2C bus busy status bit. This bit is set to 1 when a start condition is detected on the I2C bus. This bit is cleared when a stop condition is detected on the bus. 9 I2CMRxFO Master receive FIFO overflow. This bit is set to 1 when a byte is written to the receive FIFO when it is already full. This bit is cleared in all other conditions. 8 I2CMTC I2C transmission complete status bit. This bit is set to 1 when a transmission is complete between the master and the slave with which it was communicating. If the I2CMCENI bit in I2CMCON is set, an interrupt is generated when this bit is set. Clear this interrupt source. 7 I2CMND I2C master no acknowledge data bit This bit is set to 1 when a no acknowledge condition is received by the master in response to a data write transfer. If the I2CNACKENI bit in I2CMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 6 I2CMBUSY I2C master busy status bit. Set to 1 when the master is busy processing a transaction. Cleared if the master is ready or if another master device has control of the bus. 5 I2CAL I2C arbitration lost status bit. This bit is set to 1 when the I2C master does not gain control of the I2C bus. If the I2CALENI bit in I2CMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 4 I2CMNA I2C master no acknowledge address bit. This bit is set to 1 when a no acknowledge condition is received by the master in response to an address. If the I2CNACKENI bit in I2CMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 3 I2CMRXQ I2C master receive request bit. This bit is set to 1 when data enters the receive FIFO. If the I2CMRENI in I2CMCON is set, an interrupt is generated. This bit is cleared in all other conditions. 2 I2CMTXQ I2C master transmit request bit. This bit goes high if the transmit FIFO is empty or contains only one byte and the master has transmitted an address + write. If the I2CMTENI bit in I2CMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 1:0 I2CMTFSTA I2C master transmit FIFO status bits. [00] = I2C master transmit FIFO empty. [01] = 1 byte in master transmit FIFO. [10] = 1 byte in master transmit FIFO. [11] = I2C master transmit FIFO full. Rev. F | Page 90 of 107

Data Sheet ADuC7060/ADuC7061 I2C Master Receive, I2CMRX, Register I2C Master Current Read Count, I2CMCNT1, Register Name: I2CMRX Name: I2CMCNT1 Address: 0xFFFF0908 Address: 0xFFFF0914 Default value: 0x00 Default value: 0x00 Access: Read only Access: Read only Function: This 8-bit MMR is the I2C master receive Function: This 8-bit MMR holds the number of bytes register. received so far during a read sequence with a slave device. I2C Master Transmit, I2CMTX, Register I2C Address 0, I2CADR0, Register Name: I2CMTX Name: I2CADR0 Address: 0xFFFF090C Address: 0xFFFF0918 Default value: 0x00 Default value: 0x00 Access: Write only Access: Read and write Function: This 8-bit MMR is the I2C master transmit register. Function: This 8-bit MMR holds the 7-bit slave address and the read/write bit when the master begins I2C Master Read Count, I2CMCNT0, Register communicating with a slave. Name: I2CMCNT0 Table 100. I2CADR0 MMR in 7-Bit Address Mode Address: 0xFFFF0910 Bit Name Description Default value: 0x0000 7:1 I2CADR These bits contain the 7-bit address of the required slave device. Access: Read and write 0 R/W Bit 0 is the read/write bit. When this bit = 1, a read sequence is requested. Function: This 16-bit MMR holds the required number When this bit = 0, a write sequence is requested. of bytes when the master begins a read sequence from a slave device. Table 101. I2CADR0 MMR in 10-Bit Address Mode Bit Name Description Table 99. I2CMCNT0 MMR Bit Designations 7:3 These bits must be set to [11110b] in 10-bit Bit Name Description address mode. 15:9 Reserved. 2:1 I2CMADR These bits contain ADDR[9:8] in 10-bit 8 I2CRECNT Set this bit if more than 256 bytes are addressing mode. required from the slave. 0 R/W Read/write bit. Clear this bit when reading 256 bytes or When this bit = 1, a read sequence is fewer. requested. 7:0 I2CRCNT These eight bits hold the number of bytes When this bit = 0, a write sequence is required during a slave read sequence, requested. minus 1. If only a single byte is required, set these bits to 0. Rev. F | Page 91 of 107

ADuC7060/ADuC7061 Data Sheet I2C Address 1, I2CADR1, Register I2C Master Clock Control, I2CDIV, Register Name: I2CADR1 Name: I2CDIV Address: 0xFFFF091C Address: 0xFFFF0924 Default value: 0x00 Default value: 0x1F1F Access: Read and write Access: Read and write Function: This 8-bit MMR is used in 10-bit addressing Function: This MMR controls the frequency of the I2C clock generated by the master on to the SCL mode only. This register contains the least significant byte of the address. pin. For further details, see the Serial Clock Generation section. Table 102. I2CADR1 MMR in 10-Bit Address Mode Table 103. I2CDIV MMR Bit Designations Bit Name Description Bit Name Description 7:0 I2CLADR These bits contain ADDR[7:0] in 10-bit 15:8 DIVH These bits control the duration of the high addressing mode. period of SCL. 7:0 DIVL These bits control the duration of the low period of SCL. I2C Slave Registers I2C Slave Control, I2CSCON, Register Name: I2CSCON Address: 0xFFFF0928 Default value: 0x0000 Access: Read and write Function: This 16-bit MMR configures the I2C peripheral in slave mode. Rev. F | Page 92 of 107

Data Sheet ADuC7060/ADuC7061 Table 104. I2CSCON MMR Bit Designations Bit Name Description 15:11 Reserved bits. 10 I2CSTXENI Slave transmit interrupt enable bit. Set this bit to enable an interrupt after a slave transmits a byte. Clear this interrupt source. 9 I2CSRXENI Slave receive interrupt enable bit. Set this bit to enable an interrupt after the slave receives data. Clear this interrupt source. 8 I2CSSENI I2C stop condition detected interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this interrupt source. 7 I2CNACKEN I2C no acknowledge enable bit. Set this bit to no acknowledge the next byte in the transmission sequence. Clear this bit to let the hardware control the acknowledge/no acknowledge sequence. 6 Reserved. A value of 0 should be written to this bit. 5 I2CSETEN I2C early transmit interrupt enable bit. Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit transmission. Clear this bit to enable a transmit request interrupt just after the negative edge of SCL during the read bit transmission. 4 I2CGCCLR I2C general call status and ID clear bit. Writing a 1 to this bit clears the general call status and ID bits in the I2CSSTA register. Clear this bit at all other times. 3 I2CHGCEN Hardware general call enable. When this bit and Bit 2 are set, and having received a general call (Address 0x00) and a data byte, the device checks the contents of the I2CALT against the receive register. If the contents match, the device has received a hardware general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a “to whom it may concern” call. The ADuC7060/ ADuC7061 watches for these addresses. The device that requires attention embeds its own address into the message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately. The LSB of the I2CALT register should always be written to 1, as per the I2C January 2000 bus specification. 2 I2CGCEN General call enable bit. Set this bit to enable the slave device to acknowledge an I2C general call, Address 0x00 (write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave address by hardware) as the data byte, the I2C interface resets as per the I2C January 2000 bus specification. This command can be used to reset an entire I2C system. If it receives a 0x04 (write programmable part of the slave address by hardware) as the data byte, the general call interrupt status bit sets on any general call. The user must take corrective action by reprogramming the device address. 1 ADR10EN I2C 10-bit address mode. Set to 1 to enable 10-bit address mode. Clear to 0 to enable normal address mode. 0 I2CSEN I2C slave enable bit. Set by user to enable I2C slave mode. Clear to disable I2C slave mode. Rev. F | Page 93 of 107

ADuC7060/ADuC7061 Data Sheet I2C Slave Status, I2CSSTA, Register Name: I2CSSTA Address: 0xFFFF092C Default value: 0x0000 Access: Read and write Function: This 16-bit MMR is the I2C status register in slave mode. Table 105. I2CSSTA MMR Bit Designations Bit Name Description 15 Reserved bit. 14 I2CSTA This bit is set to 1 if a start condition followed by a matching address is detected, a start byte (0x01) is received, or general calls are enabled and a general call code of 0x00 is received. This bit is cleared on receiving a stop condition 13 I2CREPS This bit is set to 1 if a repeated start condition is detected. This bit is cleared on receiving a stop condition. A read of the I2CSSTA register also clears this bit. 12:11 I2CID[1:0] I2C address matching register. These bits indicate which I2CIDx register matches the received address. [00] = received address matches I2CID0. [01] = received address matches I2CID1. [10] = received address matches I2CID2. [11] = received address matches I2CID3. 10 I2CSS I2C stop condition after start detected bit. This bit is set to 1 when a stop condition is detected after a previous start and matching address. When the I2CSSENI bit in I2CSCON is set, an interrupt is generated. This bit is cleared by reading this register. 9:8 I2CGCID[1:0] I2C general call ID bits. [00] = no general call received. [01] = general call reset and program address. [10] = general program address. [11] = general call matching alternative ID. Note that these bits are not cleared by a general call reset command. Clear these bits by writing a 1 to the I2CGCCLR bit in I2CSCON. 7 I2CGC I2C general call status bit. This bit is set to 1 if the slave receives a general call command of any type. If the command received was a reset command, then all registers return to their default states. If the command received was a hardware general call, the receive FIFO holds the second byte of the command, and this can be compared with the I2CALT register. Clear this bit by writing a 1 to the I2CGCCLR bit in I2CSCON. 6 I2CSBUSY I2C slave busy status bit. Set to 1 when the slave receives a start condition. Cleared by hardware if the received address does not match any of the I2CIDx registers, the slave device receives a stop condition, or a repeated start address does not match any of the I2CIDx registers. 5 I2CSNA I2C slave no acknowledge data bit. This bit is set to 1 when the slave responds to a bus address with a no acknowledge. This bit is asserted under the following conditions: if a no acknowledge was returned because there was no data in the transmit FIFO or if the I2CNACKEN bit was set in the I2CSCON register. This bit is cleared in all other conditions. 4 I2CSRxFO Slave receive FIFO overflow. This bit is set to 1 when a byte is written to the receive FIFO when it is already full. This bit is cleared in all other conditions. 3 I2CSRXQ I2C slave receive request bit. This bit is set to 1 when the receive FIFO of the slave is not empty. This bit causes an interrupt to occur if the I2CSRXENI bit in I2CSCON is set. The receive FIFO must be read or flushed to clear this bit. Rev. F | Page 94 of 107

Data Sheet ADuC7060/ADuC7061 Bit Name Description 2 I2CSTXQ I2C slave transmit request bit. This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in I2CSCON is =0, this bit goes high just after the negative edge of SCL during the read bit transmission. If the I2CSETEN bit in I2CSCON is =1, this bit goes high just after the positive edge of SCL during the read bit transmission. This bit causes an interrupt to occur if the I2CSTXENI bit in I2CSCON is set. This bit is cleared in all other conditions. 1 I2CSTFE I2C slave FIFO underflow status bit. This bit goes high if the transmit FIFO is empty when a master requests data from the slave. This bit is asserted at the rising edge of SCL during the read bit. This bit is cleared in all other conditions. 0 I2CETSTA I2C slave early transmit FIFO status bit. If the I2CSETEN bit in I2CSCON is =0, this bit goes high if the slave transmit FIFO is empty. If the I2CSETEN bit in I2CSCON = 1, this bit goes high just after the positive edge of SCL during the write bit transmission. This bit asserts once only for a transfer. This bit is cleared after being read. I2C Slave Receive, I2CSRX, Register I2C Hardware General Call Recognition, I2CALT, Register Name: I2CSRX Name: I2CALT Address: 0xFFFF0930 Address: 0xFFFF0938 Default value: 0x00 Default value: 0x00 Access: Read only Access: Read and write Function: This 8-bit MMR is the I2C slave receive register. Function: This 8-bit MMR is used with hardware general calls when the I2CSCON Bit 3 is set to 1. This I2C Slave Transmit, I2CSTX, Register register is used in cases where a master is Name: I2CSTX unable to generate an address for a slave and, instead, the slave must generate the address for Address: 0xFFFF0934 the master. Default value: 0x00 I2C Slave Device ID, I2CIDx, Registers Access: Write only Name: I2CIDx Function: This 8-bit MMR is the I2C slave transmit Addresses: 0xFFFF093C = I2CID0 register. 0xFFFF0940 = I2CID1 0xFFFF0944 = I2CID2 0xFFFF0948 = I2CID3 Default value: 0x00 Access: Read and write Function: These 8-bit MMRs are programmed with the I2C bus IDs of the slave. See the I2C Bus Addresses section for further details. Rev. F | Page 95 of 107

ADuC7060/ADuC7061 Data Sheet I2C Common Registers Table 106. I2CFSTA MMR Bit Designations I2C FIFO Status, I2CFSTA, Register Bit Name Description Name: I2CFSTA 15:10 Reserved bits. 9 I2CFMTX Set this bit to 1 to flush the master Address: 0xFFFF094C transmit FIFO. Default value: 0x0000 8 I2CFSTX Set this bit to 1 to flush the slave transmit FIFO. Access: Read and write 7:6 I2CMRXSTA I2C master receive FIFO status bits. [00] = FIFO empty. Function: This 16-bit MMR contains the status of the [01] = byte written to FIFO. receive/transmit FIFOs in both master and [10] = one byte in FIFO. slave modes. [11] = FIFO full. 5:4 I2CMTXSTA I2C master transmit FIFO status bits. [00] = FIFO empty. [01] = byte written to FIFO. [10] = one byte in FIFO. [11] = FIFO full. 3:2 I2CSRXSTA I2C slave receive FIFO status bits. [00] = FIFO empty [01] = byte written to FIFO [10] = one byte in FIFO [11] = FIFO full 1:0 I2CSTXSTA I2C slave transmit FIFO status bits. [00] = FIFO empty. [01] = byte written to FIFO. [10] = one byte in FIFO. [11] = FIFO full. Rev. F | Page 96 of 107

Data Sheet ADuC7060/ADuC7061 SERIAL PERIPHERAL INTERFACE The ADuC7060/ADuC7061 integrates a complete hardware In slave mode, the SPICON register must be configured with serial peripheral interface (SPI) on chip. SPI is an industry the phase and polarity of the expected input clock. The slave standard, synchronous serial interface that allows eight bits of accepts data from an external master up to 5.12 Mbps. data to be synchronously transmitted and simultaneously In both master and slave modes, data transmit on one edge of received, that is, full duplex up to a maximum bit rate of the SCLK signal and sample on the other. Therefore, it is 2.56 Mbps. important that the polarity and phase be configured the same The SPI port can be configured for master or slave operation for the master and slave devices. and typically consists of four pins: MISO, MOSI, SCLK, and SS. SLAVE SELECT (P0.0/SS) INPUT PIN MISO (MASTER IN, SLAVE OUT) PIN In SPI slave mode, a transfer is initiated by the assertion of SS The MISO pin is configured as an input line in master mode on the P0.0/SS pin, which is an active low input signal. The SPI and an output line in slave mode. The MISO line on the master port then transmits and receives 8-bit data until the transfer is (data in) should be connected to the MISO line in the slave concluded by deassertion of SS. In slave mode, SS is always an device (data out). The data is transferred as byte wide (8-bit) input. serial data, most significant bit first. In SPI master mode, SS is an active low output signal. It asserts MOSI (MASTER OUT, SLAVE IN) PIN itself automatically at the beginning of a transfer and deasserts The MOSI pin is configured as an output line in master mode itself upon completion. and an input line in slave mode. The MOSI line on the master CONFIGURING EXTERNAL PINS FOR SPI (data out) should be connected to the MOSI line in the slave FUNCTIONALITY device (data in). The data is transferred as byte wide (8-bit) The SPI pins of the ADuC7060/ADuC7061 device are serial data, most significant bit first. represented by the P0[0:3] function of the following pins: SCLK (SERIAL CLOCK I/O) PIN • P0.0/SS is the slave chip select pin. In slave mode, this pin The master serial clock (SCL) synchronizes the data being is an input and must be driven low by the master. In transmitted and received through the MOSI SCLK period. master mode, this pin is an output and goes low at the Therefore, a byte is transmitted/received after eight SCLK beginning of a transfer and high at the end of a transfer. periods. The SCLK pin is configured as an output in master • P0.1/SCLK/SCL is the SCLK pin. mode and as an input in slave mode. • P0.2/MISO is the master in, slave out (MISO) pin. In master mode, polarity and phase of the clock are controlled • P0.3/MOSI/SDA is the master out, slave in (MOSI) pin. by the SPICON register, and the bit rate is defined in the SPIDIV register as follows: To configure P0.0 to P0.3 for SPI mode, Bit 0, Bit 4, Bit 8, and Bit 12 of the GP0CON0 register must be set to 1. Bit 1 of the f f = UCLK GP0CON1 must be set to 1. Note that to write to GP0CON1, SERIALCLOCK 2×(1+SPIDIV) the GP0KEY1 register must be set to 0x7 immediately before The maximum speed of the SPI clock is independent of the writing to GP0CON1. Also, the GP0KEY2 register must be set clock divider bits. to 0x13 immediately after writing to GP0CON1. The following code example shows this in detail: GP0CON0 = BIT0 + BIT4 + BIT8 + BIT12; //Select SPI/I2C alternative function for P0[0...3] GP0KEY1 = 0x7; //Write to GP0KEY1 GP0CON1 &=~ BIT1; //Select SPI functionality for P0.0 to P0.3 GP0KEY2 = 0x13; //Write to GP0KEY2 Rev. F | Page 97 of 107

ADuC7060/ADuC7061 Data Sheet SPI REGISTERS The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON. SPI Status Register SPISTA Register Name: SPISTA Address: 0xFFFF0A00 Default value: 0x00000000 Access: Read only Function: This 32-bit MMR contains the status of the SPI interface in both master and slave modes. Table 107. SPISTA MMR Bit Designations Bit Name Description 15:12 Reserved bits. 11 SPIREX SPI receive FIFO excess bytes present. This bit is set when there are more bytes in the receive FIFO than indicated in the SPIMDE bits in SPICON. This bit is cleared when the number of bytes in the FIFO is equal to or less than the number in SPIMDE. 10:8 SPIRXFSTA[2:0] SPI receive FIFO status bits. [000] = receive FIFO is empty. [001] = 1 valid byte in the FIFO. [010] = 2 valid bytes in the FIFO. [011] = 3 valid bytes in the FIFO. [100] = 4 valid bytes in the FIFO. 7 SPIFOF SPI receive FIFO overflow status bit. Set when the receive FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt except when SPIRFLH is set in SPICON. Cleared when the SPISTA register is read. 6 SPIRXIRQ SPI receive IRQ status bit. Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required number of bytes has been received. Cleared when the SPISTA register is read. 5 SPITXIRQ SPI transmit IRQ status bit. Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number of bytes has been transmitted. Cleared when the SPISTA register is read. 4 SPITXUF SPI transmit FIFO underflow. This bit is set when a transmit is initiated without any valid data in the transmit FIFO. This bit generates an interrupt except when SPITFLH is set in SPICON. Cleared when the SPISTA register is read. 3:1 SPITXFSTA[2:0] SPI transmit FIFO status bits. [000] = transmit FIFO is empty. [001] = 1 valid bytes in the FIFO. [010] = 2 valid bytes in the FIFO. [011] = 3 valid bytes in the FIFO. [100] = 4 valid bytes in the FIFO. 0 SPIISTA SPI interrupt status bit. Set to 1 when an SPI based interrupt occurs. Cleared after reading SPISTA. Rev. F | Page 98 of 107

Data Sheet ADuC7060/ADuC7061 SPI Receive Register Table 108. SPIDIV MMR Bit Designations SPIRX Register Bit Description Name: SPIRX 7:6 Reserved. 5:0 SPI Baud rate setting: Address: 0xFFFF0A04 f = fUCLK Default value: 0x00 SERIALCLOCK 2×(1+SPIDIV) Access: Read only SPI Control Register SPICON Register Function: This 8-bit MMR is the SPI receive register. Name: SPICON SPI Transmit Register Address: 0xFFFF0A10 SPITX Register Name: SPITX Default value: 0x0000 Address: 0xFFFF0A08 Access: Read and write Default value: 0x00 Function: This 16-bit MMR configures the SPI peripheral in both master and slave modes. Access: Write only Function: This 8-bit MMR is the SPI transmit register. SPI Baud Rate Selection Register SPIDIV Register Name: SPIDIV Address: 0xFFFF0A0C Default value: 0x1B Access: Write only Function: This 8-bit MMR is the SPI baud rate selection register. Rev. F | Page 99 of 107

ADuC7060/ADuC7061 Data Sheet Table 109. SPICON MMR Bit Designations Bit Name Description 15:14 SPIMDE SPI IRQ mode bits. These bits are configured when transmit/receive interrupts occur in a transfer. [00] = transmit interrupt occurs when 1 byte has been transferred. Receive interrupt occurs when one or more bytes have been received into the FIFO. [01] = transmit interrupt occurs when 2 bytes have been transferred. Receive interrupt occurs when two or more bytes have been received into the FIFO. [10] = transmit interrupt occurs when 3 bytes have been transferred. Receive interrupt occurs when three or more bytes have been received into the FIFO. [11] = transmit interrupt occurs when 4 bytes have been transferred. Receive interrupt occurs when the receive FIFO is full or 4 bytes are present. 13 SPITFLH SPI transmit FIFO flush enable bit. Set this bit to flush the transmit FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted, depending on the SPIZEN bit. Any writes to the transmit FIFO are ignored while this bit is set. Clear this bit to disable transmit FIFO flushing. 12 SPIRFLH SPI receive FIFO flush enable bit. Set this bit to flush the receive FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is set, all incoming data is ignored and no interrupts are generated. If set and SPITMDE = 0, a read of the receive FIFO initiates a transfer. Clear this bit to disable receive FIFO flushing. 11 SPICONT Continuous transfer enable. Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the transmit register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until the transmit register is empty. Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle. 10 SPILP Loopback enable bit. Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode. 9 SPIOEN Slave MISO output enable bit. Set this bit for MISO to operate as normal. Clear this bit to disable the output driver on the MISO pin. The MISO pin is open drain when this bit is cleared. 8 SPIROW SPIRX overflow overwrite enable. Set by user, the valid data in the receive register is overwritten by the new serial byte received. Cleared by user, the new serial byte received is discarded. 7 SPIZEN SPI transmit zeros when transmit FIFO is empty. Set this bit to transmit 0x00 when there is no valid data in the transmit FIFO. Clear this bit to transmit the last transmitted value when there is no valid data in the transmit FIFO. 6 SPITMDE SPI transfer and interrupt mode. Set by user to initiate transfer with a write to the SPITX register. Interrupt occurs only when the transmit FIFO is empty. Cleared by user to initiate transfer with a read of the SPI register. Interrupt occurs only when the receive FIFO is full. 5 SPILF LSB first transfer enable bit. Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first. 4 SPIWOM SPI wired or mode enable bit. Set to 1 to enable the open-drain data output enable. External pull-ups are required on data out pins. Clear for normal output levels. 3 SPICPO Serial clock polarity mode bit. Set by user, the serial clock idles high. Cleared by user, the serial clock idles low. 2 SPICPH Serial clock phase mode bit. Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the serial clock pulses at the end of each serial bit transfer. Rev. F | Page 100 of 107

Data Sheet ADuC7060/ADuC7061 Bit Name Description 1 SPIMEN Master mode enable bit. Set by user to enable master mode. Cleared by user to enable slave mode. 0 SPIEN SPI enable bit. Set by user to enable the SPI. Cleared by user to disable the SPI. Rev. F | Page 101 of 107

ADuC7060/ADuC7061 Data Sheet GENERAL-PURPOSE I/O The ADuC7060/ADuC7061 features up to 16 general-purpose When the ADuC7060/ADuC7061 enters power-saving mode, bidirectional input/output (GPIO) pins. In general, many of the the GPIO pins retain their state. GPIO pins have multiple functions that are configurable by user The GPIO pins are grouped into three port buses. code. By default, the GPIO pins are configured in GPIO mode. All Table 110 lists all the GPIO pins and their alternative functions. GPIO pins have an internal pull-up resistor with a drive capability A GPIO pin alternative function can be selected by writing to of 1.6 mA. the correct bits of the GPxCON register. All I/O pins are 3.3 V tolerant, meaning that the GPIOs support an input voltage of 3.3 V. Table 110. GPIO Multifunction Pin Descriptions Configuration via GPxCON Including GP0CON0 Port Pin Mnemonic 00 01 0 P0.0/SS GPIO SS (SPI slave select). P0.1/SCLK/SCL GPIO SCLK/SCL (serial clock/SPI clock). P0.2/MISO GPIO MISO (SPI—master in/slave out). P0.3/MOSI/SDA GPIO MOSI (SPI—master out/slave in). P0.4/IRQ0/PWM1 GPIO/IRQ0 PWM1 (PWM Output 1). P0.5/CTS GPIO CTS. UART clear to send pin. P0.6/RTS GPIO RTS. UART request to send pin. 1 P1.0/IRQ1/SIN/T0 GPIO/IRQ1 SIN (serial input). P1.1/SOUT GPIO SOUT (serial output). P1.2/SYNC GPIO PWM sync (PWM sync input pin). P1.3/TRIP GPIO PWM trip (PWM trip input pin). P1.4/PWM2 GPIO PWM2 (PWM Output 2). P1.5/PWM3 GPIO PWM3 (PWM Output 3). P1.6/PWM4 GPIO PWM4 (PWM Output 4). 2 P2.0/IRQ2/PWM0/EXTCLK GPIO/IRQ2/EXTCLK PWM0 (PWM Output 0). P2.1/IRQ3/PWM5 GPIO/IRQ3 PWM5 (PWM Output 5). GPxCON REGISTERS GPxCON are the Port x (where x is 0, 1, or 2) control registers, which select the function of each pin of Port x as described in Table 112. Table 111. GPxCON Registers Name Address Default Value Access GP0CON0 0xFFFF0D00 0x00000000 R/W GP1CON 0xFFFF0D04 0x00000000 R/W GP2CON 0xFFFF0D08 0x00000000 R/W Rev. F | Page 102 of 107

Data Sheet ADuC7060/ADuC7061 Table 112. GPxCON MMR Bit Designations GPxSET REGISTERS Bit Description GPxSET are data set Port x registers. 31:30 Reserved. 29:28 Reserved. Table 115. GPxSET Registers 27:26 Reserved. Name Address Default Value Access 25:24 Selects the function of the P0.6/RTS and P1.6/PWM pins. GP0SET 0xFFFF0D24 0x000000XX W 23:22 Reserved. GP1SET 0xFFFF0D34 0x000000XX W 21:20 Selects the function of the P0.5/CTS and P1.5/PWM3 pins. GP2SET 0xFFFF0D44 0x000000XX W 19:18 Reserved. Table 116. GPxSET MMR Bit Designations 17:16 Selects the function of the P0.4/IRQ0/PWM1 and P1.4/PWM2 pins. Bit Description 15:14 Reserved. 31:24 Reserved. 13:12 Selects the function of the P0.3/MOSI/SDA and P1.3/TRIP 23:16 Data Port x set bit. pins. Set to 1 by user to set bit on Port x; also sets the 11:10 Reserved. corresponding bit in the GPxDAT MMR. 9:8 Selects the function of the P0.2/MISO and P1.2/SYNC pins. Cleared to 0 by user; does not affect the data output. 7:6 Reserved. 15:0 Reserved. 5:4 Selects the function of the P0.1/SCLK/SCL, P1.1/SOUT, and P2.1/IRQ3/PWM5 pins. GPxCLR REGISTERS 3:2 Reserved. GPxCLR are data clear Port x registers. 1:0 Selects the function of the P0.0/SS, P1.0/IRQ1/SIN/T0, P2.0/IRQ2/PWM0/EXTCLK pins. Table 117. GPxCLR Registers GPxDAT REGISTERS Name Address Default Value Access GP0CLR 0xFFFF0D28 0x000000XX W GPxDAT are Port x configuration and data registers. They con- GP1CLR 0xFFFF0D38 0x000000XX W figure the direction of the GPIO pins of Port x, set the output GP2CLR 0xFFFF0D48 0x000000XX W value for the pins that are configured as output, and store the input value of the pins that are configured as input. Table 118. GPxCLR MMR Bit Designations Bit Description Table 113. GPxDAT Registers 31:24 Reserved. Name Address Default Value Access 23:16 Data Port x clear bit. GP0DAT 0xFFFF0D20 0x000000XX R/W Set to 1 by user to clear the bit on Port x; also clears GP1DAT 0xFFFF0D30 0x000000XX R/W the corresponding bit in the GPxDAT MMR. GP2DAT 0xFFFF0D40 0x000000XX R/W Cleared to 0 by user; does not affect the data output. Table 114. GPxDAT MMR Bit Designations 15:0 Reserved. Bit Description 31:24 Direction of the data. GPxPAR REGISTERS Set to 1 by user to configure the GPIO pin as an output. The GPxPAR registers program the parameters for Port 0, Port 1, Cleared to 0 by user to configure the GPIO pin as an input. and Port 2. Note that the GPxDAT MMR must always be written 23:16 Port x data output. after changing the GPxPAR MMR. Note that it is not possible to 15:8 Reflect the state of Port x pins at reset (read only). disable the internal pull-up resistor on P0.2. 7:0 Port x data input (read only). Table 119. GPxPAR Registers Name Address Default Value Access GP0PAR 0xFFFF0D2C 0x00000000 R/W GP1PAR 0xFFFF0D3C 0x00000000 R/W GP2PAR 0xFFFF0D4C 0x00000000 R/W Rev. F | Page 103 of 107

ADuC7060/ADuC7061 Data Sheet Table 120. GPxPAR MMR Bit Designations Table 122. GP0CON1 MMR Bit Designations Bit Name Description Bit Name Description 31:15 Reserved. 7:2 Reserve These bits must always be set to 0. 23:16 GPL[7:0] General I/O port pin functionality lock d registers. 1 SPII2CS This bit configures the P0.0 to P0.3 functions GPL[7:0] = 0, normal operation. EL in I2C or SPI mode. Note that Bit 0 of GP0CON1 must be set to 0 for this bit to work. GPL[7:0] = 1, for each GPIO pin, if this bit is set, writing to the corresponding bit in To select the P0.0, P0.1, P0.2, and P0.3 GPxCON or GPxDAT register bit has no functions in SPI mode, clear this bit to 0. effect. To select the P0.0, P0.1, P0.2, and P0.3 15:8 GPDS[7:0] Drive strength configuration. This bit is functions in I2C mode, set this bit to 1. configurable. This bit is cleared by default. GPDS[x] = 0, maximum source current is 2 mA. 0 ADCSEL This bit configures the P0.0 to P0.3 functions GPDS[x] = 1, maximum source current is 4 mA. as GPIO pins or as ADC input pins. 7:0 GPPD[7:0] Pull-Up Disable Port x[7:0]. To enable P0.0, P0.1, P0.2 and P0.3 functions as ADC inputs, set this bit to 1. GPPD[x] = 0, pull-up resistor is active. To enable P0.0, P0.1, P0.2, and P0.3 functions GPPD[x] = 1, pull-up resistor is disabled. as digital I/O, clear this bit to 0. This bit is cleared by default. GP0CON1 Control Registers The GP0CON1 write values are as follows: GP0KEY1 = 0x7, GP0CON1 = user value, and GP0KEY2 = 0x13. Name GP0KEY1 Name: GP0CON1 Address: 0xFFFF0464 Address: 0xFFFF0468 Default value: 0xXXXX Default value: 0x00 Access: Write only Access: Read and write Function: When writing to GP0CON1, the value of 0x07 must be written to this register in the Function: This register controls the P0.0, P0.1, P0.2, and instruction immediately before writing to P0.3 functionality of the multifunction GPIO GP0CON1. pins. Table 121. GP0CON1 Write Sequence Name: GP0KEY2 Name Value Address: 0xFFFF046C GP0KEY1 0x7 GP0CON1 User value Default value: 0xXXXX GP0KEY2 0x13 Access: Write only Function: When writing to GP0CON1, the value of 0x13 must be written to this register in the instruction immediately after writing to GP0CON1. Rev. F | Page 104 of 107

Data Sheet ADuC7060/ADuC7061 HARDWARE DESIGN CONSIDERATIONS POWER SUPPLIES DIGITAL BEAD ANALOG SUPPLY SUPPLY The ADuC7060/ADuC7061 operational power supply voltage + – 10µF 10µF range is 2.375 V to 2.625 V. Separate analog and digital power ADuC7060/ supply pins (AVDD and DVDD, respectively) allow AVDD to ADuC7061 be kept relatively free of noisy digital signals often present on AVDD DVDD 0.1µF the system DVDD line. In this mode, the part can also operate with split supplies; that is, it can use different voltage levels for 0.1µF each supply. For example, the system can be designed to AGND operate with a DVDD voltage level of 2.6 V, whereas the AVDD lceovnefli cgaunra btieo ant i2s. 5sh Vo worn vinic eF ivgeurrsea .2 A8. typical split supply DGND 07079-023 Figure 29. External Single Supply Connections DIGITAL ANALOG SUPPLY SUPPLY Notice that in both Figure 28 and Figure 29, a large value (10 µF) + + – 10µF 10µF – reservoir capacitor sits on DVDD, and a separate 10 µF ADuC7060/ capacitor sits on AVDD. In addition, local, small value (0.1 µF) ADuC7061 capacitors are located at each AVDD and DVDD pin of the chip. AVDD DVDD 0.1µF As per standard design practice, be sure to include all of these capacitors and ensure that the smaller capacitors are close to the 0.1µF AVDD pin with trace lengths as short as possible. Connect the AGND ground terminal of each of these capacitors directly to the underlying ground plane. DGND 07079-022 Note that the analog and digital ground pins on the ADuC7060/ ADuC7061 must be referenced to the same system ground Figure 28. External Dual Supply Connections reference point at all times. As an alternative to providing two separate power supplies, the Finally, note that, when the DVDD supply reaches 1.8 V, it must user can reduce noise on AVDD by placing a small series ramp to 2.25 V in less than 128 ms. This is a requirement of the resistor and/or ferrite bead between AVDD and DVDD, and then internal power-on reset circuitry. decoupling AVDD separately to ground. An example of this configuration is shown in Figure 29. With this configuration, other analog circuitry (such as op amps, voltage reference, and others) can be powered from the AVDD supply line as well. Rev. F | Page 105 of 107

ADuC7060/ADuC7061 Data Sheet OUTLINE DIMENSIONS 5.10 0.30 5.00 SQ 0.25 PIN 1 4.90 0.18 INDICATOR PIN 1 25 32 INDICATOR 24 1 0.50 BSC EXPOSED 3.65 PAD 3.50 SQ 3.45 8 17 0.50 16 9 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 3.50 REF 0.80 0.75 0.05 MAX 0.70 0.02 NOM COPLANARITY 0.08 SEATING 0.20 REF PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 04-02-2012-A Figure 30. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body and 0.75 mm Package Height (CP-32-11) Dimensions shown in millimeters 7.00 0.30 BSCSQ 0.23 PIN1 0.18 PIN1 INDICATOR INDICATOR 37 48 36 1 0.50 BSC EXPOSED 4.25 PAD 4.10SQ 3.95 25 12 24 13 0.45 0.20MIN TOPVIEW BOTTOMVIEW 0.40 0.35 FORPROPERCONNECTIONOF 0.80 THEEXPOSEDPAD,REFERTO 0.75 THEPINCONFIGURATIONAND 0.05MAX FUNCTIONDESCRIPTIONS 0.70 0.02NOM SECTIONOFTHISDATASHEET. COPLANARITY 0.08 SEPALTAINNGE COMPLIANTTOJEDEC0.S20TARNEDFARDSMO-220-WKKD. 08-16-2010-B Figure 31. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm × 7 mm Body and 0.75 mm Package Height (CP-48-5) Dimensions shown in millimeters Rev. F | Page 106 of 107

Data Sheet ADuC7060/ADuC7061 9.20 0.75 9.00 SQ 1.60 0.60 MAX 8.80 0.45 48 37 1 36 PIN 1 7.20 1.45 TOP VIEW 7.00 SQ 1.40 0.20 (PINS DOWN) 6.80 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 0.05 SPELAANTEING 0C.O08PLANARITY VIEW A 0.50 0.27 BSC 0.22 LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANTTO JEDEC STANDARDS MS-026-BBC 051706-A Figure 32. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Package Ordering Model1 Temperature Range Package Description Option Quantity ADuC7060BCPZ32 −40°C to +125°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-5 ADuC7060BCPZ32-RL −40°C to +125°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-5 2,500 ADuC7060BSTZ32 −40°C to +125°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 ADuC7060BSTZ32-RL −40°C to +125°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 2,000 ADuC7061BCPZ32 −40°C to +125°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-11 ADuC7061BCPZ32-RL −40°C to +125°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-11 5,000 EVAL-ADuC7060QSPZ ADuC7060 Quick Start Plus Development System EVAL-ADuC7061MKZ ADuC7061 Quick Start Evaluation System 1 Z = RoHS Compliant Part. ©2009–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07079-0-2/17(F) Rev. F | Page 107 of 107

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-ADUC7060QSPZ EVAL-ADUC7061MKZ ADUC7060BSTZ32 ADUC7061BCPZ32-RL ADUC7060BCPZ32 ADUC7060BSTZ32-RL ADUC7060BCPZ32-RL ADUC7061BCPZ32