Blackfin Embedded Processor ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 FEATURES PERIPHERALS Up to 600MHz high performance Blackfin processor USB 2.0 high speed on-the-go (OTG) with integrated PHY Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, IEEE 802.3-compliant 10/100 Ethernet MAC 40-bit shifter Parallel peripheral interface (PPI), supporting ITU-R 656 RISC-like register and instruction model for ease of video data formats programming and compiler-friendly support Host DMA port (HOSTDP) Advanced debug, trace, and performance monitoring 2 dual-channel, full-duplex synchronous serial ports Accepts a wide range of supply voltages for internal and I/O (SPORTs), supporting eight stereo I2S channels operations. See Specifications on Page28 12 peripheral DMAs, 2 mastered by the Ethernet MAC Programmable on-chip voltage regulator (ADSP-BF523/ 2 memory-to-memory DMAs with external request lines ADSP-BF525/ADSP-BF527 processors only) Event handler with 54 interrupt inputs Qualified for Automotive Applications. See Automotive Serial peripheral interface (SPI) compatible port Products on Page87 2 UARTs with IrDA support 289-ball and 208-ball CSP_BGA packages 2-wire interface (TWI) controller MEMORY Eight 32-bit timers/counters with PWM support 32-bit up/down counter with rotary support 132K bytes of on-chip memory (See Table1 on Page3 for L1 Real-time clock (RTC) and watchdog timer and L3 memory size details) 32-bit core timer External memory controller with glueless support for SDRAM and asynchronous 8-bit and 16-bit memories 48 general-purpose I/Os (GPIOs), with programmable hysteresis Flexible booting options from external flash, SPI, and TWI memory or from host devices including SPI, TWI, and UART NAND flash controller (NFC) Code security with Lockbox Secure Technology Debug/JTAG interface one-time-programmable (OTP) memory On-chip PLL capable of frequency multiplication Memory management unit providing memory protection WATCHDOG TIMER OTP MEMORY RTC VOLTAGE REGULATOR* JTAG TEST AND EMULATION PERIPHERAL COUNTER ACCESS BUS SPORT0 B SPORT1 INTERRUPT CONTROLLER UART1 GPIO PORT F UART0 L1 INSTRUCTION L1 DATA NFC MEMORY MEMORY DMA GPIO CONTROLLER DMA PPI PORT G EAB 16 ACCESS DCB BUS SPI USB TIMER7-1 GPIO DEB PORT H TIMER0 EXTERNAL PORT BOOT FLASH, SDRAM CONTROL ROM EMAC HOST DMA TWI PORT J *REGULATOR ONLY AVAILABLE ON ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS Figure 1. Processor Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 TABLE OF CONTENTS Features ................................................................. 1 Clock Signals ...................................................... 16 Memory ................................................................ 1 Booting Modes ................................................... 18 Peripherals ............................................................. 1 Instruction Set Description .................................... 20 General Description ................................................. 3 Development Tools .............................................. 20 Portable Low Power Architecture ............................. 3 Additional Information ........................................ 21 System Integration ................................................ 3 Related Signal Chains ........................................... 22 Processor Peripherals ............................................. 3 Lockbox Secure Technology Disclaimer .................... 22 Blackfin Processor Core .......................................... 4 Signal Descriptions ................................................. 23 Memory Architecture ............................................ 5 Specifications ........................................................ 28 DMA Controllers .................................................. 9 Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Host DMA Port .................................................... 9 Processors ...................................................... 28 Real-Time Clock ................................................... 9 Operating Conditions for ADSP-BF523/ADSP-BF525/ Watchdog Timer ................................................ 10 ADSP-BF527 Processors .................................... 30 Timers ............................................................. 10 Electrical Characteristics ....................................... 32 Up/Down Counter and Thumbwheel Interface .......... 10 Absolute Maximum Ratings ................................... 37 Serial Ports ........................................................ 10 Package Information ............................................ 38 Serial Peripheral Interface (SPI) Port ....................... 11 ESD Sensitivity ................................................... 38 UART Ports ...................................................... 11 Timing Specifications ........................................... 39 TWI Controller Interface ...................................... 12 Output Drive Currents ......................................... 73 10/100 Ethernet MAC .......................................... 12 Test Conditions .................................................. 75 Ports ................................................................ 12 Environmental Conditions .................................... 79 Parallel Peripheral Interface (PPI) ........................... 13 289-Ball CSP_BGA Ball Assignment ........................... 80 USB On-The-Go Dual-Role Device Controller ........... 14 208-Ball CSP_BGA Ball Assignment ........................... 83 Code Security with Lockbox Secure Technology ......... 14 Outline Dimensions ................................................ 86 Dynamic Power Management ................................ 14 Surface-Mount Design .......................................... 87 ADSP-BF523/ADSP-BF525/ADSP-BF527 Automotive Products .............................................. 87 Voltage Regulation ........................................... 16 Ordering Guide ..................................................... 88 ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation ........................................... 16 REVISION HISTORY 7/13—Rev. C to Rev. D Updated Development Tools .................................... 20 Corrected footnote 9 and added footnote 11 in Operating Conditions for ADSP-BF523/ADSP-BF525/ ADSP-BF527 Processors .......................................... 30 Rev. D | Page 2 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 GENERAL DESCRIPTION The ADSP-BF52x processors are members of the Blackfin fam- By integrating a rich set of industry-leading system peripherals ily of products, incorporating the Analog Devices/Intel Micro and memory, Blackfin processors are the platform of choice for Signal Architecture (MSA). Blackfin® processors combine a next-generation applications that require RISC-like program- dual-MAC state-of-the-art signal processing engine, the advan- mability, multimedia support, and leading-edge signal tages of a clean, orthogonal RISC-like microprocessor processing in one integrated package. instruction set, and single-instruction, multiple-data (SIMD) PORTABLE LOW POWER ARCHITECTURE multimedia capabilities into a single instruction-set architecture. Blackfin processors provide world-class power management The ADSP-BF52x processors are completely code compatible and performance. They are produced with a low power and low with other Blackfin processors. The ADSP-BF523/ voltage design methodology and feature on-chip dynamic ADSP-BF525/ADSP-BF527 processors offer performance up to power management, which is the ability to vary both the voltage 600 MHz. The ADSP-BF522/ADSP-BF524/ADSP-BF526 pro- and frequency of operation to significantly lower overall power cessors offer performance up to 400 MHz and reduced static consumption. This capability can result in a substantial reduc- power consumption. Differences with respect to peripheral tion in power consumption, compared with just varying the combinations are shown in Table1. frequency of operation. This allows longer battery life for portable appliances. Table 1. Processor Comparison SYSTEM INTEGRATION 2 4 6 3 5 7 2 2 2 2 2 2 The ADSP-BF52x processors are highly integrated system-on-a- 5 5 5 5 5 5 F F F F F F chip solutions for the next generation of embedded network B B B B B B P- P- P- P- P- P- connected applications. By combining industry-standard inter- S S S S S S D D D D D D faces with a high performance signal processing core, cost- Feature A A A A A A effective applications can be developed quickly, without the Host DMA 1 1 1 1 1 1 need for costly external components. The system peripherals USB – 1 1 – 1 1 include an IEEE-compliant 802.3 10/100 Ethernet MAC, a USB Ethernet MAC – – 1 – – 1 2.0 high speed OTG controller, a TWI controller, a NAND flash Internal Voltage Regulator – – – 1 1 1 controller, two UART ports, an SPI port, two serial ports TWI 1 1 1 1 1 1 (SPORTs), eight general purpose 32-bit timers with PWM capa- bility, a core timer, a real-time clock, a watchdog timer, a Host SPORTs 2 2 2 2 2 2 DMA (HOSTDP) interface, and a parallel peripheral interface UARTs 2 2 2 2 2 2 (PPI). SPI 1 1 1 1 1 1 PROCESSOR PERIPHERALS GP Timers 8 8 8 8 8 8 GP Counter 1 1 1 1 1 1 The ADSP-BF52x processors contain a rich set of peripherals Watchdog Timers 1 1 1 1 1 1 connected to the core via several high bandwidth buses, provid- RTC 1 1 1 1 1 1 ing flexibility in system configuration as well as excellent overall system performance (see the block diagram onPage1). Parallel Peripheral Interface 1 1 1 1 1 1 GPIOs 48 48 48 48 48 48 These Blackfin processors contain dedicated network commu- L1 Instruction SRAM 48K 48K 48K 48K 48K 48K nication modules and high speed serial and parallel ports, an s) interrupt controller for flexible management of interrupts from e L1 Instruction SRAM/Cache 16K 16K 16K 16K 16K 16K yt the on-chip peripherals or external sources, and power manage- b L1 Data SRAM 32K 32K 32K 32K 32K 32K y ( ment control functions to tailor the performance and power or L1 Data SRAM/Cache 32K 32K 32K 32K 32K 32K characteristics of the processor and system to many application m e L1 Scratchpad 4K 4K 4K 4K 4K 4K scenarios. M L3 Boot ROM 32K 32K 32K 32K 32K 32K All of the peripherals, except for the general-purpose I/O, TWI, Maximum Instruction Rate1 400 MHz 600 MHz real-time clock, and timers, are supported by a flexible DMA Maximum System Clock Speed 100 MHz 133 MHz structure. There are also separate memory DMA channels dedi- Package Options 289-Ball CSP_BGA cated to data transfers between the processor's various memory spaces, including external SDRAM and asynchronous memory. 208-Ball CSP_BGA Multiple on-chip buses running at up to 133MHz provide 1Maximum instruction rate is not available with every possible SCLK selection. enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. The ADSP-BF523/ADSP-BF525/ADSP-BF527 processors include an on-chip voltage regulator in support of the proces- sor’s dynamic power management capability. The voltage Rev. D | Page 3 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 regulator provides a range of core voltage levels when supplied The compute register file contains eight 32-bit registers. When from V . The voltage regulator can be bypassed at the user's performing compute operations on 16-bit operand data, the DDEXT discretion. register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported BLACKFIN PROCESSOR CORE register file and instruction constant fields. As shown in Figure2, the Blackfin processor core contains two Each MAC can perform a 16-bit by 16-bit multiply in each 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, cycle, accumulating the results into the 40-bit accumulators. four video ALUs, and a 40-bit shifter. The computation units Signed and unsigned formats, rounding, and saturation process 8-, 16-, or 32-bit data from the register file. are supported. ADDRESS ARITHMETIC UNIT SP I3 L3 B3 M3 FP I2 L2 B2 M2 P5 I1 L1 B1 M1 DAG1 P4 I0 L0 B0 M0 P3 DAG0 P2 DA1 32 P1 DA0 32 P0 Y OR 32 32 M RAB PREG E M O T SD 32 LD1 32 32 ASTAT LD0 32 32 SEQUENCER R7.H R7.L R6.H R6.L R5.H R5.L ALIGN R4.H R4.L 16 16 8 8 8 8 R3.H R3.L R2.H R2.L DECODE R1.H R1.L BARREL R0.H R0.L SHIFTER 40 40 LOOP BUFFER 40 40 A0 A1 CONTROL UNIT 32 32 DATA ARITHMETIC UNIT Figure 2. Blackfin Processor Core The ALUs perform a traditional set of arithmetic and logical The 40-bit shifter can perform shifts and rotates and is used to operations on 16-bit or 32-bit data. In addition, many special support normalization, field extract, and field deposit instructions are included to accelerate various signal processing instructions. tasks. These include bit operations such as field extract and pop- The program sequencer controls the flow of instruction execu- ulation count, modulo 232 multiply, divide primitives, saturation tion, including instruction alignment and decoding. For and rounding, and sign/exponent detection. The set of video program flow control, the sequencer supports PC relative and instructions include byte alignment and packing operations, indirect conditional jumps (with static branch prediction), and 16-bit and 8-bit adds with clipping, 8-bit average operations, subroutine calls. Hardware is provided to support zero-over- and 8-bit subtract/absolute value/accumulate (SAA) operations. head looping. The architecture is fully interlocked, meaning that Also provided are the compare/select and vector search the programmer need not manage the pipeline when executing instructions. instructions with data dependencies. For certain instructions, two 16-bit ALU operations can be per- The address arithmetic unit provides two addresses for simulta- formed simultaneously on register pairs (a 16-bit high half and neous dual fetches from memory. It contains a multiported 16-bit low half of a compute register). If the second ALU is used, register file consisting of four sets of 32-bit index, modify, quad 16-bit operations are possible. Rev. D | Page 4 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 length, and base registers (for circular buffering), and eight 0xFFFFFFFF additional 32-bit pointer registers (for C-style indexed stack COREMMRREGISTERS(2MBYTES) manipulation). 0xFFE00000 SYSTEMMMRREGISTERS(2MBYTES) 0xFFC00000 Blackfin processors support a modified Harvard architecture in RESERVED combination with a hierarchical memory structure. Level 1 (L1) 0xFFB01000 SCRATCHPADSRAM(4KBYTES) memories are those that typically operate at the full processor 0xFFB00000 speed with little or no latency. At the L1 level, the instruction RESERVED 0xFFA14000 memory holds instructions only. The two data memories hold INSTRUCTIONSRAM/CACHE(16KBYTES) data, and a dedicated scratchpad data memory stores stack and 0xFFA10000 RESERVED P local variable information. 0xFFA0C000 AM INSTRUCTIONBANKBSRAM(16KBYTES) Y In addition, multiple L1 memory blocks are provided, offering a 0xFFA08000 OR INSTRUCTIONBANKASRAM(32KBYTES) M configurable mix of SRAM and cache. The memory manage- 0xFFA00000 ME ment unit (MMU) provides memory protection for individual RESERVED L 0xFF908000 A tasks that may be operating on the core and can protect system DATABANKBSRAM/CACHE(16KBYTES) RN 0xFF904000 E registers from unintended access. DATABANKBSRAM(16KBYTES) NT 0xFF900000 I The architecture provides three modes of operation: user mode, RESERVED supervisor mode, and emulation mode. User mode has 0xFF808000 DATABANKASRAM/CACHE(16KBYTES) restricted access to certain system resources, thus providing a 0xFF804000 DATABANKASRAM(16KBYTES) protected software environment, while supervisor mode has 0xFF800000 unrestricted access to the system and core resources. RESERVED 0xEF008000 The Blackfin processor instruction set has been optimized so BOOTROM(32KBYTES) 0xEF000000 that 16-bit opcodes represent the most frequently used instruc- RESERVED AP tions, resulting in excellent compiled code density. Complex 0x20400000 M ASYNCMEMORYBANK3(1MBYTES) Y DSP instructions are encoded into 32-bit opcodes, representing 0x20300000 OR ASYNCMEMORYBANK2(1MBYTES) M fully featured multifunction instructions. Blackfin processors 0x20200000 EM support a limited multi-issue capability, where a 32-bit instruc- ASYNCMEMORYBANK1(1MBYTES) L 0x20100000 A tion can be issued in parallel with two 16-bit instructions, ASYNCMEMORYBANK0(1MBYTES) RN allowing the programmer to use many of the core resources in a 0x20000000 TE RESERVED X E single instruction cycle. 0x08000000 SDRAMMEMORY(16MBYTES 128MBYTES) The Blackfin processor assembly language uses an algebraic syn- 0x00000000 tax for ease of coding and readability. The architecture has been Figure 3. Internal/External Memory Map optimized for use in conjunction with the C/C++compiler, resulting in fast and efficient software implementations. Internal (On-Chip) Memory MEMORY ARCHITECTURE The processor has three blocks of on-chip memory providing high-bandwidth access to the core. The Blackfin processor views memory as a single unified 4Gbyte address space, using 32-bit addresses. All resources, The first block is the L1 instruction memory, consisting of including internal memory, external memory, and I/O control 64Kbytes SRAM, of which 16Kbytes can be configured as a registers, occupy separate sections of this common address four-way set-associative cache. This memory is accessed at full space. The memory portions of this address space are arranged processor speed. in a hierarchical structure to provide a good cost/performance The second on-chip memory block is the L1 data memory, con- balance of some very fast, low-latency on-chip memory as cache sisting of up to two banks of up to 32Kbytes each. Each memory or SRAM, and larger, lower-cost and performance off-chip bank is configurable, offering both cache and SRAM functional- memory systems. See Figure3. ity. This memory block is accessed at full processor speed. The on-chip L1 memory system is the highest-performance The third memory block is a 4Kbyte scratchpad SRAM which memory available to the Blackfin processor. The off-chip runs at the same speed as the L1 memories, but is only accessible memory system, accessed through the external bus interface as data SRAM and cannot be configured as cache memory. unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132Mbytes of External (Off-Chip) Memory physicalmemory. External memory is accessed via the EBIU. This 16-bit interface The memory DMA controller provides high-bandwidth data- provides a glueless connection to a bank of synchronous DRAM movement capability. It can perform block transfers of code (SDRAM), as well as up to four banks of asynchronous memory ordata between the internal memory and the external devices including flash, EPROM, ROM, SRAM, and memory memory spaces. mapped I/O devices. Rev. D | Page 5 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 The SDRAM controller can be programmed to interface to up ID, MAC address, etc. Hence, generic parts can be shipped, to 128Mbytes of SDRAM. A separate row can be open for each which are then programmed and protected by the developer SDRAM internal bank and the SDRAM controller supports up within this non-volatile memory. to 4 internal SDRAM banks, improving overall performance. I/O Memory Space The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing The processor does not define a separate I/O space. All requirements for a wide variety of devices. Each bank occupies a resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into 1Mbyte segment regardless of the size of the devices used, so that these banks are only contiguous if each is fully populated memory-mapped registers (MMRs) at addresses near the top of the 4Gbyte address space. These are separated into two smaller with 1Mbyte of memory. blocks, one which contains the control MMRs for all core func- NAND Flash Controller (NFC) tions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The ADSP-BF52x processors provide a NAND flash controller The MMRs are accessible only in supervisor mode and appear (NFC). NAND flash devices provide high-density, low-cost as reserved space to on-chip peripherals. memory. However, NAND flash devices also have long random access times, invalid blocks, and lower reliability over device Booting lifetimes. Because of this, NAND flash is often used for read- only code storage. In this case, all DSP code can be stored in The processor contains a small on-chip boot kernel, which con- NAND flash and then transferred to a faster memory (such as figures the appropriate peripheral for booting. If the processor is SDRAM or SRAM) before execution. Another common use of configured to boot from boot ROM memory space, the proces- NAND flash is for storage of multimedia files or other large data sor starts executing from the on-chip boot ROM. For more segments. In this case, a software file system may be used to information, see Booting Modes on Page18. manage reading and writing of the NAND flash device. The file Event Handling system selects memory segments for storage with the goal of avoiding bad blocks and equally distributing memory accesses The event controller on the processor handles all asynchronous across all address locations. Hardware features of the NFC and synchronous events to the processor. The processor pro- include: vides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to • Support for page program, page read, and block erase of be active simultaneously. Prioritization ensures that servicing of NAND flash devices, with accesses aligned to page a higher-priority event takes precedence over servicing of a boundaries. lower-priority event. The controller provides support for five • Error checking and correction (ECC) hardware that facili- different types of events: tates error detection and correction. • Emulation — An emulation event causes the processor to • A single 8-bit external bus interface for commands, enter emulation mode, allowing command and control of addresses, and data. the processor via the JTAG interface. • Support for SLC (single level cell) NAND flash devices • RESET — This event resets the processor. unlimited in size, with page sizes of 256 and 512 bytes. • Nonmaskable Interrupt (NMI) — The NMI event can be Larger page sizes can be supported in software. generated by the software watchdog timer or by the NMI • Capability of releasing external bus interface pins during input signal to the processor. The NMI event is frequently long accesses. used as a power-down indicator to initiate an orderly shut- • Support for internal bus requests of 16 bits. down of the system. • DMA engine to transfer data between internal memory and • Exceptions — Events that occur synchronously to program NAND flash device. flow (in other words, the exception is taken before the instruction is allowed to complete). Conditions such as One-Time Programmable Memory data alignment violations and undefined instructions cause exceptions. The processor has 64K bits of one-time programmable non- volatile memory that can be programmed by the developer only • Interrupts — Events that occur asynchronously to program one time. It includes the array and logic to support read access flow. They are caused by input signals, timers, and other and programming. Additionally, its pages can be write peripherals, as well as by an explicit software instruction. protected. Each event type has an associated register to hold the return OTP enables developers to store both public and private data address and an associated return-from-event instruction. When on-chip. In addition to storing public and private key data for an event is triggered, the state of the processor is saved on the applications requiring security, it also allows developers to store supervisor stack. completely user-definable data such as customer ID, product The processor event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt Rev. D | Page 6 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 controller to prioritize and control all system events. Conceptu- Table 2. Core Event Controller (CEC) ally, interrupts from the peripherals enter into the SIC and are then routed directly into the general-purpose interrupts of the Priority CEC. (0 is Highest) Event Class EVT Entry 0 Emulation/Test Control EMU Core Event Controller (CEC) 1 RESET RST The CEC supports nine general-purpose interrupts (IVG15–7), 2 Nonmaskable Interrupt NMI in addition to the dedicated interrupt and exception events. Of 3 Exception EVX these general-purpose interrupts, the two lowest-priority interrupts (IVG15–14) are recommended to be reserved for 4 Reserved — software interrupt handlers, leaving seven prioritized interrupt 5 Hardware Error IVHW inputs to support the peripherals of the processor. Table2 6 Core Timer IVTMR describes the inputs to the CEC, identifies their names in the 7 General-Purpose Interrupt 7 IVG7 event vector table (EVT), and lists their priorities. 8 General-Purpose Interrupt 8 IVG8 System Interrupt Controller (SIC) 9 General-Purpose Interrupt 9 IVG9 The system interrupt controller provides the mapping and rout- 10 General-Purpose Interrupt 10 IVG10 ing of events from the many peripheral interrupt sources to the 11 General-Purpose Interrupt 11 IVG11 prioritized general-purpose interrupt inputs of the CEC. 12 General-Purpose Interrupt 12 IVG12 Although the processor provides a default mapping, the user 13 General-Purpose Interrupt 13 IVG13 can alter the mappings and priorities of interrupt events by writ- ing the appropriate values into the interrupt assignment 14 General-Purpose Interrupt 14 IVG14 registers (SIC_IARx). Table3 describes the inputs into the SIC 15 General-Purpose Interrupt 15 IVG15 and the default mappings into the CEC. Table 3. System Interrupt Controller (SIC) General Purpose Default Peripheral Interrupt Event Interrupt (at RESET) Peripheral Interrupt ID Core Interrupt ID SIC Registers PLL Wakeup Interrupt IVG7 0 0 IAR0 IMASK0, ISR0, IWR0 DMA Error 0 (generic) IVG7 1 0 IAR0 IMASK0, ISR0, IWR0 DMAR0 Block Interrupt IVG7 2 0 IAR0 IMASK0, ISR0, IWR0 DMAR1 Block Interrupt IVG7 3 0 IAR0 IMASK0, ISR0, IWR0 DMAR0 Overflow Error IVG7 4 0 IAR0 IMASK0, ISR0, IWR0 DMAR1 Overflow Error IVG7 5 0 IAR0 IMASK0, ISR0, IWR0 PPI Error IVG7 6 0 IAR0 IMASK0, ISR0, IWR0 MAC Status IVG7 7 0 IAR0 IMASK0, ISR0, IWR0 SPORT0 Status IVG7 8 0 IAR1 IMASK0, ISR0, IWR0 SPORT1 Status IVG7 9 0 IAR1 IMASK0, ISR0, IWR0 Reserved IVG7 10 0 IAR1 IMASK0, ISR0, IWR0 Reserved IVG7 11 0 IAR1 IMASK0, ISR0, IWR0 UART0 Status IVG7 12 0 IAR1 IMASK0, ISR0, IWR0 UART1 Status IVG7 13 0 IAR1 IMASK0, ISR0, IWR0 RTC IVG8 14 1 IAR1 IMASK0, ISR0, IWR0 DMA Channel 0 (PPI/NFC) IVG8 15 1 IAR1 IMASK0, ISR0, IWR0 DMA Channel 3 (SPORT0 RX) IVG9 16 2 IAR2 IMASK0, ISR0, IWR0 DMA Channel 4 (SPORT0 TX) IVG9 17 2 IAR2 IMASK0, ISR0, IWR0 DMA Channel 5 (SPORT1 RX) IVG9 18 2 IAR2 IMASK0, ISR0, IWR0 DMA Channel 6 (SPORT1 TX) IVG9 19 2 IAR2 IMASK0, ISR0, IWR0 TWI IVG10 20 3 IAR2 IMASK0, ISR0, IWR0 DMA Channel 7 (SPI) IVG10 21 3 IAR2 IMASK0, ISR0, IWR0 DMA Channel 8 (UART0 RX) IVG10 22 3 IAR2 IMASK0, ISR0, IWR0 DMA Channel 9 (UART0 TX) IVG10 23 3 IAR2 IMASK0, ISR0, IWR0 DMA Channel 10 (UART1 RX) IVG10 24 3 IAR3 IMASK0, ISR0, IWR0 DMA Channel 11 (UART1 TX) IVG10 25 3 IAR3 IMASK0, ISR0, IWR0 Rev. D | Page 7 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 3. System Interrupt Controller (SIC) (Continued) General Purpose Default Peripheral Interrupt Event Interrupt (at RESET) Peripheral Interrupt ID Core Interrupt ID SIC Registers OTP Memory Interrupt IVG11 26 4 IAR3 IMASK0, ISR0, IWR0 GP Counter IVG11 27 4 IAR3 IMASK0, ISR0, IWR0 DMA Channel 1 (MAC RX/HOSTDP) IVG11 28 4 IAR3 IMASK0, ISR0, IWR0 Port H Interrupt A IVG11 29 4 IAR3 IMASK0, ISR0, IWR0 DMA Channel 2 (MAC TX/NFC) IVG11 30 4 IAR3 IMASK0, ISR0, IWR0 Port H Interrupt B IVG11 31 4 IAR3 IMASK0, ISR0, IWR0 Timer 0 IVG12 32 5 IAR4 IMASK1, ISR1, IWR1 Timer 1 IVG12 33 5 IAR4 IMASK1, ISR1, IWR1 Timer 2 IVG12 34 5 IAR4 IMASK1, ISR1, IWR1 Timer 3 IVG12 35 5 IAR4 IMASK1, ISR1, IWR1 Timer 4 IVG12 36 5 IAR4 IMASK1, ISR1, IWR1 Timer 5 IVG12 37 5 IAR4 IMASK1, ISR1, IWR1 Timer 6 IVG12 38 5 IAR4 IMASK1, ISR1, IWR1 Timer 7 IVG12 39 5 IAR4 IMASK1, ISR1, IWR1 Port G Interrupt A IVG12 40 5 IAR5 IMASK1, ISR1, IWR1 Port G Interrupt B IVG12 41 5 IAR5 IMASK1, ISR1, IWR1 MDMA Stream 0 IVG13 42 6 IAR5 IMASK1, ISR1, IWR1 MDMA Stream 1 IVG13 43 6 IAR5 IMASK1, ISR1, IWR1 Software Watchdog Timer IVG13 44 6 IAR5 IMASK1, ISR1, IWR1 Port F Interrupt A IVG13 45 6 IAR5 IMASK1, ISR1, IWR1 Port F Interrupt B IVG13 46 6 IAR5 IMASK1, ISR1, IWR1 SPI Status IVG7 47 0 IAR5 IMASK1, ISR1, IWR1 NFC Status IVG7 48 0 IAR6 IMASK1, ISR1, IWR1 HOSTDP Status IVG7 49 0 IAR6 IMASK1, ISR1, IWR1 Host Read Done IVG7 50 0 IAR6 IMASK1, ISR1, IWR1 Reserved IVG10 51 3 IAR6 IMASK1, ISR1, IWR1 USB_INT0 Interrupt IVG10 52 3 IAR6 IMASK1, ISR1, IWR1 USB_INT1 Interrupt IVG10 53 3 IAR6 IMASK1, ISR1, IWR1 USB_INT2 Interrupt IVG10 54 3 IAR6 IMASK1, ISR1, IWR1 USB_DMAINT Interrupt IVG10 55 3 IAR6 IMASK1, ISR1, IWR1 Event Control The processor provides a very flexible mechanism to control the written while in supervisor mode. (Note that general- processing of events. In the CEC, three registers are used to purpose interrupts can be globally enabled and disabled coordinate and control events. Each register is 16 bits wide. with the STI and CLI instructions, respectively.) • CEC interrupt latch register (ILAT) — Indicates when • CEC interrupt pending register (IPEND) — The IPEND events have been latched. The appropriate bit is set when register keeps track of all nested events. A set bit in the the processor has latched the event and cleared when the IPEND register indicates the event is currently active or event has been accepted into the system. This register is nested at some level. This register is updated automatically updated automatically by the controller, but it may be writ- by the controller but may be read while in supervisor mode. ten only when its corresponding IMASK bit is cleared. The SIC allows further control of event processing by providing • CEC interrupt mask register (IMASK) — Controls the three pairs of 32-bit interrupt control and status registers. Each masking and unmasking of individual events. When a bit is register contains a bit corresponding to each of the peripheral set in the IMASK register, that event is unmasked and is interrupt events shown in Table3 on Page7. processed by the CEC when asserted. A cleared bit in the • SIC interrupt mask registers (SIC_IMASKx) — Control the IMASK register masks the event, preventing the processor masking and unmasking of each peripheral interrupt event. from servicing the event even though the event may be When a bit is set in these registers, that peripheral event is latched in the ILAT register. This register may be read or Rev. D | Page 8 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 unmasked and is processed by the system when asserted. A Examples of DMA types supported by the processor DMA con- cleared bit in the register masks the peripheral event, pre- troller include: venting the processor from servicing the event. • A single, linear buffer that stops upon completion. • SIC interrupt status registers (SIC_ISRx) — As multiple • A circular, auto-refreshing buffer that interrupts on each peripherals can be mapped to a single event, these registers full or fractionally full buffer. allow the software to determine which peripheral event source triggered the interrupt. A set bit indicates the • 1-D or 2-D DMA using a linked list of descriptors. peripheral is asserting the interrupt, and a cleared bit indi- • 2-D DMA using an array of descriptors, specifying only the cates the peripheral is not asserting the event. base DMA address within a common page. • SIC interrupt wakeup enable registers (SIC_IWRx) — By In addition to the dedicated peripheral DMA channels, there are enabling the corresponding bit in these registers, a periph- two memory DMA channels provided for transfers between the eral can be configured to wake up the processor, should the various memories of the processor system. This enables trans- core be idled or in sleep mode when the event is generated. fers of blocks of data between any of the memories—including For more information see Dynamic Power Management on external SDRAM, ROM, SRAM, and flash memory—with mini- Page14. mal processor intervention. Memory DMA transfers can be Because multiple interrupt sources can map to a single general- controlled by a very flexible descriptor-based methodology or purpose interrupt, multiple pulse assertions can occur simulta- by a standard register-based autobuffer mechanism. neously, before or during interrupt processing for an interrupt The processor also has an external DMA controller capability event already detected on this interrupt input. The IPEND via dual external DMA request pins when used in conjunction register contents are monitored by the SIC as the interrupt with the external bus interface unit (EBIU). This functionality acknowledgement. can be used when a high speed interface is required for external The appropriate ILAT register bit is set when an interrupt rising FIFOs and high bandwidth communications peripherals such as USB 2.0. It allows control of the number of data transfers for edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The memory DMA. The number of transfers per edge is program- IPEND bit indicates that the event has entered into the proces- mable. This feature can be programmed to allow memory sor pipeline. At this point the CEC recognizes and queues the DMAto have an increased priority on the external bus relative next rising edge event on the corresponding event input. The tothecore. minimum latency from the rising edge transition of the general- HOST DMA PORT purpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depend- The host port interface allows an external host to be a DMA ing on the activity within and the state of the processor. master to transfer data in and out of the device. The host device masters the transactions and the Blackfin processor is the DMA CONTROLLERS DMAslave. The processor has multiple, independent DMA channels that The host port is enabled through the PAB interface. Once support automated data transfers with minimal overhead for enabled, the DMA is controlled by the external host, which can the processor core. DMA transfers can occur between the then program the DMA to send/receive data to any valid inter- processor's internal memories and any of its DMA-capable nal or external memory location. peripherals. Additionally, DMA transfers can be accomplished The host port interface controller has the following features. between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including • Allows external master to configure DMA read/write data the SDRAM controller and the asynchronous memory control- transfers and read port status. ler. DMA-capable peripherals include the Ethernet MAC, NFC, • Uses asynchronous memory protocol for external interface. HOSTDP, USB, SPORTs, SPI port, UARTs, and PPI. Each indi- • 8-/16-bit external data interface to host device. vidual DMA-capable peripheral has at least one dedicated DMA channel. • Half duplex operation. The processor DMA controller supports both one-dimensional • Little-/big-endian data transfer. (1-D) and two-dimensional (2-D) DMA transfers. DMA trans- • Acknowledge mode allows flow control on host fer initialization can be implemented from registers or from sets transactions. of parameters called descriptor blocks. • Interrupt mode guarantees a burst of FIFO depth host The 2-D DMA capability supports arbitrary row and column transactions. sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the REAL-TIME CLOCK column step size can be less than the row step size, allowing The real-time clock (RTC) provides a robust set of digital watch implementation of interleaved data streams. This feature is features, including current time, stopwatch, and alarm. The especially useful in video applications where data can be de- RTC is clocked by a 32.768kHz crystal external to the Blackfin interleaved on the fly. processor. Connect RTC pins RTXI and RTXO with external Rev. D | Page 9 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 components as shown in Figure4. unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. RTXI RTXO R1 If configured to generate a hardware reset, the watchdog timer resets both the core and the processor peripherals. After a reset, software can determine if the watchdog was the source of the X1 hardware reset by interrogating a status bit in the watchdog timer control register. C1 C2 The timer is clocked by the system clock (SCLK), at a maximum frequency of f . SCLK TIMERS SUGGESTEDCOMPONENTS: X1=ECLIPTEKEC38J(THROUGH-HOLEPACKAGE)OR There are nine general-purpose programmable timer units in EPSONMC40512pFLOAD(SURFACE-MOUNTPACKAGE) C1=22pF the processors. Eight timers have an external pin that can be C2=22pF configured either as a pulse width modulator (PWM) or timer R1=10M(cid:58) NOTE:C1ANDC2ARESPECIFICTOCRYSTALSPECIFIEDFORX1. output, as an input to clock the timer, or as a mechanism for CONTACTCRYSTALMANUFACTURERFORDETAILS.C1ANDC2 measuring pulse widths and periods of external events. These SPECIFICATIONSASSUMEBOARDTRACECAPACITANCEOF3pF. timers can be synchronized to an external clock input to the sev- Figure 4. External Components for RTC eral other associated PF pins, an external clock input to the PPI_CLK input pin, or to the internal SCLK. The RTC peripheral has dedicated power supply pins so that it The timer units can be used in conjunction with the two UARTs can remain powered up and clocked even when the rest of the to measure the width of the pulses in the data stream to provide processor is in a low power state. The RTC provides several pro- a software auto-baud detect function for the respective serial grammable interrupt options, including interrupt per second, channels. minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm The timers can generate interrupts to the processor core provid- time. ing periodic events for synchronization, either to the system clock or to a count of external signals. The 32.768kHz input clock frequency is divided down to a 1Hz signal by a prescaler. The counter function of the timer consists In addition to the eight general-purpose programmable timers, of four counters: a 60-second counter, a 60-minute counter, a a ninth timer is also provided. This extra timer is clocked by the 24-hour counter, and an 32,768-day counter. internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts. When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the UP/DOWN COUNTER AND THUMBWHEEL alarm control register. There are two alarms: The first alarm is INTERFACE for a time of day. The second alarm is for a day and time of that day. A 32-bit up/down counter is provided that can sense 2-bit quadrature or binary codes as typically emitted by industrial The stopwatch function counts down from a programmed drives or manual thumb wheels. The counter can also operate in value, with one-second resolution. When the stopwatch is general-purpose up/down count modes. Then, count direction enabled and the counter underflows, an interrupt is generated. is either controlled by a level-sensitive input pin or by two edge Like the other peripherals, the RTC can wake up the processor detectors. from sleep mode upon generation of any RTC wake-up event. A third input can provide flexible zero marker support and can Additionally, an RTC wakeup event can wake up the processor alternatively be used to input the push-button signal of thumb from deep sleep mode or cause a transition from the hibernate wheels. All three pins have a programmable debouncing circuit. state. An internal signal forwarded to the timer unit enables one timer WATCHDOG TIMER to measure the intervals between count events. Boundary regis- ters enable auto-zero operation or simple system warning by The processor includes a 32-bit timer that can be used to imple- interrupts when programmable count values are exceeded. ment a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known SERIAL PORTS state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer The processors incorporate two dual-channel synchronous expires before being reset by software. The programmer initial- serial ports (SPORT0 and SPORT1) for serial and multiproces- izes the count value of the timer, enables the appropriate sor communications. The SPORTs support the following interrupt, then enables the timer. Thereafter, the software must features: reload the counter before it counts to zero from the pro- • I2S capable operation. grammed value. This protects the system from remaining in an Rev. D | Page 10 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 • Bidirectional operation — Each SPORT has two sets of The SPI port’s clock rate is calculated as: independent transmit and receive pins, enabling eight channels of I2S stereo audio. SPI Clock Rate = ------------f--S--C---L---K-------------- 2SPI_BAUD • Buffered (8-deep) transmit and receive ports — Each port has a data register for transferring data words to and from Where the 16-bit SPI_BAUD register contains a value of 2 other processor components and shift registers for shifting to 65,535. data in and out of the data registers. During transfers, the SPI port simultaneously transmits and • Clocking — Each transmit and receive port can either use receives by serially shifting data in and out on its two serial data an external serial clock or generate its own, in frequencies lines. The serial clock line synchronizes the shifting and sam- ranging from (f /131,070)Hz to (f /2)Hz. SCLK SCLK pling of data on the two serial data lines. • Word length – Each SPORT supports serial data words UART PORTS from 3 to 32bits in length, transferred most-significant-bit first or least-significant-bit first. The processors provide two full-duplex universal asynchronous • Framing — Each transmit and receive port can run with or receiver/transmitter (UART) ports, which are fully compatible without frame sync signals for each data word. Frame sync with PC-standard UARTs. Each UART port provides a simpli- signals can be generated internally or externally, active high fied UART interface to other peripherals or hosts, supporting or low, and with either of two pulse widths and early or late full-duplex, DMA-supported, asynchronous transfers of serial frame sync. data. A UART port includes support for five to eightdata bits, one or two stop bits, and none, even, or odd parity. Each UART • Companding in hardware — Each SPORT can perform port supports two modes of operation: A-law or μ-law companding according to ITU recommen- dation G.711. Companding can be selected on the transmit • PIO (programmed I/O) — The processor sends or receives and/or receive channel of the SPORT without data by writing or reading I/O mapped UART registers. additional latencies. The data is double-buffered on both transmit and receive. • DMA operations with single-cycle overhead — Each • DMA (direct memory access) — The DMA controller SPORT can automatically receive and transmit multiple transfers both transmit and receive data. This reduces the buffers of memory data. The processor can link or chain number and frequency of interrupts required to transfer sequences of DMA transfers between a SPORT and data to and from memory. The UART has two dedicated memory. DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA • Interrupts — Each transmit and receive port generates an channels because of their relatively low service rates. interrupt upon completing the transfer of a data word or after transferring an entire data buffer, or buffers, Each UART port's baud rate, serial data format, error code gen- through DMA. eration and status, and interrupts are programmable: • Multichannel capability — Each SPORT supports 128 • Supporting bit rates ranging from (fSCLK/1,048,576) to channels out of a 1024-channel window and is compatible (fSCLK/16) bits per second. with the H.100, H.110, MVIP-90, and HMVIP standards. • Supporting data formats from seven to 12bits per frame. SERIAL PERIPHERAL INTERFACE (SPI) PORT • Both transmit and receive operations can be configured to generate maskable interrupts to the processor. The processors have an SPI-compatible port that enables the processor to communicate with multiple SPI-compatible The UART port’s clock rate is calculated as: devices. f The SPI interface uses three pins for transferring data: two data UART Clock Rate = --------------------S--C---L---K------------------- 16UART_Divisor pins (Master Output-Slave Input, MOSI, and Master Input- Slave Output, MISO) and a clock pin (serial clock, SCK). An SPI Where the 16-bit UART_Divisor comes from the UART_DLH chip select input pin (SPISS) lets other SPI devices select the (most significant 8 bits) and UART_DLL (least significant processor, and seven SPI chip select output pins (SPISEL7–1) let 8bits)registers. the processor select other SPI devices. The SPI select pins are In conjunction with the general-purpose timer functions, auto- reconfigured general-purpose I/O pins. Using these pins, the baud detection is supported. SPI port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster The capabilities of the UARTs are further extended with sup- environments. port for the infrared data association (IrDA®) serial infrared physical layer link specification (SIR) protocol. The SPI port’s baud rate and clock phase/polarities are pro- grammable, and it has an integrated DMA channel, configurable to support transmit or receive data streams. The SPI’s DMA channel can only service unidirectional accesses at any given time. Rev. D | Page 11 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 TWI CONTROLLER INTERFACE • Convenient frame alignment modes support even 32-bit alignment of encapsulated Rx or Tx IP packet data in mem- The processors include a 2-wire interface (TWI) module for ory after the 14-byte MAC header. providing a simple exchange method of control data between multiple devices. The TWI is compatible with the widely used • Programmable Ethernet event interrupt supports any com- I2C® bus standard. The TWI module offers the capabilities of bination of: simultaneous master and slave operation and support for both • Any selected Rx or Tx frame status conditions. 7-bit addressing and multimedia data arbitration. The TWI • PHY interrupt condition. interface utilizes two pins for transferring clock (SCL) and data (SDA) and supports the protocol at speeds up to 400k bits/sec. • Wake-up frame detected. The TWI interface pins are compatible with 5V logic levels. • Any selected MAC management counter(s) at half- Additionally, the TWI module is fully compatible with serial full. camera control bus (SCCB) functionality for easier control of • DMA descriptor error. various CMOS camera sensor devices. • 47 MAC management statistics counters with selectable 10/100 ETHERNET MAC clear-on-read behavior and programmable interrupts on half maximum value. The ADSP-BF526 and ADSP-BF527 processors offer the capa- bility to directly connect to a network by way of an embedded • Programmable Rx address filters, including a 64-bin Fast Ethernet Media Access Controller (MAC) that supports address hash table for multicast and/or unicast frames, and both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec) programmable filter modes for broadcast, multicast, uni- operation. The 10/100 Ethernet MAC peripheral on the proces- cast, control, and damaged frames. sor is fully compliant to the IEEE 802.3-2002 standard and it • Advanced power management supporting unattended provides programmable features designed to minimize supervi- transfer of Rx and Tx frames and status to/from external sion, bus use, or message processing by the rest of the processor memory via DMA during low power sleep mode. system. • System wakeup from sleep operating mode upon magic Some standard features are: packet or any of four user-definable wakeup frame filters. • Support of MII and RMII protocols for external PHYs. • Support for 802.3Q tagged VLAN frames. • Full duplex and half duplex modes. • Programmable MDC clock rate and preamble suppression. • Data framing and encapsulation: generation and detection • In RMII operation, seven unused pins may be configured of preamble, length padding, and FCS. as GPIO pins for other purposes. • Media access management (in half-duplex operation): col- PORTS lision and contention handling, including control of retransmission of collision frames and of back-off timing. Because of the rich set of peripherals, the processor groups the many peripheral signals to four ports—Port F, Port G, Port H, • Flow control (in full-duplex operation): generation and and Port J. Most of the associated pins are shared by multiple detection of PAUSE frames. signals. The ports function as multiplexer controls. • Station management: generation of MDC/MDIO frames for read-write access to PHY registers. General-Purpose I/O (GPIO) • Operating range for active and sleep operating modes, see The processor has 48 bidirectional, general-purpose I/O (GPIO) Table58 on Page68 and Table59 on Page68. pins allocated across three separate GPIO modules—PORTFIO, PORTGIO, and PORTHIO, associated with Port F, Port G, and • Internal loopback from Tx to Rx. Port H, respectively. Port J does not provide GPIO functional- Some advanced features are: ity. Each GPIO-capable pin shares functionality with other • Buffered crystal output to external PHY for support of a processor peripherals via a multiplexing scheme; however, the single crystal system. GPIO functionality is the default state of the device upon power-up. Neither GPIO output nor input drivers are active by • Automatic checksum computation of IP header and IP default. payload fields of Rx frames. • Independent 32-bit descriptor-driven Rx and Tx DMA channels. • Frame status delivery to memory via DMA, including frame completion semaphores, for efficient buffer queue management in software. • Tx DMA support for separate descriptors for MAC header and payload to eliminate buffer copy operations. Rev. D | Page 12 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Each general-purpose port pin can be individually controlled by 2.Frame capture mode — Frame syncs are outputs from the manipulation of the port control, status, and interrupt registers: PPI, but data are inputs. • GPIO direction control register — Specifies the direction of 3.Output mode — Frame syncs and data are outputs from each individual GPIO pin as input or output. the PPI. • GPIO control and status registers — The processor Input Mode employs a “write one to modify” mechanism that allows Input mode is intended for ADC applications, as well as video any combination of individual GPIO pins to be modified in communication with hardware signaling. In its simplest form, a single instruction, without affecting the level of any other PPI_FS1 is an external frame sync input that controls when to GPIO pins. Four control registers are provided. One regis- read data. The PPI_DELAY MMR allows for a delay (in PPI_- ter is written in order to set pin values, one register is CLK cycles) between reception of this frame sync and the written in order to clear pin values, one register is written initiation of data reads. The number of input data samples is in order to toggle pin values, and one register is written in user programmable and defined by the contents of the order to specify a pin value. Reading the GPIO status regis- PPI_COUNT register. The PPI supports 8-bit and 10-bit ter allows software to interrogate the sense of the pins. through 16-bit data, programmable in the PPI_CONTROL • GPIO interrupt mask registers — The two GPIO interrupt register. mask registers allow each individual GPIO pin to function as an interrupt to the processor. Similar to the two GPIO Frame Capture Mode control registers that are used to set and clear individual Frame capture mode allows the video source(s) to act as a slave pin values, one GPIO interrupt mask register sets bits to (for frame capture for example). The ADSP-BF52x processors enable interrupt function, and the other GPIO interrupt control when to read from the video source(s). PPI_FS1 is an mask register clears bits to disable interrupt function. HSYNC output, and PPI_FS2 is a VSYNC output. GPIO pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by Output Mode software interrupts. Output mode is used for transmitting video or other data with • GPIO interrupt sensitivity registers — The two GPIO inter- up to three output frame syncs. Typically, a single frame sync is rupt sensitivity registers specify whether individual pins are appropriate for data converter applications, whereas two or level- or edge-sensitive and specify—if edge-sensitive— three frame syncs could be used for sending video with hard- whether just the rising edge or both the rising and falling ware signaling. edges of the signal are significant. One register selects the ITU-R 656 Mode Descriptions type of sensitivity, and one register selects which edges are significant for edge-sensitivity. The ITU-R 656 modes of the PPI are intended to suit a wide variety of video capture, processing, and transmission applica- PARALLEL PERIPHERAL INTERFACE (PPI) tions. Three distinct submodes are supported: The processor provides a parallel peripheral interface (PPI) that 1.Active video only mode can connect directly to parallel analog-to-digital and digital-to- 2.Vertical blanking only mode analog converters, video encoders and decoders, and other gen- eral-purpose peripherals. The PPI consists of a dedicated input 3.Entire field mode clock pin, up to three frame synchronization pins, and up to 16 Active Video Mode data pins. The input clock supports parallel data rates up to half the system clock rate, and the synchronization signals can be Active video only mode is used when only the active video por- configured as either inputs or outputs. tion of a field is of interest and not any of the blanking intervals. The PPI does not read in any data between the end of active The PPI supports a variety of general-purpose and ITU-R 656 video (EAV) and start of active video (SAV) preamble symbols, modes of operation. In general-purpose mode, the PPI provides or any data present during the vertical blanking intervals. In this half-duplex, bidirectional data transfer with up to 16 bits of mode, the control byte sequences are not stored to memory; data. Up to three frame synchronization signals are also pro- they are filtered by the PPI. After synchronizing to the start of vided. In ITU-R 656 mode, the PPI provides half-duplex Field 1, the PPI ignores incoming samples until it sees an SAV bidirectional transfer of 8- or 10-bit video data. Additionally, code. The user specifies the number of active video lines per on-chip decode of embedded start-of-line (SOL) and start-of- frame (in PPI_COUNT register). field (SOF) preamble packets is supported. Vertical Blanking Interval Mode General-Purpose Mode Descriptions In this mode, the PPI only transfers vertical blanking interval The general-purpose modes of the PPI are intended to suit a (VBI) data. wide variety of data capture and transmission applications. Three distinct submodes are supported: 1.Input mode — Frame syncs and data are inputs into the PPI. Rev. D | Page 13 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Entire Field Mode DYNAMIC POWER MANAGEMENT In this mode, the entire incoming bit stream is read in through The processor provides five operating modes, each with a differ- the PPI. This includes active video, control preamble sequences, ent performance/power profile. In addition, dynamic power and ancillary data that may be embedded in horizontal and ver- management provides the control functions to dynamically alter tical blanking intervals. Data transfer starts immediately after the processor core supply voltage, further reducing power dissi- synchronization to Field 1. Data is transferred to or from the pation. When configured for a 0V core supply voltage, the synchronous channels through eight DMA engines that work processor enters the hibernate state. Control of clocking to each autonomously from the processor core. of the processor peripherals also reduces power consumption. See Table4 for a summary of the power settings for each mode. USB ON-THE-GO DUAL-ROLE DEVICE CONTROLLER The USB OTG dual-role device controller (USBDRC) provides Table 4. Power Settings a low-cost connectivity solution for consumer mobile devices Core System such as cell phones, digital still cameras, and MP3 players, PLL Clock Clock Core allowing these devices to transfer data using a point-to-point Mode/State PLL Bypassed (CCLK) (SCLK) Power USB connection without the need for a PC host. The USBDRC module can operate in a traditional USB peripheral-only mode Full-On Enabled No Enabled Enabled On as well as the host mode presented in the On-the-Go (OTG) Active Enabled/ Yes Enabled Enabled On supplement to the USB 2.0 specification. In host mode, the USB Disabled module supports transfers at high speed (480 Mbps), full speed Sleep Enabled — Disabled Enabled On (12 Mbps), and low speed (1.5 Mbps) rates. Peripheral-only Deep Sleep Disabled — Disabled Disabled On mode supports the high- and full-speed transfer rates. Hibernate Disabled — Disabled Disabled Off The USB clock (USB_XI) is provided through a dedicated exter- nal crystal or crystal oscillator. See Universal Serial Bus (USB) Full-On Operating Mode—Maximum Performance On-The-Go—Receive and Transmit Timing on Page60 for related timing requirements. If using a crystal to provide the In the full-on mode, the PLL is enabled and is not bypassed, USB clock, use a parallel-resonant, fundamental mode, micro- providing capability for maximum operational frequency. This processor-grade crystal. is the power-up default execution state in which maximum per- formance can be achieved. The processor core and all enabled The USB on-the-go dual-role device controller includes a phase peripherals run at full speed. locked loop with programmable multipliers to generate the nec- essary internal clocking frequency for USB. The multiplier value Active Operating Mode—Moderate Dynamic Power should be programmed based on the USB_XI frequency to Savings achieve the necessary 480MHz internal clock for USB high speed operation. For example, for a USB_XI crystal frequency of In the active mode, the PLL is enabled but bypassed. Because the 24MHz, the USB_PLLOSC_CTRL register should be pro- PLL is bypassed, the processor’s core clock (CCLK) and system grammed with a multiplier value of 20 to generate a 480MHz clock (SCLK) run at the input clock (CLKIN) frequency. DMA internal clock. access is available to appropriately configured L1 memories. In the active mode, it is possible to disable the control input to CODE SECURITY WITH LOCKBOX SECURE the PLL by setting the PLL_OFF bit in the PLL control register. TECHNOLOGY This register can be accessed with a user-callable routine in the A security system consisting of a blend of hardware and soft- on-chip ROM called bfrom_SysControl(). If disabled, the PLL ware provides customers with a flexible and rich set of code control input must be re-enabled before transitioning to the security features with LockboxTM Secure Technology. Key fea- full-on or sleep modes. tures include: For more information about PLL controls, see the “Dynamic • OTP memory Power Management” chapter in the ADSP-BF52x Blackfin Pro- cessor Hardware Reference. • Unique chip ID Sleep Operating Mode—High Dynamic Power Savings • Code authentication The sleep mode reduces dynamic power dissipation by disabling • Secure mode of operation the clock to the processor core (CCLK). The PLL and system The security scheme is based upon the concept of authentica- clock (SCLK), however, continue to operate in this mode. Typi- tion of digital signatures using standards-based algorithms and cally, an external event or RTC activity wakes up the processor. provides a secure processing environment in which to execute When in the sleep mode, asserting a wakeup enabled in the code and protect assets. See Lockbox Secure Technology Dis- SIC_IWRx registers causes the processor to sense the value of claimer on Page22. the BYPASS bit in the PLL control register (PLL_CTL). If BYPASS is disabled, the processor transitions to the full-on mode. If BYPASS is enabled, the processor transitions to the active mode. Rev. D | Page 14 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 System DMA access to L1 memory is not supported in Power Savings sleep mode. As shown in Table5, the processor supports six different power Deep Sleep Operating Mode—Maximum Dynamic Power domains, which maximizes flexibility while maintaining com- Savings pliance with industry standards and conventions. By isolating the internal logic of the processor into its own power domain, The deep sleep mode maximizes dynamic power savings by dis- separate from the RTC and other I/O, the processor can take abling the clocks to the processor core (CCLK) and to all advantage of dynamic power management without affecting the synchronous peripherals (SCLK). Asynchronous peripherals, RTC or other I/O devices. There are no sequencing require- such as the RTC, may still be running but cannot access internal ments for the various power domains, but all domains must be resources or external memory. This powered-down mode can powered according to the appropriate Specifications table for only be exited by assertion of the reset interrupt (RESET) or by processor Operating Conditions; even if the feature/peripheral an asynchronous interrupt generated by the RTC. When in deep is not used. sleep mode, an RTC asynchronous interrupt causes the proces- sor to transition to the Active mode. Assertion of RESET while Table 5. Power Domains in deep sleep mode causes the processor to transition to the full on mode. Power Domain V Range DD All internal logic, except RTC, Memory, USB, OTP V Hibernate State—Maximum Static Power Savings DDINT RTC internal logic and crystal I/O V DDRTC The hibernate state maximizes static power savings by disabling Memory logic V the voltage and clocks to the processor core (CCLK) and to all of DDMEM USB PHY logic V the synchronous peripherals (SCLK). The internal voltage regu- DDUSB lator (ADSP-BF523/ADSP-BF525/ADSP-BF527 only) for the OTP logic V DDOTP processor can be shut off by writing b#00 to the FREQ bits of the All other I/O V DDEXT VR_CTL register, using the bfrom_SysControl() function. This setting sets the internal power supply voltage (VDDINT) to 0V to The dynamic power management feature of the processor provide the lowest static power dissipation. Any critical infor- allows both the processor’s input voltage (V ) and clock fre- DDINT mation stored internally (for example, memory contents, quency (f ) to be dynamically controlled. CCLK register contents, and other information) must be written to a The power dissipated by a processor is largely a function of its nonvolatile storage device prior to removing power if the pro- clock frequency and the square of the operating voltage. For cessor state is to be preserved. Writing b#00 to the FREQ bits example, reducing the clock frequency by 25% results in a 25% also causes EXT_WAKE0 and EXT_WAKE1 to transition low, reduction in dynamic power dissipation, while reducing the which can be used to signal an external voltage regulator to voltage by 25% reduces dynamic power dissipation by more shutdown. than 40%. Further, these power savings are additive, in that if Since VDDEXT and VDDMEM can still be supplied in this mode, all the clock frequency and supply voltage are both reduced, the of the external pins three-state, unless otherwise specified. This power savings can be dramatic, as shown in the following allows other devices that may be connected to the processor to equations. still have power applied without drawing unwanted current. Power Savings Factor The Ethernet or USB modules can wake up the internal supply regulator (ADSP-BF525 and ADSP-BF527 only) or signal an f V 2 T external regulator to wake up using EXT_WAKE0 or = ---C----C---L---K---R----E---D---------D----D---I--N----T---R---E---D---- -----R----E---D--- f V  T  EXT_WAKE1. If PG15 does not connect as a PHYINT signal to CCLKNOM DDINTNOM NOM an external PHY device, PG15 can be pulled low by any other device to wake the processor up. The processor can also be % Power Savings = 1–Power Savings Factor100% woken up by a real-time clock wakeup event or by asserting the RESET pin. All hibernate wake-up events initiate the hardware where the variables in the equations are: reset sequence. Individual sources are enabled by the VR_CTL f is the nominal core clock frequency register. The EXT_WAKEx signals are provided to indicate the CCLKNOM occurrence of wake-up events. f is the reduced core clock frequency CCLKRED As long as V is applied, the VR_CTL register maintains its V is the nominal internal supply voltage DDEXT DDINTNOM state during hibernation. All other internal registers and memo- V is the reduced internal supply voltage ries, however, lose their content in the hibernate state. State DDINTRED variables may be held in external SRAM or SDRAM. The TNOM is the duration running at fCCLKNOM SCKELOW bit in the VR_CTL register controls whether or not T is the duration running at f RED CCLKRED SDRAM operates in self-refresh mode, which allows it to retain its content while the processor is in hibernate and through the subsequent reset sequence. Rev. D | Page 15 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ADSP-BF523/ADSP-BF525/ADSP-BF527 regulator, it is Power Good. The Soft Start feature is recom- VOLTAGE REGULATION mended to reduce the inrush currents and to reduce VDDINT voltage overshoot when coming out of hibernate or changing The ADSP-BF523/ADSP-BF525/ADSP-BF527 provides an on- voltage levels. The Power Good (PG) input signal allows the chip voltage regulator that can generate processor core voltage processor to start only after the internal voltage has reached a levels from an external supply. Figure5 shows the typical exter- chosen level. In this way, the startup time of the external nal components required to complete the power management regulator is detected after hibernation. For a complete system. description ofSoft Start and Power Good functionality, refer tothe ADSP-BF52x Blackfin Processor Hardware Reference. SETOFDECOUPLING ADSP-BF522/ADSP-BF524/ADSP-BF526 2.25V TO 3.6V VDDEXT CAPACITORS INPUTVOLTAGE (LOW-INDUCTANCE) VOLTAGE REGULATION RANGE VDDEXT The ADSP-BF522/ADSP-BF524/ADSP-BF526 processor + requires an external voltage regulator to power the V DDINT 100μF domain. To reduce standby power consumption, the external 100μF 100nF 10μH voltage regulator can be signaled through EXT_WAKE0 or VDDINT EXT_WAKE1 to remove power from the processor core. These + + identical signals are high-true for power-up and may be con- FDS9431A nected directly to the low-true shut down input of many 10μF ZHCS1000 100μF SS/PG common regulators. While in the hibernate state, all external LOWESR supplies (V , V , V , V ) can still be applied, DDEXT DDMEM DDUSB DDOTP VROUT eliminating the need for external buffers. VDDRTC must be SHORTANDLOW- EXT_WAKE1 applied at all times for correct hibernate operation. The external INDUCTANCEWIRE SEE H/W REFERENCE, VRSEL voltage regulator can be activated from this power down state SYSTEM DESIGN CHAPTER, either through an RTC wakeup, a USB wakeup, an Ethernet TO DETERMINE VALUE GND wakeup, or by asserting the RESET pin, each of which then initi- NOTE: DESIGNERSHOULDMINIMIZE ates a boot sequence. EXT_WAKE0 or EXT_WAKE1 indicate a TRACELENGTHTOFDS9431A. wakeup to the external voltage regulator. The Power Good (PG) Figure 5. ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulator Circuit input signal allows the processor to start only after the internal voltage has reached a chosen level. In this way, the startup time The regulator controls the internal logic voltage levels and is of the external regulator is detected after hibernation. For a programmable with the voltage regulator control register complete description of the Power Good functionality, refer to (VR_CTL) in increments of 50mV. This register can be the ADSP-BF52x Blackfin Processor Hardware Reference. accessed using the bfrom_SysControl() function in the on-chip CLOCK SIGNALS ROM. To reduce standby power consumption, the internal volt- age regulator can be programmed to remove power to the The processor can be clocked by an external crystal, a sine wave processor core while keeping I/O power supplied. While in the input, or a buffered, shaped clock derived from an external hibernate state, all external supplies (VDDEXT, VDDMEM, VDDUSB, clock oscillator. V ) can still be applied, eliminating the need for external DDOTP If an external clock is used, it should be a TTL compatible signal buffers. V must be applied at all times for correct hibernate DDRTC and must not be halted, changed, or operated below the speci- operation. The voltage regulator can be activated from this fied frequency during normal operation. This signal is power-down state either through an RTC wakeup, a USB wake- connected to the processor’s CLKIN pin. When an external up, an Ethernet wake-up, or by asserting the RESET pin, each of clock is used, the XTAL pin must be left unconnected. which then initiates a boot sequence. The regulator can also be disabled and bypassed at the user’s discretion. Alternatively, because the processor includes an on-chip oscilla- tor circuit, an external crystal may be used. For fundamental The voltage regulator has two modes set by the VR pin—the SEL frequency operation, use the circuit shown in Figure6. A normal pulse width control of an external FET and the external parallel-resonant, fundamental frequency, microprocessor- supply mode which can signal a power down during hibernate grade crystal is connected across the CLKIN and XTAL pins. to an external regulator. Set VR to V to use an external SEL DDEXT The on-chip resistance between CLKIN and the XTAL pin is in regulator or set VR to GND to use the internal regulator. In SEL the 500 kΩ range. Further parallel resistors are typically not rec- the external mode VR becomes EXT_WAKE1. If the internal OUT ommended. The two capacitors and the series resistor shown in regulator is used, EXT_WAKE0 can control other power Figure6 fine tune phase and amplitude of the sine frequency. sources in the system during the hibernate state. Both signals are high-true for power-up and may be connected directly to the The capacitor and resistor values shown in Figure6 are typical low-true shutdown input of many common regulators. The values only. The capacitor values are dependent upon the crystal mode of the SS/PG (Soft Start/Power Good) signal also changes manufacturers’ load capacitance recommendations and the PCB according to the state of VR . When using an internal regula- physical layout. The resistor value depends on the drive level SEL tor, the SS/PG pin is Soft Start, and when using an external Rev. D | Page 16 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 specified by the crystal manufacturer. The user should verify the permitted to run up to the frequency specified by the part’s customized values based on careful investigations on multiple maximum instruction rate. The CLKOUT pin reflects the SCLK devices over temperature range. frequency to the off-chip world. It is part of the SDRAM inter- face, but it functions as a reference signal in other timing specifications as well. While active by default, it can be disabled BLACKFIN using the EBIU_SDGCTL and EBIU_AMGCTL registers. CLKOUT TOPLLCIRCUITRY “FINE”ADJUSTMENT “COARSE”ADJUSTMENT EN REQUIRESPLLSEQUENCING ON-THE-FLY CLKBUF 560(cid:2) ÷1,2,4,8 CCLK EN PLL CLKIN CLKIN XTAL 5(cid:117)to64(cid:117) VCO 330(cid:2)* ÷1to15 SCLK FOROVERTONE OPERATIONONLY: 18pF* 18pF* SCLK(cid:100)CCLK Figure 7. Frequency Modification Methods NOTE:VALUESMARKEDWITH*MUSTBECUSTOMIZED,DEPENDING ONTHECRYSTALANDLAYOUT.PLEASEANALYZECAREFULLY.FOR FREQUENCIESABOVE33MHz,THESUGGESTEDCAPACITORVALUE All on-chip peripherals are clocked by the system clock (SCLK). OF18pFSHOULDBETREATEDASAMAXIMUM,ANDTHESUGGESTED The system clock frequency is programmable by means of the RESISTORVALUESHOULDBEREDUCEDTO0(cid:2). SSEL3–0 bits of the PLL_DIV register. The values programmed Figure 6. External Crystal Connections into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through A third-overtone crystal can be used for frequencies above 15. Table6 illustrates typical system clock ratios. 25MHz. The circuit is then modified to ensure crystal operation Note that the divisor ratio must be chosen to limit the system only at the third overtone by adding a tuned inductor circuit as clock frequency to its maximum of f . The SSEL value can be shown in Figure6. A design procedure for third-overtone oper- SCLK dynamically changed without any PLL lock latencies by writing ation is discussed in detail in application note (EE-168) Using the appropriate values to the PLL divisor register (PLL_DIV) Third Overtone Crystals with the ADSP-218x DSP on the Analog using the bfrom_SysControl() function in the on-chip ROM. Devices website (www.analog.com)—use site search on “EE-168.” Table 6. Example System Clock Ratios The CLKBUF pin is an output pin, which is a buffered version of the input clock. This pin is particularly useful in Ethernet Example Frequency Ratios applications to limit the number of required clock sources in the Signal Name Divider Ratio (MHz) system. In this type of application, a single 25MHz or 50MHz SSEL3–0 VCO/SCLK VCO SCLK crystal may be applied directly to the processor. The 25MHz or 0001 1:1 100 100 50 MHz output of CLKBUF can then be connected to an exter- 0110 6:1 300 50 nal Ethernet MII or RMII PHY device. If, instead of a crystal, an 1010 10:1 500 50 external oscillator is used at CLKIN, CLKBUF will not have the 40/60 duty cycle required by some devices. The CLKBUF output The core clock (CCLK) frequency can also be dynamically is active by default and can be disabled for power savings rea- changed by means of the CSEL1–0 bits of the PLL_DIV register. sons using the VR_CTL register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in The Blackfin core runs at a different clock rate than the on-chip Table7. This programmable core clock capability is useful for peripherals. As shown in Figure7, the core clock (CCLK) and fast core frequency modifications. system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying Table 7. Core Clock Ratios the CLKIN signal by a programmable multiplication factor (bounded by specified minimum and maximum VCO frequen- Example Frequency Ratios cies). The default multiplier can be modified by a software Signal Name Divider Ratio (MHz) instruction sequence. This sequence is managed by the CSEL1–0 VCO/CCLK VCO CCLK bfrom_SysControl() function in the on-chip ROM. 00 1:1 300 300 On-the-fly CCLK and SCLK frequency changes can be applied 01 2:1 300 150 by using the bfrom_SysControl() function in the on-chip ROM. 10 4:1 500 125 The maximum allowed CCLK and SCLK rates depend on the 11 8:1 200 25 applied voltages V , V , and V ; the VCO is always DDINT DDEXT DDMEM Rev. D | Page 17 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 The maximum CCLK frequency not only depends on the part's kernel performs an 8- or 16-bit boot or starts program exe- maximum instruction rate (see Page 88). This frequency also cution at the address provided by the header. By default, all depends on the applied V voltage. See Table12 and configuration settings are set for the slowest device possible DDINT Table15 for details. The maximal system clock rate (SCLK) (3-cycle hold time, 15-cycle R/W access times, 4-cycle depends on the chip package and the applied V , V , setup). DDINT DDEXT and V voltages (see Table14 and Table17). DDMEM The ARDY is not enabled by default, but it can be enabled BOOTING MODES through OTP programming. Similarly, all interface behav- ior and timings can be customized through OTP The processor has several mechanisms (listed in Table8) for programming. This includes activation of burst-mode or automatically loading internal and external memory after a page-mode operation. In this mode, all asynchronous reset. The boot mode is defined by four BMODE input pins interface signals are enabled at the port muxing level. dedicated to this purpose. There are two categories of boot • Boot from 16-bit asynchronous FIFO (BMODE=0x2) — modes. In master boot modes the processor actively loads data In this mode, the boot kernel starts booting from address from parallel or serial memories. In slave boot modes the pro- 0x2030 0000. Every 16-bit word that the boot kernel has to cessor receives data from external host devices. read from the FIFO must be requested by placing a low The boot modes listed in Table8 provide a number of mecha- pulse on the DMAR1 pin. nisms for automatically loading the processor’s internal and • Boot from serial SPI memory, EEPROM or flash external memories after a reset. By default, all boot modes use (BMODE=0x3) — 8-, 16-, 24-, or 32-bit addressable the slowest meaningful configuration settings. Default settings devices are supported. The processor uses the PG1 GPIO can be altered via the initialization code feature at boot time or pin to select a single SPI EEPROM/flash device and sub- by proper OTP programming at pre-boot time. The BMODE mits a read command and successive address bytes (0x00) pins of the reset configuration register, sampled during power- until a valid 8-, 16-, 24-, or 32-bit addressable device is on resets and software-initiated resets, implement the modes detected. Pull-up resistors are required on the SPISEL1 and shown in Table8. MISO pins. By default, a value of 0x85 is written to the SPI_BAUD register. Table 8. Booting Modes • Boot from SPI host device (BMODE=0x4) — The proces- BMODE3–0 Description sor operates in SPI slave mode and is configured to receive 0000 Idle — No boot the bytes of the LDR file from an SPI host (master) agent. 0001 Boot from 8- or 16-bit external flash memory The HWAIT signal must be interrogated by the host before every transmitted byte. A pull-up resistor is required on the 0010 Boot from 16-bit asynchronous FIFO SPISS input. A pull-down on the serial clock (SCK) may 0011 Boot from serial SPI memory (EEPROM or flash) improve signal quality and booting robustness. 0100 Boot from SPI host device • Boot from serial TWI memory, EEPROM/flash 0101 Boot from serial TWI memory (EEPROM/flash) (BMODE=0x5) — The processor operates in master mode 0110 Boot from TWI host and selects the TWI slave connected to the TWI with the 0111 Boot from UART0 Host unique ID 0xA0. 1000 Boot from UART1 Host The processor submits successive read commands to the 1001 Reserved memory device starting at internal address 0x0000 and begins clocking data into the processor. The TWI memory 1010 Boot from SDRAM device should comply with the Philips I2C® Bus Specifica- 1011 Boot from OTP memory tion version 2.1 and should be able to auto-increment its 1100 Boot from 8-bit NAND flash internal address counter such that the contents of the via NFC using PORTF data pins memory device can be read sequentially. By default, a 1101 Boot from 8-bit NAND flash PRESCALE value of 0xA and a TWI_CLKDIV value of via NFC using PORTH data pins 0x0811 are used. Unless altered by OTP settings, an I2C 1110 Boot from 16-Bit Host DMA memory that takes two address bytes is assumed. The development tools ensure that data booted to memories 1111 Boot from 8-Bit Host DMA that cannot be accessed by the Blackfin core is written to an intermediate storage location and then copied to the final • Idle/no boot mode (BMODE=0x0) — In this mode, the destination via memory DMA. processor goes into idle. The idle boot mode helps recover from illegal operating modes, such as when the OTP mem- • Boot from TWI host (BMODE=0x6) — The TWI host ory has been misconfigured. selects the slave with the unique ID 0x5F. • Boot from 8-bit or 16-bit external flash memory The processor replies with an acknowledgement and the (BMODE=0x1) — In this mode, the boot kernel loads the host then downloads the boot stream. The TWI host agent first block header from address 0x2000 0000, and (depend- should comply with the Philips I2C Bus Specification ing on instructions contained in the header) the boot Rev. D | Page 18 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 version 2.1. An I2C multiplexer can be used to select one —Software-configurable boot mode for booting from processor at a time when booting multiple processors from boot streams spanning multiple blocks, including bad a single TWI. blocks • Boot from UART0 host on Port G (BMODE=0x7) — —Software-configurable boot mode for booting from Using an autobaud handshake sequence, a boot-stream for- multiple copies of the boot stream, allowing for han- matted program is downloaded by the host. The host dling of bad blocks and uncorrectable errors selects a bit rate within the UART clocking capabilities. —Configurable timing via OTP memory When performing the autobaud, the UART expects a “@” Small page NAND flash devices must have a 512-byte page (0x40) character (eight bits data, one start bit, one stop bit, size, 32 pages per block, a 16-byte spare area size, and a bus no parity bit) on the UART0RX pin to determine the bit configuration of 8 bits. By default, all read requests from rate. The UART then replies with an acknowledgement the NAND flash are followed by four address cycles. If the composed of 4 bytes (0xBF, the value of UART0_DLL, the NAND flash device requires only three address cycles, the value of UART0_DLH, then 0x00). The host can then device must be capable of ignoring the additional address download the boot stream. To hold off the host the Blackfin cycles. processor signals the host with the boot host wait (HWAIT) signal. Therefore, the host must monitor The small page NAND flash device must comply with the HWAIT before every transmitted byte. following command set: • Boot from UART1 host on Port F (BMODE=0x8). Same —Reset: 0xFF as BMODE=0x7 except that the UART1 port is used. —Read lower half of page: 0x00 • Boot from SDRAM (BMODE=0xA) This is a warm boot —Read upper half of page: 0x01 scenario, where the boot kernel starts booting from address —Read spare area: 0x50 0x0000 0010. The SDRAM is expected to contain a valid boot stream and the SDRAM controller must be configured For large-page NAND-flash devices, the four-byte elec- by the OTP settings. tronic signature is read in order to configure the kernel for booting, which allows support for multiple large-page • Boot from OTP memory (BMODE=0xB) — This provides devices. The fourth byte of the electronic signature must a stand-alone booting method. The boot stream is loaded comply with the specification in Table9 on Page20. from on-chip OTP memory. By default, the boot stream is expected to start from OTP page 0x40 and can occupy all Any NAND flash array configuration from Table9, exclud- public OTP memory up to page 0xDF. This is 2560 bytes. ing 16-bit devices, that also complies with the command set Since the start page is programmable, the maximum size of listed below are directly supported by the boot kernel. the boot stream can be extended to 3072 bytes. There are no restrictions on the page size or block size as imposed by the small-page boot kernel. • Boot from 8-bit external NAND flash memory (BMODE = 0xC and BMODE = 0xD) — In this mode, auto detection of For devices consisting of a five-byte signature, only four are the NAND flash device is performed. read. The fourth must comply as outlined above. BMODE = 0xC, the processor configures PORTF GPIO Large page devices must support the following command pins PF7:0 for the NAND data pins and PORTH pins set: PH15:10 for the NAND control signals. —Reset: 0xFF BMODE = 0xD, the processor configures PORTH GPIO —Read Electronic Signature: 0x90 pins PH7:0 for the NAND data pins and PORTH pins —Read: 0x00, 0x30 (confirm command) PH15:10 for the NAND control signals. Large-page devices must not support or react to NAND For correct device operation pull-up resistors are required flash command 0x50. This is a small-page NAND flash on both ND_CE (PH10) and ND_BUSY (PH13) signals. By command used for device auto detection. default, a value of 0x0033 is written to the NFC_CTL regis- ter. The booting procedure always starts by booting from By default, the boot kernel will always issue five address byte 0 of block 0 of the NAND flash device. cycles; therefore, if a large page device requires only four cycles, the device must be capable of ignoring the addi- NAND flash boot supports the following features: tional address cycles. —Device Auto Detection • Boot from 16-Bit Host DMA (BMODE=0xE) — In this —Error Detection & Correction for maximum reliability mode, the host DMA port is configured in 16-bit Acknowl- —No boot stream size limitation edge mode, with little endian data formatting. Unlike other modes, the host is responsible for interpreting the boot —Peripheral DMA providing efficient transfer of all data stream. It writes data blocks individually into the Host (excluding the ECC parity data) DMA port. Before configuring the DMA settings for each block, the host may either poll the ALLOW_CONFIG bit in HOST_STATUS or wait to be interrupted by the HWAIT Rev. D | Page 19 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 signal. When using HWAIT, the host must still check INSTRUCTION SET DESCRIPTION ALLOW_CONFIG at least once before beginning to con- The Blackfin processor family assembly language instruction set figure the Host DMA Port. After completing the employs an algebraic syntax designed for ease of coding and configuration, the host is required to poll the READY bit in readability. The instructions have been specifically tuned to pro- HOST_STATUS before beginning to transfer data. When vide a flexible, densely encoded instruction set that compiles to the host sends an HIRQ control command, the boot kernel a very small final memory size. The instruction set also provides issues a CALL instruction to address 0xFFA0 0000. It is the fully featured multifunction instructions that allow the pro- host's responsibility to ensure that valid code has been grammer to use many of the processor core resources in a single placed at this address. The routine at 0xFFA0 0000 can be a instruction. Coupled with many features more often seen on simple initialization routine to configure internal microcontrollers, this instruction set is very efficient when com- resources, such as the SDRAM controller, which then piling C and C++ source code. In addition, the architecture returns using an RTS instruction. The routine may also by supports both user (algorithm/application code) and super- the final application, which will never return to the boot visor (O/S kernel, device drivers, debuggers, ISRs) modes kernel. ofoperation, allowing multiple levels of access to core • Boot from 8-Bit Host DMA (BMODE=0xF) — In this processor resources. mode, the Host DMA port is configured in 8-bit interrupt The assembly language, which takes advantage of the proces- mode, with little endian data formatting. Unlike other sor’s unique architecture, offers the following advantages: modes, the host is responsible for interpreting the boot stream. It writes data blocks individually into the Host • Seamlessly integrated DSP/MCU features are optimized for DMA port. Before configuring the DMA settings for each both 8-bit and 16-bit operations. block, the host may either poll the ALLOW_CONFIG bit in • A multi-issue load/store modified-Harvard architecture, HOST_STATUS or wait to be interrupted by the HWAIT which supports two 16-bit MAC or four 8-bit ALU + two signal. When using HWAIT, the host must still check load/store + two pointer updates per cycle. ALLOW_CONFIG at least once before beginning to con- • All registers, I/O, and memory are mapped into a unified figure the Host DMA Port. The host will receive an 4Gbyte memory space, providing a simplified program- interrupt from the HOST_ACK signal every time it is ming model. allowed to send the next FIFO depths worth (sixteen 32-bit words) of information. When the host sends an HIRQ con- • Microcontroller features, such as arbitrary bit and bit-field trol command, the boot kernel issues a CALL instruction to manipulation, insertion, and extraction; integer operations address 0xFFA0 0000. It is the host's responsibility to on 8-, 16-, and 32-bit data-types; and separate user and ensure valid code has been placed at this address. The rou- supervisor stack pointers. tine at 0xFFA0 0000 can be a simple initialization routine • Code density enhancements, which include intermixing of to configure internal resources, such as the SDRAM con- 16-bit and 32-bit instructions (no mode switching, no code troller, which then returns using an RTS instruction. The segregation). Frequently used instructions are encoded routine may also by the final application, which will never in 16 bits. return to the boot kernel. DEVELOPMENT TOOLS Table 9. Fourth Byte for Large Page Devices Analog Devices supports its processors with a complete line of Bit Parameter Value Meaning software and hardware development tools, including integrated development environments (which include CrossCore® Embed- D1:D0 Page Size 00 1K byte ded Studio and/or VisualDSP++®), evaluation products, (excluding spare area) 01 2K byte emulators, and a wide variety of software add-ins. 10 4K byte 11 8K byte Integrated Development Environments (IDEs) D2 Spare Area Size 00 8 byte/512 byte For C/C++ software writing and editing, code generation, and 01 16 byte/512 byte debug support, Analog Devices offers two IDEs. D5:D4 Block Size 00 64K byte The newest IDE, CrossCore Embedded Studio, is based on the (excluding spare area) 01 128K byte EclipseTM framework. Supporting most Analog Devices proces- 10 256K byte sor families, it is the IDE of choice for future processors, 11 512K byte including multicore devices. CrossCore Embedded Studio seamlessly integrates available software add-ins to support real D6 Bus width 00 x8 time operating systems, file systems, TCP/IP stacks, USB stacks, 01 not supported algorithmic software modules, and evaluation hardware board D3, D7 Not Used for configuration support packages. For more information, visit www.ana- log.com/cces. Rev. D | Page 20 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 The other Analog Devices IDE, VisualDSP++, supports proces- Middleware Packages sor families introduced prior to the release of CrossCore Analog Devices separately offers middleware add-ins such as Embedded Studio. This IDE includes the Analog Devices VDK real time operating systems, file systems, USB stacks, and TCP/ real time operating system and an open source TCP/IP stack. IP stacks. For more information see the following web pages: For more information visit www.analog.com/visualdsp. Note that VisualDSP++ will not support future Analog Devices • www.analog.com/ucos3 processors. • www.analog.com/ucfs EZ-KIT Lite Evaluation Board • www.analog.com/ucusbd For processor evaluation, Analog Devices provides wide range • www.analog.com/lwip of EZ-KIT Lite® evaluation boards. Including the processor and Algorithmic Modules key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development To speed development, Analog Devices offers add-ins that per- features. Also available are various EZ-Extenders®, which are form popular audio and video processing algorithms. These are daughter cards delivering additional specialized functionality, available for use with both CrossCore Embedded Studio and including audio and video processing. For more information VisualDSP++. For more information visit www.analog.com and visit www.analog.com and search on “ezkit” or “ezextender”. search on “Blackfin software modules” or “SHARC software modules”. EZ-KIT Lite Evaluation Kits Designing an Emulator-Compatible DSP Board(Target) For a cost-effective way to learn more about developing with Analog Devices processors, Analog Devices offer a range of EZ- For embedded system test and debug, Analog Devices provides KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT a family of emulators. On each JTAG DSP, Analog Devices sup- Lite evaluation board, directions for downloading an evaluation plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit version of the available IDE(s), a USB cable, and a power supply. emulation is facilitated by use of this JTAG interface. The emu- The USB controller on the EZ-KIT Lite board connects to the lator accesses the processor’s internal features via the USB port of the user’s PC, enabling the chosen IDE evaluation processor’s TAP, allowing the developer to load code, set break- suite to emulate the on-board processor in-circuit. This permits points, and view variables, memory, and registers. The the customer to download, execute, and debug programs for the processor must be halted to send data and commands, but once EZ-KIT Lite system. It also supports in-circuit programming of an operation is completed by the emulator, the DSP system is set the on-board Flash device to store user-specific boot code, to run at full speed with no impact on system timing. The emu- enabling standalone operation. With the full version of Cross- lators require the target board to include a header that supports Core Embedded Studio or VisualDSP++ installed (sold connection of the DSP’s JTAG port to the emulator. separately), engineers can develop software for supported EZ- For details on target board design issues including mechanical KITs or any custom system utilizing supported Analog Devices layout, single processor connections, signal buffering, signal ter- processors. mination, and emulator pod logic, see the Engineer-to-Engineer Note “Analog Devices JTAG Emulation Technical Reference” Software Add-Ins for CrossCore Embedded Studio (EE-68) on the Analog Devices website (www.analog.com)—use Analog Devices offers software add-ins which seamlessly inte- site search on “EE-68.” This document is updated regularly to grate with CrossCore Embedded Studio to extend its capabilities keep pace withimprovements to emulator support. and reduce development time. Add-ins include board support packages for evaluation hardware, various middleware pack- ADDITIONAL INFORMATION ages, and algorithmic modules. Documentation, help, The following publications that describe the ADSP-BF52x pro- configuration dialogs, and coding examples present in these cessors (and related processors) can be ordered from any add-ins are viewable through the CrossCore Embedded Studio Analog Devices sales office or accessed electronically on IDE once the add-in is installed. ourwebsite: Board Support Packages for Evaluation Hardware • Getting Started With Blackfin Processors Software support for the EZ-KIT Lite evaluation boards and EZ- • ADSP-BF52x Blackfin Processor Hardware Reference (vol- Extender daughter cards is provided by software add-ins called umes 1 and 2) Board Support Packages (BSPs). The BSPs contain the required • Blackfin Processor Programming Reference drivers, pertinent release notes, and select example code for the given evaluation hardware. A download link for a specific BSP is • ADSP-BF522/ADSP-BF524/ADSP-BF526 Blackfin Proces- located on the web page for the associated EZ-KIT or EZ- sor Anomaly List Extender product. The link is found in the Product Download • ADSP-BF523/ADSP-BF525/ADSP-BF527 Blackfin Proces- area of the product web page. sor Anomaly List Rev. D | Page 21 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 RELATED SIGNAL CHAINS A signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the “signal chain” entry in Wikipedia or the Glossary of EE Terms on the Analog Devices website. Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. The Application Signal Chains page in the Circuits from the LabTM site (http:\\www.analog.com\signalchains) provides: • Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications • Drill down links for components in each chain to selection guides and application information • Reference designs applying best practice design techniques LOCKBOX SECURE TECHNOLOGY DISCLAIMER Analog Devices products containing Lockbox Secure Technol- ogy are warranted by Analog Devices as detailed in the Analog Devices Standard Terms and Conditions of Sale. To our knowl- edge, the Lockbox Secure Technology, when used in accordance with the data sheet and hardware reference manual specifica- tions, provides a secure method of implementing code and data safeguards. However, Analog Devices does not guarantee that this technology provides absolute security. ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL EXPRESS AND IMPLIED WARRANTIES THAT THE LOCKBOX SECURE TECHNOLOGY CANNOT BE BREACHED, COMPROMISED, OR OTHERWISE CIR- CUMVENTED AND IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF DATA, INFORMATION, PHYSICAL PROPERTY, OR INTELLECTUAL PROPERTY. Rev. D | Page 22 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 SIGNAL DESCRIPTIONS Signal definitions for the ADSP-BF52x processors are listed in All I/O pins have their input buffers disabled with the exception Table10. In order to maintain maximum function and reduce of the pins that need pull-ups or pull-downs, as noted in package size and ball count, some balls have dual, multiplexed Table10. functions. In cases where ball function is reconfigurable, the It is strongly advised to use the available IBIS models to ensure default state is shown in plain text, while the alternate function that a given board design meets overshoot/undershoot and sig- is shown in italics. nal integrity requirements. If no IBIS simulation is performed, it All pins are three-stated during and immediately after reset, is strongly recommended to add series resistor terminations for with the exception of the external memory interface, asynchro- all Driver Types A, C and D. nous and synchronous memory control, and the buffered XTAL The termination resistors should be placed near the processor to output pin (CLKBUF). On the external memory interface, the reduce transients and improve signal integrity. The resistance control and address lines are driven high, with the exception of value, typically 33Ω or 47Ω, should be chosen to match the CLKOUT, which toggles at the system clock rate. During hiber- average board trace impedance. nate, all outputs are three-stated unless otherwise noted in Table10. Additionally, adding a parallel termination to CLKOUT may prove useful in further enhancing signal integrity. Be sure to verify overshoot/undershoot and signal integrity specifications on actual hardware. Table 10. Signal Descriptions Driver Signal Name Type Function Type1 EBIU ADDR19–1 O Address Bus A DATA15–0 I/O Data Bus A ABE1–0/SDQM1–0 O Byte Enables/Data Mask A AMS3–0 O Asynchronous Memory Bank Selects (Require pull-ups if hibernate is used.) A ARDY I Hardware Ready Control AOE O Asynchronous Output Enable A ARE O Asynchronous Read Enable A AWE O Asynchronous Write Enable A SRAS O SDRAM Row Address Strobe A SCAS O SDRAM Column Address Strobe A SWE O SDRAM Write Enable A SCKE O SDRAM Clock Enable (Requires a pull-down if hibernate with SDRAM self- A refresh is used.) CLKOUT O SDRAM Clock Output B SA10 O SDRAM A10 Signal A SMS O SDRAM Bank Select A Rev. D | Page 23 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 10. Signal Descriptions (Continued) Driver Signal Name Type Function Type1 USB 2.0 HS OTG USB_DP I/O Data + (This ball should be pulled low when USB is unused or not present.) F USB_DM I/O Data – (This ball should be pulled low when USB is unused or not present.) F USB_XI I USB Crystal Input (This ball should be pulled low when USB is unused or not present.) USB_XO O USB Crystal Output (This ball should be left unconnected when USB is unused F or not present.) USB_ID I USB OTG mode (This ball should be pulled low when USB is unused or not present.) USB_VREF A USB voltage reference (Connect to GND through a 0.1 μF capacitor or leave unconnected when not used.) USB_RSET A USB resistance set. (This ball should be left unconnected.) USB_VBUS I/O 5VUSB VBUS. USB_VBUS is an output only in peripheral mode during SRP F signaling. Host mode requires that an external voltage source of 5 V at 8 mA or more (per the OTG specification) be applied to VBUS. The voltage source needs to be able to charge and discharge VBUS, thus an ON/OFF switch is required to control the voltage source. A GPIO can be used for this purpose (This ball should be pulled low when USB is unused or not present.) Port F: GPIO and Multiplexed Peripherals PF0/PPI D0/DR0PRI /ND_D0A I/O GPIO/PPI Data 0/SPORT0 Primary Receive Data C /NAND Alternate Data 0 PF1/PPI D1/RFS0/ND_D1A I/O GPIO/PPI Data 1/SPORT0 Receive Frame Sync C /NAND Alternate Data 1 PF2/PPI D2/RSCLK0/ND_D2A I/O GPIO/PPI Data 2/SPORT0 Receive Serial Clock D /NAND Alternate Data 2/Alternate Capture Input 0 PF3/PPI D3/DT0PRI/ND_D3A I/O GPIO/PPI Data 3/SPORT0 Transmit Primary Data C /NAND Alternate Data 3 PF4/PPI D4/TFS0/ND_D4A/TACLK0 I/O GPIO/PPI Data 4/SPORT0 Transmit Frame Sync C /NAND Alternate Data 4/Alternate Timer Clock 0 PF5/PPI D5/TSCLK0/ND_D5A/TACLK1 I/O GPIO/PPI Data 5/SPORT0 Transmit Serial Clock D /NAND Alternate Data 5/Alternate Timer Clock 1 PF6/PPI D6/DT0SEC/ND_D6A/TACI0 I/O GPIO/PPI Data 6/SPORT0 Transmit Secondary Data C /NAND Alternate Data 6/Alternate Capture Input 0 PF7/PPI D7/DR0SEC/ND_D7A/TACI1 I/O GPIO/PPI Data 7/SPORT0 Receive Secondary Data C /NAND Alternate Data 7/Alternate Capture Input 1 PF8/PPI D8/DR1PRI I/O GPIO/PPI Data 8/SPORT1 Primary Receive Data C PF9/PPI D9/RSCLK1/SPISEL6 I/O GPIO/PPI Data 9/SPORT1 Receive Serial Clock/SPI Slave Select 6 D PF10/PPI D10/RFS1/SPISEL7 I/O GPIO/PPI Data 10/SPORT1 Receive Frame Sync/SPI Slave Select 7 C PF11/PPI D11/TFS1/CZM I/O GPIO/PPI Data 11/SPORT1 Transmit Frame Sync/Counter Zero Marker C PF12/PPI D12/DT1PRI/SPISEL2/CDG I/O GPIO/PPI Data 12/SPORT1 Transmit Primary Data/SPI Slave Select 2/Counter C Down Gate PF13/PPI D13/TSCLK1/SPISEL3/CUD I/O GPIO/PPI Data 13/SPORT1 Transmit Serial Clock/SPI Slave Select 3/Counter Up D Direction PF14/PPI D14/DT1SEC/UART1TX I/O GPIO/PPI Data 14/SPORT1 Transmit Secondary Data/UART1 Transmit C PF15/PPI D15/DR1SEC/UART1RX/TACI3 I/O GPIO/PPI Data 15/SPORT1 Receive Secondary Data C /UART1 Receive /Alternate Capture Input 3 Rev. D | Page 24 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 10. Signal Descriptions (Continued) Driver Signal Name Type Function Type1 Port G: GPIO and Multiplexed Peripherals PG0/HWAIT I/O GPIO/Boot Host Wait2 C PG1/SPISS/SPISEL1 I/O GPIO/SPI Slave Select Input/SPI Slave Select 1 C PG2/SCK I/O GPIO/SPI Clock D PG3/MISO/DR0SECA I/O GPIO/SPI Master In Slave Out/Sport 0 Alternate Receive Data Secondary C PG4/MOSI/DT0SECA I/O GPIO/SPI Master Out Slave In/Sport 0 Alternate Transmit Data Secondary C PG5/TMR1/PPI_FS2 I/O GPIO/Timer1/PPI Frame Sync2 C PG6/DT0PRIA/TMR2/PPI_FS3 I/O GPIO/SPORT0 Alternate Primary Transmit Data / Timer2 / PPI Frame Sync3 C PG7/TMR3/DR0PRIA/UART0TX I/O GPIO/Timer3/Sport 0 Alternate Receive Data Primary/UART0 Transmit C PG8/TMR4/RFS0A/UART0RX/TACI4 I/O GPIO/Timer 4/Sport 0 Alternate Receive Clock/Frame Sync C /UART0 Receive/Alternate Capture Input 4 PG9/TMR5/RSCLK0A/TACI5 I/O GPIO/Timer5/Sport 0 Alternate Receive Clock D /Alternate Capture Input 5 PG10/TMR6/TSCLK0A/TACI6 I/O GPIO/Timer 6 /Sport 0 Alternate Transmit D /Alternate Capture Input 6 PG11/TMR7/HOST_WR I/O GPIO/Timer7/Host DMA Write Enable C PG12/DMAR1/UART1TXA/HOST_ACK I/O GPIO/DMA Request 1/Alternate UART1 Transmit/Host DMA Acknowledge C PG13/DMAR0/UART1RXA/HOST_ADDR/TACI2 I/O GPIO/DMA Request 0/Alternate UART1 Receive/Host DMA Address/Alternate C Capture Input 2 PG14/TSCLK0A1/MDC/HOST_RD I/O GPIO/SPORT0 Alternate 1 Transmit/Ethernet Management Channel Clock D /Host DMA Read Enable PG153/TFS0A/MII PHYINT/RMII MDINT/HOST_CEI/O GPIO/SPORT0 Alternate Transmit Frame Sync/Ethernet/MII PHY Interrupt/RMII C Management Channel Data Interrupt/Host DMA Chip Enable Port H: GPIO and Multiplexed Peripherals PH0/ND_D0/MIICRS/RMIICRSDV/HOST_D0 I/O GPIO/NAND D0/Ethernet MII or RMII Carrier Sense/Host DMA D0 C PH1/ND_D1/ERxER/HOST_D1 I/O GPIO/NAND D1/Ethernet MII or RMII Receive Error/Host DMA D1 C PH2/ND_D2/MDIO/HOST_D2 I/O GPIO/NAND D2/Ethernet Management Channel Serial Data/Host DMA D2 C PH3/ND_D3/ETxEN/HOST_D3 I/O GPIO/NAND D3/Ethernet MII Transmit Enable/Host DMA D3 C PH4/ND_D4/MIITxCLK/RMIIREF_CLK/HOST_D4 I/O GPIO/NAND D4/Ethernet MII or RMII Reference Clock/Host D4 C PH5/ND_D5/ETxD0/HOST_D5 I/O GPIO/NAND D5/Ethernet MII or RMII Transmit D0/Host DMA D5 C PH6/ND_D6/ERxD0/HOST_D6 I/O GPIO/NAND D6/Ethernet MII or RMII Receive D0/Host DMA D6 C PH7/ND_D7/ETxD1/HOST_D7 I/O GPIO/NAND D7/Ethernet MII or RMII Transmit D1/Host DMA D7 C PH8/SPISEL4/ERxD1/HOST_D8/TACLK2 I/O GPIO/Alternate Timer Clock 2/Ethernet MII or RMII Receive D1/Host DMA D8 C /SPI Slave Select 4 PH9/SPISEL5/ETxD2/HOST_D9/TACLK3 I/O GPIO/SPI Slave Select 5/Ethernet MII Transmit D2/Host DMA D9 C /Alternate Timer Clock 3 PH10/ND_CE/ERxD2/HOST_D10 I/O GPIO/NAND Chip Enable/Ethernet MII Receive D2/Host DMA D10 C PH11/ND_WE/ETxD3/HOST_D11 I/O GPIO/NAND Write Enable/Ethernet MII Transmit D3/Host DMA D11 C PH12/ND_RE/ERxD3/HOST_D12 I/O GPIO/NAND Read Enable/Ethernet MII Receive D3/Host DMA D12 C PH13/ND_BUSY/ERxCLK/HOST_D13 I/O GPIO/NAND Busy/Ethernet MII Receive Clock/Host DMA D13 C PH14/ND_CLE/ERxDV/HOST_D14 I/O GPIO/NAND Command Latch Enable/Ethernet MII or RMII Receive Data Valid/ C Host DMA D14 PH15/ND_ALE/COL/HOST_D15 I/O GPIO/NAND Address Latch Enable/Ethernet MII Collision/Host DMA Data 15 C Rev. D | Page 25 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 10. Signal Descriptions (Continued) Driver Signal Name Type Function Type1 Port J: Multiplexed Peripherals PJ0: PPI_FS1/TMR0 I/O PPI Frame Sync1/Timer0 C PJ1: PPI_CLK/TMRCLK I PPI Clock/Timer Clock PJ2: SCL I/O 5VTWI Serial Clock (This pin is an open-drain output and requires a pull-up E resistor.4) PJ3: SDA I/O 5VTWI Serial Data (This pin is an open-drain output and requires a pull-up E resistor.4) Real Time Clock RTXI I RTC Crystal Input (This ball should be pulled low when not used.) RTXO O RTC Crystal Output (Does not three-state during hibernate.) JTAG Port TCK I JTAG Clock TDO O JTAG Serial Data Out C TDI I JTAG Serial Data In TMS I JTAG Mode Select TRST I JTAG Reset (This ball should be pulled low if the JTAG port is not used.) EMU O Emulation Output C Clock CLKIN I Clock/Crystal Input XTAL O Crystal Output (If CLKBUF is enabled, does not three-state during hibernate.) CLKBUF O Buffered XTAL Output (If enabled, does not three-state during hibernate.) C Mode Controls RESET I Reset NMI I Nonmaskable Interrupt (This ball should be pulled high when not used.) BMODE3–0 I Boot Mode Strap 3-0 ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulation I/F VR I Internal/External Voltage Regulator Select SEL VR /EXT_WAKE1 O External FET Drive/Wake up Indication 1 (Does not three-state during G OUT hibernate.) EXT_WAKE0 O Wake up Indication 0 (Does not three-state during hibernate.) C SS/PG A Soft Start/Power Good ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation I/F EXT_WAKE1 O Wake up Indication 1 (Does not three-state during hibernate.) C EXT_WAKE0 O Wake up Indication 0 (Does not three-state during hibernate.) C PG A Power Good (This signal should be pulled low when not used.) Rev. D | Page 26 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 10. Signal Descriptions (Continued) Driver Signal Name Type Function Type1 Power Supplies ALL SUPPLIES MUST BE POWERED See Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors on Page30, and see Operating Conditions for ADSP-BF522/ ADSP-BF524/ADSP-BF526 Processors on Page28. V P I/O Power Supply DDEXT V P Internal Power Supply DDINT V P Real Time Clock Power Supply DDRTC V P 3.3 V USB Phy Power Supply DDUSB V P MEM Power Supply DDMEM V P OTP Power Supply DDOTP V P OTP Programming Voltage PPOTP GND G Ground for All Supplies 1See Output Drive Currents on Page73 for more information about each driver type. 2HWAIT must be pulled high or low to configure polarity. It is driven as an output and toggle during processor boot. See Booting Modes on Page18. 3When driven low, this ball can be used to wake up the processor from the hibernate state, either in normal GPIO mode or in Ethernet mode as MII PHYINT. If the ball is used for wake up, enable the feature with the PHYWE bit in the VR_CTL register, and pull-up the ball with a resistor. 4Consult version 2.1 of the I2C specification for the proper resistor value. Rev. D | Page 27 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 SPECIFICATIONS Specifications are subject to change without notice. OPERATING CONDITIONS FOR ADSP-BF522/ADSP-BF524/ADSP-BF526 PROCESSORS Parameter Conditions Min Nominal Max Unit V Internal Supply Voltage 1.235 1.47 V DDINT V External Supply Voltage1 1.7 1.8 1.9 V DDEXT V External Supply Voltage1 2.25 2.5 2.75 V DDEXT V External Supply Voltage1 3 3.3 3.6 V DDEXT V RTC Power Supply Voltage2 2.25 3.6 V DDRTC V MEM Supply Voltage1, 3 1.7 1.8 1.9 V DDMEM V MEM Supply Voltage1, 3 2.25 2.5 2.75 V DDMEM V MEM Supply Voltage1, 3 3 3.3 3.6 V DDMEM V OTP Supply Voltage1 2.25 2.5 2.75 V DDOTP V OTP Programming Voltage1 PPOTP For Reads 2.25 2.5 2.75 V For Writes4 6.9 7.0 7.1 V V USB Supply Voltage5 3.0 3.3 3.6 V DDUSB V High Level Input Voltage6,7 V /V = 1.90 V 1.1 V IH DDEXT DDMEM V High Level Input Voltage6,8 V /V = 2.75 V 1.7 V IH DDEXT DDMEM V High Level Input Voltage6,8 V /V = 3.6 V 2.0 V IH DDEXT DDMEM V 9 High Level Input Voltage V = 1.90 V/2.75 V/3.6 V 0.7 × V V V IHTWI DDEXT BUSTWI BUSTWI V Low Level Input Voltage6,7 V /V = 1.7 V 0.6 V IL DDEXT DDMEM V Low Level Input Voltage6,8 V /V = 2.25 V 0.7 V IL DDEXT DDMEM V Low Level Input Voltage6,8 V /V = 3.0 V 0.8 V IL DDEXT DDMEM V Low Level Input Voltage V = Minimum 0.3 × V 10 V ILTWI DDEXT BUSTWI T Junction Temperature 289-Ball CSP_BGA 0 +105 °C J @T =0°C to +70°C AMBIENT T Junction Temperature 208-Ball CSP_BGA 0 +105 °C J @T =0°C to +70°C AMBIENT T Junction Temperature 208-Ball CSP_BGA –40 +105 °C J @T =–40°C to +85°C AMBIENT 1Must remain powered (even if the associated function is not used). 2If not used, power with V . DDEXT 3Balls that use V are DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AOE, AMS3–0, ARDY, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These balls are not tolerant DDMEM to voltages higher than V . DDMEM 4The V voltage for writes must only be applied when programming OTP memory. There is a finite amount of cumulative time that this voltage may be applied (dependent PPOTP on voltage and junction temperature) over the lifetime of the part. Please see Table30 on Page38 for details. 5When not using the USB peripheral on the ADSP-BF524/ADSP-BF526 or terminating V on the ADSP-BF522, V must be powered by V . DDUSB DDUSB DDEXT 6Parameter value applies to all input and bidirectional balls, except USB_DP, USB_DM, USB_VBUS, SDA, and SCL. 7Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF52x processors are 2.5 V tolerant (always accept up to 2.7 V maximum V ). Voltage compliance (on outputs, V ) is limited by the V supply voltage. IH OH DDEXT 8Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF52x processors are 3.3 V tolerant (always accept up to 3.6 V maximum V ). Voltage compliance (on outputs, V ) is limited by the V supply voltage. IH OH DDEXT 9The V min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See V min and max values in Table11. IHTWI BUSTWI 10SDA and SCL are pulled up to V . See Table11. BUSTWI Rev. D | Page 28 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table11 shows settings for TWI_DT in the NONGPIO_DRIVE register. Set this register prior to using the TWI port. Table 11. TWI_DT Field Selections and V /V DDEXT BUSTWI TWI_DT V Nominal V Min V Nominal V Max Unit DDEXT BUSTWI BUSTWI BUSTWI 000 (default)1 3.3 2.97 3.3 3.63 V 001 1.8 1.7 1.8 1.98 V 010 2.5 2.97 3.3 3.63 V 011 1.8 2.97 3.3 3.63 V 100 3.3 4.5 5 5.5 V 101 1.8 2.25 2.5 2.75 V 110 2.5 2.25 2.5 2.75 V 111 (reserved) – – – – – 1Designs must comply with the V and V voltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset. DDEXT BUSTWI Clock Related Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Table12 describes the core clock timing requirements for the ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock (see Table14). Table13 describes phase-locked loop operating conditions. Table 12. Core Clock (CCLK) Requirements (All Instruction Rates1) for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Parameter Nominal Voltage Setting Max Unit f Core Clock Frequency (V =1.33 V minimum) 1.40 V 4002 MHz CCLK DDINT f Core Clock Frequency (V = 1.235 V minimum) 1.30 V 300 MHz CCLK DDINT 1See the Ordering Guide on Page88. 2Applies to 400 MHz models only. See the Ordering Guide on Page88. Table 13. Phase-Locked Loop Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Parameter Min Max Unit f Voltage Controlled Oscillator (VCO) Frequency 70 Instruction Rate1 MHz VCO 1See the Ordering Guide on Page88. Table 14. SCLK Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors V /V V /V DDEXT DDMEM DDEXT DDMEM 1.8 V Nominal1 2.5 V or 3.3 V Nominal Parameter Max Max Unit f CLKOUT/SCLK Frequency (V ≥ 1.33 V)2 80 100 MHz SCLK DDINT f CLKOUT/SCLK Frequency (V < 1.33 V) 80 80 MHz SCLK DDINT 1If either V or V are operating at 1.8 V nominal, f is constrained to 80 MHz. DDEXT DDMEM SCLK 2f must be less than or equal to f and is subject to additional restrictions for SDRAM interface operation. See Table37 on Page47. SCLK CCLK Rev. D | Page 29 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 OPERATING CONDITIONS FOR ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS Parameter Conditions Min Nominal Max Unit V Internal Supply Voltage1 Nonautomotive models2 0.95 1.26 V DDINT V Internal Supply Voltage1 Automotive 533 MHz models3 1.093 1.15 1.26 V DDINT V Internal Supply Voltage1 Automotive 400 MHz models3 1.045 1.10 1.20 V DDINT V External Supply Voltage4,5 Nonautomotive models, 1.7 1.8 1.9 V DDEXT Internal Voltage Regulator Disabled V External Supply Voltage4,5 Nonautomotive models 2.25 2.5 2.75 V DDEXT V External Supply Voltage4,5 Nonautomotive models 3 3.3 3.6 V DDEXT V External Supply Voltage4,5 Automotive models 2.7 3.3 3.6 V DDEXT V RTC Power Supply Voltage6 Nonautomotive models 2.25 3.6 V DDRTC V RTC Power Supply Voltage6 Automotive models 2.7 3.3 3.6 V DDRTC V MEM Supply Voltage4,7 Nonautomotive models 1.7 1.8 1.9 V DDMEM V MEM Supply Voltage4,7 Nonautomotive models 2.25 2.5 2.75 V DDMEM V MEM Supply Voltage4,7 Nonautomotive models 3 3.3 3.6 V DDMEM V MEM Supply Voltage4,7 Automotive models 2.7 3.3 3.6 V DDMEM V OTP Supply Voltage4 2.25 2.5 2.75 V DDOTP V OTP Programming Voltage4 2.25 2.5 2.75 V PPOTP V USB Supply Voltage8 3.0 3.3 3.6 V DDUSB V High Level Input Voltage9,10 V /V = 1.90 V 1.1 V IH DDEXT DDMEM V High Level Input Voltage10,11 V /V = 2.75 V 1.7 V IH DDEXT DDMEM V High Level Input Voltage10,11 V /V = 3.6 V 2.0 V IH DDEXT DDMEM V High Level Input Voltage12 V = 1.90 V/2.75 V/3.6 V 0.7 × V V V IHTWI DDEXT BUSTWI BUSTWI V Low Level Input Voltage9,10 V /V = 1.7 V 0.6 V IL DDEXT DDMEM V Low Level Input Voltage10,11 V /V = 2.25 V 0.7 V IL DDEXT DDMEM V Low Level Input Voltage10,11 V /V = 3.0 V 0.8 V IL DDEXT DDMEM V Low Level Input Voltage V = Minimum 0.3 × V 13 V ILTWI DDEXT BUSTWI T Junction Temperature 289-Ball CSP_BGA 0 +105 °C J @T =0°C to +70°C AMBIENT T Junction Temperature 289-Ball CSP_BGA –40 +105 °C J @T =–40°C to +70°C AMBIENT T Junction Temperature 208-Ball CSP_BGA 0 +105 °C J @T =0°C to +70°C AMBIENT T Junction Temperature 208-Ball CSP_BGA –40 +105 °C J @T =–40°C to +85°C AMBIENT 1The voltage regulator can generate V at levels of 1.00 V to 1.20 V with –5% to +5% tolerance when VRCTL is programmed with the bfrom_SysControl() API. This DDINT specification is only guaranteed when the API is used. 2See Ordering Guide on Page88. 3See Automotive Products on Page87. 4Must remain powered (even if the associated function is not used). 5V is the supply to the voltage regulator and GPIO. DDEXT 6If not used, power with V . DDEXT 7Balls that use V are DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AOE, AMS3–0, ARDY, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These balls are not tolerant DDMEM to voltages higher than V . DDMEM 8When not using the USB peripheral on the ADSP-BF525/ADSP-BF527 or terminating V on the ADSP-BF523, V must be powered by V . DDUSB DDUSB DDEXT 9Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF52x processors are 2.5 V tolerant (always accept up to 2.7 V maximum V ). Voltage compliance (on outputs, V ) is limited by the V supply voltage. IH OH DDEXT 10Parameter value applies to all input and bidirectional balls, except USB_DP, USB_DM, USB_VBUS, SDA, and SCL. 11Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF52x processors are 3.3 V tolerant (always accept up to 3.6 V maximum V ). Voltage compliance (on outputs, V ) is limited by the V supply voltage. IH OH DDEXT 12The V min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See V min and max values in Table11 on Page29. IHTWI BUSTWI 13SDA and SCL are pulled up to V . See Table11 on Page29. BUSTWI Rev. D | Page 30 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Clock Related Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527Processors Table15 describes the core clock timing requirements for the Use the nominal voltage setting (Table15) for internal and ADSP-BF523/ADSP-BF525/ADSP-BF527 processors. Take care external regulators. in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock (see Table17). Table16 describes phase-locked loop operating conditions. Table 15. Core Clock (CCLK) Requirements (All Instruction Rates1) for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Parameter Nominal Voltage Setting Max Unit f Core Clock Frequency (V =1.14 V minimum) 1.20 V 6002 MHz CCLK DDINT f Core Clock Frequency (V =1.093 V minimum) 1.15 V 5333 MHz CCLK DDINT f Core Clock Frequency (V = 1.045 V minimum)4 1.10 V 400 MHz CCLK DDINT f Core Clock Frequency (V = 0.95 V minimum) 1.0 V 400 MHz CCLK DDINT 1See the Ordering Guide on Page88. 2Applies to 600 MHz models only. See the Ordering Guide on Page88. 3Applies to 533 MHz and 600 MHz models only. See the Ordering Guide on Page88. 4Applies only to automotive products. See Automotive Products on Page87. Table 16. Phase-Locked Loop Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Parameter Min Max Unit f Voltage Controlled Oscillator (VCO) Frequency 60 Instruction Rate1 MHz VCO (Commercial/Industrial Models) f Voltage Controlled Oscillator (VCO) Frequency 70 Instruction Rate1 MHz VCO (Automotive Models) 1See the Ordering Guide on Page88. Table 17. SCLK Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors V /V V /V DDEXT DDMEM DDEXT DDMEM 1.8 V Nominal1 2.5 V or 3.3 V Nominal Parameter Max Max Unit f CLKOUT/SCLK Frequency (V ≥ 1.14 V)2 100 1333 MHz SCLK DDINT f CLKOUT/SCLK Frequency (V < 1.14 V)2 100 100 MHz SCLK DDINT 1If either V or V are operating at 1.8 V nominal, f is constrained to 100 MHz. DDEXT DDMEM SCLK 2f must be less than or equal to f and is subject to additional restrictions for SDRAM interface operation. See Table38 on Page47. SCLK CCLK 3Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table38 on Page47. Rev. D | Page 31 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ELECTRICAL CHARACTERISTICS Table 18. Common Electrical Characteristics for All ADSP-BF52x Processors Parameter Test Conditions Min Typical Max Unit V High Level Output Voltage V /V = 1.7 V, 1.35 V OH DDEXT DDMEM I =–0.5mA OH V High Level Output Voltage V /V = 2.25 V, 2.0 V OH DDEXT DDMEM I =–0.5mA OH V High Level Output Voltage V /V = 3.0 V, 2.4 V OH DDEXT DDMEM I =–0.5mA OH V Low Level Output Voltage V /V = 1.7 V/2.25 V/ 0.4 V OL DDEXT DDMEM 3.0V, I =2.0mA OL I High Level Input Current1 V /V =3.6 V, 10.0 μA IH DDEXT DDMEM V =3.6V IN I Low Level Input Current1 V /V =3.6 V, V = 0 V 10.0 μA IL DDEXT DDMEM IN I High Level Input Current JTAG2V = 3.6 V, V = 3.6 V 75.0 μA IHP DDEXT IN I Three-State Leakage Current3 V /V = 3.6 V, 10.0 μA OZH DDEXT DDMEM V =3.6V IN I Three-State Leakage Current4 V =3.0 V, V = 5.5 V 10.0 μA OZHTWI DDEXT IN I Three-State Leakage Current3 V /V = 3.6 V, V = 0 V 10.0 μA OZL DDEXT DDMEM IN C Input Capacitance5,6 f = 1 MHz, T = 25°C, 5 8 pF IN IN AMBIENT V =2.5V IN C Input Capacitance4,6 f = 1 MHz, T = 25°C, 15 pF INTWI IN AMBIENT V =2.5V IN 1Applies to input balls. 2Applies to JTAG input balls (TCK, TDI, TMS, TRST). 3Applies to three-statable balls. 4Applies to bidirectional balls SCL and SDA. 5Applies to all signal balls, except SCL and SDA. 6Guaranteed, but not tested. Rev. D | Page 32 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 19. Electrical Characteristics for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Parameter Test Conditions Min Typical Max Unit I 1 V Current in V = 1.3 V, f = 0 MHz, f =0MHz, 2 mA DDDEEPSLEEP DDINT DDINT CCLK SCLK Deep Sleep Mode T= 25°C, ASF=0.00 J I V Current in V = 1.3 V, f = 25 MHz, T= 25°C 13 mA DDSLEEP DDINT DDINT SCLK J Sleep Mode I V Current in V = 1.3 V, f = 300 MHz, f = 25 MHz, 44 mA DD-IDLE DDINT DDINT CCLK SCLK Idle T= 25°C, ASF = 0.4 J I V Current V = 1.3 V, f = 300 MHz, f = 25 MHz, 83 mA DD-TYP DDINT DDINT CCLK SCLK T= 25°C, ASF = 1.00 J I V Current V = 1.4 V, f = 400 MHz, f = 25 MHz, 114 mA DD-TYP DDINT DDINT CCLK SCLK T= 25°C, ASF = 1.00 J I 1, 2 Hibernate State V =V =V =V =3.30V, 40 μA DDHIBERNATE DDEXT DDMEM DDRTC DDUSB Current V =V =2.5V, T =25°C, CLKIN=0MHz DDOTP PPOTP J withvoltage regulator off (V = 0V) DDINT I V Current V = 3.3 V, T = 25°C 20 μA DDRTC DDRTC DDRTC J I V Current in V = 3.3 V, T = 25°C, Full Speed USB Transmit 9 mA DDUSB-FS DDUSB DDUSB J Full/Low Speed Mode I V Current in V = 3.3 V, T = 25°C, High Speed USB Transmit 25 mA DDUSB-HS DDUSB DDUSB J High Speed Mode I 1, 3 V Current in f = 0 MHz, f > 0 MHz Table22 + mA4 DDSLEEP DDINIT CCLK SCLK Sleep Mode (0.52 × V × f )4 DDINT SCLK I 1, 3 V Current in f = 0 MHz, f = 0 MHz Table22 mA DDDEEPSLEEP DDINT CCLK SCLK Deep Sleep Mode I 3, 5 V Current f > 0 MHz, f ≥ 0 MHz Table22 + mA DDINT DDINT CCLK SCLK (Table23 × ASF) + (0.52 × V × f ) DDINT SCLK I V Current V = 2.5 V, T = 25°C, OTPMemory Read 2 mA DDOTP DDOTP DDOTP J I V Current V = 2.5 V, T = 25°C, OTPMemory Write 2 mA DDOTP DDOTP DDOTP J I V Current V = 2.5 V, T = 25°C, OTPMemory Read 100 μA PPOTP PPOTP PPOTP J I V Current V = see Table30, T =25°C, OTPMemory 3 mA PPOTP PPOTP PPOTP J Write 1See the ADSP-BF52x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes. 2Includes current on V , V , V , V , and V supplies. Clock inputs are tied high or low. DDEXT DDUSB DDMEM DDOTP PPOTP 3Guaranteed maximum specifications. 4Unit for V is V (Volts). Unit for f is MHz. Example: 1.4V, 75MHz would be 0.52 × 1.4 × 75 = 54.6 mA adder. DDINT SCLK 5See Table21 for the list of I power vectors covered. DDINT Rev. D | Page 33 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 20. Electrical Characteristics for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Parameter Test Conditions Min Typical Max Unit I 1 V Current in V = 1.0 V, f = 0 MHz, f =0MHz, 10 mA DDDEEPSLEEP DDINT DDINT CCLK SCLK Deep Sleep Mode T = 25°C, ASF=0.00 J I V Current in V = 1.0 V, f = 25 MHz, T = 25°C 20 mA DDSLEEP DDINT DDINT SCLK J Sleep Mode I V Current in V = 1.0 V, f = 400 MHz, f = 25 MHz, 53 mA DD-IDLE DDINT DDINT CCLK SCLK Idle T= 25°C, ASF = 0.44 J I V Current V = 1.0 V, f = 400 MHz, f = 25 MHz, 94 mA DD-TYP DDINT DDINT CCLK SCLK T = 25°C, ASF = 1.00 J I V Current V = 1.15 V, f = 533 MHz, f = 25 MHz, 144 mA DD-TYP DDINT DDINT CCLK SCLK T = 25°C, ASF = 1.00 J I V Current V = 1.2 V, f = 600 MHz, f = 25 MHz, 170 mA DD-TYP DDINT DDINT CCLK SCLK T = 25°C, ASF = 1.00 J I 1, 2 Hibernate State V =V =V = V =3.30V, 40 μA DDHIBERNATE DDEXT DDMEM DDRTC DDUSB Current V =V =2.5V, T =25°C, CLKIN=0MHz DDOTP PPOTP J withvoltage regulator off (V = 0 V) DDINT I V Current V = 3.3 V, T = 25°C 20 μA DDRTC DDRTC DDRTC J I V Current in V = 3.3 V, T = 25°C, FullSpeed USB Transmit 9 mA DDUSB-FS DDUSB DDUSB J Full/Low Speed Mode I V Current in V = 3.3 V, T = 25°C, HighSpeed USB 25 mA DDUSB-HS DDUSB DDUSB J High Speed Mode Transmit I 1, 3 V Current in f = 0 MHz, f > 0 MHz Table24 + (0.61 × mA4 DDSLEEP DDINT CCLK SCLK Sleep Mode V × f )4 DDINT SCLK I 1, 3 V Current in f = 0 MHz, f = 0 MHz Table24 mA DDDEEPSLEEP DDINT CCLK SCLK Deep Sleep Mode I 3, 5 V Current f > 0 MHz, f ≥ 0 MHz Table24 + (Table25 mA DDINT DDINT CCLK SCLK × ASF) + (0.61 × V DDINT × f ) SCLK I V Current V = 2.5 V, T = 25°C, OTPMemory Read 1 mA DDOTP DDOTP DDOTP J I V Current V = 2.5 V, T = 25°C, OTPMemory Write 25 mA DDOTP DDOTP DDOTP J I V Current V = 2.5 V, T = 25°C, OTPMemory Read 0 mA PPOTP PPOTP PPOTP J I V Current V = 2.5 V, T =25°C, OTPMemory Write 0 mA PPOTP PPOTP PPOTP J 1See the ADSP-BF52x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes. 2Includes current on V , V , V , V , and V supplies. Clock inputs are tied high or low. DDEXT DDUSB DDMEM DDOTP PPOTP 3Guaranteed maximum specifications. 4Unit for V is V (Volts). Unit for f is MHz. Example: 1.2V, 75MHz would be 0.61 × 1.2 × 75 = 54.9 mA adder. DDINT SCLK 5See Table21 for the list of I power vectors covered. DDINT Rev. D | Page 34 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Total Power Dissipation Total power dissipation has two components: The ASF is combined with the CCLK Frequency and V DDINT dependent data in Table23 or Table25 to calculate this part. 1.Static, including leakage current The second part is due to transistor switching in the system 2.Dynamic, due to transistor switching characteristics clock (SCLK) domain, which is included in the I specifica- DDINT Many operating conditions can also affect power dissipation, tion equation. including temperature, voltage, operating frequency, and pro- cessor activity. Electrical Characteristics on Page32 shows the Table 21. Activity Scaling Factors (ASF)1 current dissipation for internal circuitry (V ). I DDINT DDDEEPSLEEP I Power Vector Activity Scaling Factor (ASF) specifies static power dissipation as a function of voltage DDINT (VDDINT) and temperature (see Table22 or Table24), and IDDINT IDD-PEAK 1.29 specifies the total power specification for the listed test condi- I 1.26 DD-HIGH tions, including the dynamic component as a function of voltage I 1.00 DD-TYP (V ) and frequency (Table23 or Table25). DDINT I 0.88 DD-APP There are two parts to the dynamic component. The first part is I 0.72 DD-NOP due to transistor switching in the core clock (CCLK) domain. I 0.44 This part is subject to an Activity Scaling Factor (ASF) which DD-IDLE represents application code running on the processor core and 1See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors (EE-297). The power vector information also applies to the ADSP-BF52x L1 memories (Table21). processors. Table 22. Static Current — I (mA) for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors DD-DEEPSLEEP Voltage (V )1 DDINT TJ (°C)1 1.2 V 1.25 V 1.3 V 1.35 V 1.4 V 1.45 V 1.5 V –40 1.47 1.42 1.50 1.64 1.85 2.12 2.09 –20 1.67 1.81 1.89 1.95 2.01 2.07 2.12 0 1.97 2.07 2.15 2.22 2.30 2.39 2.47 25 2.49 2.66 2.79 2.92 3.07 3.20 3.36 40 3.12 3.37 3.57 3.75 3.96 4.18 4.40 55 4.07 4.47 4.82 5.11 5.41 5.73 6.06 70 5.77 6.28 6.71 7.17 7.61 8.09 8.60 85 8.32 8.88 9.56 10.25 10.94 11.63 12.36 100 12.11 12.93 13.94 14.76 15.76 16.77 17.83 105 13.78 14.72 15.74 16.81 17.91 19.06 20.27 1Valid temperature and voltage ranges are model-specific. See Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors on Page28. Table 23. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1 for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors f Voltage (V )2 CCLK DDINT (MHz)2 1.2 V 1.25 V 1.3 V 1.35 V 1.4 V 1.45 V 1.5 V 400 N/A N/A 91.41 95.7 100.11 104.51 109.01 350 N/A N/A 80.56 84.37 88.26 92.17 96.17 300 63.31 66.51 69.78 73.09 76.51 79.93 83.42 250 53.36 56.10 58.88 61.72 64.64 67.56 70.55 200 43.49 45.76 48.08 50.44 52.86 55.28 57.77 100 23.6 24.93 26.29 27.68 29.12 30.56 32.04 1The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page32. 2Valid frequency and voltage ranges are model-specific. See Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors on Page28. Rev. D | Page 35 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 24. Static Current — I (mA) for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors DD-DEEPSLEEP Voltage (V )1 DDINT TJ (°C)1 0.95 V 1.00 V 1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V –40 6.5 7.8 9.3 11.1 13.1 15.4 18.0 21.0 –20 9.0 10.6 12.4 14.6 17.0 19.8 22.9 26.4 0 13.2 15.2 17.7 20.4 23.5 27.0 30.9 35.3 25 22.3 25.4 28.9 32.8 37.2 42.1 47.6 53.7 40 30.8 34.8 39.2 44.1 49.6 55.7 62.5 70.0 55 42.9 47.9 53.6 59.9 66.9 74.6 83.2 92.6 70 59.1 65.6 72.9 80.8 89.7 99.4 110.2 122.0 85 80.4 88.6 97.9 107.8 119.2 131.5 145.1 159.8 100 109.3 118.7 130.5 143.2 157.4 172.8 189.7 208.1 105 120.8 132.1 144.7 158.8 174.2 190.9 209.3 229.2 115 144.4 157.5 172.3 188.4 206.0 225.3 246.4 269.2 125 173.9 189.1 206.4 224.9 245.4 267.8 292.2 318.7 1Valid temperature and voltage ranges are model-specific. See Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors on Page30. Table 25. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1 for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors f Voltage (V )2 CCLK DDINT (MHz)2 0.95 V 1.00 V 1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 600 N/A N/A N/A N/A 130.4 137.6 145.1 152.5 533 N/A N/A N/A 110.3 116.7 123.3 129.8 136.4 500 N/A N/A 97.3 103.1 109.1 115.0 121.3 127.7 400 69.8 74.3 78.9 83.6 88.5 93.5 98.6 103.9 300 53.4 56.9 60.4 64.1 68.0 71.8 75.8 80.0 200 36.9 39.4 41.9 44.6 47.4 50.1 53.0 56.0 100 20.5 22.0 23.6 25.3 27.0 28.8 30.6 32.5 1The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page32. 2Valid frequency and voltage ranges are model-specific. See Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors on Page30. Rev. D | Page 36 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ABSOLUTE MAXIMUM RATINGS tions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum Stresses greater than those listed in Table26 may cause perma- rating conditions for extended periods may affect device nent damage to the device. These are stress ratings only. reliability. Functional operation of the device at these or any other condi- Table 26. Absolute Maximum Ratings Parameter Rating Internal Supply Voltage (V ) forADSP-BF523/ADSP-BF525/ADSP-BF527 processors –0.3 V to +1.26 V DDINT Internal Supply Voltage (V ) forADSP-BF522/ADSP-BF524/ADSP-BF526 processors –0.3 V to +1.47 V DDINT External (I/O) Supply Voltage (V /V ) –0.3 V to +3.8 V DDEXT DDMEM Real-Time Clock Supply Voltage (V ) –0.5 V to +3.8 V DDRTC OTP Supply Voltage (V ) –0.5 V to +3.0 V DDOTP OTP Programming Voltage (V )1 –0.5 V to +3.0 V PPOTP OTP Programming Voltage (V )2 –0.5 V to +7.1 V PPOTP USB PHY Supply Voltage (V ) –0.5 V to +3.8 V DDUSB Input Voltage3, 4, 5 –0.5 V to +3.8 V Input Voltage3, 4, 6 –0.5 V to +5.5 V Input Voltage3, 4, 7 –0.5 V to +5.25 V Output Voltage Swing –0.5 V toV /V + 0.5 V DDEXT DDMEM I /I Current per Pin Group3, 8 82mA (max) OH OL Storage Temperature Range –65°C to +150°C Junction Temperature While Biased +110°C 1Applies to OTP memory reads and writes for ADSP-BF523/ADSP-BF525/ADSP-BF527 processors and to OTP memory reads for ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. 2Applies only to OTP memory writes for ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. 3Applies to 100% transient duty cycle. 4Applies only when V is within specifications. When V is outside specifications, the range is V ±0.2 V. DDEXT DDEXT DDEXT 5For other duty cycles see Table27. 6Applies to balls SCL and SDA. 7Applies to balls USB_DP, USB_DM, and USB_VBUS. 8For pin group information, see Table28. For other duty cycles see Table29. Table 27. Maximum Duty Cycle for Input Transient Volt- Table26 specifies the maximum total source/sink (I /I ) cur- OH OL age1, 2 rent for a group of pins. Permanent damage can occur if this value is exceeded. To understand this specification, if pins PH4, Maximum Duty Cycle3 VIN Min (V)4 VIN Max (V)6 PH3, PH2, PH1, and PH0 from group 1 in Table28 were sourc- 100% –0.50 +3.80 ing or sinking 2mA each, the total current for those pins would be 10mA. This would allow up to 72mA total that could be 40% –0.70 +4.00 sourced or sunk by the remaining pins in the group without 25% –0.80 +4.10 damaging the device. For a list of all groups and their pins, see 15% –0.90 +4.20 the Table28 table. For duty cycles that are less than 100%, see 10% –1.00 +4.30 Table29. Note that the VOH and VOL specifications have separate per-pin maximum current requirements (see Table19 on 1Applies to all signal balls with the exception of CLKIN, XTAL, VROUT/ Page33 and Table20 on Page34). EXT_WAKE1, SCL, SDA, USB_DP, USB_DM, and USB_VBUS. 2Applies only when V is within specifications. When V is outside specifi- DDEXT DDEXT cations, the range is V ±0.2 V. Table 28. Total Current Pin Groups DDEXT 3Duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. The is equivalent to the measured duration of a single instance of overshoot Group Pins in Group or undershoot as a percentage of the period of occurrence. 1 PH4, PH3, PH2, PH1, PH0, PF15, PF14, PF13 4The individual values cannot be combined for analysis of a single instance of overshoot or undershoot. The worst case observed value must fall within one of the 2 PF12, SDA, SCL, PF11, PF10, PF9, PF8, PF7 voltages specified, and the total duration of the overshoot or undershoot (exceeding 3 PF6, PF5, PF4, PF3, PF2, PF1, PF0, PPI_FS1 the 100% case) must be less than or equal to the corresponding duty cycle. 4 PPI_CLK, PG15, PG14, PG13, PG12, PG11, PG10, PG9 5 PG8, PG7, PG6, PG5, PG4, BMODE3, BMODE2, BMODE1 Rev. D | Page 37 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 28. Total Current Pin Groups (Continued) PACKAGE INFORMATION Group Pins in Group The information presented in Figure8 and Table31 provides details about the package branding for the ADSP-BF52x proces- 6 BMODE0, PG3, PG2, PG1, PG0, TDI, TDO, EMU sors. For a complete listing of product availability, see Ordering 7 TCK, TRST, TMS Guide on Page88. 8 PH12, PH11, PH10, PH9, PH8, PH7, PH6, PH5 9 PH15, PH14, PH13, CLKBUF, NMI, RESET a 10 DATA15, DATA14, DATA13, DATA12, DATA11, DATA10 11 DATA9, DATA8, DATA7, DATA6, DATA5, DATA4 ADSP-BF52x 12 DATA3, DATA2, DATA1, DATA0, ADDR19, ADDR18 tppZccc 13 ADDR17, ADDR16, ADDR15, ADDR14, ADDR13 vvvvvv.xn.n 14 ADDR12, ADDR11, ADDR10, ADDR9, ADDR8, ADDR7 #yyww country_of_origin B 15 ADDR6, ADDR5, ADDR4, ADDR3, ADDR2, ADDR1 16 ABE1, ABE0, SA10, SWE, SCAS, SRAS Figure 8. Product Information on Package 17 SMS, SCKE, ARDY, AWE, ARE, AOE 18 AMS3, AMS2, AMS1, AMS0, CLKOUT Table 31. Package Brand Information1 Table 29. Maximum Duty Cycle for IOH/IOL Current Per Pin Brand Key Field Description Group ADSP-BF52x Product Name2 Maximum Duty Cycle RMS Current (mA) t Temperature Range 100% 82 pp Package Type 80% 92 Z Lead Free Option 60% 106 ccc See Ordering Guide 40% 130 vvvvvv.x Assembly Lot Code 25% 165 n.n Silicon Revision 10% 261 # RoHS Compliance Designator yyww Date Code When programming OTP memory on the ADSP-BF522/ 1Non Automotive only. For branding information specific to Automotive ADSP-BF524/ADSP-BF526 processors, the VPPOTP ball must products, contact Analog Devices Inc. be set to the write value specified in the Operating Conditions 2See product names in the Ordering Guide on Page88. for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors on Page28. There is a finite amount of cumulative time that the ESD SENSITIVITY write voltage may be applied (dependent on voltage and junc- tion temperature) to VPPOTP over the lifetime of the part. Therefore, maximum OTP memory programming time for the ADSP-BF522/ADSP-BF524/ADSP-BF526 processors is shown ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge in Table30. The ADSP-BF523/ADSP-BF525/ADSP-BF527 pro- without detection. Although this product features cessors do not have a similar restriction. patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Table 30. Maximum OTP Memory Programming Time for Therefore, proper ESD precautions should be taken to ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors avoid performance degradation or loss of functionality. Temperature (T) J V Voltage (V) 25°C 85°C 105°C PPOTP 6.9 6000 sec 100 sec 25 sec 7.0 2400 sec 44 sec 12 sec 7.1 1000 sec 18 sec 4.5 sec Rev. D | Page 38 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 TIMING SPECIFICATIONS Specifications are subject to change without notice. Clock and Reset Timing Table32 and Figure9 describe clock and reset operations. Per the CCLK and SCLK timing specifications in Table12 to Table17, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of the processor's maximum instruction rate. Table 32. Clock and Reset Timing Parameter Min Max Unit Timing Requirements f CLKIN Frequency (Commercial/ Industrial Models) 1, 2, 3, 4 12 50 MHz CKIN CLKIN Frequency (Automotive Models) 1, 2, 3, 4 14 50 MHz t CLKIN Low Pulse1 10 ns CKINL t CLKIN High Pulse1 10 ns CKINH t RESET Asserted Pulse Width Low5 11 × t ns WRST CKIN Switching Characteristic t CLKIN to CLKBUF Delay 10 ns BUFDLAY 1Applies to PLL bypass mode and PLL nonbypass mode. 2Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f , f , and f settings discussed in Table12 on Page29 through VCO CCLK SCLK Table14 on Page29 and Table15 on Page31 through Table17 on Page31. 3The t period (see Figure9) equals 1/f . CKIN CKIN 4If the DF bit in the PLL_CTL register is set, the minimum f specification is 24MHz for commercial/industrial models and 28MHz for automotive models. CKIN 5Applies after power-up sequence is complete. See Table33 and Figure10 for power-up reset timing. t CKIN CLKIN t t t BUFDLAY CKINL CKINH t BUFDLAY CLKBUF t WRST RESET Figure 9. Clock and Reset Timing Rev. D | Page 39 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 33. Power-Up Reset Timing Parameter Min Max Unit Timing Requirement t RESET Deasserted after the V , V , V , V , V , V , and CLKIN 3500 × t ns RST_IN_PWR DDINT DDEXT DDRTC DDUSB DDMEM DDOTP CKIN Pins are Stable and Within Specification t RST_IN_PWR RESET CLKIN V DD_SUPPLIES In Figure10, V is V , V , V , V , V , and V . DD_SUPPLIES DDINT DDEXT DDRTC DDUSB DDMEM DDOTP Figure 10. Power-Up Reset Timing Rev. D | Page 40 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Asynchronous Memory Read Cycle Timing Table 34. Asynchronous Memory Read Cycle Timing ADSP-BF522/ADSP-BF524/ ADSP-BF523/ADSP-BF525/ ADSP-BF526 ADSP-BF527 V V V V DDMEM DDMEM DDMEM DDMEM 1.8 V Nominal 2.5 V or 3.3 V 1.8 V Nominal 2.5 V or 3.3 V Nominal Nominal Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements t DATA15–0 Setup Before CLKOUT 2.1 2.1 2.1 2.1 ns SDAT t DATA15–0 Hold After CLKOUT 1.2 0.8 0.9 0.8 ns HDAT t ARDY Setup Before CLKOUT 4.0 4.0 4.0 4.0 ns SARDY t ARDY Hold After CLKOUT 0.2 0.2 0.2 0.2 ns HARDY Switching Characteristics t Output Delay After CLKOUT1 6.0 6.0 6.0 6.0 ns DO t Output Hold After CLKOUT1 0.8 0.8 0.8 0.8 ns HO 1Output balls include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE. SETUP PROGRAMMED READ ACCESS EXTENDED HOLD 2 CYCLES ACCESS 4 CYCLES 3 CYCLES 1 CYCLE CLKOUT t t DO HO AMSx ABE1–0 ADDR19–1 AOE t t DO HO ARE t t SARDY HARDY ARDY t t SARDY SDAT t t HARDY HDAT DATA 15–0 Figure 11. Asynchronous Memory Read Cycle Timing Rev. D | Page 41 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Asynchronous Memory Write Cycle Timing Table 35. Asynchronous Memory Write Cycle Timing ADSP-BF522/ADSP-BF524/ ADSP-BF523/ADSP-BF525/ ADSP-BF526 ADSP-BF527 V V V V DDMEM DDMEM DDMEM DDMEM 1.8 V Nominal 2.5 V or 3.3 V 1.8 V Nominal 2.5 V or 3.3 V Nominal Nominal Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements t ARDY Setup Before CLKOUT 4.0 4.0 4.0 4.0 ns SARDY t ARDY Hold After CLKOUT 0.2 0.2 0.2 0.2 ns HARDY Switching Characteristics t DATA15–0 Disable After CLKOUT 6.0 6.0 6.0 6.0 ns DDAT t DATA15–0 Enable After CLKOUT 0.0 0.0 0.0 0.0 ns ENDAT t Output Delay After CLKOUT1 6.0 6.0 6.0 6.0 ns DO t Output Hold After CLKOUT1 0.8 0.8 0.8 0.8 ns HO 1Output balls include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AWE. PROGRAMMED WRITE ACCESS SETUP ACCESS EXTEND HOLD 2 CYCLES 2 CYCLES 1 CYCLE1 CYCLE CLKOUT t t DO HO AMSx ABE1–0 ADDR19–1 t t DO HO AWE t SARDY t HARDY ARDY t t t ENDAT t HARDY DDAT SARDY DATA 15–0 Figure 12. Asynchronous Memory Write Cycle Timing Rev. D | Page 42 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 NAND Flash Controller Interface Timing Table36 and Figure13 on Page44 through Figure17 on Page46 describe NAND Flash Controller Interface operations. Table 36. NAND Flash Controller Interface Timing V V DDEXT DDEXT 1.8 V Nominal 2.5 V or 3.3 V Nominal Parameter Min Min Unit Write Cycle Switching Characteristics t ND_CE Setup Time to AWE Low 1.0 × t – 4 1.0 × t – 4 ns CWL SCLK SCLK t ND_CE Hold Time From AWE High 3.0 × t – 4 3.0 × t – 4 ns CH SCLK SCLK t ND_CLE Setup Time to AWE Low 0.0 0.0 ns CLEWL t ND_CLE Hold Time From AWE high 2.5 × t – 4 2.5 × t – 4 ns CLH SCLK SCLK t ND_ALE Setup Time to AWE Low 0.0 0.0 ns ALEWL t ND_ALE Hold Time From AWE High 2.5 × t – 4 2.5 × t – 4 ns ALH SCLK SCLK t 1 AWE Low to AWE high (WR_DLY +1.0) × t – 4 (WR_DLY +1.0) × t – 4 ns WP SCLK SCLK t AWE High to AWE Low 4.0 × t – 4 4.0 × t – 4 ns WHWL SCLK SCLK t 1 AWE Low to AWE Low (WR_DLY +5.0) × t – 4 (WR_DLY +5.0) × t – 4 ns WC SCLK SCLK t 1 Data Setup Time for a Write Access (WR_DLY +1.5) × t – 4 (WR_DLY +1.5) × t – 4 ns DWS SCLK SCLK t Data Hold Time for a Write Access 2.5 × t – 4 2.5 × t – 4 ns DWH SCLK SCLK Read Cycle Switching Characteristics t ND_CE Setup Time to ARE Low 1.0 × t – 4 1.0 × t – 4 ns CRL SCLK SCLK t ND_CE Hold Time From ARE High 3.0 × t – 4 3.0 × t – 4 ns CRH SCLK SCLK t 1 ARE Low to ARE High (RD_DLY +1.0) × t – 4 (RD_DLY +1.0) × t – 4 ns RP SCLK SCLK t ARE High to ARE Low 4.0 × t – 4 4.0 × t – 4 ns RHRL SCLK SCLK t 1 ARE Low to ARE Low (RD_DLY +5.0) × t – 4 (RD_DLY +5.0) × t – 4 ns RC SCLK SCLK Timing Requirements (ADSP-BF522/ADSP-BF524/ADSP-BF526) t Data Setup Time for a Read Transaction 14.0 10.0 ns DRS t Data Hold Time for a Read Transaction 0.0 0.0 ns DRH Timing Requirements (ADSP-BF523/ADSP-BF525/ADSP-BF527) t Data Setup Time for a Read Transaction 11.0 8.0 ns DRS t Data Hold Time for a Read Transaction 0.0 0.0 ns DRH Write Followed by Read Switching Characteristic t AWE High to ARE Low 5.0 × t – 4 5.0 × t – 4 ns WHRL SCLK SCLK 1WR_DLY and RD_DLY are defined in the NFC_CTL register. Rev. D | Page 43 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 t t CWL CH ND_CE ND_CLE t t CLEWL CLH t t ALEWL ALH ND_ALE t WP AWE t t DWH DWS ND_DATA In Figure13, ND_DATA is ND_D0–D7. Figure 13. NAND Flash Controller Interface Timing — Command Write Cycle t CWL ND_CE t CLEWL ND_CLE ND_ALE t t t ALH t ALH ALEWL ALEWL t t WP t WP WHWL AWE t WC t t t t DWS DWH DWS DWH ND_DATA In Figure14, ND_DATA is ND_D0–D7. Figure 14. NAND Flash Controller Interface Timing — Address Write Cycle Rev. D | Page 44 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 t CWL ND_CE t CLEWL ND_CLE t ALEWL ND_ALE t t WC WP AWE t t WP WHWL t t t t DWS DWH DWS DWH ND_DATA In Figure15, ND_DATA is ND_D0–D7. Figure 15. NAND Flash Controller Interface Timing — Data Write Operation t t CRL CRH ND_CE ND_CLE ND_ALE t t RP RC ARE t t RP RHRL t t t t DRS DRH DRS DRH ND_DATA In Figure16, ND_DATA is ND_D0–D7. Figure 16. NAND Flash Controller Interface Timing — Data Read Operation Rev. D | Page 45 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 t CLWL ND_CE ND_CLE t t CLEWL CLH t WP AWE t t WHRL RP ARE t t t t DWS DWH DRS DRH ND_DATA In Figure17, ND_DATA is ND_D0–D7. Figure 17. NAND Flash Controller Interface Timing — Write Followed by Read Operation Rev. D | Page 46 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 SDRAM Interface Timing Table 37. SDRAM Interface Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors V V DDMEM DDMEM 1.8V Nominal 2.5 V or 3.3V Nominal Parameter Min Max Min Max Unit Timing Requirements t Data Setup Before CLKOUT 1.5 1.5 ns SSDAT t Data Hold After CLKOUT 1.3 0.8 ns HSDAT Switching Characteristics t CLKOUT Period1 12.5 10 ns SCLK t CLKOUT Width High 5.0 4.0 ns SCLKH t CLKOUT Width Low 5.0 4.0 ns SCLKL t Command, Address, Data Delay After CLKOUT2 5.0 4.0 ns DCAD t Command, Address, Data Hold After CLKOUT2 1.0 1.0 ns HCAD t Data Disable After CLKOUT 5.5 5.0 ns DSDAT t Data Enable After CLKOUT 0.0 0.0 ns ENSDAT 1The t value is the inverse of the f specification discussed in Table14 and Table17. Package type and reduced supply voltages affect the best-case values listed here. SCLK SCLK 2Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. Table 38. SDRAM Interface Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors V V DDMEM DDMEM 1.8V Nominal 2.5 V or 3.3V Nominal Parameter Min Max Min Max Unit Timing Requirements t Data Setup Before CLKOUT 1.5 1.5 ns SSDAT t Data Hold After CLKOUT 1.0 0.8 ns HSDAT Switching Characteristics t CLKOUT Period1 10 7.5 ns SCLK t CLKOUT Width High 2.5 2.5 ns SCLKH t CLKOUT Width Low 2.5 2.5 ns SCLKL t Command, Address, Data Delay After CLKOUT2 4.0 4.0 ns DCAD t Command, Address, Data Hold After CLKOUT2 1.0 1.0 ns HCAD t Data Disable After CLKOUT 5.0 4.0 ns DSDAT t Data Enable After CLKOUT 0.0 0.0 ns ENSDAT 1The t value is the inverse of the f specification discussed in Table14 and Table17. Package type and reduced supply voltages affect the best-case values listed here. SCLK SCLK 2Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. Rev. D | Page 47 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 t SCLK CLKOUT t t t t SSDAT HSDAT SCLKL SCLKH DATA (IN) t t DCAD DSDAT t t ENSDAT HCAD DATA (OUT) t t DCAD HCAD COMMAND, ADDRESS (OUT) NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. Figure 18. SDRAM Interface Timing Rev. D | Page 48 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 External DMA Request Timing Table39, Table40, and Figure19 describe the External DMA Request operations. Table 39. External DMA Request Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors1 V /V V /V DDEXT DDMEM DDEXT DDMEM 1.8 V Nominal 2.5 V or 3.3 V Nominal Parameter Min Max Min Max Unit Timing Requirements t DMARx Asserted to CLKOUT High Setup 9.0 6.0 ns DS t CLKOUT High to DMARx Deasserted Hold Time 0.0 0.0 ns DH t DMARx Active Pulse Width 1.0 × t 1.0 × t ns DMARACT SCLK SCLK t DMARx Inactive Pulse Width 1.75 × t 1.75 × t ns DMARINACT SCLK SCLK 1Because the external DMA control pins are part of the V power domain and the CLKOUT signal is part of the V power domain, systems in which V and DDEXT DDMEM DDEXT V are NOT equal may require level shifting logic for correct operation. DDMEM Table 40. External DMA Request Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors1 V /V V /V DDEXT DDMEM DDEXT DDMEM 1.8 V Nominal 2.5 V or 3.3 V Nominal Parameter Min Max Min Max Unit Timing Requirements t DMARx Asserted to CLKOUT High Setup 8.0 6.0 ns DS t CLKOUT High to DMARx Deasserted Hold Time 0.0 0.0 ns DH t DMARx Active Pulse Width 1.0 × t 1.0 × t ns DMARACT SCLK SCLK t DMARx Inactive Pulse Width 1.75 × t 1.75 × t ns DMARINACT SCLK SCLK 1Because the external DMA control pins are part of the V power domain and the CLKOUT signal is part of the V power domain, systems in which V and DDEXT DDMEM DDEXT V are NOT equal may require level shifting logic for correct operation. DDMEM CLKOUT t t DS DH DMAR0/1 (ACTIVE LOW) t t DMARACT DMARINACT DMAR0/1 (ACTIVE HIGH) Figure 19. External DMA Request Timing Rev. D | Page 49 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Parallel Peripheral Interface Timing Table41 and Figure20 on Page51, Figure24 on Page55, and Figure27 on Page57 describe parallel peripheral interface operations. Table 41. Parallel Peripheral Interface Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors V V DDEXT DDEXT 1.8V Nominal 2.5 V or 3.3 V Nominal Parameter Min Max Min Max Unit Timing Requirements t PPI_CLK Width1 6.4 6.4 ns PCLKW t PPI_CLK Period1 25.0 20.0 ns PCLK Timing Requirements - GP Input and Frame Capture Modes t External Frame Sync Setup Before PPI_CLK 6.7 6.7 ns SFSPE (Nonsampling Edge for Rx, Sampling Edge for Tx) t External Frame Sync Hold After PPI_CLK 1.2 1.2 ns HFSPE t Receive Data Setup Before PPI_CLK 4.1 3.5 ns SDRPE t Receive Data Hold After PPI_CLK 2.0 1.6 ns HDRPE Switching Characteristics - GP Output and Frame Capture Modes t Internal Frame Sync Delay After PPI_CLK 8.0 8.0 ns DFSPE t Internal Frame Sync Hold After PPI_CLK 1.7 1.7 ns HOFSPE t Transmit Data Delay After PPI_CLK 8.2 8.0 ns DDTPE t Transmit Data Hold After PPI_CLK 2.3 1.9 ns HDTPE 1PPI_CLK frequency cannot exceed f /2. SCLK Table 42. Parallel Peripheral Interface Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors V V DDEXT DDEXT 1.8V Nominal 2.5 V or 3.3V Nominal Parameter Min Max Min Max Unit Timing Requirements t PPI_CLK Width1 6.0 6.0 ns PCLKW t PPI_CLK Period1 20.0 15.0 ns PCLK Timing Requirements - GP Input and Frame Capture Modes t External Frame Sync Setup Before PPI_CLK 6.7 6.7 ns SFSPE (Nonsampling Edge for Rx, Sampling Edge for Tx) t External Frame Sync Hold After PPI_CLK 1.0 1.0 ns HFSPE t Receive Data Setup Before PPI_CLK 3.5 3.5 ns SDRPE t Receive Data Hold After PPI_CLK 2.0 1.6 ns HDRPE Switching Characteristics - GP Output and Frame Capture Modes t Internal Frame Sync Delay After PPI_CLK 8.0 8.0 ns DFSPE t Internal Frame Sync Hold After PPI_CLK 1.7 1.7 ns HOFSPE t Transmit Data Delay After PPI_CLK 8.0 8.0 ns DDTPE t Transmit Data Hold After PPI_CLK 2.3 1.9 ns HDTPE 1PPI_CLK frequency cannot exceed f /2. SCLK Rev. D | Page 50 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 DATA SAMPLED / DATA SAMPLED / FRAME SYNC SAMPLED FRAME SYNC SAMPLED PPI_CLK t t t PCLKW SFSPE HFSPE t PCLK PPI_FS1/2 t t SDRPE HDRPE PPI_DATA Figure 20. PPI GP Rx Mode with External Frame Sync Timing DATA DRIVEN / FRAME SYNC SAMPLED PPI_CLK t t t SFSPE HFSPE PCLKW t PCLK PPI_FS1/2 t DDTPE t HDTPE PPI_DATA Figure 21. PPI GP Tx Mode with External Frame Sync Timing FRAME SYNC DATA DRIVEN SAMPLED PPI_CLK t t DFSPE PCLKW t t HOFSPE PCLK PPI_FS1/2 t t SDRPE HDRPE PPI_DATA Figure 22. PPI GP Rx Mode with Internal Frame Sync Timing Rev. D | Page 51 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 FRAME SYNC DATA DATA DRIVEN DRIVEN DRIVEN t PCLK PPI_CLK t t DFSPE PCLKW t HOFSPE PPI_FS1/2 t t DDTPE HDTPE PPI_DATA Figure 23. PPI GP Tx Mode with Internal Frame Sync Timing Rev. D | Page 52 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Serial Ports Table43 through Table47 on Page57 and Figure24 on Page55 through Figure27 on Page57 describe serial port operations. Table 43. Serial Ports—External Clock ADSP-BF522/ADSP-BF524/ ADSP-BF523/ADSP-BF525/ ADSP-BF526 ADSP-BF527 V V DDEXT DDEXT VDDEXT 2.5 V or 3.3V VDDEXT 2.5 V or 3.3V 1.8V Nominal Nominal 1.8V Nominal Nominal Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements t TFSx/RFSx Setup Before TSCLKx RSCLKx1 3.0 3.0 3.0 3.0 ns SFSE t TFSx/RFSx Hold After TSCLKx/RSCLKx1 3.0 3.0 3.0 3.0 ns HFSE t Receive Data Setup Before RSCLKx1 3.0 3.0 3.0 3.0 ns SDRE t Receive Data Hold After RSCLKx1 3.5 3.0 3.5 3.0 ns HDRE t TSCLKx/RSCLKx Width 7.0 4.5 7.0 4.5 ns SCLKEW t TSCLKx/RSCLKx Period 2.0 × t 2.0 × t 2.0 × t 2.0 × t ns SCLKE SCLK SCLK SCLK SCLK t Start-Up Delay From SPORT Enable To 4.0 × t 4.0 × t 4.0 × t 4.0 × t ns SUDTE SCLKE SCLKE SCLKE SCLKE First External TFSx2 t Start-Up Delay From SPORT Enable To 4.0 × t 4.0 × t 4.0 × t 4.0 × t ns SUDRE SCLKE SCLKE SCLKE SCLKE First External RFSx2 Switching Characteristics t TFSx/RFSx Delay After TSCLKx/RSCLKx 10.0 10.0 10.0 10.0 ns DFSE (Internally Generated TFSx/RFSx)3 t TFSx/RFSx Hold After TSCLKx/RSCLKx 0.0 0.0 0.0 0.0 ns HOFSE (Internally Generated TFSx/RFSx)3 t Transmit Data Delay After TSCLKx3 10.0 10.0 10.0 10.0 ns DDTE t Transmit Data Hold After TSCLKx3 0.0 0.0 0.0 0.0 ns HDTE 1Referenced to sample edge. 2Verified in design but untested. 3Referenced to drive edge. Rev. D | Page 53 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 44. Serial Ports—Internal Clock for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors V V DDEXT DDEXT 1.8V Nominal 2.5 V or 3.3V Nominal Parameter Min Max Min Max Unit Timing Requirements t TFSx/RFSx Setup Before TSCLKx/RSCLKx1 11.0 9.6 ns SFSI t TFSx/RFSx Hold After TSCLKx/RSCLKx1 –1.5 –1.5 ns HFSI t Receive Data Setup Before RSCLKx1 11.0 9.6 ns SDRI t Receive Data Hold After RSCLKx1 –1.5 –1.5 ns HDRI Switching Characteristics t TSCLKx/RSCLKx Width 10.0 8.0 ns SCLKIW t TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 3.0 3.0 ns DFSI t TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 –2.0 –1.0 ns HOFSI t Transmit Data Delay After TSCLKx2 3.0 3.0 ns DDTI t Transmit Data Hold After TSCLKx2 –1.8 –1.5 ns HDTI 1Referenced to sample edge. 2Referenced to drive edge. Table 45. Serial Ports—Internal Clock for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors V V DDEXT DDEXT 1.8V Nominal 2.5 V or 3.3V Nominal Parameter Min Max Min Max Unit Timing Requirements t TFSx/RFSx Setup Before TSCLKx/RSCLKx1 11.0 9.6 ns SFSI t TFSx/RFSx Hold After TSCLKx/RSCLKx1 –1.5 –1.5 ns HFSI t Receive Data Setup Before RSCLKx1 11.0 9.6 ns SDRI t Receive Data Hold After RSCLKx1 –1.5 –1.5 ns HDRI Switching Characteristics t TSCLKx/RSCLKx Width 4.5 4.5 ns SCLKIW t TFSx/RFSx Delay After TSCLKx/RSCLKx 3.0 3.0 ns DFSI (Internally Generated TFSx/RFSx)2 t TFSx/RFSx Hold After TSCLKx/RSCLKx –1.0 –1.0 ns HOFSI (Internally Generated TFSx/RFSx)2 t Transmit Data Delay After TSCLKx2 3.0 3.0 ns DDTI t Transmit Data Hold After TSCLKx2 –1.8 –1.5 ns HDTI 1Referenced to sample edge. 2Referenced to drive edge. Rev. D | Page 54 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 DATARECEIVE—INTERNALCLOCK DATARECEIVE—EXTERNALCLOCK DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE t t t SCLKE SCLKIW SCLKEW RSCLKx RSCLKx t t DFSI DFSE t t HOFSI HOFSE RFSx RFSx (OUTPUT) (OUTPUT) t t t t SFSI HFSI SFSE HFSE RFSx RFSx (INPUT) (INPUT) tSDRI tHDRI tSDRE tHDRE DRx DRx DATATRANSMIT—INTERNALCLOCK DATATRANSMIT—EXTERNALCLOCK DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE t SCLKE tSCLKIW tSCLKEW TSCLKx TSCLKx t t DFSI DFSE t t HOFSI HOFSE TFSx TFSx (OUTPUT) (OUTPUT) t t t t SFSI HFSI SFSE HFSE TFSx TFSx (INPUT) (INPUT) t t DDTI DDTE t t HDTI HDTE DTx DTx Figure 24. Serial Ports TSCLKx (INPUT) t SUDTE TFSx (INPUT) RSCLKx (INPUT) t SUDRE RFSx (INPUT) FIRST TSCLKx/RSCLKx EDGE AFTER SPORT ENABLED Figure 25. Serial Port Start Up with External Clock and Frame Sync Rev. D | Page 55 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 46. Serial Ports—Enable and Three-State ADSP-BF522/ADSP-BF524/ADSP-BF526 ADSP-BF523/ADSP-BF525/ADSP-BF527 V V V V DDEXT DDEXT DDEXT DDEXT 1.8V Nominal 2.5 V or 3.3V Nominal 1.8V Nominal 2.5 V or 3.3V Nominal Parameter Min Max Min Max Min Max Min Max Unit Switching Characteristics t Data Enable Delay from 0.0 0.0 0.0 0.0 ns DTENE External TSCLKx1 t Data Disable Delay from t +1 t +1 t +1 t +1 ns DDTTE SCLK SCLK SCLK SCLK External TSCLKx1 t Data Enable Delay from –2.0 –2.0 –2.0 –2.0 ns DTENI Internal TSCLKx1 t Data Disable Delay from t +1 t +1 t +1 t +1 ns DDTTI SCLK SCLK SCLK SCLK Internal TSCLKx1 1Referenced to drive edge. DRIVE EDGE DRIVE EDGE TSCLKx t t DTENE/I DDTTE/I DTx Figure 26. Serial Ports — Enable and Three-State Rev. D | Page 56 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 47. Serial Ports — External Late Frame Sync ADSP-BF522/ADSP-BF524/ ADSP-BF523/ADSP-BF525/ ADSP-BF526 ADSP-BF527 V V DDEXT DDEXT V 2.5 V or 3.3V V 2.5 V or 3.3V DDEXT DDEXT 1.8V Nominal Nominal 1.8V Nominal Nominal Parameter Min Max Min Max Min Max Min Max Unit Switching Characteristics t Data Delay from Late External TFSx 12.0 10.0 12.0 10.0 ns DDTLFSE or External RFSx in multi-channel mode with MFD = 01, 2 t Data Enable from External RFSx in multi- 0.0 0.0 0.0 0.0 ns DTENLFSE channel mode with MFD = 01, 2 1When in multi-channel mode, TFSx enable and TFSx valid follow t and t . DTENLFSE DDTLFSE 2If external RFSx/TFSx setup to RSCLKx/TSCLKx > t /2 then t and t apply, otherwise t and t apply. SCLKE DDTTE/I DTENE/I DDTLFSE DTENLFSE EXTERNAL RFSx IN MULTI-CHANNEL MODE DRIVE SAMPLE DRIVE EDGE EDGE EDGE RSCLKx RFSx t DDTLFSE t DTENLFSE DTx 1ST BIT LATE EXTERNAL TFSx DRIVE SAMPLE DRIVE EDGE EDGE EDGE TSCLKx TFSx t DDTLFSE DTx 1ST BIT Figure 27. Serial Ports — External Late Frame Sync Rev. D | Page 57 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Serial Peripheral Interface (SPI) Port—Master Timing Table48 and Figure28 describe SPI port master operations. Table 48. Serial Peripheral Interface (SPI) Port—Master Timing ADSP-BF522/ADSP-BF524/ ADSP-BF523/ADSP-BF525/ ADSP-BF526 ADSP-BF527 V V DDEXT DDEXT V 2.5 V or 3.3V V 2.5 V or 3.3V DDEXT DDEXT 1.8V Nominal Nominal 1.8V Nominal Nominal Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements t Data Input Valid to SCK Edge (Data 11.6 9.6 11.6 9.6 ns SSPIDM Input Setup) t SCK Sampling Edge to Data Input –1.5 –1.5 –1.5 –1.5 ns HSPIDM Invalid Switching Characteristics t SPISELx low to First SCK Edge 2 × t –1.5 2 × t –1.5 2 × t –1.5 2 × t –1.5 ns SDSCIM SCLK SCLK SCLK SCLK t Serial Clock High Period 2 × t –1.5 2 × t –1.5 2 × t –1.5 2 × t –1.5 ns SPICHM SCLK SCLK SCLK SCLK t Serial Clock Low Period 2 × t –1.5 2 × t –1.5 2 × t –1.5 2 × t –1.5 ns SPICLM SCLK SCLK SCLK SCLK t Serial Clock Period 4 × t –1.5 4 × t –1.5 4 × t –1.5 4 × t –1.5 ns SPICLK SCLK SCLK SCLK SCLK t Last SCK Edge to SPISELx High 2 × t –1.5 2 × t –1.5 2 × t –1.5 2 × t –1.5 ns HDSM SCLK SCLK SCLK SCLK t Sequential Transfer Delay 2 × t –1.5 2 × t –1.5 2 × t –1.5 2 × t –1.5 ns SPITDM SCLK SCLK SCLK SCLK t SCK Edge to Data Out Valid (Data 6 6 6 6 ns DDSPIDM Out Delay) t SCK Edge to Data Out Invalid (Data –1.0 –1.0 –1.0 –1.0 ns HDSPIDM Out Hold) SPIxSELy (OUTPUT) t t t SDSCIM SPICLM SPICHM t t t SPICLK HDSM SPITDM SPIxSCK (OUTPUT) t t HDSPIDM DDSPIDM SPIxMOSI (OUTPUT) t SSPIDM CPHA = 1 t HSPIDM SPIxMISO (INPUT) t t HDSPIDM DDSPIDM SPIxMOSI (OUTPUT) t t SSPIDM HSPIDM CPHA = 0 SPIxMISO (INPUT) Figure 28. Serial Peripheral Interface (SPI) Port—Master Timing Rev. D | Page 58 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Serial Peripheral Interface (SPI) Port—Slave Timing Table49 and Figure29 describe SPI port slave operations. Table 49. Serial Peripheral Interface (SPI) Port—Slave Timing ADSP-BF522/ADSP-BF524/ ADSP-BF523/ADSP-BF525/ ADSP-BF526 ADSP-BF527 V V DDEXT DDEXT V 2.5 V or 3.3V V 2.5 V or 3.3V DDEXT DDEXT 1.8V Nominal Nominal 1.8V Nominal Nominal Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements t Serial Clock High Period 2 × t –1.5 2 × t –1.5 2 × t –1.5 2 × t –1.5 ns SPICHS SCLK SCLK SCLK SCLK t Serial Clock Low Period 2 × t –1.5 2 × t –1.5 2 × t –1.5 2 × t –1.5 ns SPICLS SCLK SCLK SCLK SCLK t Serial Clock Period 4 × 4 × t –1.5 4 × 4 × t –1.5 ns SPICLK SCLK SCLK t –1.5 t –1.5 SCLK SCLK t Last SCK Edge to SPISS Not Asserted 2 × t –1.5 2 × t –1.5 2 × t –1.5 2 × t –1.5 ns HDS SCLK SCLK SCLK SCLK t Sequential Transfer Delay 2 × t –1.5 2 × t –1.5 2 × t –1.5 2 × t –1.5 ns SPITDS SCLK SCLK SCLK SCLK t SPISS Assertion to First SCK Edge 2 × t –1.5 2 × t –1.5 2 × t –1.5 2 × t –1.5 ns SDSCI SCLK SCLK SCLK SCLK t Data Input Valid to SCK Edge (Data Input 1.6 1.6 1.6 1.6 ns SSPID Setup) t SCK Sampling Edge to Data Input Invalid 2.0 1.6 1.6 1.6 ns HSPID Switching Characteristics t SPISS Assertion to Data Out Active 0 12.0 0 10.3 0 12.0 0 10.3 ns DSOE t SPISS Deassertion to Data High Impedance 0 11.0 0 8.5 0 8.5 0 8 ns DSDHI t SCK Edge to Data Out Valid (Data Out Delay) 10 10 10 10 ns DDSPID t SCK Edge to Data Out Invalid (Data Out Hold)0 0 0 0 ns HDSPID SPIxSS (INPUT) t t t SDSCI SPICLS SPICHS t t t SPICLK HDS SPITDS SPIxSCK (INPUT) t t DSOE DDSPID t t t HDSPID DDSPID DSDHI SPIxMISO (OUTPUT) CPHA = 1 t t SSPID HSPID SPIxMOSI (INPUT) t t t t DSOE HDSPID DDSPID DSDHI SPIxMISO (OUTPUT) t HSPID CPHA = 0 t SSPID SPIxMOSI (INPUT) Figure 29. Serial Peripheral Interface (SPI) Port—Slave Timing Rev. D | Page 59 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing Table50 describes the USB On-The-Go receive and transmit operations. Table 50. USB On-The-Go—Receive and Transmit Timing ADSP-BF522/ADSP-BF524/ADSP-BF526 ADSP-BF523/ADSP-BF525/ ADSP-BF527 V V V V DDEXT DDEXT DDEXT DDEXT 1.8V Nominal 2.5 V or 3.3V Nominal 1.8V Nominal 2.5 V or 3.3V Nominal Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements f USB_XI Frequency 12 33.3 12 33.3 9 33.3 9 33.3 MHz USBS FS USB_XI Clock Frequency –50 +50 –50 +50 –50 +50 –50 +50 ppm USB Stability Rev. D | Page 60 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing For information on the UART port receive and transmit opera- tions, see the ADSP-BF52x Hardware Reference Manual. General-Purpose Port Timing Table51 and Figure30 describe general-purpose port operations. Table 51. General-Purpose Port Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors V V DDEXT DDEXT 1.8V Nominal 2.5 V or 3.3V Nominal Parameter Min Max Min Max Unit Timing Requirement t General-Purpose Port Ball Input Pulse Width t + 1 t + 1 ns WFI SCLK SCLK Switching Characteristic t General-Purpose Port Ball Output Delay from CLKOUT 0 11.0 0 8.2 ns GPOD Low Table 52. General-Purpose Port Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors V V DDEXT DDEXT 1.8V Nominal 2.5 V or 3.3V Nominal Parameter Min Max Min Max Unit Timing Requirement t General-Purpose Port Ball Input Pulse Width t + 1 t + 1 ns WFI SCLK SCLK Switching Characteristic t General-Purpose Port Ball Output Delay from CLKOUT Low 0 8.2 0 6.5 ns GPOD CLKOUT t GPOD GPIO OUTPUT t WFI GPIO INPUT Figure 30. General-Purpose Port Timing Rev. D | Page 61 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Timer Cycle Timing Table53 and Figure31 describe timer expired operations. The input signal is asynchronous in “width capture mode” and “external clock mode” and has an absolute maximum input fre- quency of (f /2) MHz. SCLK Table 53. Timer Cycle Timing ADSP-BF522/ADSP-BF524/ADSP-BF526 ADSP-BF523/ADSP-BF525/ADSP-BF527 V V V V DDEXT DDEXT DDEXT DDEXT 1.8V Nominal 2.5 V or 3.3V Nominal 1.8V Nominal 2.5 V or 3.3V Nominal Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements t Timer Pulse Width Input t t t t ns WL SCLK SCLK SCLK SCLK Low (Measured In SCLK Cycles)1 t Timer Pulse Width Input t t t t ns WH SCLK SCLK SCLK SCLK High (Measured In SCLK Cycles)1 t Timer Input Setup Time 10 7 8.1 6.2 ns TIS Before CLKOUT Low2 t Timer Input Hold Time –2 –2 –2 –2 ns TIH After CLKOUT Low2 Switching Characteristics t Timer Pulse Width Output t –1.5 (232– 1)t t – 1 (232– 1)t t – 1 (232– 1)t t – 1 (232 – 1)t ns HTO SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK (Measured In SCLK Cycles) t Timer Output Update 6 6 6 6 ns TOD Delay After CLKOUT High 1The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode. 2Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs. CLKOUT t TOD TMRx OUTPUT t t t TIS TIH HTO TMRx INPUT t ,t WH WL Figure 31. Timer Cycle Timing Rev. D | Page 62 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Timer Clock Timing Table54 and Figure32 describe timer clock timing. Table 54. Timer Clock Timing V V DDEXT DDEXT 1.8V Nominal 2.5 V or 3.3V Nominal Parameter Min Max Min Max Unit Switching Characteristic t Timer Output Update Delay After PPI_CLK High 12.0 12.0 ns TODP PPI_CLK t TODP TMRx OUTPUT Figure 32. Timer Clock Timing Up/Down Counter/Rotary Encoder Timing Table 55. Up/Down Counter/Rotary Encoder Timing V V DDEXT DDEXT 1.8V Nominal 2.5 V or 3.3V Nominal Parameter Min Max Min Max Unit Timing Requirements t Up/Down Counter/Rotary Encoder Input Pulse Width t + 1 t + 1 ns WCOUNT SCLK SCLK t Counter Input Setup Time Before CLKOUT High1 9.0 7.0 ns CIS t Counter Input Hold Time After CLKOUT High1 0 0 ns CIH 1Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs. CLKOUT t CIS t CIH CUD/CDG/CZM t WCOUNT Figure 33. Up/Down Counter/Rotary Encoder Timing Rev. D | Page 63 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 HOSTDP A/C Timing- Host Read Cycle Table56 describes the HOSTDP A/C Host Read Cycle timing requirements. Table 56. Host Read Cycle Timing Requirements ADSP-BF522/ADSP-BF524/ ADSP-BF523/ADSP-BF525/ ADSP-BF526 ADSP-BF527 V V DDEXT DDEXT V 2.5 V or 3.3V V 2.5 V or 3.3V DDEXT DDEXT 1.8V Nominal Nominal 1.8V Nominal Nominal Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements t HOST_ADDR and HOST_CE Setup 4 4 4 4 ns SADRDL before HOST_RD falling edge t HOST_ADDR and HOST_CE Hold 2.5 2.5 2.5 2.5 ns HADRDH after HOST_RD rising edge t HOST_RD pulse width low t + t + t + t + ns RDWL DRDYRDL DRDYRDL DRDYRDL DRDYRDL (ACK mode) t + t + t + t + RDYPRD RDYPRD RDYPRD RDYPRD t t t t DRDHRDY DRDHRDY DRDHRDY DRDHRDY t HOST_RD pulse width low 1.5 × t 1.5 × t 1.5 × t 1.5 × t ns RDWL SCLK SCLK SCLK SCLK (INT mode) + 8.7 + 8.7 + 8.7 + 8.7 t HOST_RD pulse width high or time 2 × t 2 × t 2 × t 2 × t ns RDWH SCLK SCLK SCLK SCLK between HOST_RD rising edge and HOST_WR falling edge t HOST_RD rising edge delay after 2.0 2.0 0 0 ns DRDHRDY HOST_ACK rising edge (ACK mode) Switching Characteristics t Data valid prior HOST_ACK rising 4.5 3.5 4.5 3.5 ns SDATRDY edge (ACK mode) t Host_ACK falling edge after 12.5 11.25 11.25 11.25 ns DRDYRDL HOST_CE (ACK mode) t HOST_ACK low pulse-width for NM1 NM1 NM1 NM1 ns RDYPRD Read access (ACK mode) t Data disable after HOST_RD 11.0 9.0 9.0 9.0 ns DDARWH t Data valid after HOST_RD falling 1.5 × t 1.5 × t 1.5 × t 1.5 × t ns ACC SCLK SCLK SCLK SCLK edge (INT mode) t Data hold after HOST_RD rising 1.0 1.0 1.0 1.0 ns HDARWH edge 1NM (Not Measured) — This parameter is based on t . It is not measured because the number of SCLK cycles for which HOST_ACK is low depends on the Host DMA FIFO SCLK status and is system design dependent. Rev. D | Page 64 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 HOST_ADDR HOST_CE t t SADRDL HADRDH t t HOST_RD RDWL RDWH t t SDATRDY DDARWH t t ACC HDARWH HOST_DATA t t DRDHRDY DRDYRDL t RDYPRD HOST_ACK In Figure34, HOST_DATA is HOST_D0–D15. Figure 34. HOSTDP A/C- Host Read Cycle Rev. D | Page 65 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 HOSTDP A/C Timing- Host Write Cycle Table57 describes the HOSTDP A/C Host Write Cycle timing requirements. Table 57. Host Write Cycle Timing Requirements ADSP-BF522/ADSP-BF524/ ADSP-BF523/ADSP-BF525/ ADSP-BF526 ADSP-BF527 V V DDEXT DDEXT V 2.5 V or 3.3V V 2.5 V or 3.3V DDEXT DDEXT 1.8V Nominal Nominal 1.8V Nominal Nominal Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements t HOST_ADDR/HOST_CE Setup 4 4 4 4 ns SADWRL before HOST_WR falling edge t HOST_ADDR/HOST_CE Hold 2.5 2.5 2.5 2.5 ns HADWRH after HOST_WR rising edge t HOST_WR pulse width low t + t + t + t + ns WRWL DRDYWRL DRDYWRL DRDYWRL DRDYWRL (ACK mode) t + t + t + t + RDYPRD RDYPRD RDYPRD RDYPRD t t t t DWRHRDY DWRHRDY DWRHRDY DWRHRDY HOST_WR pulse width low 1.5 × t 1.5 × t 1.5 × t 1.5 × t ns SCLK SCLK SCLK SCLK (INT mode) + 8.7 + 8.7 + 8.7 + 8.7 t HOST_WR pulse width high 2 × t 2 × t 2 × t 2 × t ns WRWH SCLK SCLK SCLK SCLK or time between HOST_WR rising edge and HOST_RD falling edge t HOST_WR rising edge delay 2.0 2.0 0 0 ns DWRHRDY after HOST_ACK rising edge (ACK mode) t Data Hold after HOST_WR rising edge 2.5 2.5 2.5 2.5 ns HDATWH t Data Setup before HOST_WR 3.5 2.5 2.5 2.5 ns SDATWH rising edge Switching Characteristics t HOST_ACK falling edge after HOST_CE 12.5 11.5 11.5 11.5 ns DRDYWRL asserted (ACK mode) t HOST_ACK low pulse-width for Write NM1 NM1 NM1 NM1 ns RDYPWR access (ACK mode) 1NM (Not Measured) — This parameter is based on t . It is not measured because the number of SCLK cycles for which HOST_ACK is low depends on the Host DMA FIFO SCLK status and is system design dependent. Rev. D | Page 66 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 HOST_ADDR HOST_CE t t SADWRL HADWRH t t WRWL WRWH HOST_WR t t SDATWH HDATWH HOST_DATA t RDYPWR t t DRDYWRL DWRHRDY HOST_ACK In Figure35, HOST_DATA is HOST_D0–D15. Figure 35. HOSTDP A/C- Host Write Cycle Rev. D | Page 67 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 10/100 Ethernet MAC Controller Timing Table58 through Table63 and Figure36 through Figure41 describe the 10/100 Ethernet MAC Controller operations. Table 58. 10/100 Ethernet MAC Controller Timing: MII Receive Signal V V DDEXT DDEXT 1.8V Nominal 2.5 V or 3.3V Nominal Parameter1 Min Max Min Max Unit Timing Requirements t ERxCLK Frequency (f = SCLK Frequency) None 25 + 1% None 25 + 1% MHz ERXCLKF SCLK t ERxCLK Width (t = ERxCLK Period) t × 40% t × 60% t × 35% t × 65% ns ERXCLKW ERxCLK ERxCLK ERxCLK ERxCLK ERxCLK t Rx Input Valid to ERxCLK Rising Edge (Data In Setup) 7.5 7.5 ns ERXCLKIS t ERxCLK Rising Edge to Rx Input Invalid (Data In Hold) 7.5 7.5 ns ERXCLKIH 1MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER. t ERXCLK ERx_CLK tERXCLKW ERxD3–0 ERxDV ERxER t t ERXCLKIS ERXCLKIH Figure 36. 10/100 Ethernet MAC Controller Timing: MII Receive Signal Table 59. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal V V DDEXT DDEXT 1.8V Nominal 2.5 V or 3.3V Nominal Parameter1 Min Max Min Max Unit Switching Characteristics t ETxCLK Frequency (f = SCLK Frequency) None 25 + 1% None 25 + 1% MHz ETXCLKF SCLK t ETxCLK Width (t = ETxCLK Period) t × 40% t × 60% t × 35% t × 65% ns ETXCLKW ETxCLK ETxCLK ETxCLK ETxCLK ETxCLK t ETxCLK Rising Edge to Tx Output Valid (Data Out Valid) 20 20 ns ETXCLKOV t ETxCLK Rising Edge to Tx Output Invalid (Data Out 0 0 ns ETXCLKOH Hold) 1MII outputs synchronous to ETxCLK are ETxD3–0. t ETXCLK MIITxCLK t ETXCLKW t ETXCLKOH ETxD3–0 ETxEN t ETXCLKOV Figure 37. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal Rev. D | Page 68 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 60. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal V V DDEXT DDEXT 1.8V Nominal 2.5 V or 3.3V Nominal Parameter1 Min Max Min Max Unit Timing Requirements t REF_CLK Frequency (f = SCLK Frequency) None 50 + 1% None 50 + 1% MHz EREFCLKF SCLK t EREF_CLK Width (t = EREFCLK Period) t × 40% t × 60% t × 35% t × 65% ns EREFCLKW EREFCLK EREFCLK EREFCLK EREFCLK EREFCLK t Rx Input Valid to RMII REF_CLK Rising Edge (Data In 4 4 ns EREFCLKIS Setup) t RMII REF_CLK Rising Edge to Rx Input Invalid (Data In 2 2 ns EREFCLKIH Hold) 1RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER. t REFCLK RMII_REF_CLK tREFCLKW ERxD1–0 ERxDV ERxER t t REFCLKIS REFCLKIH Figure 38. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal Table 61. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal ADSP-BF522/ADSP-BF524/ ADSP-BF523/ADSP-BF525/ ADSP-BF526 ADSP-BF527 V V DDEXT DDEXT V 2.5 V or 3.3V V 2.5 V or 3.3V DDEXT DDEXT 1.8V Nominal Nominal 1.8V Nominal Nominal Parameter1 Min Max Min Max Min Max Min Max Unit Switching Characteristics t RMII REF_CLK Rising Edge 8.1 8.1 7.5 7.5 ns EREFCLKOV to Tx Output Valid (Data Out Valid) t RMII REF_CLK Rising Edge 2 2 2 2 ns EREFCLKOH to Tx Output Invalid (Data Out Hold) 1RMII outputs synchronous to RMII REF_CLK are ETxD1–0. t REFCLK RMII_REF_CLK t REFCLKOH ETxD1–0 ETxEN t REFCLKOV Figure 39. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal Rev. D | Page 69 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 62. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal V V DDEXT DDEXT 1.8V Nominal 2.5 V or 3.3V Nominal Parameter Min Max Min Max Unit Timing Requirements t COL Pulse Width High1 t × 1.5 t × 1.5 ns ECOLH ETxCLK ETxCLK t × 1.5 t × 1.5 ERxCLK ERxCLK t COL Pulse Width Low1 t × 1.5 t × 1.5 ns ECOLL ETxCLK ETxCLK t × 1.5 t × 1.5 ERxCLK ERxCLK t CRS Pulse Width High2 t × 1.5 t × 1.5 ns ECRSH ETxCLK ETxCLK t CRS Pulse Width Low2 t × 1.5 t × 1.5 ns ECRSL ETxCLK ETxCLK 1MII/RMII asynchronous signals are COL and CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both the ETxCLK and the ERxCLK, and the COL input must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks. 2The asynchronous CRS input is synchronized to the ETxCLK, and the CRS input must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK. MIICRS, COL t t ECRSH ECRSL t t ECOLH ECOLL Figure 40. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal Table 63. 10/100 Ethernet MAC Controller Timing: MII Station Management ADSP-BF522/ADSP-BF524/ ADSP-BF523/ADSP-BF525/ ADSP-BF526 ADSP-BF527 V V DDEXT DDEXT V 2.5 V or 3.3V V 2.5 V or 3.3V DDEXT DDEXT 1.8V Nominal Nominal 1.8V Nominal Nominal Parameter1 Min Max Min Max Min Max Min Max Unit Timing Requirements t MDIO Input Valid to MDC Rising Edge 11.5 11.5 10 10 ns MDIOS (Setup) t MDC Rising Edge to MDIO Input Invalid 11.5 11.5 10 10 ns MDCIH (Hold) Switching Characteristics t MDC Falling Edge to MDIO Output Valid 25 25 25 25 ns MDCOV t MDC Falling Edge to MDIO Output –1 –1 –1 –1 ns MDCOH Invalid (Hold) 1MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple of the system clock SCLK. MDIO is a bidirectional data line. Rev. D | Page 70 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 MDC (OUTPUT) t MDCOH MDIO (OUTPUT) t MDCOV MDIO (INPUT) t t MDIOS MDCIH Figure 41. 10/100 Ethernet MAC Controller Timing: MII Station Management Rev. D | Page 71 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 JTAG Test And Emulation Port Timing Table64 and Figure42 describe JTAG port operations. Table 64. JTAG Port Timing V V DDEXT DDEXT 1.8V Nominal 2.5 V or 3.3V Nominal Parameter Min Max Min Max Unit Timing Requirements t TCK Period 20 20 ns TCK t TDI, TMS Setup Before TCK High 4 4 ns STAP t TDI, TMS Hold After TCK High 4 4 ns HTAP t System Inputs Setup Before TCK High1 12 12 ns SSYS t System Inputs Hold After TCK High1 5 5 ns HSYS t TRST Pulse Width2 (measured in TCK cycles) 4 4 TCK TRSTW Switching Characteristics t TDO Delay from TCK Low 10 10 ns DTDO t System Outputs Delay After TCK Low3 12 12 ns DSYS 1System Inputs = DATA15–0, ARDY, SCL, SDA, PF15–0, PG15–0, PH15–0, RESET, NMI, BMODE3–0. 250MHz Maximum. 3System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, PF15–0, PG15–0, PH15–0. t TCK TCK t t STAP HTAP TMS TDI t DTDO TDO t t SSYS HSYS SYSTEM INPUTS t DSYS SYSTEM OUTPUTS Figure 42. JTAG Port Timing Rev. D | Page 72 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 OUTPUT DRIVE CURRENTS Figure43 through Figure57 show typical current-voltage char- The curves represent the current drive capability of the output acteristics for the output drivers of the ADSP-BF52x processors. drivers. See Table10 on Page23 for information about which driver type corresponds to a particular ball. 200 160 VVDDDDEEXXTT == 33..36VV @@ 2–5 4°0C°C 220400 VDDEXT = 3.6V @ – 40°C 120 VDDEXT = 3.0V @ 105°C 160 VDDEXT = 3.3V @ 25°C V = 3.0V @ 105°C A) 80 120 DDEXT T (m 40 VOH mA) 80 CURREN –400 RRENT ( 400 VOH CE CU –40 OUR –80 VOL RCE –80 S –120 U O –120 S VOL –160 –160 –200 –200 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 –240 SOURCE VOLTAGE (V) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 SOURCE VOLTAGE (V) Figure 43. Driver Type A Current (3.3V V /V ) DDEXT DDMEM Figure 46. Driver Type B Current (3.3V V /V ) DDEXT DDMEM 160 V = 2.75V @ – 40°C DDEXT 160 120 V = 2.5V @ 25°C V = 2.75V @ – 40°C DDEXT DDEXT V = 2.25V @ 105°C 120 V = 2.5V @ 25°C DDEXT DDEXT 80 V = 2.25V @ 105°C A) 80 DDEXT m E CURRENT ( –44000 VOH URRENT (mA) –44000 VOH C C SOUR –80 VOL OURCE –80 VOL –120 S –120 –160 –160 0 0.5 1.0 1.5 2.0 2.5 –200 SOURCE VOLTAGE (V) 0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE (V) Figure 44. Driver Type A Current (2.5V V /V ) DDEXT DDMEM Figure 47. Driver Type B Current (2.5V V /V ) DDEXT DDMEM 80 V = 1.9V @ – 40°C DDEXT 80 60 VDDEXT = 1.8V @ 25°C VDDEXT = 1.9V @ – 40°C 40 VDDEXT = 1.7V @ 105°C 60 VVDDEXT == 11..87VV @@ 21505°C°C NT (mA) 20 VOH mA) 4200 DDEXT VOH E CURRE –200 URRENT ( –200 C C SOUR –40 VOL URCE –40 VOL –60 SO –60 –80 –80 0 0.5 1.0 1.5 –100 SOURCE VOLTAGE (V) 0 0.5 1.0 1.5 SOURCE VOLTAGE (V) Figure 45. Driver Type A Current (1.8V V /V ) DDEXT DDMEM Figure 48. Driver Type B Current (1.8V V /V ) DDEXT DDMEM Rev. D | Page 73 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 100 160 V = 3.6V @ – 40°C V = 3.6V @ – 40°C 80 DDEXT DDEXT V = 3.3V @ 25°C 120 V = 3.3V @ 25°C DDEXT DDEXT 60 V = 3.0V @ 105°C V = 3.0V @ 105°C DDEXT 80 DDEXT T (mA) 2400 VOH T (mA) 40 VOH N N E E R 0 R 0 R R U U C –20 C E E –40 C C R –40 R OU VOL OU –80 S –60 S VOL –80 –120 –100 –160 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 SOURCE VOLTAGE (V) SOURCE VOLTAGE (V) Figure 49. Driver Type C Current (3.3V VDDEXT/VDDMEM) Figure 52. Driver Type D Current (3.3V VDDEXT/VDDMEM) 80 120 VDDEXT = 2.75V @ – 40°C 100 VDDEXT = 2.75V @ – 40°C 4600 VVDDDDEEXXTT == 22..52V5V @ @ 2 51°0C5°C 8600 VVDDDDEEXXTT == 22..52V5V @ @ 2 51°0C5°C NT (mA) 20 VOH NT (mA) 2400 VOH RRE 0 RRE 0 U U C C –20 RCE –20 RCE –40 OU –40 OU –60 S VOL S –80 VOL –60 –100 –80 –120 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE (V) SOURCE VOLTAGE (V) Figure 50. Drive Type C Current (2.5V VDDEXT/VDDMEM) Figure 53. Driver Type D Current (2.5V VDDEXT/VDDMEM) 40 60 VDDEXT = 1.9V @ – 40°C VDDEXT = 1.9V @ – 40°C 3200 VVDDDDEEXXTT == 11..87VV @@ 2150°5C°C 40 VVDDDDEEXXTT == 11..87VV @@ 2150°5C°C SOURCE CURRENT (mA) ––1210000 VOHVOL SOURCE CURRENT (mA) –22000 VOVHOL –30 –40 –40 –60 0 0.5 1.0 1.5 0 0.5 1.0 1.5 SOURCE VOLTAGE (V) SOURCE VOLTAGE (V) Figure 51. Driver Type C Current (1.8V VDDEXT/VDDMEM) Figure 54. Driver Type D Current (1.8V VDDEXT/VDDMEM) Rev. D | Page 74 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 TEST CONDITIONS 60 V = 3.6V @ – 40°C 50 DDEXT All Timing Requirements appearing in this data sheet were V = 3.3V @ 25°C 40 DDEXT measured under the conditions described in this section. V = 3.0V @ 105°C 30 DDEXT Figure58 shows the measurement point for AC measurements mA) 20 (except output enable/disable). The measurement point VMEAS is NT ( 10 VDDEXT/2 or VDDMEM/2 for VDDEXT/VDDMEM (nominal) = 1.8 V/ E 2.5 V/3.3 V. R 0 R U C –10 E C –20 R SOU –30 VOL INOPRUT VMEAS VMEAS –40 OUTPUT –50 –60 Figure 58. Voltage Reference Levels for AC Measurements 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 (Except Output Enable/Disable) SOURCE VOLTAGE (V) Figure 55. Driver Type E Current (3.3V V /V ) Output Enable Time Measurement DDEXT DDMEM Output balls are considered to be enabled when they have made 40 a transition from a high impedance state to the point when they V = 2.75V @ – 40°C DDEXT start driving. 30 V = 2.5V @ 25°C DDEXT 20 VDDEXT = 2.25V @ 105°C The output enable time tENA is the interval from the point when A) a reference signal reaches a high or low voltage level to the point m T ( 10 when the output starts driving as shown on the right side of N Figure59. E R 0 R U C E –10 OURC –20 VOL RESFIEGRNEANLCE S –30 t t DIS_MEASURED ENA_MEASURED t t –40 DIS ENA 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH VOH(MEASURED) SOURCE VOLTAGE (V) (MEASURED) VOH(MEASURED)(cid:3)(cid:4)V VTRIP(HIGH) Figure 56. Driver Type E Current (2.5V VDDEXT/VDDMEM) VOL VOL(MEASURED)+(cid:4)V VTRIP(VLOOLW(M)EASURED) (MEASURED) t t DECAY TRIP 20 V = 1.9V @ – 40°C DDEXT 15 V = 1.8V @ 25°C OUTPUTSTOPSDRIVING OUTPUTSTARTSDRIVING DDEXT V = 1.7V @ 105°C 10 DDEXT HIGHIMPEDANCESTATE A) m Figure 59. Output Enable/Disable T ( 5 N E RR 0 The time tENA_MEASURED is the interval from when the reference RCE CU –5 VOL soirg nVaTlR sIPw(liotcwh)e. sF toor wVhDeDnE XtTh/eV oDuDtMpEuMt (vnooltmagine arle)a =c h1e.8s VVT, RVIPT(RhIPig h) U (high) is 1.05V, and V (low) is 0.75V. For V /V O –10 TRIP DDEXT DDMEM S (nominal) = 2.5V, V (high) is 1.5V and V (low) is 1.0V. TRIP TRIP –15 For V /V (nominal) = 3.3V, V (high) is 1.9V, and DDEXT DDMEM TRIP V (low) is 1.4V. Time t is the interval from when the out- –20 TRIP TRIP 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 put starts driving to when the output reaches the V (high) or TRIP SOURCE VOLTAGE (V) VTRIP(low) trip voltage. Figure 57. Driver Type E Current (1.8V VDDEXT/VDDMEM) Time tENA is calculated as shown in the equation: t = t –t ENA ENA_MEASURED TRIP If multiple balls (such as the data bus) are enabled, the measure- ment value is that of the first ball to start driving. Rev. D | Page 75 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Output Disable Time Measurement TESTER PIN ELECTRONICS Output balls are considered to be disabled when they stop driv- 50Ω ing, go into a high impedance state, and start to decay from their VLOAD T1 DUT output high or low voltage. The output disable time tDIS is the 45Ω OUTPUT difference between t and t as shown on the left 70Ω DIS_MEASURED DECAY side of Figure59. tDIS = tDIS_MEASURED–tDECAY 50Ω ZTOD == 45.00Ω4 (±i m1.p1e8d nasnce) 0.5pF The time for the voltage on the bus to decay by ΔV is dependent 4pF 2pF on the capacitive load CL and the load current IL. This decay 400Ω time can be approximated by the equation: t = C VI DECAY L L NOTES: The time t is calculated with test loads C and I , and with THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED DECAY L L FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE V equal to 0.25 V for VDDEXT/VDDMEM (nominal) = 2.5 V/3.3 V EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR and 0.15 V for V /V (nominal) = 1.8V. LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS. DDEXT DDMEM The time t is the interval from when the reference ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN DIS_MEASURED SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE signal switches, to when the output voltage decays ΔV from the EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES. measured output high or output low voltage. Figure 60. Equivalent Device Loading for AC Measurements Example System Hold Time Calculation (Includes All Fixtures) To determine the data output hold time in a particular system, first calculate t using the equation given above. Choose ΔV 12 DECAY to be the difference between the processor’s output voltage and the input threshold for the device requiring the hold time. C is %) 10 L 0 the total bus capacitance (per data line), and IL is the total leak- TO 9 tRISE age or three-state current (per data line). The hold time will be % 8 0 tDECAY plus the various output disable times as specified in the E (1 tFALL Timing Specifications on Page39 (for example tDSDAT for an TIM 6 SDRAM write cycle as shown in SDRAM Interface Timing on LL A Page47). D F 4 N A Capacitive Loading E RIS 2 t = 1.8V @ 25°C Output delays and holds are based on standard capacitive loads RISE t = 1.8V @ 25°C of an average of 6pF on all balls (see Figure60). V is equal FALL LOAD 0 to (V /V ) /2. The graphs of Figure61 through 0 50 100 150 200 DDEXT DDMEM Figure72 show how output rise time varies with capacitance. LOAD CAPACITANCE (pF) The delay and hold specifications given should be derated by a Figure 61. Driver Type A Typical Rise and Fall Times (10%–90%) vs. factor derived from these figures. The graphs in these figures Load Capacitance (1.8V V /V ) DDEXT DDMEM may not be linear outside the ranges shown. Rev. D | Page 76 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 8 7 7 %) %) 6 RISE AND FALL TIME (10% TO 90 425361 tRISE tRtFISAEL L= 2.5V @ 25°C RISE AND FALL TIME (10% TO 90 41253 tRISE tFtARLISLE = 2.5V @ 25°C 0 tFALL = 2.5V @ 25°C 0 tFALL = 2.5V @ 25°C 0 50 100 150 200 0 50 100 150 200 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) Figure 62. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Figure 65. Driver Type B Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2.5V VDDEXT/VDDMEM) Load Capacitance (2.5V VDDEXT/VDDMEM) 6 6 %) 5 %) 5 O 90 tRISE O 90 t % T 4 % T 4 RISE D FALL TIME (10 32 tFALL D FALL TIME (10 32 tFALL N N A A RISE 1 tRISE = 3.3V @ 25°C RISE 1 tRISE = 3.3V @ 25°C 0 tFALL = 3.3V @ 25°C 0 tFALL = 3.3V @ 25°C 0 50 100 150 200 0 50 100 150 200 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) Figure 63. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Figure 66. Driver Type B Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (3.3V VDDEXT/VDDMEM) Load Capacitance (3.3V VDDEXT/VDDMEM) 9 25 8 %) tRISE %) % TO 90 67 % TO 90 20 tRISE ME (10 5 tFALL ME (10 15 tFALL D FALL TI 43 D FALL TI 10 N N RISE A 21 tRISE = 1.8V @ 25°C RISE A 5 tRISE = 1.8V @ 25°C tFALL = 1.8V @ 25°C tFALL = 1.8V @ 25°C 0 0 0 50 100 150 200 0 50 100 150 200 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) Figure 64. Driver Type B Typical Rise and Fall Times (10%–90%) vs. Figure 67. Driver Type C Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (1.8V VDDEXT/VDDMEM) Load Capacitance (1.8V VDDEXT/VDDMEM) Rev. D | Page 77 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 16 10 9 14 O 90%) 12 O 90%) 8 ND FALL TIME (10% T 1860 tRISE tFALL ND FALL TIME (10% T 45376 tRISE tFALL RISE A 42 tRISE = 2.5V @ 25°C RISE A 21 tRISE = 2.5V @ 25°C 0 tFALL = 2.5V @ 25°C 0 tFALL = 2.5V @ 25°C 0 50 100 150 200 0 50 100 150 200 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) Figure 68. Driver Type C Typical Rise and Fall Times (10%–90%) vs. Figure 71. Driver Type D Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2.5V VDDEXT/VDDMEM) Load Capacitance (2.5V VDDEXT/VDDMEM) 14 8 %) 12 %) 7 % TO 90 10 tRISE % TO 90 6 tRISE LL TIME (10 68 tFALL LL TIME (10 45 tFALL FA FA 3 D D N 4 N E A E A 2 S S RI 2 t = 3.3V @ 25°C RI 1 t = 3.3V @ 25°C RISE RISE t = 3.3V @ 25°C t = 3.3V @ 25°C 0 FALL 0 FALL 0 50 100 150 200 0 50 100 150 200 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) Figure 69. Driver Type C Typical Rise and Fall Times (10%–90%) vs. Figure 72. Driver Type D Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (3.3V VDDEXT/VDDMEM) Load Capacitance (3.3V VDDEXT/VDDMEM) 14 9 8 % TO 90%) 1102 tRISE % TO 90%) 67 tRISE E (10 8 tFALL E (10 5 tFALL M M ALL TI 6 ALL TI 4 D F D F 3 AN 4 AN E E 2 S S RI 2 tRISE = 1.8V @ 25°C RI 1 tRISE = 1.8V @ 25°C t = 1.8V @ 25°C t = 1.8V @ 25°C FALL FALL 0 0 0 50 100 150 200 0 50 100 150 200 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) Figure 70. Driver Type D Typical Rise and Fall Times (10%–90%) vs. Figure 73. Driver Type G Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (1.8V VDDEXT/VDDMEM) Load Capacitance (1.8V VDDEXT/VDDMEM) Rev. D | Page 78 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Values of  are provided for package comparison and printed 9 JA circuit board design considerations.  can be used for a first JA 8 order approximation of T by the equation: %) J 90 7 O 10% T 6 tRISE TJ = TA+JAPD E ( 5 TIM tFALL where: L 4 L A T = Ambient temperature (°C) F A D 3 SE AN 2 Vciracluueits boof arJdC adrees ipgrno vcoidnesdid feorra ptiaocnksa wgeh ceonm anp aerxisteornn aanl hde part isnitnekd RI 1 tRISE = 2.5V @ 25°C is required. t = 2.5V @ 25°C 0 FALL Values of JB are provided for package comparison and printed 0 50 100 150 200 circuit board design considerations. LOAD CAPACITANCE (pF) In Table66, airflow measurements comply with JEDEC stan- Figure 74. Driver Type G Typical Rise and Fall Times (10%–90%) vs. dards JESD51-2 and JESD51-6, and the junction-to-board Load Capacitance (2.5V VDDEXT/VDDMEM) measurement complies with JESD51-8. The junction-to-case measurement complies with MIL-STD-883 (Method 1012.1). 9 All measurements use a 2S2P JEDEC test board. 8 %) Table 65. Thermal Characteristics for BC-208-1 Package 90 7 % TO 6 tRISE Parameter Condition Typical Unit 0 E (1 5 JA 0 linear m/s air flow 23.20 °C/W L TIM 4 tFALL JMA 1 linear m/s air flow 20.20 °C/W L A  2 linear m/s air flow 19.20 °C/W F JMA D 3 N  13.05 °C/W A JB E 2 S  6.92 °C/W RI JC 1 t = 3.3V @ 25°C RISE  0 linear m/s air flow 0.18 °C/W t = 3.3V @ 25°C JT 0 FALL  1 linear m/s air flow 0.27 °C/W 0 50 100 150 200 JT LOAD CAPACITANCE (pF) JT 2 linear m/s air flow 0.32 °C/W Figure 75. Driver Type G Typical Rise and Fall Times (10%–90%) vs. Table 66. Thermal Characteristics for BC-289-2 Package Load Capacitance (3.3V V /V ) DDEXT DDMEM Parameter Condition Typical Unit ENVIRONMENTAL CONDITIONS  0 linear m/s air flow 34.5 °C/W JA To determine the junction temperature on the application  1 linear m/s air flow 31.1 °C/W printed circuit board use: JMA  2 linear m/s air flow 29.8 °C/W JMA T = T + P  JB 20.3 °C/W J CASE JT D  8.8 °C/W JC where:  0 linear m/s air flow 0.24 °C/W JT TJ = Junction temperature (°C) JT 1 linear m/s air flow 0.44 °C/W TCASE = Case temperature (°C) measured by customer at top JT 2 linear m/s air flow 0.53 °C/W center of package.  = From Table66 JT P = Power dissipation — For a description, see Total Power D Dissipation on Page35. Rev. D | Page 79 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 289-BALL CSP_BGA BALL ASSIGNMENT Table67 lists the CSP_BGA balls by signal mnemonic. Table68 on Page81 lists the CSP_BGA by ball number. Table 67. 289-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) Ball Ball Ball Ball Ball Ball Ball Signal No. Signal No. SignalNo. Signal No. Signal No. Signal No. Signal No. ABE0/SDQM0 AB9 DATA6 T2 GND M10 NC D23 PH0 A11 USB_XO AA23V R8 DDINT ABE1/SDQM1 AC9 DATA7 T1 GND M11 NC E22 PH1 A12 V G7 V R16 DDEXT DDINT ADDR1 AB8 DATA8 R1 GND M12 NC E23 PH2 A13 V G8 V T8 DDEXT DDINT ADDR2 AC8 DATA9 P1 GND M13 NC F22 PH3 B14 V G9 V T9 DDEXT DDINT ADDR3 AB7 DATA10 P2 GND M14 NC F23 PH4 A14 V G10 V T10 DDEXT DDINT ADDR4 AC7 DATA11 R2 GND M15 NC G22 PH5 K23 V G11 V T11 DDEXT DDINT ADDR5 AC6 DATA12 N1 GND N9 NC H23 PH6 K22 V G12 V T12 DDEXT DDINT ADDR6 AB6 DATA13 N2 GND N10 NC J23 PH7 L23 V G13 V T13 DDEXT DDINT ADDR7 AB4 DATA14 M2 GND N11 NMI U22 PH8 L22 V G14 V T14 DDEXT DDINT ADDR8 AB5 DATA15 M1 GND N12 VPPOTPAB11 PH9 T23 V G15 V T15 DDEXT DDINT ADDR9 AC5 EMU J2 GND N13 PF0 A7 PH10 M22 V H7 V T16 DDEXT DDINT ADDR10 AC4 EXT_WAKE0 AC19 GND N14 PF1 B8 PH11 R22 V J17 V J7 DDEXT DDMEM ADDR11 AB3 GND A1 GND N15 PF2 A8 PH12 M23 V K17 V K7 DDEXT DDMEM ADDR12 AC3 GND A23 GND P9 PF3 B9 PH13 N22 V L17 V L7 DDEXT DDMEM ADDR13 AB2 GND B6 GND P10 PF4 B11 PH14 N23 V M17 V M7 DDEXT DDMEM ADDR14 AC2 GND1 G16 GND P11 PF5 B10 PH15 P22 V N17 V N7 DDEXT DDMEM ADDR15 AA2 GND G17 GND P12 PF6 B12 PPI_CLK/TMRCLK A6 V P17 V P7 DDEXT DDMEM ADDR16 W2 GND1 H17 GND P13 PF7 B13 PPI_FS1/TMR0 B7 V R17 V R7 DDEXT DDMEM ADDR17 Y2 GND H22 GND P14 PF8 B16 RESET V22 V T17 V T7 DDEXT DDMEM ADDR18 AA1 GND1 J22 GND P15 PF9 A20 RTXI U23 V U17 V U7 DDEXT DDMEM ADDR19 AB1 GND J9 GND R9 PF10 B15 RTXO V23 V B5 V U8 DDINT DDMEM AMS0 AC17 GND J10 GND R10 PF11 B17 SA10 AC10V H8 V U9 DDINT DDMEM AMS1 AB16 GND J11 GND R11 PF12 B18 SCAS AC11V H9 V U10 DDINT DDMEM AMS2 AC16 GND J12 GND R12 PF13 B19 SCKE AB13V H10 V U11 DDINT DDMEM AMS3 AB15 GND J13 GND R13 PF14 A9 SCL B22 V H11 V U12 DDINT DDMEM AOE AC15 GND J14 GND R14 PF15 A10 SDA C22 V H12 V U13 DDINT DDMEM ARDY AC14 GND J15 GND R15 PG0 H2 SMS AC13V H13 V U14 DDINT DDMEM ARE AB17 GND K9 GND T22 PG1 G1 SRAS AB12V H14 V U15 DDINT DDMEM AWE AB14 GND K10 GND AC1 PG2 H1 SS/PG AC20V H15 V U16 DDINT DDMEM BMODE0 G2 GND K11 GND AC23 PG3 F1 SWE AB10V H16 V AC12 DDINT DDOTP BMODE1 F2 GND K12 NC A15 PG4 D1 TCK L1 V J8 V W23 DDINT DDRTC BMODE2 E1 GND K13 NC A16 PG5 D2 TDI J1 V J16 V W22 DDINT DDUSB BMODE3 E2 GND K14 NC A17 PG6 C2 TDO K1 V K8 V Y23 DDINT DDUSB CLKBUF AB19 GND K15 NC A18 PG7 B1 TMS L2 V K16 NC G23 DDINT CLKIN R23 GND L9 NC A19 PG8 C1 TRST K2 V L8 VR /EXT_WAKE1 AC18 DDINT OUT CLKOUT AB18 GND L10 NC A21 PG9 B2 USB_DM AB21V L16 VR /V AB22 DDINT SEL DDEXT DATA0 Y1 GND L11 NC A22 PG10 B4 USB_DP AA22V M8 XTAL P23 DDINT DATA1 V2 GND L12 NC B20 PG11 B3 USB_ID Y22 V M16 DDINT DATA2 W1 GND L13 NC B21 PG12 A2 USB_RSET AC21V N8 DDINT DATA3 U2 GND L14 NC B23 PG13 A3 USB_VBUS AB20V N16 DDINT DATA4 V1 GND L15 NC C23 PG14 A4 USB_VREF AC22V P8 DDINT DATA5 U1 GND M9 NC D22 PG15 A5 USB_XI AB23V P16 DDINT NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. 1For ADSP-BF52xC compatibility, connect this ball to V . DDEXT Rev. D | Page 80 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 68. 289-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) Ball Ball Ball Ball Ball Ball Ball No. Signal No. Signal No. Signal No. Signal No. Signal No. Signal No. Signal A1 GND B20 NC H12 V L9 GND P2 DATA10 T22 GND AB10SWE DDINT A2 PG12 B21 NC H13 V L10 GND P7 V T23 PH9 AB11VPPOTP DDINT DDMEM A3 PG13 B22 SCL H14 V L11 GND P8 V U1 DATA5 AB12SRAS DDINT DDINT A4 PG14 B23 NC H15 V L12 GND P9 GND U2 DATA3 AB13SCKE DDINT A5 PG15 C1 PG8 H16 V L13 GND P10 GND U7 V AB14AWE DDINT DDMEM A6 PPI_CLK/TMRCLK C2 PG6 H17 GND1 L14 GND P11 GND U8 V AB15AMS3 DDMEM A7 PF0 C22 SDA H22 GND L15 GND P12 GND U9 V AB16AMS1 DDMEM A8 PF2 C23 NC H23 NC L16 V P13 GND U10 V AB17ARE DDINT DDMEM A9 PF14 D1 PG4 J1 TDI L17 V P14 GND U11 V AB18CLKOUT DDEXT DDMEM A10 PF15 D2 PG5 J2 EMU L22 PH8 P15 GND U12 V AB19CLKBUF DDMEM A11 PH0 D22 NC J7 V L23 PH7 P16 V U13 V AB20USB_VBUS DDMEM DDINT DDMEM A12 PH1 D23 NC J8 V M1 DATA15 P17 V U14 V AB21USB_DM DDINT DDEXT DDMEM A13 PH2 E1 BMODE2 J9 GND M2 DATA14 P22 PH15 U15 V AB22VR /V DDMEM SEL DDEXT A14 PH4 E2 BMODE3 J10 GND M7 V P23 XTAL U16 V AB23USB_XI DDMEM DDMEM A15 NC E22 NC J11 GND M8 V R1 DATA8 U17 V AC1 GND DDINT DDEXT A16 NC E23 NC J12 GND M9 GND R2 DATA11 U22 NMI AC2 ADDR14 A17 NC F1 PG3 J13 GND M10 GND R7 V U23 RTXI AC3 ADDR12 DDMEM A18 NC F2 BMODE1 J14 GND M11 GND R8 V V1 DATA4 AC4 ADDR10 DDINT A19 NC F22 NC J15 GND M12 GND R9 GND V2 DATA1 AC5 ADDR9 A20 PF9 F23 NC J16 V M13 GND R10 GND V22 RESET AC6 ADDR5 DDINT A21 NC G1 PG1 J17 V M14 GND R11 GND V23 RTXO AC7 ADDR4 DDEXT A22 NC G2 BMODE0 J22 GND1 M15 GND R12 GND W1 DATA2 AC8 ADDR2 A23 GND G7 V J23 NC M16 V R13 GND W2 ADDR16 AC9 ABE1/SDQM1 DDEXT DDINT B1 PG7 G8 V K1 TDO M17 V R14 GND W22 V AC10SA10 DDEXT DDEXT DDUSB B2 PG9 G9 V K2 TRST M22 PH10 R15 GND W23 V AC11SCAS DDEXT DDRTC B3 PG11 G10 V K7 V M23 PH12 R16 V Y1 DATA0 AC12V DDEXT DDMEM DDINT DDOTP B4 PG10 G11 V K8 V N1 DATA12 R17 V Y2 ADDR17 AC13SMS DDEXT DDINT DDEXT B5 V G12 V K9 GND N2 DATA13 R22 PH11 Y22 USB_ID AC14ARDY DDINT DDEXT B6 GND G13 V K10 GND N7 V R23 CLKIN Y23 V AC15AOE DDEXT DDMEM DDUSB B7 PPI_FS1/TMR0 G14 V K11 GND N8 V T1 DATA7 AA1 ADDR18 AC16AMS2 DDEXT DDINT B8 PF1 G15 V K12 GND N9 GND T2 DATA6 AA2 ADDR15 AC17AMS0 DDEXT B9 PF3 G16 GND1 K13 GND N10 GND T7 V AA22USB_DP AC18VR /EXT_WAKE1 DDMEM OUT B10 PF5 G17 GND K14 GND N11 GND T8 V AA23USB_XO AC19EXT_WAKE0 DDINT B11 PF4 G22 NC K15 GND N12 GND T9 V AB1 ADDR19 AC20SS/PG DDINT B12 PF6 G23 NC K16 V N13 GND T10 V AB2 ADDR13 AC21USB_RSET DDINT DDINT B13 PF7 H1 PG2 K17 V N14 GND T11 V AB3 ADDR11 AC22USB_VREF DDEXT DDINT B14 PH3 H2 PG0 K22 PH6 N15 GND T12 V AB4 ADDR7 AC23GND DDINT B15 PF10 H7 V K23 PH5 N16 V T13 V AB5 ADDR8 DDEXT DDINT DDINT B16 PF8 H8 V L1 TCK N17 V T14 V AB6 ADDR6 DDINT DDEXT DDINT B17 PF11 H9 V L2 TMS N22 PH13 T15 V AB7 ADDR3 DDINT DDINT B18 PF12 H10 V L7 V N23 PH14 T16 V AB8 ADDR1 DDINT DDMEM DDINT B19 PF13 H11 V L8 V P1 DATA9 T17 V AB9 ABE0/SDQM0 DDINT DDINT DDEXT NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. 1For ADSP-BF52xC compatibility, connect this ball to V . DDEXT Rev. D | Page 81 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Figure76 shows the top view of the BC-289-2 CSP_BGA ball configuration. Figure77 shows the bottom view of the BC-289-2 CSP_BGA ball configuration. A1 BALL PAD CORNER A B C D E F G H J K TOP VIEW L M N P KEY: R T V GND NC DDINT U V V I/O V DDEXT DDMEM W Y AA AB AC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2122 23 Figure 76. 289-Ball CSP_BGA Ball Configuration (Top View) A1 BALL PAD CORNER A B C D E BOTTOM VIEW F G H J KEY: K L V GND NC DDINT M N V I/O V DDEXT DDMEM P R T U V W Y AA AB AC 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 77. 289-Ball CSP_BGA Ball Configuration (Bottom View) Rev. D | Page 82 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 208-BALL CSP_BGA BALL ASSIGNMENT Table69 lists the CSP_BGA balls by signal mnemonic. Table70 on Page84 lists the CSP_BGA by ball number. Table 69. 208-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) Ball Ball Ball Ball Ball Ball Signal No. Signal No. Signal No. Signal No. Signal No. Signal No. ABE0/SDQM0 V19 CLKOUT K20 GND K11 PF13 A5 PPI_CLK/TMRCLK G2 V J8 DDEXT ABE1/SDQM1 V20 DATA0 Y8 GND K12 PF14 B6 PPI_FS1/TMR0 F2 V K7 DDEXT ADDR1 W20 DATA1 W8 GND K13 PF15 A6 RESET B18 V K8 DDEXT ADDR2 W19 DATA2 Y7 GND L9 PG0 R2 RTXI A14 V L7 DDEXT ADDR3 Y19 DATA3 W7 GND L10 PG1 P1 RTXO A15 V G12 DDINT ADDR4 W18 DATA4 Y6 GND L11 PG2 P2 SA10 U19 V G13 DDINT ADDR5 Y18 DATA5 W6 GND L12 PG3 N1 SCAS U20 V G14 DDINT ADDR6 W17 DATA6 Y5 GND L13 PG4 N2 SCKE P20 V H14 DDINT ADDR7 Y17 DATA7 W5 GND M9 PG5 M1 SCL A4 V J14 DDINT ADDR8 W16 DATA8 Y4 GND M10 PG6 M2 SDA B4 V K14 DDINT ADDR9 Y16 DATA9 W4 GND M11 PG7 L1 SMS R19 V L14 DDINT ADDR10 W15 DATA10 Y3 GND M12 PG8 L2 SRAS T19 V M14 DDINT ADDR11 Y15 DATA11 W3 GND M13 PG9 K1 SS/PG G19 V N14 DDINT ADDR12 W14 DATA12 Y2 GND N9 PG10 K2 SWE T20 V P12 DDINT ADDR13 Y14 DATA13 W2 GND N10 PG11 J1 TCK V2 V P13 DDINT ADDR14 W13 DATA14 W1 GND N11 PG12 J2 TDI R1 V P14 DDINT ADDR15 Y13 DATA15 V1 GND N12 PG13 H1 TDO T1 V L8 DDMEM ADDR16 W12 EMU T2 GND N13 PG14 H2 TMS U2 V M7 DDMEM ADDR17 Y12 EXT_WAKE0 J20 GND Y1 PG15 G1 TRST U1 V M8 DDMEM ADDR18 W11 GND A1 GND Y20 PH0 A7 USB_DM F20 V N7 DDMEM ADDR19 Y11 GND A17 NMI B19 PH1 B7 USB_DP E20 V N8 DDMEM AMS0 J19 GND A20 VPPOTP L19 PH2 A8 USB_ID C20 V P7 DDMEM AMS1 K19 GND B20 PF0 F1 PH3 B8 USB_RSET D20 V P8 DDMEM AMS2 M19 GND H9 PF1 E1 PH4 A9 USB_VBUS E19 V P9 DDMEM AMS3 L20 GND H10 PF2 E2 PH5 B9 USB_VREF H19 V P10 DDMEM AOE N20 GND H11 PF3 D1 PH6 B10 USB_XI A19 V P11 DDMEM ARDY P19 GND H12 PF4 D2 PH7 B11 USB_XO A18 V R20 DDOTP ARE M20 GND H13 PF5 C1 PH8 A12 V G7 V A16 DDEXT DDRTC AWE N19 GND J9 PF6 C2 PH9 B12 V G8 V D19 DDEXT DDUSB BMODE0 Y10 GND J10 PF7 B1 PH10 A13 V G9 V G20 DDEXT DDUSB BMODE1 W10 GND J11 PF8 B2 PH11 B13 V G10 VR /EXT_WAKE1 H20 DDEXT OUT BMODE2 Y9 GND J12 PF9 A2 PH12 B14 V G11 VR /V F19 DDEXT SEL DDEXT BMODE3 W9 GND J13 PF10 B3 PH13 B15 V H7 XTAL A10 DDEXT CLKBUF C19 GND K9 PF11 A3 PH14 B16 V H8 DDEXT CLKIN A11 GND K10 PF12 B5 PH15 B17 V J7 DDEXT NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. Rev. D | Page 83 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 70. 208-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) Ball Ball Ball Ball Ball Ball No. Signal No. Signal No. Signal No. Signal No. Signal No. Signal A1 GND B16 PH14 H7 V L2 PG8 P1 PG1 W8 DATA1 DDEXT A2 PF9 B17 PH15 H8 V L7 V P2 PG2 W9 BMODE3 DDEXT DDEXT A3 PF11 B18 RESET H9 GND L8 V P7 V W10 BMODE1 DDMEM DDMEM A4 SCL B19 NMI H10 GND L9 GND P8 V W11 ADDR18 DDMEM A5 PF13 B20 GND H11 GND L10 GND P9 V W12 ADDR16 DDMEM A6 PF15 C1 PF5 H12 GND L11 GND P10 V W13 ADDR14 DDMEM A7 PH0 C2 PF6 H13 GND L12 GND P11 V W14 ADDR12 DDMEM A8 PH2 C19 CLKBUF H14 V L13 GND P12 V W15 ADDR10 DDINT DDINT A9 PH4 C20 USB_ID H19 USB_VREF L14 V P13 V W16 ADDR8 DDINT DDINT A10 XTAL D1 PF3 H20 VR /EXT_WAKE1 L19 VPPOTP P14 V W17 ADDR6 OUT DDINT A11 CLKIN D2 PF4 J1 PG11 L20 AMS3 P19 ARDY W18 ADDR4 A12 PH8 D19 V J2 PG12 M1 PG5 P20 SCKE W19 ADDR2 DDUSB A13 PH10 D20 USB_RSET J7 V M2 PG6 R1 TDI W20 ADDR1 DDEXT A14 RTXI E1 PF1 J8 V M7 V R2 PG0 Y1 GND DDEXT DDMEM A15 RTXO E2 PF2 J9 GND M8 V R19 SMS Y2 DATA12 DDMEM A16 V E19 USB_VBUS J10 GND M9 GND R20 V Y3 DATA10 DDRTC DDOTP A17 GND E20 USB_DP J11 GND M10 GND T1 TDO Y4 DATA8 A18 USB_XO F1 PF0 J12 GND M11 GND T2 EMU Y5 DATA6 A19 USB_XI F2 PPI_FS1/TMR0 J13 GND M12 GND T19 SRAS Y6 DATA4 A20 GND F19 VR /V J14 V M13 GND T20 SWE Y7 DATA2 SEL DDEXT DDINT B1 PF7 F20 USB_DM J19 AMS0 M14 V U1 TRST Y8 DATA0 DDINT B2 PF8 G1 PG15 J20 EXT_WAKE0 M19 AMS2 U2 TMS Y9 BMODE2 B3 PF10 G2 PPI_CLK/TMRCLK K1 PG9 M20 ARE U19 SA10 Y10 BMODE0 B4 SDA G7 V K2 PG10 N1 PG3 U20 SCAS Y11 ADDR19 DDEXT B5 PF12 G8 V K7 V N2 PG4 V1 DATA15 Y12 ADDR17 DDEXT DDEXT B6 PF14 G9 V K8 V N7 V V2 TCK Y13 ADDR15 DDEXT DDEXT DDMEM B7 PH1 G10 V K9 GND N8 V V19 ABE0/SDQM0 Y14 ADDR13 DDEXT DDMEM B8 PH3 G11 V K10 GND N9 GND V20 ABE1/SDQM1 Y15 ADDR11 DDEXT B9 PH5 G12 V K11 GND N10 GND W1 DATA14 Y16 ADDR9 DDINT B10 PH6 G13 V K12 GND N11 GND W2 DATA13 Y17 ADDR7 DDINT B11 PH7 G14 V K13 GND N12 GND W3 DATA11 Y18 ADDR5 DDINT B12 PH9 G19 SS/PG K14 V N13 GND W4 DATA9 Y19 ADDR3 DDINT B13 PH11 G20 V K19 AMS1 N14 V W5 DATA7 Y20 GND DDUSB DDINT B14 PH12 H1 PG13 K20 CLKOUT N19 AWE W6 DATA5 B15 PH13 H2 PG14 L1 PG7 N20 AOE W7 DATA3 NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. Rev. D | Page 84 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Figure78 shows the top view of the CSP_BGA ball configura- tion. Figure79 shows the bottom view of the CSP_BGA ball configuration. A1 BALL PAD CORNER A B C D E F G H J TOP VIEW K L M N P R KEY: T VDDINT GND U V VDDEXT I/O W Y VDDMEM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure 78. 208-Ball CSP_BGA Ball Configuration (Top View) A1 BALL PAD CORNER A B C D E F G H BOTTOM VIEW J K L M N P KEY: R VDDINT GND T U VDDEXT I/O V W VDDMEM Y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 79. 208-Ball CSP_BGA Ball Configuration (Bottom View) Rev. D | Page 85 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 OUTLINE DIMENSIONS Dimensions in the outline dimension figures (Figure80 and Figure81) are shown in millimeters. 12.00 BSC SQ A1 BALL 222018 16 14 12 10 8 6 4 2 CORNER 23 2119 17 15 13 11 9 7 5 3 1 A B C D E F G 11.00 J H BSC SQ K L M N P R 0.50 U T BSC V W Y AA AB AC TOP VIEW BOTTOM VIEW DETAIL A 1.40 1.26 DETAIL A 1.11 0.20 MIN SEATING 0.35 COPLANARITY PLANE 0.30 0.08 0.25 BALL DIAMETER *COMPLIANT WITH JEDEC STANDARD MO-275-GGCE-1 Figure 80. 289-Ball CSP_BGA (BC-289-2) 17.10 17.00 SQ A1 BALL A1 BALL 16.90 20 18 16 14 12 10 8 6 4 2 CORNER CORNER 19 17 15 13 11 9 7 5 3 1 A B C D E 15.20 F BSC SQ G H J 0.80 K BSC L M N P R T U V W Y TOP VIEW BOTTOM VIEW *1.36 *1.75 DETAIL A DETAIL A 1.26 1.61 0.35 NOM 1.16 1.46 0.30 MIN 0.50 COPLANARITY SEATING 0.45 0.12 PLANE 0.40 BALL DIAMETER *COMPLIANT TO JEDEC STANDARDS MO-275-MMAB-1 WITH EXCEPTION TO PACKAGE HEIGHT AND THICKNESS. Figure 81. 208-Ball CSP_BGA (BC-208-2) Rev. D | Page 86 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 SURFACE-MOUNT DESIGN Table71 is provided as an aid to PCB design. For industry-stan- dard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 71. Surface-Mount Design Supplement Package Solder Mask Package Package Ball Attach Type Opening Package Ball Pad Size 289-Ball CSP_BGA Solder Mask Defined 0.26 mm diameter 0.35 mm diameter 208-Ball CSP_BGA Solder Mask Defined 0.40 mm diameter 0.50 mm diameter AUTOMOTIVE PRODUCTS The ADBF525W model is available with controlled manufactur- of this data sheet carefully. Only the automotive grade products ing to support the quality and reliability requirements of shown in Table72 are available for use in automotive applica- automotive applications. Note that these automotive models tions. Contact your local ADI account representative for specific may have specifications that differ from the commercial models product ordering information and to obtain the specific auto- and designers should review the product Specifications section motive Reliability reports for these models. Table 72. Automotive Products Temperature Package Instruction Automotive Models1, 2 Range3 Package Description Option Rate (Max) ADBF525WBBCZ4xx –40°C to +85°C 208-Ball CSP_BGA BC-208-2 400 MHz ADBF525WBBCZ5xx –40°C to +85°C 208-Ball CSP_BGA BC-208-2 533 MHz ADBF525WYBCZxxx –40°C to +105°C 208-Ball CSP_BGA BC-208-2 For product details, please contact your ADI account representative. 1Z = RoHS Compliant Part. 2The information indicated by x in the model number will be provided by your ADI account representative. 3Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions for ADSP-BF523/ADSP-BF525/ ADSP-BF527 Processors on Page30 for junction temperature (T) specification which is the only temperature specification. J Rev. D | Page 87 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ORDERING GUIDE Temperature Instruction Package Model1 Range2 Rate (Max) Package Description Option ADSP-BF522BBCZ-3A –40°C to +85°C 300 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF522BBCZ-4A –40°C to +85°C 400 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF522KBCZ-3 0°C to +70°C 300 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF522KBCZ-4 0°C to +70°C 400 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF523BBCZ-5A –40°C to +85°C 533 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF523KBCZ-5 0°C to +70°C 533 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF523KBCZ-6 0°C to +70°C 600 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF523KBCZ-6A 0°C to +70°C 600 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF524BBCZ-3A –40°C to +85°C 300 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF524BBCZ-4A –40°C to +85°C 400 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF524KBCZ-3 0°C to +70°C 300 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF524KBCZ-4 0°C to +70°C 400 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF525ABCZ-5 –40°C to +70°C 500 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF525ABCZ-6 –40°C to +70°C 600 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF525BBCZ-5A –40°C to +85°C 533 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF525KBCZ-5 0°C to +70°C 533 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF525KBCZ-6 0°C to +70°C 600 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF525KBCZ-6A 0°C to +70°C 600 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF526BBCZ-3A –40°C to +85°C 300 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF526BBCZ-4A –40°C to +85°C 400 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF526KBCZ-3 0°C to +70°C 300 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF526KBCZ-4 0°C to +70°C 400 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF527BBCZ-5A –40°C to +85°C 533 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF527KBCZ-5 0°C to +70°C 533 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF527KBCZ-6 0°C to +70°C 600 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF527KBCZ-6A 0°C to +70°C 600 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 1Z = RoHS Compliant Part. 2Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors on Page28 and Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors on Page30 for junction temperature (T) specification which is J the only temperature specification. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06675-0-7/13(D) Rev. D | Page 88 of 88 | July 2013