a DSP Microcomputer ADSP-2185M FEATURES System Interface Performance Flexible I/O Structure Allows 2.5 V or 3.3 V Operation; 13.3 ns Instruction Cycle Time @ 2.5 V (Internal), All Inputs Tolerate up to 3.6 V Regardless of Mode 75 MIPS Sustained Performance 16-Bit Internal DMA Port for High-Speed Access to Single-Cycle Instruction Execution On-Chip Memory (Mode Selectable) Single-Cycle Context Switch 4 MByte Memory Interface for Storage of Data Tables 3-Bus Architecture Allows Dual Operand Fetches in and Program Overlays (Mode Selectable) Every Instruction Cycle 8-Bit DMA to Byte Memory for Transparent Program Multifunction Instructions and Data Memory Transfers (Mode Selectable) Power-Down Mode Featuring Low CMOS Standby Power I/O Memory Interface with 2048 Locations Supports Dissipation with 200 CLKIN Cycle Recovery from Parallel Peripherals (Mode Selectable) Power-Down Condition Programmable Memory Strobe and Separate I/O Low Power Dissipation in Idle Mode Memory Space Permits “Glueless” System Design Programmable Wait State Generation Integration Two Double-Buffered Serial Ports with Companding ADSP-2100 Family Code Compatible (Easy to Use Hardware and Automatic Data Buffering Algebraic Syntax), with Instruction Set Extensions Automatic Booting of On-Chip Program Memory from 80K Bytes of On-Chip RAM, Configured as Byte-Wide External Memory, e.g., EPROM, or 16K Words Program Memory RAM through Internal DMA Port 16K Words Data Memory RAM Six External Interrupts Dual-Purpose Program Memory for Both Instructionand 13 Programmable Flag Pins Provide Flexible System Data Storage Signaling Independent ALU, Multiplier/Accumulator, and Barrel UART Emulation through Software SPORT Reconfiguration Shifter Computational Units ICE-Port™ Emulator Interface Supports Debugging in Two Independent Data Address Generators Final Systems Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16-Bit Interval Timer with Prescaler 100-Lead LQFP and 144-Ball Mini-BGA FUNCTIONAL BLOCK DIAGRAM POWER-DOWN CONTROL FULL MEMORY MODE MEMORY DATA ADDRESS PROGRAM DATA PROGRAMMABLE EXTERNAL GENERATORS PROGRAM MEMORY MEMORY I/O ADDRESS DAG1 DAG2 SEQUENCER 16K (cid:1) 24 BIT 16K (cid:1) 16 BIT FLAANGDS BUS EXTERNAL DATA PROGRAM MEMORY ADDRESS BUS DATA MEMORY ADDRESS BYTE DMA CONTROLLER PROGRAM MEMORY DATA OR DATA MEMORY DATA EXTERNAL DATA BUS ARITHMETIC UNITS SERIAL PORTS TIMER ALU MAC SHIFTER SPORT0 SPORT1 INTERNAL DMA PORT ADSP-2100 BASE ARCHITECTURE HOST MODE ICE-Port is a trademark of Analog Devices, Inc. REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000

ADSP-2185M TABLE OF CONTENTS RECOMMENDED OPERATING CONDITIONS . . . . . 18 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . 18 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . 1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . 19 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 3 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 19 DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . 3 GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . 3 TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 4 MEMORY TIMING SPECIFICATIONS . . . . . . . . . . . . 19 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 FREQUENCY DEPENDENCY FOR PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . 20 Common-Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . 20 Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Full Memory Mode Pins (Mode C = 0) . . . . . . . . . . . . . . 7 Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Host Mode Pins (Mode C = 1) . . . . . . . . . . . . . . . . . . . . 7 Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Terminating Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . 8 TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pin Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 LOW POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 9 Clock Signals and Reset . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Interrupts and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . 25 Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 IDMA Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 IDMA Write, Short Write Cycle . . . . . . . . . . . . . . . . . . 30 MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . 11 IDMA Write, Long Write Cycle . . . . . . . . . . . . . . . . . . . 31 Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11 IDMA Read, Long Read Cycle . . . . . . . . . . . . . . . . . . . 32 Passive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 IDMA Read, Short Read Cycle . . . . . . . . . . . . . . . . . . . 33 Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IDMA Read, Short Read Cycle in Short Read IACK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 12 100-LEAD LQFP PIN CONFIGURATION . . . . . . . . . . 35 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 144-Ball Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . 37 Memory Mapped Registers (New to the Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . 38 ADSP-2185M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 OUTLINE DIMENSIONS I/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . . 13 100-Lead Metric Thin Plastic Quad Flatpack Composite Memory Select (CMS) . . . . . . . . . . . . . . . . . 14 (LQFP) (ST-100) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Byte Memory Select (BMS) . . . . . . . . . . . . . . . . . . . . . . 14 OUTLINE DIMENSIONS Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 144-Ball Mini-BGA (CA-144) . . . . . . . . . . . . . . . . . . . . 40 Byte Memory DMA (BDMA, Full Memory Mode) . . . . 14 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Internal Memory DMA Port (IDMA Port; Host Memory Mode) . . . . . . . . . . . . . . 15 Tables Bootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . . 15 Table I. Interrupt Priority and Interrupt IDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . . . 16 Table II. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . 11 Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table III. PMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 12 Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . 16 Table IV. DMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 13 DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM . . . 16 Table V. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Target Board Connector for EZ-ICE Probe . . . . . . . . . . 17 Table VI. Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Target Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . 17 PM, DM, BM, IOM, AND CM . . . . . . . . . . . . . . . . . . . . 17 Target System Interface Signals . . . . . . . . . . . . . . . . . . . 17 –2– REV. 0

ADSP-2185M GENERAL DESCRIPTION The EZ-KIT Lite is a hardware/software kit offering a complete The ADSP-2185M is a single-chip microcomputer optimized evaluation environment for the ADSP-218x family: an ADSP- for digital signal processing (DSP) and other high-speed numeric 2189M-based evaluation board with PC monitor software plus processing applications. assembler, linker, simulator, and PROM splitter software. The ADSP-2189M EZ-KIT Lite is a low cost, easy to use hardware The ADSP-2185M combines the ADSP-2100 family base archi- platform on which you can quickly get started with your DSP tecture (three computational units, data address generators, and software design. The EZ-KIT Lite includes the following features: a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, exten- • 75 MHz ADSP-2189M sive interrupt capabilities, and on-chip program and data memory. • Full 16-Bit Stereo Audio I/O with AD73322 Codec • RS-232 Interface The ADSP-2185M integrates 80K bytes of on-chip memory • EZ-ICE Connector for Emulator Control configured as 16K words (24-bit) of program RAM, and 16K • DSP Demo Programs words (16-bit) of data RAM. Power-down circuitry is also pro- • Evaluation Suite of VisualDSP vided to meet the low power needs of battery-operated portable equipment. The ADSP-2185M is available in a 100-lead LQFP The ADSP-218x EZ-ICE® Emulator aids in the hardware package and 144 Ball Mini-BGA. debugging of an ADSP-2185M system. The ADSP-2185M integrates on-chip emulation support with a 14-pin ICE-Port In addition, the ADSP-2185M supports new instructions, which interface. This interface provides a simpler target board connec- include bit manipulations—bit set, bit clear, bit toggle, bit test— new ALU constants, new multiplication instruction (× squared), tion that requires fewer mechanical clearance considerations than other ADSP-2100 Family EZ-ICEs. The ADSP-2185M biased rounding, result-free ALU operations, I/O memory trans- device need not be removed from the target system when using fers, and global interrupt masking, for increased flexibility. the EZ-ICE, nor are any adapters needed. Due to the small Fabricated in a high-speed, low-power, CMOS process, the footprint of the EZ-ICE connector, emulation can be supported ADSP-2185M operates with a 13.3 ns instruction cycle time. in final board designs. Every instruction can execute in a single processor cycle. The EZ-ICE performs a full range of functions, including: The ADSP-2185M’s flexible architecture and comprehensive • In-target operation instruction set allow the processor to perform multiple opera- • Up to 20 breakpoints tions in parallel. In one processor cycle, the ADSP-2185M can: • Single-step or full-speed operation • Generate the next program address • Registers and memory values can be examined and altered • Fetch the next instruction • PC upload and download functions • Perform one or two data moves • Instruction-level emulation of program booting and execution • Update one or two data address pointers • Complete assembly and disassembly of instructions • Perform a computational operation • C source-level debugging This takes place while the processor continues to: See Designing An EZ-ICE-Compatible Target System in the • Receive and transmit data through the two serial ports ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as • Receive and/or transmit data through the internal DMA port well as the Designing an EZ-ICE-Compatible System section of • Receive and/or transmit data through the byte DMA port this data sheet for the exact specifications of the EZ-ICE target • Decrement timer board connector. Additional Information DEVELOPMENT SYSTEM This data sheet provides a general overview of ADSP-2185M The ADSP-2100 Family Development Software, a complete set functionality. For additional information on the architecture and of tools for software and hardware system development, supports instruction set of the processor, refer to the ADSP-2100 Family the ADSP-2185M. The System Builder provides a high-level User’s Manual. For more information about the development method for defining the architecture of systems under develop- tools, refer to the ADSP-2100 Family Development Tools ment. The Assembler has an algebraic syntax that is easy to data sheet. program and debug. The Linker combines object files into an executable file. The Simulator provides an interactive instruction- level simulation with a reconfigurable user interface to display different portions of the hardware environment. EZ-ICE is a registered trademark of Analog Devices, Inc. REV. 0 –3–

ADSP-2185M POWER-DOWN CONTROL FULL MEMORY MODE MEMORY DATA ADDRESS PROGRAM DATA PROGRAMMABLE EXTERNAL GENERATORS PROGRAM MEMORY MEMORY I/O ADDRESS DAG1 DAG2 SEQUENCER 16K (cid:1) 24 BIT 16K (cid:1) 16 BIT FLAANGDS BUS EXTERNAL DATA PROGRAM MEMORY ADDRESS BUS DATA MEMORY ADDRESS BYTE DMA CONTROLLER PROGRAM MEMORY DATA OR DATA MEMORY DATA EXTERNAL DATA BUS ARITHMETIC UNITS SERIAL PORTS TIMER ALU MAC SHIFTER SPORT0 SPORT1 INTERNAL DMA PORT ADSP-2100 BASE ARCHITECTURE HOST MODE Figure 1.Functional Block Diagram ARCHITECTURE OVERVIEW (indirect addressing), it is post-modified by the value of one of The ADSP-2185M instruction set provides flexible data moves four possible modify registers. A length value may be associated and multifunction (one or two data moves with a computation) with each pointer to implement automatic modulo addressing instructions. Every instruction can be executed in a single for circular buffers. processor cycle. The ADSP-2185M assembly language uses an Efficient data transfer is achieved with the use of five algebraic syntax for ease of coding and readability. A compre- internal buses: hensive set of development tools supports program development. • Program Memory Address (PMA) Bus Figure 1 is an overall block diagram of the ADSP-2185M. The • Program Memory Data (PMD) Bus processor contains three independent computational units: • Data Memory Address (DMA) Bus the ALU, the multiplier/accumulator (MAC), and the shifter. • Data Memory Data (DMD) Bus The computational units process 16-bit data directly and have • Result (R) Bus provisions to support multiprecision computations. The ALU The two address buses (PMA and DMA) share a single external performs a standard set of arithmetic and logic operations; address bus, allowing memory to be expanded off-chip, and the division primitives are also supported. The MAC performs two data buses (PMD and DMD) share a single external data single-cycle multiply, multiply/add, and multiply/subtract opera- bus. Byte memory space and I/O memory space also share the tions with 40 bits of accumulation. The shifter performs logical external buses. and arithmetic shifts, normalization, denormalization, and derive exponent operations. Program memory can store both instructions and data, permit- ting the ADSP-2185M to fetch two operands in a single cycle, The shifter can be used to efficiently implement numeric one from program memory and one from data memory. The format control, including multiword and block floating-point ADSP-2185M can fetch an operand from program memory and representations. the next instruction in the same cycle. The internal result (R) bus connects the computational units so In lieu of the address and data bus for external memory connec- that the output of any unit may be the input of any unit on the tion, the ADSP-2185M may be configured for 16-bit Internal next cycle. DMA port (IDMA port) connection to external systems. The A powerful program sequencer and two dedicated data address IDMA port is made up of 16 data/address pins and five control generators ensure efficient delivery of operands to these computa- pins. The IDMA port provides transparent, direct access to the tional units. The sequencer supports conditional jumps, subroutine DSPs on-chip program and data RAM. calls, and returns in a single cycle. With internal loop counters An interface to low-cost byte-wide memory is provided by the and loop stacks, the ADSP-2185M executes looped code with Byte DMA port (BDMA port). The BDMA port is bidirectional zero overhead; no explicit jump instructions are required to and can directly address up to four megabytes of external RAM maintain loops. or ROM for off-chip storage of program overlays or data tables. Two data address generators (DAGs) provide addresses for The byte memory and I/O memory space interface supports slow simultaneous dual operand fetches (from data memory and memories and I/O memory-mapped peripherals with program- program memory). Each DAG maintains and updates four mable wait state generation. External devices can gain control of address pointers. Whenever the pointer is used to access data –4– REV. 0

ADSP-2185M external buses with bus request/grant signals (BR, BGH, and BG). • SPORTs can use an external serial clock or generate their One execution mode (Go Mode) allows the ADSP-2185M to own serial clock internally. continue running from on-chip memory. Normal execution • SPORTs have independent framing for the receive and trans- mode requires the processor to halt while buses are granted. mit sections. Sections run in a frameless mode or with frame The ADSP-2185M can respond to eleven interrupts. There can synchronization signals internally or externally generated. be up to six external interrupts (one edge-sensitive, two level- Frame sync signals are active high or inverted, with either of sensitive, and three configurable) and seven internal interrupts two pulsewidths and timings. generated by the timer, the serial ports (SPORTs), the Byte DMA • SPORTs support serial data word lengths from 3 to 16 bits port, and the power-down circuitry. There is also a master and provide optional A-law and µ-law companding according RESET signal. The two serial ports provide a complete synchro- to CCITT recommendation G.711. nous serial interface with optional companding in hardware and • SPORT receive and transmit sections can generate unique a wide variety of framed or frameless data transmit and receive interrupts on completing a data word transfer. modes of operation. • SPORTs can receive and transmit an entire circular buffer of Each port can generate an internal programmable serial clock or data with only one overhead cycle per data word. An interrupt accept an external serial clock. is generated after a data buffer transfer. The ADSP-2185M provides up to 13 general-purpose flag pins. • SPORT0 has a multichannel interface to selectively receive The data input and output pins on SPORT1 can be alternatively and transmit a 24 or 32 word, time- division multiplexed, configured as an input flag and an output flag. In addition, eight serial bitstream. flags are programmable as inputs or outputs, and three flags are always outputs. • SPORT1 can be configured to have two external interrupts A programmable interval timer generates periodic interrupts. (IRQ0 and IRQ1) and the FI and FO signals. The internally generated serial clock may still be used in this configuration. A 16-bit count register (TCOUNT) decrements every n pro- cessor cycle, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, PIN DESCRIPTIONS an interrupt is generated and the count register is reloaded from The ADSP-2185M is available in a 100-lead LQFP package a 16-bit period register (TPERIOD). and a 144-Ball Mini-BGA package. In order to maintain maxi- mum functionality and reduce package size and pin count, some Serial Ports serial port, programmable flag, interrupt and external bus pins The ADSP-2185M incorporates two complete synchronous have dual, multiplexed functionality. The external bus pins are serial ports (SPORT0 and SPORT1) for serial communications configured during RESET only, while serial port pins are soft- and multiprocessor communication. ware configurable during program execution. Flag and interrupt Here is a brief list of the capabilities of the ADSP-2185M functionality is retained concurrently on multiplexed pins. In SPORTs. For additional information on Serial Ports, refer to cases where pin functionality is reconfigurable, the default state is the ADSP-2100 Family User’s Manual. shown in plain text; alternate functionality is shown in italics. • SPORTs are bidirectional and have a separate, double- buffered transmit and receive section. REV. 0 –5–

ADSP-2185M Common-Mode Pins Pin Name # of Pins I/O Function RESET 1 I Processor Reset Input BR 1 I Bus Request Input BG 1 O Bus Grant Output BGH 1 O Bus Grant Hung Output DMS 1 O Data Memory Select Output PMS 1 O Program Memory Select Output IOMS 1 O Memory Select Output BMS 1 O Byte Memory Select Output CMS 1 O Combined Memory Select Output RD 1 O Memory Read Enable Output WR 1 O Memory Write Enable Output IRQ2 1 I Edge- or Level-Sensitive Interrupt Request1 PF7 I/O Programmable I/O Pin IRQL1 1 I Level-Sensitive Interrupt Requests1 PF6 I/O Programmable I/O Pin IRQL0 1 I Level-Sensitive Interrupt Requests1 PF5 I/O Programmable I/O Pin IRQE 1 I Edge-Sensitive Interrupt Requests1 PF4 I/O Programmable I/O Pin Mode D 1 I Mode Select Input—Checked Only During RESET PF3 I/O Programmable I/O Pin During Normal Operation Mode C 1 I Mode Select Input—Checked Only During RESET PF2 I/O Programmable I/O Pin During Normal Operation Mode B 1 I Mode Select Input—Checked Only During RESET PF1 I/O Programmable I/O Pin During Normal Operation Mode A 1 I Mode Select Input—Checked Only During RESET PF0 I/O Programmable I/O Pin During Normal Operation CLKIN, XTAL 2 I Clock or Quartz Crystal Input CLKOUT 1 O Processor Clock Output SPORT0 5 I/O Serial Port I/O Pins SPORT1 5 I/O Serial Port I/O Pins IRQ1:0, FI, FO Edge- or Level-Sensitive Interrupts, FI, FO2 PWD 1 I Power-Down Control Input PWDACK 1 O Power-Down Control Output FL0, FL1, FL2 3 O Output Flags V 2 I Internal V (2.5 V) Power (LQFP) DDINT DD V 4 I External V (2.5 V or 3.3 V) Power (LQFP) DDEXT DD GND 10 I Ground (LQFP) V 4 I Internal V (2.5 V) Power (Mini-BGA) DDINT DD V 7 I External V (2.5 V or 3.3 V) Power (Mini-BGA) DDEXT DD GND 20 I Ground (Mini-BGA) EZ-Port 9 I/O For Emulation Use NOTES 1Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag. 2SPORT configuration determined by the DSP System Control Register. Software configurable. –6– REV. 0

ADSP-2185M Memory Interface Pins The ADSP-2185M processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full exter- nal overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities. The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running. The following tables list the active signals at specific pins of the DSP during either of the two operating modes (Full Memory or Host). A signal in one table shares a pin with a signal from the other table, with the active signal determined by the mode set. For the shared pins and their alternate signals (e.g., A4/IAD3), refer to the package pinout tables. Full Memory Mode Pins (Mode C = 0) Pin Name # of Pins I/O Function A13:0 14 O Address Output Pins for Program, Data, Byte, and I/O Spaces D23:0 24 I/O Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used as Byte Memory Addresses.) Host Mode Pins (Mode C = 1) Pin Name # of Pins I/O Function IAD15:0 16 I/O IDMA Port Address/Data Bus A0 1 O Address Pin for External I/O, Program, Data, or Byte Access1 D23:8 16 I/O Data I/O Pins for Program, Data, Byte, and I/O Spaces IWR 1 I IDMA Write Enable IRD 1 I IDMA Read Enable IAL 1 I IDMA Address Latch Pin IS 1 I IDMA Select IACK 1 O IDMA Port Acknowledge Configurable in Mode D; Open Drain NOTE 1In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals. REV. 0 –7–

ADSP-2185M Terminating Unused Pins The following table shows the recommendations for terminating unused pins. Pin Terminations I/O 3-State Reset Hi-Z* Pin Name (Z) State Caused By Unused Configuration XTAL I I Float CLKOUT O O Float A13:1 or O (Z) Hi-Z BR, EBR Float IAD 12:0 I/O (Z) Hi-Z IS Float A0 O (Z) Hi-Z BR, EBR Float D23:8 I/O (Z) Hi-Z BR, EBR Float D7 or I/O (Z) Hi-Z BR, EBR Float IWR I I High (Inactive) D6 or I/O (Z) Hi-Z BR, EBR Float IRD I I BR, EBR High (Inactive) D5 or I/O (Z) Hi-Z Float IAL I I Low (Inactive) D4 or I/O (Z) Hi-Z BR, EBR Float IS I I High (Inactive) D3 or I/O (Z) Hi-Z BR, EBR Float IACK Float D2:0 or I/O (Z) Hi-Z BR, EBR Float IAD15:13 I/O (Z) Hi-Z IS Float PMS O (Z) O BR, EBR Float DMS O (Z) O BR, EBR Float BMS O (Z) O BR, EBR Float IOMS O (Z) O BR, EBR Float CMS O (Z) O BR, EBR Float RD O (Z) O BR, EBR Float WR O (Z) O BR, EBR Float BR I I High (Inactive) BG O (Z) O EE Float BGH O O Float IRQ2/PF7 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let Float IRQL1/PF6 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let Float IRQL0/PF5 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let Float IRQE/PF4 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let Float SCLK0 I/O I Input = High or Low, Output = Float RFS0 I/O I High or Low DR0 I I High or Low TFS0 I/O I High or Low DT0 O O Float SCLK1 I/O I Input = High or Low, Output = Float RFS1/IRQ0 I/O I High or Low DR1/FI I I High or Low TFS1/IRQ1 I/O I High or Low DT1/FO O O Float EE I I Float EBR I I Float EBG O O Float ERESET I I Float EMS O O Float EINT I I Float ECLK I I Float ELIN I I Float ELOUT O O Float NOTES *Hi-Z = High Impedance. 1. If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register. 2. If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as inter- rupts and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1, prior to enabling interrupts, and let pins float. 3. All bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive. 4. CLKIN, RESET, and PF3:0/MODE D:A are not included in the table because these pins must be used. –8– REV. 0

ADSP-2185M Interrupts of the state of IMASK. Disabling the interrupts does not affect The interrupt controller allows the processor to respond to the serial port autobuffering or DMA. 11 possible interrupts and reset with minimum overhead. The ENA INTS; ADSP-2185M provides four dedicated external interrupt input DIS INTS; pins: IRQ2, IRQL0, IRQL1, and IRQE (shared with the PF7:4 When the processor is reset, interrupt servicing is enabled. pins). In addition, SPORT1 may be reconfigured for IRQ0, IRQ1, FI and FO, for a total of six external interrupts. The ADSP-2185M also supports internal interrupts from the timer, LOW POWER OPERATION The ADSP-2185M has three low power modes that significantly the byte DMA port, the two serial ports, software, and the power- down control circuit. The interrupt levels are internally prioritized reduce the power dissipation when the device operates under and individually maskable (except power- down and reset). The standby conditions. These modes are: IRQ2, IRQ0, and IRQ1 input pins can be programmed to be • Power-Down either level- or edge-sensitive. IRQL0 and IRQL1 are level- • Idle sensitive and IRQE is edge-sensitive. The priorities and vector • Slow Idle addresses of all interrupts are shown in Table I. The CLKOUT pin may also be disabled to reduce external power dissipation. Table I. Interrupt Priority and Interrupt Vector Addresses Power-Down Interrupt Vector The ADSP-2185M processor has a low power feature that lets Source Of Interrupt Address (Hex) the processor enter a very low-power dormant state through hardware or software control. Following is a brief list of power- Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority) down features. Refer to the ADSP-2100 Family User’s Manual, Power-Down (Nonmaskable) 002C “System Interface” chapter, for detailed information about the IRQ2 0004 power-down feature. IRQL1 0008 IRQL0 000C • Quick recovery from power-down. The processor begins SPORT0 Transmit 0010 executing instructions in as few as 200 CLKIN cycles. SPORT0 Receive 0014 • Support for an externally generated TTL or CMOS processor IRQE 0018 clock. The external clock can continue running during power- BDMA Interrupt 001C down without affecting the lowest power rating and 200 CLKIN SPORT1 Transmit or IRQ1 0020 cycle recovery. SPORT1 Receive or IRQ0 0024 Timer 0028 (Lowest Priority) • Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits approximately Interrupt routines can either be nested with higher priority inter- 4096 CLKIN cycles for the crystal oscillator to start or stabi- rupts taking precedence or processed sequentially. Interrupts lize), and letting the oscillator run to allow 200 CLKIN cycle can be masked or unmasked with the IMASK register. Individual start-up. interrupt requests are logically ANDed with the bits in IMASK; • Power-down is initiated by either the power-down pin (PWD) the highest priority unmasked interrupt is then selected. The or the software power-down force bit. Interrupt support allows power-down interrupt is nonmaskable. an unlimited number of instructions to be executed before The ADSP-2185M masks all interrupts for one instruction optionally powering down. The power-down interrupt also cycle following the execution of an instruction that modifies the can be used as a nonmaskable, edge-sensitive interrupt. IMASK register. This does not affect serial port autobuffering • Context clear/save control allows the processor to continue or DMA transfers. where it left off or start with a clean context when leaving the The interrupt control register, ICNTL, controls interrupt nest- power-down state. ing and defines the IRQ0, IRQ1, and IRQ2 external interrupts • The RESET pin also can be used to terminate power-down. to be either edge- or level-sensitive. The IRQE pin is an exter- • Power-down acknowledge pin indicates when the processor nal edge sensitive interrupt and can be forced and cleared. The has entered power-down. IRQL0 and IRQL1 pins are external level sensitive interrupts. Idle The IFC register is a write-only register used to force and clear When the ADSP-2185M is in the Idle Mode, the processor interrupts. On-chip stacks preserve the processor status and are waits indefinitely in a low-power state until an interrupt occurs. automatically maintained during interrupt handling. The stacks When an unmasked interrupt occurs, it is serviced; execution are twelve levels deep to allow interrupt, loop, and subroutine then continues with the instruction following the IDLE instruc- nesting. The following instructions allow global enable or disable tion. In Idle mode IDMA, BDMA and autobuffer cycle steals servicing of the interrupts (including power down), regardless still occur. REV. 0 –9–

ADSP-2185M Slow Idle ADSP-2185M also provides four external interrupts and two The IDLE instruction is enhanced on the ADSP-2185M to let serial ports or six external interrupts and one serial port. Host the processor’s internal clock signal be slowed, further reducing Memory Mode allows access to the full external data bus, but power consumption. The reduced clock frequency, a program- limits addressing to a single address bit (A0). Through the use mable fraction of the normal clock rate, is specified by a selectable of external hardware, additional system peripherals can be added divisor given in the IDLE instruction. in this mode to generate and latch address signals. The format of the instruction is: Clock Signals The ADSP-2185M can be clocked by either a crystal or a IDLE (n); TTL-compatible clock signal. where n = 16, 32, 64, or 128. This instruction keeps the proces- The CLKIN input cannot be halted, changed during opera- sor fully functional, but operating at the slower clock rate. While tion, nor operated below the specified frequency during normal it is in this state, the processor’s other internal clock signals, such operation. The only exception is while the processor is in the as SCLK, CLKOUT, and timer clock, are reduced by the same power-down state. For additional information, refer to Chap- ratio. The default form of the instruction, when no clock divisor ter 9, ADSP-2100 Family User’s Manual, for detailed information is given, is the standard IDLE instruction. on this power-down feature. When the IDLE (n) instruction is used, it effectively slows down If an external clock is used, it should be a TTL-compatible signal the processor’s internal clock and thus its response time to incom- running at half the instruction rate. The signal is connected to ing interrupts. The one-cycle response time of the standard idle the processor’s CLKIN input. When an external clock is used, state is increased by n, the clock divisor. When an enabled inter- the XTAL input must be left unconnected. rupt is received, the ADSP-2185M will remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or The ADSP-2185M uses an input clock with a frequency equal to 128) before resuming normal operation. half the instruction rate; a 37.50 MHz input clock yields a 13 ns processor cycle (which is equivalent to 75 MHz). Normally, When the IDLE (n) instruction is used in systems that have an instructions are executed in a single processor cycle. All device externally generated serial clock (SCLK), the serial clock rate timing is relative to the internal instruction clock rate, which is may be faster than the processor’s reduced internal clock rate. indicated by the CLKOUT signal when enabled. Under these conditions, interrupts must not be generated at a faster than can be serviced, due to the additional time the Because the ADSP-2185M includes an on-chip oscillator circuit, processor takes to come out of the idle state (a maximum of n an external crystal may be used. The crystal should be connected processor cycles). across the CLKIN and XTAL pins, with two capacitors con- nected as shown in Figure 3. Capacitor values are dependent on SYSTEM INTERFACE crystal type and should be specified by the crystal manufacturer. Figure 2 shows typical basic system configurations with the A parallel-resonant, fundamental frequency, microprocessor- ADSP-2185M, two serial devices, a byte-wide EPROM, and grade crystal should be used. optional external program and data overlay memories (mode- A clock output (CLKOUT) signal is generated by the processor selectable). Programmable wait state generation allows the at the processor’s cycle rate. This can be enabled and disabled by processor to connect easily to slow peripheral devices. The the CLKODIS bit in the SPORT0 Autobuffer Control Register. FULL MEMORY MODE HOST MEMORY MODE ADSP-2185M 1/2x CLOCK CLKIN 1/2x CLOCK CLKIN CRYOSRTAL XTAL ADDR13–0 14 A13–0 CRYOSRTAL XTAL 1 FL0–2 D23–16 A0–A21 FL0–2 A0 IIRRQQE2//PPFF74 DATA23–0 24 D15–8 DATA MEBMYTOERY IIRRQQ2E//PPFF74 DATA23–8 16 IIRRQQLL01//PPFF56 BMS AADDSSPP--22118855MM CS IIRRQQLL01//PPFF56 BMS WR A10–0 MODE D/PF3 WR MMMOOODDDEEE DCA///PPPFFF320 RD D23–8 DAADTDAR(PEI/ROIP SHPEARCAELS) MMMOOODDDEEE CBA///PPPFFF210 RD MODE B/PF1 2048 LOCATIONS SPORT1 IOMS CS IOMS DSEERVIICAEL SRTFCFSSSLP11KO O1ORRRT 1IIRRQQ10 DA2133––00 DAADTDAR OMVEEMROLRAYY DSEERVIICAEL SRTDFCFTSS1L1 1KO O1ORRR F IOIRRQQ10 DDTR11 OORR FFOI DPMMSS PM TSWEGOM 8EKNTS DRSP1 OORRT F0I DPMMSS SPORT0 CMS TWO 8K SCLK0 CMS DSEERVIICAEL SRTDFCFTSS0L0K00 BGBBHGR DM SEGMENTS DSEERVIICAEL RTDDFFTRSS0000 BBGBGHR DR0 PWD IDMA PORT PWD PWDACK IRD/D6 PWDACK SYSTEM IWR/D7 INTERFACE IS/D4 OR IAL/D5 (cid:2)CONTROLLER IACK/D3 IAD15–0 16 Figure 2. Basic System Interface –10– REV. 0

ADSP-2185M performed. The first instruction is fetched from on-chip pro- gram memory location 0x0000 once boot loading completes. CLKIN XTAL CLKOUT Power Supplies The ADSP-2185M has separate power supply connections for DSP the internal (V ) and external (V ) power supplies. DDINT DDEXT The internal supply must meet the 2.5 V requirement. The external supply can be connected to either a 2.5 V or 3.3 V supply. Figure 3.External Crystal Connections All external supply pins must be connected to the same supply. All input and I/O pins can tolerate input voltages up to 3.6 V, RESET regardless of the external supply voltage. This feature provides The RESET signal initiates a master reset of the ADSP-2185M. maximum flexibility in mixing 2.5 V and 3.3 V components. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial MODES OF OPERATION power-up must be held long enough to allow the internal clock Setting Memory Mode to stabilize. If RESET is activated any time after power-up, the Memory Mode selection for the ADSP-2185M is made during clock continues to run and does not require stabilization time. chip reset through the use of the Mode C pin. This pin is multi- The power-up sequence is defined as the total time required for the plexed with the DSP’s PF2 pin, so care must be taken in how crystal oscillator circuit to stabilize after a valid V is applied to the mode selection is made. The two methods for selecting the DD the processor, and for the internal phase-locked loop (PLL) to lock value of Mode C are active and passive. onto the specific crystal frequency. A minimum of 2000 CLKIN Passive Configuration cycles ensures that the PLL has locked but does not include the Passive Configuration involves the use a pull-up or pull-down crystal oscillator start-up time. During this power-up sequence resistor connected to the Mode C pin. To minimize power con- the RESET signal should be held low. On any subsequent resets, sumption, or if the PF2 pin is to be used as an output in the DSP the RESET signal must meet the minimum pulsewidth specifi- application, a weak pull-up or pull-down, on the order of 10 kΩ, cation, t . RSP can be used. This value should be sufficient to pull the pin to the The RESET input contains some hysteresis; however, if an desired level and still allow the pin to operate as a programmable RC circuit is used to generate the RESET signal, the use of an flag output without undue strain on the processor’s output driver. external Schmidt trigger is recommended. For minimum power consumption during power-down, recon- The master reset sets all internal stack pointers to the empty stack figure PF2 to be an input, as the pull-up or pull-down will condition, masks all interrupts, and clears the MSTAT register. hold the pin in a known state, and will not switch. When RESET is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is Table II. Modes of Operation MODE D MODE C MODE B MODE A Booting Method X 0 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Full Memory Mode.1 X 0 1 0 No automatic boot operations occur. Program execution starts at external memory location 0. Chip is configured in Full Memory Mode. BDMA can still be used, but the processor does not automatically use or wait for these operations. 0 1 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode. IACK has active pull-down. (REQUIRES ADDITIONAL HARDWARE). 0 1 0 1 IDMA feature is used to load any internal memory as desired. Program execution is held off until internal program memory location 0 is written to. Chip is configured in Host Mode. IACK has active pull-down.1 1 1 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode; IACK requires exter- nal pull down. (REQUIRES ADDITIONAL HARDWARE) 1 1 0 1 IDMA feature is used to load any internal memory as desired. Program execution is held off until internal program memory location 0 is written to. Chip is configured in Host Mode. IACK requires external pull-down.1 NOTE 1Considered as standard operating settings. Using these configurations allows for easier design and better memory management. REV. 0 –11–

ADSP-2185M Active Configuration MEMORY ARCHITECTURE Active Configuration involves the use of a three-statable external The ADSP-2185M provides a variety of memory and peripheral driver connected to the Mode C pin. A driver’s output enable interface options. The key functional groups are Program Memory, should be connected to the DSP’s RESET signal such that it Data Memory, Byte Memory, and I/O. Refer to the following only drives the PF2 pin when RESET is active (low). When figures and tables for PM and DM memory allocations in the RESET is deasserted, the driver should three-state, thus allow- ADSP-2185M. ing full use of the PF2 pin as either an input or output. To Program Memory minimize power consumption during power-down, configure Program Memory (Full Memory Mode) is a 24-bit-wide the programmable flag as an output when connected to a three- space for storing both instruction opcodes and data. The ADSP- stated buffer. This ensures that the pin will be held at a constant 2185M has 16K words of Program Memory RAM on chip, and level, and will not oscillate should the three-state driver’s level the capability of accessing up to two 8K external memory over- hover around the logic switching point. lay spaces using the external data bus. IACK Configuration Program Memory (Host Mode) allows access to all internal Mode D = 0 and in host mode: IACK is an active, driven signal memory. External overlay access is limited by a single external and cannot be “wire OR’d.” address line (A0). External program execution is not available in Mode D = 1 and in host mode: IACK is an open drain and host mode due to a restricted data bus that is 16 bits wide only. requires an external pull-down, but multiple IACK pins can be “wire OR’d” together. PM (MODE B = 0) PM (MODE B = 1)1 ALWAYS ACCESSIBLE AT ADDRESS RESERVED 0x2000 – 0x0000 – 0x1FFF 0x3FFF 0x2000 – ACCESSIBLE WHEN 0x0000 – 0x3FFF PMOVLAY = 0 0x1FFF2 ACCESSIBLE WHEN PMOVLAY = 0 ACCESSIBLE WHEN 0x0000 – PMOVLAY = 0 0x1FFF2 0x2000 – 0x3FFF2 ACCESSIBLE WHEN PMOVLAY = 1 EXTERNAL RESERVED MEMORY 0x2000 – 0x3FFF2 NOTES: EXTERNAL ACCESSIBLE WHEN 1WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0 MEMORY PMOVLAY = 2 2SEE TABLE III FOR PMOVLAY BITS PROGRAM MEMORY PROGRAM MEMORY MODE B = 0 ADDRESS MODE B = 1 ADDRESS 8K INTERNAL 0x3FFF 0x3FFF PMOVLAY = 0 OR 8K INTERNAL 8K EXTERNAL PMOVLAY = 0 PMOVLAY = 1, 2 0x2000 0x2000 0x1FFF 0x1FFF 8K 8K INTERNAL EXTERNAL 0x0000 0x0000 Figure 4. Program Memory Table III. PMOVLAY Bits PMOVLAY Memory A13 A12:0 0 Internal Not Applicable Not Applicable 1 External Overlay 1 0 13 LSBs of Address Between 0x2000 and 0x3FFF 2 External Overlay 2 1 13 LSBs of Address Between 0x2000 and 0x3FFF –12– REV. 0

ADSP-2185M Data Memory complete in one cycle. Accesses to external memory are timed Data Memory (Full Memory Mode) is a 16-bit-wide space used using the wait states specified by the DWAIT register and the for the storage of data variables and for memory-mapped control wait state mode bit. registers. The ADSP-2185M has 16K words on Data Memory Data Memory (Host Mode) allows access to all internal memory. RAM on-chip. Part of this space is used by 32 memory-mapped External overlay access is limited by a single external address registers. Support also exists for up to two 8K external memory line (A0). overlay spaces through the external data bus. All internal accesses DATA MEMORY DATA MEMORY ADDR 32 MEMORY 0x3FFF ALWAYS MAPPED ACCESSIBLE AT ADDRESS REGISTERS 0x3FE0 0x2000 – 0x3FFF 0x3FDF INTERNAL 8160 WORDS 0x2000 0x0000 – 0x1FFF 0x1FFF ACCESSIBLE WHEN 8K INTERNAL DM OVLAY = 0 DMOVLAY = 0 0x0000 – 0x1FFF1 OR EXTERNAL 8K 0x0000 – 0x1FFF1 DMOVLAY = 1, 2 ACCESSIBLE WHEN 0x0000 DMOVLAY = 1 EXTERNAL NOTE: MEMORY ADCMCOEVSLSAIYB L=E 2 WHEN 1SEE TABLE IV FOR DMOVAY BITS Figure 5. Data Memory Map Table IV. DMOVLAY Bits DMOVLAY Memory A13 A12:0 0 Internal Not Applicable Not Applicable 1 External Overlay 1 0 13 LSBs of Address Between 0x2000 and 0x3FFF 2 External Overlay 2 1 13 LSBs of Address Between 0x2000 and 0x3FFF Memory Mapped Registers (New to the ADSP-2185M) SYSTEM CONTROL The ADSP-2185M has three memory mapped registers that differ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 from other ADSP-21xx Family DSPs. The slight modifications 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 DM(0x3FFF) to these registers (Wait State Control, Programmable Flag and RESERVED RESERVED, ALWAYS PWAIT Composite Select Control, and System Control) provide the SET TO 0 SET TO 0 PROGRAM MEMORY WAIT STATES ADSP-2185M’s wait state and BMS control features. Default SPORT0 ENABLE bit values at reset are shown; if no value is shown, the bit is unde- 01 == EDNISAABBLLEE DISABLE BMS fined at reset. Reserved bits are shown on a grey field. These bits 0 = ENABLE BMS SPORT1 ENABLE 1 = DISABLE BMS, EXCEPT WHEN MEMORY should always be written with zeros. 0 = DISABLE STROBES ARE THREE-STATED 1 = ENABLE WAITSTATE CONTROL SPORT1 CONFIGURE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 = FI, FO, IRQ0, IRQ1, SCLK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DM(0(cid:1)3FFE) 1 = SPORT1 NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAIT0 ALWAYS BE WRITTEN WITH ZEROS. Figure 8.System Control Register WAIT STATE MODE SELECT 0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES, RANGING I/O Space (Full Memory Mode) FROM 0 TO 7) 1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES, RANGING The ADSP-2185M supports an additional external memory FROM 0 TO 15) space called I/O space. This space is designed to support simple Figure 6.Wait State Control Register connections to peripherals (such as data converters and external registers) or to bus interface ASIC data registers. I/O space sup- PROGRAMMABLE FLAG AND COMPOSITE SELECT CONTROL ports 2048 locations of 16-bit wide data. The lower eleven bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 of the external address bus are used; the upper three bits are 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 DM(0x3FE6) undefined. Two instructions were added to the core ADSP-2100 Family instruction set to read from and write to I/O memory BMWAIT CMSSEL PFTYPE 0 = DISABLE CMS 0 = INPUT space. The I/O space also has four dedicated three-bit wait state 1 = ENABLE CMS 1 = OUTPUT registers, IOWAIT0–3, which in combination with the wait state (WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM) mode bit, specify up to 15 wait states to be automatically gener- Figure 7.Programmable Flag and Composite Control ated for each of four regions. The wait states act on address Register ranges as shown in Table V. REV. 0 –13–

ADSP-2185M Table V. Wait States BDMA CONTROL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Range Wait State Register 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 DM (0(cid:1)3FE3) 0x000–0x1FF IOWAIT0 and Wait State Mode Select Bit BMPAGE BDMA BTYPE 0x200–0x3FF IOWAIT1 and Wait State Mode Select Bit OVERLAY BDIR BITS 0 = LOAD FROM BM 0x400–0x5FF IOWAIT2 and Wait State Mode Select Bit 1 = STORE TO BM 0x600–0x7FF IOWAIT3 and Wait State Mode Select Bit BCR 0 = RUN DURING BDMA 1 = HALT DURING BDMA Composite Memory Select (CMS) Figure 9.BDMA Control Register The ADSP-2185M has a programmable memory select signal that The BDMA circuit supports four different data formats that are is useful for generating memory select signals for memories selected by the BTYPE register field. The appropriate number mapped to more than one space. The CMS signal is gener- of 8-bit accesses are done from the byte memory space to build ated to have the same timing as each of the individual memory the word size selected. Table VI shows the data formats sup- select signals (PMS, DMS, BMS, IOMS) but can combine their ported by the BDMA circuit. functionality. Each bit in the CMSSEL register, when set, causes the CMS Table VI. Data Formats signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both BTYPE Internal Memory Space Word Size Alignment program and data memory, set the PMS and DMS bits in the 00 Program Memory 24 Full Word CMSSEL register and use the CMS pin to drive the chip 01 Data Memory 16 Full Word select of the memory, and use either DMS or PMS as the 10 Data Memory 8 MSBs additional address bit. 11 Data Memory 8 LSBs The CMS pin functions like the other memory select signals with the same timing and bus request logic. A 1 in the enable bit Unused bits in the 8-bit data memory formats are filled with 0s. causes the assertion of the CMS signal at the same time as the The BIAD register field is used to specify the starting address selected memory select signal. All enable bits default to 1 at reset, for the on-chip memory involved with the transfer. The 14-bit except the BMS bit. BEAD register specifies the starting address for the external byte memory space. The 8-bit BMPAGE register specifies the start- Byte Memory Select (BMS) ing page for the external byte memory space. The BDIR register The ADSP-2185M’s BMS disable feature combined with the field selects the direction of the transfer. Finally, the 14-bit CMS pin allows use of multiple memories in the byte memory BWCOUNT register specifies the number of DSP words to space. For example, an EPROM could be attached to the BMS transfer and initiates the BDMA circuit transfers. select, and an SRAM could be connected to CMS. Because at reset BMS is enabled, the EPROM would be used for booting. BDMA accesses can cross page boundaries during sequential After booting, software could disable BMS and set the CMS addressing. A BDMA interrupt is generated on the completion signal to respond to BMS, enabling the SRAM. of the number of transfers specified by the BWCOUNT register. Byte Memory The BWCOUNT register is updated after each transfer so it can The byte memory space is a bidirectional, 8-bit-wide, external be used to check the status of the transfers. When it reaches zero, memory space used to store programs and data. Byte memory is the transfers have finished and a BDMA interrupt is generated. accessed using the BDMA feature. The byte memory space con- The BMPAGE and BEAD registers must not be accessed by the sists of 256 pages, each of which is 16K × 8. DSP during BDMA operations. The byte memory space on the ADSP-2185M supports read and The source or destination of a BDMA transfer will always be write operations as well as four different data formats. The byte on-chip program or data memory. memory uses data bits 15:8 for data. The byte memory uses data When the BWCOUNT register is written with a nonzero value bits 23:16 and address bits 13:0 to create a 22-bit address. This the BDMA circuit starts executing byte memory accesses with wait allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be used states set by BMWAIT. These accesses continue until the count without glue logic. All byte memory accesses are timed by the reaches zero. When enough accesses have occurred to create a BMWAIT register and the wait state mode bit. destination word, it is transferred to or from on-chip memory. Byte Memory DMA (BDMA, Full Memory Mode) The transfer takes one DSP cycle. DSP accesses to external The byte memory DMA controller allows loading and storing of memory have priority over BDMA byte memory accesses. program instructions and data using the byte memory space. The The BDMA Context Reset bit (BCR) controls whether the BDMA circuit is able to access the byte memory space while the processor is held off while the BDMA accesses are occurring. processor is operating normally and steals only one DSP cycle Setting the BCR bit to 0 allows the processor to continue opera- per 8-, 16- or 24-bit word transferred. tions. Setting the BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear the context of the processor, and start execution at address 0 when the BDMA accesses have completed. –14– REV. 0

ADSP-2185M The BDMA overlay bits specify the OVLAY memory blocks to Through the IDMAA register, the DSP can also specify the be accessed for internal memory. For ADSP-2185M, set to zero starting address and data format for DMA operation. Asserting BDMA overlay bits in BDMA control register. the IDMA port select (IS) and address latch enable (IAL) directs the ADSP-2185M to write the address onto the IAD0–14 bus The BMWAIT field, which has 4 bits on ADSP-2185M, allows into the IDMA Control Register. If Bit 15 is set to 0, IDMA selection up to 15 wait states for BDMA transfers. latches the address. If Bit 15 is set to 1, IDMA latches into the Internal Memory DMA Port (IDMA Port; Host Memory OVLAY register. This register, shown below, is memory mapped Mode) at address DM (0x3FE0). Note that the latched address (IDMAA) The IDMA Port provides an efficient means of communication cannot be read back by the host. When Bit 14 in 0x3FE7 is set between a host system and the ADSP-2185M. The port is used to 1, timing in Figure 31 applies for short reads. When Bit 14 to access the on-chip program memory and data memory of the in 0x3FE7 is set to zero, short reads use the timing shown in Fig- DSP with only one DSP cycle per word overhead. The IDMA ure 32. For ADSP-2185M, IDDMOVLAY and IDPMOVLAY port cannot, however, be used to write to the DSP’s memory- bits in IDMA overlay register should be set to zero. mapped control registers. A typical IDMA transfer process is Refer to the following figures for more information on IDMA described as follows: and DMA memory maps. 1. Host starts IDMA transfer 2. Host checks IACK control line to see if the DSP is busy IDMA OVERLAY 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3. Host uses IS and IAL control lines to latch either the DMA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x3FE7) starting address (IDMAA) or the PM/DM OVLAY selection into the DSP’s IDMA control registers. If Bit 15 = 1, the RESERVED SET TO 0 IDDMOVLAY IDPMOVLAY value of bits 7:0 represent the IDMA overlay: bits 14:8 must SHORT READ ONLY 0 = ENABLE be set to 0. If Bit 15 = 0, the value of Bits 13:0 represent the RESERVED SET TO 0 1 = DISABLE starting address of internal memory to be accessed and IDMA CONTROL (U = UNDEFINED AT RESET) Bit 14 reflects PM or DM for access. For ADSP-2185M, 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDDMOVLAY and IDPMOVLAY bits in IDMA overlay 0 U U U U U U U U U U U U U U U DM (0x3FE0) register should be set to zero. IDMAA ADDRESS 4. Host uses IS and IRD (or IWR) to read (or write) DSP inter- IDMAD DESTINATION MEMORY TYPE nal memory (PM or DM). 0 = PM RESERVED SET TO 0 1 = DM 5. Host checks IACK line to see if the DSP has completed the NOTES: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS previous IDMA operation. SHOULD ALWAYS BE WRITTEN WITH ZEROS. 6. Host ends IDMA transfer. Figure 10.IDMA Control/OVLAY Registers The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The IDMA port is com- DMA DMA PROGRAM MEMORY DATA MEMORY pletely asynchronous and can be written while the ADSP-2185M OVLAY OVLAY is operating at full speed. ALWAYS ALWAYS The DSP memory address is latched and then automatically incre- ACCESSIBLE ACCESSIBLE mented after each IDMA transaction. An external device can AT ADDRESS AT ADDRESS 0x0000 – 0x1FFF 0x2000 – 0x3FFF therefore access a block of sequentially addressed memory by specifying only the starting address of the block. This increases 0x2000 – 0x0000 – throughput as the address does not have to be sent for each 0x3FFF 0x1FFF ACCESSIBLE WHEN ACCESSIBLE WHEN memory access. PMOVLAY = 0 DMOVLAY = 0 IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by NOTE: IDMA AND BDMA HAVE SEPARATE DMA CONTROL REGISTERS. an external device. The address specifies an on-chip memory Figure 11.Direct Memory Access—PM and DM location, the destination type specifies whether it is a DM or Memory Maps PM access. The falling edge of the IDMA address latch signal Bootstrap Loading (Booting) (IAL) or the missing edge of the IDMA select signal (IS) latches The ADSP-2185M has two mechanisms to allow automatic load- this value into the IDMAA register. ing of the internal program memory after reset. The method for Once the address is stored, data can be read from, or written to, booting is controlled by the Mode A, B, and C configuration bits. the ADSP-2185M’s on-chip memory. Asserting the select line When the MODE pins specify BDMA booting, the ADSP-2185M (IS) and the appropriate read or write line (IRD and IWR initiates a BDMA boot sequence when reset is released. respectively) signals the ADSP-2185M that a particular transac- tion is required. In either case, there is a one-processor-cycle The BDMA interface is set up during reset to the following delay for synchronization. The memory access consumes one defaults when BDMA booting is specified: the BDIR, BMPAGE, additional processor cycle. BIAD, and BEAD registers are set to 0, the BTYPE register is set to 0 to specify program memory 24-bit words, and the Once an access has occurred, the latched address is automati- BWCOUNT register is set to 32. This causes 32 words of cally incremented, and another access can occur. on-chip program memory to be loaded from byte memory. REV. 0 –15–

ADSP-2185M These 32 words are used to set up the BDMA to load in the read and write the values on the pins. Data being read from a remaining program code. The BCR bit is also set to 1, which pin configured as an input is synchronized to the ADSP-2185M’s causes program execution to be held off until all 32 words are clock. Bits that are programmed as outputs will read the value loaded into on-chip program memory. Execution then begins at being output. The PF pins default to input during reset. address 0. In addition to the programmable flags, the ADSP-2185M has five The ADSP-2100 Family development software (Revision 5.02 fixed-mode flags, FI, FO, FL0, FL1, and FL2. FL0–FL2 are and later) fully supports the BDMA booting feature and can dedicated output flags. FI and FO are available as an alternate generate byte memory space compatible boot code. configuration of SPORT1. The IDLE instruction can also be used to allow the processor Note: Pins PF0, PF1, PF2, and PF3 are also used for device to hold off execution while booting continues through the configuration during reset. BDMA interface. For BDMA accesses while in Host Mode, the Instruction Set Description addresses to boot memory must be constructed externally to the The ADSP-2185M assembly language instruction set has an ADSP-2185M. The only memory address bit provided by the algebraic syntax that was designed for ease of coding and read- processor is A0. ability. The assembly language, which takes full advantage of the IDMA Port Booting processor’s unique architecture, offers the following benefits: The ADSP-2185M can also boot programs through its Internal • The algebraic syntax eliminates the need to remember cryptic DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the assembler mnemonics. For example, a typical arithmetic add ADSP-2185M boots from the IDMA port. IDMA feature can instruction, such as AR = AX0 + AY0, resembles a simple load as much on-chip memory as desired. Program execution is equation. held off until on-chip program memory location 0 is written to. • Every instruction assembles into a single, 24-bit word that Bus Request and Bus Grant can execute in a single instruction cycle. The ADSP-2185M can relinquish control of the data and address • The syntax is a superset ADSP-2100 Family assembly lan- buses to an external device. When the external device requires guage and is completely source and object code compatible access to memory, it asserts the bus request (BR) signal. If the with other family members. Programs may need to be relocated ADSP-2185M is not performing an external memory access, it to utilize on-chip memory and conform to the ADSP-2185M’s responds to the active BR input in the following processor cycle by: interrupt vector and reset vector map. • Three-stating the data and address buses and the PMS, DMS, • Sixteen condition codes are available. For conditional jump, BMS, CMS, IOMS, RD, WR output drivers, call, return, or arithmetic instructions, the condition can • Asserting the bus grant (BG) signal, and be checked and the operation executed in the same instruc- • Halting program execution. tion cycle. If Go Mode is enabled, the ADSP-2185M will not halt program • Multifunction instructions allow parallel execution of an execution until it encounters an instruction that requires an arithmetic instruction with up to two fetches or one write to external memory access. processor memory space during a single instruction cycle. If the ADSP-2185M is performing an external memory access DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM when the external device asserts the BR signal, it will not three- The ADSP-2185M has on-chip emulation support and an state the memory interfaces nor assert the BG signal until the ICE-Port, a special set of pins that interface to the EZ-ICE. processor cycle after the access completes. The instruction does These features allow in-circuit emulation without replacing the not need to be completed when the bus is granted. If a single target system processor by using only a 14-pin connection from instruction requires two external memory accesses, the bus will the target system to the EZ-ICE. Target systems must have a be granted between the two accesses. 14-pin connector to accept the EZ-ICE’s in-circuit probe, a When the BR signal is released, the processor releases the BG 14-pin plug. signal, re-enables the output drivers, and continues program Issuing the chip reset command during emulation causes the execution from the point at which it stopped. DSP to perform a full chip reset, including a reset of its memory The bus request feature operates at all times, including when mode. Therefore, it is vital that the mode pins are set correctly the processor is booting and when RESET is active. PRIOR to issuing a chip reset command from the emulator user The BGH pin is asserted when the ADSP-2185M requires the interface. If a passive method of maintaining mode information is external bus for a memory or BDMA access, but is stopped. being used (as discussed in Setting Memory Modes), it does not The other device can release the bus by deasserting bus request. matter that the mode information is latched by an emulator Once the bus is released, the ADSP-2185M deasserts BG and reset. However, if the RESET pin is being used as a method of BGH and executes the external memory access. setting the value of the mode pins, the effects of an emulator reset must be taken into consideration. Flag I/O Pins The ADSP-2185M has eight general purpose programmable One method of ensuring that the values located on the mode input/output flag pins. They are controlled by two memory pins are those desired is to construct a circuit like the one shown mapped registers. The PFTYPE register determines the direc- in Figure 12. This circuit forces the value located on the Mode tion, 1 = output and 0 = input. The PFDATA register is used to A pin to logic high; regardless of whether it is latched via the RESET or ERESET pin. –16– REV. 0

ADSP-2185M The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca- ERESET tion—Pin 7 must be removed from the header. The pins must RESET be 0.025 inch square and at least 0.20 inch in length. Pin spac- ing should be 0.1 × 0.1 inches. The pin strip header must have ADSP-2185M at least 0.15 inch clearance on all sides to accept the EZ-ICE 1k(cid:3) probe plug. MODE A/PFO Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec. PROGRAMMABLE I/O Target Memory Interface Figure 12.Mode A Pin/EZ-ICE Circuit For your target system to be compatible with the EZ-ICE See the ADSP-2100 Family EZ-Tools data sheet for complete emulator, it must comply with the memory interface guidelines information on ICE products. listed below. The ICE-Port interface consists of the following ADSP-2185M pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS, PM, DM, BM, IOM, AND CM and ELOUT Design your Program Memory (PM), Data Memory (DM), Byte Memory (BM), I/O Memory (IOM), and Composite Memory These ADSP-2185M pins must be connected only to the EZ-ICE (CM) external interfaces to comply with worst case device tim- connector in the target system. These pins have no function except ing requirements and switching characteristics as specified in during emulation, and do not require pull-up or pull-down this data sheet. The performance of the EZ- ICE may approach resistors. The traces for these signals between the ADSP-2185M published worst-case specification for some memory access and the connector must be kept as short as possible, no longer timing requirements and switching characteristics. than 3 inches. Note: If your target does not meet the worst-case chip specifica- The following pins are also used by the EZ-ICE: BR, BG, tion for memory access parameters, you may not be able to RESET, and GND. emulate your circuitry at the desired CLKIN frequency. Depend- The EZ-ICE uses the EE (emulator enable) signal to take con- ing on the severity of the specification violation, you may have trol of the ADSP-2185M in the target system. This causes the trouble manufacturing your system as DSP components statisti- processor to use its ERESET, EBR, and EBG pins instead of cally vary in switching characteristic and timing requirements the RESET, BR, and BG pins. The BG output is three-stated. within published limits. These signals do not need to be jumper-isolated in your system. Restriction: All memory strobe signals on the ADSP-2185M The EZ-ICE connects to your target system via a ribbon cable (RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your and a 14-pin female plug. The female plug is plugged onto the target system must have 10 kΩ pull-up resistors connected when 14-pin connector (a pin strip header) on the target board. the EZ-ICE is being used. The pull-up resistors are necessary because there are no internal pull-ups to guarantee their state Target Board Connector for EZ-ICE Probe during prolonged three-state conditions resulting from typical The EZ-ICE connector (a standard pin strip header) is shown in EZ-ICE debugging sessions. These resistors may be removed at Figure 13. You must add this connector to your target board your option when the EZ-ICE is not being used. design if you intend to use the EZ-ICE. Be sure to allow enough room in your system to fit the EZ-ICE probe onto the 14-pin Target System Interface Signals connector. When the EZ-ICE board is installed, the performance on some system signals change. Design your system to be compatible with the following system interface signal changes introduced by 1 2 GND BG the EZ-ICE board: 3 4 • EZ-ICE emulation introduces an 8 ns propagation delay EBG BR 5 6 between your target circuitry and the DSP on the RESET EBR EINT signal. 7 8 KEY (NO PIN) (cid:1) ELIN • EZ-ICE emulation introduces an 8 ns propagation delay 9 10 between your target circuitry and the DSP on the BR signal. ELOUT ECLK - 11 12 • EZ-ICE emulation ignores RESET and BR when single- EE EMS stepping. 13 14 RESET ERESET • EZ-ICE emulation ignores RESET and BR when in Emulator Space (DSP halted). TOP VIEW • EZ-ICE emulation ignores the state of target BR in certain Figure 13.Target Board Connector for EZ-ICE modes. As a result, the target system may take control of the DSP’s external memory bus only if bus grant (BG) is asserted by the EZ- ICE board’s DSP. REV. 0 –17–

ADSP-2185M–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade B Grade Parameter Min Max Min Max Unit V 2.37 2.63 2.25 2.75 V DDINT V 2.37 3.6 2.25 3.6 V DDEXT V 1 V = –0.3 V = +3.6 V = –0.3 V = +3.6 V INPUT IL IH IL IH T 0 +70 –40 +85 °C AMB NOTES 1The ADSP-2185M is 3.3 V tolerant (always accepts up to 3.6 V max V ), but voltage compliance (on outputs, V ) depends on the input V ; because V (max) IH OH DDEXT OH ≈ V (max). This applies to bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7) and input only pins (CLKIN, RESET, DDEXT BR, DR0, DR1, PWD). Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS K/B Grades Parameter Test Conditions Min Typ Max Unit V Hi-Level Input Voltage1, 2 @ V = max 1.5 V IH DDINT V Hi-Level CLKIN Voltage @ V = max 2.0 V IH DDINT V Lo-Level Input Voltage1, 3 @ V = min 0.7 V IL DDINT V Hi-Level Output Voltage1, 4, 5 @ V = min, I = –0.5 mA 2.0 V OH DDEXT OH @ V = 3.0 V, I = –0.5 mA 2.4 V DDEXT OH @ V = min, I = –100 µA6 V – 0.3 V DDEXT OH DDEXT V Lo-Level Output Voltage1, 4, 5 @ V = min, I = 2 mA 0.4 V OL DDEXT OL I Hi-Level Input Current3 @ V = max, V = 3.6 V 10 µA IH DDINT IN I Lo-Level Input Current3 @ V = max, V = 0 V 10 µA IL DDINT IN I Three-State Leakage Current7 @ V = max, V = 3.6 V8 10 µA OZH DDEXT IN I Three-State Leakage Current7 @ V = max, V = 0 V8 10 µA OZL DDEXT IN I Supply Current (Idle)9 @ V = 2.5, t = 15 ns 9 mA DD DDINT CK I Supply Current (Idle)9 @ V = 2.5, t = 13.3 ns 10 mA DD DDINT CK I Supply Current (Dynamic)10 @ V = 2.5, t = 15 ns11, T = 25°C 35 mA DD DDINT CK AMB I Supply Current (Dynamic)10 @ V = 2.5, t = 13.3 ns11, T = 25°C 38 mA DD DDINT CK AMB I Supply Current (Power-Down)12 @ V = 2.5, T = 25°C in Lowest 100 µA DD DDINT AMB Power Mode C Input Pin Capacitance3, 6 @ V = 2.5 V, f = 1.0 MHz, T = 25°C 8 pF I IN IN AMB C Output Pin Capacitance6, 7, 12, 13 @ V = 2.5 V, f = 1.0 MHz, T = 25°C 8 pF O IN IN AMB NOTES 1Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7. 2Input only pins: RESET, BR, DR0, DR1, PWD. 3Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD. 4Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH. 5Although specified for TTL outputs, all ADSP-2185M outputs are CMOS-compatible and will drive to V and GND, assuming no dc loads. DDEXT 6Guaranteed but not tested. 7Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7. 80 V on BR. 9Idle refers to ADSP-2185M state of operation during execution of IDLE instruction. Deasserted pins are driven to either V or GND. DD 10I measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2 DD and Type 6, and 20% are idle instructions. 11V = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section. IN 12See Chapter 9 of the ADSP-2100 Family User’s Manual for details. 13Output pin capacitance is the capacitive load for any three-stated output pin. Specifications subject to change without notice. –18– REV. 0

ADSP-2185M ABSOLUTE MAXIMUM RATINGS1 NOTES 1Stresses greater than those listed may cause permanent damage to the device. Value These are stress ratings only; functional operation of the device at these or any other Parameter Min Max conditions greater than those indicated in the operational sections of this specifi- cation is not implied. Exposure to absolute maximum rating conditions for Internal Supply Voltage (V ) –0.3 V +3.0 V DDINT extended periods may affect device reliability. External Supply Voltage (VDDEXT) –0.3 V +4.0 V 2Applies to Bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, Input Voltage2 –0.5 V +4.0 V TFS1, A1–A13, PF0–PF7) and Input only pins (CLKIN, RESET, BR, DR0, Output Voltage Swing3 –0.5 V V + 0.5 V DR1, PWD). Operating Temperature Range –40°C +8D5D°ECXT 3Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH). Storage Temperature Range –65°C +150°C Lead Temperature (5 sec) LQFP 280°C ESD SENSITIVITY ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2185M features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE TIMING SPECIFICATIONS Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a GENERAL NOTES read operation. Timing requirements guarantee that the proces- Use the exact timing information given. Do not attempt to sor operates correctly with other devices. derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for MEMORY TIMING SPECIFICATIONS an individual device, the values given in this data sheet reflect The table below shows common memory device specifications statistical variations and worst cases. Consequently, you cannot and the corresponding ADSP-2185M timing parameters, for meaningfully add up parameters to derive longer times. your convenience. TIMING NOTES Memory Timing Switching characteristics specify how the processor changes its Device Parameter signals. You have no control over this timing—circuitry external Specification Parameter Definition1 to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the Address Setup to tASW A0–A13, xMS Setup before processor will do in a given circumstance. You can also use Write Start WR Low switching characteristics to ensure that any timing require- Address Setup to t A0–A13, xMS Setup before AW ment of a device connected to the processor (such as memory) Write End WR Deasserted is satisfied. Address Hold Time t A0–A13, xMS Hold before WRA WR Low Data Setup Time t Data Setup before WR DW High Data Hold Time t Data Hold after WR High DH OE to Data Valid t RD Low to Data Valid RDD Address Access Time t A0–A13, xMS to Data Valid AA NOTE 1xMS = PMS, DMS, BMS, CMS or IOMS. REV. 0 –19–

ADSP-2185M FREQUENCY DEPENDENCY FOR TIMING • Each address and data pin has a 10 pF total load at the pin. SPECIFICATIONS • The application operates at V = 3.3 V and t = 30 ns. DDEXT CK t is defined as 0.5 t . The ADSP-2185M uses an input clock CK CKI Total Power Dissipation = P + (C × V 2 × f) with a frequency equal to half the instruction rate. For example, INT DDEXT a 37.50 MHz input clock (which is equivalent to 26.6 ns) yields P = internal power dissipation from Power vs. Frequency INT a 13.3 ns processor cycle (equivalent to 75 MHz). t values graph (Figure 15). CK within the range of 0.5 t period should be substituted for all CKI (C × V 2 × f) is calculated for each output: relevant timing parameters to obtain the specification value. DDEXT Example: t = 0.5 t – 2 ns = 0.5 (15 ns) – 2 ns = 5.5 ns CKH CK # of (cid:1) C (cid:1) V 2 (cid:1) f PD DDEXT Parameters Pins pF V MHz mW ENVIRONMENTAL CONDITIONS1 Address 7 10 3.32 16.67 12.7 Rating Data Output, WR 9 10 3.32 16.67 16.3 Description Symbol LQFP Mini-BGA RD 1 10 3.32 16.67 1.8 Thermal Resistance θ 48°C/W 63.3°C/W CLKOUT, DMS 2 10 3.32 33.3 7.2 CA (Case-to-Ambient) 38.0 Thermal Resistance θ 50°C/W 70.7°C/W JA Total power dissipation for this example is P + 38.0 mW. (Junction-to-Ambient) INT Thermal Resistance θJC 2°C/W 7.4°C/W Output Drive Currents (Junction-to-Case) Figure 14 shows typical I-V characteristics for the output drivers on the ADSP-2185M. The curves represent the current drive NOTE 1Where the Ambient Temperature Rating (T ) is: capability of the output drivers as a function of output voltage. AMB T = T – (PD × θ ) AMB CASE CA TCASE = Case Temperature in °C 80 PD = Power Dissipation in W POWER DISSIPATION 60 VDDEXT = 3.6V @ –40(cid:4)C VOH To determine total power dissipation in a specific application, mA 40 VDDEXT = 3.3V @ +25(cid:4)C the following equation should be applied for each output: – T 20 N C × V 2 × f RE VDDEXT = 2.5V @ +85(cid:4)C DD UR 0 C = load capacitance, f = output switching frequency. E C RC–20 VDDEXT = 3.6V @ –40(cid:4)C Example: U In an application where external data memory is used and no other SO–40 VOL VDDEXT = 2.5V @ +85(cid:4)C VDDEXT = 3.3V @ +25(cid:4)C outputs are active, power dissipation is calculated as follows: –60 Assumptions: –80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 • External data memory is accessed every cycle with 50% of the SOURCE VOLTAGE – V address pins switching. Figure 14.Typical Output Driver Characteristics • External data memory writes occur every other cycle with 50% of the data pins switching. –20– REV. 0

ADSP-2185M POWER, INTERNAL1, 2, 3 Capacitive Loading 115 Figure 16 and Figure 17 show the capacitive loading character- 110mW 110 istics of the ADSP-2185M. 105 mW100 VDD = 2.65V 95mW 30 – 95 T = 85(cid:4)C POWER (P) INT7788905050 8720mmWW VVDDDD == 22..53V5V 82mW –2.4V) – ns2250 VDD = 0V TO 2.0V V 65 61mW 0.415 60 ME ( 55 TI 50 55 60 65 70 75 80 E 10 S 1/tCK – MHz RI POWER, IDLE1, 2, 4 5 30 28mW 28 0 VDD = 2.65V 0 50 100 150 200 250 300 26 CL – pF ) – mWE 24 24mW VDD = 2.5V 24mW (Faigt uMraex 1im6.uTmy pAicmabl Oieunttp Oupt eRriastei nTgim Tee mvsp.e Lroaatudr eC)apacitance DL 22 WER (PI 20 20mW VDD = 2.35V 20mW 18 PO 18 16 16.5mW ns 14 16 LD – 12 1450 55 60 65 70 75 80 R HO 10 1/tCK – MHz Y O 8 A POWER, IDLE n MODES2 EL 6 26 D T 4 24 24mW IDLE UTPU 2 mW 22 ALID ONOMINA–L2 n) – E 20 20mW V –4 DL –6 PI 0 50 100 150 200 250 ER ( 18 16.4mW CL – pF OW 16 15mW IIDDLLEE ((11268)) Figure 17.Typical Output Valid Delay or Hold vs. Load P 15.7mW Capacitance, C (at Maximum Ambient Operating 14 L 14.25mW Temperature) 12 50 55 60 65 70 75 80 1/tCK – MHz NOTES: VALID FOR ALL TEMPERATURE GRADES. 1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. 2TYPICAL POWER DISSIPATION AT 2.5V VDDINT AND 25(cid:4)C, EXCEPT WHERE SPECIFIED. 3IDD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. 4IDLE REFERS TO STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND. Figure 15.Power vs. Frequency REV. 0 –21–

ADSP-2185M TEST CONDITIONS Output Enable Time Output Disable Time Output pins are considered to be enabled when they have made Output pins are considered to be disabled when they have stopped a transition from a high-impedance state to when they start driving. driving and started a transition from the measured output high The output enable time (t ) is the interval from when a refer- ENA or low voltage to a high impedance state. The output disable ence signal reaches a high or low voltage level to when the output time (t ) is the difference of t and t , as shown has reached a specified high or low trip point, as shown Figure DIS MEASURED DECAY in the Output Enable/Disable diagram. The time is the interval 19. If multiple pins (such as the data bus) are enabled, the mea- from when a reference signal reaches a high or low voltage level surement value is that of the first pin to start driving. to when the output voltages have changed by 0.5 V from the measured output high or low voltage. REFERENCE SIGNAL The decay time, t , is dependent on the capacitive load, DECAY t C , and the current load, i , on the output pin. It can be MEASURED L L tENA approximated by the following equation: VOH tDIS VOH (MEASURED) (MEASURED) C ×0.5V t = L VOH (MEASURED) – 0.5V 2.0V DECAY iL OUTPUT VOL (MEASURED) +0.5V 1.0V from which VOL t VOL (MEASURED) DECAY (MEASURED) t = t – t DIS MEASURED DECAY OUTPUT is calculated. If multiple pins (such as the data bus) are disabled, OUTPUT STOPS STARTS DRIVING DRIVING the measurement value is that of the last pin to stop driving. HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V. Figure 19.Output Enable/Disable INPUT 1.5V IOL 2.0V OUTPUT 1.5V 0.8V Figure 18.Voltage Reference Levels for AC Measure- TO ments (Except Output Enable/Disable) OUTPUT 1.5V PIN 50pF IOH Figure 20.Equivalent Loading for AC Measurements (Including All Fixtures) –22– REV. 0

ADSP-2185M Parameter Min Max Unit Clock Signals and Reset Timing Requirements: t CLKIN Period 26.6 80 ns CKI t CLKIN Width Low 8 ns CKIL t CLKIN Width High 8 ns CKIH Switching Characteristics: t CLKOUT Width Low 0.5t – 2 ns CKL CK t CLKOUT Width High 0.5t – 2 ns CKH CK t CLKIN High to CLKOUT High 0 13 ns CKOH Control Signals Timing Requirements: t RESET Width Low 5t 1 ns RSP CK t Mode Setup before RESET High 2 ns MS t Mode Hold after RESET High 5 ns MH NOTE 1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). t CKI t CKIH CLKIN t CKIL t CKOH t CKH CLKOUT t CKL PF(3:0)* tMS tMH RESET t RSP *PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A Figure 21.Clock Signals REV. 0 –23–

ADSP-2185M Parameter Min Max Unit Interrupts and Flags Timing Requirements: t IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4 0.25t + 10 ns IFS CK t IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4 0.25t ns IFH CK Switching Characteristics: t Flag Output Hold after CLKOUT Low5 0.5t – 5 ns FOH CK t Flag Output Delay from CLKOUT Low5 0.5t + 4 ns FOD CK NOTES 1If IRQx and FI inputs meet t and t setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on IFS IFH the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual for further information on interrupt servicing.) 2Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE. 4PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7. 5Flag Outputs = PFx, FL0, FL1, FL2, FO. t FOD CLKOUT t FOH FLAG OUTPUTS t IFH IRQx FI PFx t IFS Figure 22.Interrupts and Flags –24– REV. 0

ADSP-2185M Parameter Min Max Unit Bus Request–Bus Grant Timing Requirements: t BR Hold after CLKOUT High1 0.25t + 2 ns BH CK t BR Setup before CLKOUT Low1 0.25t + 10 ns BS CK Switching Characteristics: t CLKOUT High to xMS, RD, WR Disable 0.25t + 8 ns SD CK t xMS, RD, WR Disable to BG Low 0 ns SDB t BG High to xMS, RD, WR Enable 0 ns SE t xMS, RD, WR Enable to CLKOUT High 0.25t – 3 ns SEC CK t xMS, RD, WR Disable to BGH Low2 0 ns SDBH t BGH High to xMS, RD, WR Enable2 0 ns SEH NOTES xMS = PMS, DMS, CMS, IOMS, BMS. 1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships. 2BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue. t BH CLKOUT BR t BS CLKOUT PMS, DMS BMS, RD WR tSD tSEC BG t SDB t SE BGH t SDBH t SEH Figure 23.Bus Request–Bus Grant REV. 0 –25–

ADSP-2185M Parameter Min Max Unit Memory Read Timing Requirements: t RD Low to Data Valid 0.5t – 5 + w ns RDD CK t A0–A13, xMS to Data Valid 0.75t – 6 + w ns AA CK t Data Hold from RD High 0 ns RDH Switching Characteristics: t RD Pulsewidth 0.5t – 3 + w ns RP CK t CLKOUT High to RD Low 0.25t – 2 0.25t + 4 ns CRD CK CK t A0–A13, xMS Setup before RD Low 0.25t – 3 ns ASR CK t A0–A13, xMS Hold after RD Deasserted 0.25t – 3 ns RDA CK t RD High to RD or WR Low 0.5t – 3 ns RWR CK NOTES w = wait states x t . CK xMS = PMS, DMS, CMS, IOMS, BMS. CLKOUT A0–A13 DMS, PMS, BMS, IOMS, CMS t RDA RD t ASR tCRD tRP tRWR D0–D23 tRDD tRDH t AA WR Figure 24.Memory Read –26– REV. 0

ADSP-2185M Parameter Min Max Unit Memory Write Switching Characteristics: t Data Setup before WR High 0.5t – 4 + w ns DW CK t Data Hold after WR High 0.25t – 1 ns DH CK t WR Pulsewidth 0.5t – 3 + w ns WP CK t WR Low to Data Enabled 0 ns WDE t A0–A13, xMS Setup before WR Low 0.25t – 3 ns ASW CK t Data Disable before WR or RD Low 0.25t – 3 ns DDR CK t CLKOUT High to WR Low 0.25t – 2 0.25 t + 4 ns CWR CK CK t A0–A13, xMS, Setup before WR Deasserted 0.75t – 5 + w ns AW CK t A0–A13, xMS Hold after WR Deasserted 0.25t – 1 ns WRA CK t WR High to RD or WR Low 0.5t – 3 ns WWR CK NOTES w = wait states x t CK. xMS = PMS, DMS, CMS, IOMS, BMS. CLKOUT A0–A13 DMS, PMS, BMS, CMS, IOMS t WRA WR tASW tWP tWWR t AW t t t DH DDR CWR D0–D23 t DW t WDE RD Figure 25.Memory Write REV. 0 –27–

ADSP-2185M Serial Ports Parameter Min Max Unit Serial Ports Timing Requirements: t SCLK Period 26.6 ns SCK t DR/TFS/RFS Setup before SCLK Low 4 ns SCS t DR/TFS/RFS Hold after SCLK Low 7 ns SCH t SCLKIN Width 12 ns SCP Switching Characteristics: t CLKOUT High to SCLKOUT 0.25t 0.25t + 6 ns CC CK CK t SCLK High to DT Enable 0 ns SCDE t SCLK High to DT Valid 12 ns SCDV t TFS/RFS Hold after SCLK High 0 ns RH OUT t TFS/RFS Delay from SCLK High 12 ns RD OUT t DT Hold after SCLK High 0 ns SCDH t TFS (Alt) to DT Enable 0 ns TDE t TFS (Alt) to DT Valid 12 ns TDV t SCLK High to DT Disable 12 ns SCDD t RFS (Multichannel, Frame Delay Zero) to DT Valid 12 ns RDV CLKOUT tCC tCC tSCK SCLK t SCP tSCS tSCH tSCP DR TFSIN RFSIN t RD t RH RFSOUT TFSOUT t t SCDD SCDV tSCDE tSCDH DT t TDE t TDV TFSOUT ALTERNATE FRAME MODE t RDV RFSOUT MULTICHANNEL MODE, FRAME DELAY 0 t (MFD = 0) TDE t TDV TFSIN ALTERNATE FRAME MODE t RDV RFSIN MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0) Figure 26.Serial Ports –28– REV. 0

ADSP-2185M Parameter Min Max Unit IDMA Address Latch Timing Requirements: t Duration of Address Latch1, 2 10 ns IALP t IAD15–0 Address Setup before Address Latch End2 5 ns IASU t IAD15–0 Address Hold after Address Latch End2 3 ns IAH t IACK Low before Start of Address Latch2, 3 0 ns IKA t Start of Write or Read after Address Latch End2, 3 3 ns IALS t Address Latch Start after Address Latch End1, 2 2 ns IALD NOTES 1Start of Address Latch = IS Low and IAL High. 2End of Address Latch = IS High or IAL Low. 3Start of Write or Read = IS Low and IWR Low or IRD Low. IACK t IKA t IALD IAL t t IALP IALP IS IAD15–0 t t IASU t IASU t IAH IAH t IALS IRD OR IWR Figure 27.IDMA Address Latch REV. 0 –29–

ADSP-2185M Parameter Min Max Unit IDMA Write, Short Write Cycle Timing Requirements: t IACK Low before Start of Write1 0 ns IKW t Duration of Write1, 2 10 ns IWP t IAD15–0 Data Setup before End of Write2, 3, 4 3 ns IDSU t IAD15–0 Data Hold after End of Write2, 3, 4 2 ns IDH Switching Characteristic: t Start of Write to IACK High 10 ns IKHW NOTES 1Start of Write = IS Low and IWR Low. 2End of Write = IS High or IWR High. 3If Write Pulse ends before IACK Low, use specifications t , t . IDSU IDH 4If Write Pulse ends after IACK Low, use specifications t , t . IKSU IKH t IKW IACK t IKHW IS t IWP IWR t IDH t IDSU IAD15–0 DATA Figure 28.IDMA Write, Short Write Cycle –30– REV. 0

ADSP-2185M Parameter Min Max Unit IDMA Write, Long Write Cycle Timing Requirements: t IACK Low before Start of Write1 0 ns IKW t IAD15–0 Data Setup before End of Write2, 3, 4 0.5t + 5 ns IKSU CK t IAD15–0 Data Hold after End of Write2, 3, 4 0 ns IKH Switching Characteristics: t Start of Write to IACK Low4 1.5t ns IKLW CK t Start of Write to IACK High 10 ns IKHW NOTES 1Start of Write = IS Low and IWR Low. 2If Write Pulse ends before IACK Low, use specifications t , t . IDSU IDH 3If Write Pulse ends after IACK Low, use specifications t , t . IKSU IKH 4This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual. t IKW IACK t IKHW t IKLW IS IWR t IKSU t IKH IAD15–0 DATA Figure 29.IDMA Write, Long Write Cycle REV. 0 –31–

ADSP-2185M Parameter Min Max Unit IDMA Read, Long Read Cycle Timing Requirements: t IACK Low before Start of Read1 0 ns IKR t End of read after IACK Low2 2 ns IRK Switching Characteristics: t IACK High after Start of Read1 10 ns IKHR t IAD15–0 Data Setup before IACK Low 0.5t – 2 ns IKDS CK t IAD15–0 Data Hold after End of Read2 0 ns IKDH t IAD15–0 Data Disabled after End of Read2 10 ns IKDD t IAD15–0 Previous Data Enabled after Start of Read 0 ns IRDE t IAD15–0 Previous Data Valid after Start of Read 11 ns IRDV t IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3 2t – 5 ns IRDH1 CK t IAD15–0 Previous Data Hold after Start of Read (PM2)4 t – 5 ns IRDH2 CK NOTES 1Start of Read = IS Low and IRD Low. 2End of Read = IS High or IRD High. 3DM read or first half of PM read. 4Second half of PM read. IACK t IKHR t IKR IS t IRK IRD tIRDE tIKDS tIKDH IAD15–0 PREVIOUS READ DATA DATA tIRDV tIKDD t t IRDH1 or IRDH2 Figure 30.IDMA Read, Long Read Cycle –32– REV. 0

ADSP-2185M Parameter Min Max Unit IDMA Read, Short Read Cycle1, 2 Timing Requirements: t IACK Low before Start of Read3 0 ns IKR t Duration of Read (DM/PM1)4 10 2t – 5 ns IRP1 CK t Duration of Read (PM2)5 10 t – 5 ns IRP2 CK Switching Characteristics: t IACK High after Start of Read3 10 ns IKHR t IAD15–0 Data Hold after End of Read6 0 ns IKDH t IAD15–0 Data Disabled after End of Read6 10 ns IKDD t IAD15–0 Previous Data Enabled after Start of Read 0 ns IRDE t IAD15–0 Previous Data Valid after Start of Read 10 ns IRDV NOTES 1Short Read Only must be disabled in the IDMA Overlay memory mapped register. 2Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies. 3Start of Read = IS Low and IRD Low. 4DM Read or first half of PM Read. 5Second half of PM Read. 6End of Read = IS High or IRD High. IACK t IKR t IKHR IS t IRP IRD tIRDE tIKDH IAD15–0 PREVIOUS DATA tIRDV tIKDD Figure 31.IDMA Read, Short Read Cycle REV. 0 –33–

ADSP-2185M Parameter Min Max Unit IDMA Read, Short Read Cycle in Short Read Only Mode1 Timing Requirements: t IACK Low before Start of Read2 0 ns IKR t Duration of Read3 10 ns IRP Switching Characteristics: t IACK High after Start of Read2 10 ns IKHR t IAD15–0 Previous Data Hold after End of Read3 0 ns IKDH t IAD15–0 Previous Data Disabled after End of Read3 10 ns IKDD t IAD15–0 Previous Data Enabled after Start of Read 0 ns IRDE t IAD15–0 Previous Data Valid after Start of Read 10 ns IRDV NOTES 1Short Read Only is enabled by setting Bit 14 of the IDMA Overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the register or by an external host writing to the register. Disabled by default. 2Start of Read = IS Low and IRD Low. Previous data remains until end of read. 3End of Read = IS High or IRD High. IACK t IKR t IKHR IS t IRP IRD tIRDE tIKDH IAD15–0 PREVIOUS DATA tIRDV tIKDD Figure 32.IDMA Read, Short Read Only Cycle –34– REV. 0

ADSP-2185M 100-LEAD LQFP PIN CONFIGURATION A]B] C]D] E E E E A3/IAD2A2/IAD1 A1/IAD0A0 PWDACK BGH PF0 [MODPF1 [MOD GND PWDVDDEXT PF2 [MODPF3 [MOD FL0 FL1FL2 D23 D22 D21 D20 GNDD19 D18 D17 D16 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A4/IAD3 1 75 D15 A5/IAD4 2 PIN 1 74 D14 IDENTIFIER GND 3 73 D13 A6/IAD5 4 72 D12 A7/IAD6 5 71 GND A8/IAD7 6 70 D11 A9/IAD8 7 69 D10 A10/IAD9 8 68 D9 A11/IAD10 9 67 VDDEXT A12/IAD11 10 66 GND A13/IAD12 11 65 D8 GND 12 64 D7/IWR ADSP-2185M CLKIN 13 63 D6/IRD XTAL 14 TOP VIEW 62 D5/IAL (Not to Scale) VDDEXT 15 61 D4/IS CLKOUT 16 60 GND GND 17 59 VDDINT VDDINT 18 58 D3/IACK WR 19 57 D2/IAD15 RD 20 56 D1/IAD14 BMS 21 55 D0/IAD13 DMS 22 54 BG PMS 23 53 EBG IOMS 24 52 BR CMS 25 51 EBR 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 +PF4IRQE +PF5IRQL0 GND +PF6IRQL1 +PF7IRQ2 DT0TFS0 RFS0 DR0SCLK0 VDDEXT DT1/FOTFS1/IRQ1 RFS1/IRQ0 DR1/FI GND SCLK1 ERESET RESET EMS EEECLK ELOUT ELIN EINT REV. 0 –35–

ADSP-2185M The LQFP package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode selectable by setting Bit 10 (SPORT1 configure) of the System Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external inter- rupt and flag pins. This bit is set to 1 by default upon reset. LQFP Package Pinout Pin Pin Pin Pin No. Pin Name No. Pin Name No. Pin Name No. Pin Name 1 A4/IAD3 26 IRQE + PF4 51 EBR 76 D16 2 A5/IAD4 27 IRQL0 + PF5 52 BR 77 D17 3 GND 28 GND 53 EBG 78 D18 4 A6/IAD5 29 IRQL1 + PF6 54 BG 79 D19 5 A7/IAD6 30 IRQ2 + PF7 55 D0/IAD13 80 GND 6 A8/IAD7 31 DT0 56 D1/IAD14 81 D20 7 A9/IAD8 32 TFS0 57 D2/IAD15 82 D21 8 A10/IAD9 33 RFS0 58 D3/IACK 83 D22 9 A11/IAD10 34 DR0 59 V 84 D23 DDINT 10 A12/IAD11 35 SCLK0 60 GND 85 FL2 11 A13/IAD12 36 V 61 D4/IS 86 FL1 DDEXT 12 GND 37 DT1/FO 62 D5/IAL 87 FL0 13 CLKIN 38 TFS1/IRQ1 63 D6/IRD 88 PF3 [MODE D] 14 XTAL 39 RFS1/IRQ0 64 D7/IWR 89 PF2 [MODE C] 15 V 40 DR1/FI 65 D8 90 V DDEXT DDEXT 16 CLKOUT 41 GND 66 GND 91 PWD 17 GND 42 SCLK1 67 V 92 GND DDEXT 18 V 43 ERESET 68 D9 93 PF1 [MODE B] DDINT 19 WR 44 RESET 69 D10 94 PF0 [MODE A] 20 RD 45 EMS 70 D11 95 BGH 21 BMS 46 EE 71 GND 96 PWDACK 22 DMS 47 ECLK 72 D12 97 A0 23 PMS 48 ELOUT 73 D13 98 A1/IAD0 24 IOMS 49 ELIN 74 D14 99 A2/IAD1 25 CMS 50 EINT 75 D15 100 A3/IAD2 –36– REV. 0

ADSP-2185M 144-Ball Mini-BGA Package Pinout (Bottom View) 12 11 10 9 8 7 6 5 4 3 2 1 GND GND D22 NC NC NC GND NC A0 GND A1/IAD0 A2/IAD1 A D16 D17 D18 D20 D23 VDDEXT GND NC NC GND A3/IAD2 A4/IAD3 B D14 NC D15 D19 D21 VDDEXT PWD A7/IAD6 A5/IAD4 RD A6/IAD5 PWDACK C GND NC D12 D13 NC [MOPDFE2 C] [MOPDFE1 B] A9/IAD8 BGH NC WR NC D D10 GND VDDEXT GND GND [MOPDFE3 D] FL2 [MOPDFE0 A] FL0 A8/IAD7 VDDEXT VDDEXT E D9 NC D8 D11 D7/IWR NC NC FL1 A11/IAD10 A12/IAD11 NC A13/IAD12 F D4/IS NC NC D5/IAL D6/IRD NC NC NC A10/IAD9 GND NC XTAL G GND NC GND D3/IACK D2/IAD15 TFS0 DT0 VDDINT GND GND GND CLKIN H VDDINT VDDINT D1/IAD14 BG RFS1/IRQ0 D0/IAD13 SCLK0 VDDEXT VDDEXT NC VDDINT CLKOUT J EBG BR EBR ERESET SCLK1 TFS1/IRQ1 RFS0 DMS BMS NC NC NC K EINT ELOUT ELIN RESET GND DR0 PMS GND IOMS IRQL1 + PF6 NC IRQE + PF4 L ECLK EE EMS NC GND DR1/FI DT1/FO GND CMS NC IRQ2 + PF7 IRQL0 + PF5 M REV. 0 –37–

ADSP-2185M The Mini-BGA package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode selectable by setting Bit 10 (SPORT1 configure) of the System Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external interrupt and flag pins. This bit is set to 1 by default upon reset. Mini-BGA Package Pinout Ball # Pin Name Ball # Pin Name Ball # Pin Name Ball # Pin Name A01 A2/IAD1 D01 NC G01 XTAL K01 NC A02 A1/IAD0 D02 WR G02 NC K02 NC A03 GND D03 NC G03 GND K03 NC A04 A0 D04 BGH G04 A10/IAD9 K04 BMS A05 NC D05 A9/IAD8 G05 NC K05 DMS A06 GND D06 PF1 [MODE B] G06 NC K06 RFS0 A07 NC D07 PF2 [MODE C] G07 NC K07 TFS1/IRQ1 A08 NC D08 NC G08 D6/IRD K08 SCLK1 A09 NC D09 D13 G09 D5/IAL K09 ERESET A10 D22 D10 D12 G10 NC K10 EBR A11 GND D11 NC G11 NC K11 BR A12 GND D12 GND G12 D4/IS K12 EBG B01 A4/IAD3 E01 V H01 CLKIN L01 IRQE + PF4 DDEXT B02 A3/IAD2 E02 V H02 GND L02 NC DDEXT B03 GND E03 A8/IAD7 H03 GND L03 IRQL1 + PF6 B04 NC E04 FL0 H04 GND L04 IOMS B05 NC E05 PF0 [MODE A] H05 V L05 GND DDINT B06 GND E06 FL2 H06 DT0 L06 PMS B07 V E07 PF3 [MODE D] H07 TFS0 L07 DR0 DDEXT B08 D23 E08 GND H08 D2/IAD15 L08 GND B09 D20 E09 GND H09 D3/IACK L09 RESET B10 D18 E10 V H10 GND L10 ELIN DDEXT B11 D17 E11 GND H11 NC L11 ELOUT B12 D16 E12 D10 H12 GND L12 EINT C01 PWDACK F01 A13/IAD12 J01 CLKOUT M01 IRQL0 + PF5 C02 A6/IAD5 F02 NC J02 V M02 IRQL2 + PF7 DDINT C03 RD F03 A12/IAD11 J03 NC M03 NC C04 A5/IAD4 F04 A11/IAD10 J04 V M04 CMS DDEXT C05 A7/IAD6 F05 FL1 J05 V M05 GND DDEXT C06 PWD F06 NC J06 SCLK0 M06 DT1/FO C07 V F07 NC J07 D0/IAD13 M07 DR1/FI DDEXT C08 D21 F08 D7/IWR J08 RFS1/IRQ0 M08 GND C09 D19 F09 D11 J09 BG M09 NC C10 D15 F10 D8 J10 D1/IAD14 M10 EMS C11 NC F11 NC J11 V M11 EE DDINT C12 D14 F12 D9 J12 V M12 ECLK DDINT –38– REV. 0

ADSP-2185M OUTLINE DIMENSIONS Dimensions shown in millimeters. 100-Lead Metric Thin Plastic Quad Flatpack (LQFP) (ST-100) 16.20 16.00 TYP SQ 15.80 14.05 14.00 TYP SQ 13.95 1.60 MAX 0.75 12.00 BSC 0.60 TYP 0.50 12(cid:4) 1100 7675 TYP SEATING PLANE TOP VIEW (PINS DOWN) 0.08 COPMLAANXA LREIATDY 6(cid:4) ± 4(cid:4) 2526 5051 0(cid:4) – 7(cid:4) 0.50 0.27 BSC 0.22 TYP 0.15 LEAD PITCH 0.17 0.05 LEAD WIDTH NOTE: THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. REV. 0 –39–

ADSP-2185M OUTLINE DIMENSIONS Dimensions shown in millimeters. 144-Ball Mini-BGA (CA-144) 0) 10.10 v. 10.00 SQ e 9.90 12 11 10 9 8 7 6 5 4 3 2 1 0 (r A 0 B 0/ C –1 10.10 B8.S8C0 DEF 7–3.5 TOP VIEW 10.00 SQ G 04 9.90 H 02 0.80 J C BSC K L M DETAIL A 0.80 BSC 8.80 BSC 1.40 MAX DETAIL A 1.00 NOTES: 0.85 1.THE ACTUAL POSITION OF THE BALL POPULATION 0.40 IS WITHIN 0.150 OF ITS IDEAL POSITION RELATIVE 0.25 TO THE PACKAGE EDGES. 2.THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.08 0.55 0.12 SEATING OF ITS IDEAL POSITION RELATIVE TO THE BALL 0.50 MAX PLANE POPULATION. 0.45 BALL DIAMETER ORDERING GUIDE Ambient Temperature Instruction Package Package Part Number Range Rate Description* Option ADSP-2185MKST-300 0°C to 70°C 75 100-Lead LQFP ST-100 ADSP-2185MBST-266 –40°C to +85°C 66 100-Lead LQFP ST-100 ADSP-2185MKCA-300 0°C to 70°C 75 144-Ball Mini-BGA CA-144 ADSP-2185MBCA-266 –40°C to +85°C 66 144-Ball Mini-BGA CA-144 *In 1998, JEDEC reevaluated the specifications for the TQFP package designation, assigning it to packages 1.0 mm thick. Previously labeled TQFP packages (1.6 mm thick) are now designated as LQFP. A. S. U. N D I E T N RI P –40– REV. 0

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADSP-2185MBSTZ-266 ADSP-2185MKCAZ-300 ADSP-2185MKSTZ-300