SHARC Processor ADSP-21369 SUMMARY DEDICATED AUDIO COMPONENTS High performance 32-bit/40-bit floating-point processor S/PDIF-compatible digital audio receiver/transmitter optimized for high performance audio processing 4 independent asynchronous sample rate converters (SRC) Single-instruction, multiple-data (SIMD) computational 16 PWM outputs configured as four groups of four outputs architecture ROM-based security features include On-chip memory—2M bits of on-chip SRAM and 6M bits of JTAG access to memory permitted with a 64-bit key on-chip mask programmable ROM Protected memory regions that can be assigned to limit Code compatible with all other members of the SHARC family access under program control to sensitive code 400 MHz core instruction rate with unique audiocentric PLL has a wide variety of software and hardware multi- peripherals such as the digital applications interface, plier/divider ratios S/PDIF transceiver, serial ports, 8-channel asynchronous Available in 256-ball BGA_ED and 208-lead LQFP_EP sample rate converter, precision clock generators, and packages more. For complete ordering information, see Ordering Guide. Internal Memory SIMD Core Block 0 Block 1 Block 2 Block 3 RAM/ROM RAM/ROM RAM RAM Instruction 5 stage Cache Sequencer S B0D B1D B2D B3D 64-BIT 64-BIT 64-BIT 64-BIT DAG1/2 Timer DMD 64-BIT DMD 64-BIT PEx PEy Core Bus Internal Memory I/F Cross Bar PMD PMD 64-BIT 64-BIT FLAGx/IRQx/ JTAG EPD BUS 32-BIT IOD0 32-BIT TMREXP PERIPHERAL BUS 32-BIT IOD1 32-BIT IOD0 BUS MTM PERIPHERAL BUS EP CORE PCG TIMER UART S/PDIF PCG ASRC IDP/ SPORT CORE PWM FLAGS C-D 2-0 TWI SPI/B 1-0 Tx/Rx A-D 3-0 PDAP 7-0 FLAGS 3-0 AMI SDRAM 7-0 DPI Routing/Pins DAI Routing/Pins External Port Pin MUX External DPI Peripherals DAI Peripherals Peripherals Port Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies. Technical Support www.analog.com

ADSP-21369 TABLE OF CONTENTS General Description ................................................. 3 Maximum Power Dissipation ................................. 17 SHARC Family Core Architecture ............................ 4 Absolute Maximum Ratings ................................... 18 Family Peripheral Architecture ................................ 7 Timing Specifications ........................................... 18 I/O Processor Features ......................................... 10 Output Drive Currents ......................................... 50 System Design .................................................... 10 Test Conditions .................................................. 50 Development Tools ............................................. 11 Capacitive Loading .............................................. 50 Additional Information ........................................ 12 Thermal Characteristics ........................................ 52 Related Signal Chains .......................................... 12 256-Ball BGA_ED Pinout ......................................... 53 Pin Function Descriptions ....................................... 13 208-Lead LQFP_EP Pinout ....................................... 56 Specifications ........................................................ 16 Package Dimensions ............................................... 58 Operating Conditions .......................................... 16 Surface-Mount Design .......................................... 59 Electrical Characteristics ....................................... 17 Ordering Guide ..................................................... 60 ESD Caution ...................................................... 17 REVISION HISTORY 3/2019—Rev. G to Rev. H Deleted obsolete models ADSP-21367 and ADSP-21368 throughout data sheet. Reorganized layout of data sheet. Rev. H | Page 2 of 60 | March 2019

ADSP-21369 GENERAL DESCRIPTION The ADSP-21369 SHARC® processor is a member of the SIMD Table 2. Product Features (Continued) SHARC family of DSPs that feature Analog Devices’ Super Har- vard Architecture. These processors are source code-compatible Feature ADSP-21369 with the ADSP-2126x and ADSP-2116x DSPs as well as with DPI Yes first generation ADSP-2106x SHARC processors in SISD (sin- gle-instruction, single-data) mode. The processors are 32- S/PDIF Transceiver 1 bit/40-bit floating-point processors optimized for high perfor- AMI Interface Bus Width 32 bits/16 bits/8 bits mance automotive audio applications with its large on-chip SRAM, mask programmable ROM, multiple internal buses to SPI 2 eliminate I/O bottlenecks, and an innovative digital applications TWI Yes interface (DAI). SRC Performance 128 dB As shown in the functional block diagram onPage1, the processor uses two computational units to deliver a significant Shared Memory Support 256-Ball BGA only performance increase over the previous SHARC processors on a Package 256-Ball BGA, 208-Lead LQFP_EP range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the processor achieves an instruction cycle time of up to 2.5 ns at 400 MHz. With its SIMD computa- The diagram onPage1 shows the two clock domains. The core tional hardware, the processor can perform 2.4 GFLOPS clock domain contains the following features. running at 400 MHz. • Two processing elements (PEx, PEy), each of which com- Table1 shows performance benchmarks for the ADSP-21369 prises an ALU, multiplier, shifter, and data register file processor. • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache Table 1. Processor Benchmarks (at 400 MHz) • PM and DM buses capable of supporting two 64-bit data Speed transfers between memory and the core at every core pro- Benchmark Algorithm (at 400 MHz) cessor cycle 1024 Point Complex FFT (Radix 4, with Reversal) 23.2 s • One periodic interval timer with pinout FIR Filter (per Tap)1 1.25 ns • On-chip SRAM (2M bit) IIR Filter (per Biquad)1 5.0 ns • JTAG test access port for emulation and boundary scan. Matrix Multiply (Pipelined) The JTAG provides software debug through user break- [3×3] × [3×1] 11.25 ns points which allows flexible exception handling. [4×4] × [4×1] 20.0 ns The block diagram onPage1 also shows the peripheral clock Divide (y/x) 8.75 ns domain (also known as the I/O processor) and contains the fol- Inverse Square Root 13.5 ns lowing features: 1Assumes two files in multichannel SIMD mode. • IOD0 (peripheral DMA) andI OD1 (external port DMA) buses for 32-bit data transfers Table 2. Product Features • Peripheral and external port buses for core connection • External port with an AMI and SDRAM controller Feature ADSP-21369 • 4 units for PWM control Frequency 400 MHz • 1 MTM unit for internal-to-internal memory transfers RAM 2M bits • Digital applications interface that includes four precision ROM 6M bits clock generators (PCG), a input data port (IDP) for serial Pulse-Width Modulation Yes and parallel interconnect, an S/PDIF receiver/transmitter, four asynchronous sample rate converters, eight serial S/PDIF Yes ports, a flexible signal routing unit (DAI SRU). SDRAM Memory Bus Width 32 bits/16 bits • Digital peripheral interface that includes three timers, a 2- Serial Ports 8 wire interface, two UARTs, two serial peripheral interfaces (SPI), 2 precision clock generators (PCG) and a flexible sig- IDP Yes nal routing unit (DPI SRU). DAI Yes UART 2 Rev. H | Page 3 of 60 | March 2019

ADSP-21369 SHARC FAMILY CORE ARCHITECTURE shares architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC processors, as shown in Figure2 The processor is code compatible at the assembly level with the and detailed in the following sections. ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The processor S JTAG FLAG TIMER INTERRUPT CACHE SIMD Core PM ADDRESS 24 DMD/PMD 64 5 STAGE PROGRAM SEQUENCER PM DATA 48 DAG1 DAG2 16x32 16x32 PM ADDRESS 32 SYSTEM I/F DM ADDRESS 32 USTAT PM DATA 64 4x32-BIT PX DM DATA 64 64-BIT RF DATA RF MULTIPLIER SHIFTER ALU Rx/Fx SWAP Sx/SFx ALU SHIFTER MULTIPLIER PEx PEy 16x40-BIT 16x40-BIT MRF MRB MSB MSF 80-BIT 80-BIT ASTATx ASTATy 80-BIT 80-BIT STYKx STYKy Figure 2. SHARC Core Block Diagram Rev. H | Page 4 of 60 | March 2019

ADSP-21369 SIMD Computational Engine The data bus exchange register (PX) permits data to be passed between the 64-bit PM data bus and the 64-bit DM data bus, or The processor contains two computational processing elements between the 40-bit register file and the PM data bus. These reg- that operate as a single-instruction, multiple-data (SIMD) isters contain hardware to handle the data width difference. engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. Timer PEX is always active, and PEY may be enabled by setting the A core timer that can generate periodic software Interrupts. The PEYEN mode bit in the MODE1 register. When this mode is core timer can be configured to use FLAG3 as a timer expired enabled, the same instruction is executed in both processing ele- signal. ments, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP Single-Cycle Fetch of Instruction and Four Operands algorithms. The processor features an enhanced Harvard architecture in Entering SIMD mode also has an effect on the way data is trans- which the data memory (DM) bus transfers data and the pro- ferred between memory and the processing elements. When in gram memory (PM) bus transfers both instructions and data SIMD mode, twice the data bandwidth is required to sustain (see Figure2). With separate program and data memory buses computational operation in the processing elements. Because of and on-chip instruction cache, the processors can simultane- this requirement, entering SIMD mode also doubles the band- ously fetch four operands (two over each data bus) and one width between memory and the processing elements. When instruction (from the cache), all in a single cycle. using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file. Instruction Cache Independent, Parallel Computation Units The processors include an on-chip instruction cache that enables three-bus operation for fetching an instruction and four Within each processing element is a set of computational units. data values. The cache is selective—only the instructions whose The computational units consist of an arithmetic/logic unit fetches conflict with PM bus data accesses are cached. This (ALU), multiplier, and shifter. These units perform all opera- cache allows full-speed execution of core, looped operations tions in a single cycle. The three units within each processing such as digital filter multiply-accumulates, and FFT butterfly element are arranged in parallel, maximizing computational processing. throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel Data Address Generators with Zero-Overhead Hardware ALU and multiplier operations occur in both processing Circular Buffer Support elements. These computation units support IEEE 32-bit single- The processor has two data address generators (DAGs). The precision floating-point, 40-bit extended precision floating- DAGs are used for indirect addressing and implementing circu- point, and 32-bit fixed-point data formats. lar data buffers in hardware. Circular buffers allow efficient Data Register File programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital A general-purpose data register file is contained in each pro- filters and Fourier transforms. The two DAGs contain sufficient cessing element. The register files transfer data between the registers to allow the creation of up to 32 circular buffers computation units and the data buses, and store intermediate (16primary register sets, 16 secondary). The DAGs automati- results. These 10-port, 32-register (16 primary, 16 secondary) cally handle address pointer wraparound, reduce overhead, register files, combined with the enhanced Harvard architecture increase performance, and simplify implementation. Circular of the ADSP-21369 processor, allow unconstrained data flow buffers can start and end at any memory location. between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15. Flexible Instruction Set Context Switch The 48-bit instruction word accommodates a variety of parallel operations for concise programming. For example, the Many of the processor’s registers have secondary registers that ADSP-21369 processor can conditionally execute a multiply, an can be activated during interrupt servicing for a fast context add, and a subtract in both processing elements while branching switch. The data registers in the register file, the DAG registers, and fetching up to four 32-bit values from memory—all in a sin- and the multiplier result registers all have secondary registers. gle instruction. The primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register. Universal Registers These registers can be used for general-purpose tasks. The USTAT (4) registers allow easy bit manipulations (Set, Clear, Toggle, Test, XOR) for all system registers (control/status) of the core. Rev. H | Page 5 of 60 | March 2019

ADSP-21369 On-Chip Memory Using the DM bus and PM buses, with one bus dedicated to each memory block, assures single-cycle execution with two The processors contain two megabits of internal RAM and six data transfers. In this case, the instruction must be available in megabits of internal mask-programmable ROM. Each block can the cache. be configured for different combinations of code and data stor- age (see Table3). Each memory block supports single-cycle, On-Chip Memory Bandwidth independent accesses by the core processor and I/O processor. The internal memory architecture allows programs to have four The memory architecture, in combination with its separate on- accesses at the same time to any of the four blocks (assuming chip buses, allows two data transfers from the core and one there are no block conflicts). The total bandwidth is realized from the I/O processor, in a single cycle. using the DMD and PMD buses (2 × 64-bit, core CLK) and the The SRAM can be configured as a maximum of 64k words of IOD0/1 buses (2 × 32-bit, PCLK). 32-bit data, 128k words of 16-bit data, 42k words of 48-bit instructions (or 40-bit data), or combinations of different word ROM-Based Security sizes up to two megabits. All of the memory can be accessed as The processor has a ROM security feature that provides hard- 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point ware support for securing user software code by preventing storage format is supported that effectively doubles the amount unauthorized reading from the internal code when enabled. of data that can be stored on-chip. Conversion between the When using this feature, the processor does not boot-load any 32-bit floating-point and 16-bit floating-point formats is per- external code, executing exclusively from internal ROM. Addi- formed in a single instruction. While each memory block can tionally, the processor is not freely accessible via the JTAG port. store combinations of code and data, accesses are most efficient Instead, a unique 64-bit key, which must be scanned in through when one block stores data using the DM bus for transfers, and the JTAG or test access port will be assigned to each customer. the other block stores instructions and data using the PM bus The device will ignore a wrong key. Emulation features and for transfers. external boot modes are only available after the correct key is scanned. Table 3. Internal Memory Space1 IOP Registers 0x0000 0000–0x0003 FFFF Extended Precision Normal or Long Word (64 Bits) Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits) Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) 0x0004 0000–0x0004 BFFF 0x0008 0000–0x0008 FFFF 0x0008 0000–0x0009 7FFF 0x0010 0000–0x0012 FFFF Reserved Reserved Reserved Reserved 0x0004 F000–0x0004 FFFF 0x0009 4000–0x0009 FFFF 0x0009 E000–0x0009 FFFF 0x0013 C000–0x0013 FFFF Block 0 SRAM Block 0 SRAM Block 0 SRAM Block 0 SRAM 0x0004 C000–0x0004 EFFF 0x0009 0000–0x0009 3FFF 0x0009 8000–0x0009 DFFF 0x0013 0000–0x0013 BFFF Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) 0x0005 0000–0x0005 BFFF 0x000A 0000–0x000A FFFF 0x000A 0000–0x000B 7FFF 0x0014 0000–0x0016 FFFF Reserved Reserved Reserved Reserved 0x0005 F000–0x0005 FFFF 0x000B 4000–0x000B FFFF 0x000B E000–0x000B FFFF 0x0017 C000–0x0017 FFFF Block 1 SRAM Block 1 SRAM Block 1 SRAM Block 1 SRAM 0x0005 C000–0x0005 EFFF 0x000B 0000–0x000B 3FFF 0x000B 8000–0x000B DFFF 0x0017 0000–0x0017 BFFF Block 2 SRAM Block 2 SRAM Block 2 SRAM Block 2 SRAM 0x0006 0000–0x0006 0FFF 0x000C 0000–0x000C 1554 0x000C 0000–0x000C 1FFF 0x0018 0000–0x0018 3FFF Reserved Reserved Reserved Reserved 0x0006 1000– 0x0006 FFFF 0x000C 1555–0x000C 3FFF 0x000C 2000–0x000D FFFF 0x0018 4000–0x001B FFFF Block 3 SRAM Block 3 SRAM Block 3 SRAM Block 3 SRAM 0x0007 0000–0x0007 0FFF 0x000E 0000–0x000E 1554 0x000E 0000–0x000E 1FFF 0x001C 0000–0x001C 3FFF Reserved Reserved Reserved Reserved 0x0007 1000–0x0007 FFFF 0x000E 1555–0x000F FFFF 0x000E 2000–0x000F FFFF 0x001C 4000–0x001F FFFF 1The processor includes a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details. Rev. H | Page 6 of 60 | March 2019

ADSP-21369 FAMILY PERIPHERAL ARCHITECTURE Table 4. External Memory for SDRAM Addresses The processor contains a rich set of peripherals that support a Size in wide variety of applications including high quality audio, medi- Bank Words Address Range cal imaging, communications, military, test equipment, 3D graphics, speech recognition, motor control, imaging, and other Bank 0 62M 0x0020 0000–0x03FF FFFF applications. Bank 1 64M 0x0400 0000–0x07FF FFFF External Port Bank 2 64M 0x0800 0000–0x0BFF FFFF The external port interface supports access to the external mem- Bank 3 64M 0x0C00 0000–0x0FFF FFFF ory through core and DMA accesses. The external memory address space is divided into four banks. Any bank can be pro- devices and DIMMs (dual inline memory module), while the grammed as either asynchronous or synchronous memory. The second is an asynchronous memory controller intended to external ports of the processor are comprised of the following interface to a variety of memory devices. Four memory select modules. pins enable up to four separate devices to coexist, supporting • An Asynchronous Memory Interface which communicates any desired combination of synchronous and asynchronous with SRAM, FLASH, and other devices that meet the stan- device types. Non-SDRAM external memory address space is dard asynchronous SRAM access protocol. The AMI shown in Table5. supports 14M words of external memory in bank 0 and 16M words of external memory in bank 1, bank 2, and Table 5. External Memory for Non-SDRAM Addresses bank 3. • An SDRAM controller that supports a glueless interface Size in with any of the standard SDRAMs. The SDC supports 62M Bank Words Address Range words of external memory in bank 0, and 64M words of Bank 0 14M 0x0020 0000–0x00FF FFFF external memory in bank 1, bank 2, and bank 3. Bank 1 16M 0x0400 0000–0x04FF FFFF • Arbitration Logic to coordinate core and DMA transfers between internal and external memory over the external Bank 2 16M 0x0800 0000–0x08FF FFFF port. Bank 3 16M 0x0C00 0000–0x0CFF FFFF • A Shared Memory Interface that allows the connection of up to four processors to create shared external bus systems. Shared External Memory SDRAM Controller The ADSP-21369 processor supports connecting to common The SDRAM controller provides an interface of up to four sepa- shared external memory with other ADSP-21369 processors to rate banks of industry-standard SDRAM devices or DIMMs, at create shared external bus processor systems. This support speeds up to f . Fully compliant with the SDRAM standard, includes: SCLK each bank has its own memory select line (MS0–MS3), and can • Distributed, on-chip arbitration for the shared external bus be configured to contain between 16Mbytes and 128Mbytes of memory. SDRAM external memory address space is shown in • Fixed and rotating priority bus arbitration Table4. • Bus time-out logic A set of programmable timing parameters is available to config- • Bus lock ure the SDRAM banks to support slower memory devices. The Multiple processors can share the external bus with no addi- memory banks can be configured as either 32 bits wide for max- tional arbitration logic. Arbitration logic is included on-chip to imum performance and bandwidth or 16 bits wide for allow the connection of up to four processors. minimum device count and lower system cost. Bus arbitration is accomplished through the BR1–4 signals and The SDRAM controller address, data, clock, and control pins the priority scheme for bus arbitration is determined by the set- can drive loads up to distributed 30 pF loads. For larger memory ting of the RPBA pin. Table8 provides descriptions of the pins systems, the SDRAM controller external buffer timing should used in multiprocessor systems. be selected and external buffering should be provided so that the load on the SDRAM controller pins does not exceed 30 pF. External Port Throughput External Memory The throughput for the external port, based on 166 MHz clock and 32-bit data bus, is 221M bytes/s for the AMI and 664M The external port provides a high performance, glueless inter- bytes/s for SDRAM. face to a wide variety of industry-standard memory devices. The 32-bit wide bus can be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers. The first is an SDRAM controller for connection of industry-standard synchronous DRAM Rev. H | Page 7 of 60 | March 2019

ADSP-21369 Asynchronous Memory Controller data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own The asynchronous memory controller provides a configurable DMA channel that is independent from the processor’s serial interface for up to four separate banks of memory or I/O ports. devices. Each bank can be independently programmed with dif- ferent timing parameters, enabling connection to a wide variety For complete information on using the DAI, see the of memory devices including SRAM, ROM, flash, and EPROM, ADSP-2137x SHARC Processor Hardware Reference. as well as I/O devices that interface with standard memory Serial Ports control lines. Bank 0 occupies a 14M word window and Banks 1, 2, and 3 occupy a 16M word window in the processor’s address The processors feature eight synchronous serial ports (SPORTs) space but, if not fully populated, these windows are not made that provide an inexpensive interface to a wide variety of digital contiguous by the memory controller logic. The banks can also and mixed-signal peripheral devices such as Analog Devices’ be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of AD183x family of audio codecs, ADCs, and DACs. The serial interfacing to a range of memories and I/O devices tailored ports are made up of two data lines, a clock, and frame sync. The either to high performance or to low cost and power. data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Pulse-Width Modulation Serial ports are enabled via 16 programmable and simultaneous The PWM module is a flexible, programmable, PWM waveform receive or transmit pins that support up to 32 transmit or 32 generator that can be programmed to generate the required receive channels of audio data when all eight SPORTs are switching patterns for various applications related to motor and enabled, or eight full duplex TDM streams of 128 channels engine control or audio power control. The PWM generator can per frame. generate either center-aligned or edge-aligned PWM wave- The serial ports operate at a maximum data rate of 50 Mbps. forms. In addition, it can generate complementary signals on Serial port data can be automatically transferred to and from two outputs in paired mode or independent signals in non- on-chip memory via dedicated DMA channels. Each of the paired mode (applicable to a single group of four PWM serial ports can work in conjunction with another serial port to waveforms). provide TDM support. One SPORT provides two transmit sig- The entire PWM module has four groups of four PWM outputs nals while the other SPORT provides the two receive signals. each. Therefore, this module generates 16 PWM outputs in The frame sync and clock are shared. total. Each PWM group produces two pairs of PWM signals on Serial ports operate in five modes: the four PWM outputs. • Standard DSP serial mode The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single • Multichannel (TDM) mode with support for packed I2S update mode or double update mode. In single update mode, mode the duty cycle values are programmable only once per PWM • I2S mode period. This results in PWM patterns that are symmetrical • Packed I2S mode about the midpoint of the PWM period. In double update mode, a second updating of the PWM registers is implemented • Left-justified sample pair mode at the midpoint of the PWM period. In this mode, it is possible Left-justified sample pair mode is a mode where in each frame to produce asymmetrical PWM patterns that produce lower sync cycle two samples of data are transmitted/received—one harmonic distortion in 2-phase PWM inverters. sample on the high segment of the frame sync, the other on the Digital Applications Interface (DAI) low segment of the frame sync. Programs have control over var- ious attributes of this mode. The digital applications interface (DAI) provides the ability to Each of the serial ports supports the left-justified sample pair connect various peripherals to any of the DAI pins of the DSP and I2S protocols (I2S is an industry-standard interface com- (DAI_P20–1). Programs make these connections using the sig- monly used by audio codecs, ADCs, and DACs such as the nal routing unit (SRU1), shown in Figure1. Analog Devices AD183x family), with two data pins, allowing The SRU is a matrix routing unit (or group of multiplexers) that four left-justified sample pair or I2S channels (using two stereo enables the peripherals provided by the DAI to be intercon- devices) per serial port, with a maximum of up to 32 I2S chan- nected under software control. This allows easy use of the nels. The serial ports permit little-endian or big-endian associated peripherals for a much wider variety of applications transmission formats and word lengths selectable from 3 bits to by using a larger set of algorithms than is possible with noncon- 32 bits. For the left-justified sample pair and I2S modes, data- figurable signal paths. word lengths are selectable between 8 bits and 32 bits. Serial The DAI includes eight serial ports, an S/PDIF receiver/trans- ports offer selectable synchronization and transmit modes as mitter, four precision clock generators (PCG), eight channels of well as optional -law or A-law companding selection on a per synchronous sample rate converters, and an input data port channel basis. Serial port clocks and frame syncs can be inter- (IDP). The IDP provides an additional input path to the nally or externally generated. processor core, configurable as either eight channels of I2S serial Rev. H | Page 8 of 60 | March 2019

ADSP-21369 The serial ports also contain frame sync error detection logic Serial Peripheral (Compatible) Interface where the serial ports detect frame syncs that arrive early (for The processors contain two serial peripheral interface ports example, frame syncs that arrive while the transmission/recep- (SPIs). The SPI is an industry-standard synchronous serial link, tion of the previous word is occurring). All the serial ports also enabling the SPI-compatible port to communicate with other share one dedicated error interrupt. SPI-compatible devices. The SPI consists of two data pins, one S/PDIF-Compatible Digital Audio Receiver/Transmitter device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave The S/PDIF receiver/transmitter has no separate DMA chan- modes. The SPI port can operate in a multimaster environment nels. It receives audio data in serial format and converts it into a by interfacing with up to four other SPI-compatible devices, biphase encoded signal. The serial data input to the either acting as a master or slave device. The SPI-compatible receiver/transmitter can be formatted as left-justified, I2S, or peripheral implementation also features programmable baud right-justified with word widths of 16, 18, 20, or 24 bits. rate and clock phase and polarities. The SPI-compatible port The serial data, clock, and frame sync inputs to the S/PDIF uses open-drain drivers to support a multimaster configuration receiver/transmitter are routed through the signal routing unit and to avoid data contention. (SRU). They can come from a variety of sources such as the UART Port SPORTs, external pins, the precision clock generators (PCGs), or the sample rate converters (SRC) and are controlled by the The processors provide a full-duplex universal asynchronous SRU control registers. receiver/transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simpli- Synchronous/Asynchronous Sample Rate Converter fied UART interface to other peripherals or hosts, supporting The sample rate converter (SRC) contains four SRC blocks and full-duplex, DMA-supported, asynchronous transfers of serial is the same core as that used in the AD1896 192 kHz stereo data. The UART also has multiprocessor communication capa- asynchronous sample rate converter and provides up to 128 dB bility using 9-bit address detection. This allows it to be used in SNR. The SRC block is used to perform synchronous or asyn- multidrop networks through the RS-485 data interface chronous sample rate conversion across independent stereo standard. The UART port also includes support for five data bits channels, without using internal processor resources. The four to eightdata bits, one stop bit or twostop bits, and none, even, SRC blocks can also be configured to operate together to con- or odd parity. The UART port supports two modes of vert multichannel audio data without phase mismatches. operation: Finally, the SRC can be used to clean up audio data from jittery • PIO (programmed I/O) – The processor sends or receives clock sources such as the S/PDIF receiver. data by writing or reading I/O-mapped UART registers. Input Data Port The data is double-buffered on both transmit and receive. • DMA (direct memory access) – The DMA controller trans- The IDP provides up to eight serial input channels—each with fers both transmit and receive data. This reduces the its own clock, frame sync, and data inputs. The eight channels number and frequency of interrupts required to transfer are automatically multiplexed into a single 32-bit by eight-deep data to and from memory. The UART has two dedicated FIFO. Data is always formatted as a 64-bit frame and divided DMA channels, one for transmit and one for receive. These into two 32-bit words. The serial protocol is designed to receive DMA channels have lower default priority than most DMA audio channels in I2S, left-justified sample pair, or right-justi- channels because of their relatively low service rates. fied mode. One frame sync cycle indicates one 64-bit left/right pair, but data is sent to the FIFO as 32-bit words (that is, one- The UART port’s baud rate, serial data format, error code gen- half of a frame at a time). The processor supports 24- and 32-bit eration and status, and interrupts are programmable: I2S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit • Supporting bit rates ranging from (f /1,048,576) to right-justified formats. SCLK (f /16) bits per second. SCLK Precision Clock Generators • Supporting data formats from 7 bits to 12bits per frame. The precision clock generators (PCG) consist of four units, each • Both transmit and receive operations can be configured to of which generates a pair of signals (clock and frame sync) generate maskable interrupts to the processor. derived from a clock input signal. The units, A B, C, and D, are Where the 16-bit UART_Divisor comes from the DLH register identical in functionality and operate independently of each (most significant eight bits) and DLL register (least significant other. The two signals generated by each unit are normally used eightbits). as a serial bit clock/frame sync pair. In conjunction with the general-purpose timer functions, auto- Digital Peripheral Interface (DPI) baud detection is supported. The digital peripheral interface provides connections to two serial peripheral interface ports (SPI), two universal asynchro- nous receiver-transmitters (UARTs), a 2-wire interface (TWI), 12 flags, and three general-purpose timers. Rev. H | Page 9 of 60 | March 2019

ADSP-21369 Peripheral Timers Delay Line DMA Three general-purpose timers can generate periodic interrupts The processor provides delay line DMA functionality. This and be independently set to operate in one of three modes: allows processor reads and writes to external delay line buffers (in external memory, SRAM, or SDRAM) with limited core • Pulse waveform generation mode interaction. • Pulse width count/capture mode SYSTEM DESIGN • External event watchdog mode Each general-purpose timer has one bidirectional pin and four The following sections provide an introduction to system design registers that implement its mode of operation: a 6-bit configu- options and power supply issues. ration register, a 32-bit count register, a 32-bit period register, Program Booting and a 32-bit pulse width register. A single control and status register enables or disables all three general-purpose timers The internal memory of the processors can be booted up at sys- independently. tem power-up from an 8-bit EPROM via the external port, an SPI master or slave, or an internal boot. Booting is determined 2-Wire Interface Port (TWI) by the boot configuration (BOOT_CFG1–0) pins (see Table7 The TWI is a bidirectional 2-wire serial bus used to move 8-bit and the processor hardware reference). Selection of the boot data while maintaining compliance with the I2C bus protocol. source is controlled via the SPI as either a master or slave device, The TWI master incorporates the following features: or it can immediately begin executing from ROM. • Simultaneous master and slave operation on multiple Table 7. Boot Mode Selection device systems with support for multimaster data arbitration BOOT_CFG1–0 Booting Mode • Digital filtering and timed event processing 00 SPI Slave Boot • 7-bit and 10-bit addressing 01 SPI Master Boot 10 EPROM/FLASH Boot • 100 kbps and 400 kbps data rates 11 No boot (processor executes from • Low interrupt rate internal ROM after reset) I/O PROCESSOR FEATURES Power Supplies The I/O processor provides many channels of DMA, and con- trols the extensive set of peripherals described in the previous The processors have separate power supply connections for the sections. internal (V ), external (V ), and analog (A /A ) power DDINT DDEXT VDD VSS supplies. The internal and analog supplies must meet the 1.3 V DMA Controller requirement for the 400 MHz device and 1.2 V for the The processor’s on-chip DMA controller allows data transfers 333 MHz and 266 MHz devices. The external supply must meet without processor intervention. The DMA controller operates the 3.3 V requirement. All external supply pins must be con- independently and invisibly to the processor core, allowing nected to the same power supply. DMA operations to occur while the core is simultaneously exe- Note that the analog supply pin (A ) powers the processor’s VDD cuting its program instructions. DMA transfers can occur internal clock generator PLL. To produce a stable clock, it is rec- between the processor’s internal memory and its serial ports, the ommended that PCB designs use an external filter circuit for the SPI-compatible (serial peripheral interface) ports, the IDP A pin. Place the filter components as close as possible to the VDD (input data port), the parallel data acquisition port (PDAP), or A /A pins. For an example circuit, see Figure3. (A recom- VDD VSS the UART. mended ferrite chip is the muRata BLM18AG102SN1D). To Thirty four channels of DMA are available on the ADSP-2136x reduce noise coupling, the PCB should use a parallel pair of processors as shown in Table6. power and ground planes for VDDINT and GND. Use wide traces to connect the bypass capacitors to the analog power (A ) and VDD Table 6. DMA Channels ground (A ) pins. Note that the A and A pins specified in VSS VDD VSS Figure3 are inputs to the processor and not the analog ground Peripheral DMA Channels plane on the board—the A pin should connect directly to dig- VSS SPORTs 16 ital ground (GND) at the chip. PDAP 8 SPI 2 UART 4 External Port 2 Memory-to-Memory 2 Rev. H | Page 10 of 60 | March 2019

ADSP-21369 emulation capabilities and other evaluation and development ADSP-213xx features. Also available are various EZ-Extenders®, which are 100nF 10nF 1nF daughter cards delivering additional specialized functionality, VDDINT AVDD including audio and video processing. For more information visit www.analog.com and search on “ezkit” or “ezextender”. HI-ZFERRITE BEADCHIP AVSS EZ-KIT Lite Evaluation Kits For a cost-effective way to learn more about developing with LOCATEALLCOMPONENTS Analog Devices processors, Analog Devices offer a range of EZ- CLOSETOAVDDANDAVSSPINS KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT Lite evaluation board, directions for downloading an evaluation Figure 3. Analog Power (A ) Filter Circuit VDD version of the available IDE(s), a USB cable, and a power supply. The USB controller on the EZ-KIT Lite board connects to the Target Board JTAG Emulator Connector USB port of the user’s PC, enabling the chosen IDE evaluation Analog Devices DSP Tools product line of JTAG emulators uses suite to emulate the on-board processor in-circuit. This permits the IEEE 1149.1 JTAG test access port of the processor to moni- the customer to download, execute, and debug programs for the tor and control the target board processor during emulation. EZ-KIT Lite system. It also supports in-circuit programming of Analog Devices DSP Tools product line of JTAG emulators pro- the on-board Flash device to store user-specific boot code, vides emulation at full processor speed, allowing inspection and enabling standalone operation. With the full version of Cross- modification of memory, registers, and processor stacks. The Core Embedded Studio or VisualDSP++ installed (sold processor’s JTAG interface ensures that the emulator will not separately), engineers can develop software for supported EZ- affect target system loading or timing. KITs or any custom system utilizing supported Analog Devices processors. For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appro- Software Add-Ins for CrossCore Embedded Studio priate “Emulator Hardware User’s Guide.” Analog Devices offers software add-ins which seamlessly inte- DEVELOPMENT TOOLS grate with CrossCore Embedded Studio to extend its capabilities and reduce development time. Add-ins include board support Analog Devices supports its processors with a complete line of packages for evaluation hardware, various middleware pack- software and hardware development tools, including integrated ages, and algorithmic modules. Documentation, help, development environments (which include CrossCore® Embed- configuration dialogs, and coding examples present in these ded Studio and/or VisualDSP++®), evaluation products, add-ins are viewable through the CrossCore Embedded Studio emulators, and a wide variety of software add-ins. IDE once the add-in is installed. Integrated Development Environments (IDEs) Board Support Packages for Evaluation Hardware For C/C++ software writing and editing, code generation, and Software support for the EZ-KIT Lite evaluation boards and EZ- debug support, Analog Devices offers two IDEs. Extender daughter cards is provided by software add-ins called The newest IDE, CrossCore Embedded Studio, is based on the Board Support Packages (BSPs). The BSPs contain the required EclipseTM framework. Supporting most Analog Devices proces- drivers, pertinent release notes, and select example code for the sor families, it is the IDE of choice for future processors, given evaluation hardware. A download link for a specific BSP is including multicore devices. CrossCore Embedded Studio located on the web page for the associated EZ-KIT or EZ- seamlessly integrates available software add-ins to support real Extender product. The link is found in the Product Download time operating systems, file systems, TCP/IP stacks, USB stacks, area of the product web page. algorithmic software modules, and evaluation hardware board support packages. For more information visit www.analog.com/cces. The other Analog Devices IDE, VisualDSP++, supports proces- sor families introduced prior to the release of CrossCore Embedded Studio. This IDE includes the Analog Devices VDK real time operating system and an open source TCP/IP stack. For more information visit www.analog.com/visualdsp. Note that VisualDSP++ will not support future Analog Devices processors. EZ-KIT Lite Evaluation Board For processor evaluation, Analog Devices provides wide range of EZ-KIT Lite® evaluation boards. Including the processor and key peripherals, the evaluation board also supports on-chip Rev. H | Page 11 of 60 | March 2019

ADSP-21369 Middleware Packages RELATED SIGNAL CHAINS Analog Devices separately offers middleware add-ins such as A signal chain is a series of signal-conditioning electronic com- real time operating systems, file systems, USB stacks, and ponents that receive input (data acquired from sampling either TCP/IP stacks. For more information see the following web real-time phenomena or from stored data) in tandem, with the pages: output of one portion of the chain supplying input to the next. • www.analog.com/ucos2 Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on • www.analog.com/ucos3 analysis of real-time phenomena. • www.analog.com/ucfs Analog Devices eases signal processing system development by • www.analog.com/ucusbd providing signal processing components that are designed to work together well. A tool for viewing relationships between • www.analog.com/ucusbh specific applications and related components is available on the • www.analog.com/lwip www.analog.com website. Algorithmic Modules The application signal chains page in the Circuits from the Lab® site (http:\\www.analog.com\circuits) provides: To speed development, Analog Devices offers add-ins that per- form popular audio and video processing algorithms. These are • Graphical circuit block diagram presentation of signal available for use with both CrossCore Embedded Studio and chains for a variety of circuit types and applications VisualDSP++. For more information visit www.analog.com and • Drill down links for components in each chain to selection search on “Blackfin software modules” or “SHARC software guides and application information modules”. • Reference designs applying best practice design techniques Designing an Emulator-Compatible DSP Board(Target) For embedded system test and debug, Analog Devices provides a family of emulators. On each JTAG DSP, Analog Devices sup- plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit emulation is facilitated by use of this JTAG interface. The emu- lator accesses the processor’s internal features via the processor’s TAP, allowing the developer to load code, set break- points, and view variables, memory, and registers. The processor must be halted to send data and commands, but once an operation is completed by the emulator, the DSP system is set to run at full speed with no impact on system timing. The emu- lators require the target board to include a header that supports connection of the JTAG port of the DSP to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal ter- mination, and emulator pod logic, see “Analog Devices JTAG Emulation Technical Reference” (EE-68). This document is updated regularly to keep pace withimprovements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the architecture and functionality of the ADSP-21369 processor. For detailed information on the ADSP-2136x family core archi- tecture and instruction set, refer to the ADSP-2137x SHARC Processor Hardware Reference and the SHARC Processor Pro- gramming Reference. Rev. H | Page 12 of 60 | March 2019

ADSP-21369 PIN FUNCTION DESCRIPTIONS The following symbols appear in the Type column of Table8: The ADSP-21369 SHARC processors use extensive pin multi- A = asynchronous, G = ground, I=input, O = output, plexing to achieve a lower pin count. For complete information O/T = output three-state, P = power supply, S = synchronous, on the multiplexing scheme, see the ADSP-2137x SHARC Pro- (A/D) = active drive, (O/D) = open-drain, (pd) = pull-down cessor Hardware Reference, “System Design” chapter. resistor, (pu) = pull-up resistor. Table 8. Pin Descriptions State During/ After Reset Name Type (ID = 00x) Description ADDR O/T (pu)1 Pulled high/ External Address. The processors output addresses for external memory and peripher- 23–0 driven low als on these pins. DATA I/O (pu)1 Pulled high/ External Data. Data pins can be multiplexed to support external memory interface data 31–0 pulled high (I/O), the PDAP (I), FLAGS (I/O), and PWM (O). After reset, all DATA pins are in EMIF mode and FLAG(0-3) pins are in FLAGS mode (default). When configured using the IDP_P- DAP_CTL register, IDP Channel 0 scans the external port data pins for parallel input data. ACK I (pu)1 Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other periph- erals to hold off completion of an external memory access. MS O/T (pu)1 Pulled high/ Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre- 0–1 driven high sponding banks of external memory. The MS lines are decoded memory address lines 3-0 that change at the same time as the other address lines. When no external memory access is occurring, the MS lines are inactive; they are active, however, when a conditional 3-0 memory access instruction is executed, whether or not the condition is true. The MS pin can be used in EPORT/FLASH boot mode. See the processor hardware 1 reference for more information. RD O/T (pu)1 Pulled high/ External Port Read Enable. RD is asserted whenever the processors read a word from driven high external memory. WR O/T (pu)1 Pulled high/ External Port Write Enable. WR is asserted when the processors write a word to external driven high memory. FLAG[0]/IRQ0 I/O FLAG[0] INPUT FLAG0/Interrupt Request 0. FLAG[1]/IRQ1 I/O FLAG[1] INPUT FLAG1/Interrupt Request 1. FLAG[2]/IRQ2/ I/O with pro- FLAG[2] INPUT FLAG2/Interrupt Request 2/Memory Select 2. MS grammable pu 2 (for MS mode) FLAG[3]/ I/O with pro- FLAG[3] INPUT FLAG3/Timer Expired/Memory Select 3. TMREXP/MS grammable pu 3 (for MS mode) Rev. H | Page 13 of 60 | March 2019

ADSP-21369 Table 8. Pin Descriptions (Continued) State During/ After Reset Name Type (ID = 00x) Description SDRAS O/T (pu)1 Pulled high/ SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other driven high SDRAM command pins, defines the operation for the SDRAM to perform. SDCAS O/T (pu)1 Pulled high/ SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with other driven high SDRAM command pins, defines the operation for the SDRAM to perform. SDWE O/T (pu)1 Pulled high/ SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin. driven high SDCKE O/T (pu)1 Pulled high/ SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK signal. driven high For details, see the data sheet supplied with the SDRAM device. SDA10 O/T (pu)1 Pulled high/ SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non- driven low SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses. SDCLK0 O/T High-Z/driving SDRAM Clock Output 0. Clock driver for this pin differs from all other clock drivers. See Figure39. SDCLK1 O/T SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple SDRAM devices, handles the increased clock load requirements, eliminating need of off- chip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated. Clock driver for this pin differs from all other clock drivers. See Figure39. The SDCLK1 signal is only available on the FCBGA package. SDCLK1 is not available on the LQFP_EP package. DAI _P I/O with pro- Pulled high/ Digital Applications Interface. These pins provide the physical interface to the DAI SRU. 20–1 grammable pulled high The DAI SRU configuration registers define the combination of on-chip audiocentric pu2 peripheral inputs or outputs connected to the pin, and to the pin’s output enable. The configuration registers then determines the exact behavior of the pin. Any input or output signal present in the DAI SRU may be routed to any of these pins. The DAI SRU provides the connection from the serial ports (8), the SRC module, the S/PDIF module, input data ports (2), and the precision clock generators (4), to the DAI_P20–1 pins. Pull- ups can be disabled via the DAI_PIN_PULLUP register. DPI _P I/O with pro- Pulled high/ Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU. 14–1 grammable pulled high The DPI SRU configuration registers define the combination of on-chip peripheral inputs pu2 or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU provides the connection from the timers (3), SPIs (2), UARTs (2), flags (12) TWI (1), and general-purpose I/O (9) to the DPI_P14–1 pins. The TWI output is an open-drain output— so the pins used for I2C data and clock should be connected to logic level 0. Pull-ups can be disabled via the DPI_PIN_PULLUP register. TDI I (pu) Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDO O/T Test Data Output (JTAG). Serial scan output of the boundary scan path. TMS I (pu) Test Mode Select (JTAG). Used to control the test state machine. TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up, or held low for proper operation of the processor TRST I (pu) Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the processor. Rev. H | Page 14 of 60 | March 2019

ADSP-21369 Table 8. Pin Descriptions (Continued) State During/ After Reset Name Type (ID = 00x) Description EMU O (O/D, pu) Emulation Status. Must be connected to the processor Analog Devices DSP Tools product line of JTAG emulator target board connectors only. CLK_CFG I Core/CLKIN Ratio Control. These pins set the start-up clock frequency. See the processor 1–0 hardware reference for a description of the clock configuration modes. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. CLKIN I Local Clock In. Used with XTAL. CLKIN is the processor’s clock input. It configures the processors to use either its internal clock generator or an external clock source. Connect- ing the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processor to use an external clock such as an external clock oscillator. CLKIN may not be halted, changed, or operated below the specified frequency. XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal. RESET I Processor Reset. Resets the processor to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power- up. RESETOUT O Driven low/ Reset Out. Drives out the core reset signal to an external device. driven high BOOT_CFG I Boot Configuration Select. These pins select the boot mode for the processor. The 1–0 BOOT_CFG pins must be valid before reset is asserted. See the processor hardware reference for a description of the boot modes. BR I/O (pu)1 Pulled high/ External Bus Request. Used to arbitrate for bus mastership. A processor only drives its 4–1 pulled high own BR line (corresponding to the value of its ID2-0 inputs) and monitors all others. In a x system with less than four processors, the unused BR pins should be tied high; the pro- x cessor’s own BR line must not be tied high or low because it is an output. x ID I (pd) Processor ID. Determines which bus request (BR ) is used by the processor. ID = 001 2–0 4–1 corresponds to BR ID = 010 corresponds to BR, and so on. Use ID = 000 or 001 in single- 1, 2 processor systems. These lines are a system configuration selection that should be hardwired or only changed at reset. ID = 101,110, and 111 are reserved. RPBA I (pu)1 Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for external bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection which must be set to the same value on every processor in the system. 1The pull-up is always enabled. 2Pull-up can be enabled/disabled, value of pull-up cannot be programmed. Rev. H | Page 15 of 60 | March 2019

ADSP-21369 SPECIFICATIONS OPERATING CONDITIONS 366 MHz 333 MHz 400 MHz 350 MHz 266 MHz Parameter1 Description Min Max Min Max Min Max Unit V Internal (Core) Supply Voltage 1.25 1.35 1.235 1.365 1.14 1.26 V DDINT A Analog (PLL) Supply Voltage 1.25 1.35 1.235 1.365 1.14 1.26 V VDD V External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 3.13 3.47 V DDEXT V 2 High Level Input Voltage @ V = Max 2.0 V + 0.5 2.0 V + 0.5 2.0 V + 0.5 V IH DDEXT DDEXT DDEXT DDEXT V2 Low Level Input Voltage @ V = Min –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 V IL DDEXT V 3 High Level Input Voltage @ V = Max 1.74 V + 0.5 1.74 V + 0.5 1.74 V + 0.5 V IH_CLKIN DDEXT DDEXT DDEXT DDEXT V 3 Low Level Input Voltage @ V = Min –0.5 +1.1 –0.5 +1.1 –0.5 +1.1 V IL_CLKIN DDEXT T Junction Temperature 208-Lead LQFP_EP @ J T 0C to 70C 0 95 0 110 0 110 C AMBIENT T Junction Temperature 208-Lead LQFP_EP @ J T –40C to +85C N/A N/A N/A N/A –40 +120 C AMBIENT T Junction Temperature 256-Ball BGA_ED @ J T 0C to 70C 0 95 N/A N/A 0 105 C AMBIENT T Junction Temperature 256-Ball BGA_ED @ J T –40C to +85C N/A N/A N/A N/A –40 +105 C AMBIENT 1Specifications subject to change without notice. 2Applies to input and bidirectional pins: DATAx, ACK, RPBA, BRx, IDx, FLAGx, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, TRST. 3Applies to input pin CLKIN. Rev. H | Page 16 of 60 | March 2019

ADSP-21369 ELECTRICAL CHARACTERISTICS Parameter Description Test Conditions Min Typ Max Unit V 1 High Level Output Voltage @ V = Min, I = –1.0 mA2 2.4 V OH DDEXT OH V 1 Low Level Output Voltage @ V = Min, I = 1.0 mA2 0.4 V OL DDEXT OL I 3, 4 High Level Input Current @ V = Max, V = V Max 10 μA IH DDEXT IN DDEXT I3, 5, 6 Low Level Input Current @ V = Max, V = 0 V 10 μA IL DDEXT IN I 5 High Level Input Current Pull-Down @ V = Max, V = 0 V 250 μA IHPD DDEXT IN I 4 Low Level Input Current Pull-Up @ V = Max, V = 0 V 200 μA ILPU DDEXT IN I 7, 8 Three-State Leakage Current @ V = Max, V = V Max 10 μA OZH DDEXT IN DDEXT I 7, 9 Three-State Leakage Current @ V = Max, V = 0 V 10 μA OZL DDEXT IN I 8 Three-State Leakage Current Pull-Up @ V = Max, V = 0 V 200 μA OZLPU DDEXT IN I 10 Supply Current (Internal) t = 3.75 ns, V = 1.2 V, 25°C 700 mA DD-INTYP CCLK DDINT t = 3.00 ns, V = 1.2 V, 25°C 900 mA CCLK DDINT t = 2.85 ns, V = 1.3 V, 25°C 1050 mA CCLK DDINT t = 2.73 ns, V = 1.3 V, 25°C 1080 mA CCLK DDINT t = 2.50 ns, V = 1.3 V, 25°C 1100 mA CCLK DDINT AI 11 Supply Current (Analog) A = Max 11 mA DD VDD C 12 Input Capacitance f = 1 MHz, T = 25°C, V = 1.3 V 4.7 pF IN IN CASE IN 1Applies to output and bidirectional pins: ADDRx, DATAx, RD, WR, MSx, BRx, FLAGx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDCLKx, EMU, TDO. 2See Output Drive Currents for typical drive current capabilities. 3Applies to input pins without internal pull-ups: BOOT_CFGx, CLK_CFGx, CLKIN, RESET, TCK. 4Applies to input pins with internal pull-ups: ACK, RPBA, TMS, TDI, TRST. 5Applies to input pins with internal pull-downs: IDx. 6Applies to input pins with internal pull-ups disabled: ACK, RPBA. 7Applies to three-statable pins without internal pull-ups: FLAGx, SDCLKx, TDO. 8Applies to three-statable pins with internal pull-ups: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, EMU. 9Applies to three-statable pins with internal pull-ups disabled: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10 10See the Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-21368 SHARC Processors” (EE-299) for further information. 11Characterized, but not tested. 12Applies to all signal pins. ESD CAUTION MAXIMUM POWER DISSIPATION See the Engineer-to-Engineer Note “Estimating Power Dissipa- ESD (electrostatic discharge) sensitive device. tion for ADSP-21368 SHARC Processors” (EE-299) for detailed Charged devices and circuit boards can discharge thermal and power information regarding maximum power dis- without detection. Although this product features sipation. For information on package thermal specifications, see patented or proprietary protection circuitry, damage Thermal Characteristics. may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Rev. H | Page 17 of 60 | March 2019

ADSP-21369 ABSOLUTE MAXIMUM RATINGS Voltage Controlled Oscillator Stresses at or above those listed in Table9 may cause permanent In application designs, the PLL multiplier value should be damage to the product. This is a stress rating only; functional selected in such a way that the VCO frequency never exceeds operation of the product at these or any other conditions above fVCO specified in Table12. those indicated in the operational section of this specification is • The product of CLKIN and PLLM must never exceed 1/2 of not implied. Operation beyond the maximum operating condi- f (max) in Table12 if the input divider is not enabled VCO tions for extended periods may affect product reliability. (INDIV = 0). • The product of CLKIN and PLLM must never exceed f Table 9. Absolute Maximum Ratings VCO (max) in Table12 if the input divider is enabled Parameter Rating (INDIV = 1). Internal (Core) Supply Voltage (V ) –0.3 V to +1.5 V The VCO frequency is calculated as follows: DDINT Analog (PLL) Supply Voltage (A ) –0.3 V to +1.5 V f = 2  PLLM  f VDD VCO INPUT External (I/O) Supply Voltage (V ) –0.3 V to +4.6 V f = (2  PLLM  f )  (2  PLLD) DDEXT CCLK INPUT Input Voltage –0.5 V to +3.8 V where: Output Voltage Swing –0.5 V to VDDEXT + 0.5 V fVCO = VCO output Load Capacitance 200 pF PLLM = Multiplier value programmed in the PMCTL register. Storage Temperature Range –65C to +150C During reset, the PLLM value is derived from the ratio selected Junction Temperature Under Bias 125C using the CLK_CFG pins in hardware. PLLD = Divider value 1, 2, 4, or 8 based on the PLLD value pro- TIMING SPECIFICATIONS grammed on the PMCTL register. During reset this value is 1. Use the exact timing information given. Do not attempt to f = Input frequency to the PLL. INPUT derive parameters from the addition or subtraction of others. f = CLKIN when the input divider is disabled or While addition or subtraction would yield meaningful results INPUT for an individual device, the values given in this data sheet fINPUT = CLKIN  2 when the input divider is enabled reflect statistical variations and worst cases. Consequently, it is Note the definitions of the clock periods that are a function of not meaningful to add parameters to derive longer times. See CLKIN and the appropriate ratio control shown in and Figure40 under Test Conditions for voltage reference levels. Table10. All of the timing specifications for the ADSP-2136x Switching Characteristics specify how the processor changes its peripherals are defined in relation to t . See the peripheral spe- PCLK signals. Circuitry external to the processor must be designed for cific timing section for timing information for each peripheral. compatibility with these signal characteristics. Switching char- acteristics describe what the processor will do in a given Table 10. Clock Periods circumstance. Use switching characteristics to ensure that any Timing timing requirement of a device connected to the processor (such Requirements Description as memory) is satisfied. t CLKIN Clock Period Timing Requirements apply to signals that are controlled by cir- CK t Processor Core Clock Period cuitry external to the processor, such as the data input for a read CCLK operation. Timing requirements guarantee that the processor tPCLK Peripheral Clock Period = 2 × tCCLK operates correctly with other devices. Figure4 shows core to CLKIN relationships with external oscil- Core Clock Requirements lator or crystal. The shaded divider/multiplier blocks denote The processor’s internal clock (a multiple of CLKIN) provides where clock ratios can be set through hardware or software the clock signal for timing internal memory, processor core, and using the power management control register (PMCTL). For serial ports. During reset, program the ratio between the proces- more information, see the processor hardware reference. sor’s internal clock frequency and external (CLKIN) clock frequency with the CLK_CFG1–0 pins. The processor’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the processor uses an internal phase-locked loop (PLL, see Figure4). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the processor’s internal clock. Rev. H | Page 18 of 60 | March 2019

ADSP-21369 PMCTL (SDCKR) PMCTL PLL (PLLBP) XTAL BCULFKIN DCIVLIKDIENR fINPUT FLILOTOEPR VCO fVCO DPIVMPILCDLTELR fCCLK BYPASSMUX CCLK DSIDVRIDAEMR YPASSUXM SDCLK (2xPLLD) B P(IMNDCITVL) MULPTLIPLLIER (PPMLLCBTPL) DBIVYID2E PCLK PCLK CLK_CFGx/PMCTL(2xPLLM) CCLK CLKOUT(TESTONLY) X U DELAYOF M BUF 4096CLKIN N CYCLES IP Figure 4. Core Clock and System Clock Relationship to CLKIN Rev. H | Page 19 of 60 | March 2019

ADSP-21369 Power-Up Sequencing The timing requirements for processor start-up are given in driven low before power up is complete. This leakage current Table11. Note that during power-up, a leakage current of results from the weak internal pull-up resistor on this pin being approximately 200μA may be observed on the RESET pin if it is enabled during power-up. Table 11. Power-Up Sequencing Timing Requirements (Processor Start-up) Parameter Min Max Unit Timing Requirements t RESET Low Before V /V On 0 ns RSTVDD DDINT DDEXT t V On Before V –50 +200 ms IVDDEVDD DDINT DDEXT t 1 CLKIN Valid After V /V Valid 0 200 ms CLKVDD DDINT DDEXT t CLKIN Valid Before RESET Deasserted 102 μs CLKRST t PLL Control Setup Before RESET Deasserted 20 μs PLLRST Switching Characteristic t Core Reset Deasserted After RESET Deasserted 4096t + 2 t 3, 4 CORERST CK CCLK 1Valid V /V assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds DDINT DDEXT depending on the design of the power supply subsystem. 2Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time. Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal. 3Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate default states at all I/O pins. 4The 4096 cycle count depends on t specification in Table13. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles srst maximum. t RSTVDD RESET VDDINT t IVDDEVDD VDDEXT t CLKVDD CLKIN t CLKRST CLK_CFG1–0 t t PLLRST CORERST RESETOUT Figure 5. Power-Up Sequencing Rev. H | Page 20 of 60 | March 2019

ADSP-21369 Clock Input Table 12. Clock Input 400 MHz1 366 MHz2 350 MHz3 333 MHz4 266 MHz5 Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirements t CLKIN Period 156 100 16.396 100 17.146 100 186 100 22.56 100 ns CK t CLKIN Width Low 7.51 45 8.11 45 8.51 45 91 45 11.251 45 ns CKL t CLKIN Width High 7.51 45 8.11 45 8.51 45 91 45 11.251 45 ns CKH t CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 3 3 3 ns CKRF t 7 CCLK Period 2.56 10 2.736 10 2.856 10 3.06 10 3.756 10 ns CCLK f 8 VCO Frequency 100 800 100 800 100 800 100 800 100 600 MHz VCO t 9, 10 CLKIN Jitter Tolerance –250 +250 –250 +250 –250 +250 –250 +250 –250 +250 ps CKJ 1Applies to all 400 MHz models. See Ordering Guide. 2Applies to all 366 MHz models. See Ordering Guide. 3Applies to all 350 MHz models. See Ordering Guide. 4Applies to all 333 MHz models. See Ordering Guide. 5Applies to all 266 MHz models. See Ordering Guide. 6Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL. 7Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t . CCLK 8See Figure4 for VCO diagram. 9Actual input jitter should be combined with ac specifications for accurate timing analysis. 10Jitter specification is maximum peak-to-peak time interval error (TIE) jitter. t t CK CKJ CLKIN t t CKH CKL Figure 6. Clock Input Rev. H | Page 21 of 60 | March 2019

ADSP-21369 Clock Signals The processors can use an external clock or a crystal. See the CLKIN pin description in Table8. Programs can configure the processor to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure7 shows the component connections used for a crystal operating in funda- mental mode. Note that the clock rate is achieved using a 25 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed of 400 MHz). To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register. ADSP-21369 CLKIN R1 XTAL 1MV* R2 47V* C1 C2 22pF Y1 22pF 25.00MHz R2SHOULDBECHOSENTOLIMITCRYSTAL DRIVEPOWER.REFERTOCRYSTAL MANUFACTURER’SSPECIFICATIONS Figure 7. 400 MHz Operation (Fundamental Mode Crystal) Rev. H | Page 22 of 60 | March 2019

ADSP-21369 Reset Table 13. Reset Parameter Min Max Unit Timing Requirements t 1 RESET Pulse Width Low 4t ns WRST CK t RESET Setup Before CLKIN Low 8 ns SRST 1Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than100s while RESET is low, assuming stable V and CLKIN (not including start-up time of external clock oscillator). DD CLKIN t t WRST SRST RESET Figure 8. Reset Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts. Table 14. Interrupts Parameter Min Max Unit Timing Requirement t IRQx Pulse Width 2 × t +2 ns IPW PCLK INTERRUPT INPUTS t IPW Figure 9. Interrupts Rev. H | Page 23 of 60 | March 2019

ADSP-21369 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP). Table 15. Core Timer Parameter Min Max Unit Switching Characteristic t TMREXP Pulse Width 4 × t – 1 ns WCTIM PCLK t WCTIM FLAG3 (TMREXP) Figure 10. Core Timer Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0, Timer1, and Timer2 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins. Table 16. Timer PWM_OUT Timing Parameter Min Max Unit Switching Characteristic t Timer Pulse Width Output 2 × t – 1.2 2 × (231 – 1) × t ns PWMO PCLK PCLK t PWMO PWM OUTPUTS Figure 11. Timer PWM_OUT Timing Rev. H | Page 24 of 60 | March 2019

ADSP-21369 Timer WDTH_CAP Timing The following specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the specification provided in Table17 is valid at the DPI_P14–1 pins. Table 17. Timer Width Capture Timing Parameter Min Max Unit Switching Characteristic t Timer Pulse Width 2 × t 2 × (231 – 1) × t ns PWI PCLK PCLK t PWI TIMER CAPTURE INPUTS Figure 12. Timer Width Capture Timing Pin to Pin Direct Routing (DAI and DPI) For direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O). Table 18. DAI/DPI Pin to Pin Routing Parameter Min Max Unit Timing Requirement t Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid 1.5 12 ns DPIO DAI_Pn DPI_Pn t DPIO DAI_Pm DPI_Pm Figure 13. DAI/DPI Pin to Pin Direct Routing Rev. H | Page 25 of 60 | March 2019

ADSP-21369 Precision Clock Generator (Direct Pin Routing) inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing param- This timing is only valid when the SRU is configured such that eters and switching characteristics apply to external DAI pins the precision clock generator (PCG) takes its inputs directly (DAI_P01–20). from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s Table 19. Precision Clock Generator (Direct Pin Routing) Parameter Min Max Unit Timing Requirements t Input Clock Period t × 4 ns PCGIP PCLK t PCG Trigger Setup Before Falling 4.5 ns STRIG Edge of PCG Input Clock t PCG Trigger Hold After Falling 3 ns HTRIG Edge of PCG Input Clock Switching Characteristics t PCG Output Clock and Frame Sync Active Edge 2.5 10 ns DPCGIO Delay After PCG Input Clock t PCG Output Clock Delay After PCG Trigger 2.5 + (2.5 × t ) 10 + (2.5 × t ) ns DTRIGCLK PCGIP PCGIP t PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D – PH) × t ) 10 + ((2.5 + D – PH) × t ) ns DTRIGFS PCGIP PCGIP t 1 Output Clock Period 2 × t – 1 ns PCGOW PCGIP D = FSxDIV, and PH = FSxPHASE. For more information, see the ADSP-2137x SHARC Processor Hardware Reference, “Precision Clock Gener- ators” chapter. 1In normal mode. t t STRIG HTRIG DAI_Pn DPI_Pn PCG_TRIGx_I DAI_Pm DPI_Pm PCG_EXTx_I (CLKIN) t t DPCGIO PCGIP DAI_Py DPI_Py PCG_CLKx_O tDTRIGCLK tDPCGIO tPCGOW DAI_Pz DPI_Pz PCG_FSx_O t DTRIGFS Figure 14. Precision Clock Generator (Direct Pin Routing) Rev. H | Page 26 of 60 | March 2019

ADSP-21369 Flags The timing specifications provided below apply to the FLAG3–0 and DPI_P14–1 pins, and the serial peripheral interface (SPI). See Table8 for more information on flag use. Table 20. Flags Parameter Min Max Unit Timing Requirement t FLAG3–0 IN Pulse Width 2 × t + 3 ns FIPW PCLK Switching Characteristic t FLAG3–0 OUT Pulse Width 2 × t – 1.5 ns FOPW PCLK FLAG INPUTS t FIPW FLAG OUTPUTS t FOPW Figure 15. Flags Rev. H | Page 27 of 60 | March 2019

ADSP-21369 SDRAM Interface Timing (166 MHz SDCLK) The 166 MHz access speed is for a single processor. When mul- tiple ADSP-21369 processors are connected in a shared memory system, the access speed is 100 MHz. Table 21. SDRAM Interface Timing1 All Other Speed 366 MHz 350 MHz Grades Parameter Min Max Min Max Min Max Unit Timing Requirements t DATA Setup Before SDCLK 500 500 500 ps SSDAT t DATA Hold After SDCLK 1.23 1.23 1.23 ns HSDAT Switching Characteristics t SDCLK Period 6.83 7.14 6.0 ns SDCLK t SDCLK Width High 3 3 2.6 ns SDCLKH t SDCLK Width Low 3 3 2.6 ns SDCLKL t Command, ADDR, Data Delay After SDCLK2 4.8 4.8 4.8 ns DCAD t Command, ADDR, Data Hold After SDCLK2 1.2 1.2 1.2 ns HCAD t Data Disable After SDCLK 5.3 5.3 5.3 ns DSDAT t Data Enable After SDCLK 1.3 1.3 1.3 ns ENSDAT 1The processor needs to be programmed in t = 2.5  t mode when operated at 350 MHz, 366 MHz, and 400 MHz. SDCLK CCLK 2Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE. t t SDCLKH SDCLK SDCLK tSSDAT tHSDAT tSDCLKL DATA (IN) t DCAD t t DSDAT ENSDAT t HCAD DATA (OUT) t t DCAD HCAD COMMAND/ADDR (OUT) Figure 16. SDRAM Interface Timing Rev. H | Page 28 of 60 | March 2019

ADSP-21369 SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Table 22. SDRAM Interface Enable/Disable Timing1 Parameter Min Max Unit Switching Characteristics t Command Disable After CLKIN Rise 2 × t + 3 ns DSDC PCLK t Command Enable After CLKIN Rise 4.0 ns ENSDC t SDCLK Disable After CLKIN Rise 8.5 ns DSDCC t SDCLK Enable After CLKIN Rise 3.8 ns ENSDCC t Address Disable After CLKIN Rise 9.2 ns DSDCA t Address Enable After CLKIN Rise 2 × t – 4 4 × t ns ENSDCA PCLK PCLK 1For f = 400 MHz (SDCLK ratio = 1:2.5). CCLK CLKIN t DSDC t DSDCC COMMAND tDSDCA SDCLK ADDR t ENSDC t ENSDCA t ENSDCC COMMAND SDCLK ADDR Figure 17. SDRAM Interface Enable/Disable Timing Rev. H | Page 29 of 60 | March 2019

ADSP-21369 Memory Read Use these specifications for asynchronous interfacing to memo- ries. These specifications apply when the processors are the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. Table 23. Memory Read Parameter Min Max Unit Timing Requirements t Address, Selects Delay to Data Valid1, 2 W + t – 5.12 ns DAD SDCLK t RD Low to Data Valid2 W – 3.2 ns DRLD t Data Setup to RD High 2.5 ns SDS t Data Hold from RD High3, 4 0 ns HDRH t ACK Delay from Address, Selects1, 5 t – 9.5 + W ns DAAK SDCLK t ACK Delay from RD Low5 W – 7.0 ns DSAK Switching Characteristics t Address Selects Hold After RD High RH + 0.20 ns DRHA t Address Selects to RD Low1 t – 3.3 ns DARL SDCLK t RD Pulse Width W – 1.4 ns RW t RD High to WR, RD Low HI + t – 0.8 ns RWR SDCLK W = (number of wait states specified in AMICTLx register) × t SDCLK RHC = (number of Read Hold Cycles specified in AMICTLx register) × t SDCLK Where PREDIS = 0 HI = RHC (if IC = 0): Read to Read from same bank HI = RHC+ t (if IC > 0): Read to Read from same bank SDCLK HI = RHC + IC: Read to Read from different bank HI = RHC + Max (IC, (4 × t )): Read to Write from same or different bank SDCLK Where PREDIS = 1 HI = RHC + Max (IC, (4 × t )): Read to Write from same or different bank SDCLK HI = RHC + (3 × t ): Read to Read from same bank SDCLK HI = RHC + Max (IC, (3 × t )): Read to Read from different bank SDCLK IC = (number of idle cycles specified in AMICTLx register) × t SDCLK H = (number of hold cycles specified in AMICTLx register) × t SDCLK 1The falling edge of MSx is referenced. 2The maximum limit of timing requirement values for t and t parameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not used. DAD DRLD 3Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. 4Data hold: User must meet t or t in asynchronous access mode. See Test Conditions for the calculation of hold times given capacitive and dc loads. HDA HDRH 5ACK delay/setup: User must meet t , or t , for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet t or t . DAAK DSAK DAAK DSAK Rev. H | Page 30 of 60 | March 2019

ADSP-21369 ADDR MSx t t t DARL RW DRHA RD t t DRLD SDS t t DAD HDRH DATA t t DSAK RWR t DAAK ACK WR Figure 18. Memory Read Rev. H | Page 31 of 60 | March 2019

ADSP-21369 Memory Write access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access Use these specifications for asynchronous interfacing to memo- mode. ries. These specifications apply when the processor is the bus master, accessing external memory space in asynchronous Table 24. Memory Write Parameter Min Max Unit Timing Requirements t ACK Delay from Address, Selects1, 2 t – 9.7 + W ns DAAK SDCLK t ACK Delay from WR Low 1, 3 W – 4.9 ns DSAK Switching Characteristics t Address, Selects to WR Deasserted2 t –3.1+ W ns DAWH SDCLK t Address, Selects to WR Low2 t –2.7 ns DAWL SDCLK t WR Pulse Width W – 1.3 ns WW t Data Setup Before WR High t –3.0+ W ns DDWH SDCLK t Address Hold After WR Deasserted H + 0.15 ns DWHA t Data Hold After WR Deasserted H + 0.02 ns DWHD t WR High to WR, RD Low t –1.5+ H ns WWR SDCLK t Data Disable Before RD Low 2t – 4.11 ns DDWR SDCLK t Data Enabled to WR Low t – 3.5 ns WDE SDCLK W = (number of wait states specified in AMICTLx register) × t . SDCLK H = (number of hold cycles specified in AMICTLx register) × t . SDCLK 1ACK delay/setup: System must meet t , or t , for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet t or t . DAAK DSAK DAAK DSAK 2The falling edge of MSx is referenced. 3Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode. ADDR MSx t t DAWH DWHA t t DAWL WW WR t WWR t WDE t DATRWH t t DDWH DDWR DATA tDSAK tDWHD t DAAK ACK RD Figure 19. Memory Write Rev. H | Page 32 of 60 | March 2019

ADSP-21369 Asynchronous Memory Interface (AMI) Enable/Disable Use these specifications for passing bus mastership between ADSP-21369 processors (BRx). Table 25. AMI Enable/Disable Parameter Min Max Unit Switching Characteristics t Address/Control Enable After Clock Rise 4 ns ENAMIAC t Data Enable After Clock Rise t + 4 ns ENAMID SDCLK t Address/Control Disable After Clock Rise 8.7 ns DISAMIAC t Data Disable After Clock Rise 0 ns DISAMID CLKIN t DISAMIAC t DISAMID ADDR, WR , RD, MS1–0, DATA t ENAMIAC t ADDR , WR , RD, ENAMID MS1–0, DATA Figure 20. AMI Enable/Disable Rev. H | Page 33 of 60 | March 2019

ADSP-21369 Shared Memory Bus Request Use these specifications for passing bus mastership between ADSP-21369 processors (BRx). Table 26. Multiprocessor Bus Request Parameter Min Max Unit Timing Requirements t BRx, Setup Before CLKIN High 9 ns SBRI t BRx, Hold After CLKIN High 0.5 ns HBRI Switching Characteristics t BRx Delay After CLKIN High 9 ns DBRO t BRx Hold After CLKIN High 1.0 ns HBRO CLKIN t DBRO t HBRO BRX(OUT) t t SBRI HBRI BRX(IN) Figure 21. Shared Memory Bus Request Rev. H | Page 34 of 60 | March 2019

ADSP-21369 Serial Ports To determine whether communication is possible between two Serial port signals SCLK, frame sync (FS), data channel A, and devices at clock speed n, the following specifications must be data channel B are routed to the DAI_P20–1 pins using the confirmed: 1) frame sync delay and frame sync setup and hold, SRU. Therefore, the timing specifications provided in Table27 2) data delay and data setup and hold, and 3) SCLK width. are valid at the DAI_P20–1 pins. Table 27. Serial Ports—External Clock 400 MHz 366 MHz 350 MHz 333 MHz 266 MHz Parameter Min Max Min Max Min Max Unit Timing Requirements t 1 FS Setup Before SCLK 2.5 2.5 2.5 ns SFSE (Externally Generated FS in Either Transmit or Receive Mode) t 1 FS Hold After SCLK 2.5 2.5 2.5 ns HFSE (Externally Generated FS in Either Transmit or Receive Mode) t 1 Receive Data Setup Before Receive 1.9 2.0 2.5 ns SDRE SCLK t 1 Receive Data Hold After SCLK 2.5 2.5 2.5 ns HDRE t SCLK Width (t × 4) ÷ 2 – 0.5 (t × 4) ÷ 2 – 0.5 (t × 4) ÷ 2 – 0.5 ns SCLKW PCLK PCLK PCLK t SCLK Period t × 4 t × 4 t × 4 ns SCLK PCLK PCLK PCLK Switching Characteristics t 2 FS Delay After SCLK 10.25 10.25 10.25 ns DFSE (Internally Generated FS in Either Transmit or Receive Mode) t 2 FS Hold After SCLK 2 2 2 ns HOFSE (Internally Generated FS in Either Transmit or Receive Mode) t 2 Transmit Data Delay After Transmit 7.8 9.6 9.8 ns DDTE SCLK t 2 Transmit Data Hold After Transmit 2 2 2 ns HDTE SCLK 1Referenced to sample edge. 2Referenced to drive edge. Rev. H | Page 35 of 60 | March 2019

ADSP-21369 Table 28. Serial Ports—Internal Clock Parameter Min Max Unit Timing Requirements t 1 FS Setup Before SCLK 7 ns SFSI (Externally Generated FS in Either Transmit or Receive Mode) t 1 FS Hold After SCLK 2.5 ns HFSI (Externally Generated FS in Either Transmit or Receive Mode) t 1 Receive Data Setup Before SCLK 7 ns SDRI t 1 Receive Data Hold After SCLK 2.5 ns HDRI Switching Characteristics t 2 FS Delay After SCLK (Internally Generated FS in Transmit Mode) 4 ns DFSI t 2 FS Hold After SCLK (Internally Generated FS in Transmit Mode) –1.0 ns HOFSI t 2 FS Delay After SCLK (Internally Generated FS in Receive Mode) 9.75 ns DFSIR t 2 FS Hold After SCLK (Internally Generated FS in Receive Mode) –1.0 ns HOFSIR t 2 Transmit Data Delay After SCLK 3.25 ns DDTI t 2 Transmit Data Hold After SCLK –1.0 ns HDTI t 3 Transmit or Receive SCLK Width 2 × t – 1.5 2 × t + 1.5 ns SCLKIW PCLK PCLK 1Referenced to the sample edge. 2Referenced to drive edge. 3Minimum SPORT divisor register value. Table 29. Serial Ports—Enable and Three-State Parameter Min Max Unit Switching Characteristics t 1 Data Enable from External Transmit SCLK 2 ns DDTEN t 1 Data Disable from External Transmit SCLK 10 ns DDTTE t 1 Data Enable from Internal Transmit SCLK –1 ns DDTIN 1Referenced to drive edge. Table 30. Serial Ports—External Late Frame Sync Parameter Min Max Unit Switching Characteristics t 1 Data Delay from Late External Transmit FS or External Receive 7.75 ns DDTLFSE FS with MCE = 1, MFD = 0 t 1 Data Enable for MCE = 1, MFD = 0 0.5 ns DDTENFS 1The t and t parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0. DDTLFSE DDTENFS Rev. H | Page 36 of 60 | March 2019

ADSP-21369 DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE t t SCLKIW SCLKW DAI_P20–1 DAI_P20–1 (SCLK) (SCLK) t t DFSI DFSE t t t t t t HOFSI SFSI HFSI HOFSE SFSE HFSE DAI_P20–1 DAI_P20–1 (FS) (FS) t t t t SDRI HDRI SDRE HDRE DAI_P20–1 DAI_P20–1 (DATA (DATA CHANNEL A/B) CHANNEL A/B) DATA TRANSMIT—INTERNAL CLOCK DATA TRANSMIT—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE t t SCLKIW SCLKW DAI_P20–1 DAI_P20–1 (SCLK) (SCLK) t t DFSI DFSE t t t t t t HOFSI SFSI HFSI HOFSE SFSE HFSE DAI_P20–1 DAI_P20–1 (FS) (FS) t t DDTI DDTE t t HDTI HDTE DAI_P20–1 DAI_P20–1 (DATA (DATA CHANNEL A/B) CHANNEL A/B) Figure 22. Serial Ports DRIVE EDGE DRIVE EDGE DAI_P20–1 (SCLK, EXT) t t DDTEN DDTTE DAI_P20–1 (DATA CHANNEL A/B) DRIVE EDGE DAI_P20–1 (SCLK, INT) t DDTIN DAI_P20–1 (DATA CHANNEL A/B) Figure 23. Enable and Three-State Rev. H | Page 37 of 60 | March 2019

ADSP-21369 EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE DAI_P20–1 (SCLK) t HFSE/I t SFSE/I DAI_P20–1 (FS) t DDTE/I t DDTENFS t HDTE/I DAI_P20–1 (DATA CHANNEL 1ST BIT 2ND BIT A/B) t DDTLFSE LATE EXTERNAL TRANSMIT FS DRIVE SAMPLE DRIVE DAI_P20–1 (SCLK) t HFSE/I t SFSE/I DAI_P20–1 (FS) t DDTE/I t DDTENFS t HDTE/I DAI_P20–1 (DATA CHANNEL 1ST BIT 2ND BIT A/B) t DDTLFSE Figure 24. External Late Frame Sync1 1This figure reflects changes made to support left-justified sample pair mode. Rev. H | Page 38 of 60 | March 2019

ADSP-21369 Input Data Port The timing requirements for the IDP are given in Table31. IDP signals SCLK, frame sync (FS), and SDATA are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifica- tions provided in Table31 are valid at the DAI_P20–1 pins. Table 31. IDP Parameter Min Max Unit Timing Requirements t 1 FS Setup Before SCLK Rising Edge 4 ns SISFS t 1 FS Hold After SCLK Rising Edge 2.5 ns SIHFS t 1 SDATA Setup Before SCLK Rising Edge 2.5 ns SISD t 1 SDATA Hold After SCLK Rising Edge 2.5 ns SIHD t Clock Width (t × 4) ÷ 2 – 1 ns IDPCLKW PCLK t Clock Period t × 4 ns IDPCLK PCLK 1 DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tIDPCLK t IDPCLKW DAI_P20–1 (SCLK) t t SISFS SIHFS DAI_P20–1 (FS) t SISD t SIHD DAI_P20–1 (SDATA) Figure 25. IDP Master Timing Rev. H | Page 39 of 60 | March 2019

ADSP-21369 Parallel Data Acquisition Port (PDAP) For details on the operation of the IDP, see the “Input Data Port” chapter of the ADSP-2137x SHARC Processor Hardware The timing requirements for the PDAP are provided in Reference. Note that the 20 bits of external PDAP data can be Table32. PDAP is the parallel mode operation of Channel 0 of provided through the external port DATA31–12 pins or the the input data port (IDP). DAI pins. Table 32. Parallel Data Acquisition Port (PDAP) Parameter Min Max Unit Timing Requirements t 1 PDAP_HOLD Setup Before PDAP_CLK Sample Edge 2.5 ns SPHOLD t 1 PDAP_HOLD Hold After PDAP_CLK Sample Edge 2.5 ns HPHOLD t 1 PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 3.85 ns PDSD t 1 PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 2.5 ns PDHD t Clock Width (t × 4) ÷ 2 – 3 ns PDCLKW PCLK t Clock Period t × 4 ns PDCLK PCLK Switching Characteristics t Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × t + 3 ns PDHLDD PCLK t PDAP Strobe Pulse Width 2 × t – 1 ns PDSTRB PCLK 1Data Source pins are DATA31–12, or DAI pins. Source pins for SCLK and FS are: 1) DATA11–10 pins, 2) DAI pins. SAMPLE EDGE t PDCLK t PDCLKW DAI_P20–1 (PDAP_CLK) t t SPHOLD HPHOLD DAI_P20–1 (PDAP_HOLD) tPDSD tPDHD DAI_P20–1/ ADDR23–4 (PDAP_DATA) t t PDHLDD PDSTRB DAI_P20–1 (PDAP_STROBE) Figure 26. PDAP Timing Rev. H | Page 40 of 60 | March 2019

ADSP-21369 Pulse-Width Modulation Generators Table 33. PWM Timing Parameter Min Max Unit Switching Characteristics t PWM Output Pulse Width t – 2 (216 – 2) × t ns PWMW PCLK PCLK t PWM Output Period 2 × t – 1.5 (216 – 1) × t ns PWMP PCLK PCLK t PWMW PWM OUTPUTS t PWMP Figure 27. PWM Timing Sample Rate Converter—Serial Input Port The SRC input signals SCLK, frame sync (FS), and SDATA are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table34 are valid at the DAI_P20–1 pins. Table 34. SRC, Serial Input Port Parameter Min Max Unit Timing Requirements t 1 FS Setup Before SCLK Rising Edge 4 ns SRCSFS t 1 FS Hold After SCLK Rising Edge 5.5 ns SRCHFS t 1 SDATA Setup Before SCLK Rising Edge 4 ns SRCSD t 1 SDATA Hold After SCLK Rising Edge 5.5 ns SRCHD t Clock Width (t × 4) ÷ 2 – 1 ns SRCCLKW PCLK t Clock Period t × 4 ns SRCCLK PCLK 1 DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. Rev. H | Page 41 of 60 | March 2019

ADSP-21369 SAMPLE EDGE t SRCCLK DAI_P20–1 tSRCCLKW (SCLK) t t SRCSFS SRCHFS DAI_P20–1 (FS) t t SRCSD SRCHD DAI_P20–1 (SDATA) Figure 28. SRC Serial Input Port Timing Rev. H | Page 42 of 60 | March 2019

ADSP-21369 Sample Rate Converter—Serial Output Port and delay specification with regard to SCLK. Note that SCLK rising edge is the sampling edge and the falling edge is the For the serial output port, the frame-sync is an input and it drive edge. should meet setup and hold times with regard to SCLK on the output port. The serial data output, SDATA, has a hold time Table 35. SRC, Serial Output Port Parameter Min Max Unit Timing Requirements t 1 FS Setup Before SCLK Rising Edge 4 ns SRCSFS t 1 FS Hold After SCLK Rising Edge 5.5 ns SRCHFS t Clock Width (t × 4) ÷ 2 – 1 ns SRCCLKW PCLK t Clock Period t × 4 ns SRCCLK PCLK Switching Characteristics t 1 Transmit Data Delay After SCLK Falling Edge 9.9 ns SRCTDD t 1 Transmit Data Hold After SCLK Falling Edge 1 ns SRCTDH 1 DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE t SRCCLK DAI_P20–1 tSRCCLKW (SCLK) t t SRCSFS SRCHFS DAI_P20–1 (FS) t SRCTDD t SRCTDH DAI_P20–1 (SDATA) Figure 29. SRC Serial Output Port Timing Rev. H | Page 43 of 60 | March 2019

ADSP-21369 S/PDIF Transmitter mode) from an LRCLK transition, so that when there are 64 SCLK periods per LRCLK period, the LSB of the data is right- Serial data input to the S/PDIF transmitter can be formatted as justified to the next LRCLK transition. left justified, I2S, or right justified with word widths of 16, 18, 20, or 24 bits. The following sections provide timing for the Figure31 shows the default I2S-justified mode. LRCLK is low transmitter. for the left channel and high for the right channel. Data is valid on the rising edge of SCLK. The MSB is left-justified to an S/PDIF Transmitter—Serial Input Waveforms LRCLK transition but with a single SCLK period delay. Figure30 shows the right-justified mode. LRCLK is high for the left channel and low for the right channel. Data is valid on the rising edge of SCLK. The MSB is delayed 12-bit clock periods (in 20-bit output mode) or 16-bit clock periods (in 16-bit output DAI_P20–1 LEFT/RIGHT CHANNEL FS DAI_P20–1 SCLK t RJD DAI_P20–1 LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB SDATA Figure 30. Right-Justified Mode DAI_P20–1 LEFT/RIGHT CHANNEL FS DAI_P20–1 SCLK t I2SD DAI_P20–1 SDATA MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB Figure 31. I2S-Justified Mode Rev. H | Page 44 of 60 | March 2019

ADSP-21369 Figure32 shows the left-justified mode. LRCLK is high for the S/PDIF Transmitter Input Data Timing left channel and low for the right channel. Data is valid on the The timing requirements for the input port are given in rising edge of SCLK. The MSB is left-justified to an LRCLK Table36. Input signals SCLK, frame sync (FS), and SDATA are transition with no MSB delay. routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table36 are valid at the DAI_P20–1 pins. DAI_P20–1 LEFT/RIGHT CHANNEL FS DAI_P20–1 SCLK t LJD DAI_P20–1 SDATA MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB Figure 32. Left-Justified Mode Table 36. S/PDIF Transmitter Input Data Timing Parameter Min Max Unit Timing Requirements t 1 FS Setup Before SCLK Rising Edge 3 ns SISFS t 1 FS Hold After SCLK Rising Edge 3 ns SIHFS t 1 SDATA Setup Before SCLK Rising Edge 3 ns SISD t 1 SDATA Hold After SCLK Rising Edge 3 ns SIHD t Clock Width 36 ns SISCLKW t Clock Period 80 ns SISCLK t Transmit Clock Width 9 ns SITXCLKW t Transmit Clock Period 20 ns SITXCLK 1 DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE t t SITXCLKW SITXCLK DAI_P20–1 (TxCLK) t SISCLK t SISCLKW DAI_P20–1 (SCLK) t t SISFS SIHFS DAI_P20–1 (FS) t t SISD SIHD DAI_P20–1 (SDATA) Figure 33. S/PDIF Transmitter Input Timing Rev. H | Page 45 of 60 | March 2019

ADSP-21369 Oversampling Clock (TxCLK) Switching Characteristics The S/PDIF transmitter has an oversampling clock. This TxCLK input is divided down to generate the biphase clock. Table 37. Oversampling Clock (TxCLK) Switching Characteristics Parameter Min Max Unit TxCLK Frequency for TxCLK = 384 × FS Oversampling Ratio × FS <= 1/t MHz SITXCLK TxCLK Frequency for TxCLK = 256 × FS 49.2 MHz Frame Rate (FS) 192.0 kHz S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 38. S/PDIF Receiver Internal Digital PLL Mode Timing Parameter Min Max Unit Switching Characteristics t LRCLK Delay After SCLK 5 ns DFSI t LRCLK Hold After SCLK –2 ns HOFSI t Transmit Data Delay After SCLK 5 ns DDTI t Transmit Data Hold After SCLK –2 ns HDTI t 1 Transmit SCLK Width 40 ns SCLKIW 1SCLK frequency is 64 × FS where FS = the frequency of LRCLK. DRIVE EDGE SAMPLE EDGE t SCLKIW DAI_P20–1 (SCLK) t DFSI t HOFSI DAI_P20–1 (FS) t DDTI t HDTI DAI_P20–1 (DATA CHANNEL A/B) Figure 34. S/PDIF Receiver Internal Digital PLL Mode Timing Rev. H | Page 46 of 60 | March 2019

ADSP-21369 SPI Interface—Master The processors contain two SPI ports. The primary has dedi- cated pins and the secondary is available through the DPI. The timing provided in Table39 and Table40 applies to both. Table 39. SPI Interface Protocol—Master Switching and Timing Specifications Parameter Min Max Unit Timing Requirements t Data Input Valid to SPICLK Edge (Data Input Setup Time) 8.2 ns SSPIDM t SPICLK Last Sampling Edge to Data Input Not Valid 2 ns HSPIDM Switching Characteristics t Serial Clock Cycle 8 × t – 2 ns SPICLKM PCLK t Serial Clock High Period 4 × t – 2 ns SPICHM PCLK t Serial Clock Low Period 4 × t – 2 ns SPICLM PCLK t SPICLK Edge to Data Out Valid (Data Out Delay Time) 2.5 ns DDSPIDM t SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 4 × t – 2 ns HDSPIDM PCLK t DPI Pin (SPI Device Select) Low to First SPICLK Edge 4 × t – 2 ns SDSCIM PCLK t Last SPICLK Edge to DPI Pin (SPI Device Select) High 4 × t – 2 ns HDSM PCLK t Sequential Transfer Delay 4 × t – 1 ns SPITDM PCLK DPI (OUTPUT) t t t SDSCIM SPICHM SPICLM t t t SPICLKM HDSM SPITDM SPICLK (CP = 0, CP = 1) (OUTPUT) t t HDSPIDM DDSPIDM MOSI (OUTPUT) t t CPHASE = 1 SSPIDM SSPIDM t t HSPIDM HSPIDM MISO (INPUT) t t DDSPIDM HDSPIDM MOSI (OUTPUT) t t CPHASE = 0 SSPIDM HSPIDM MISO (INPUT) Figure 35. SPI Master Timing Rev. H | Page 47 of 60 | March 2019

ADSP-21369 SPI Interface—Slave Table 40. SPI Interface Protocol—Slave Switching and Timing Specifications Parameter Min Max Unit Timing Requirements t Serial Clock Cycle 4 × t – 2 ns SPICLKS PCLK t Serial Clock High Period 2 × t – 2 ns SPICHS PCLK t Serial Clock Low Period 2 × t – 2 ns SPICLS PCLK t SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1 2 × t ns SDSCO PCLK t Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × t ns HDS PCLK t Data Input Valid to SPICLK Edge (Data Input Setup Time) 2 ns SSPIDS t SPICLK Last Sampling Edge to Data Input Not Valid 2 ns HSPIDS t SPIDS Deassertion Pulse Width (CPHASE = 0) 2 × t ns SDPPW PCLK Switching Characteristics t SPIDS Assertion to Data Out Active 0 6.8 ns DSOE t 1 SPIDS Assertion to Data Out Active (SPI2) 0 8 ns DSOE t SPIDS Deassertion to Data High Impedance 0 6.8 ns DSDHI t 1 SPIDS Deassertion to Data High Impedance (SPI2) 0 8.6 ns DSDHI t SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.5 ns DDSPIDS t SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t ns HDSPIDS PCLK t SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × t ns DSOV PCLK 1The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the ADSP-2137x SHARC Processor Hardware Reference, “Serial Peripheral Interface Port” chapter. SPIDS (INPUT) t t t t t SPICHS SPICLS SPICLKS HDS SDPPW SPICLK (CP = 0, CP = 1) (INPUT) t SDSCO t t DSDHI t DDSPIDS DSOE t t DDSPIDS HDSPIDS MISO (OUTPUT) CPHASE = 1 tSSPIDS tHSPIDS MOSI (INPUT) t HDSPIDS t DSDHI MISO (OUTPUT) t DSOV t CPHASE = 0 HSPIDS t SSPIDS MOSI (INPUT) Figure 36. SPI Slave Timing Rev. H | Page 48 of 60 | March 2019

ADSP-21369 JTAG Test Access Port and Emulation Table 41. JTAG Test Access Port and Emulation Parameter Min Max Unit Timing Requirements t TCK Period t ns TCK CK t TDI, TMS Setup Before TCK High 5 ns STAP t TDI, TMS Hold After TCK High 6 ns HTAP t 1 System Inputs Setup Before TCK High 7 ns SSYS t 1 System Inputs Hold After TCK High 18 ns HSYS t TRST Pulse Width 4t ns TRSTW CK Switching Characteristics t TDO Delay from TCK Low 7 ns DTDO t 2 System Outputs Delay After TCK Low t ÷ 2 + 7 ns DSYS CK 1System Inputs = AD15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0. 2System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, EMU. t TCK TCK t t STAP HTAP TMS TDI t DTDO TDO t t SSYS HSYS SYSTEM INPUTS t DSYS SYSTEM OUTPUTS Figure 37. IEEE 1149.1 JTAG Test Access Port Rev. H | Page 49 of 60 | March 2019

ADSP-21369 OUTPUT DRIVE CURRENTS TEST CONDITIONS Figure38 shows typical I-V characteristics for the output driv- The AC signal specifications (timing parameters) appear in ers and Figure39 shows typical I-V characteristics for the Table13 through Table41. These include output disable time, SDCLK output drivers. The curves represent the current drive output enable time, and capacitive loading. The timing specifi- capability of the output drivers as a function of output voltage. cations for the SHARC apply for the voltage reference levels in Figure40. Timing is measured on signals when they cross the 1.5V level as 40 described in Figure40. All delays (in nanoseconds) are mea- 30 VOH 3.3V,25°C sured between the point that the first signal reaches 1.5V and the point that the second signal reaches 1.5V. )Am 20 3.47V,-45°C ( T EN 10 3.11V,125°C R R CU 0 3.11V,105°C INOPRUT 1.5V 1.5V )XT OUTPUT DE -10 3.11V,125°C VD 3.11V,105°C ( E -20 RC 3.3V,25°C Figure 40. Voltage Reference Levels for AC Measurements U SO -30 VOL CAPACITIVE LOADING -40 3.47V,-45°C 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Output delays and holds are based on standard capacitive loads SWEEP(VDDEXT)VOLTAGE(V) of an average of 6 pF on all pins (see Figure41). Figure46 and Figure47 show graphically how output delays and holds vary Figure 38. Typical Drive at Junction Temperature with load capacitance. The graphs of Figure42 through Figure47 may not be linear outside the ranges shown for Typi- cal Output Delay vs. Load Capacitance and Typical Output Rise 75 Time (20% to 80%, V = Min) vs. Load Capacitance. 60 VOH )Am 45 3.47V,-45°C ( 3.3V,25°C T 30 TESTER PIN ELECTRONICS N E 3.13V,125°C R 15 R CU 0 3.13V,105°C 1.5V T1 )VDDEXT --3105 3.13V,125°C 70(cid:58) 45(cid:58) OUDTUPTUT ( E -45 3.13V,105°C OURC -60 3.3V,25°C 50(cid:58) ZTOD == 45.00(cid:58)4(cid:3) ((cid:2)i m1.p1e8d nasnce) S -75 3.47V,-45°C 4pF 2pF 0.5pF -90 VOL -105 400(cid:58) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 SWEEP(VDDEXT)VOLTAGE(V) NOTES: Figure 39. SDCLK1–0 Drive at Junction Temperature THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES. Figure 41. Equivalent Device Loading for AC Measurements (Includes All Fixtures) Rev. H | Page 50 of 60 | March 2019

ADSP-21369 12 10 RISE RISE 10 8 )s y=0.049x+1.5105 FALL )s y=0.0372x+0.228 n n ( ( S 8 S E E M M 6 IT IT LL 6 LL FALL A A F F D y=0.0482x+1.4604 D 4 y=0.0277x+0.369 N N A 4 A E E S S IR IR 2 2 0 0 0 50 100 150 200 250 0 50 100 150 200 250 LOADCAPACITANCE(pF) LOADCAPACITANCE(pF) Figure 42. Typical Output Rise/Fall Time Figure 44. SDCLK Typical Output Rise/Fall Time (20% to 80%, V = Min) (20% to 80%, V = Min) DDEXT DDEXT 12 10 RISE 10 y=0.0467x+1.6323 RISE 8 )(nsESM 8 FALL )(nsESM 6 y=0.0364x+0.197 IT IT ALL 6 ALL FALL F F ND y=0.045x+1.524 ND 4 A 4 A y=0.0259x+0.311 ISER IRSE 2 2 0 0 0 50 100 150 200 250 0 50 100 150 200 250 LOADCAPACITANCE(pF) LOADCAPACITANCE(pF) Figure 43. Typical Output Rise/Fall Time Figure 45. SDCLK Typical Output Rise/Fall Time (20% to 80%, V = Max) DDEXT (20% to 80%, V = Max) DDEXT Rev. H | Page 51 of 60 | March 2019

ADSP-21369 To determine the junction temperature of the device while on 10 the application PCB, use: T = T + P  8 J TOP JT D )s n ( 6 where: D L y=0.0488x-1.5923 HO 4 TJ = junction temperature (C) R O T = case temperature (C) measured at the top center of the Y TOP LA 2 package E D T  = junction-to-top (of package) characterization parameter is U 0 JT P T the typical value from Table42 and Table43. U O -2 P = power dissipation (see Engineer-to-Engineer Note EE-299) D -4 Values of JA are provided for package comparison and PCB 0 50 100 150 200 design considerations.  can be used for a first-order approxi- JA mation of T by the equation: LOADCAPACITANCE(pF) J T = T + P  J A JA D Figure 46. Typical Output Delay or Hold vs. Load Capacitance (at Junction Temperature) where: T = ambient temperature (C) A 8 Values of  are provided for package comparison and PCB JC design considerations when an external heat sink is required. This is only applicable when a heat sink is used. 6 y=0.0256x-0.021 )s Values of  are provided for package comparison and PCB n JB ( S design considerations. The thermal characteristics values pro- E ITM 4 vided in Table42 and Table43 are modeled values at 2 W. L L A F Table 42. Thermal Characteristics for 256-Ball BGA_ED D 2 N A E Parameter Condition Typical Unit S IR 0 JA Airflow = 0 m/s 12.5 C/W  Airflow = 1 m/s 10.6 C/W JMA  Airflow = 2 m/s 9.9 C/W -2 JMA 0 50 100 150 200  0.7 C/W JC LOADCAPACITANCE(pF)  5.3 C/W JB  Airflow = 0 m/s 0.3 C/W Figure 47. SDCLK Typical Output Delay or Hold vs. Load Capacitance JT  Airflow = 1 m/s 0.3 C/W (at Junction Temperature) JMT  Airflow = 2 m/s 0.3 C/W JMT THERMAL CHARACTERISTICS Table 43. Thermal Characteristics for 208-Lead LQFP EPAD The processor is rated for performance over the temperature (with Exposed Pad Soldered to PCB) range specified in Operating Conditions. Table42 and Table43 airflow measurements comply with Parameter Condition Typical Unit JEDEC standards JESD51-2 and JESD51-6 and the junction-to-  Airflow = 0 m/s 17.1 C/W JA board measurement complies with JESD51-8. The test board  Airflow = 1 m/s 14.7 C/W JMA design complies with JEDEC standards JESD51-9 (BGA_ED)  Airflow = 2 m/s 14.0 C/W and JESD51-8 (LQFP_EP). The junction-to-case measurement JMA  9.6 C/W complies with MIL-STD-883. All measurements use a 2S2P JC JEDEC test board. JT Airflow = 0 m/s 0.23 C/W  Airflow = 1 m/s 0.39 C/W The LQFP-EP package requires thermal trace squares and ther- JMT mal vias, to an embedded ground plane, in the PCB. Refer to JMT Airflow = 2 m/s 0.45 C/W JEDEC standard JESD51-5 for more information.  Airflow = 0 m/s 11.5 C/W JB  Airflow = 1 m/s 11.2 C/W JMB  Airflow = 2 m/s 11.0 C/W JMB Rev. H | Page 52 of 60 | March 2019

ADSP-21369 256-BALL BGA_ED PINOUT The following table shows the pin names and their default func- tion after reset (in parentheses) for the ADSP-21369 processor. Table 44. 256-Ball BGA_ED Pin Assignment (Numerically by Ball Number) Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal A01 NC B01 DAI_P05 (SD1A) C01 DAI_P09 (SD2A) D01 DAI_P10 (SD2B) A02 TDI B02 SDCLK11 C02 DAI_P07 (SCLK1) D02 DAI_P06 (SD1B) A03 TMS B03 TRST C03 GND D03 GND A04 CLK_CFG0 B04 TCK C04 V D04 V DDEXT DDEXT A05 CLK_CFG1 B05 BOOT_CFG0 C05 GND D05 GND A06 EMU B06 BOOT_CFG1 C06 GND D06 V DDEXT A07 DAI_P04 (SFS0) B07 TDO C07 V D07 V DDINT DDINT A08 DAI_P01 (SD0A) B08 DAI_P03 (SCLK0) C08 GND D08 GND A09 DPI_P14 (TIMER1) B09 DAI_P02 (SD0B) C09 GND D09 V DDEXT A10 DPI_P12 (TWI_CLK) B10 DPI_P13 (TIMER0) C10 V D10 V DDINT DDINT A11 DPI_P10 (UART0RX) B11 DPI_P11 (TWI_DATA) C11 GND D11 GND A12 DPI_P09 (UART0TX) B12 DPI_P08 (SPIFLG3) C12 GND D12 V DDEXT A13 DPI_P07 (SPIFLG2) B13 DPI_P05 (SPIFLG0) C13 V D13 V DDINT DDINT A14 DPI_P06 (SPIFLG1) B14 DPI_P04 (SPIDS) C14 GND D14 GND A15 DPI_P03 (SPICLK) B15 DPI_P01 (SPIMOSI) C15 GND D15 V DDEXT A16 DPI_P02 (SPIMISO) B16 RESET C16 V D16 GND DDINT A17 RESETOUT B17 DATA30 C17 V D17 V DDINT DDEXT A18 DATA31 B18 DATA29 C18 V D18 GND DDINT A19 NC B19 DATA28 C19 DATA27 D19 DATA26 A20 NC B20 NC C20 RPBA D20 DATA24 E01 DAI_P11 (SD3A) F01 DAI_P14 (SFS3) G01 DAI_P15 (SD4A) H01 DAI_P17 (SD5A) E02 DAI_P08 (SFS1) F02 DAI_P12 (SD3B) G02 DAI_P13 (SCLK3) H02 DAI_P16 (SD4B) E03 V F03 GND G03 GND H03 V DDINT DDINT E04 V F04 GND G04 V H04 V DDINT DDEXT DDINT E17 GND F17 V G17 V H17 V DDEXT DDINT DDEXT E18 GND F18 GND G18 V H18 GND DDINT E19 DATA25 F19 ID2 G19 DATA22 H19 DATA19 E20 DATA23 F20 DATA21 G20 DATA20 H20 DATA18 J01 DAI_P19 (SCLK5) K01 FLAG0 L01 FLAG2 M01 ACK J02 DAI_P18 (SD5B) K02 DAI_P20 (SFS5) L02 FLAG1 M02 FLAG3 J03 GND K03 GND L03 V M03 GND DDINT J04 GND K04 V L04 V M04 GND DDEXT DDINT J17 GND K17 V L17 V M17 V DDINT DDINT DDEXT J18 GND K18 V L18 V M18 GND DDINT DDINT J19 ID1 K19 ID0 L19 DATA15 M19 DATA12 J20 DATA17 K20 DATA16 L20 DATA14 M20 DATA13 Rev. H | Page 53 of 60 | March 2019

ADSP-21369 Table 44. 256-Ball BGA_ED Pin Assignment (Numerically by Ball Number) (Continued) Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal N01 RD P01 SDA10 R01 SDWE T01 SDCKE N02 SDCLK0 P02 WR R02 SDRAS T02 SDCAS N03 GND P03 V R03 GND T03 GND DDINT N04 V P04 V R04 GND T04 V DDEXT DDINT DDEXT N17 GND P17 V R17 V T17 GND DDINT DDEXT N18 GND P18 V R18 GND T18 GND DDINT N19 DATA11 P19 DATA8 R19 DATA6 T19 DATA5 N20 DATA10 P20 DATA9 R20 DATA7 T20 DATA4 U01 MS0 V01 ADDR22 W01 GND Y01 GND U02 MS1 V02 ADDR23 W02 ADDR21 Y02 NC U03 V V03 V W03 ADDR19 Y03 NC DDINT DDINT U04 GND V04 GND W04 ADDR20 Y04 ADDR18 U05 V V05 GND W05 ADDR17 Y05 BR1 DDEXT U06 GND V06 GND W06 ADDR16 Y06 BR2 U07 V V07 GND W07 ADDR15 Y07 XTAL DDEXT U08 V V08 V W08 ADDR14 Y08 CLKIN DDINT DDINT U09 V V09 GND W09 A Y09 NC DDEXT VDD U10 GND V10 GND W10 A Y10 NC VSS U11 V V11 GND W11 ADDR13 Y11 BR3 DDEXT U12 V V12 V W12 ADDR12 Y12 BR4 DDINT DDINT U13 V V13 V W13 ADDR10 Y13 ADDR11 DDEXT DDEXT U14 V V14 GND W14 ADDR8 Y14 ADDR9 DDEXT U15 V V15 V W15 ADDR5 Y15 ADDR7 DDINT DDINT U16 V V16 GND W16 ADDR4 Y16 ADDR6 DDEXT U17 V V17 GND W17 ADDR1 Y17 ADDR3 DDINT U18 V V18 GND W18 ADDR2 Y18 GND DDINT U19 DATA0 V19 DATA1 W19 ADDR0 Y19 GND U20 DATA2 V20 DATA3 W20 NC Y20 NC 1The SDCLK1 signal is only available on the FCBGA package. SDCLK1 is not available on the LQFP_EP package. Rev. H | Page 54 of 60 | March 2019

ADSP-21369 Figure48 shows the bottom view of the BGA_ED ball configu- ration. Figure49 shows the top view of the BGA_ED ball configuration. 2 4 6 8 10 12 14 16 18 20 2019181716151413121110 9 8 7 6 5 4 3 2 1 1 3 5 7 9 11 13 15 17 19 A A B B C C D D E E F F G G H H J BOTTOM J TOP K VIEW LK VIEW L M M N N P P R R T T U U V V W W Y Y KEY KEY VDDINT VDDEXT AVDD AVSS VDDINT VDDEXT AVDD AVSS I/OSIGNALS GND NOCONNECT I/OSIGNALS GND NOCONNECT Figure 48. 256-Ball BGA_ED Ball Configuration (Bottom View) Figure 49. 256-Ball BGA_ED Ball Configuration (Top View) Rev. H | Page 55 of 60 | March 2019

ADSP-21369 208-LEAD LQFP_EP PINOUT The following table shows the pin names and their default func- tion after reset (in parentheses) for the ADSP-21369 processor. Table 45. 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number) Lead Lead Lead Lead Lead No. Signal No. Signal No. Signal No. Signal No. Signal 1 V 43 V 85 V 127 V 169 CLK_CFG0 DDINT DDINT DDEXT DDINT 2 DATA28 44 DATA4 86 GND 128 GND 170 BOOT_CFG0 3 DATA27 45 DATA5 87 V 129 V 171 CLK_CFG1 DDINT DDEXT 4 GND 46 DATA2 88 ADDR14 130 DAI_P19 (SCLK5) 172 EMU 5 V 47 DATA3 89 GND 131 DAI_P18 (SD5B) 173 BOOT_CFG1 DDEXT 6 DATA26 48 DATA0 90 V 132 DAI_P17 (SD5A) 174 TDO DDEXT 7 DATA25 49 DATA1 91 ADDR15 133 DAI_P16 (SD4B) 175 DAI_P04 (SFS0) 8 DATA24 50 V 92 ADDR16 134 DAI_P15 (SD4A) 176 DAI_P02 (SD0B) DDEXT 9 DATA23 51 GND 93 ADDR17 135 DAI_P14 (SFS3) 177 DAI_P03 (SCLK0) 10 GND 52 V 94 ADDR18 136 DAI_P13 (SCLK3) 178 DAI_P01 (SD0A) DDINT 11 V 53 V 95 GND 137 DAI_P12 (SD3B) 179 V DDINT DDINT DDEXT 12 DATA22 54 GND 96 V 138 V 180 GND DDEXT DDINT 13 DATA21 55 V 97 ADDR19 139 V 181 V DDEXT DDEXT DDINT 14 DATA20 56 ADDR0 98 ADDR20 140 GND 182 GND 15 V 57 ADDR2 99 ADDR21 141 V 183 DPI_P14 (TIMER1) DDEXT DDINT 16 GND 58 ADDR1 100 ADDR23 142 GND 184 DPI_P13 (TIMER0) 17 DATA19 59 ADDR4 101 ADDR22 143 DAI_P11 (SD3A) 185 DPI_P12 (TWI_CLK) 18 DATA18 60 ADDR3 102 MS1 144 DAI_P10 (SD2B) 186 DPI_P11 (TWI_DATA) 19 V 61 ADDR5 103 MS0 145 DAI_P08 (SFS1) 187 DPI_P10 (UART0RX) DDINT 20 GND 62 GND 104 V 146 DAI_P09 (SD2A) 188 DPI_P09 (UART0TX) DDINT 21 DATA17 63 V 105 V 147 DAI_P06 (SD1B) 189 DPI_P08 (SPIFLG3) DDINT DDINT 22 V 64 GND 106 GND 148 DAI_P07 (SCLK1) 190 DPI_P07 (SPIFLG2) DDINT 23 GND 65 V 107 V 149 DAI_P05 (SD1A) 191 V DDEXT DDEXT DDEXT 24 V 66 ADDR6 108 SDCAS 150 V 192 GND DDINT DDEXT 25 GND 67 ADDR7 109 SDRAS 151 GND 193 V DDINT 26 DATA16 68 ADDR8 110 SDCKE 152 V 194 GND DDINT 27 DATA15 69 ADDR9 111 SDWE 153 GND 195 DPI_P06 (SPIFLG1) 28 DATA14 70 ADDR10 112 WR 154 V 196 DPI_P05 (SPIFLG0) DDINT 29 DATA13 71 GND 113 SDA10 155 GND 197 DPI_P04 (SPIDS) 30 DATA12 72 V 114 GND 156 V 198 DPI_P03 (SPICLK) DDINT DDINT 31 V 73 GND 115 V 157 V 199 DPI_P01 (SPIMOSI) DDEXT DDEXT DDINT 32 GND 74 V 116 SDCLK0 158 V 200 DPI_P02 (SPIMISO) DDEXT DDINT 33 V 75 ADDR11 117 GND 159 GND 201 RESETOUT DDINT 34 GND 76 ADDR12 118 V 160 V 202 RESET DDINT DDINT 35 DATA11 77 ADDR13 119 RD 161 V 203 V DDINT DDEXT 36 DATA10 78 GND 120 ACK 162 V 204 GND DDINT 37 DATA9 79 V 121 FLAG3 163 TDI 205 DATA30 DDINT 38 DATA8 80 A 122 FLAG2 164 TRST 206 DATA31 VSS 39 DATA7 81 A 123 FLAG1 165 TCK 207 DATA29 VDD Rev. H | Page 56 of 60 | March 2019

ADSP-21369 Table 45. 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number) (Continued) Lead Lead Lead Lead Lead No. Signal No. Signal No. Signal No. Signal No. Signal 40 DATA6 82 GND 124 FLAG0 166 GND 208 V DDINT 41 V 83 CLKIN 125 DAI_P20 (SFS5) 167 V DDEXT DDINT 42 GND 84 XTAL 126 GND 168 TMS Rev. H | Page 57 of 60 | March 2019

ADSP-21369 PACKAGE DIMENSIONS The ADSP-21369 processor is available in 256-ball RoHS com- pliant and leaded BGA_ED, and 208-lead RoHS compliant LQFP_EP packages. 30.20 30.00 SQ 25.50 29.80 28.10 REF 0.75 1.60 MAX 28.00 SQ 8R.7E1F2 0.60 27.90 0.45 208 157 157 208 1.00 REF 1 156 156 1 SEATING PIN 1 PLANE TOP VIEW 8.890 (PINS DOWN) EXPOSED REF PAD 1.45 0.20 1.40 0.15 1.35 0.09 0.15 7° 00..1005 0.08 30.5°° BOT(PTINOSM U VP)IEW COPLANARITY 52 105 105 52 53 104 104 53 VIEW A 0.27 ROTATED 90° CCW VIEW A 0.50 0.22 BSC 0.17 LEAD PITCH A COMPLIANT TO JEDEC STANDARDS MS-026-BJB-HD 100907 NOTE: THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND THERMALLY CONNECTED TO VSS. THIS SHOULD BE IMPLEMENTED BY SOLDERING THE EXPOSED PAD TO A VSS PCB LAND THAT IS THE SAME SIZE AS THE EXPOSED PAD. THE VSS PCB LAND SHOULD BE ROBUSTLY CONNECTED TO THE VSS PLANE IN THE PCB WITH AN ARRAY OF THERMAL VIAS FOR BEST PERFORMANCE. Figure 50. 208-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] (SW-208-1) Dimensions shown in millimeters Rev. H | Page 58 of 60 | March 2019

ADSP-21369 27.10 A1 BALL 27.00 SQ A1 BALL PAD CORNER 26.90 PAD CORNER 20191817161514131211109 8 7 6 5 4 3 2 1 A B C D E F G H 21.00 REF 24.13 REF J SQ SQ LK M N 1.27 P BSC R T U V W Y TOP VIEW 1.44 REF BOTTOM VIEW 2.84 19.00 DETAIL A 1.30 REF 0.75 2.65 SIDE VIEW 0.65 2.46 0.59 REF 0.55 DETAIL A 0.91 SEPALTAINNGE 0.76 C0.O20P LANARITY 0.61 BALL DIAMETER Figure 51. 256-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] (BP-256-2) Dimension shown in millimeters SURFACE-MOUNT DESIGN Table46 is provided as an aide to PCB design. For industry- standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Table 46. BGA_ED Data for Use with Surface-Mount Design Package Ball Attach Type Solder Mask Opening Ball Pad Size 256-Lead Ball Grid Array BGA_ED Solder Mask Defined (SMD) 0.63 mm 0.73 mm (BP-256-2) Rev. H | Page 59 of 60 | March 2019

ADSP-21369 ORDERING GUIDE Temperature Instruction On-Chip Package Model Notes Range1 Rate SRAM ROM Package Description Option ADSP-21369KBPZ-2A 2 0°C to +70°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256-2 ADSP-21369BBPZ-2A 2 –40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256-2 ADSP-21369KBPZ-3A 2 0°C to +70°C 400 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256-2 ADSP-21369KSWZ-1A 2 0°C to +70°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 ADSP-21369KSWZ-2A 2 0°C to +70°C 333 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 ADSP-21369KSWZ-4A 2 0°C to +70°C 350 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 ADSP-21369KSWZ-5A 2 0°C to +70°C 366 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 ADSP-21369KSWZ-6A 2 0°C to +70°C 400 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 ADSP-21369BSWZ-1A 2 –40°C to +85°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 ADSP-21369BSWZ-2A 2 –40°C to +85°C 333 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 1Referenced temperature is ambient temperature. 2Z = RoHS Compliant Part. ©2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05267-0-3/19(H) Rev. H | Page 60 of 60 | March 2019