SHARC Digital Signal Processor ADSP-21160M/ADSP-21160N SUMMARY FEATURES High performance 32-bit DSP—applications in audio, medi- 100 MHz (10 ns) core instruction rate (ADSP-21160N) cal, military, graphics, imaging, and communication Single-cycle instruction execution, including SIMD opera- Super Harvard architecture—4 independent buses for dual tions in both computational units data fetch, instruction fetch, and nonintrusive, zero-over- Dual data address generators (DAGs) with modulo and bit- head I/O reverse addressing Backward compatible—assembly source level compatible Zero-overhead looping and single-cycle loop setup, provid- with code for ADSP-2106x DSPs ing efficient program sequencing Single-instruction, multiple-data (SIMD) computational IEEE 1149.1 JTAG standard Test Access Port and on-chip architecture—two 32-bit IEEE floating-point computation emulation units, each with a multiplier, ALU, shifter, and register file 400-ball 27 mm ×27mm PBGA package Integrated peripherals—integrated I/O processor, 4Mbits Available in lead-free (RoHS compliant) package on-chip dual-ported SRAM, glueless multiprocessing fea- 200 million fixed-point MACs sustained performance tures, and ports (serial, link, external bus, and JTAG) (ADSP-21160N) COREPROCESSOR DUAL-PORTEDSRAM TIMER IN3S2CTxRAU4C8CH-BTEIIOTN DUTAWLO-PIONRDTEEPDENBDLOENCTKS 0CKO 1K TEJSTTAAGND 6 PROCESSORPORT I/OPORT LB OC EMULATION ADDR DATA DATA ADDR L B ADDR DATA DATA ADDR DAG1 DAG2 PROGRAM 8x4x32 8x4x32 SEQUENCER EXTERNAL IOD IOA PORT PMADDRESSBUS 32 64 18 32 ADDRBUS DMADDRESSBUS 32 MUX MULTIPROCESSOR INTERFACE PMDATABUS 16/32/40/48/64 BUS DATABUS 64 CONNECT DMDATABUS 32/40/64 MUX (PX) HOSTPORT DATA DATA REGISTER REGISTER FILE FILE MULT 16(xP4E0X-)BIT SBHAIRFRTEERL SBHAIRFRTEERL 16(xPE40Y-)BIT MULT REGIIOSTPERS CONTDRMOALLER 46 (MEMORY MAPPED) SERIALPORTS (2) 6 CONTROL, STATUSAND LINKPORTS 60 ALU ALU DATABUFFERS (6) I/OPROCESSOR Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADSP-21160M/ADSP-21160N Single-instruction, multiple-data (SIMD) architectureprovides Two computational processing elements Concurrent execution—each processing element executes the same instruction, but operates on different data Code compatibility—at assembly level, uses the same instruction set as the ADSP-2106x SHARCDSPs Parallelism in buses and computational units allows Single-cycle execution (with or without SIMD) of a multiply operation, an ALU operation, a dual memory read or write, and an instruction fetch Transfers between memory and core at up to four 32-bit floating- or fixed-point words per cycle Accelerated FFT butterfly computation through a multiply with add and subtract Memory attributes 4M bits on-chip dual-ported SRAM for independent access by core processor, host, and DMA 4G word address range for off-chip memory Memory interface supports programmable wait state gen- eration and page-mode for off-chip memory DMA controller supports 14 zero-overhead DMA channels for transfers between ADSP-21160x internal memory and external memory, external peripherals, host processor, serial ports, or link ports 64-bit background DMA transfers at core clock speed, in parallel with full-speed processor execution Host processor interface to 16- and 32-bit microprocessors Multiprocessing support provides Glueless connection for scalable DSP multiprocessing architecture Distributed on-chip bus arbitration for parallel bus con- nect of up to 6 ADSP-21160x processors plus host 6 link ports for point-to-point connectivity and array multiprocessing Serial ports provide Two synchronous serial ports with companding hardware Independent transmit and receive functions TDM support for T1 and E1 interfaces 64-bit-wide synchronous external port provides Glueless connection to asynchronous and SBSRAM exter- nal memories Rev. D | Page 2 of 58 | September 2015

ADSP-21160M/ADSP-21160N TABLE OF CONTENTS General Description ................................................. 4 ESD Sensitivity ................................................... 19 ADSP-21160x Family Core Architecture .................... 4 Package Information ............................................ 19 Memory and I/O Interface Features ........................... 7 Timing Specifications ........................................... 20 Development Tools ............................................... 9 Output Drive Currents—ADSP-21160M ................... 47 Additional Information ......................................... 10 Output Drive Currents—ADSP-21160N ................... 47 Related Signal Chains ........................................... 10 Power Dissipation ............................................... 47 Pin Function Descriptions ........................................ 11 Test Conditions .................................................. 48 Specifications ......................................................... 15 Environmental Conditions .................................... 51 Operating Conditions—ADSP-21160M .................... 15 400-Ball PBGA Pin Configurations ............................. 52 Electrical Characteristics—ADSP-21160M ................. 16 Outline Dimensions ................................................ 57 Operating Conditions—ADSP-21160N ..................... 17 Surface-Mount Design ............................................. 57 Electrical Characteristics—ADSP-21160N ................. 18 Ordering Guide ..................................................... 58 Absolute Maximum Ratings ................................... 19 REVISION HISTORY 9/15—Rev. C to Rev. D Removed model ADSP-21160NKB-100 (no longer available) from Ordering Guide ............................................... 58 Rev. D | Page 3 of 58 | September 2015

ADSP-21160M/ADSP-21160N GENERAL DESCRIPTION The ADSP-21160x SHARC® DSP family has two members: Table 2. ADSP-21160x Benchmarks ADSP-21160M and ADSP-21160N. The ADSP-21160M is fabri- cated in a 0.25 micron CMOS process. The ADSP-21160N is ADSP-21160M ADSP-21160N fabricated in a 0.18 micron CMOS process. The ADSP-21160N Benchmark Algorithm 80 MHz 100 MHz offers higher performance and lower power consumption than 1024 Point Complex FFT 115 μs 92 μs the ADSP-21160M. Easing portability, the ADSP-21160x is (Radix 4, with reversal) application source code compatible with first generation FIR Filter (per tap) 6.25 ns 5 ns ADSP-2106x SHARC DSPs in SISD (single instruction, single IIR Filter (per biquad) 25 ns 20 ns data) mode. To take advantage of the processor’s SIMD (single- Matrix Multiply (pipelined) instruction, multiple-data) capability, some code changes are [33]  [31] 56.25 ns 45 ns needed. Like other SHARC DSPs, the ADSP-21160x is a 32-bit processor that is optimized for high performance DSP applica- [44]  [41] 100 ns 80 ns tions. The ADSP-21160x includes a core running up to Divide (y/x) 37.5 ns 30 ns 100 MHz, a dual-ported on-chip SRAM, an integrated I/O pro- Inverse Square Root 56.25 ns 45 ns cessor with multiprocessing support, and multiple internal DMA Transfer Rate 560M bytes/s 800M bytes/s buses to eliminate I/O bottlenecks. Table1 shows major differences between the ADSP-21160M The functional block diagram (Figure1 on Page1) of the and ADSP-21160N processors. ADSP-21160x illustrates the following architectural features: • Two processing elements, each made up of an ALU, multi- Table 1. ADSP-21160x SHARC Processor Family Features plier, shifter, and data register file Feature ADSP-21160M ADSP-21160N • Data address generators (DAG1, DAG2) SRAM 4 Mbits 4 Mbits • Program sequencer with instruction cache Operating Voltage 3.3 V I/O 3.3 V I/O • PM and DM buses capable of supporting four 32-bit data 2.5 V Core 1.9 V Core transfers between memory and the core every core proces- Instruction Rate 80 MHz 100 MHz sor cycle Link Port Transfer Rate (6) 80 MBytes/s 100 MBytes/s • Interval timer Serial Port Transfer Rate (2) 40 Mbits/s 50 Mbits/s • On-chip SRAM (4M bits) The ADSP-21160x introduces single-instruction, multiple-data • External port that supports: (SIMD) processing. Using two computational units • Interfacing to off-chip memory peripherals (ADSP-2106x SHARC DSPs have one), the ADSP-21160x can • Glueless multiprocessing support for six double performance versus the ADSP-2106x on a range of DSP ADSP-21160x SHARC DSPs algorithms. • Host port Fabricated in a state-of-the-art, high speed, low power CMOS process, the ADSP-21160N has a 10ns instruction cycle time. • DMA controller With its SIMD computational hardware running at 100MHz, • Serial ports and link ports the ADSP-21160N can perform 600 million math operations • JTAG test access port per second (480 million operations for ADSP-21160M at a 12.5ns instruction cycle time). Figure2 shows a typical single-processor system. A multipro- cessing system appears in Figure3 on Page6. Table2 shows performance benchmarks for the ADSP-21160x. These benchmarks provide single-channel extrapolations of ADSP-21160X FAMILY CORE ARCHITECTURE measured dual-channel (SIMD) processing performance. For The ADSP-21160x processor includes the following architec- more information on benchmarking and optimizing DSP code tural features of the ADSP-2116x family core. The for single- and dual-channel processing, see the Analog Devices ADSP-21160x is code compatible at the assembly level with the website (www.analog.com). ADSP-2106x andADSP-21161. The ADSP-21160x continues the SHARC family’s industry- SIMD Computational Engine leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system The ADSP-21160x contains two computational processing ele- features. These features include a 4M-bit dual-ported SRAM ments that operate as a single-instruction multiple-data (SIMD) memory, host processor interface, I/O processor that supports engine. The processing elements are referred to as PEX and 14 DMA channels, two serial ports, six link ports, external par- PEY, and each contains an ALU, multiplier, shifter, and register allel bus, and glueless multiprocessing. file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is Rev. D | Page 4 of 58 | September 2015

ADSP-21160M/ADSP-21160N Data Register File ADSP-21160X A general-purpose data register file is contained in each pro- CLOCK CLKIN BMS CS cessing element. The register files transfer data between the BOOT 4 CLK_CFG3–0 CIF ADDR EPROM computation units and the data buses, and store intermediate EBOOT (OPTIONAL) results. These 10-port, 32-register (16 primary, 16 secondary) DATA LBOOT BRST register files, combined with the ADSP-2116x enhanced 3 IRQ2–0 Harvard architecture, allow unconstrained data flow between 4 ADDR31–0 ADDR FLAG3–0 computation units and internal memory. The registers in PEX TIMEXP DATA63–0 DATA MEMORY/ are referred to as R0–R15 and in PEY asS0–S15. LINK RDx OE MAPPED DEVICES LXCLK WRx WE DEVICES Single-Cycle Fetch of Instruction and Four Operands (6MAX) LXACK ACK ACK (OPTIONAL) The processor features an enhanced Harvard architecture in (OPTIONAL) LXDAT7–0 MS3–0 CS which the data memory (DM) bus transfers data, and the pro- (ODSPEETIRVOIICANELAL) TTRRCFCSSLFL0K0K00 PSABGTES CONTROL DARESSD DATA DATAD(OMPATDIOENVAICLE) g(DsreSaePm ’tsh m see efpmuanrocarttyieo (pnPraMol gb)r lbaomucks atdrniadang dsrfaaetmras m1b)oe. tmWh oiinrthys t btrhuuecs etAiso DannSsd Pa -no2dn1 -1dc6ah0tiaxp DT0 CLKOUT instruction cache, the processor can simultaneously fetch four DR0 DMAR1–2 operands and an instruction (from the cache), all in a single TCLK1 DMAG1–2 cycle. SERIAL RCLK1 CS DEVICE TFS1 HBR HOST Instruction Cache RSF1 PROCESSOR (OPTIONAL) DT1 HBG INTERFACE The ADSP-21160x includes an on-chip instruction cache that DR1 REDY (OPTIONAL) enables three-bus operation for fetching an instruction and four RPBA BR1–6 ADDR data values. The cache is selective—only the instructions whose ID2–0 PA fetches conflict with PM bus data accesses are cached. This DATA cache allows full-speed execution of core, providing looped RESET JTAG operations, such as digital filter multiply- accumulates and FFT 6 butterfly processing. Data Address Generators with Hardware CircularBuffers Figure 2. Single-Processor System The ADSP-21160x DSP’s two data address generators (DAGs) are used for indirect addressing and provide for implementing enabled, the same instruction is executed in both processing ele- circular data buffers in hardware. Circular buffers allow efficient ments, but each processing element operates on different data. programming of delay lines and other data structures required This architecture is efficient at executing math-intensive DSP in digital signal processing, and are commonly used in digital algorithms. filters and Fourier transforms. The two DAGs of the product Entering SIMD mode also has an effect on the way data is trans- contain sufficient registers to allow the creation of up to 32 cir- ferred between memory and the processing elements. In SIMD cular buffers (16 primary register sets, 16 secondary). The DAGs mode, twice the data bandwidth is required to sustain computa- automatically handle address pointer wraparound, reducing tional operation in the processing elements. Because of this overhead, increasing performance, and simplifying implemen- requirement, entering SIMD mode also doubles the bandwidth tation. Circular buffers can start and end at any memory between memory and the processing elements. When using the location. DAGs to transfer data in SIMD mode, two data values are trans- ferred with each access of memory or the register file. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel Independent, Parallel Computation Units operations for concise programming. For example, the proces- Within each processing element is a set of computational units. sor can conditionally execute a multiply, an add, and subtract, The computational units consist of an arithmetic/logic unit in both processing elements, while branching, allin a single (ALU), multiplier, and shifter. These units perform single-cycle instruction. instructions. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit single-precision float- ing-point, 40-bit extended-precision floating-point, and 32-bit fixed-point data formats. Rev. D | Page 5 of 58 | September 2015

ADSP-21160M/ADSP-21160N ADSP-21160X#6 ADSP-21160X#5 ADSP-21160X#4 L S ADSP-21160X#3 CONTRO DDRAES DATA CLKIN ADDR31–0 DATA63–0 RESET RPBA 3 ID2–0 CONTROL 011 PA BR1–2,BR4–6 5 BR3 ADSP-21160X#2 CLKIN ADDR31–0 RESET DATA63–0 RPBA 3 ID2–0 CONTROL 010 PA 5 BR1,BR3–6 BR2 L S ADSP-21160X#1 ONTRO DSDRE TADA C A CLKIN ADDR31–0 ADDR RESET DATA63–0 DATA GLOBALMEMORY AND RPBA RDx OE PERIPHERALS WRx WE (OPTIONAL) 3 ACK ACK ID2–0 OL MS3–0 CS R T N 001 CO BMS CS PAGE ADDR BOOTEPROM(OPTIONAL) SBTS DATA BUS PRIORITY CS HBR RESET HBG HOSTPROCESSOR CLOCK REDY INTERFACE(OPTIONAL) ADDR PA BR2–6 5 DATA BR1 Figure 3. Shared Memory Multiprocessing System Rev. D | Page 6 of 58 | September 2015

ADSP-21160M/ADSP-21160N MEMORY AND I/O INTERFACE FEATURES IOP Reg’s 0x00 0000 0x80 0000 Augmenting the ADSP-2116x family core, the ADSP-21160x Internal Long Word 0x02 0000 adds the following architectural features. Memory Normal Word 0x04 0000 Bank 0 MS0 Space Dual-Ported On-Chip Memory 0x08 0000 Short Word The ADSP-21160x contains four megabits of on-chip SRAM, Internal 0x10 0000 organized as two blocks of 2Mbits each, which can be config- Memory ured for different combinations of code and data storage Space Bank 1 MS1 (Figure4). Each memory block is dual-ported for single-cycle, (ID=001) independent accesses by the core processor and I/O processor. 0x20 0000 Internal The dual-ported memory in combination with three separate Memory on-chip buses allows two data transfers from the core and one Space Bank 2 MS2 from I/O processor, in a single cycle. The ADSP-21160x mem- (ID=010) ory can be configured as a maximum of 128K words of 0x30 0000 32-bit data, 256K words of 16-bit data, 85K words of 48-bit Internal instructions (or 40-bit data), or combinations of different word MSepmacoery Bank 3 MS3 sizes up to four megabits. All of the memory can be accessed as (ID=011) 16-, 32-, 48-, or 64-bit words. A 16-bit floating-point storage 0x40 0000 format is supported that effectively doubles the amount of data Multiprocessor Internal that may be stored on-chip. Conversion between the 32-bit Memory Memory Space External floating-point and 16-bit floating-point formats is done in a sin- Space Memory gle instruction. While each memory block can store (ID=100) Space 0x50 0000 combinations of code and data, accesses are most efficient when Internal one block stores data, using the DM bus for transfers, and the Memory other block stores instructions and data, using the PM bus for Space transfers. Using the DM bus and PM bus in this way, with one (ID=101) Nonbanked dedicated to each memory block, assures single-cycle execution Internal 0x60 0000 with two data transfers. In this case, the instruction must be Memory available in thecache. Space (ID=110) Off-Chip Memory and Peripherals Interface Broadcast 0x70 0000 The ADSP-21160x DSP’s external port provides the processor’s Write to interface to off-chip memory and peripherals. The 4Gword off- All DSPs (ID=111) chip address space is included in the processor’s unified address 0x7F FFFF 0xFFFF FFFF space. The separate on-chip buses—for PM addresses, PM data, DM addresses, DM data, I/O addresses, and I/O data—are mul- Figure 4. Memory Map tiplexed at the external port to create an external system bus with a single 32-bit address bus and a single 64-bit data bus. The DMA Controller lower 32 bits of the external data bus connect to even addresses, The ADSP-21160x DSP’s on-chip DMA controller allows zero- and the upper 32 bits of the 64 connect to odd addresses. Every overhead data transfers without processor intervention. The access to external memory is based on an address that fetches a DMA controller operates independently and invisibly to the 32-bit word, and with the 64-bit bus, two address locations can processor core, allowing DMA operations to occur while the be accessed at once. When fetching an instruction from external core is simultaneously executing its program instructions. DMA memory, two 32-bit data locations are being accessed (16 bits transfers can occur between the processor’s internal memory are unused). Figure5 shows the alignment of various accesses to and external memory, external peripherals, or a host processor. externalmemory. DMA transfers can also occur between the product’s DSP’s The external port supports asynchronous, synchronous, and internal memory and its serial ports or link ports. External bus synchronous burst accesses. ZBT synchronous burst SRAM can packing to 16-, 32-, 48-, or 64-bit words is performed during be interfaced gluelessly. Addressing of external memory devices DMA transfers. Fourteen channels of DMA are available on the is facilitated by on-chip decoding of high-order address lines to ADSP-21160x—six via the link ports, four via the serial ports, generate memory bank select signals. Separate control lines are and four via the processor’s external port (for either host pro- also generated for simplified addressing of page-mode DRAM. cessor, other ADSP-21160x processors, memory or I/O The ADSP-21160x provides programmable memory wait states transfers). Programs can be downloaded to the processor using and external memory acknowledge controls to allow interfacing DMA transfers. Asynchronous off-chip peripherals can control to DRAM and peripherals with variable access, hold, and disable two DMA channels using DMA Request/Grant lines time requirements. (DMAR1–2, DMAG1–2). Other DMA features include Rev. D | Page 7 of 58 | September 2015

ADSP-21160M/ADSP-21160N (ADSP-21160N). Link port I/O is especially useful for point-to- point interprocessor communication in multiprocessing sys- DATA63–0 tems. The link ports can operate independently and 63 55 47 39 31 23 15 7 0 simultaneously. Link port data is packed into 48- or 32-bit words, and can be directly read by the core processor or DMA- BYTE7 BYTE0 transferred to on-chip memory. Each link port has its own dou- RDH/WRH RDL/WRL ble-buffered input and output registers. Clock/acknowledge handshaking controls link port transfers. Transfers are pro- 64-BITLONGWORD,SIMD,DMA,IOPREGISTERTRANSFERS grammable as transmit orreceive. 64-BITTRANSFERFOR48-BITINSTRUCTIONFETCH Serial Ports 64-BITTRANS.FOR40-BITEXT.PRECISION The processor features two synchronous serial ports that pro- vide an inexpensive interface to a wide variety of digital and 32-BITNORMALWD.(EVENADDR.) mixed-signal peripheral devices. The serial ports can operate up 32-BITNORMALWORD(ODDADDR) to half the clock rate of the core, providing each with a maxi- mum data rate of 50M bits/s (ADSP-21160N). Independent RESTRICTEDDMA,HOST,EPROMDATAALIGNMENTS: transmit and receive functions provide greater flexibility for 32-BITPACKED serial communications. Serial port data can be automatically transferred to and from on-chip memory via a dedicated DMA. 16-BITPACKED Each of the serial ports offers a TDM multichannel mode. The serial ports can operate with little-endian or big-endian trans- EPROM mission formats, with word lengths selectable from 3 bits to 32 bits. They offer selectable synchronization and transmit modes Figure 5. External Data Alignment Options as well as optional μ-law or A-law companding. Serial port clocks and frame syncs can be generated internally or externally. interrupt generation upon completion of DMA transfers, two- dimensional DMA, and DMA chaining for automatic linked Host Processor Interface DMA transfers. The ADSP-21160x host interface allows easy connection to Multiprocessing standard microprocessor buses, both 16- and 32-bit, with little additional hardware required. The host interface is accessed The ADSP-21160x offers powerful features tailored to multipro- through the ADSP-21160x DSP’s external port and is memory- cessing DSP systems as shown in M. The external port and link mapped into the unified address space. Four channels of DMA ports provide integrated glueless multiprocessing support. are available for the host interface; code and data transfers are The external port supports a unified address space (see Figure4) accomplished with low software overhead. The host processor that allows direct interprocessor accesses of each processor’s communicates with the ADSP-21160x DSP’s external bus with internal memory. Distributed bus arbitration logic is included host bus request (HBR), host bus grant (HBG), ready (REDY), on-chip for simple, glueless connection of systems containing acknowledge (ACK), and chip select (CS) signals. The host can up to six ADSP-21160x processors and a host processor. Master directly read and write the internal memory of the processor, processor changeover incurs only one cycle of overhead. Bus and can access the DMA channel setup and mailbox registers. arbitration is selectable as either fixed or rotating priority. Bus Vector interrupt support provides efficient execution of host lock allows indivisible read-modify-write sequences for sema- commands. phores. A vector interrupt is provided for interprocessor The host processor interface can be used in either multiproces- commands. Maximum throughput for interprocessor data sor or uniprocessor systems. For multiprocessor systems, host transfer is 400M bytes/s (ADSP-21160N) over the external port. access to the SHARC requires that address pins ADDR17, Broadcast writes allow simultaneous transmission of data to all ADDR18, ADDR19, and ADDR20 be driven low. It is not ADSP-21160x DSPs and can be used to implement reflective enough to tie these pins to ground through a resistor (for exam- semaphores. ple, 10 k). These pins must be driven low with a strong enough Six link ports provide for a second method of multiprocessing drive strength (10  to 50 ) to overcome the SHARC keeper communications. Each link port can support communications latches present on these pins. If the drive strength provided is to another ADSP-21160x. Using the links, a large multiproces- not strong enough, data access failures can occur. sor system can be constructed in a 2D or 3D fashion. Systems For uniprocessor SHARC systems using this host access feature, can use the link ports and cluster multiprocessing concurrently address pins ADDR17, ADDR18, ADDR19, and ADDR20 may or independently. be tied low (for example, through a 10 k ohm resistor), driven low by a buffer/driver, or left floating. Any of these options is Link Ports sufficient. The processor features six 8-bit link ports that provide addi- tional I/O capabilities. With the capability of running at 100MHz rates, each link port can support 100M bytes/s Rev. D | Page 8 of 58 | September 2015

ADSP-21160M/ADSP-21160N Program Booting seamlessly integrates available software add-ins to support real time operating systems, file systems, TCP/IP stacks, USB stacks, The internal memory of the ADSP-21160x can be booted at sys- algorithmic software modules, and evaluation hardware board tem power-up from an 8-bit EPROM, a host processor, or support packages. For more information visit through one of the link ports. Selection of the boot source is www.analog.com/cces. controlled by the BMS (Boot Memory Select), EBOOT (EPROM Boot), and LBOOT (Link/Host Boot) pins. 32-bit and 16-bit The other Analog Devices IDE, VisualDSP++, supports proces- host processors can be used forbooting. sor families introduced prior to the release of CrossCore Embedded Studio. This IDE includes the Analog Devices VDK Phase-Locked Loop real time operating system and an open source TCP/IP stack. The processor uses an on-chip PLL to generate the internal For more information visit www.analog.com/visualdsp. Note clock for the core. Ratios of 2:1, 3:1, and 4:1 between the core that VisualDSP++ will not support future Analog Devices and CLKIN are supported. The CLK_CFG pins are used to processors. select the ratio. The CLKIN rate is the rate at which the synchro- EZ-KIT Lite Evaluation Board nous external portoperates. For processor evaluation, Analog Devices provides wide range Power Supplies of EZ-KIT Lite® evaluation boards. Including the processor and The processor has separate power supply connections for the key peripherals, the evaluation board also supports on-chip internal (V ), external (V ), and analog (AV and emulation capabilities and other evaluation and development DDINT DDEXT DD AGND) power supplies. The internal and analog supplies must features. Also available are various EZ-Extenders®, which are meet the V and AV requirement. The external supply daughter cards delivering additional specialized functionality, DDINT DD must meet the 3.3V requirement. All external supply pins must including audio and video processing. For more information be connected to the same supply. visit www.analog.com and search on “ezkit” or “ezextender”. The PLL filter, Figure6, must be added for each ADSP-21160x EZ-KIT Lite Evaluation Kits in the system. V is the digital core supply. It is recom- DDINT For a cost-effective way to learn more about developing with mended that the capacitors be connected directly to AGND Analog Devices processors, Analog Devices offer a range of EZ- using short thick trace. It is recommended that the capacitors be KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT placed as close to AV and AGND as possible. The connection DD Lite evaluation board, directions for downloading an evaluation from AGND to the (digital) ground plane should be made after version of the available IDE(s), a USB cable, and a power supply. the capacitors. The use of a thick trace for AGND is reasonable The USB controller on the EZ-KIT Lite board connects to the only because the PLL is a relatively low power circuit—it does USB port of the user’s PC, enabling the chosen IDE evaluation not apply to any other ADSP-21160x GND connection. suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also supports in-circuit programming of the on-board Flash device to store user-specific boot code, 10(cid:2) VDDINT AVDD enabling standalone operation. With the full version of Cross- 0.1(cid:3)F 0.01(cid:3)F Core Embedded Studio or VisualDSP++ installed (sold separately), engineers can develop software for supported EZ- KITs or any custom system utilizing supported Analog Devices AGND processors. Software Add-Ins for CrossCore Embedded Studio Figure 6. Analog Power (AV ) Filter Circuit DD Analog Devices offers software add-ins which seamlessly inte- DEVELOPMENT TOOLS grate with CrossCore Embedded Studio to extend its capabilities and reduce development time. Add-ins include board support Analog Devices supports its processors with a complete line of packages for evaluation hardware, various middleware pack- software and hardware development tools, including integrated development environments (which include CrossCore® Embed- ages, and algorithmic modules. Documentation, help, ded Studio and/or VisualDSP++®), evaluation products, configuration dialogs, and coding examples present in these add-ins are viewable through the CrossCore Embedded Studio emulators, and a wide variety of software add-ins. IDE once the add-in is installed. Integrated Development Environments (IDEs) Board Support Packages for Evaluation Hardware For C/C++ software writing and editing, code generation, and Software support for the EZ-KIT Lite evaluation boards and EZ- debug support, Analog Devices offers two IDEs. Extender daughter cards is provided by software add-ins called The newest IDE, CrossCore Embedded Studio, is based on the Board Support Packages (BSPs). The BSPs contain the required EclipseTM framework. Supporting most Analog Devices proces- drivers, pertinent release notes, and select example code for the sor families, it is the IDE of choice for future processors, given evaluation hardware. A download link for a specific BSP is including multicore devices. CrossCore Embedded Studio Rev. D | Page 9 of 58 | September 2015

ADSP-21160M/ADSP-21160N located on the web page for the associated EZ-KIT or EZ- Signal chains are often used in signal processing applications to Extender product. The link is found in the Product Download gather and process data or to apply system controls based on area of the product web page. analysis of real-time phenomena. Middleware Packages Analog Devices eases signal processing system development by providing signal processing components that are designed to Analog Devices separately offers middleware add-ins such as work together well. A tool for viewing relationships between real time operating systems, file systems, USB stacks, and specific applications and related components is available on the TCP/IP stacks. For more information, see the following web www.analog.com website. pages: The application signal chains page in the Circuits from the Lab® • www.analog.com/ucos3 site (http:\\www.analog.com\circuits) provides: • www.analog.com/ucfs • Graphical circuit block diagram presentation of signal • www.analog.com/ucusbd chains for a variety of circuit types and applications • www.analog.com/lwip • Drill down links for components in each chain to selection guides and application information Algorithmic Modules • Reference designs applying best practice design techniques To speed development, Analog Devices offers add-ins that per- form popular audio and video processing algorithms. These are available for use with both CrossCore Embedded Studio and VisualDSP++. For more information visit www.analog.com and search on “Blackfin software modules” or “SHARC software modules”. Designing an Emulator-Compatible DSP Board(Target) For embedded system test and debug, Analog Devices provides a family of emulators. On each JTAG DSP, Analog Devices sup- plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit emulation is facilitated by use of this JTAG interface. The emu- lator accesses the processor’s internal features via the processor’s TAP, allowing the developer to load code, set break- points, and view variables, memory, and registers. The processor must be halted to send data and commands, but once an operation is completed by the emulator, the DSP system is set to run at full speed with no impact on system timing. The emu- lators require the target board to include a header that supports connection of the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal ter- mination, and emulator pod logic, see the application note (EE-68) “Analog Devices JTAG Emulation Technical Refer- ence” (www.analog.com/ee-68). This document is updated regularly to keep pace withimprovements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21160x architecture and functionality. For detailed infor- mation on the Blackfin family core architecture and instruction set, refer to the ADSP-21160 SHARC DSP Hardware Reference and the ADSP-21160 SHARC DSP Instruction Set Reference. For detailed information on the development tools for this proces- sor, see the VisualDSP++ User’s Guide. RELATED SIGNAL CHAINS A signal chain is a series of signal conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Rev. D | Page 10 of 58 | September 2015

ADSP-21160M/ADSP-21160N PIN FUNCTION DESCRIPTIONS ADSP-21160x pin definitions are listed below. Inputs identified • LxCLK, LxACK, LxDAT7–0 (LxPDRDE = 0) (Note: See as synchronous (S) must meet timing requirements with respect Link Port Buffer Control Register Bit definitions in the to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden- ADSP-21160 SHARC DSP Hardware Reference.) tified as asynchronous (A) can be asserted asynchronously to • DTx, DRx, TCLKx, RCLKx, EMU, TMS, TRST, TDI CLKIN (or to TCK for TRST). (Note: These pins have a pull-up.) Tie or pull unused inputs to V or GND, except for the DD The following symbols appear in the Type column of Table3: following: A=Asynchronous, G=Ground, I=Input, O=Output, • ADDR31–0, DATA63–0, PAGE, BRST, CLKOUT (ID2–0 P=Power Supply, S=Synchronous, (A/D)=Active Drive, = 00x) (Note: These pins have a logic-level hold circuit (O/D)=Open Drain, and T=Three-State (when SBTS is enabled on the ADSP-21160x DSP with ID2–0 = 00x.) asserted, or when the ADSP-21160x is a bus slave). • PA, ACK, MS3–0, RDx, WRx, CIF, DMARx, DMAGx (ID2–0 = 00x) (Note: These pins have a pull-up enabled on the ADSP-21160x with ID2–0 = 00x.) Table 3. Pin Function Descriptions Pin Type Function ADDR31–0 I/O/T External Bus Address. The ADSP-21160x outputs addresses for external memory and peripherals on these pins. In a multiprocessor system, the bus master outputs addresses for read/writes of the internal memory or IOP registers of other ADSP-21160x DSPs. The ADSP-21160x inputs addresses when a host processor or multiprocessing bus master is reading or writing its internal memory or IOP registers. A keeper latch on the DSP’s ADDR31–0 pins maintains the input at the level it was last driven (only enabled on the processor with ID2–0=00x). DATA63–0 I/O/T External Bus Data. The ADSP-21160x inputs and outputs data and instructions on these pins. Pull- up resistors on unused DATA pins are not necessary. A keeper latch on the DSP’s DATA63-0 pins maintains the input at the level it was last driven (only enabled on the processor with ID2–0=00x). MS3–0 O/T Memory Select Lines. These outputs are asserted (low) as chip selects for the corresponding banks of external memory. Memory bank size must be defined in the SYSCON control register. The MS3–0 outputs are decoded memory address lines. In asynchronous access mode, the MS3–0 outputs transition with the other address outputs. In synchronous access modes, the MS3–0 outputs assert with the other address lines; however, they deassert after the first CLKIN cycle in which ACK is sampledasserted. MS3–0 has a 20 k internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0=00x. RDL I/O/T Memory Read Low Strobe. RDL is asserted whenever ADSP-21160x reads from the low word of external memory or from the internal memory of other ADSP-21160x DSPs. External devices, including other ADSP-21160x DSPs, must assert RDL for reading from the low word of processor internal memory. In a multiprocessing system, RDL is driven by the bus master. RDL has a 20 k internal pull-up resistor that is enabled on the processor with ID2–0=00x. RDH I/O/T Memory Read High Strobe. RDH is asserted whenever ADSP-21160x reads from the high word of external memory or from the internal memory of other ADSP-21160x DSPs. External devices, including other ADSP-21160x DSPs, must assert RDH for reading from the high word of ADSP-21160x internal memory. In a multiprocessing system, RDH is driven by the bus master. RDH has a 20 k internal pull-up resistor that is enabled on the processor with ID2–0=00x. WRL I/O/T Memory Write Low Strobe. WRL is asserted when ADSP-21160x writes to the low word of external memory or internal memory of other ADSP-21160x DSPs. External devices must assert WRL for writing to ADSP-21160x DSP’s low word of internal memory. In a multiprocessing system, WRL is driven by the bus master. WRL has a 20 k internal pull-up resistor that is enabled on the processor with ID2–0=00x. WRH I/O/T Memory Write High Strobe. WRH is asserted when ADSP-21160x writes to the high word of external memory or internal memory of other ADSP-21160x DSPs. External devices must assert WRH for writing to ADSP-21160x DSP’s high word of internal memory. In a multiprocessing system, WRH is driven by the bus master. WRH has a 20 k internal pull-up resistor that is enabled on the processor with ID2–0=00x. Rev. D | Page 11 of 58 | September 2015

ADSP-21160M/ADSP-21160N Table 3. Pin Function Descriptions (Continued) Pin Type Function PAGE O/T DRAM Page Boundary. The processor asserts this pin to an external DRAM controller, to signal that an external DRAM page boundary has been crossed. DRAM page size must be defined in the processor’s memory control register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses. In a multiprocessing system, PAGE is output by the bus master. A keeper latch on the DSP’s PAGE pin maintains the output at the level it was last driven (only enabled on the processor with ID2–0 = 00x). BRST I/O/T Sequential Burst Access. BRST is asserted by ADSP-21160x or a host to indicate that data associated with consecutive addresses is being read or written. A slave device samples the initial address and increments an internal address counter after each transfer. The incremented address is not pipelined on the bus. If the burst access is a read from the host to the processor, the processor automatically increments the address as long as BRST is asserted. BRST is asserted after the initial access of a burst transfer. It is asserted for every cycle after that, except for the last data request cycle (denoted by RDx or WRx asserted and BRST negated). A keeper latch on the DSP’s BRST pin maintains the input at the level it was last driven (only enabled on the processor with ID2–0=00x). ACK I/O/S Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The ADSP-21160x deasserts ACK as an output to add wait states to a synchronous access of its internal memory, by a synchronous host or another DSP in a multiprocessor configuration. ACK has a 2 k internal pull-up resistor that is enabled on the processor with ID2–0=00x. SBTS I/S Suspend Bus and Three-State. External devices can assert SBTS (low) to place the external bus address, data, selects, and strobes in a high-impedance state for the following cycle. If the ADSP-21160x attempts to access external memory while SBTS is asserted, the processor will halt and the memory access will not be completed until SBTS is deasserted. SBTS should only be used to recover from host processor and/or ADSP-21160x deadlock or used with a DRAM controller. IRQ2–0 I/A Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be either edge- triggered or level-sensitive. FLAG3–0 I/O/A Flag Pins. Each is configured via control bits as either an input or output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals. TIMEXP O Timer Expired. Asserted for four processor core clock (CCLK) cycles when the timer is enabled and TCOUNT decrements to zero. HBR I/A Host Bus Request. Must be asserted by a host processor to request control of the ADSP-21160x DSP’s external bus. When HBR is asserted in a multiprocessing system, the processor that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the processor places the address, data, select, and strobe lines in a high-impedance state. HBR has priority over all processor bus requests (BR6–1) in a multiprocessing system. HBG I/O Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take control of the external bus. HBG is asserted (held low) by the ADSP-21160x until HBR is released. In a multiprocessing system, HBG is output by the processor bus master and is monitored by all others. After HBR is asserted, and before HBG is given, HBG will float for 1 t CLK (1 CLKIN cycle). To avoid erroneous grants, HBG should be pulled up with a 20 k to 50 k external resistor. CS I/A Chip Select. Asserted by host processor to select the ADSP-21160x, for asynchronous transfer protocol. REDY O (O/D) Host Bus Acknowledge. The ADSP-21160x deasserts REDY (low) to add wait states to an asynchronous host access when CS and HBR inputs are asserted. DMAR1 I/A DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA services. DMAR1 has a 20 k internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0=00x. DMAR2 I/A DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA services. DMAR2 has a 20 k internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0=00x. Rev. D | Page 12 of 58 | September 2015

ADSP-21160M/ADSP-21160N Table 3. Pin Function Descriptions (Continued) Pin Type Function ID2–0 I Multiprocessing ID. Determines which multiprocessing bus request (BR1–BR6) is used by the ADSP-21160x. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and so on. Use ID = 000 or ID = 001 in single-processor systems. These lines are a system configuration selection which should be hardwired or only changed at reset. DMAG1 O/T DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21160x to indicate that the requested DMA starts on the next cycle. Driven by bus master only. DMAG1 has a 20k internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0=00x. DMAG2 O/T DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21160x to indicate that the requested DMA starts on the next cycle. Driven by bus master only. DMAG2 has a 20k internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0=00x. BR6–1 I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-21160x DSPs to arbitrate for bus mastership. An ADSP-21160x only drives its own BRx line (corresponding to the value of its ID2–0 inputs) and monitors all others. In a multiprocessor system with less than six ADSP-21160x DSPs, the unused BRx pins should be pulled high; the processor’s own BRx line must not be pulled high or low because it is an output. RPBA I/S Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configu- ration selection which must be set to the same value on every ADSP-21160x. If the value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on every processor. PA I/O/T Priority Access. Asserting its PA pin allows an ADSP-21160x bus slave to interrupt background DMA transfers and gain access to the external bus. PA is connected to all ADSP-21160x DSPs in the system. If access priority is not required in a system, the PA pin should be left unconnected. PA has a 20 k internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0=00x. DTx O Data Transmit (Serial Ports 0, 1). Each DT pin has a 50k internal pull-upresistor. DRx I Data Receive (Serial Ports 0, 1). Each DR pin has a 50k internal pull-upresistor. TCLKx I/O Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50k internal pull-upresistor. RCLKx I/O Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50k internal pull-upresistor. TFSx I/O Transmit Frame Sync (Serial Ports 0, 1). RFSx I/O Receive Frame Sync (Serial Ports 0, 1). LxDAT7–0 I/O Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50k internal pull-down resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register. LxCLK I/O Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50k internal pull-down resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1register. LxACK I/O Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50k internal pull-down resistor that is enabled or disabled by the LPDRD bit of the LCOMregister. EBOOT I EPROM Boot Select. For a description of how this pin operates, see Table4. This signal is a system configuration selection that should behardwired. LBOOT I Link Boot. For a description of how this pin operates, see Table4. This signal is a system configu- ration selection that should be hardwired. BMS I/O/T Boot Memory Select. Serves as an output or input as selected with the EBOOT and LBOOT pins; see Table4. This input is a system configuration selection that should be hardwired. CLKIN I Local Clock In. CLKIN is the ADSP-21160x clock input. The ADSP-21160x external port cycles at the frequency of CLKIN. The instruction cycle rate is a multiple of the CLKIN frequency; it is program- mable at power-up. CLKIN may not be halted, changed, or operated below the specified frequency. CLK_CFG3–0 I Core/CLKIN Ratio Control. ADSP-21160x core clock (instruction cycle) rate is equal to n x CLKIN where n is user-selectable to 2, 3, or 4, using the CLK_CFG3–0inputs. For clock configuration defini- tions, see the RESET & CLKIN section of the System Design chapter of the ADSP-21160 SHARC DSP Hardware Reference. Rev. D | Page 13 of 58 | September 2015

ADSP-21160M/ADSP-21160N Table 3. Pin Function Descriptions (Continued) Pin Type Function CLKOUT O/T Local Clock Out. CLKOUT is driven at the CLKIN frequency by the processor. This output can be three-stated by setting the COD bit in the SYSCON register. A keeper latch on the DSP’s CLKOUT pin maintains the output at the level it was last driven (only enabled on the processor with ID2-0 = 00x). Do not use CLKOUT in multiprocessing systems; use CLKIN instead. RESET I/A Processor Reset. Resets the ADSP-21160x to a known state and begins execution at the program memory location specified by the hardware reset vector address. The RESET input must be asserted (low) at power-up. TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan. TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20k internal pull-up resistor. TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20k internal pull-up resistor. TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path. TRST I/A Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power- up or held low for proper operation of the ADSP-21160x. TRST has a 20k internal pull-up resistor. EMU O (O/D) Emulation Status. Must be connected to the ADSP-21160x emulator target board connector only. EMU has a 50k internal pull-up resistor. CIF O/T Core Instruction Fetch. Signal is active low when an external instruction fetch is performed. Driven by bus master only. Three-state when host is bus master. CIF has a 20 k internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0=00x. V P Core Power Supply. Nominally 2.5V (ADSP-21160M) or 1.9 V (ADSP-21160N) dc and supplies the DDINT DSP’s core processor V P I/O Power Supply. Nominally 3.3V dc. DDEXT AV P Analog Power Supply. Nominally 2.5 V (ADSP-21160M) or 1.9V (ADSP-21160N) dc and supplies the DD DSP’s internal PLL (clock generator). This pin has the same specifications as V , except that added DDINT filtering circuitry is required. For more information, see Power Supplies on page 9. AGND G Analog Power Supply Return. GND G Power Supply Return. NC Do Not Connect. Reserved pins that must be left open and unconnected. Table 4. Boot Mode Selection EBOOT LBOOT BMS Booting Mode 1 0 Output EPROM (Connect BMS to EPROM chip select.) 0 0 1 (Input) Host Processor 0 1 1 (Input) Link Port 0 0 0 (Input) No Booting. Processor executes from external memory. 0 1 0 (Input) Reserved 1 1 x (Input) Reserved Rev. D | Page 14 of 58 | September 2015

ADSP-21160M/ADSP-21160N SPECIFICATIONS OPERATING CONDITIONS—ADSP-21160M Table5 shows the recommended operating conditions for the ADSP-21160M. Specifications are subject to change without notice. Table 5. Operating Conditions—ADSP-21160M K Grade Parameter Min Max Unit V Internal (Core) Supply Voltage 2.37 2.63 V DDINT AV Analog (PLL) Supply Voltage 2.37 2.63 V DD V External (I/O) Supply Voltage 3.13 3.47 V DDEXT T Case Operating Temperature1 0 85 ºC CASE V High Level Input Voltage,2 @ V =Max 2.2 V +0.5 V IH1 DDEXT DDEXT V High Level Input Voltage,3 @ V =Max 2.3 V +0.5 V IH2 DDEXT DDEXT V Low Level Input Voltage,2, 3 @ V =Min –0.5 +0.8 V IL DDEXT 1See Environmental Conditions on Page51 for information on thermal specifications. 2Applies to input and bidirectional pins: DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, IRQ2–0, FLAG3–0, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, PA, BRST, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, and RCLK1. 3Applies to input pins: CLKIN, RESET, and TRST. Rev. D | Page 15 of 58 | September 2015

ADSP-21160M/ADSP-21160N ELECTRICAL CHARACTERISTICS—ADSP-21160M Table6shows ADSP-21160M electrical characteristics. These specifications are subject to change without notification. Table 6. Electrical Characteristics—ADSP-21160M Parameter Test Conditions Min Max Unit V High Level Output Voltage1 @ V =Min, I =–2.0 mA2 2.4 V OH DDEXT OH V Low Level Output Voltage1 @ V =Min, I =4.0 mA2 0.4 V OL DDEXT OL I High Level Input Current3, 4, 5 @ V =Max, V =V Max 10 μA IH DDEXT IN DD I Low Level Input Current3 @ V =Max, V =0 V 10 μA IL DDEXT IN I Low Level Input Current Pull-Up14 @ V =Max, V =0 V 250 μA ILPU1 DDEXT IN I Low Level Input Current Pull-Up25 @ V =Max, V =0 V 500 μA ILPU2 DDEXT IN I Three-State Leakage Current6, 7, 8, 9 @ V =Max, V =V Max 10 μA OZH DDEXT IN DD I Three-State Leakage Current6 @ V =Max, V =0 V 10 μA OZL DDEXT IN I Three-State Leakage Current Pull-Down9 @ V =Max, V =V Max 250 μA OZHPD DDEXT IN DD I Three-State Leakage Current Pull-Up17 @ V =Max, V =0 V 250 μA OZLPU1 DDEXT IN I Three-State Leakage Current Pull-Up28 @ V =Max, V =0 V 500 μA OZLPU2 DDEXT IN I Three-State Leakage Current10 @ V =Max, V =V Max 25 μA OZHA DDEXT IN DD I Three-State Leakage Current10 @ V =Max, V =0 V 4 mA OZLA DDEXT IN I Supply Current (Internal)11 t =12.5 ns, V =Max 1400 mA DD-INPEAK CCLK DDINT I Supply Current (Internal)12 t =12.5 ns, V =Max 875 mA DD-INHIGH CCLK DDINT I Supply Current (Internal)13 t =12.5 ns, V =Max 625 mA DD-INLOW CCLK DDINT I Supply Current (Idle)14 t =12.5 ns, V =Max 400 mA DD-IDLE CCLK DDINT AI Supply Current (Analog)15 @AV =Max 10 mA DD DD C Input Capacitance16, 17 f =1 MHz, T =25°C, V =2.5 V 4.7 pF IN IN CASE IN 1Applies to output and bidirectional pins: DATA63–0, ADDR31–0, MS3–0, RDx, WRx, PAGE, CLKOUT, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS, TDO, and EMU. 2See Output Drive Currents—ADSP-21160M on Page47 for typical drive current capabilities. 3Applies to input pins: SBTS, IRQ2–0, HBR, CS, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK, and CLK_CFG3-0. 4Applies to input pins with internal pull-ups: DR0, and DR1. 5Applies to input pins with internal pull-ups: DMARx, TMS, TDI, and TRST. 6Applies to three-statable pins: DATA63–0, ADDR31–0, PAGE, CLKOUT, ACK, FLAG3–0, REDY, HBG, BMS, BR6–1, TFSx, RFSx, and TDO. 7Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, and EMU. 8Applies to three-statable pins with internal pull-ups: MS3–0,RDx, WRx, DMAGx, PA, and CIF. 9Applies to three-statable pins with internal pull-downs: LxDAT7–0, LxCLK, and LxACK. 10Applies to ACK pulled up internally with 2k during reset or ID2–0= 00x. 11The test program used to measure I represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power DD-INPEAK measurements made using typical applications are less than specified. For more information, see Power Dissipation on Page47. 12I is a composite average based on a range of high activity code. For more information, see Power Dissipation on Page47. DD-INHIGH 13I is a composite average based on a range of low activity code. For more information, see Power Dissipation on Page47. DD-INLOW 14Idle denotes ADSP-21160M state during execution of IDLE instruction. For more information, see Power Dissipation on Page47. 15Characterized, but not tested. 16Applies to all signal pins. 17Guaranteed, but not tested. Rev. D | Page 16 of 58 | September 2015

ADSP-21160M/ADSP-21160N OPERATING CONDITIONS—ADSP-21160N Table7 shows recommended operating conditions for the ADSP-21160N. These specifications are subject to change without notice. Table 7. Operating Conditions—ADSP-21160N C Grade K Grade Parameter Min Max Min Max Unit V Internal (Core) Supply Voltage 1.8 2.0 1.8 2.0 V DDINT AV Analog (PLL) Supply Voltage 1.8 2.0 1.8 2.0 V DD V External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 V DDEXT T Case Operating Temperature1 –40 +100 0 85 ºC CASE V High Level Input Voltage,2 @ V =Max 2.0 V +0.5 2.0 V +0.5 V IH1 DDEXT DDEXT DDEXT V High Level Input Voltage,3 @ V =Max 2.0 V +0.5 2.0 V +0.5 V IH2 DDEXT DDEXT DDEXT V Low Level Input Voltage,2, 3 @ V =Min –0.5 +0.8 –0.5 +0.8 V IL DDEXT 1See Environmental Conditions on Page51 for information on thermal specifications. 2Applies to input and bidirectional pins: DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, IRQ2–0, FLAG3–0, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, PA, BRST, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, and RCLK1. 3Applies to input pins: CLKIN, RESET, and TRST. Rev. D | Page 17 of 58 | September 2015

ADSP-21160M/ADSP-21160N ELECTRICAL CHARACTERISTICS—ADSP-21160N Table8shows the electrical characteristics. Note that these spec- ifications are subject to change without notification. Table 8. Electrical Characteristics—ADSP-21160N Parameter Test Conditions Min Max Unit V High Level Output Voltage1 @ V =Min, I =–2.0 mA2 2.4 V OH DDEXT OH V Low Level Output Voltage1 @ V =Min, I =4.0 mA2 0.4 V OL DDEXT OL I High Level Input Current3, 4, 5 @ V =Max, V =V Max 10 μA IH DDEXT IN DD I Low Level Input Current3 @ V =Max, V =0 V 10 μA IL DDEXT IN I CLKIN High Level Input Current6 @ V = Max, V = V Max 25 μA IHC DDEXT IN DDEXT I CLKIN Low Level Input Current6 @ V = Max, V = 0 V 25 μA ILC DDEXT IN I Keeper High Load Current7 @ V = Max, V = 2.0 V –250 –50 μA IKH DDEXT IN I Keeper Low Load Current7 @ V = Max, V = 0.8 V 50 200 μA IKL DDEXT IN I Keeper High Overdrive Current7, 8, 9 @ V = Max –300 μA IKH-OD DDEXT I Keeper Low Overdrive Current7, 8, 9 @ V = Max 300 μA IKL-OD DDEXT I Low Level Input Current Pull-Up14 @ V =Max, V =0 V 250 μA ILPU1 DDEXT IN I Low Level Input Current Pull-Up25 @ V =Max, V =0 V 500 μA ILPU2 DDEXT IN I Three-State Leakage Current10, 11, 12, 13 @ V =Max, V =V Max 10 μA OZH DDEXT IN DD I Three-State Leakage Current10 @ V =Max, V =0 V 10 μA OZL DDEXT IN I Three-State Leakage Current Pull-Down13 @ V =Max, V =V Max 250 μA OZHPD DDEXT IN DD I Three-State Leakage Current Pull-Up111 @ V =Max, V =0 V 250 μA OZLPU1 DDEXT IN I Three-State Leakage Current Pull-Up212 @ V =Max, V =0 V 500 μA OZLPU2 DDEXT IN I Three-State Leakage Current14 @ V =Max, V =V Max 25 μA OZHA DDEXT IN DD I Three-State Leakage Current14 @ V =Max, V =0 V 4 mA OZLA DDEXT IN I Supply Current (Internal)15 t =10.0 ns, V =Max 960 mA DD-INPEAK CCLK DDINT I Supply Current (Internal)16 t =10.0 ns, V =Max 715 mA DD-INHIGH CCLK DDINT I Supply Current (Internal)17 t =10.0 ns, V =Max 550 mA DD-INLOW CCLK DDINT I Supply Current (Idle)18 t =10.0 ns, V =Max 450 mA DD-IDLE CCLK DDINT AI Supply Current (Analog)9 @AV =Max 10 mA DD DD C Input Capacitance19, 20 f =1 MHz, T =25°C, V =2.5 V 4.7 pF IN IN CASE IN 1Applies to output and bidirectional pins: DATA63–0, ADDR31–0, MS3–0, RDx, WRx, PAGE, CLKOUT, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS, TDO, and EMU. 2See Output Drive Currents 47 for typical drive current capabilities. 3Applies to input pins: SBTS, IRQ2–0, HBR, CS, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK, and CLK_CFG3-0. 4Applies to input pins with internal pull-ups: DR0, and DR1. 5Applies to input pins with internal pull-ups: DMARx, TMS, TDI, and TRST. 6Applies to CLKIN only. 7Applies to all pins with keeper latches: ADDR31–0, DATA63–0, PAGE, BRST, and CLKOUT. 8Current required to switch from kept high to low, or from kept low to high. 9Characterized, but not tested. 10Applies to three-statable pins: DATA63–0, ADDR31–0, PAGE, CLKOUT, ACK, FLAG3–0, REDY, HBG, BMS, BR6–1, TFSx, RFSx, and TDO. 11Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, and EMU. 12Applies to three-statable pins with internal pull-ups: MS3–0,RDx, WRx, DMAGx, PA, and CIF. 13Applies to three-statable pins with internal pull-downs: LxDAT7–0, LxCLK, and LxACK. 14Applies to ACK pulled up internally with 2k during reset or ID2–0= 00x. 15The test program used to measure I represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power DD-INPEAK measurements made using typical applications are less than specified. For more information, see Power Dissipation on Page47. 16I is a composite average based on a range of high activity code. For more information, see Power Dissipation on Page47. DD-INHIGH 17I is a composite average based on a range of low activity code. For more information, see Power Dissipation on Page47. DD-INLOW 18Idle denotes ADSP-21160N state during execution of IDLE instruction. For more information, see Power Dissipation on Page47. 19Applies to all signal pins. 20Guaranteed, but not tested. Rev. D | Page 18 of 58 | September 2015

ADSP-21160M/ADSP-21160N ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION Stresses at or above those listed in Table9 (ADSP-21160M) and The information presented in Figure7 provides details about Table10 (ADSP-21160N) may cause permanent damage to the the package branding for the ADSP-21160M/ADSP-21160N product. These are stress ratings only; functional operation of processor. For a complete listing of product availability, see the product at these or any other conditions above those indi- Ordering Guide on Page58. cated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. a Table 9. Absolute Maximum Ratings—ADSP-21160M Parameter Rating ADSP-21160a tppZ-cc Internal (Core) Supply Voltage (V ) –0.3 V to +3.0 V DDINT vvvvvv.x n.n Analog (PLL) Supply Voltage (A ) –0.3 V to +3.0 V VDD #yyww country_of_origin External (I/O) Supply Voltage (V ) –0.3 V to +4.6 V DDEXT S Input Voltage –0.5 V to V + 0.5 V DDEXT Output Voltage Swing –0.5 V to V + 0.5 V DDEXT Load Capacitance 200 pF Figure 7. Typical Package Brand Storage Temperature Range –65C to +150C Table 11. Package Brand Information Table 10. Absolute Maximum Ratings—ADSP-21160N Brand Key Field Description Parameter Rating a ADSP-21160 Model (M or N) Internal (Core) Supply Voltage (V ) –0.3 V to +2.3 V t Temperature Range DDINT Analog (PLL) Supply Voltage (A ) –0.3 V to +2.3 V pp Package Type VDD External (I/O) Supply Voltage (V ) –0.3 V to +4.6 V Z RoHS Compliant Designation DDEXT Input Voltage –0.5 V to V + 0.5 V cc See Ordering Guide DDEXT Output Voltage Swing –0.5 V to V + 0.5 V vvvvvv.x Assembly Lot Code DDEXT Load Capacitance 200 pF n.n Silicon Revision Storage Temperature Range –65C to +150C # RoHS Compliant Designation yyww Date Code ESD SENSITIVITY ESD (electrostatic discharge sensitive device) Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Rev. D | Page 19 of 58 | September 2015

ADSP-21160M/ADSP-21160N TIMING SPECIFICATIONS circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such The ADSP-21160x DSP’s internal clock switches at higher fre- as memory) is satisfied. quencies than the system input clock (CLKIN). To generate the internal clock, the DSP uses an internal phase-locked loop Timing requirements apply to signals that are controlled by cir- (PLL). This PLL-based clocking minimizes the skew between cuitry external to the processor, such as the data input for a read the system clock (CLKIN) signal and the DSP’s internal clock operation. Timing requirements guarantee that the processor (the clock source for the external port logic and I/O pads). operates correctly with other devices. The ADSP-21160x DSP’s internal clock (a multiple of CLKIN) During processor reset (RESET pin low) or software reset (SRST provides the clock signal for timing internal memory, processor bit in SYSCON register = 1), deassertion (MS3–0, HBG, core, link ports, serial ports, and external port (as required for DMAGx, RDx, WRx, CIF, PAGE, BRST) and three-state read/write strobes in asynchronous access mode). During reset, (FLAG3-0, LxCLK, LxACK, LxDAT7-0, ACK, REDY, PA, program the ratio between the DSP’s internal clock frequency TFSx, RFSx, TCLKx, RCLKx, DTx, BMS, TDO, EMU, DATA) and external (CLKIN) clock frequency with the CLK_CFG3–0 timings differ. These occur asynchronously to CLKIN, and may pins. Even though the internal clock is the clock source for the not meet the specifications published in the timing require- external port, the external port clock always switches at the ments and switching characteristics tables. The maximum delay CLKIN frequency. To determine switching frequencies for the for deassertion and three-state is one tCK from RESET pin asser- serial and link ports, divide down the internal clock, using the tion low or setting the SRST bit in SYSCON. During reset the programmable divider control of each port (TDIVx/RDIVx for DSP will not respond to SBTS, HBR, and MMS accesses. HBR the serial ports and LxCLKD1–0 for the link ports). asserted before reset will be recognized, but an HBG will not be returned by the DSP until after reset is deasserted and the DSP Note the following definitions of various clock periods that are a has completed bus synchronization. function of CLKIN and the appropriate ratio control: Unless otherwise noted, all timing specifications (Timing • t = (t ) / CR CCLK CK Requirements and Switching Characteristics) listed on pages 21 • tLCLK = (tCCLK)  LR through 46 apply to both ADSP-21160M and ADSP-21160N. • t = (t ) SR SCLK CCLK Power-Up Sequencing where: For power-up sequencing, see Table12 and Figure8. During the • LCLK = Link Port Clock power-up sequence of the DSP, differences in the ramp-up rates • SCLK = Serial Port Clock and activation time between the two power supplies can cause current to flow in the I/O ESD protection circuitry. To prevent • t = CLKIN Clock Period CK this damage to the ESD diode protection circuitry, Analog • t = (Processor) Core Clock Period Devices recommends including a bootstrap Schottky diode (see CCLK Figure9). The bootstrap Schottky diode connected between the • t = Link Port Clock Period LCLK V and V power supplies protects the ADSP-21160x DDINT DDEXT • tSCLK = Serial Port Clock Period from partially powering the VDDEXT supply. Including a Schottky • CR = Core/CLKIN Ratio (2, 3, or 4:1, diode will shorten the delay between the supply ramps and thus determined by CLK_CFG3–0 at reset) prevent damage to the ESD diode protection circuitry. With this technique, if the V rail rises ahead of the V rail, the • LR = Link Port/Core Clock Ratio (1, 2, 3, or 4:1, DDINT DDEXT Schottky diode pulls the V rail along with the V rail. determined by LxCLKD) DDEXT DDINT • SR = Serial Port/Core Clock Ratio (wide range, determined by  CLKDIV) Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See Figure33 on Page49 under Test Conditions for voltage ref- erence levels. Switching characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching char- acteristics describe what the processor will do in a given Rev. D | Page 20 of 58 | September 2015

ADSP-21160M/ADSP-21160N Table 12. Power-Up Sequencing Parameter Min Max Unit Timing Requirements t RESET Low Before V /V on 0 ns RSTVDD DDINT DDEXT t V on Before V –50 +200 ms IVDDEVDD DDINT DDEXT t CLKIN Running After valid V /V 1 0 200 ms CLKVDD DDINT DDEXT t CLKIN Valid Before RESET Deasserted 102 μs CLKRST t PLL Control Setup Before RESET Deasserted 203 μs PLLRST Switching Characteristics t DSP Core Reset Deasserted After RESET Deasserted 4096t 3, 4 CORERST CK 1Valid V /V assumes that the supplies are fully ramped to their V and V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds, DDINT DDEXT DDINT DDEXT depending on the design of the power supply subsystem. 2Assumes a stable CLKIN signal after meeting worst-case start-up timing of oscillators. Refer to your oscillator manufacturer’s data sheet for start-up time. 3Based on CLKIN cycles. 4CORERST is an internal signal only. The 4096 cycle count is dependent on t specification. If setup time is not met, one additional CLKIN cycle may be added to the core SRST reset time, resulting in 4097 cycles maximum. RESET t RSTVDD VDDINT t IVDDEVDD VDDEXT t CLKVDD CLKIN t CLKRST CLK_CFG3-0 tPLLRST tCORERST CORERST Figure 8. Power-Up Sequencing Rev. D | Page 21 of 58 | September 2015

ADSP-21160M/ADSP-21160N VDDEXT VDDEXT VOLTAGEREGULATOR ADSP-21160x VDDINT VDDINT VOLTAGEREGULATOR Figure 9. Dual Voltage Schottky Diode Clock Input For clock input, see Table13 and Figure10. Table 13. Clock Input ADSP-21160M ADSP-21160N 80 MHz 100 MHz Unit Parameter Min Max Min Max Timing Requirements t CLKIN Period 25 80 20 80 ns CK t CLKIN Width Low 10.5 40 7.5 40 ns CKL t CLKIN Width High 10.5 40 7.5 40 ns CKH t CLKIN Rise/Fall (0.4 V–2.0 V) 3 3 ns CKRF t Core Clock Period 12.5 40 10 30 ns CCLK t CK CLKIN tCKH tCKL Figure 10. Clock Input Rev. D | Page 22 of 58 | September 2015

ADSP-21160M/ADSP-21160N Reset For reset, see Table14 and Figure11. Table 14. Reset Parameter Min Max Unit Timing Requirements t RESET Pulsewidth Low1 4t ns WRST CK t RESET Setup Before CLKIN High2 8 ns SRST 1Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than100μs while RESET is low, assuming stable V and CLKIN (not including start-up time of external clock oscillator). DD 2Only required if multiple ADSP-21160x DSPs must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21160x DSPs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself afterreset. CLKIN t t SRST WRST RESET Figure 11. Reset Rev. D | Page 23 of 58 | September 2015

ADSP-21160M/ADSP-21160N Interrupts For interrupts, see Table15 and Figure12. Table 15. Interrupts Parameter Min Max Unit Timing Requirements t IRQ2–0 Setup Before CLKIN High1 6 ns SIR t IRQ2–0 Hold After CLKIN High1 0 ns HIR t IRQ2–0 Pulsewidth2 2+t ns IPW CK 1Only required for IRQx recognition in the following cycle. 2Applies only if t and t requirements are not met. SIR HIR CLKIN t SIR t HIR IRQ2–0 t IPW Figure 12. Interrupts Timer For timer, see Table16 and Figure13. Table 16. Timer Parameter Min Max Unit Switching Characteristic t CLKIN High to TIMEXP1 1 9 ns DTEX 1For ADSP-21160M, specification is 7ns, maximum. CLKIN t t DTEX DTEX TIMEXP Figure 13. Timer Rev. D | Page 24 of 58 | September 2015

ADSP-21160M/ADSP-21160N Flags For flags, see Table17 and Figure14. Table 17. Flags Parameter Min Max Unit Timing Requirements t FLAG3–0 IN Setup Before CLKIN High1 4 ns SFI t FLAG3–0 IN Hold After CLKIN High1 1 ns HFI t FLAG3–0 IN Delay After RDx/WRx Low1, 2 10 ns DWRFI t FLAG3–0 IN Hold After RDx/WRx Deasserted1 0 ns HFIWR Switching Characteristics t FLAG3–0 OUT Delay After CLKIN High 9 ns DFO t FLAG3–0 OUT Hold After CLKIN High 1 ns HFO t CLKIN High to FLAG3–0 OUT Enable 1 ns DFOE t CLKIN High to FLAG3–0 OUT Disable3 t –t +5 ns DFOD CK CCLK 1Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2. 2For ADSP-21160M, specification is 12ns, maximum. 3For ADSP-21160M, specification is 5ns, maximum. CLKIN t tDFOE tDFO DFO tDFOD t HFO FLAG3–0OUT FLAGOUTPUT CLKIN t t SFI HFI FLAG3–0IN tDWRFI tHFIWR RDx WRx FLAGINPUT Figure 14. Flags Rev. D | Page 25 of 58 | September 2015

ADSP-21160M/ADSP-21160N Memory Read—Bus Master of Table18. These specifications apply when the ADSP-21160x is the bus master accessing external memory space in asynchro- Use these specifications for asynchronous interfacing to nous access mode. memories (and memory-mapped peripherals) without reference to CLKIN except for the ACK pin requirements listed in note 6 Table 18. Memory Read—Bus Master Parameter Min Max Unit Timing Requirements t Address, CIF, Selects Delay to Data Valid1, 2, 3, 4 t –0.25t –8.5+W ns DAD CK CCLK t RDx Low to Data Valid1, 4, 5 t –0.5t +W ns DRLD CK CCLK t Data Hold from Address, Selects6 0 ns HDA t Data Setup to RDx High1 8 ns SDS t Data Hold from RDx High6 1 ns HDRH t ACK Delay from Address, Selects2, 7 t –0.5t –12+W ns DAAK CK CCLK t ACK Delay from RDx Low7 t –0.75t –11+W ns DSAK CK CCLK t ACK Setup to CLKIN7 0.5t +3 ns SAKC CCLK t ACK Hold After CLKIN 1 ns HAKC Switching Characteristics t Address, CIF, Selects Hold After RDx High 0.25t –1+H ns DRHA CCLK t Address, CIF, Selects to RDx Low2 0.25t –3 ns DARL CCLK t RDx Pulsewidth t –0.5t –1+W ns RW CK CCLK t RDx High to WRx, RDx, DMAGx Low 0.5t –1+HI ns RWR CCLK W = (number of wait states specified in WAIT register)  t . CK HI = t (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0). CK H = t (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0). CK 1Data Delay/Setup: User must meet t , t , or t . DAD DRLD SDS 2The falling edge of MSx, BMS is referenced. 3For ADSP-21160M, specification is t –0.25t –11+Wns, maximum. CK CCLK 4The maximum limit of timing requirement values for t and t parameters are applicable for the case where AMI_ACK is always high. DAD DRLD 5For ADSP-21160M, specification is 0.75t –11+Wns, maximum. CK 6Data Hold: User must meet t or t in asynchronous access mode. See Example System Hold Time Calculation on page 49 for the calculation of hold times given capacitive HDA HDRH and dc loads. 7For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access, ACK must be driven low (deasserted) by t , t , or t . For the second and subsequent cycles of an asynchronous external memory access, the t and t must be DAAK DSAK SAKC SAKC HAKC met for both assertion and deassertion of ACK signal. Rev. D | Page 26 of 58 | September 2015

ADSP-21160M/ADSP-21160N t HDA ADDRESS MSx,BMS, CIF t t t DRHA DARL RW RD t t DRLD SDS t t DAD HDRH DATA t DSAK t t DAAK RWR ACK tSAKC tHAKC CLKIN WR,DMAG Figure 15. Memory Read—Bus Master Rev. D | Page 27 of 58 | September 2015

ADSP-21160M/ADSP-21160N Memory Write—Bus Master of Table19. These specifications apply when the ADSP-21160x is the bus master accessing external memory space in asynchro- Use these specifications for asynchronous interfacing to nous access mode. memories (and memory-mapped peripherals) without reference to CLKIN except for the ACK pin requirements listed in note 1 Table 19. Memory Write—Bus Master Parameter Min Max Unit Timing Requirements t ACK Delay from Address, Selects1, 2 t –0.5t –12+W ns DAAK CK CCLK t ACK Delay from WRx Low1 t –0.75t –11+W ns DSAK CK CCLK t ACK Setup to CLKIN1 0.5t +3 ns SAKC CCLK t ACK Hold After CLKIN1 1 ns HAKC Switching Characteristics t Address, CIF, Selects to WRx Deasserted2 t –0.25t –3+W ns DAWH CK CCLK t Address, CIF, Selects to WRx Low2 0.25t –3 ns DAWL CCLK t WRx Pulsewidth t –0.5t –1+W ns WW CK CCLK t Data Setup before WRx High3 t –0.5t –1+W ns DDWH CK CCLK t Address Hold after WRx Deasserted 0.25t –1+H ns DWHA CCLK t Data Hold after WRx Deasserted 0.25t –1+H ns DWHD CCLK t Data Disable after WRx Deasserted4 0.25t –2+H 0.25t +2+H ns DATRWH CCLK CCLK t WRx High to WRx, RDx, DMAGx Low 0.5t –1+HI ns WWR CCLK t Data Disable before WRx or RDx Low 0.25t –1+I ns DDWR CCLK t WRx Low to Data Enabled –0.25t –1 ns WDE CCLK W = (number of wait states specified in WAIT register) × t . CK H = t (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0). CK HI = t (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0). CK I = t (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0). CK 1For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access, ACK must be driven low (deasserted) by t or t or t . For the second and subsequent cycles of an asynchronous external memory access, the t and DAAK DSAK SAKC SAKC t must be met for both assertion and deassertion of ACK signal. HAKC 2The falling edge of MSx, BMS is referenced. 3For ADSP-21160M, specification is t –0.25t –12.5+Wns, minimum. CK CCLK 4See Example System Hold Time Calculation on Page49 for calculation of hold times given capacitive and dc loads. Rev. D | Page 28 of 58 | September 2015

ADSP-21160M/ADSP-21160N ADDRESS MSx, BMS, CIF tDAWH tDWHA tDAWL tWW WR t WWR t tWDE DATRWH tDDWH tDDWR DATA t tDSAK tDWHD DAAK ACK t t SAKC HAKC CLKIN RD, DMAG Figure 16. Memory Write—Bus Master Rev. D | Page 29 of 58 | September 2015

ADSP-21160M/ADSP-21160N Synchronous Read/Write—Bus Master When accessing a slave ADSP-21160x, these switching charac- teristics must meet the slave’s timing requirements for See Table20 and Figure17. Use these specifications for interfac- synchronous read/writes (see Synchronous Read/Write–Bus ing to external memory systems that require CLKIN—relative Slave on page 32). The slave ADSP-21160x must also meet these timing or for accessing a slave ADSP-21160x (in multiprocessor (bus master) timing requirements for data and acknowledge memory space). These synchronous switching characteristics setup and hold times. are also valid during asynchronous memory reads and writes except where noted (see Memory Read–Bus Master on page 26 and Memory Write–Bus Master on page 28). Table 20. Synchronous Read/Write—Bus Master Parameter Min Max Unit Timing Requirements t Data Setup Before CLKIN 5.5 ns SSDATI t Data Hold After CLKIN 1 ns HSDATI t ACK Setup Before CLKIN 0.5t +3 ns SACKC CCLK t ACK Hold After CLKIN 1 ns HACKC Switching Characteristics t Address, MSx, BMS, BRST, CIF Delay After CLKIN 10 ns DADDO t Address, MSx, BMS, BRST, CIF Hold After CLKIN 1.5 ns HADDO t PAGE Delay After CLKIN 1.5 11 ns DPGO t RDx High Delay After CLKIN 0.25t –1 0.25t +9 ns DRDO CCLK CCLK t WRx High Delay After CLKIN 0.25t –1 0.25t +9 ns DWRO CCLK CCLK t RDx/WRx Low Delay After CLKIN 0.25t –1 0.25t +9 ns DRWL CCLK CCLK t Data Delay After CLKIN1 0.25t +9 ns DDATO CCLK t Data Hold After CLKIN 1.5 ns HDATO t ACK Delay After CLKIN2, 3 3 9 ns DACKMO t ACK Disable Before CLKIN2 –3 ns ACKMTR t CLKOUT Delay After CLKIN4 0.5 5 ns DCKOO t CLKOUT Period t –1 t 5+1 ns CKOP CK CK t CLKOUT Width High t /2–2 t /2+22 ns CKWH CK CK t CLKOUT Width Low t /2–2 t /2+22 ns CKWL CK CK 1For ADSP-21160M, specification is 12.5ns, maximum. 2Applies to broadcast write, master precharge of ACK. 3For ADSP-21160M, specification is 0.25t +3ns (minimum) and .25t +9ns (maximum). CCLK CCLK 4For ADSP-21160M, specification is 2ns, minimum. 5Applies only when the DSP drives a bus operation; CLKOUT held inactive or three-state otherwise. For more information, see the System Design chapter in the ADSP-21160 SHARC DSP Hardware Reference. Rev. D | Page 30 of 58 | September 2015

ADSP-21160M/ADSP-21160N CLKIN t CKOP t t t DCKOO CKWH CKWL CLKOUT tDADDO tHADDO ADDRESS MSx,BRST, CIF t DPGO PAGE tSACKC tHACKC ACK (IN) t t DACKMO ACKMTR ACK (OUT) READCYCLE t DRWL t DRDO RDx t t SSDATI HSDATI DATA (IN) WRITECYCLE tDRWL tDWRO WRx t t HDATO DDATO DATA (OUT) Figure 17. Synchronous Read/Write—Bus Master Rev. D | Page 31 of 58 | September 2015

ADSP-21160M/ADSP-21160N Synchronous Read/Write—Bus Slave See Table21 and Figure18. Use these specifications for ADSP-21160x bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor memory space). The bus master must meet these (bus slave) timing requirements. Table 21. Synchronous Read/Write—Bus Slave Parameter Min Max Unit Timing Requirements t Address, BRST Setup Before CLKIN 5 ns SADDI t Address, BRST Hold After CLKIN 1 ns HADDI t RDx/WRx Setup Before CLKIN 5 ns SRWI t RDx/WRx Hold After CLKIN 1 ns HRWI t Data Setup Before CLKIN 5.5 ns SSDATI t Data Hold After CLKIN 1 ns HSDATI Switching Characteristics t Data Delay After CLKIN1 0.25 t + 9 ns DDATO CCLK t Data Hold After CLKIN 1.5 ns HDATO t ACK Delay After CLKIN 10 ns DACKC t ACK Hold After CLKIN 1.5 ns HACKO 1For ADSP-21160M, specification is 12.5ns, maximum. CLKIN t SADDI t HADDI ADDRESS BRST tDACKC tHACKO ACK READACCESS tSRWI tHRWI RDx tDDATO tHDATO DATA (OUT) WRITEACCESS tSRWI tHRWI WRx tSSDATI tHSDATI DATA (IN) Figure 18. Synchronous Read/Write—Bus Slave Rev. D | Page 32 of 58 | September 2015

ADSP-21160M/ADSP-21160N Multiprocessor Bus Request and Host Bus Request See Table22 and Figure19. Use these specifications for passing of bus mastership between multiprocessing ADSP-21160x DSPs (BRx) or a host processor, both synchronous and asynchronous (HBR, HBG). Table 22. Multiprocessor Bus Request and Host Bus Request Parameter Min Max Unit Timing Requirements t HBG Low to RDx/WRx/CS Valid1 6.5 + t + t – 12.5CR ns HBGRCSV CK CCLK t HBR Setup Before CLKIN2 6 ns SHBRI t HBR Hold After CLKIN2 1 ns HHBRI t HBG Setup Before CLKIN 6 ns SHBGI t HBG Hold After CLKIN High 1 ns HHBGI t BRx, PA Setup Before CLKIN 9 ns SBRI t BRx, PA Hold After CLKIN High 1 ns HBRI t RPBA Setup Before CLKIN 6 ns SRPBAI t RPBA Hold After CLKIN 2 ns HRPBAI Switching Characteristics t HBG Delay After CLKIN 7 ns DHBGO t HBG Hold After CLKIN3 1.5 ns HHBGO t BRx Delay After CLKIN 8 ns DBRO t BRx Hold After CLKIN 1.5 ns HBRO t PA Delay After CLKIN, Slave 8 ns DPASO t PA Disable After CLKIN, Slave 1.5 ns TRPAS t PA Delay After CLKIN, Master 0.25t +9 ns DPAMO CCLK t PA Disable Before CLKIN, Master4 0.25t –5.5 ns PATR CCLK t REDY (O/D) or (A/D) Low from CS and HBR Low5, 6 0.5t +1.0 ns DRDYCS CK t REDY (O/D) Disable or REDY (A/D) High from HBG5, 7 t +15 ns TRDYHG CK t REDY (A/D) Disable from CS or HBR High5 11 ns ARDYTR 1For ADSP-21160M, specification is 19ns, maximum. 2Only required for recognition in the current cycle. 3For ADSP-21160M, specification is 2ns, maximum. 4For ADSP-21160M, specification is 0.25t –5ns, minimum. CK 5(O/D) = open drain, (A/D) = active drive. 6For ADSP-21160M, specification is 0.5t ns, maximum. CK 7For ADSP-21160M, specification is t +25ns, maximum. CK Rev. D | Page 33 of 58 | September 2015

ADSP-21160M/ADSP-21160N CLKIN t SHBRI t HHBRI HBR tDHBGO t HHBGO HBG(OUT) t DBRO t HBRO BRx(OUT) tDPASO tTRPAS PA(OUT) (SLAVE) tDPAMO tPATR PA(OUT) (MASTER) t SHBGI tHHBGI HBG(IN) t SBRI t HBRI BRx,PA(IN) t SRPBAI t HRPBAI RPBA HRB CS tDRDYCS tTRDYHG REDY (O/D) t ARDYTR REDY (A/D) t HBGRCSV HBG(OUT) RDx WRx CS O/D=OPENDRAIN,A/D=ACTIVEDRIVE Figure 19. Multiprocessor Bus Request and Host Bus Request Rev. D | Page 34 of 58 | September 2015

ADSP-21160M/ADSP-21160N Asynchronous Read/Write—Host to ADSP-21160x After HBG is returned by the ADSP-21160x, the host can drive the RDx and WRx pins to access the ADSP-21160x DSP’s Use these specifications (Table23, Table24, Figure20, and internal memory or IOP registers. HBR and HBG are assumed Figure21) for asynchronous host processor accesses of an low for this timing. ADSP-21160x, after the host has asserted CS and HBR (low). Table 23. Read Cycle Parameter Min Max Unit Timing Requirements t Address Setup/CS Low Before RDx Low 0 ns SADRDL t Address Hold/CS Hold Low After RDx 2 ns HADRDH t RDx/WRx High Width 5 ns WRWH t RDx High Delay After REDY (O/D) Disable 0 ns DRDHRDY t RDx High Delay After REDY (A/D) Disable 0 ns DRDHRDY Switching Characteristics t Data Valid Before REDY Disable from Low 2 ns SDATRDY t REDY (O/D) or (A/D) Low Delay After RDx Low1 11 ns DRDYRDL t REDY (O/D) or (A/D) Low Pulsewidth for Read2 t – 4 ns RDYPRD CK t Data Disable After RDx High3 1.5 6 ns HDARWH 1For ADSP-21160M, specification is 7ns, minimum. 2For ADSP-21160M, specification is t ns, minimum. CK 3For ADSP-21160M, specification is 2ns, minimum. Table 24. Write Cycle Parameter Min Max Unit Timing Requirements t CS Low Setup Before WRx Low 0 ns SCSWRL t CS Low Hold After WRx High 0 ns HCSWRH t Address Setup Before WRx High 6 ns SADWRH t Address Hold After WRx High 2 ns HADWRH t WRx Low Width1 t +1 ns WWRL CCLK t RDx/WRx High Width 5 ns WRWH t WRx High Delay After REDY (O/D) or (A/D) Disable 0 ns DWRHRDY t Data Setup Before WRx High 5 ns SDATWH t Data Hold After WRx High 4 ns HDATWH Switching Characteristics t REDY (O/D) or (A/D) Low Delay After WRx/CS Low 11 ns DRDYWRL t REDY (O/D) or (A/D) Low Pulsewidth for Write2 5.75 + 0.5t ns RDYPWR CCLK 1For ADSP-21160M, specification is 7ns, minimum. 2For ADSP-21160M, specification is 12ns, minimum. Rev. D | Page 35 of 58 | September 2015

ADSP-21160M/ADSP-21160N READCYCLE ADDRESS/CS t t HADRDH SADRDL t WRWH RDx t HDARWH DATA(OUT) tSDATRDY tDRDHRDY t t DRDYRDL RDYPRD REDY(O/D) REDY(A/D) Figure 20. Asynchronous Read—Host to ADSP-21160x WRITECYCLE ADDRESS t SADWRH t HADWRH t SCSWRL t HCSWRH CS t t WWRL WRWH WRx t t HDATWH SDATWH DATA(IN) t t t DRDYWRL RDYPWR DWRHRDY REDY(O/D) REDY(A/D) O/D=OPENDRAIN,A/D=ACTIVEDRIVE Figure 21. Asynchronous Write—Host to ADSP-21160x Rev. D | Page 36 of 58 | September 2015

ADSP-21160M/ADSP-21160N Three-State Timing—Bus Master, Bus Slave See Table25 and Figure22. These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin. Table 25. Three-State Timing—Bus Master, Bus Slave Parameter Min Max Unit Timing Requirements t SBTS Setup Before CLKIN 6 ns STSCK t SBTS Hold After CLKIN1 2 ns HTSCK Switching Characteristics t Address/Select Enable After CLKIN 1.5 9 ns MIENA t Strobes Enable After CLKIN2 1.5 9 ns MIENS t HBG Enable After CLKIN 1.5 9 ns MIENHG t Address/Select Disable After CLKIN3 0.5 9 ns MITRA t Strobes Disable After CLKIN2, 4, 5 0.25t –4 0.25t +1.5 ns MITRS CCLK CCLK t HBG Disable After CLKIN6 0.5 8 ns MITRHG t Data Enable After CLKIN7, 8 0.25t +1 0.25t +7 ns DATEN CCLK CCLK t Data Disable After CLKIN7, 9 0.5 5 ns DATTR t ACK Enable After CLKIN7 1.5 9 ns ACKEN t ACK Disable After CLKIN7 1.5 5 ns ACKTR t CLKOUT Enable After CLKIN10 0.5 9 ns CDCEN t CLKOUT Disable After CLKIN t –3 t +1 ns CDCTR CCLK CCLK t Address, MSx Disable Before HBG Low11 1.5t –6 1.5t + 5 ns ATRHBG CK CK t RDx, WRx, DMAGx Disable Before HBG Low11 t + 0.25t –6 t + 0.25t + 5 ns STRHBG CK CCLK CK CCLK t Page Disable Before HBG Low11 t –6 t + 5 ns PTRHBG CK CK t BMS Disable Before HBG Low11 0.5t –6.5 0.5t + 1.5 ns BTRHBG CK CK t Memory Interface Enable After HBG High12, 13 t –5 t +6 ns MENHBG CK CK 1For ADSP-21160M, specification is 1ns, minimum. 2Strobes = RDx, WRx, and DMAGx. 3For ADSP-21160M, specification is 0.25t –1ns (minimum) and 0.25t +4ns (maximum). CCLK CCLK 4If access aborted by SBTS, then strobes disable before CLKIN [0.25t + 1.5 (min.), 0.25t + 5 (max.)] CCLK CCLK 5For ADSP-21160M, specification is 0.25t ns (maximum). CCLK 6For ADSP-21160M, specification is 3.5 ns (minimum). 7In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write. 8For ADSP-21160M, specification is 1.5ns (minimum) and 10ns (maximum). 9For ADSP-21160M, specification is 1.5ns (minimum). 10For ADSP-21160M, specification is 0.5ns (minimum). 11Not specified for ADSP-21160M. 12Memory Interface = Address, RDx, WRx, MSx, PAGE, DMAGx, and BMS (in EPROM boot mode). 13For ADSP-21160M, specification is t +5ns (maximum). CK Rev. D | Page 37 of 58 | September 2015

ADSP-21160M/ADSP-21160N CLKIN t STSCK t HTSCK SBTS tMIENA,tMIENS,tMIENHG tMITRA,tMITRS,tMITRHG MEMORY INTERFACE t t DATTR DATEN DATA tACKEN tACKTR ACK t CDCEN t CDCTR CLKOUT t HBG ATRHBG t STRHBG tMENHBG ttPTRHBG BTRHBG MEMORY INTERFACE MEMORYINTERFACE=ADDRESS,RDx,WRx,MSx,PAGE,DMAGx.BMS(INEPROMBOOTMODE) Figure 22. Three-State Timing—Bus Master, Bus Slave Rev. D | Page 38 of 58 | September 2015

ADSP-21160M/ADSP-21160N DMA Handshake signals. For Paced Master mode, the data transfer is controlled by ADDR31–0, RDx, WRx, MS3–0, and ACK (not DMAGx). See Table26 and Figure23. These specifications describe the For Paced Master mode, the Memory Read-Bus Master, Mem- three DMA handshake modes. In all three modes, DMARx is ory Write-Bus Master, and Synchronous Read/Write-Bus used to initiate transfers. For handshake mode, DMAGx con- Master timing specifications for ADDR31–0, RDx, WRx, trols the latching or enabling of data externally. For external MS3–0, PAGE, DATA63–0, and ACK also apply. handshake mode, the data transfer is controlled by the ADDR31–0, RDx, WRx, PAGE, MS3–0, ACK, and DMAGx Table 26. DMA Handshake Parameter Min Max Unit Timing Requirements t DMARx Setup Before CLKIN1 3 ns SDRC t DMARx Width Low (Nonsynchronous)2, 3 0.5t +2.5 ns WDR CCLK t Data Setup After DMAGx Low4, 5 t –0.5t –7 ns SDATDGL CK CCLK t Data Hold After DMAGx High 2 ns HDATIDG t Data Valid After DMARx High4, 6 t +3 ns DATDRH CK t DMARx Low Edge to Low Edge7 t ns DMARLL CK t DMARx Width High2, 8 0.5t +1 ns DMARH CCLK Switching Characteristics t DMAGx Low Delay After CLKIN 0.25t +1 0.25t +9 ns DDGL CCLK CCLK t DMAGx High Width 0.5t –1+HI ns WDGH CCLK t DMAGx Low Width t –0.5t –1 ns WDGL CK CCLK t DMAGx High Delay After CLKIN t –0.25t +1.5 t –0.25t +9 ns HDGC CK CCLK CK CCLK t Data Valid Before DMAGx High9 t –0.25t –8 t –0.25t +5 ns VDATDGH CK CCLK CK CCLK t Data Disable After DMAGx High10 0.25t –3 0.25t +1.5 ns DATRDGH CCLK CCLK t WRx Low Before DMAGx Low –1.5 2 ns DGWRL t DMAGx Low Before WRx High t –0.5t –2+W ns DGWRH CK CCLK t WRx High Before DMAGx High11 –1.5 2 ns DGWRR t RDx Low Before DMAGx Low –1.5 2 ns DGRDL t RDx Low Before DMAGx High t –0.5t –2+W ns DRDGH CK CCLK t RDx High Before DMAGx High11 –1.5 2 ns DGRDR t DMAGx High to WRx, RDx, DMAGx Low 0.5t –2+HI ns DGWR CCLK t Address/Select Valid to DMAGx High12 15.5 ns DADGH t Address/Select Hold after DMAGx High 1 ns DDGHA W = (number of wait states specified in WAIT register)  t . CK HI = t (if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0). CK 1Only required for recognition in the current cycle. 2Maximum throughput using DMARx / DMAGx handshaking equals t + t = (0.5t +1) + (0.5t +1)=10.0 ns (100 MHz). This throughput limit applies to WDR DMARH CCLK CCLK non-synchronous access mode only. 3For ADSP-21160M, specification is t +4.5ns, minimum. CCLK 4t is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the SDATDGL data can be driven t after DMARx is brought high. DATDRH 5For ADSP-21160M, specification is 0.75t –7ns, maximum. CCLK 6For ADSP-21160M, specification is t +10ns, maximum. CLK 7Use t if DMARx transitions synchronous with CLKIN. Otherwise, use t and t . DMARLL WDR DMARH 8For ADSP-21160M, specification is t +4.5ns, minimum. CCLK 9t is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t =t –0.25t –8+(n×t ) where VDATDGH VDATDGH CK CCLK CK n equals the number of extra cycles that the access is prolonged. 10See Example System Hold Time Calculation on page 49 for calculation of hold times given capacitive and dc loads. 11This parameter applies for synchronous access mode only. 12For ADSP-21160M, specification is 18ns, minimum. Rev. D | Page 39 of 58 | September 2015

ADSP-21160M/ADSP-21160N CLKIN t SDRC t DMARLL t SDRC t t WDR DMARH DMARx t HDGC t DDGL t t WDGL WDGH DMAGx TRANSFERSBETWEEN ADSP-2116X t INTERNALMEMORYANDEXTERNALDEVICE DATRDGH t VDATDGH DATA (FROM ADSP-2116XTOEXTERNALDRIVE) t DATDRH t t SDATDGL HDATIDG DATA (FROMEXTERNAL DRIVETOADSP-2116X) TRANSFERSBETWEENEXTERNALDEVICEAND EXTERNALMEMORY*(EXTERNALHANDSHAKE MODE) tDGWRL tDGWRH tDGWRR WRx (EXTERNALDEVICETOEXTERNAL MEMORY) t DGRDR RDx t DGRDL (EXTERNALMEMORYTOEXTERNALDEVICE) t DRDGH t t DADGH DDGHA ADDR MSx *MEMORYREADBUSMASTER,MEMORYWRITEBUSMASTER,ORSYNCHRONOUSREAD/WRITEBUSMASTER TIMINGSPECIFICATIONSFORADDR31–0,RDx,WRx,MS3–0ANDACKALSOAPPLYHERE. Figure 23. DMA Handshake Rev. D | Page 40 of 58 | September 2015

ADSP-21160M/ADSP-21160N Link Ports—Receive, Transmit maximum delay that can be introduced in LCLK, relative to LDATA (hold skew=t minimum + t –t ). Cal- For link ports, see Table27, Table28, Figure24, and Figure25. LCLKTWL HLDCH HLDCL culations made directly from speed specifications result in Calculation of link receiver data setup and hold, relative to link unrealistically small skew times, because they include multiple clock, is required to determine the maximum allowable skew tester guardbands. that can be introduced in the transmission path, between LDATA and LCLK. Setup skew is the maximum delay that can Note that there is a two-cycle effect latency between the link be introduced in LDATA, relative to LCLK (setup port enable instruction and the DSP enabling the link port. skew=t minimum–t –t ). Hold skew is the LCLKTWH DLDCH SLDCL Table 27. Link Ports—Receive Parameter Min Max Unit Timing Requirements t Data Setup Before LCLK Low 2.5 ns SLDCL t Data Hold After LCLK Low1 3 ns HLDCL t LCLK Period t ns LCLKIW LCLK t LCLK Width Low2 4 ns LCLKRWL t LCLK Width High3 4 ns LCLKRWH Switching Characteristics t LACK Low Delay After LCLK High4, 5 9 17 ns DLALC 1For ADSP-21160M, specification is 2.5ns, minimum. 2For ADSP-21160M, specification is 6ns, minimum. 3For ADSP-21160M, specification is 6ns, minimum. 4LACK goes low with t relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill. DLALC 5For ADSP-21160M, specification is 12ns, minimum. RECEIVE t LCLKIW tLCLKRWH tLCLKRWL LCLK t t HLDCL SLDCL LDAT(7:0) IN t DLALC LACK(OUT) Figure 24. Link Ports—Receive Rev. D | Page 41 of 58 | September 2015

ADSP-21160M/ADSP-21160N Table 28. Link Ports—Transmit Parameter Min Max Unit Timing Requirements t LACK Setup Before LCLK High 14 ns SLACH t LACK Hold After LCLK High –2 ns HLACH Switching Characteristics t Data Delay After LCLK High 4 ns DLDCH t Data Hold After LCLK High –2 ns HLDCH t LCLK Width Low1 0.5t –0.5 0.5t +0.5 ns LCLKTWL LCLK LCLK t LCLK Width High2 0.5t –0.5 0.5t +0.5 ns LCLKTWH LCLK LCLK t LCLK Low Delay After LACK High3 0.5t +4 3/2t +11 ns DLACLK LCLK LCLK 1For ADSP-21160M, specification is 0.5t –1.5ns (minimum) and 0.5t +1.5ns (maximum). LCLK LCLK 2For ADSP-21160M, specification is 0.5t –1.5ns (minimum) and 0.5t +1.5ns (maximum). LCLK LCLK 3For ADSP-21160M, specification is 0.5t +5ns (minimum) and 3t +11ns (maximum). LCLK LCLK TRANSMIT tLCLKTWH tLCLKTWL LASTNIBBLE/BYTE FIRSTNIBBLE/BYTE LCLKINACTIVE TRANSMITTED TRANSMITTED (HIGH) LCLK t DLDCH t HLDCH LDAT(7:0) OUT tSLACH tHLACH tDLACLK LACK(IN) THEtSLACHREQUIREMENTAPPLIESTOTHERISINGEDGEOFLCLKONLYFORTHEFIRSTNIBBLE/BYTETRANSMITTED. Figure 25. Link Ports—Transmit Rev. D | Page 42 of 58 | September 2015

ADSP-21160M/ADSP-21160N Serial Ports at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay For serial ports, see Table29, Table30, Table31, Table32, and data setup and hold, and 3) SCLK width. Table33, Table34, Table35, Figure26, and Figure27. To deter- mine whether communication is possible between two devices Table 29. Serial Ports—External Clock Parameter Min Max Unit Timing Requirements t TFS/RFS Setup Before TCLK/RCLK1 3.5 ns SFSE t TFS/RFS Hold After TCLK/RCLK1 4 ns HFSE t Receive Data Setup Before RCLK1 1.5 ns SDRE t Receive Data Hold After RCLK1, 2 6.5 ns HDRE t TCLK/RCLK Width3 8 ns SCLKW t TCLK/RCLK Period 2t ns SCLK CCLK 1Referenced to sample edge. 2For ADSP-21160M, specification is 4ns, minimum. 3For ADSP-21160M, specification is 14ns, minimum. Table 30. Serial Ports—Internal Clock Parameter Min Max Unit Timing Requirements t TFS Setup Before TCLK1; RFS Setup Before RCLK1 8 ns SFSI t TFS/RFS Hold After TCLK/RCLK1, 2 t /2 + 1 ns HFSI CCLK t Receive Data Setup Before RCLK1 6.5 ns SDRI t Receive Data Hold After RCLK1 3 ns HDRI 1Referenced to sample edge. 2For ADSP-21160M, specification is 1ns, minimum. Table 31. Serial Ports—External or Internal Clock Parameter Min Max Unit Switching Characteristics t RFS Delay After RCLK (Internally Generated RFS)1 13 ns DFSE t RFS Hold After RCLK (Internally Generated RFS)1 3 ns HOFSE 1Referenced to drive edge. Table 32. Serial Ports—External Clock Parameter Min Max Unit Switching Characteristics t TFS Delay After TCLK (Internally Generated TFS)1 13 ns DFSE t TFS Hold After TCLK (Internally Generated TFS)1 3 ns HOFSE t Transmit Data Delay After TCLK1 16 ns DDTE t Transmit Data Hold After TCLK1 0 ns HDTE 1Referenced to drive edge. Rev. D | Page 43 of 58 | September 2015

ADSP-21160M/ADSP-21160N Table 33. Serial Ports—Enable and Three-State Parameter Min Max Unit Switching Characteristics t Data Enable from External TCLK1 4 ns DDTEN t Data Disable from External TCLK1 10 ns DDTTE t Data Enable from Internal TCLK1 0 ns DDTIN t Data Disable from Internal TCLK1 3 ns DDTTI 1Referenced to drive edge. Table 34. Serial Ports—Internal Clock Parameter Min Max Unit Switching Characteristics t TFS Delay After TCLK (Internally Generated TFS)1 4.5 ns DFSI t TFS Hold After TCLK (Internally Generated TFS)1 –1.5 ns HOFSI t Transmit Data Delay After TCLK1 7.5 ns DDTI t Transmit Data Hold After TCLK1 0 ns HDTI t TCLK/RCLK Width2 0.5t –1.5 0.5t +1.5 ns SCLKIW SCLK SCLK 1Referenced to drive edge. 2For ADSP-21160M, specification is 0.5t –2.5ns (minimum) and 0.5t +2ns (maximum) SCLK SCLK EXTERNALRFSWITHMCE=1,MFD=0 DRIVE SAMPLE DRIVE RCLK t t SFSE/I HOFSE/I RFS t DDTE/I tDDTENFS tHDTE/I DT 1STBIT 2NDBIT t DDTLFSE LATEEXTERNALTFS DRIVE SAMPLE DRIVE TCLK t t HOFSE/I SFSE/I TFS t DDTE/I TDDTENFS t HDTE/I DT 1STBIT 2NDBIT t DDTLFSE Figure 26. Serial Ports—External Late Frame Sync Rev. D | Page 44 of 58 | September 2015

ADSP-21160M/ADSP-21160N Table 35. Serial Ports—External Late Frame Sync Parameter Min Max Unit Switching Characteristics t Data Delay from Late External TFS or External RFS with MCE = 1, 13 ns DDTLFSE MFD = 01 t Data Enable from Late FS or MCE = 1, MFD = 01 1.0 ns DDTENFS 1MCE = 1, TFS enable and TFS valid follow t and t . DDTLFSE DDTENFS DATARECEIVE—INTERNALCLOCK DATARECEIVE—EXTERNALCLOCK DRIVE SAMPLE DRIVE SAMPLE EDGE EDGE EDGE EDGE tSCLKIW tSCLKW RCLK RCLK tDFSE tDFSE tHOFSE tSFSI tHFSI tHOFSE tSFSE tHFSE RFS RFS tSDRI tHDRI tSDRE tHDRE DR DR NOTE:EITHERTHERISINGEDGEORFALLINGEDGEOFRCLK,TCLKCANBEUSEDASTHEACTIVESAMPLINGEDGE. DATATRANSMIT—INTERNALCLOCK DATATRANSMIT—EXTERNALCLOCK DRIVE SAMPLE DRIVE SAMPLE EDGE EDGE EDGE EDGE tSCLKIW tSCLKW TCLK TCLK tDFSI tDFSE tHOFSI tSFSI tHFSI tHOFSE tSFSE tHFSE TFS TFS tDDTI tDDTE tHDTI tHDTE DT DT NOTE:EITHERTHERISINGEDGEORFALLINGEDGEOFRCLK,TCLKCANBEUSEDASTHEACTIVESAMPLINGEDGE. DRIVEEDGE DRIVEEDGE TCLK TCLK/ (EXT) RCLK tDDTEN tDDTTE DT DRIVE DRIVE EDGE EDGE TCLK TCLK/ (INT) tDDTIN RCLK tDDTTI DT Figure 27. Serial Ports Rev. D | Page 45 of 58 | September 2015

ADSP-21160M/ADSP-21160N JTAG Test Access Port and Emulation For JTAG Test Access Port and emulation, see Table36 and Figure28. Table 36. JTAG Test Access Port and Emulation Parameter Min Max Unit Timing Requirements t TCK Period t ns TCK CK t TDI, TMS Setup Before TCK High 5 ns STAP t TDI, TMS Hold After TCK High 6 ns HTAP t System Inputs Setup Before TCK Low1 7 ns SSYS t System Inputs Hold After TCK Low1 18 ns HSYS t TRST Pulsewidth 4t ns TRSTW CK Switching Characteristics t TDO Delay from TCK Low 13 ns DTDO t System Outputs Delay After TCK Low2 30 ns DSYS 1System Inputs = DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0, PA, BRST, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, and RESET. 2System Outputs = DATA63–0, ADDR31–0, MS3–0, RDx, WRx, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF, FLAG3–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, and BMS. t TCK TCK t t STAP HTAP TMS TDI t DTDO TDO t t SSYS HSYS SYSTEM INPUTS t DSYS SYSTEM OUTPUTS Figure 28. JTAG Test Access Port and Emulation Rev. D | Page 46 of 58 | September 2015

ADSP-21160M/ADSP-21160N OUTPUT DRIVE CURRENTS—ADSP-21160M Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. Using the Figure29 shows typical I–V characteristics for the output driv- current specifications (I , I , I , and ers of the ADSP-21160M. The curves represent the current DD-INPEAK DD-INHIGH DD-INLOW I ) from Electrical Characteristics—ADSP-21160M on drive capability of the output drivers as a function of output DD-IDLE Page16 and Electrical Characteristics—ADSP-21160N on voltage. Page18 and the current-versus-operation information in Table37, engineers can estimate the ADSP-21160x DSP’s internal power supply (V ) input current for a specific DDINT 120 application, according to the formula: 100 % Peak  I –TNAm 6800 VDDEXT=3.47VV,D0D°CEXT=3.3V,2V5D°DCEXT=3.13V, %% HLoigwh   I IDDDDDD--I-NIINNLPOHEWIAGKH ERR 40 85°C + % Peak  IDD-IDLE U 20 = I C DDINT )XT 0 The external component of total power dissipation is caused by E DD–20 the switching of output pins. Its magnitude depends on: V (E –40 C • The number of output pins that switch during each SOUR ––8600 VDDEXT=3.47VV,D0D°CEXT=3.3V,25°C cycle(O) –100 VDDEXT=3.13V, • The maximum frequency at which they can switch (f) 85°C –120 • Their load capacitance (C) 0 0.5 1 1.5 2 2.5 3 3.5 SOURCE(VDDEXT)VOLTAGE–V • Their voltage swing (V ) DD and is calculated by: Figure 29. ADSP-21160M Typical Drive Currents P = O × C × V 2 × f EXT DD OUTPUT DRIVE CURRENTS—ADSP-21160N The load capacitance should include the processor’s package capacitance (C ). The switching frequency includes driving the Figure30 shows typical I–V characteristics for the output driv- IN load high and then back low. Address and data pins can drive ers of the ADSP-21160N. The curves represent the current drive high and low at a maximum rate of 1/(2t ). The write strobe capability of the output drivers as a function of output voltage. CK can switch every cycle at a frequency of 1/t . Select pins switch CK at 1/(2t ), but selects can switch on each cycle. CK Example for ADSP-21160N: Estimate P with the following EXT 80 assumptions: VDDEXT=3.47V,–45°C 60 VDDEXT=3.3V,25°C • A system with one bank of external data memory— A m asynchronous RAM (64-bit) – 40 ETN VOH • Four 64K × 16 RAM chips are used, each with a load RR 20 VDDEXT=3.11V,115°C of 10pF U C )T 0 • External data memory writes occur every other cycle, a rate X VDED –20 VDDEXT=3.11V,115°C of 1/(2 tCK), with 50% of the pins switching (E VOL VDDEXT=3.3V,25°C • The bus cycle time is 50MHz (t = 20ns). C CK R –40 SUO The PEXT equation is calculated for each class of pins that –60 can drive, as shown in Table38. –80 VDDEXT=3.47V,–45°C A typical power consumption can now be calculated for these 0 0.5 1 1.5 2 2.5 3 3.5 conditions by adding a typical internal power dissipation: SWEEP(VDDEXT)VOLTAGE–V P = P + P + P TOTAL EXT INT PLL Figure 30. ADSP-21160N Typical Drive Currents where: • P is from Table38 POWER DISSIPATION EXT • P is I × 1.9 V, using the calculation I listed in INT DDINT DDINT Total power dissipation has two components: one due to inter- Power Dissipation on page 47 nal circuitry and one due to the switching of external output • P is AI × 1.9 V, using the value for AI listed in Elec- drivers. PLL DD DD trical Characteristics—ADSP-21160M on Page16 and Electrical Characteristics—ADSP-21160N on Page18 Rev. D | Page 47 of 58 | September 2015

ADSP-21160M/ADSP-21160N Table 37. ADSP-21160x Operation Types vs. Input Current Operation Peak Activity1 High Activity1 Low Activity1 Instruction Type Multifunction Multifunction Single Function Instruction Fetch Cache Internal Memory Internal Memory Core Memory Access2 2 per t Cycle 1 per t Cycle None CK CK (DM 3 64 and PM 3 64) (DM 3 64) Internal Memory DMA 1 per 2 t Cycles 1 per 2 t Cycles None CCLK CCLK External Memory DMA 1 per External Port Cycle (364) 1 per External Port Cycle (3 64) None Data Bit Pattern for Core Worst Case Random N/A Memory Access and DMA 1Peak activity = I , high activity = I , and low activity = I . The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations. DD-INPEAK DD-INHIGH DD-INLOW 2These assume a 2:1 core clock ratio. For more information on ratios and clocks (t and t ), see the timing ratio definitions on page 20. CK CCLK Table 38. External Power Calculations (ADSP-21160N Example) Pin Type No. of Pins % Switching × C × f × V 2 = P DD EXT Address 15 50 × 44.7 pF × 24 MHz × 10.9 V = 0.088 W MS0 1 0 × 44.7 pF × 24 MHz × 10.9 V = 0.000 W WRx 2 × 44.7 pF × 24 MHz × 10.9 V = 0.023 W Data 64 50 × 14.7 pF × 24 MHz × 10.9 V = 0.123 W CLKOUT 1 × 4.7 pF × 48 MHz × 10.9 V = 0.003 W P = 0.237 W EXT Note that the conditions causing a worst-case P are different voltage decaysV from the measured output high or output low EXT from those causing a worst-case P . Maximum P cannot voltage. t is calculated with test loads C and I , and with INT INT DECAY L L occur while 100% of the output pins are switching from all ones V equal to 0.5 V. to all zeros. Note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. TEST CONDITIONS REFERENCE SIGNAL The test conditions for timing parameters appearing in ADSP-21160x specifications on page 17 include output disable t MEASURED time, output enable time, and capacitive loading. tDIS tENA Output Disable Time VOH(MEASURED) Output pins are considered to be disabled when they stop driv- VOH(MEASURED)–(cid:36)V2.0V ing, go into a high-impedance state, and start to decay from VOL(MEASURED)+(cid:36)V1.0V their output high or low voltage. The time for the voltage on the VOL(MEASURED) t DECAY bus to decay by V is dependent on the capacitive load, C and L the load current, I . This decay time can be approximated by the L OUTPUTSTOPS OUTPUTSTARTS following equation: DRIVING DRIVING tDECAY = (CLV)/IL HIGHIMPEDANCESTATE. TESTCONDITIONSCAUSETHISVOLTAGE The output disable time t is the difference between t DIS MEASURED TOBEAPPROXIMATELY1.5V and t as shown in Figure31. The time t is the inter- DECAY MEASURED val from when the reference signal switches to when the output Figure 31. Output Enable/Disable Rev. D | Page 48 of 58 | September 2015

ADSP-21160M/ADSP-21160N Output Enable Time Capacitive Loading Output pins are considered to be enabled when they have made Output delays and holds are based on standard capacitive loads: a transition from a high impedance state to when they start driv- 30pF on all pins (see Figure32). Figure34, Figure35, Figure37, ing. The output enable time t is the interval from when a and Figure38 show how output rise time varies with capaci- ENA reference signal reaches a high or low voltage level to when the tance. Figure36 and Figure39 graphically show how output output has reached a specified high or low trip point, as shown delays and holds vary with load capacitance. (Note that this in the output enable/disable diagram (Figure31). If multiple graph or derating does not apply to output disable delays; see pins (such as the data bus) are enabled, the measurement value Output Disable Time on Page48.) The graphs of Figure34 is that of the first pin to start driving. through Figure39 may not be linear outside the ranges shown. Example System Hold Time Calculation To determine the data output hold time in a particular system, 30 first calculate t using the equation given above. Choose V DECAY to be the difference between the ADSP-21160x DSP’s output 25 voltage and the input threshold for the device requiring the hold s time. A typical V will be 0.4V. CL is the total bus capacitance –nS 20 RISETIME (per data line), and I is the total leakage or three-state current E L M (per data line). The hold time will be t plus the minimum IT Y=0.086687X+2.18 disable time (i.e., tDATRWH for the writeD cEyCcAlYe). FLAL 15 D N FALLTIME A 10 SE Y=0.072781X+1.99 50(cid:54) IR TO OUTPUT 1.5V 5 PIN 0 0 50 100 150 200 30pF LOADCAPACITANCE–pF Figure 34. ADSP-21160M Typical Output Rise Time (10%–90%, V =Max) DDEXT vs. Load Capacitance Figure 32. Equivalent Device Loading for AC Measurements (Includes All Fixtures) 25 INPUT OR 1.5V 1.5V 20 OUTPUT ns RISETIME – ES Y=0.0813x+2.312 M 15 Figure 33. Voltage Reference Levels for AC Measurements (Except Output ILT TBD L Enable/Disable) A FALLTIME F ND 10 A Y=0.0834x+1.0653 E S IR 5 0 0 50 100 150 200 250 LOADCAPACITANCE–pF Figure 35. ADSP-21160M Typical Output Rise Time (10%–90%, V =Min) DDEXT vs. Load Capacitance Rev. D | Page 49 of 58 | September 2015

ADSP-21160M/ADSP-21160N 25 20 20 s 15 s RISETIME n n – – LD ES Y=0.0813x+2.312 O M 15 H 10 IT R L O L ELDAY 5 Y=0.085526X–3.87 FANDA 10 Y=0.083F4AxL+L1T.0IM65E3 T E U S TUP IR 5 O 0 0 –5 0 50 100 150 200 0 50 100 150 200 LOADCAPACITANCE–pF LOADCAPACITANCE–pF Figure 38. ADSP-21160N Typical Output Rise Time (20%–80%, V =Min) Figure 36. ADSP-21160M Typical Output Delay or Hold vs. Load Capacitance DDEXT vs. Load Capacitance (at Max Case Temperature) 12 10 20 18 sn 8 – 16 LD 6 RISETIME O –ns 14 RHO 4 ILTESM 1120 Y=0.0716x+2.9043 LEAYD 2 Y=0.0716x–3.9037 L T FA 8 PU 0 EAND 6 Y=0.075F1AxL+L1T.4IM88E2 TUO –2 S IR 4 –4 0 50 100 150 200 2 LOADCAPACITANCE–pF 0 0 50 100 150 200 LOADCAPACITANCE–pF Figure 39. ADSP-21160N Typical Output Delay or Hold vs. Load Capacitance (at Max Case Temperature) Figure 37. ADSP-21160N Typical Output Rise Time (20%–80%, V =Max) DDEXT vs. Load Capacitance Rev. D | Page 50 of 58 | September 2015

ADSP-21160M/ADSP-21160N ENVIRONMENTAL CONDITIONS Thermal Characteristics The ADSP-21160x DSPs are provided in a 400-Ball PBGA (Plas- tic Ball Grid Array) package. The ADSP-21160x is specified for a case temperature (T ). CASE Toensure that the T data sheet specification is not exceeded, CASE a heatsink and/or an air flow source may be used. Use the cen- terblock of ground pins (for ADSP-21160M, PBGA balls: H8-13, J8-13, K8-13, L8-13, M8-13, N8-13; for ADSP-21160N, PBGA balls: F7-14, G7-14, H7-14, J7-14, K7-14, L7-14, M-14, N7-14, P7-14, R7-15) to provide thermal pathways to the printed circuit board’s ground plane. A heatsink should be attached to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive. T = T +PD  CASE AMB CA • T = Case temperature (measured on top surface CASE ofpackage) • T = Ambient temperature °C AMB • PD = Power dissipation in W (this value depends upon the specific application; a method for calculating PD is shown under Power Dissipation). •  = Value from Table39. CA •  = 6.46°C/W JB Table 39. Airflow Over Package Versus  CA Airflow (Linear Ft./Min.) 0 200 400  (°C/W)1 12.13 9.86 8.7 CA 1 = 3.6 °C/W JC Rev. D | Page 51 of 58 | September 2015

ADSP-21160M/ADSP-21160N 400-BALL PBGA PIN CONFIGURATIONS Table40 lists the pin assignments for the PBGA package, and the pin configurations diagram in Figure40 (ADSP-21160M) and Figure41 (ADSP-21160N) show the pin assignment summary. Table 40. 400-Ball PBGA Pin Assignments (See Footnotes 1 and 2) Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. DATA[14] A01 DATA[22] B01 DATA[24] C01 DATA[28] D01 DATA[13] A02 DATA[16] B02 DATA[18] C02 DATA[25] D02 DATA[10] A03 DATA[15] B03 DATA[17] C03 DATA[20] D03 DATA[8] A04 DATA[9] B04 DATA[11] C04 DATA[19] D04 DATA[4] A05 DATA[6] B05 DATA[7] C05 DATA[12] D05 DATA[2] A06 DATA[3] B06 DATA[5] C06 V D06 DDEXT TDI A07 DATA[0] B07 DATA[1] C07 V D07 DDINT TRST A08 TCK B08 TMS C08 V D08 DDEXT RESET A09 EMU B09 TD0 C09 V D09 DDEXT RPBA A10 IRQ2 B10 IRQ1 C10 V D10 DDEXT IRQ0 A11 FLAG3 B11 FLAG2 C11 V D11 DDEXT FLAG1 A12 FLAG0 B12 NC1 C12 V D12 DDEXT TIMEXP A13 NC1 B13 NC C13 V D13 DDINT NC1 A14 NC B14 TCLK1 C14 V D14 DDEXT NC A15 DT1 B15 DR1 C15 TFS0 D15 TFS1 A16 RCLK1 B16 DR0 C16 L1DAT[7] D16 RFS1 A17 RFS0 B17 L0DAT[7] C17 L0CLK D17 RCLK0 A18 TCLK0 B18 L0DAT[6] C18 L0DAT[3] D18 DT0 A19 L0DAT[5] B19 L0ACK C19 L0DAT[1] D19 L0DAT[4] A20 L0DAT[2] B20 L0DAT[0] C20 L1CLK D20 DATA[30] E01 DATA[34] F01 DATA[38] G01 DATA[40] H01 DATA[29] E02 DATA[33] F02 DATA[35] G02 DATA[39] H02 DATA[23] E03 DATA[27] F03 DATA[32] G03 DATA[37] H03 DATA[21] E04 DATA[26] F04 DATA[31] G04 DATA[36] H04 V E05 V F05 V G05 V H05 DDEXT DDEXT DDEXT DDEXT V E06 V F06 V G06 V H06 DDINT DDINT DDINT DDINT V E07 GND F07 GND G07 GND H07 DDINT V E08 GND F08 GND G08 GND H08 DDINT V E09 GND F09 GND G09 GND H09 DDINT V E10 GND F10 GND G10 GND H10 DDINT GND E11 GND F11 GND G11 GND H11 V E12 GND F12 GND G12 GND H12 DDINT V E13 GND F13 GND G13 GND H13 DDINT V E14 GND F14 GND G14 GND H14 DDINT V E15 V F15 V G15 V H15 DDINT DDINT DDINT DDINT V E16 V F16 V G16 V H16 DDEXT DDEXT DDEXT DDEXT L1DAT[6] E17 L1DAT[4] F17 L1DAT[2] G17 L2DAT[5] H17 L1DAT[5] E18 L1DAT[3] F18 L2DAT[6] G18 L2ACK H18 L1ACK E19 L1DAT[0] F19 L2DAT[4] G19 L2DAT[3] H19 L1DAT[1] E20 L2DAT[7] F20 L2CLK G20 L2DAT[1] H20 Rev. D | Page 52 of 58 | September 2015

ADSP-21160M/ADSP-21160N Table 40. 400-Ball PBGA Pin Assignments (Continued) (See Footnotes 1 and 2) Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. DATA[44] J01 CLK_CFG_0 K01 CLKIN L01 AV M01 DD DATA[43] J02 DATA[46] K02 CLK_CFG_1 L02 CLK_CFG_3 M02 DATA[42] J03 DATA[45] K03 AGND L03 CLKOUT M03 DATA[41] J04 DATA[47] K04 CLK_CFG_2 L04 NC2 M04 V J05 V K05 V L05 V M05 DDEXT DDEXT DDEXT DDEXT V J06 V K06 V L06 V M06 DDINT DDINT DDINT DDINT GND J07 GND K07 GND L07 GND M07 GND J08 GND K08 GND L08 GND M08 GND J09 GND K09 GND L09 GND M09 GND J10 GND K10 GND L10 GND M10 GND J11 GND K11 GND L11 GND M11 GND J12 GND K12 GND L12 GND M12 GND J13 GND K13 GND L13 GND M13 GND J14 GND K14 GND L14 GND M14 V J15 V K15 V L15 V M15 DDINT DDINT DDINT DDINT V J16 V K16 V L16 V M16 DDEXT DDEXT DDEXT DDEXT L2DAT[2] J17 BR6 K17 BR2 L17 PAGE M17 L2DAT[0] J18 BR5 K18 BR1 L18 SBTS M18 HBG J19 BR4 K19 ACK L19 PA M19 HBR J20 BR3 K20 REDY L20 L3DAT[7] M20 NC N01 DATA[49] P01 DATA[53] R01 DATA[56] T01 NC N02 DATA[50] P02 DATA[54] R02 DATA[58] T02 DATA[48] N03 DATA[52] P03 DATA[57] R03 DATA[59] T03 DATA[51] N04 DATA[55] P04 DATA[60] R04 DATA[63] T04 V N05 V P05 V R05 V T05 DDEXT DDEXT DDEXT DDEXT V N06 V P06 V R06 V T06 DDINT DDINT DDINT DDINT GND N07 GND P07 GND R07 V T07 DDINT GND N08 GND P08 GND R08 V T08 DDINT GND N09 GND P09 GND R09 V T09 DDINT GND N10 GND P10 GND R10 V T10 DDINT GND N11 GND P11 GND R11 V T11 DDINT GND N12 GND P12 GND R12 V T12 DDINT GND N13 GND P13 GND R13 V T13 DDINT GND N14 GND P14 GND R14 V T14 DDINT V N15 V P15 GND R15 V T15 DDINT DDINT DDINT V N16 V P16 V R16 V T16 DDEXT DDEXT DDEXT DDEXT L3DAT[5] N17 L3DAT[2] P17 L4DAT[5] R17 L4DAT[3] T17 L3DAT[6] N18 L3DAT[1] P18 L4DAT[6] R18 L4ACK T18 L3DAT[4] N19 L3DAT[3] P19 L4DAT[7] R19 L4CLK T19 L3CLK N20 L3ACK P20 L3DAT[0] R20 L4DAT[4] T20 DATA[61] U01 ADDR[4] V01 ADDR[5] W01 ADDR[8] Y01 DATA[62] U02 ADDR[6] V02 ADDR[9] W02 ADDR[11] Y02 ADDR[3] U03 ADDR[7] V03 ADDR[12] W03 ADDR[13] Y03 ADDR[2] U04 ADDR[10] V04 ADDR[15] W04 ADDR[16] Y04 V U05 ADDR[14] V05 ADDR[17] W05 ADDR[19] Y05 DDEXT V U06 ADDR[18] V06 ADDR[20] W06 ADDR[21] Y06 DDEXT Rev. D | Page 53 of 58 | September 2015

ADSP-21160M/ADSP-21160N Table 40. 400-Ball PBGA Pin Assignments (Continued) (See Footnotes 1 and 2) Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. V U07 ADDR[22] V07 ADDR[23] W07 ADDR[24] Y07 DDEXT V U08 ADDR[25] V08 ADDR[26] W08 ADDR[27] Y08 DDEXT V U09 ADDR[28] V09 ADDR[29] W09 ADDR[30] Y09 DDEXT V U10 ID0 V10 ID1 W10 ADDR[31] Y10 DDEXT V U11 ADDR[1] V11 ADDR[0] W11 ID2 Y11 DDEXT V U12 MS1 V12 BMS W12 BRST Y12 DDEXT V U13 CS V13 MS2 W13 MS0 Y13 DDEXT V U14 RDL V14 CIF W14 MS3 Y14 DDEXT V U15 DMAR2 V15 RDH W15 WRH Y15 DDEXT V U16 L5DAT[0] V16 DMAG2 W16 WRL Y16 DDEXT L5DAT[7] U17 L5DAT[2] V17 LBOOT W17 DMAG1 Y17 L4DAT[0] U18 L5ACK V18 L5DAT[1] W18 DMAR1 Y18 L4DAT[1] U19 L5DAT[4] V19 L5DAT[3] W19 EBOOT Y19 L4DAT[2] U20 L5DAT[6] V20 L5DAT[5] W20 L5CLK Y20 1For ADSP-21160M, Pin Name and function is defined as V . For ADSP-21160N, Pin Name and function is defined as No Connect (NC). DDEXT 2For ADSP-21160M, Pin Name and function is defined as GND. For ADSP-21160N, Pin Name and function is defined as No Connect (NC). Rev. D | Page 54 of 58 | September 2015

ADSP-21160M/ADSP-21160N 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 A B C D E F G H J K L M N P R T U V W Y KEY: 1 VDDINT GND AVDD VDDEXT AGND I/OSIGNALS NOCONNECTION 1 USETHECENTERBLOCKOFGROUNDPINS (PBGABALLS:H8-13,J8-13,K8-13,L8-13, M8-13,N8-13)TOPROVIDETHERMALPATHWAYSTOYOURPRINTEDCIRCUITBOARD’S GROUNDPLANE. Figure 40. ADSP-21160M 400-Ball PBGA Pin Configurations (Bottom View, Summary) Rev. D | Page 55 of 58 | September 2015

ADSP-21160M/ADSP-21160N 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 A B C D E F G H J K L M N P R T U V W Y KEY: 1 VDDINT GND AVDD VDDEXT AGND I/OSIGNALS NOCONNECTION 1 USETHECENTERBLOCKOFGROUNDPINS (PBGABALLS:F7-14,G7-14,H7-14,J7-14, K7-14,L7-14,M7-14,N7-14,P7-14,R7-15)TOPROVIDETHERMALPATHWAYSTOYOUR PRINTEDCIRCUITBOARD’SGROUNDPLANE. Figure 41. ADSP-21160N 400-Ball PBGA Pin Configurations (Bottom View, Summary) Rev. D | Page 56 of 58 | September 2015

ADSP-21160M/ADSP-21160N OUTLINE DIMENSIONS The ADSP-21160x processors are available in a 27 mm × 27 mm, 400-ball PBGA lead-free package. 27.20 BALLA1PADCORNER 27.00SQ 20 18 16 14 12 10 8 6 4 2 26.80 19 17 15 13 11 9 7 5 3 1 BALLA1 INDICATOR A B C D E F G H 24.13 J BSC K SQ L M N 1.27 P BSC R T U V W Y TOPVIEW BOTTOMVIEW 2.49 1.19 2.32 DETAILA 0.60 1.17 2.15 0.55 1.15 0.50 0.70 SEPALTAINNGE 0.90 0.60 0.75 0.50 0.60 BALLDIAMETER 0.20MAX COPLANARITY DETAILA Figure 42. 400-Ball Plastic Grid Array (PBGA) (B-400) Compliant to JEDEC Standards MS-034-BAL-2 (Dimensions in Millimeters) SURFACE-MOUNT DESIGN The following table is provided as an aide to PCB design. Forindustry-standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design andLand Pattern Standard. Package Ball Attach Type Solder Mask Opening Ball Pad Size 400-Ball Grid Array (PBGA) Solder Mask Defined (SMD) 0.63mm diameter 0.76mm diameter Rev. D | Page 57 of 58 | September 2015

ADSP-21160M/ADSP-21160N ORDERING GUIDE Instruction On-Chip Package Model Notes Temperature Range Rate SRAM Package Description Option ADSP-21160MKBZ-80 1 0°C to +85°C 80 MHz 4M bits 400-Ball Plastic Ball Grid Array (PBGA) B-400 ADSP-21160MKB-80 0°C to +85°C 80 MHz 4M bits 400-Ball Plastic Ball Grid Array (PBGA) B-400 ADSP-21160NCBZ-100 1 –40°C to +100°C 100 MHz 4M bits 400-Ball Plastic Ball Grid Array (PBGA) B-400 ADSP-21160NCB-100 –40°C to +100°C 100 MHz 4M bits 400-Ball Plastic Ball Grid Array (PBGA) B-400 ADSP-21160NKBZ-100 1 0°C to +85°C 100 MHz 4M bits 400-Ball Plastic Ball Grid Array (PBGA) B-400 1Z = RoHS Compliant Part. ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02426-0-9/15(D) Rev. D | Page 58 of 58 | September 2015