Product Sample & Technical Tools & Support & Reference Folder Buy Documents Software Community Design ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 ADS8555 16-Bit, Six-Channel, Simultaneous Sampling Analog-to-Digital Converter 1 Features 3 Description • SixSARADCsGroupedinThreePairs The ADS8555 device contains six low-power, 16-bit, 1 successive approximation register (SAR)-based • MaximumDataRatePerChannelWithInternal analog-to-digital converters (ADCs) with true bipolar ClockandReference: inputs. Each channel contains a sample-and-hold 630kSPS(Parallel)or450kSPS(Serial) circuit that allows simultaneous high-speed multi- • MaximumDataRatePerChannelWithExternal channelsignalacquisition. ClockandReference: The ADS8555 device supports data rates of up to 800kSPS(Parallel)or500kSPS(Serial) 630 kSPS in parallel interface mode or up to • Pin-SelectableorProgrammableInputVoltage 450 kSPS if the serial interface is used. The bus Ranges:Upto±12V widthoftheparallelinterfacecanbesettoeightor16 bits. In serial mode, up to three output channels can • ExcellentACPerformance: beactivated. 91.5-dBSNR, –94-dBTHD • ProgrammableandBufferedInternalReference: The ADS8555 device is specified over the extended industrialtemperaturerangeof –40°Cto125°Candis 0.5Vto2.5Vand0.5Vto3V availableinanLQFP-64package. • ComprehensivePower-DownModes: – DeepPowerDown(StandbyMode) DeviceInformation(1) – Auto-NapPowerDown PARTNUMBER PACKAGE BODYSIZE(NOM) • SelectableParallelorSerialInterface ADS8555 LQFP(64) 10.00mm×10.00mm • OperatingTemperatureRange:–40°Cto125°C (1) For all available packages, see the orderable addendum at theendofthedatasheet. • LQFP-64Package BlockDiagram 2 Applications HVDD HVSS AVDD BVDD • PowerQualityMeasurements • ProtectionRelays Clock Generator • Multi-AxisMotorControls CH_A0 SAR ADC • ProgrammableLogicControllers AGND BUSY/INT RANGE/XCLK CONVST_A • IndustrialDataAcquisition Control HW/SW REFC_A Logic REFEN/WR SNRvsTemperature CAHG_NAD1 SAR ADC RSTEBSYET CH_B0 SAR ADC 94 AGND 92 CONVST_B Config 90 REFC_B Register dB) 88 CH_B1 SAR ADC atio ( 86 CAHG_NCD0 e R 84 AGND SAR ADC CS/FS Signal-to-Nois 88772086 AHfSVVIGDSNDASL === -B11V05kDVHD, zH ,= Vf D5DAVTDA == 1M5aVx CORNEVCAFSHGCT_N__CCCD1 SAR ADC I/O RDWPADBOR[1R/5SD:E0/BR]YTE 74 Range =±4´V REF String 2.5V/3V 72 Internal Reference REF_IO DAC REF 70 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) AGND BGND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com Table of Contents 1 Features.................................................................. 1 7.2 FunctionalBlockDiagram.......................................19 2 Applications........................................................... 1 7.3 FeatureDescription.................................................20 3 Description............................................................. 1 7.4 DeviceFunctionalModes........................................25 7.5 RegisterMaps.........................................................29 4 RevisionHistory..................................................... 2 8 ApplicationsandImplementation...................... 31 5 PinConfigurationandFunctions......................... 3 8.1 ApplicationInformation............................................31 6 Specifications......................................................... 6 8.2 TypicalApplication..................................................31 6.1 AbsoluteMaximumRatings......................................6 9 PowerSupplyRecommendations...................... 35 6.2 ESDRatings..............................................................7 10 Layout................................................................... 35 6.3 RecommendedOperatingConditions.......................7 6.4 ThermalInformation..................................................7 10.1 LayoutGuidelines.................................................35 6.5 ElectricalCharacteristics...........................................8 10.2 LayoutExample....................................................36 6.6 SerialInterfaceTimingRequirements.....................11 11 DeviceandDocumentationSupport................. 37 6.7 ParallelInterfaceTimingRequirements(Read 11.1 DocumentationSupport .......................................37 Access)....................................................................11 11.2 CommunityResources..........................................37 6.8 ParallelInterfaceTimingRequirements(Write 11.3 Trademarks...........................................................37 Access)....................................................................11 11.4 ElectrostaticDischargeCaution............................37 6.9 TypicalCharacteristics............................................14 11.5 Glossary................................................................37 7 DetailedDescription............................................ 19 12 Mechanical,Packaging,andOrderable 7.1 Overview.................................................................19 Information........................................................... 37 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(October2015)toRevisionD Page • ChangedFigure36:changedcapacitorvaluesfrom820nFto820pF .............................................................................. 32 ChangesfromRevisionB(February2011)toRevisionC Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection ................................................................................................. 1 ChangesfromRevisionA(January2011)toRevisionB Page • Changeddescriptionofpin18inPinDescriptionstable........................................................................................................ 5 • AddedclarificationofINTinBUSY/INTsection................................................................................................................... 23 • UpdatedTable4................................................................................................................................................................... 28 • ChangedbitC20inTable5.................................................................................................................................................. 30 ChangesfromOriginal(December2010)toRevisionA Page • ChangeddescriptionofCONVST_C,CONVST_B,andCONVST_ApinsinPinDescriptionstable.................................... 5 • ChangeddescriptionofCONVST_xsection........................................................................................................................ 22 • ChangedfirstparagraphofBUSY/INTsection..................................................................................................................... 23 2 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 5 Pin Configuration and Functions PMPackage 64-PinLQFP TopView R B15 EF/WEN W/SW AR/SER VDD GND EFC_C GND EFC_B GND EFC_A GND GND EFIO VDD GND D R H P A A R A R A R A A R A A 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DB14/REFBUFEN 1 48 CH_C1 DB13/SDI 2 47 AVDD DB12 3 46 AVDD DB11 4 45 CH_C0 DB10/SDO_C 5 44 AGND DB9/SDO_B 6 43 AGND DB8/SDO_A 7 42 CH_B1 ADS8555 BGND 8 41 AVDD BVDD 9 40 AVDD DB7/HBEN/DCEN 10 39 CH_B0 DB6/SCLK 11 38 AGND DB5/DCIN_A 12 37 AGND DB4/DCIN_B 13 36 CH_A1 DB3/DCIN_C 14 35 AVDD DB2/SEL_C 15 34 AVDD DB1/SEL_B 16 33 CH_A0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A T S D C B A Y D D K T E S D D _ N F R _ _ _ B N D L E T S D N DB0/SEL BUSY/I CS / CONVST CONVST CONVST ST AG AV ANGE/XC RES WORD/BY HV HV AG R Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com PinFunctions PIN DESCRIPTION TYPE(1) NAME NO. PARALLELINTERFACE(PAR/SER=0) SERIALINTERFACE(PAR/SER=1) Hardwaremode(HW/SW=0): Referencebuffersenableinput. Whenlow,allreferencebuffersareenabled(mandatoryif internalreferenceisused).Whenhigh,allreferencebuffers DB14/REFBUFEN 1 DIO/DI Databit14input/output aredisabled. Softwaremode(HW/SW=1):ConnecttoBGNDorBVDD. ThereferencebuffersarecontrolledbybitC24(REFBUF)in controlregister(CR). Hardwaremode(HW/SW=0):ConnecttoBGND DB13/SDI 2 DIO/DI Databit13input/output Softwaremode(HW/SW=1):Serialdatainput DB12 3 DIO Databit12input/output ConnecttoBGND DB11 4 DIO Databit11input/output ConnecttoBGND WhenSEL_C=1,dataoutputforchannelC DB10/SDO_C 5 DIO/DO Databit10input/output WhenSEL_C=0,tiethispintoBGND WhenSEL_B=1,dataoutputforchannelB WhenSEL_B=0,tiethispintoBGND DB9/SDO_B 6 DIO/DO Databit9input/output WhenSEL_C=0,datafromchannelC1arealsoavailable onthisoutput DataoutputforchannelA WhenSEL_C=0,datafromchannelC0arealsoavailable DB8/SDO_A 7 DIO/DO Databit8input/output onthisoutput WhenSEL_C=0andSEL_B=0,SDO_Aactsasthesingle dataoutputforallchannels BGND 8 P BufferI/Oground,connecttodigitalgroundplane BufferI/Osupply,connecttodigitalsupply(2.7Vto5.5V).Decouplewitha1-μFceramiccapacitorora BVDD 9 P combinationof100-nFand10-μFceramiccapacitorstoBGND. Wordmode(WORD/BYTE=0): Databit7input/output Bytemode(WORD/BYTE=1): Daisy-chainenableinput. DB7/HBEN/DCEN 10 DIO/DI/DI Highbyteenableinput. Whenhigh,DB[5:3]serveasdaisy-chaininputsDCIN[A:C]. Whenhigh,thehighbyteisoutputfirston Ifdaisy-chainmodeisnotused,connecttoBGND. DB[15:8].Whenlow,thelowbyteisoutputfirston DB[15:8]. Wordmode(WORD/BYTE=0): Databit6input/output DB6/SCLK 11 DIO/DI Serialinterfaceclockinput(36MHz,max) Bytemode(WORD/BYTE=1): ConnecttoBGNDorBVDD Wordmode(WORD/BYTE=0): DB5/DCIN_A 12 DIO/DI Databit5input/output WhenDCEN=1,daisy-chaindatainputforchannelA Bytemode(WORD/BYTE=1): WhenDCEN=0,connecttoBGND ConnecttoBGNDorBVDD Wordmode(WORD/BYTE=0): Databit4input/output WhenSEL_B=1andDCEN=1,daisy-chaindatainputfor DB4/DCIN_B 13 DIO/DI channelB Bytemode(WORD/BYTE=1): WhenDCEN=0,connecttoBGND ConnecttoBGNDorBVDD Wordmode(WORD/BYTE=0): Databit3input/output WhenSEL_C=1andDCEN=1,daisy-chaindatainputfor DB3/DCIN_C 14 DIO/DI channelC Bytemode(WORD/BYTE=1): WhenDCEN=0,connecttoBGND ConnecttoBGNDorBVDD Wordmode(WORD/BYTE=0): Databit2input/output SelectSDO_Cinput. DB2/SEL_C 15 DIO/DI Bytemode(WORD/BYTE=1): Whenhigh,SDO_Cisactive.Whenlow,SDO_Cisdisabled. ConnecttoBGNDorBVDD Wordmode(WORD/BYTE=0): Databit1input/output SelectSDO_Binput. DB1/SEL_B 16 DIO/DI Bytemode(WORD/BYTE=1): Whenhigh,SDO_Bisactive.Whenlow,SDO_Bisdisabled. ConnecttoBGNDorBVDD (1) AI=analoginput;AIO=analoginput/output;DI=digitalinput;DO=digitaloutput;DIO=digitalinput/output;andP=powersupply. 4 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 PinFunctions(continued) PIN DESCRIPTION TYPE(1) NAME NO. PARALLELINTERFACE(PAR/SER=0) SERIALINTERFACE(PAR/SER=1) Wordmode(WORD/BYTE=0): Databit0(LSB)input/output SelectSDO_Ainput. DB0/SEL_A 17 DIO/DI Whenhigh,SDO_Aisactive.Whenlow,SDO_Aisdisabled. Bytemode(WORD/BYTE=1): Mustalwaysbehigh. ConnecttoBGNDorBVDD WhenCRbitC21=0(BUSY/INT),converterbusystatusoutput.Transitionshighwhenaconversionstartsand remainshighduringtheentireprocess.Transitionslowwhentheconversiondataofallsixchannelsarelatchedto theoutputregisterandremainslowthereafter. Insequentialmode(SEQ=1intheCR),theBUSYoutputtransitionshighwhenaconversionstartsandgoeslow BUSY/INT 18 DO forasingleconversionclockcycle(tCCLK)wheneverachannelpairconversioncompletes. WhenbitC21=1(BUSY/INTinCR),interruptoutput.Thisbittransitionshighafteraconversioncompletesand goeslowwiththefirstreaddataaccess. ThepolarityofBUSY/INToutputcanbechangedusingbitC20(BUSYL/H)inthecontrolregister. Chipselectinput. Framesynchronization. CS/FS 19 DI/DI Whenlow,theparallelinterfaceisenabled.When ThefallingedgeofFScontrolstheframetransfer. high,theinterfaceisdisabled. Readdatainput. RD 20 DI Whenlow,theparalleldataoutputisenabled. ConnecttoBGND Whenhigh,thedataoutputisdisabled. Hardwaremode(HW/SW=0):ConversionstartofchannelpairC. TherisingedgeofthissignalinitiatessimultaneousconversionofanalogsignalsatinputsCH_C[1:0]. CONVST_C 21 DI Softwaremode(HW/SW=1):ConversionstartofchannelpairCinsequentialmode(CRbitC23=1)only; connecttoBGNDorBVDDotherwise Hardwaremode(HW/SW=0):ConversionstartofchannelpairB. TherisingedgeofthissignalinitiatessimultaneousconversionofanalogsignalsatinputsCH_B[1:0]. CONVST_B 22 DI Softwaremode(HW/SW=1):ConversionstartofchannelpairBinsequentialmode(CRbitC23=1)only; connecttoBGNDorBVDDotherwise Hardwaremode(HW/SW=0):ConversionstartofchannelpairA. TherisingedgeofthissignalinitiatessimultaneousconversionofanalogsignalsatinputsCH_A[1:0]. CONVST_A 23 DI Softwaremode(HW/SW=1):Conversionstartofallselectedchannelsexceptinsequentialmode (CRbitC23=1):ConversionstartofchannelpairAonly Standbymodeinput.Whenlow,theentiredeviceispowereddown(includingtheinternalclockandreference). STBY 24 DI Whenhigh,thedeviceoperatesinnormalmode. 25,32, 37,38, Analogground,connecttoanaloggroundplane 43,44, AGND P Pin25canhaveadedicatedgroundifthedifferencebetweenitspotentialandAGNDisalwayskeptwithin±300 49,52, mV. 53,55, 57,59 26,34, Analogpowersupply(4.5Vto5.5V).Decoupleeachpinwitha100-nFceramiccapacitortoAGND.Usean 35,40, additional10-μFcapacitortoAGNDclosetothedevicebutwithoutcompromisingtheplacementofthesmaller AVDD 41,46, P capacitor.Pin26canhaveadedicatedpowersupplyifthedifferencebetweenitspotentialandAVDDisalways 47,50, keptwithin±300mV. 60 Hardwaremode(HW/SW=0):Inputvoltagerangeselectinput. Whenlow,theanaloginputrangeis±4VREF.Whenhigh,theanaloginputrangeis±2VREF. RANGE/XCLK 27 DI/DIO Softwaremode(HW/SW=1):Externalconversionclockinput,ifCRbitC11(CLKSEL)issethighorinternal conversionclockoutput,ifCRbitC10(CLKOUT_EN)issethigh.Ifnotused,connecttoBVDDorBGND. Resetinput,activehigh.Abortsanyongoingconversions.Resetstheinternalcontrolregisterto0x000003FF.The RESET 28 DI RESETpulsemustbeatleast50nslong. Outputmodeselectioninput. Whenlow,dataaretransferredinwordmodeusing DB[15:0].Whenhigh,dataaretransferredinbyte WORD/BYTE 29 DI ConnecttoBGND modeusingDB[15:8]withthebyteordercontrolled byHBENpinwhentwoaccessesarerequiredfora complete16-bittransfer. Negativesupplyvoltagefortheanaloginputs(–16.5Vto–5V). HVSS 30 P Decouplewitha10-0nFceramiccapacitortoAGNDplacednexttothedeviceanda10-μFcapacitortoAGND closetothedevicebutwithoutcompromisingtheplacementofthesmallercapacitor. Positivesupplyvoltagefortheanaloginputs(5Vto16.5V).Decouplewitha100-nFceramiccapacitortoAGND HVDD 31 P placednexttothedeviceanda10-μFcapacitortoAGNDclosetothedevicebutwithoutcompromisingthe placementofthesmallercapacitor. AnaloginputofchannelA0.TheinputvoltagerangeiscontrolledbyRANGEpininhardwaremodeorCRbitC26 CH_A0 33 AI (RANGE_A)insoftwaremode. AnaloginputofchannelA1.TheinputvoltagerangeiscontrolledbyRANGEpininhardwaremodeorCRbitC26 CH_A1 36 AI (RANGE_A)insoftwaremode. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com PinFunctions(continued) PIN DESCRIPTION TYPE(1) NAME NO. PARALLELINTERFACE(PAR/SER=0) SERIALINTERFACE(PAR/SER=1) AnaloginputofchannelB0.TheinputvoltagerangeiscontrolledbyRANGEpininhardwaremodeorCRbitC27 CH_B0 39 AI (RANGE_B)insoftwaremode. AnaloginputofchannelB1.TheinputvoltagerangeiscontrolledbyRANGEpininhardwaremodeorCRbitC27 CH_B1 42 AI (RANGE_B)insoftwaremode. AnaloginputofchannelC0.TheinputvoltagerangeiscontrolledbyRANGEpininhardwaremodeorCRbitC28 CH_C0 45 AI (RANGE_C)insoftwaremode. AnaloginputofchannelC1.TheinputvoltagerangeiscontrolledbyRANGEpininhardwaremodeorCRbitC28 CH_C1 48 AI (RANGE_C)insoftwaremode. Referencevoltageinput/output(0.5Vto3.025V). REFIO 51 AIO TheinternalreferenceisenabledthroughREFEN/WRpininhardwaremodeorCRbitC25(REFEN)insoftware mode.TheoutputvalueiscontrolledbytheinternalDAC(CRbitsC[9:0]).Connecta470-nFceramicdecoupling capacitorbetweenthispinandpin52. DecouplingcapacitorforreferenceofchannelsA. REFC_A 54 AI Connecta10-μFceramicdecouplingcapacitorbetweenthispinandpin53. DecouplingcapacitorforreferenceofchannelsB. REFC_B 56 AI Connecta10-μFceramicdecouplingcapacitorbetweenthispinandpin55. DecouplingcapacitorforreferenceofchannelsC. REFC_C 58 AI Connecta10-μFceramicdecouplingcapacitorbetweenthispinandpin57. Interfacemodeselectioninput. PAR/SER 61 DI Whenlow,theparallelinterfaceisselected.Whenhigh,theserialinterfaceisenabled. Modeselectioninput. HW/SW 62 DI Whenlow,thehardwaremodeisselectedandthedeviceworksaccordingtothesettingsofexternalpins.When high,thesoftwaremodeisselectedinwhichthedeviceisconfiguredbywritingintothecontrolregister. Hardwaremode(HW/SW=0): Hardwaremode(HW/SW=0): Internalreferenceenableinput. Internalreferenceenableinput. Whenhigh,theinternalreferenceisenabled(the Whenhigh,theinternalreferenceisenabled(thereference referencebuffersaretobeenabled).Whenlow, buffersaretobeenabled).Whenlow,theinternalreference theinternalreferenceisdisabledandanexternal isdisabledandanexternalreferencemustbeappliedat REFEN/WR 63 DI referenceisappliedatREFIO. REFIO. Softwaremode(HW/SW=1):Writeinput. TheparalleldatainputisenabledwhenCSand Softwaremode(HW/SW=1):ConnecttoBGNDorBVDD. WRarelow.Theinternalreferenceisenabledby TheinternalreferenceisenabledbyCRbitC25(REFEN). theCRbitC25(REFEN). DB15 64 DIO Databit15(MSB)input/output ConnecttoBGND 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT Supplyvoltage,HVDDtoAGND –0.3 18 V Supplyvoltage,HVSStoAGND –18 0.3 V Supplyvoltage,AVDDtoAGND –0.3 6 V Supplyvoltage,BVDDtoBGND –0.3 6 V Analoginputvoltage HVSS–0.3 HVDD+0.3 V ReferenceinputvoltagewithrespecttoAGND AGND–0.3 AVDD+0.3 V DigitalinputvoltagewithrespecttoBGND BGND–0.3 BVDD+0.3 V GroundvoltagedifferenceAGNDtoBGND ±0.3 V Inputcurrenttoallpinsexceptsupply –10 10 mA Maximumvirtualjunctiontemperature,T 150 °C J Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions MIN NOM MAX UNIT Supplyvoltage,AVDDtoAGND 4.5 5 5.5 V Low-voltagelevels 2.7 3 3.6 Supplyvoltage,BVDDtoBGND V 5-Vlogiclevels 4.5 5 5.5 Inputrange=±2×V 2×V 16.5 REF REF Inputsupplyvoltage,HVDDtoAGND V Inputrange=±4×V 4×V 16.5 REF REF Inputrange=±2×V –16.5 –2×V REF REF Inputsupplyvoltage,HVSStoAGND V Inputrange=±4×V –16.5 –4×V REF REF Referenceinputvoltage(V ) 0.5 2.5 3 V REF Analoginputs Inputrange=±2×VREF –2×VREF 2×VREF V (alsoseetheAnalogInputssection) Inputrange=±4×V –4×V 4×V REF REF REF Operatingambienttemperature,T –40 125 °C A 6.4 Thermal Information ADS8555 THERMALMETRIC(1) PM(LQFP) UNIT 64PINS R Junction-to-ambientthermalresistance 48 °C/W θJA R Junction-to-case(top)thermalresistance 16 °C/W θJC(top) R Junction-to-boardthermalresistance N/A °C/W θJB ψ Junction-to-topcharacterizationparameter N/A °C/W JT ψ Junction-to-boardcharacterizationparameter N/A °C/W JB R Junction-to-case(bottom)thermalresistance N/A °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com 6.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerangeof–40°Cto125°C,AVDD=4.5Vto5.5V,BVDD=2.7Vto5.5V, HVDD=10Vto15V,HVSS=–15Vto–10V,V =2.5V(internal),andf =maximum(unlessotherwisenoted) REF DATA PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT DCACCURACY Resolution 16 Bits Nomissingcodes 16 Bits AtTA=–40°Cto85°C –3 ±1.5 3 Integrallinearityerror INL LSB AtTA=–40°Cto125°C –4 ±1.5 4 AtTA=–40°Cto85°C –1 ±0.75 1.5 Differentiallinearityerror DNL LSB AtTA=–40°Cto125°C –1 ±0.75 2 Offseterror –4 ±0.8 4 mV Offseterrordrift ±3.5 μV/°C Gainerror ReferencedtovoltageatREFIO –0.75 ±0.25 0.75 %FSR Gainerrordrift ReferencedtovoltageatREFIO ±6 ppm/°C Power-supplyrejectionratio PSRR AtoutputcodeFFFFh,relatedtoAVDD 60 dB SAMPLINGDYNAMICS Acquisitiontime tACQ 280 ns ConversiontimeperADC tCONV 1.26 μs 18.5 tCCLK Internalconversionclockperiod tCCLK 68 ns Parallelinterface,internalclockandreference 630 Throughputrate fDATA kSPS Serialinterface,internalclockandreference 450 ACACCURACY AtfIN=10kHz,TA=–40°Cto85°C 90 91.5 Signal-to-noiseratio SNR dB AtfIN=10kHz,TA=–40°Cto125°C 89 91.5 AtfIN=10kHz,TA=–40°Cto85°C 87 89.5 Signal-to-noiseratio+distortion SINAD dB AtfIN=10kHz,TA=–40°Cto125°C 86.5 89.5 Totalharmonicdistortion(2) THD AtfIN=10kHz,TA=–40°Cto85°C –94 –90 dB AtfIN=10kHz,TA=–40°Cto125°C –94 –89.5 AtfIN=10kHz,TA=–40°Cto85°C 90 95 Spurious-freedynamicrange SFDR dB AtfIN=10kHz,TA=–40°Cto125°C 89.5 95 Channel-to-channelisolation AtfIN=10kHz 100 dB Inputrange=±4×VREF 48 –3-dBsmall-signalbandwidth MHz Inputrange=±2×VREF 24 ANALOGINPUT RANGEpin,RANGEbit=0 –4×VREF 4×VREF Bipolarfull-scalerange CHXX V RANGEpin,RANGEbit=1 –2×VREF 2×VREF Inputrange=±4×VREF 10 Inputcapacitance pF Inputrange=±2×VREF 20 Inputleakagecurrent Noongoingconversion ±1 μA Aperturedelay 5 ns Aperturedelaymatching CommonCONVSTforallchannels 250 ps Aperturejitter 50 ps EXTERNALCLOCKINPUT(XCLK) Externalclockfrequency fXCLK AnexternalreferencemustbeusedforfXCLK>fCCLK 1 18 20 MHz Externalclockdutycycle 45% 55% (1) AllvaluesareatT =25°C. A (2) Calculatedonthefirstnineharmonicsoftheinputfrequency. 8 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 Electrical Characteristics (continued) overrecommendedoperatingfree-airtemperaturerangeof–40°Cto125°C,AVDD=4.5Vto5.5V,BVDD=2.7Vto5.5V, HVDD=10Vto15V,HVSS=–15Vto–10V,V =2.5V(internal),andf =maximum(unlessotherwisenoted) REF DATA PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT REFERENCEVOLTAGEOUTPUT(REFOUT) 2.5-Voperation,REFDAC=0x3FF 2.485 2.5 2.515 2.5-Voperation,REFDAC=0x3FFat25°C 2.496 2.5 2.504 Referencevoltage VREF V 3-Voperation,REFDAC=0x3FF 2.985 3 3.015 3-Voperation,REFDAC=0x3FFat25°C 2.995 3 3.005 Referencevoltagedrift dVREF/dT ±10 ppm/°C Power-supplyrejectionratio PSRR 73 dB Outputcurrent IREFOUT Withdccurrent –2 2 mA Shortcircuitcurrent(3) IREFSC 50 mA Turnonsettlingtime tREFON 10 ms AtCREF_xpins 4.7 10 μF Externalloadcapacitance AtREFIOpins 100 470 nF Tuningrange REFDAC Internalreferenceoutputvoltagerange 0.2×VREF VREF V REFDACresolution 10 Bits REFDACdifferentialnonlinearity DNLDAC –1 ±0.1 1 LSB REFDACintegralnonlinearity INLDAC –2 ±0.1 2 LSB REFDACoffseterror VOSDAC VREF=0.5V(DAC=0x0CC) –4 ±0.65 4 LSB REFERENCEVOLTAGEINPUT(REFIN) Referenceinputvoltage VREFIN 0.5 2.5 3.025 V Inputresistance 100 MΩ Inputcapacitance 5 pF Referenceinputcurrent 1 μA SERIALCLOCKINPUT(SCLK) Serialclockinputfrequency fSCLK 0.1 36 MHz Serialclockperiod tSCLK 0.0278 10 μs Serialclockdutycycle 40% 60% DIGITALINPUTS(4) Logicfamily CMOSwithSchmitt-Trigger High-levelinputvoltage 0.7×BVDD BVDD+0.3 V Low-levelinputvoltage BGND–0.3 0.3×BVDD V Inputcurrent VI=BVDDtoBGND –50 50 nA Inputcapacitance 5 pF DIGITALOUTPUTS(4) Logicfamily CMOS High-leveloutputvoltage IOH=100μA BVDD–0.6 BVDD V Low-leveloutputvoltage IOH=–100μA BGND BGND+0.4 V High-impedance-stateoutputcurrent –50 50 nA Outputcapacitance 5 pF Loadcapacitance 30 pF (3) Referenceoutputcurrentisnotlimitedinternally. (4) Specifiedbydesign. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com Electrical Characteristics (continued) overrecommendedoperatingfree-airtemperaturerangeof–40°Cto125°C,AVDD=4.5Vto5.5V,BVDD=2.7Vto5.5V, HVDD=10Vto15V,HVSS=–15Vto–10V,V =2.5V(internal),andf =maximum(unlessotherwisenoted) REF DATA PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT POWER-SUPPLYREQUIREMENTS Analogsupplyvoltage AVDD 4.5 5 5.5 V BufferI/Osupplyvoltage BVDD 2.7 3 5.5 V Inputpositivesupplyvoltage HVDD 5 10 16.5 V Inputnegativesupplyvoltage HVSS –16.5 –10 –5 V fDATA=maximum 30 36 fDATA=250kSPS(auto-NAPmode) 14 16.5 mA Analogsupplycurrent(5) IAVDD Auto-NAPmode,noongoingconversion, 4 6 internalconversionclock Power-downmode 0.1 50 μA fDATA=maximum 0.9 2 mA fDATA=250kSPS(auto-NAPmode) 0.5 1.5 BufferI/Osupplycurrent(6) IBVDD Auto-NAPmode,noongoingconversion, 0.1 10 internalconversionclock μA Power-downmode 0.1 10 fDATA=maximum 3 3.5 mA fDATA=250kSPS(auto-NAPmode) 1.6 2 Inputpositivesupplycurrent(7) IHVDD Auto-NAPmode,noongoingconversion, 0.2 0.3 internalconversionclock μA Power-downmode 0.1 10 fDATA=maximum 3.6 4 mA fDATA=250kSPS(auto-NAPmode) 1.8 2.2 Inputnegativesupplycurrent(8) IHVSS Auto-NAPmode,noongoingconversion, 0.2 0.25 internalconversionclock μA Power-downmode 0.1 10 fDATA=maximum 251.7 298.5 fDATA=250kSPS(auto-NAPmode) 122.5 150 mW Powerdissipation(9) Auto-NAPmode,noongoingconversion, 26 38.3 internalconversionclock Power-downmode 3.8 580 μW (5) AtAVDD=5V. (6) AtBVDD=3V,parallelmode,loadcapacitance=6pFperpin. (7) AtHVDD=15V. (8) AtHVSS=–15V. (9) AtAVDD=5V,BVDD=3V,HVDD=15V,andHVSS=–15V. 10 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 6.6 Serial Interface Timing Requirements overrecommendedoperatingfree-airtemperaturerangeat–40°Cto125°C,AVDD=5V,andBVDD=2.7Vto5.5V(unless otherwisenoted)(1) MIN MAX UNIT t Acquisitiontime 280 ns ACQ t Conversiontime 1.26 µs CONV t CONVST_xlowtime 20 ns 1 t BUSYlowtoFSlowtime 0 ns 2 t Busaccessfinishedtonextconversionstarttime 40 ns 3 t CONVST_xhightoBUSYhighdelay 5 20 ns D1 t FSlowtoSDO_xactivedelay 5 12 ns D2 t SCLKrisingedgetonewdatavaliddelay 15 ns D3 t FShightoSDO_x3-statedelay 10 ns D4 t InputdatatoSCLKfallingedgeholdtime 5 ns H1 t OutputdatatoSCLKrisingedgeholdtime 5 ns H2 t InputdatatoSCLKfallingedgesetuptime 3 ns S1 t CONVST_xhightoXCLKfallingorrisingedgesetuptime 6 ns S3 t Serialclockperiod 0.0278 10 μs SCLK (1) Allinputsignalsarespecifiedwitht =t =1.5ns(10%to90%ofBVDD)andtimedfromavoltagelevelof(V +V )/2. R F IL IH 6.7 Parallel Interface Timing Requirements (Read Access) overrecommendedoperatingfree-airtemperaturerangeat–40°Cto125°C,AVDD=5V,andBVDD=2.7Vto5.5V(unless otherwisenoted)(1) MIN MAX UNIT t Acquisitiontime 280 ns ACQ t Conversiontime 1.26 µs CONV t CONVST_xlowtime 20 ns 1 t BUSYlowtoCSlowtime 0 ns 2 t Busaccessfinishedtonextconversionstarttime(2) 40 ns 3 t CSlowtoRDlowtime 0 ns 4 t RDhightoCShightime 0 ns 5 t RDpulsewidth 30 ns 6 t Minimumtimebetweentworeadaccesses 10 ns 7 t CONVST_xhightoBUSYhighdelay 5 20 ns D1 t RDfallingedgetooutputdatavaliddelay 20 ns D5 t OutputdatatoRDrisingedgeholdtime 5 ns H3 (1) Allinputsignalsarespecifiedwitht =t =1.5ns(10%to90%ofBVDD)andtimedfromavoltagelevelof(V +V )/2. R F IL IH (2) RefertotheCSsignalorRD,whicheveroccursfirst. 6.8 Parallel Interface Timing Requirements (Write Access) overrecommendedoperatingfree-airtemperaturerangeat–40°Cto125°C,AVDD=5V,andBVDD=2.7Vto5.5V(unless otherwisenoted)(1) MIN MAX UNIT t CSlowtoWRlowtime 0 ns 8 t WRlowpulseduration 15 ns 9 t WRhighpulseduration 10 ns 10 t WRhightoCShightime 0 ns 11 t OutputdatatoWRrisingedgesetuptime 5 ns S2 t DataoutputtoWRrisingedgeholdtime 5 ns H4 (1) Allinputsignalsarespecifiedwitht =t =1.5ns(10%to90%ofBVDD)andtimedfromavoltagelevelof(V +V )/2. R F IL IH Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com XCLK (C11 = 1) t tS3 t1 S3 CONVST_x t t CONV ACQ t D1 BUSY (C20 = C21 = 0) t2 t3 FS t SCLK SCLK 1 32 t t D3 D4 t t D2 H2 ADS8556 CH_x0 CH_x1 CH_x1 CH_x1 CH_x1 SDO_x MSB D3 D2 D1 LSB t H1 t S1 SDI or Don’t Don’t Care D31 D3 D2 D1 D0 DCIN_x Care Figure1. SerialOperationTimingDiagram(AllThreeSDOsActive) t 1 CONVST_A CONVST_B CONVST_C t CONV t t ACQ D1 BUSY (C20 = C21 = 0) t t 2 3 CS t4 t5 t6 t7 RD t t D5 H3 CH CH CH CH CH CH DB[15:0] A0 A1 B0 B1 C0 C1 Figure2. ParallelReadAccessTimingDiagram 12 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 CS t9 t10 t t 8 11 WR t S2 t H4 C C Don’t C C C C DB[15:0] [31:16] [15:0] Care [31:24] [23:16] [15:8] [7:0] Word Mode ByteMode (WORD/BYTE = 0) (WORD/BYTE = 1) Figure3. ParallelWriteAccessTimingDiagram Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com 6.9 Typical Characteristics at25°C,overentiresupplyvoltagerange,V =2.5V(internal),andf =maximum(unlessotherwisenoted) REF DATA 3.0 3.0 2.5 2.5 B) 2.0 B) 2.0 S 1.5 S 1.5 L L y ( 1.0 y ( 1.0 arit 0.5 arit 0.5 e e nlin 0 nlin 0 No -0.5 No-0.5 al -1.0 al -1.0 gr gr e -1.5 e-1.5 nt nt I -2.0 I-2.0 -2.5 -2.5 -3.0 -3.0 0 8190 16380 24570 32760 40950 49140 57330 65520 0 8190 16380 24570 32760 40950 49140 57330 65520 Code Code Figure4.INLvsCode(±10-V Range) Figure5.INLvsCode(±5-V Range) IN IN 1.5 1.5 SB) 1.0 SB) 1.0 L L earity ( 0.5 earity ( 0.5 n n nli nli o o N N al 0 al 0 nti nti e e er er Diff -0.5 Diff-0.5 -1.0 -1.0 0 8190 16380 24570 32760 40950 49140 57330 65520 0 8190 16380 24570 32760 40950 49140 57330 65520 Code Code Figure6.DNLvsCode(±10-V Range) Figure7.DNLvsCode(±5-V Range) IN IN 4 0.75 3 0.50 2 mV) 1 %) 0.25 or ( or ( Err 0 Err 0 Offset -1 Gain -0.25 -2 -0.50 -3 -4 -0.75 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Temperature (°C) Figure8.OffsetErrorvsTemperature Figure9.GainErrorvsTemperature 14 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 Typical Characteristics (continued) at25°C,overentiresupplyvoltagerange,V =2.5V(internal),andf =maximum(unlessotherwisenoted) REF DATA -30 1.40 B) 1.35 o (d -40 1.30 ati s) R m 1.25 Supply Rejection ---567000 Conversion Time ( 1111....21100505 wer- -80 1.00 Po 0.95 -90 0.90 0 20 40 60 80 100 120 140 160 180 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 AVDD Noise Frequency (kHz) Temperature (°C) Figure10.PSRRvsAVDDNoiseFrequency Figure11.ConversionTimevsTemperature 5500 94 5000 92 s 4500 B) 90 e d 88 Number of Occurrenc 433221050505000000000000 Signal-to-Noise Ratio ( 888877642086 AHfSVVIGDSNDASL === -B11V05kDVHD, zH ,= Vf D5DAVTDA == 1M5aVx 74 Range =±4´V 1000 REF 72 Internal Reference 500 70 -3 -2 -1 0 1 2 -40 -25 -10 5 20 35 50 65 80 95 110 125 Code Temperature (°C) Figure12.CodeHistogram(8192Hits) Figure13.SNRvsTemperature B) 94 -86 AVDD = BVDD = 5V, HVSS =-15V, HVDD = 15V nd Distortion (d 9988820864 stortion (dB) --8980 fSIGNAL= 10kHz, fDATA= Max, RInatenrgnea =l R±e4fe´reVnRcEeF atio a 82 nic Di -92 R 80 o oise 78 AHVVDSDS == -B1V5DVD, H =V 5DVD = 15V Harm -94 gnal-to-N 777642 fRISnaItGenNrgnAeLa l== R 1±e04fke´HreVzn,R cfEeDFATA= Max Total -96 Si 70 -98 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Temperature (°C) Figure14.SINADvsTemperature Figure15.THDvsTemperature Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com Typical Characteristics (continued) at25°C,overentiresupplyvoltagerange,V =2.5V(internal),andf =maximum(unlessotherwisenoted) REF DATA 100 0 B) -20 d 98 ge ( -40 an 96 c R B) -60 e Dynami 9942 plitude (d -1-0800 s-Fre 90 HVSS =A-V1D5DV, =H BVVDDDD = = 1 55VV Am -120 uriou 88 fSIGNAL= 1R0aknHgze, =fD±AT4A´= VMax -140 p REF S Internal Reference -160 86 -180 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 25 50 75 100 125 150 175 200 225 250 Temperature (°C) Frequency (kHz) f =10kHz IN Figure16.SFDRvsTemperature Figure17.FrequencySpectrum (2048-PointFFT,±10-V Range) IN 0 120 -20 115 -40 110 dB) -60 B) 105 ude ( -80 on (d 100 Amplit --110200 Isolati 95 90 -140 -160 85 -180 80 0 25 50 75 100 125 150 175 200 225 250 0 30 60 90 120 150 180 210 240 270 300 Frequency (kHz) Noise Frequency (kHz) f =10kHz IN Figure18.FrequencySpectrum Figure19.Channel-to-ChannelIsolationvs (2048-PointFFT,±5-V Range) InputNoiseFrequency IN 2.504 2.504 2.503 2.503 2.502 2.502 2.501 2.501 V) V V) ( REF ( EF 2.500 EF 2.500 R R V V 2.499 2.499 2.498 2.498 2.497 2.497 2.496 2.496 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 AVDD (V) Temperature (°C) Figure20.InternalReferenceVoltagevsAnalogSupply Figure21.InternalReferenceVoltagevsTemperature Voltage(2.5-VMode) (2.5-VMode) 16 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 Typical Characteristics (continued) at25°C,overentiresupplyvoltagerange,V =2.5V(internal),andf =maximum(unlessotherwisenoted) REF DATA 3.005 36 3.004 34 3.003 32 fDATA= Max 30 3.002 28 V) 3.001 mA) 26 (REF 3.000 DD ( 2242 V 2.999 AV 20 I 2.998 18 2.997 16 14 2.996 f = 250kSPS (A-NAP) 12 DATA 2.995 10 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Temperature (°C) Figure22.InternalReferenceVoltagevsTemperature Figure23.AnalogSupplyCurrentvsTemperature (3-VMode) 36 2.0 34 32 1.8 30 Normal Operation 28 1.6 26 mA) 2242 mA) 11..42 DD ( 2108 DD ( 1.0 fDATA= Max V 16 V A B I 14 I 0.8 12 10 A-NAPMode 0.6 8 6 0.4 fDATA= 250kSPS (A-NAP) 4 2 0.2 0 45 90 135180225270315360405450495540585630 -40 -25 -10 5 20 35 50 65 80 95 110 125 Sample Rate (kSPS) Temperature (°C) Figure24.AnalogSupplyCurrentvsDataRate Figure25.BufferI/OSupplyCurrentvsTemperature 4.00 4.5 3.75 IHVSS (fDATA= Max) 4.0 A) 3.50 A) 3.5 IHVSS (fDATA= Max) m 3.25 m Input Supply Current ( 3222211.......07520750505050 IIIHHHVVVSDDSDD (((22fD55A00TkkASS=PP MSSaAAx--)NNAAPP)) Input Supply Current ( 32211.....05050 IHVDD (fDATA= Max) IHVSS (250kSPS A-NAP) 0.5 1.25 IHVDD (250kSPS A-NAP) 1.00 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 5 6 7 8 9 10 11 12 13 14 15 Temperature (°C) HVDD, |HVSS| (V) Figure26.InputSupplyCurrentvsTemperature Figure27.InputSupplyCurrentvsInputSupplyVoltage Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com Typical Characteristics (continued) at25°C,overentiresupplyvoltagerange,V =2.5V(internal),andf =maximum(unlessotherwisenoted) REF DATA 3.6 IHVSS 3.3 3.0 IHVSS (A-NAP) 2.7 2.4 A) m 2.1 x ( 1.8 IHVDD (A-NAP) x V H 1.5 I IHVDD 1.2 0.9 0.6 0.3 0 0 90 180 270 360 450 540 630 Data Rate (kSPS) Figure28.InputSupplyCurrentvsDataRate 18 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 7 Detailed Description 7.1 Overview The ADS8555 device includes six 16-bit analog-to-digital converters (ADCs) that operate based on the successive approximation register (SAR) principle. The architecture is designed on the charge redistribution principle that inherently includes a sample-and-hold function. The six analog inputs are grouped into three channel pairs. These channel pairs can be sampled and converted simultaneously, preserving the relative phase information of the signals of each pair. Separate conversion start signals allow simultaneous sampling on each channelpair,onfourchannelsoronallsixchannels. These devices accept single-ended, bipolar analog input signals in the selectable ranges of ±4 V or ±2 V REF REF withanabsolutevalueofupto ±12V;seetheAnalogInputssectionformoredetails. The devices offer an internal 2.5-V, 3-V reference source followed by a 10-bit, digital-to-analog converter (DAC) thatallowsthereferencevoltageV tobeadjustedin2.44-mVor2.93-mVsteps,respectively. REF The ADS8555 device also offers a selectable parallel or serial interface that can be used in hardware or software mode;seetheDeviceConfigurationsectionfordetails. 7.2 Functional Block Diagram HVDD HVSS AVDD BVDD Clock Generator CH_A0 SAR ADC AGND BUSY/INT RANGE/XCLK CONVST_A Control HW/SW REFC_A Logic REFEN/WR CH_A1 STBY SAR ADC AGND RESET CH_B0 SAR ADC AGND CONVST_B Config Register REFC_B CH_B1 SAR ADC AGND CH_C0 AGND SAR ADC CS/FS RD CONVST_C I/O DB[15:0] REFC_C WORD/BYTE CH_C1 SAR ADC PAR/SER AGND String 2.5V/3V REF_IO DAC REF AGND BGND Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com 7.3 Feature Description 7.3.1 Analog This section addresses the analog input circuit, the ADCs and control signals, and the reference design of the device. 7.3.1.1 AnalogInputs The inputs and the converters are of the single-ended, bipolar type. The absolute voltage range can be selected using the RANGE pin (in hardware mode) or RANGE_x bits (in software mode) in the control register (CR, see Table 5) to either ±4 V or ±2 V . With the reference set to 2.5 V (CR bit C18 = 0), the input voltage range REF REF can be ±10 V or ±5 V. With the reference source set to 3 V (CR bit C18 = 1), an input voltage range of ±12 V or ±6 V can be configured. The logic state of the RANGE pin is latched with the falling edge of BUSY (if CR bit C20 =0). The input current on the analog inputs depends on the actual sample rate, input voltage, and signal source impedance. Essentially, the current into the analog inputs charges the internal capacitor array only during the sampling period (t ). The source of the analog input voltage must be able to charge the input capacitance of ACQ 10 pF in ±4-V mode or 20 pF in ±2-V mode to a 12-, 14-, 16-bit accuracy level within the acquisition time REF REF of280nsatmaximumdatarate,asshowninFigure29. Input range:±2V Input range:±4V REF REF R = 200W R = 130W R = 200W R = 130W SER SW SER SW CH_XX CH_XX C = 20pF C = 10pF S S CPAR= 5pF VDC CPAR= 5pF VDC C = 20pF C = 10pF S S AGND AGND R = 200W R = 130W R = 200W R = 130W SER SW SER SW Figure29. EquivalentInputCircuits Duringtheconversionperiod,thereisnofurtherinputcurrentflowandtheinputimpedanceisgreaterthan1MΩ. To ensure a defined start condition, the sampling capacitors of the ADS8555 device are precharged to a fixed internalvoltage,beforeswitchingintosamplingmode. To maintain the linearity of the converter, the inputs must always remain within the specified range of HVSS – 0.2VtoHVDD+0.2V. Theminimum–3-dBbandwidthofthedrivingoperationalamplifiercanbecalculatedusingEquation1: ln(2)´(n + 1) f = -3dB 2p´t ACQ where • n=16(nistheresolutionofthedevice) (1) With a minimum acquisition time of t = 280 ns, the required minimum bandwidth of the driving amplifier is 6.7 ACQ MHz. The required bandwidth can be lower if the application allows a longer acquisition time. A gain error occurs ifagivenapplicationdoesnotfulfillthebandwidthrequirementshowninEquation1. 20 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 Feature Description (continued) A driving operational amplifier may not be required if the impedance of the signal source (R ) fulfills the SOURCE requirementofEquation2: t R < ACQ -(R + R ) SOURCE C ln(2)´(n + 1) SER SW S where • n=16(nistheresolutionoftheADC) • C =10pFisthesamplecapacitorvalueforV =±4×V mode S IN REF • R =200Ωistheinputresistorvalue SER • R =130Ωistheswitchresistancevalue (2) SW With t = 280 ns, the maximum source impedance must be less than 2 kΩ in V = ±4-V mode or less than ACQ IN REF 0.9 kΩ in V = ±2-V mode. The source impedance can be higher if the application allows longer acquisition IN REF time. 7.3.1.2 Analog-to-DigitalConverter(ADC) The devices include six ADCs that operate with either an internal or an external conversion clock. The conversion time is 1.26 μs with the internal conversion clock. When an external clock and reference are used, theminimumconversiontimeis925ns. 7.3.1.3 ConversionClock The device uses either an internally-generated or an external (XCLK) conversion clock signal (in software mode only). In default mode, the device generates an internal clock. When the CLKSEL bit is set high (bit C11 in Table 5), an external conversion clock of up to 20 MHz (maximum) can be applied on pin 27. In both cases, 18.5 clock cycles are required for a complete conversion including the precharging of the sample capacitors. The externalclockcanremainlowbetweenconversions. The conversion clock duty cycle must be 50%. However, the ADS8555 device functions properly with a duty cyclefrom45%to55%. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com Feature Description (continued) 7.3.1.4 CONVST_x The analog inputs of each channel pair (CH_x0, CH_x1) are held with the rising edge of the corresponding CONVST_x signal. Only in software mode (except sequential mode), CONVST_A is used for all six ADCs. The conversionautomaticallystartswiththenextedgeoftheconversionclock. A conversion start must not be issued during an ongoing conversion on the same channel pair. However, conversionsareallowedtobeinitiatedonotherinputpairs;seetheSequentialModesectionformoredetails. If a parallel interface is used, the behavior of the output port depends on which CONVST_x signals are issued. Figure30showsexamplesofdifferentscenarios. BUSY (C20 = C21 = 0) CS CONVST_A CONVST_C CONVST_B RD CH CH CH CH CH CH CH DB[15:0] A0 A1 C0 C1 A0 A1 C0 CONVST_B CONVST_A CONVST_B RD CH CH CH CH CH CH CH DB[15:0] B0 B1 B0 B1 B0 B1 B0 NOTE: Boxedareasindicatetheminimumrequiredframetoacquirealldata. Figure30. DataOutputvsCONVST_x 22 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 Feature Description (continued) 7.3.1.5 BUSY/INT The BUSY signal indicates if a conversion is in progress. The BUSY signal goes high with a rising edge of any CONVST_x signal and goes low when the output data of the last channel pair are available in the respective outputregister.ThereadoutofthedatacanbeinitiatedimmediatelyafterthefallingedgeofBUSY. In sequential mode, the BUSY signal goes low only for one clock cycle; see the Sequential Mode section for moredetails. TheINToutputgoeshighatcompletionofaconversionprocessandremainshighafterfirstreaddataaccess. ThepolarityoftheBUSY/INTsignalcanbechangedusingTable5bitC20. 7.3.1.6 Reference The ADS8555 device provides an internal, low-drift, 2.5-V reference source. To increase the input voltage range, the reference voltage can be switched to 3-V mode using the VREF bit (bit C18 in the CR). The reference feeds a 10-bit string-DAC controlled by bits C[9:0] in the control register. The buffered DAC output is connected to the REFIO pin. In this way, the voltage at this pin is programmable in 2.44 mV (2.92 mV in 3-V mode) steps and adjustable to the application needs without additional external components. The actual output voltage can be calculatedusingEquation3: Range´(Code + 1) V = REF 1024 where • Range=thechosenmaximumreferencevoltageoutputrange(2.5Vor3V) • Code=thedecimalvalueoftheDACregistercontent (3) Table 1 lists some examples of internal reference DAC settings with a reference range set to 2.5 V. However, to ensureproperperformance,theDACoutputvoltageshouldnotbeprogrammedbelow0.5V. Decouple the buffered output of the DAC with a 100-nF capacitor (minimum); for best performance, TI recommends a 470-nF capacitor. If the internal reference is placed into power-down (default), an external referencevoltagecandrivetheREFIOpin. The voltage at the REFIO pin is buffered with three internal amplifiers, one for each ADC pair. The output of each buffer must be decoupled with a 10-μF capacitor between pin pairs 53 and 54, 55 and 56, and 57 and 58. The10-μFcapacitorsareavailableasceramic0805-SMDcomponentsandinX5Rquality. The internal reference buffers can be powered down to decrease the power dissipation of the device. In this case, external reference drivers can be connected to REFC_A, REFC_B, and REFC_C pins. With 10-μF decouplingcapacitors,theminimumrequiredbandwidthcanbecalculatedusingEquation4. ln(2) f = -3dB 2p´t CONV (4) Withtheminimumt of1.26 μs,theexternalreferencebuffersrequireaminimumbandwidthof88kHz. CONV Table1.DACSettingExamples(2.5-VOperation) V DECIMAL BINARY HEXADECIMAL REFOUT (V) CODE CODE CODE 0.5 204 0011001100 CC 1.25 511 0111111111 1FF 2.5 1023 1111111111 3FF Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com 7.3.2 Digital Thissectiondescribesthedigitalcontrolandthetimingofthedeviceindetail. 7.3.2.1 DeviceConfiguration Depending on the desired mode of operation, the ADS8555 device can be configured using the external pins or thecontrolregister(seeTable5),asshowninTable2. Table2.ADS8555ConfigurationSettings HARDWAREMODE(HW/SW=0) SOFTWAREMODE(HW/SW=1) CONVERSIONSTARTCONTROLLEDBYSEPARATE CONVERSIONSTARTCONTROLLEDBYCONVST_A INTERFACEMODE CONVST_xPINS PINONLY,EXCEPTINSEQUENTIALMODE ConfigurationusingcontrolregisterbitsC[31:0]only; Parallel Configurationusingpins,optionally,controlbitsC[22:18], statusofpins27(onlyifusedasRANGEinput)and63is (PAR/SER=0) C[15:13],andC[9:0] disregarded ConfigurationusingcontrolregisterbitsC[31:0]only; statusofpins1,27(onlyifusedasRANGEinput),and Serial Configurationusingpins,optionally,controlbitsC[22:18], 63isdisregarded;eachaccessrequiresacontrolregister (PAR/SER=1) C[15:13],andC[9:0];bitsC[31:24]aredisregarded updatethroughSDI(seetheSerialInterfacesectionfor details) 7.3.2.2 ParallelInterface To use the device with the parallel interface, hold the PAR/SER pin low. The maximum achievable data throughputrateusingtheinternalclockis630kSPSinthiscase. AccesstotheADS8555deviceiscontrolledasillustratedinFigure2 andFigure3. The device can either operate with a 16-bit (WORD/BYTE pin set low) or an 8-bit (WORD/BYTE pin set high) parallel interface. If 8-bit operation is used, the HB pin selects if the low-byte (DB7 low) or the high-byte (DB7 EN high)isavailableonthedataoutputDB[15:8]first. 7.3.2.3 SerialInterface TheserialinterfacemodeisselectedbysettingthePAR/SERpinhigh.Inthiscase,eachdatatransferstartswith the falling edge of the frame synchronization input (FS). The conversion results are presented on the serial data output pins SDO_A, SDO_B, and SDO_C depending on the selections made using the SEL_x pins. Starting with the most significant bit (MSB), the output data are changed at the rising edge of SCLK, so that the host processorcanreaditatthefollowingfallingedge. SerialdatainputSDIarelatchedatthefallingedgeofSCLK. The serial interface can be used with one, two, or three output ports. These ports are enabled with pins SEL_A, SEL_B, and SEL_C. If all three serial data output ports (SDO_A, SDO_B, and SDO_C) are selected, the data canbereadwitheithertwo16-bitdatatransfersorwithone32-bitdatatransfer.ThedataofchannelsCH_x0are available first, followed by data from channels CH_x1. The maximum achievable data throughput rate is 450 kSPSinthiscase. If the application allows a data transfer using two ports only, SDO_A and SDO_B outputs are used. The device outputs data from channel CH_A0 followed by CH_A1 and CH_C0 on SDO_A, and data from channel CH_B0 followedbyCH_B1andCH_C1occursonSDO_B.Inthiscase,adatatransferofthreeconsecutive16-bitwords oronecontinuous48-bitwordissupported.Themaximumachievabledatathroughputrateis375kSPS. The output SDO_A is selected if only one serial data port is used in the application. The data are available in the following order: CH_A0, CH_A1, CH_B0, CH_B1, CH_C0, and, finally CH_C1. Data can be read using six 16-bit transfers, three 32-bit transfers, or a single 96-bit transfer. The maximum achievable data throughput rate is 250 kSPSinthiscase. Figure1 (theserialoperationtimingdiagram)andFigure31illustrateallpossiblescenariosinmoredetail. 24 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 CONVST_A CONVST_B CONVST_C BUSY (C20 = C21 = 0) SEL_A= SEL_B=1,SEL_C=0 48SCLKs FS SDO_A CHA0 CHA1 CHC0 SDO_B CHB0 CHB1 CHC1 SEL_A= 1, SEL_B =SEL_C=0 96SCLKs FS SDO_A CHA0 CHA1 CHB0 CHB1 CHC0 CHC1 Figure31. SerialInterface:DataOutputWithOneorTwoActiveSDOs 7.3.2.4 OutputDataFormat ThedataoutputformatoftheADS8555isbinarytwoscomplement,asshowninTable3. Table3.OutputDataFormat DESCRIPTION INPUTVOLTAGEVALUE BINARYCODE(HEXADECIMALCODE) Positivefull-scale 4V or2V 0111111111111111(7FFF) REF REF Midscale+0.5LSB V /(2×resolution) 0000000000000000(0000) REF Midscale–0.5LSB –V /(2×resolution) 1111111111111111(FFFF) REF Negativefull-scale –4V or–2V 1000000000000000(8000) REF REF 7.4 Device Functional Modes 7.4.1 HardwareMode With the HW/SW input (pin 62) set low, the device functions are controlled through the pins and, optionally, controlregisterbitsC[22:18],C[15:13],andC[9:0]. Generally, the device can be used in hardware mode and switched into software mode to initialize or adjust the control register settings (for example, the internal reference DAC) and then switched back to hardware mode thereafter. 7.4.2 SoftwareMode When the HW/SW input is set high, the device operates in software mode with functionality set only by the controlregisterbits(correspondingpinsettingsareignored). If parallel interface is used, an update of all control register settings is performed by issuing two 16-bit write accesses on pins DB[15:0] in word mode or four 8-bit accesses on pins DB[15:8] in byte mode (to avoid losing data, the entire sequence must be finished before starting a new conversion). Hold CS low during the two or four write accesses to completely update the configuration register. Updating only the upper eight bits (C[31:24]) is possible using a single write access and pins DB[15:8] in both word and byte modes. In word mode, the first write access updates only the upper eight bits and stores the lower eight bits (C[23:16]) for an update that takes placewiththesecondwriteaccessalongwithC[15:0]. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com Device Functional Modes (continued) If the serial interface is used, input data containing control register contents are required with each read access to the device in this mode (combined read/write access). For initialization purposes, all 32 bits of the register must be set (bit C16 must be set to 1 during that access to allow the update of the entire register content). To minimize switching noise on the interface, an update of the first eight bits (C[31:24]) with the remaining bits held lowcanbeperformedthereafter. Figure35illustratesthedifferentcontrolregisterupdateoptions. 7.4.3 Daisy-ChainMode(InSerialModeOnly) The serial interface of the ADS8555 device supports a daisy-chain feature that allows cascading of multiple devices to minimize the board space requirements and simplify routing of the data and control lines. In this case, pins DB5/DCIN_A, DB4/DCIN_B, and DB3/DCIN_C are used as serial data inputs for channels A, B, and C, respectively. Figure 32 shows an example of a daisy-chain connection of three devices sharing a common CONVST line to allow simultaneous sampling of 18 analog channels along with the corresponding timing diagram. To activate the daisy-chain mode, the DC pin must be pulled high. As a result of the time EN specifications t , t , and t , the maximum SCLK frequency that may be used in daisy-chain mode is 27.78 S1 H1 D3 MHz(assuming50%dutycycle). CONVST FS SCLK ADS8555 ADS8555 ADS8555 #1 #2 #3 CONVST_A CONVST_A CONVST_A FS FS FS SCLK SCLK SCLK SDO_A DCIN_A SDO_A DCIN_A SDO_A To SDO_B DCIN_B SDO_B DCIN_B SDO_B Processing SDO_C DCIN_C SDO_C DCIN_C SDO_C Unit DC =‘0’ DC =‘1’ DC =‘1’ EN EN EN CONVST BUSY (C20 = C21 = 0) FS 16-Bit Data CHx0 16-Bit Data CHx1 16-Bit Data CHx0 16-Bit Data CHx1 16-Bit Data CHx0 16-Bit Data CHx1 SDO_x #3 Don’t Care ADS8555 #3 ADS8555 #3 ADS8555 #2 ADS8555 #2 ADS8555 #1 ADS8555 #1 Figure32. ExampleofDaisy-ChainingThreeADS8555Devices 26 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 Device Functional Modes (continued) 7.4.4 SequentialMode(InSoftwareModeWithExternalConversionClockOnly) The three channel pairs of the ADS8555 device can be run in sequential mode, with the corresponding CONVST_x signals interleaved, when an external clock is used. To activate the device in sequential mode, CR bits C11 (CLKSEL) and C23 (SEQ) must be asserted. In this case, the BUSY output indicates a finished conversion by going low (when C20 = 0) or high (when C20 = 1) for only a single conversion clock cycle in case of ongoing conversions of any other channel pairs. Figure 33 shows the behavior of the BUSY output in this mode. Initiate each conversion start during the high phase of the external clock, as shown in Figure 33. The minimum time required between two CONVST_x pulses is the time required to read the conversion result of a channel(pair). XCLK CONVST_A (1)CAx OH EC CONVST_B (1)CBx OH EC CONVST_C (1)CCx OH tCCLK EC BUSY (C20 = 0) CS RD CH CH CH CH CH CH D[15:0] A0 A1 B0 B1 C0 C1 (1) EOC=endofconversion(internalsignal). Figure33. SequentialModeTiming 7.4.5 ResetandPower-DownModes The device supports two reset mechanisms: a power-on reset (POR) and a pin-controlled reset (RESET) that can be issued using pin 28. Both the POR and RESET act as a master reset that causes any ongoing conversion to be interrupted, the control register content to be set to the default value, and all channels to be switchedintosamplemode. When the device is powered up, the POR sets the device in default mode when AVDD reaches 1.5 V. When the device is powered down, the POR circuit requires AVDD to remain below 125 mV at least 350 ms to ensure proper discharging of internal capacitors and to ensure correct behavior of the device when powered up again. If the AVDD drops below 400 mV but remains above 125 mV (see the undefined zone in Figure 34), the internal POR capacitor does not discharge fully and the device requires a pin-controlled reset to perform correctly after therecoveryofAVDD. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com Device Functional Modes (continued) AVDD (V) 5.500 Specified Supply 5.000 Voltage Range 4.500 4.000 3.000 2.000 POR 1.500 Trigger Level 1.000 0.400 Undefined Zone 0.125 0 0.350 t (s) Figure34. POR:RelevantVoltageLevels The entire device, except the digital interface, can be powered down by pulling the STBY pin low (pin 24). Because the digital interface section remains active, data can be retrieved when in stand-by mode. To power the device on again, the STBY pin must be brought high. The device is ready to start a new conversion after the 10 ms required to activate and settle the internal circuitry. This user-controlled approach can be used in applications that require lower data throughput rates and lowest power dissipation. The content of CR is not changed during standbymode.Apin-controlledresetisnotrequiredafterreturningtonormaloperation. Although the standby mode affects the entire device, each device channel pair can also be individually switched off by setting control register bits C[15:13] (PD_x). When reactivated, the relevant channel pair requires 10 ms to fully settle before starting a new conversion. The internal reference remains active, except all channels are powereddownatthesametime. The auto-NAP power-down mode is enabled by asserting the A-NAP bit (C22) in the control register. If the auto- NAPmodeisenabled,theADS8555deviceautomaticallyreducesthecurrentrequirementto6mAafterfinishing a conversion; thus, the end of conversion actually activates the power-down mode. Triggering a new conversion by applying a positive CONVST_x edge puts the device back into normal operation, starts the acquisition of the analog input, and automatically starts a new conversion six conversion clock cycles later. Therefore, a complete conversion cycle takes 24.5 conversion clock cycles; thus, the maximum throughput rate in auto-NAP power- down mode is reduced to a maximum of 380 kSPS in serial mode, and 500 kSPS in parallel mode. The internal reference remains active during the auto-NAP mode. Table 4 compares the analog current requirements of the deviceinthedifferentmodes. Table4.MaximumAnalogCurrent(I )DemandoftheADS8555 AVDD NORMAL POWERUP POWERUP ANALOG OPERATIONAL ACTIVATED OPERATION TONORMAL TONEXT CURRENT ENABLEDBY RESUMEDBY DISABLEDBY MODE BY TOPOWER- OPERATION CONVERSION (IAVDD) DOWNDELAY DELAY STARTTIME 12mA/channel Normaloperation pair(maximum Poweron CONVST_x — — — — Poweroff datarate) A-NAP=1 Eachendof Atfallingedge A-NAP=0 Auto-NAP 6mA (CRbit) conversion ofBUSY CONVST_x Immediate 6×tCCLK (CRbit) Immediateafter Powerdownof 16μA PD_x=1 PD_x=0 HW/SW=1 Immediate completing 10ms HW/SW=0 channelpairx (channelpairx) (CRbit) (CRbit) registerupdate Stand-by 50μA Poweron STBY=0 Immediate STBY=1 Immediate 10ms Poweroff 28 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 7.5 Register Maps 7.5.1 ControlRegister(CR);DefaultValue=0x000003FF The control register settings can only be changed in software mode and are not affected when switching to hardware mode thereafter. The register values are independent from input pin settings. Changes are active with the rising edge of WR in parallel interface mode or with the 32nd falling SCLK edge of the access in which the register content has been updated in serial mode. Optionally, the register can also be partially updated by writing onlytheuppereightbits(C[31:24]).TheCRcontentisdefinedinTable5. RESET (or Power-Up) BUSY (C20 = C21 = 0) PAR/SER = 1 FS Continuous Update Continuous Update C[31:0] C C SDI Initialization Data [31:24] [31:24] PAR/SER = 0; WORD/BYTE = 0 CS WR Initialization Data Update C C C C DB[15:0] [31:16] [15:0] [31:24] [15:0] PAR/SER = 0; WORD/BYTE = 1 WR Initialization Data Update C C C C C C DB[15:8] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] Figure35. ControlRegisterUpdateOptions Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com Register Maps (continued) Table5.ControlRegister(CR)Map ACTIVEIN BIT NAME DESCRIPTION HARDWAREMODE 0=ChannelpairCdisabledfornextconversion(default) C31 CH_C No 1=ChannelpairCenabled 0=ChannelpairBdisabledfornextconversion(default) C30 CH_B No 1=ChannelpairBenabled 0=ChannelpairAdisabledfornextconversion(default) C29 CH_A No 1=ChannelpairAenabled C28 RANGE_C 0=InputvoltagerangeselectionforchannelpairC:4VREF(default) No 1=InputvoltagerangeselectionforchannelpairC:2VREF C27 RANGE_B 0=InputvoltagerangeselectionforchannelpairB:4VREF(default) No 1=InputvoltagerangeselectionforchannelpairB:2VREF C26 RANGE_A 0=InputvoltagerangeselectionforchannelpairA:4VREF(default) No 1=InputvoltagerangeselectionforchannelpairA:2VREF 0=Internalreferencesourcedisabled(default) C25 REFEN 1=Internalreferencesourceenabled No 0=Internalreferencebuffersenabled(default) C24 REFBUF No 1=Internalreferencebuffersdisabled 0=Sequentialconvertstartmodedisabled(default) C23 SEQ No 1=Sequentialconvertstartmodeenabled(bit11mustbe1inthiscase) 0=Normaloperation(default) C22 A-NAP Yes 1=Auto-NAPfeatureenabled 0=BUSY/INTpininnormalmode(BUSY)(default) C21 BUSY/INT Yes 1=BUSY/INTpinininterruptmode(INT) 0=BUSY/INTactivehigh(default) C20 BUSYL/H Yes 1=BUSY/INTactivelow C19 Don’tuse Thisbitisalwayssetto0 — 0=Internalreferencevoltage:2.5V(default) C18 VREF Yes 1=Internalreferencevoltage:3V 0=Normaloperation(conversionresultsavailableonSDO_x)(default) C17 READ_EN Yes 1=ControlregistercontentsoutputonSDO_xwithnextaccess 0=ControlregisterbitsC[31:24]updateonly(serialmodeonly)(default) C16 C23:0_EN Yes 1=Entirecontrolregisterupdateenabled(serialmodeonly) 0=Normaloperation(default) C15 PD_C Yes 1=PowerdownforchannelpairCenabled(bit31mustbe0inthiscase) 0=Normaloperation(default) C14 PD_B Yes 1=PowerdownforchannelpairBenabled(bit30mustbe0inthiscase) 0=Normaloperation(default) C13 PD_A Yes 1=PowerdownforchannelpairAenabled(bit29mustbe0inthiscase) C12 Don'tuse Thisbitisalways0 — 0=Normaloperationwithinternalconversionclock(mandatoryinhardwaremode)(default) C11 CLKSEL No 1=Externalconversionclock(appliedthroughpin27)used 0=Normaloperation(default) C10 CLKOUT_EN No 1=Internalconversionclockavailableatpin27 C9 REFDAC[9] Bit9(MSB)ofreferenceDACvalue;default=1 Yes C8 REFDAC[8] Bit8ofreferenceDACvalue;default=1 Yes C7 REFDAC[7] Bit7ofreferenceDACvalue;default=1 Yes C6 REFDAC[6] Bit6ofreferenceDACvalue;default=1 Yes C5 REFDAC[5] Bit5ofreferenceDACvalue;default=1 Yes C4 REFDAC[4] Bit4ofreferenceDACvalue;default=1 Yes C3 REFDAC[3] Bit3ofreferenceDACvalue;default=1 Yes C2 REFDAC[2] Bit2ofreferenceDACvalue;default=1 Yes C1 REFDAC[1] Bit1ofreferenceDACvalue;default=1 Yes C0 REFDAC[0] Bit0(LSB)ofreferenceDACvalue;default=1 Yes 30 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 8 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The ADS8555 device enables high-precision measurement of up to six analog signals simultaneously. The following sections summarize some of the typical use cases for the ADS8555 device and the main steps and componentsusedaroundtheanalog-to-digitalconverter. 8.2 Typical Application 8.2.1 MeasurementofElectricalVariablesina3-PhasePowerSystem The accurate measurement of electrical variables in a power grid is extremely critical because it helps determine the operating status and running quality of the grid. Such accurate measurements also help diagnose problems with the power network thereby enabling prompt solutions and minimizing down time. The key electrical variables measured in 3-phase power systems are the three line voltages and the three line currents; see Figure 36. These variables enable metrology and power automation systems to determine the amplitude, frequency and phase information to perform harmonic analysis, power factor calculation and power quality assessment among others. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com Typical Application (continued) 0.1 (cid:29)F ADS8555 From reference REFIO 50 k(cid:13)(cid:3) HVDD block OPA2277 49.9 (cid:13) 0.47 (cid:29)F BVDD CH_A1 From analog CH_B1 STBY 100 k(cid:13)(cid:3) HVSS 370 pF front ends of RANGE 0.1 (cid:29)F CH_B1 and CH_C1 100 k(cid:13)(cid:3) CH_C1 50 k(cid:13)(cid:3) HVDD REFEN/WR 820 pF OPA2277 49.9 (cid:13) HW/SW CH_A0 PAR/SER 370 pF 100 k(cid:13)(cid:3) HVSS To analog front ends of +15 V WORD/BYTE CH_B1 and CH_C1 100 k(cid:13)(cid:3) HVDD 10(cid:29)F 0.1(cid:29)F AGND PT1 PT2 PT3 820 pF 10(cid:29)F 0.1(cid:29)F HVSS -15 V +5 V AVDD CT1 40(cid:29)F Phase A AGND +3.3 V Phase B CT2 BVDD 1(cid:29)F BGND Neutral REFCP Load 10(cid:29)F REFCN Three Phase From analog Phase C Power System CT3 front end of CH_C0 CH_C0 REFBP 10(cid:29)F REFBN From analog To analog front ends of front end of CH_B0 CH_B0 and CH_C0 CH_B0 REFAP 10(cid:29)F REFAN CONVST_A CONVST_B CONVST_C RESET Host CS controller RD DB[15:0] Figure36. SimultaneousAcquisitionofVoltageandCurrentina3-PhasePowerSystem 32 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 Typical Application (continued) 8.2.1.1 DesignRequirements Tobeginthedesignprocess,afewparametersmustbedecidedupon.Thedesignermustknowthefollowing: • Outputrangeofthepotentialtransformers(elementslabeledPT1,PT2,andPT3inFigure36) • Outputrangeofthecurrenttransformers(elementslabeledCT1,CT2,andCT3inFigure36) • Inputimpedancerequiredfromtheanalogfrontendforeachchannel • Fundamentalfrequencyofthepowersystem • Numberofharmonicsthatmustbeacquired • Typeofsignalconditioningrequiredfromtheanalogfrontendforeachchannel 8.2.1.2 DetailedDesignProcedure Figure 37 shows the topology chosen to meet the design requirements. A feedback capacitor C is included to F providealow-passfiltercharacteristicandattenuatesignalsoutsidethebandofinterest. C 1 HVDD R 1 R 2 To ADS8555 V out input R HVSS C IN 2 R F V in From PT C or CT F Figure37. OpAmpinanInvertingConfiguration The potential transformers (PTs) and current transformers (CTs) used in the system depicted in Figure 36 provide the six input variables required. These transformers have a ±10-V output range. Although the PTs and CTs provide isolation from the power system, the value of R is selected as 100 kΩ to provide an additional, IN high-impedance safety element to the input of the ADC. Moreover, selecting a low-frequency gain of –1 V/V (as shown in Equation 5) provides a ±10-V output that can be fed into the ADS8555 device; therefore, the value of R isselectedas100kΩ. F R 100 k: V (cid:16) F V (cid:16) V (cid:16)V out Low f R in 100 k: in in IN (5) The primary goal of the acquisition system depicted in Figure 36 is to measure up to 20 harmonics in a 60-Hz power network. Thus, the analog front-end must have sufficient bandwidth to detect signals up to 1260 Hz, as showninEquation6. f (20 (cid:14)1)60Hz 1260Hz MAX (6) Based on the bandwidth found in Equation 6 the ADS8555 device is set to simultaneously sample all six channelsat15.36kSPS,whichprovidesenoughsamplestoclearlyresolveeventhehighestharmonicrequired. The passband of the configuration shown in Figure 37 is determined by the –3-dB frequency according to Equation 7. The value of C is selected as 820 pF, which is a standard capacitance value available in 0603 size F (surface-mount component) and such values, combined with that of R , result in sufficient bandwidth to F accommodatetherequired20harmonics(at60Hz). 1 1 f 1940 Hz (cid:16)3dB 2SR C 2S(100 k:)(820 pF ) F F (7) The value of R is selected as the parallel combination of R and R to prevent the input bias current of the 1 IN F operationalamplifierfromgeneratinganoffseterror. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com Typical Application (continued) The value of component C is chosen as 0.1 µF to provide a low-impedance path for noise signals that can be 1 picked up by R ; the 0.1-µF capacitance value improves the EMI robustness and noise performance of the 1 system. The OPA2277 device is chosen for its low input offset voltage, low drift, bipolar swing, sufficient gain-bandwidth product and low quiescent current. For additional information on the procedure to select SAR ADC input drivers, seereferenceguideTIDU181. The charge injection damping circuit is composed of R (49.9 Ω) and C (370 pF); these components reject high- 2 2 frequencynoiseandmeetthesettlingrequirementsoftheADS8555deviceinput. Figure38showsthereferenceblockusedinthisdesign. REF5025 AVDD 10 (cid:13)(cid:3) OPA211 VIN OUT 100 (cid:13) To REFIO 10 (cid:29)F 0.1 (cid:29)F 1 (cid:13)(cid:3) GND TRIM 47 (cid:29)F 47 (cid:29)F 10 nF AVDD 47 (cid:29)F AGND 1 (cid:29)F 10 nF 22 (cid:29)F 49.9 (cid:13)(cid:3) Figure38. OpAmpinanInvertingConfiguration For more information on the design of charge injection damping circuits and reference driving circuits for SAR ADCs,consultreferenceguideTIDU014. 8.2.1.3 ApplicationCurve Figure 39 shows the frequency spectrum of the data acquired by the ADS8555 device for a sinusoidal, 20-V PP inputat60Hz. Figure39. FrequencySpectrumforaSinusoidal20-V Signalat60Hz PP Theacperformanceparametersare: 34 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 Typical Application (continued) • SNR:91.9dB • THD:–99.68dB • SNDR:91.23dB • SFDR:103.65dB 9 Power Supply Recommendations The ADS8555 device requires four separate supplies: the analog supply for the ADC (AVDD), the buffer I/O supplyforthedigitalinterface(BVDD),andthetwohigh-voltagesuppliesdrivingtheanaloginputcircuitry(HVDD and HVSS). Generally, there are no specific requirements with regard to the power sequencing of the device. However, when HVDD is supplied before AVDD, the internal ESD structure conducts, increasing IHVDD beyond thespecifiedvalue. The AVDD supply provides power to the internal circuitry of the ADC. AVDD can be set in the range of 4.5 V to 5.5 V. Because the supply current of the device is typically 30 mA, a passive filter cannot be used between the digital board supply of the application and the AVDD pin. TI recommends a linear regulator to generate the analog supply voltage. Decouple each AVDD pin to AGND with a 100-nF capacitor. In addition, place a single 10-μF capacitor close to the device but without compromising the placement of the smaller capacitor. Optionally, eachsupplypincanbedecoupledusinga1-μFceramiccapacitorwithouttherequirementfora10-μFcapacitor. The BVDD supply is only used to drive the digital I/O buffers and can be set in the range of 2.7 V to 5.5 V. This range allows the device to interface with most state-of-the-art processors and controllers. To limit the noise energy from the external digital circuitry to the device, filter BVDD. A 10-Ω resistor can be placed between the external digital circuitry and the device because the current drawn is typically below 2 mA (depending on the external loads). Place a bypass ceramic capacitor of 1 μF (or alternatively, a pair of 100-nF and 10-μF capacitors)betweentheBVDDpinandpin8. The high-voltage supplies (HVSS and HVDD) are connected to the analog inputs. Noise and glitches on these supplies directly couple into the input signals. Place a 100-nF ceramic decoupling capacitor, located as close to the device as possible, between each of pins 30, 31, and AGND. An additional 10-μF capacitor is used that must beplacedclosetothedevicebutwithoutcompromisingtheplacementofthesmallercapacitor. 10 Layout 10.1 Layout Guidelines All GND pins must be connected to a clean ground reference. This connection must be kept as short as possible to minimize the inductance of this path. TI recommends using vias connecting the pads directly to the ground plane. In designs without ground planes, keep the ground trace as wide as possible. Avoid connections that are tooclosetothegroundingpointofamicrocontrollerordigitalsignalprocessor. Depending on the circuit density on the board, placement of the analog and digital components, and the related current loops, a single solid ground plane for the entire printed-circuit-board (PCB) or a dedicated analog ground area can be used. In case of a separated analog ground area, ensure a low-impedance connection between the analoganddigitalgroundoftheADCbyplacingabridgeunderneath(ornext)totheADC.Otherwise,evenshort undershoots on the digital interface lower than –300 mV lead to the conduction of ESD diodes causing current flowthroughthesubstrateanddegradingtheanalogperformance. DuringPCBlayout,takecaretoavoidanyreturncurrentscrossingsensitiveanalogareasorsignals. Figure 40 illustrates a layout recommendation for the ADS8555 device along with the proper decoupling and referencecapacitorplacementandconnections. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:ADS8555

ADS8555 SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 www.ti.com 10.2 Layout Example ADS8555 Top View To AVDD To AVDD To DUT AVDD Source 10 mF 0.1mF 10mF 10mF 10mF 0.47mF 0.1mF D D D D D D D D 64 63 62 61 VD GN 58 GN 56 GN 54 GN GN 51 VD GN A A A A A A A A 1 48 0.1 mF 2 AVDD 3 AVDD To AVDD 4 45 0.1 mF 5 AGND 6 AGND 7 42 0.1 mF 1 BGND AVDD BVDTDo mF BVDD AVDD To AVDD 10 39 0.1 mF 11 AGND 12 AGND 0.1 13 36 mF 14 AVDD To AVDD 15 AVDD 16 33 0.1 mF D D S D D 17 18 19 20 21 22 23 24 GN VD 27 28 29 VS VD GN A A H H A 0.1mF 0.1mF 0.1mF 10mF 10mF To To LEGEND AVDD HVSS/HVDD TOP layer; copper pour and traces Lowerlayer; AGND area Lowerlayer; BGND area Via (1) All0.1-μF,0.47-μF,and1-μFcapacitorsmustbeplacedasclosetotheADS8555deviceaspossible. (2) All10-μFcapacitorsmustbeclosetothedevicebutwithoutcompromisingtheplacementofthesmallercapacitors. Figure40. LayoutRecommendation 36 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8555

ADS8555 www.ti.com SBAS531D–DECEMBER2010–REVISEDFEBRUARY2016 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 RelatedDocumentation Forrelateddocumentationseethefollowing: • OPA2277DataSheet,SBOS079 • REF5025DataSheet,SBOS410 • Power-Optimized16-Bit1-MSPSDataAcquisitionBlockDesignGuide,TIDU014 • 16-Bit400-KSPS4-ChannelMultiplexedDataAcquisitionSystemDesignGuide,TIDU181 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.3 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:ADS8555

PACKAGE OPTION ADDENDUM www.ti.com 12-May-2017 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS8555SPM ACTIVE LQFP PM 64 160 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS & no Sb/Br) 8555 ADS8555SPMR ACTIVE LQFP PM 64 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS & no Sb/Br) 8555 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 12-May-2017 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS8555SPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS8555SPMR LQFP PM 64 1000 350.0 350.0 43.0 PackMaterials-Page2

MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 M 0,17 48 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 0,25 12,20 SQ 0,05 MIN 0°–7° 11,80 1,45 0,75 1,35 0,45 Seating Plane 1,60 MAX 0,08 4040152/C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. May also be thermally enhanced plastic with leads connected to the die pads. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

None

IMPORTANTNOTICEANDDISCLAIMER TIPROVIDESTECHNICALANDRELIABILITYDATA(INCLUDINGDATASHEETS),DESIGNRESOURCES(INCLUDINGREFERENCE DESIGNS),APPLICATIONOROTHERDESIGNADVICE,WEBTOOLS,SAFETYINFORMATION,ANDOTHERRESOURCES“ASIS” ANDWITHALLFAULTS,ANDDISCLAIMSALLWARRANTIES,EXPRESSANDIMPLIED,INCLUDINGWITHOUTLIMITATIONANY IMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSEORNON-INFRINGEMENTOFTHIRD PARTYINTELLECTUALPROPERTYRIGHTS. TheseresourcesareintendedforskilleddevelopersdesigningwithTIproducts.Youaresolelyresponsiblefor(1)selectingtheappropriate TIproductsforyourapplication,(2)designing,validatingandtestingyourapplication,and(3)ensuringyourapplicationmeetsapplicable standards,andanyothersafety,security,orotherrequirements.Theseresourcesaresubjecttochangewithoutnotice.TIgrantsyou permissiontousetheseresourcesonlyfordevelopmentofanapplicationthatusestheTIproductsdescribedintheresource.Other reproductionanddisplayoftheseresourcesisprohibited.NolicenseisgrantedtoanyotherTIintellectualpropertyrightortoanythird partyintellectualpropertyright.TIdisclaimsresponsibilityfor,andyouwillfullyindemnifyTIanditsrepresentativesagainst,anyclaims, damages,costs,losses,andliabilitiesarisingoutofyouruseoftheseresources. TI’sproductsareprovidedsubjecttoTI’sTermsofSale(www.ti.com/legal/termsofsale.html)orotherapplicabletermsavailableeitheron ti.comorprovidedinconjunctionwithsuchTIproducts.TI’sprovisionoftheseresourcesdoesnotexpandorotherwisealterTI’sapplicable warrantiesorwarrantydisclaimersforTIproducts. MailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265 Copyright©2019,TexasInstrumentsIncorporated