ADS8517 ADS8517 ADS8517 www.ti.com................................................................................................................................................. SLAS527A–SEPTEMBER2008–REVISEDJUNE2009 16-Bit, 200-kSPS, Low-Power, Sampling ANALOG-TO-DIGITAL CONVERTER with Internal Reference and Parallel/Serial Interface FEATURES APPLICATIONS 1 • 200-kHzMinimumSamplingRate • PortableTestEquipment 23 • 4-V,5-V,and±10-VInputRangeswith • USBDataAcquisitionModule High-ImpedanceInput • MedicalEquipment • ±1.5LSBMaxINL • IndustrialProcessControl • +1.5/–1LSBMax/MinDNL,16BitsNMC • DigitalSignalProcessing • ±2-mVMaxBPZ,±0.6ppm/°CBPZDrift • Instrumentation • ±2-mVMaxUPZ,±0.15ppm/°CUPZDrift DESCRIPTION • 88.8-dBSINADwith10-kHzInput The ADS8517 is a complete low-power, single 5-V • SPI™-CompatibleSerialOutputWith supply, 16-bit sampling analog-to-digital (A/D) Daisy-Chain(TAG),SPIMaster/SlaveFeature converter. It contains a complete, 16-bit, • FullParallelInterface capacitor-based, successive approximation register • BinaryTwosComplementorStraightBinary (SAR) A/D converter with sample-and-hold, clock, reference, and data interface. The converter can be OutputCodeFormats configured for a variety of input ranges including • Single4.5-Vto5.5-VAnalogSupply,1.65-Vto ±10 V, 4 V, and 5 V. For most input ranges, the input 5.5-VInterfaceSupply voltage can swing to 25 V or –25 V without damage • UsesInternal2.5-VorExternalReference tothedevice. • NoExternalPrecisionResistorsRequired An SPI-compatible serial interface allows data to be • LowPowerDissipation(ADC+REF+BUF): synchronized to an internal or external clock. A full parallel interface using the selectable BYTE pin is – 47mWTyp,60mWMaxat200kSPS also provided to allow the maximum system design • 50-m WMaxPower-DownMode flexibility. The ADS8517 is specified at a 200-kHz • Pin-Compatiblewith16-BitADS7807and sampling rate over the industrial –40°C to +85°C ADS8507,and12-BitADS7806andADS8506 temperaturerange. • SO-28andTSSOP-28Packages ADC Successive Approximation Register (SAR) Parallel Data PWRD Parallel BYTE 40 kW CDAC and BUSY R1 Serial CS IN Data Out R/C and SB/BTC Control TAG 10 kW 20 kW 40 kW SDATA R2IN Comparator DATACLK CAP Clock EXT/INT BUF Ref REF Buffer 6 kW 2.5-V REF REFD Internal Reference 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. SPIisatrademarkofMotorola,Inc. 2 Allothertrademarksarethepropertyoftheirrespectiveowners. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2008–2009,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

ADS8517 SLAS527A–SEPTEMBER2008–REVISEDJUNE2009................................................................................................................................................. www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. PACKAGE/ORDERINGINFORMATION(1) MINIMUM RELATIVE NO MINIMUM SPECIFIED ACCURACY MISSING SINAD TEMPERATURE PACKAGE- PACKAGE ORDERING TRANSPORT PRODUCT (LSB) CODE (dB) RANGE LEAD DESIGNATOR NUMBER MEDIA,QTY ADS8517IBDW Tube,20 SO-28 DW ADS8517IBDWR TapeandReel,1000 ADS8517IB ±1.5 16 87 -40°Cto+85°C ADS8517IBPW Tube,50 TSSOP-28 PW ADS8517IBPWR TapeandReel,2000 ADS8517IDW Tube,20 SO-28 DW ADS8517IDWR TapeandReel,1000 ADS8517I ±3 15 85 -40°Cto+85°C ADS8517W Tube,50 TSSOP-28 PW ADS8517IPWR TapeandReel,2000 (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS (1)(2) Overoperatingfree-airtemperaturerange(unlessotherwisenoted). UNIT R1 ±25V IN Analoginputs R2 ±25V IN REF +V +0.3VtoAGND2–0.3V ANA DGND,AGND2 ±0.3V V 6V ANA Groundvoltagedifferences V toV 0.3V DIG ANA V 6V DIG Digitalinputs -0.3Vto+V +0.3V DIG Maximumjunctiontemperature +165°C Storagetemperaturerange –65°Cto+150°C Internalpowerdissipation 700mW (1) StressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Exposuretoabsolute maximumconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevaluesarewithrespecttonetworkgroundterminal. ELECTRICAL CHARACTERISTICS AtT =-40°Cto+85°C,f =200kHz,V =V =5V,usinginternalreference(seeFigure39),unlessotherwisenoted. A S DIG ANA ADS8517I ADS8517IB(1) PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT Resolution 16 16 Bits ANALOGINPUT –10 10 –10 10 Voltageranges SeeTable1 0 5 0 5 V 0 4 0 4 Impedance SeeTable1 Capacitance 45 45 pF (1) Shadedcellsindicatedifferentspecificationsforhigh-gradeversionofthedevice. 2 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8517

ADS8517 www.ti.com................................................................................................................................................. SLAS527A–SEPTEMBER2008–REVISEDJUNE2009 ELECTRICAL CHARACTERISTICS (continued) AtT =-40°Cto+85°C,f =200kHz,V =V =5V,usinginternalreference(seeFigure39),unlessotherwisenoted. A S DIG ANA ADS8517I ADS8517IB(1) PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT THROUGHPUTSPEED Conversiontime 2.5 2.5 m s Completecycle Acquireandconvert 5 5 m s Throughputrate 200 200 kHz DCACCURACY INL Integrallinearityerror –3 3 –1.5 1.5 LSB(2) DNL Differentiallinearityerror –2 3 –1 1.5 LSB Nomissingcodes 15 16 Bits Transitionnoise(3) 0.9 0.8 LSB Gainerror ±0.2 ±0.1 % Internalreference –0.75 0.75 –0.75 0.75 % Full-scaleerror(4) External2.5-Vreference –0.75 0.75 –0.75 0.75 % Internalreference ±9 ±9 ppm/°C Full-scaleerrordrift External2.5-Vreference ±1 ±1 ppm/°C BPZ Bipolarzeroerror ±10Vrange –5 ±1 5 –2 ±1 2 mV Bipolarzeroerrordrift ±10Vrange ±0.6 ±0.6 ppm/°C UPZ Unipolarzeroerror 0Vto5V,0Vto4Vranges –3 ±0.1 3 –2 ±0.1 2 mV Unipolarzeroerrordrift 0Vto5V,0Vto4Vranges ±0.15 ±0.15 ppm/°C Rfroemcopveorwyetrimdeowton(r5a)tedaccuracy 2.2-m FcapacitortoCAP 1 1 ms Power-supplysensitivity +4.75V<VANA<+5.25V –8 +8 –6 +6 LSB (VDIG=VANA=VS) +4.5V<VANA<+5.5V –20 +20 –12 +12 ACACCURACY SFDR Spurious-freedynamicrange fIN=10kHz,±10V 92 100 96 101 dB(6) THD Totalharmonicdistortion fIN=10kHz,±10V –97 –92 –98 –95 dB fIN=10kHz,±10V 85 88 87 88.5 SINAD Signal-to-(noise+distortion) dB –60dBInput 29 29 SNR Signal-to-noiseratio fIN=10kHz,±10V 85 88 88 89 dB SNRusablebandwidth(7) fIN=10kHz,±10V 130 130 kHz SNRfull-powerbandwidth(–3dB) fIN=10kHz,±10V 600 600 kHz SAMPLINGDYNAMICS Aperturedelay 40 40 ns Aperturejitter 20 20 ps Transientresponse FSstep 5 5 m s Overvoltagerecovery(8) 750 750 ns (2) LSBmeansLeastSignificantBit.OneLSBforthe±10Vinputrangeis305m V. (3) Typicalrmsnoiseatworst-casetransitions. (4) Full-scaleerroristheworstcaseof–FullScaleor+FullScaleuntrimmeddeviationfromidealfirstandlastcodetransitions,dividedby thetransitionvoltage(notdividedbythefull-scalerange)andincludestheeffectofoffseterror. (5) ThisisthetimedelayaftertheADS8517isbroughtoutofPower-Downmodeuntilallinternalsettlingoccursandtheanaloginputis acquiredtoratedaccuracy.AConvertcommandafterthisdelaywillyieldaccurateresults. (6) AllspecificationsindBarereferredtoafull-scaleinput. (7) Usablebandwidthdefinedasfull-scaleinputfrequencyatwhichSignal-to-(Noise+Distortion)degradesto60dB. (8) Recoverstospecifiedperformanceafter2xFSinputovervoltage. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):ADS8517

ADS8517 SLAS527A–SEPTEMBER2008–REVISEDJUNE2009................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (continued) AtT =-40°Cto+85°C,f =200kHz,V =V =5V,usinginternalreference(seeFigure39),unlessotherwisenoted. A S DIG ANA ADS8517I ADS8517IB(1) PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT REFERENCE Internalreferencevoltage Noload 2.48 2.5 2.52 2.48 2.5 2.52 V Internalreferencesourcecurrent 1 1 m A (mustuseexternalbuffer) Internalreferencedrift 8 8 ppm/°C Externalreferencevoltagerange 2.3 2.5 2.7 2.3 2.5 2.7 V forspecifiedlinearity Externalreferencecurrentdrain External2.5-Vreference 100 100 m A DIGITALINPUTS VIL Low-levelinputvoltage(9) VDIG=1.65Vto5.5V –0.3 0.6 –0.3 0.6 V VIH High-levelinputvoltage(9) VDIG=1.65Vto5.5V 0.5xVDIG VDIG+0.3 0.5xVDIG VDIG+0.3 V IIL Low-levelinputcurrent VIL=0V ±10 ±10 m A IIH High-levelinputcurrent VIH=5V ±10 ±10 m A DIGITALOUTPUTS Dataformat-Parallel16-bitsin2-bytes,Serial Datacoding-Binarytwoscomplementorstraightbinary VOL Low-leveloutputvoltage IVSDINIGK==11..665mVA,to5.5V 0.45 0.45 V VOH High-leveloutputvoltage IVSDOIUGR=CE1=.655V00tmoA5,.5V VDIG–0.45 VDIG–0.45 V Leakagecurrent High-Zstate, ±5 ±5 m A VOUT=0VtoVDIG Outputcapacitance High-Zstate 15 15 pF DIGITALTIMING Busaccesstime RL=3.3kΩ,CL=50pF 83 83 ns Busrelinquishtime RL=3.3kΩ,CL=10pF 83 83 ns POWERSUPPLIES VDIG Interfacevoltage 1.65 1.8 5.5 1.65 1.8 5.5 V VANA ADCcorevoltage 4.5 5 5.5 4.5 5 5.5 V IDIG Interfacecurrent VDIG=5V 0.3 0.3 mA IANA ADCcorecurrent VANA=5V 9 9 mA VANA=VDIG=5V, 47 60 47 60 mW fS=200kHz Powerdissipation REFDhighwithBUFon 42 42 mW PWRDandREFDhigh 50 50 m W TEMPERATURERANGE Specifiedperformance –40 +85 –40 +85 °C Deratedperformance –55 +125 –55 +125 °C Storagetemperature –65 +150 –65 +150 °C TSSOP 62 62 q JA Thermalimpedance °C/W SO 46 46 (9) TTL-compatibleat5Vsupply. Table1. AnalogInputRangeConnections(seeFigure38andFigure39) ANALOGINPUT RANGE CONNECTR1 VIA200ΩTO CONNECTR2 VIA100ΩTO IMPEDANCE IN IN ±10V V CAP 45.7kΩ IN 0Vto5V AGND V 20.0kΩ IN 0Vto4V V V 21.4kΩ IN IN 4 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8517

ADS8517 www.ti.com................................................................................................................................................. SLAS527A–SEPTEMBER2008–REVISEDJUNE2009 PIN CONFIGURATION DW,PWPACKAGES SO-28,TSSOP-28 (TOPVIEW) R1 1 28 V IN DIG AGND1 2 27 V ANA R2 3 26 REFD IN CAP 4 25 PWRD REF 5 24 BUSY AGND2 6 23 CS SB/BTC 7 22 R/C ADS8517 EXT/INT 8 21 BYTE D7 9 20 TAG D6 10 19 SDATA D5 11 18 DATACLK D4 12 17 D0 D3 13 16 D1 DGND 14 15 D2 PINASSIGNMENTS PIN DIGITAL NAME NO. I/O DESCRIPTION R1 1 AnalogInput. IN AGND1 2 Analogsenseground.Usedinternallyasgroundreferencepoint.Minimalcurrentflow R2 3 AnalogInput. IN CAP 4 Referencebufferoutput.2.2-m Ftantalumcapacitortoground. Referenceinput/output.Outputsinternal2.5-Vreference.Canalsobedrivenbyexternalsystem REF 5 reference.Inbothcases,bypasstogroundwitha2.2-m Ftantalumcapacitor. AGND2 6 Analogground Outputmodeselect.Selectsstraightbinaryorbinarytwoscomplementforoutputdataformat.If SB/BTC 7 I high,dataareoutputinastraightbinaryformat.Iflow,dataareoutputinabinarytwos complementformat. External/internaldataselect.Selectsexternal/internaldataclockfortransmittingdata.Ifhigh, dataisoutputsynchronizedtotheclockinputonDATACLK.Iflow,aconvertcommandinitiates EXT/INT 8 I thetransmissionofthedatafromthepreviousconversion,alongwith16-clockpulsesoutputon DATACLK. Databit7ifBYTEishigh.Databit15(MSB)ifBYTEislow.High-ZwhenCSishighand/orR/C D7 9 O islow.Leaveunconnectedwhenusingserialoutput. D6 10 O Databit6ifBYTEishigh.Databit14ifBYTEislow.High-ZwhenCSishighand/orR/Cislow. D5 11 O Databit5ifBYTEishigh.Databit13ifBYTEislow.High-ZwhenCSishighand/orR/Cislow. D4 12 O Databit4ifBYTEishigh.Databit12ifBYTEislow.High-ZwhenCSishighand/orR/Cislow. D3 13 O Databit3ifBYTEishigh.Databit11ifBYTEislow.High-ZwhenCSishighand/orR/Cislow. DGND 14 Digitalground D2 15 O Databit2ifBYTEishigh.Databit10ifBYTEislow.High-ZwhenCSishighand/orR/Cislow. D1 16 O Databit1ifBYTEishigh.Databit9ifBYTEislow.High-ZwhenCSishighand/orR/Cislow. Databit0(LSB)ifBYTEishigh.Databit8ifBYTEislow.High-ZwhenCSishighand/orR/Cis D0 17 O low. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):ADS8517

ADS8517 SLAS527A–SEPTEMBER2008–REVISEDJUNE2009................................................................................................................................................. www.ti.com PINASSIGNMENTS(continued) Dataclock.Eitheraninputoranoutput,dependingontheEXT/INTlevel.Outputdataare DATACLK 18 I/O synchronizedtothisclock.IfEXT/INTislow,DATACLKtransmits16pulsesaftereach conversion,andthenremainslowbetweenconversions. Serialdataoutput.DataaresynchronizedtoDATACLK,withtheformatdeterminedbythelevel ofSB/BTC.Intheexternalclockmode,after16bitsofdata,theADCoutputsthelevelinputon SDATA 19 O TAGaslongasCSislowandR/Cishigh.IfEXT/INTislow,dataarevalidonboththerising andfallingedgesofDATACLK,andbetweenconversionsSDATAstaysattheleveloftheTAG inputwhentheconversionwasstarted. Taginputforuseintheexternalclockmode.IfEXTishigh,digitaldatainputfromTAGisoutput TAG 20 I onDATAwithadelaythatdependsontheexternalclockmode. Byteselect.Selectstheeightmostsignificantbits(low)oreightleastsignificantbits(high)on BYTE 21 I paralleloutputpins. Read/convertinput.WithCSlow,afallingedgeonR/Cputstheinternalsample-and-holdcircuit R/C 22 I intotheholdstateandstartsaconversion.WithEXT/INTislow,thetransmissionofthedata resultsfromthepreviousconversionisinitiated. Chipselect.InternallyORedwithR/C.IfR/Cislow,afallingedgeonCSinitiatesanew CS 23 I conversion.IfEXT/INTislow,thissamefallingedgewillstartthetransmissionofserialdata resultsfromthepreviousconversion. Busyoutput.Atthestartofaconversion,BUSYgoeslowandstayslowuntiltheconversionis BUSY 24 O completedandthedigitaloutputshavebeenupdated. Power-downinput.Ifhigh,conversionsareinhibitedandpowerconsumptionissignificantly PWRD 25 I reduced.Resultsfromthepreviousconversionaremaintainedintheoutputshiftregister. Referencedisable.REFDhighshutsdowntheinternalreference.Theexternalreferenceis REFD 26 I requiredforconversions. V 27 ADCcoresupply.Nominally+5V.Decouplewith0.1-m Fceramicand10-m Ftantalumcapacitors. ANA V 28 I/Osupply.Nominally+1.8V. DIG 6 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8517

ADS8517 www.ti.com................................................................................................................................................. SLAS527A–SEPTEMBER2008–REVISEDJUNE2009 TYPICAL CHARACTERISTICS Atf =200kHz,V =V =5V,andusinginternalreference(seeFigure39),unlessotherwisespecified. S DIG ANA POWER-SUPPLYCURRENT INTERNALREFERENCEVOLTAGE vsFREE-AIRTEMPERATURE vsFREE-AIRTEMPERATURE 10.0 2.520 2.515 mA) 9.5 e (V) 2.510 urrent ( e Voltag 2.505 C c upply 9.0 eferen 22..540905 S R wer- 8.5 nal 2.490 Po Inter 2.485 8.0 2.480 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Figure1. Figure2. POWER-SUPPLYCURRENT BIPOLAROFFSETERROR vsSAMPLINGFREQUENCY vsFREE-AIRTEMPERATURE 10.0 2 Bipolar±10 V Range A) m 9.5 1 nt ( urre mV) ply C 9.0 set ( 0 up Off S wer- 8.5 -1 o P 8.0 -2 50 100 150 200 -50 -25 0 25 50 75 100 125 Sampling Frequency (kHz) Temperature (°C) Figure3. Figure4. BIPOLARPOSITIVEFULL-SCALEERROR BIPOLARNEGATIVEFULL-SCALEERROR vsFREE-AIRTEMPERATURE vsFREE-AIRTEMPERATURE 0.10 0 Bipolar 10 V Range Bipolar 10 V Range %) %) Error ( Error ( Scale 0.05 Scale -0.05 Positive Full- Negative Full- 0 -0.10 -40 -50 0 25 50 75 100 125 -50 -45 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Figure5. Figure6. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):ADS8517

ADS8517 SLAS527A–SEPTEMBER2008–REVISEDJUNE2009................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) Atf =200kHz,V =V =5V,andusinginternalreference(seeFigure39),unlessotherwisespecified. S DIG ANA UNIPOLAROFFSETERROR UNIPOLAROFFSETERROR vsFREE-AIRTEMPERATURE vsFREE-AIRTEMPERATURE 0.2 0.2 Unipolar 4 V Range Unipolar 5 V Range 0.1 0.1 V) V) m m et ( 0 et ( 0 s s Off Off -0.1 -0.1 -0.2 -0.2 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Figure7. Figure8. UNIPOLARFULL-SCALEERROR UNIPOLARFULL-SCALEERROR vsFREE-AIRTEMPERATURE vsFREE-AIRTEMPERATURE 0.10 0.10 Unipolar 4 V Range Unipolar 5 V Range 0.05 0.05 V) V) m m et ( 0 et ( 0 s s Off Off -0.05 -0.05 -0.10 -0.10 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Figure9. Figure10. ACPARAMETERS SIGNAL-TO-(NOISE+DISTORTION) vsFREE-AIRTEMPERATURE vsFREE-AIRTEMPERATURE 110 -80 89.5 f = 10 kHz, 0 dB f = 10 kHz, 0 dB IN f = 150 kHz IN B) 105 -85 S d NR ( 100 SFDR -90 89.0 SINAD, and S 9950 TSHNDR --91500THD (dB) SINAD (dB) 88.5 fS= 2fS00= k5H0z kHz fS= 100 kHz DR, SINAD 88.0 SF 85 -105 80 -110 87.5 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Figure11. Figure12. 8 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8517

ADS8517 www.ti.com................................................................................................................................................. SLAS527A–SEPTEMBER2008–REVISEDJUNE2009 TYPICAL CHARACTERISTICS (continued) Atf =200kHz,V =V =5V,andusinginternalreference(seeFigure39),unlessotherwisespecified. S DIG ANA SIGNAL-TO-(NOISE+DISTORTION) SIGNAL-TO-NOISERATIO vsINPUTFREQUENCYANDINPUTAMPLITUDE vsINPUTFREQUENCY 100 100 0 dB 90 80 -20 dB 70 NAD (dB) 6500 NR (dB) 90 SI S 40 -60 dB 30 20 10 80 0 2 4 6 8 10 12 14 16 18 20 1 10 100 Input Signal Frequency (kHz) Input Sampling Frequency (kHz) Figure13. Figure14. SIGNAL-TO-(NOISE+DISTORTION) SPURIOUS-FREEDYNAMICRANGE vsINPUTFREQUENCY vsINPUTFREQUENCY 100 110 100 B) B) D (d 90 R (d 90 A D N F SI S 80 80 70 1 10 100 1 10 100 Input Sampling Frequency (kHz) Input Sampling Frequency (kHz) Figure15. Figure16. TOTALHARMONICDISTORTION ACPARAMETERS vsINPUTFREQUENCY vsCAPPINCAPACITORESR -70 110 -80 f = 10 kHz, 0 dB IN -80 dB)105 -85 R ( SFDR N100 -90 S THD (dB) -1-0900 NAD, and 95 THD -95 THD (dB) SI 90 SNR -100 R, -110 SFD 85 SINAD -105 -120 80 -110 1 10 100 0 1 2 3 4 5 6 7 8 9 10 Input Sampling Frequency (kHz) ESR (W) Figure17. Figure18. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):ADS8517

ADS8517 SLAS527A–SEPTEMBER2008–REVISEDJUNE2009................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) Atf =200kHz,V =V =5V,andusinginternalreference(seeFigure39),unlessotherwisespecified. S DIG ANA ACPARAMETERS OUTPUTREJECTION vsPOWER-SUPPLYVOLTAGE vsPOWER-SUPPLYRIPPLEFREQUENCY 110 -70 -20 f = 10 kHz, 0 dB 105 IN -75 -30 NR (dB)10905 SFDR --8805 n (dB) -40 S o R, SINAD, and 988050 SSINNARD THD ---9910500THD (dB) Output Rejecti --5600 D -70 SF 75 -105 70 -110 -80 4.00 4.25 4.50 4.75 5.00 5.25 5.50 10 100 1k 10k 100k 1M Power-Supply Voltage (V) Power-Supply Ripple Frequency (Hz) Figure19. Figure20. INTEGRALLINEARITYERRORAND CONVERSIONTIME DIFFERENTIALLINEARITYERROR vsFREE-AIRTEMPERATURE vsPOWER-SUPPLYVOLTAGE 2.40 2.0 1.5 B) e (s)m 2.35 Min (LS 10..05 INL Max Tim nd DNL Max on 2.30 x a 0 DNL Min versi L Ma -0.5 Con 2.25 DN -1.0 INL Min L/ N I -1.5 2.20 -2.0 -50 -25 0 25 50 75 100 125 4.00 4.25 4.50 4.75 5.00 5.25 5.50 Temperature (°C) Power-Supply Voltage (V) Figure21. Figure22. INTEGRALLINEARITYERROR DIFFERENTIALLINEARITYERROR 3 3 2 2 1 1 B) B) S S NL (L 0 NL (L 0 I -1 D -1 -2 -2 All Codes INL All Codes DNL -3 -3 0 8192 16384 24576 32768 40960 49152 57344 65535 0 8192 16384 24576 32768 40960 49152 57344 65535 Code Code Figure23. Figure24. 10 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8517

ADS8517 www.ti.com................................................................................................................................................. SLAS527A–SEPTEMBER2008–REVISEDJUNE2009 TYPICAL CHARACTERISTICS (continued) Atf =200kHz,V =V =5V,andusinginternalreference(seeFigure39),unlessotherwisespecified. S DIG ANA FFT FFT 0 0 -10 4096 Point FFT -10 4096 Point FFT -20 fIN= 1 kHz, 0 dB -20 fIN= 10 kHz, 0 dB -30 -30 -40 -40 dB) -50 dB) -50 e ( -60 e ( -60 d d mplitu --7800 mplitu --7800 A -90 A -90 -100 -100 -110 -110 -120 -120 -130 -130 0 25 50 75 100 0 25 50 75 100 Frequency (kHz) Frequency (kHz) Figure25. Figure26. FFT 0 -10 4096 Point FFT -20 fIN= 20 kHz, 0 dB -30 -40 dB) -50 e ( -60 d mplitu --7800 A -90 -100 -110 -120 -130 0 25 50 75 100 Frequency (kHz) Figure27. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):ADS8517

ADS8517 SLAS527A–SEPTEMBER2008–REVISEDJUNE2009................................................................................................................................................. www.ti.com BASIC OPERATION PARALLEL OUTPUT Figure 28 shows a basic circuit for operating the ADS8517 with a ±10-V input range and parallel output. Taking R/C(pin22)lowforaminimumof40ns(5 m s max) initiates a conversion. BUSY (pin 24) goes low and stays low until the conversion completes and the output register updates. If BYTE (pin 21) is low, the eight most significant bits (MSBs) will be valid when BUSY rises; if BYTE is high, the eight least significant bits (LSBs) will be valid when BUSY rises. Data are output in binary twos complement (BTC) format. BUSY going high can be used to latch the data. After the first byte has been read, BYTE can be toggled, allowing the remaining byte to be read. AllconvertcommandsareignoredwhileBUSYislow. The ADS8517 begins tracking the input signal at the end of the conversion. Allowing 5 m s between convert commandsassuresaccurateacquisitionofanewsignal. ±10V 1 28 +1.8 V 2 27 +5V 0.1mF + + 3 26 0.1mF 10mF 4 25 + 5 24 BUSY 2.2mF 2.2mF 6 23 Convert Pulse 7 22 R/C ADS8517 +5 V 8 21 BYTE 40 ns min 9 20 10 19 NC(1) 11 18 12 17 13 16 14 15 Pin 21 B15 B14B13B12B11 B10 B9 B8 LOW (MSB) Pin 21 B7 B6 B5 B4 B3 B2 B1 B0 HIGH (LSB) NOTE: (1) NC = not connected. Figure28.Basic±10-VOperation,BothParallelandSerialOutput 12 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8517

ADS8517 www.ti.com................................................................................................................................................. SLAS527A–SEPTEMBER2008–REVISEDJUNE2009 SERIAL OUTPUT Figure 29 shows a basic circuit to operate the ADS8517 with a ±10-V input range and serial output. Taking R/C (pin 22) low for 40 ns (5 m s max) initiates a conversion and outputs valid data from the previous conversion on SDATA (pin 19) synchronized to 16 clock pulses output on DATACLK (pin 18). BUSY (pin 24) goes low and stays low until the conversion completes and the serial data have been transmitted. Data are output in BTC format, MSB first, and are valid on both the rising and falling edges of the data clock. BUSY going high can be usedtolatchthedata.AllconvertcommandsareignoredwhileBUSYislow. The ADS8517 begins tracking the input signal at the end of the conversion. Allowing 5 m s between convert commandsassuresaccurateacquisitionofanewsignal. ±10V 1 28 +1.8 V 2 27 +5V 0.1mF + + 3 26 0.1mF 10mF 4 25 + + 5 24 BUSY 22mF 2.2mF 6 23 Convert Pulse 7 22 R/C ADS8517 8 21 40 ns min NC(1) 9 20 NC(1) 10 19 SDATA NC(1) 11 18 DATACLK NC(1) 12 17 NC(1) NC(1) 13 16 NC(1) 14 15 NC(1) NOTE: (1) NC = not connected. Figure29.Basic±10-VOperationwithSerialOutput Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):ADS8517

ADS8517 SLAS527A–SEPTEMBER2008–REVISEDJUNE2009................................................................................................................................................. www.ti.com STARTING A CONVERSION The combination of CS (pin 23) and R/C (pin 22) held low for a minimum of 40 ns puts the sample-and-hold of theADS8517inthehold state and starts conversion N.BUSY (pin 24) goes low and stays low until conversion N completes and the internal output register has been updated. All new convert commands received while BUSY is lowareignored. The ADS8517 begins tracking the input signal at the end of the conversion. Allowing 5 m s between convert commands assures accurate acquisition of a new signal. Refer to Table 2 and Table 3 for a summary of CS, R/C,andBUSYstates,andFigure30throughFigure36fortimingdiagrams. Table2.ControlFunctionsWhenUsingParallelOutput(DATACLKTiedLow,EXT/INTTiedHigh) CS R/C BUSY OPERATION 1 X X None.DatabusisinHigh-Zstate. ↓ 0 1 InitiatesconversionN.DatabusremainsinHigh-Zstate. 0 ↓ 1 InitiatesconversionN.DatabusentersHigh-Zstate. 0 1 ↑ ConversionNcompleted.ValiddatafromconversionNonthedatabus. ↓ 1 1 EnablesdatabuswithvaliddatafromconversionN. ↓ 1 0 EnablesdatabuswithvaliddatafromconversionN–1(1).ConversionNinprogress. 0 ↑ 0 EnablesdatabuswithvaliddatafromconversionN–1(1).ConversionNinprogress. 0 0 ↑ Newconversioninitiatedwithoutacquisitionofanewsignal.Dataareinvalid.CSand/orR/C mustbehighwhenBUSYgoeshigh. X X 0 Newconvertcommandsignored.ConversionNinprogress. (1) SeeFigure30andFigure31forconstraintsondatavalidfromconversionN–1. CSandR/CareinternallyORedandlevel-triggered.Itdoesnotmatterwhichinputgoeslowfirstwheninitiating a conversion. If, however, it is critical that CS or R/C initiates conversion N, be sure the less critical input is low at leastt ≥10nsbeforetheinitiatinginput.If EXT/INT (pin 8) is low when initiating conversion N, serial data from su2 conversion N–1 is output on SDATA (pin 19) following the start of conversion N. See Internal Data Clock in the ReadingDatasectionformoreinformation. To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. This configuration has no effect when using the internal data clock in the serial output mode. However, when using an active external data clock, the parallel and serial outputs are affected whenever R/C goes high; refer to the Reading Data section for more information. In the internal clock mode, data are clocked out every convert cycle regardless of the states of CS and R/C. The conversion result is available as soon as BUSY returns to high. Therefore,dataalwaysrepresentthepreviously-completedconversion,evenwhenreadduringaconversion. 14 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8517

ADS8517 www.ti.com................................................................................................................................................. SLAS527A–SEPTEMBER2008–REVISEDJUNE2009 READING DATA The ADS8517 outputs serial or parallel data in straight binary (SB) or binary twos complement data output format. If SB/BTC (pin 7) is high, the output is in SB format; if it is low, the output is in BTC format. Refer to Table 4 for the ideal output codes. The first conversion immediately following a power-up does not produce a validconversionresult. The parallel output can be read without affecting the internal output registers; however, reading the data through theserialportshiftstheinternaloutputregistersonebitperdataclockpulse.Asaresult,datacanbereadonthe parallel port before reading the same data on the serial port, but data cannot be read through the serial port beforereadingthesamedataontheparallelport. Table3.ControlFunctionsWhenUsingSerialOutput(1) CS R/C BUSY EXT/INT DATACLK OPERATION ↓ 0 1 0 Output InitiatesconversionN.ValiddatafromconversionN–1clockedoutonSDATA. 0 ↓ 1 0 Output InitiatesconversionN.ValiddatafromconversionN–1clockedoutonSDATA. ↓ 0 1 1 Input InitiatesconversionN.Internalclockstillrunsconversionprocess. 0 ↓ 1 1 InitiatesconversionN.Internalclockstillrunsconversionprocess. ↓ 1 1 1 Input ConversionNcompleted.ValiddatafromconversionNclockedoutonSDATA synchronizedtoexternaldataclock. ↓ 1 0 1 Input ValiddatafromconversionN–1outputonSDATAsynchronizedtoexternaldataclock. ConversionNinprogress. 0 ↑ 0 1 Input ValiddatafromconversionN–1outputonSDATAsynchronizedtoexternaldataclock. ConversionNinprogress. 0 0 ↑ X Input Newconversioninitiatedwithoutacquisitionofanewsignal.Dataareinvalid.CSand/or R/CmustbehighwhenBUSYgoeshigh. X X 0 X X Newconvertcommandsignored.ConversionNinprogress.. (1) SeeFigure34,Figure35,andFigure36forconstraintsondatavalidfromconversionN–1. Table4.OutputCodesandIdealInputVoltages DIGITALOUTPUT BINARYTWOSCOMPLEMENT (SB/BTCLOW) STRAIGHTBINARY(SB/BTCHIGH) DESCRIPTION ANALOGINPUT Full-scalerange ±10 0Vto5V 0Vto4V HEX Leastsignificantbit(LSB) 305m V 76m V 61m V BINARYCODE CODE BINARYCODE HEXCODE +Full-scale(FS–1LSB) 9.999695V 4.999924V 3.999939V 0111111111111111 7FFF 1111111111111111 FFFF Midscale 0V 2.5V 2V 0000000000000000 0000 1000000000000000 8000 1LSBbelowmidscale 305m V 2.499924V 1.999939V 1111111111111111 FFFF 0111111111111111 7FFF –Full-scale -10V 0V 0V 1000000000000000 8000 0000000000000000 0000 ParallelOutput To use the parallel output, tie EXT/INT (pin 8) high and DATACLK (pin 18) low. SDATA (pin 19) should be left unconnected. The parallel output is active when R/C (pin 22) is high and CS (pin 23) is low. Any other combination of CS and R/C 3-states the parallel output. Valid conversion data can be read in two 8-bit bytes on D7-D0 (pins 9-13 and 15-17). When BYTE (pin 21) is low, the eight most significant bits are valid with the MSB on D7. When BYTE is high, the eight least significant bits are valid with the LSB on D0. BYTE can be toggled to readbothbyteswithinoneconversioncycle. Uponinitialdevicepower-up,theparalleloutputcontainsindeterminatedata. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):ADS8517

ADS8517 SLAS527A–SEPTEMBER2008–REVISEDJUNE2009................................................................................................................................................. www.ti.com ParallelOutput(AfteraConversion) After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. Valid data from conversion N are available on D7-D0 (pin 9-13 and 15-17). BUSY going high can be used to latch the data.RefertoTable5,Figure30,andFigure31fortimingspecifications. t1 t1 R/C t3 t4 t3 BUSY t6 t5 t6 t7 t8 MODE Acquire Convert Acquire Convert t12 t11 t10 t12 Parallel Previous Previous High Previous Low High Byte Low Byte High Byte Data Bus High Byte Valid Hi-Z Byte Valid Byte Valid Not Valid Valid Valid Hi-Z Valid t2 t9 t9 t12 t12 t12 t12 BYTE Figure30.ConversionTimingWithParallelOutput(CSandDATACLKTiedLow,EXT/INTTiedHigh) t21 t1 t21 t21 t21 R/C t21 t21 CS t3 t4 BUSY t21 t21 BYTE t21 t21 Data Bus Hi-Z State High Byte Hi-Z State Low Byte Hi-Z State t21 t21 t9 t9 Figure31.CStoControlConversionandReadTimingWithParallelOutputs 16 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8517

ADS8517 www.ti.com................................................................................................................................................. SLAS527A–SEPTEMBER2008–REVISEDJUNE2009 ParallelOutput(DuringaConversion) After conversion N has been initiated, valid data from conversion N–1 can be read and are valid up to 2.2 m s after the start of conversion N. Do not attempt to read data beyond 2.2 m s after the start of conversion N until BUSY (pin 24) goes high; doing so may result in reading invalid data. Refer to Table 5, Figure 30, and Figure 31 fortimingconstraints. Table5.ConversionandDataTimingwithParallelInterfaceatT =–40°Cto+85°C A SYMBOL DESCRIPTION MIN TYP MAX UNITS t Convertpulsewidth 0.04 5 m s 1 t DatavaliddelayafterR/Clow 2.3 2.5 m s 2 t BUSYdelayfromstartofconversion 20 85 ns 3 t BUSYlow 2.3 2.5 m s 4 t BUSYdelayafterendofconversion 90 ns 5 t Aperturedelay 40 ns 6 t Conversiontime 1.8 2.2 m s 7 t Acquisitiontime 2.7 m s 8 t Busrelinquishtime 10 83 ns 9 t BUSYdelayafterdatavalid 20 60 ns 10 t Previousdatavalidafterstartofconversion 1.8 2.2 m s 11 t R/CtoCSsetuptime 10 ns 21 t +t Throughputtime 5 m s 7 8 SerialOutput Data can be clocked out with the internal data clock or an external data clock. When using the serial output, be careful with the parallel outputs, D7-D0 (pins 9-13 and 15-17), because these pins come out of a High-Z state whenever CS (pin 23) is low and R/C (pin 22) is high. The serial output cannot be 3-stated and is always active. Refer to the Applications Information section for specific serial interfaces. If an external clock is used, the TAG inputcanbeusedtodaisy-chainmultipleADS8517datapinstogether. InternalDataClock(DuringaConversion) To use the internal data clock, tie EXT/INT (pin 8) low. The combination of R/C (pin 22) and CS (pin 23) low initiates conversion N and activates the internal data clock (typically, a 900-kHz clock rate). The ADS8517 outputs16bitsofvaliddata,MSBfirst,fromconversionN–1onSDATA (pin 19), synchronized to 16 clock pulses output on DATACLK (pin 18). The data are valid on both the rising and falling edges of the internal data clock. The rising edge of BUSY (pin 24) can be used to latch the data. After the 16th clock pulse, DATACLK remains low until the next conversion is initiated, while SDATA returns to the state of the TAG pin input sensed at the startoftransmission.RefertoTable6andFigure33formoreinformation. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):ADS8517

ADS8517 SLAS527A–SEPTEMBER2008–REVISEDJUNE2009................................................................................................................................................. www.ti.com ExternalDataClock To use an external data clock, tie EXT/INT (pin 8) high. The external data clock is not and cannot be synchronized with the internal conversion clock; care must be taken to avoid corrupting the data. To enable the output mode of the ADS8517, CS (pin 23) must be low and R/C (pin 22) must be high. DATACLK must be high for 20% to 70% of the total data clock period; the clock rate can be between dc and 10 MHz. Serial data from conversionNcanbeoutputonSDATA(pin19)afterconversionNcompletesorduringconversionN+1. AnobviouswaytosimplifycontroloftheconverteristotieCSlowanduseR/Ctoinitiateconversions. While this configuration is perfectly acceptable, there is a possible problem when using an external data clock. At an indeterminate point from 12 m s after the start of conversion N until BUSY rises, the internal logic shifts the results of conversion N into the output register. If CS is low, R/C high, and the external clock is high at this point, data are lost. Consequently, with CS low, either R/C and/or DATACLK must be low during this period to avoid losingvaliddata. ExternalDataClock(AfteraConversion) After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. With CS low and R/C high, valid data from conversion N are output on SDATA (pin 19) synchronized to the external data clock input on DATACLK (pin 18). The MSB is valid on the first falling edge and the second rising edge of the external data clock. The LSB is valid on the 16th falling edge and 17th rising edge of the data clock. TAG (pin 20) inputs a bit of data for every external clock pulse. The first bit input on TAG is valid on SDATA on the 17th falling edge and the 18th rising edge of DATACLK; the second input bit is valid on the 18th falling edge and the 19th rising edge, etc. With a continuous data clock, TAG data is output on SDATA until the internal output registers are updated with the results from the next conversion. Refer to Table 6 and Figure 35 for more information. ExternalDataClock(DuringaConversion) After conversion N has been initiated, valid data from conversion N–1 can be read and are valid up to 2.2 m s after the start of conversion N. Do not attempt to clock out data from 2.2 m s after the start of conversion N until BUSY(pin24)rises;doingsoresultsindataloss. NOTE: For the best possible performance when using an external data clock, data should not beclockedoutduringaconversion. The switching noise of the asynchronous data clock can cause digital feedthrough, degrading converter performance.RefertoTable6andFigure36formoreinformation. 18 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8517

ADS8517 www.ti.com................................................................................................................................................. SLAS527A–SEPTEMBER2008–REVISEDJUNE2009 Table6.TimingRequirements(T =–40°Cto+85°C) A PARAMETER MIN TYP MAX UNIT t Pulseduration,convert 0.04 5 m s w1 t Delaytime,BUSYfromR/Clow 20 85 ns d1 t Pulseduration,BUSYlow 2.3 2.5 m s w2 t Delaytime,BUSY,afterendofconversion 90 ns d2 t Delaytime,aperture 40 ns d3 t Conversiontime 2.0 2.2 2.4 m s conv t Acquisitiontime 2.6 2.7 m s acq t +t Cycletime 5 m s conv acq t Delaytime,R/ClowtointernalDATACLKoutput 171 ns d4 t Cycletime,internalDATACLK 92 96 98 ns c1 t Delaytime,datavalidtointernalDATACLKhigh 2 3.5 ns d5 t Delaytime,datavalidafterinternalDATACLKlow 41 43 ns d6 t Cycletime,externalDATACLK 35 ns c2 t Pulseduration,externalDATACLKhigh 15 ns w3 t Pulseduration,externalDATACLKlow 15 ns w4 t Setuptime,R/Crise/falltoexternalDATACLKhigh 15 ns su1 t Setuptime,R/CtransitiontoCStransition 10 ns su2 t Delaytime,datavalidfromexternalDATCLKhigh 2 25 40 ns d8 t Delaytime,CSrisingedgetoexternalDATACLKrisingedge 15 ns d9 t Delaytime,previousdataavailableafterCS,R/Clow 1.8 2.2 m s d10 t Setuptime,BUSYtransitiontofirstexternalDATACLK 5 ns su3 t Delaytime,finalexternalDATACLKtoBUSYrisingedge 825 ns d11 t Setuptime,TAGvalidbeforerisingedgeofDATACLK 2 ns su4 t Holdtime,TAGvalidafterrisingedgeofDATACLK 2 ns h1 CS R/C td9 R/C CS tsu1 tsu1 tsu1 tsu1 External External DATACLK DATACLK CS Set Low, Discontinuous Ext DATACLK R/C Set Low, Discontinuous Ext DATACLK CS BUSY tsu2 tsu2 tsu3 1 2 External R/C DATACLK CS Set Low, Discontinuous Ext DATACLK Figure32.CriticalTimingParameters Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):ADS8517

ADS8517 SLAS527A–SEPTEMBER2008–REVISEDJUNE2009................................................................................................................................................. www.ti.com tw1 tw1 R/C td1 tw2 td1 tw2 BUSY (N + 1)th (N + 2)th td3 td2 td3 td2 td11 td11 STATUS Nth Conversion ECrorrorrection (N+1)th Accquisition (N+1)th Conversion ECrorrorrection (N+2)th Accquisition tconv tacq tconv tacq td4 tc1 td4 Internal DATACLK 1 2 16 1 2 16 td6 td5 SDATA TAG = 0 D15 D0 TAG = 0 D15 D0 TAG = 0 (N−1)th Conversion Data Nth Conversion Data CS, EXT/INT, and TAG are tied low 8starts READ Figure33.BasicConversionTiming:InternalDATACLK(ReadPreviousDataDuringConversion) tw1 tw1 R/C td1 tw2 td1 tw2 BUSY (N + 1)th (N + 2)th td2 td2 td3 td11 td3 td11 STATUS Nth Conversion Error (N+1)th Accquisition (N+1)th ConversionError (N+2)th Accquisition Correction Correction tconv tacq tconv tacq tsu1 tsu3 tsu1 tsu3 External DATACLK 1 16 1 2 16 1 16 1 2 16 No more No more SDATA TAG = 0 dshaitfat otout TAG = 0 Nth Data TAG = 0 dshaitfat otout TAG = 0 (N+1)th Data TAG = 0 EXT/INT tied high, CS and TAG are tied low tw1 + tsu1 starts READ Figure34.BasicConversionTiming:ExternalDATACLK 20 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8517

ADS8517 www.ti.com................................................................................................................................................. SLAS527A–SEPTEMBER2008–REVISEDJUNE2009 tw1 R/C td1 tw2 tsu1 td1 BUSY td2 td3 td11 td3 STATUS NthConversion CEorrrorerction (N+1)thAccquisition tconv tsu3 tacq External tw3tc2 tw4 tsu1 DATACLK 0 1 2 3 4 5 10 11 12 13 14 15 16 SYNC =0 td8 NthConversionData td8 DATA D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 T00 Txx tsu4 th1 TAG T00 T01 T02 T03 T04 T05 T06 T11 T12 T13 T14 T15 T16 T17 Tyy EXT/INTtiedhigh,CStiedlow tw1+tsu1startsREAD Figure35.ReadAfterConversion(DiscontinuousExternalDATACLK) tw1 R/C td1 tw2 BUSY td3 td10 td2 Error STATUS (N + 1)th Conversion Correction tsu3 tconv tc2 tsu1 tw3 tw4 td11 External DATACLK 0 1 2 3 4 5 10 11 12 13 14 15 16 td8 Nth Conversion Data td8 SDATA D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 EXT/INT tied high, CS and TAG tied low Rising DATACLK change DATA, tw1 + tsu1 Starts READ TAG is not recommended for this mode. There is not enough time to do so without violating td11. Figure36.ReadDuringConversion(DiscontinuousExternalDATACLK) Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):ADS8517

ADS8517 SLAS527A–SEPTEMBER2008–REVISEDJUNE2009................................................................................................................................................. www.ti.com TAG FEATURE TheTAGfeatureallows data from multiple ADS8517 converters to be read on a single serial line. The converters are cascaded together using the DATA pins as outputs and the TAG pins as inputs, as illustrated in Figure 37. The DATA pin of the last converter drives the processor serial data input. Data are then shifted through each converter, synchronous to the externally supplied data clock, onto the serial data line. The internal clock cannot beusedforthisconfiguration. The preferred timing uses the discontinuous, external data clock during the sampling period. Data must be read during the sampling period because there is not sufficient time to read data from multiple converters during a conversion period without violating the t constraint (see the External Data Clock section). The sampling period d11 mustbesufficientlylongenoughtoallowalldatawordstobereadbeforestartinganewconversion. Note that in Figure 37, the state of the DATA pin at the end of a READ cycle reflects the state of the TAG pin at the start of the cycle for each converter. The ADS8517 works the same way when it is running in external or internal clock mode. That is, the state of the TAG pin is shown on the DATA pin at the 17th clock after all 16 bits have shifted out. However, it is only practical to use the TAG feature with the external clock mode when multiple ADS8517s are daisy-chained, so that they are running at the same clock speed. For example, when two converters (ADS8517A and ADS8517B) are cascaded together, the 17th external clock cycle brings the MSB dataofADS8517AontotheDATApinofADS8517B. ADS8517A ADS8517B Processor TAG DATA TAG DATA A00 A15 DATA (A) CS CS D Q D Q R/C R/C DATACLK DATACLK SCLK GPIO TAG (B) B00 B15 DATA (B) GPIO D Q D Q SDI DATACLK R/C (both A and B) BUSY (both A and B) SYNC (both A and B) External DATACLK 1 2 3 4 15 16 17 18 19 20 21 32 33 34 DATA (A) A15 A14 A13 A01 A00 TAG(A) = 0 NthConversionData DATA (B) B15 B14 B13 B01 B00 A15 A14 A13 A12 A00 TAG(A) = 0 EXT/INTtiedhigh,CSofbothconverterAandB,TAGinputofconverterAaretiedlow. Figure37.TimingofTAGFeatureWithSingleConversion(UsingExternalDATACLK) 22 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8517

ADS8517 www.ti.com................................................................................................................................................. SLAS527A–SEPTEMBER2008–REVISEDJUNE2009 ANALOG INPUTS The ADS8517 offers three analog input ranges, as shown in Table 1. The offset specification is factory-calibrated with internal resistors. The gain specification is factory-calibrated with 0.1%, 0.25-W external resistors, as shown in Figure 38 and Figure 39. The external resistors can be omitted if a larger gain error is acceptable or if using softwarecalibration.ThehardwaretrimcircuitryshowninFigure38andFigure39canreducetheerrortozero. ±10 V 0 V to 5 V 0 V to 4 V 1 1 1 VIN R1IN R1IN R1IN 2 2 2 AGND1 AGND1 V AGND1 IN 3 R2IN VIN 3 R2IN 3 R2IN 4 +5 V 4 +5 V 4 +5 V 2.2mF+ CAP 2.2mF+ CAP 2.2mF+ CAP 1 MW 5 1 MW 5 1 MW 5 50 kW REF 50 kW REF 50 kW REF + + + 2.2mF 2.2mF 2.2mF 6 6 6 AGND2 AGND2 AGND2 Figure38.CircuitDiagrams(withGainAdjustTrim) ±10 V 0 V to 5 V 0 V to 4 V 1 1 1 VIN R1IN R1IN R1IN 2 2 2 AGND1 AGND1 V AGND1 IN 3 R2IN VIN 3 R2IN 3 R2IN 4 4 4 2.2mF+ CAP 2.2mF+ CAP 2.2mF+ CAP 5 1 MW 5 5 REF REF REF + + + 2.2mF 2.2mF 2.2mF 6 6 6 AGND2 AGND2 AGND2 Figure39.CircuitDiagrams(WithoutGainAdjustTrim) Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):ADS8517

ADS8517 SLAS527A–SEPTEMBER2008–REVISEDJUNE2009................................................................................................................................................. www.ti.com Analog input pins R1 and R2 have ±25-V overvoltage protection. The input signal must be referenced to IN IN AGND1. This referencing minimizes ground-loop problems typical to analog designs. The analog input should be drivenbyalow-impedancesource.AtypicaldrivingcircuitusingtheOPA627orOPA132isshowninFigure40. +15 V 2.2mF 22 pF ADS8517 2 kW 100 nF R1 IN Pin 7 2 kW Pin 1 AGND1 Pin 2 V IN OPA627 Pin 6 R2 22 pF or IN OPA132 Pin 3 Pin 4 CAP EXT/INT 2.2mF 2.2mF REF 2.2mF DGND 100 nF AGND2 -15 V GND GND GND GND GND GND Figure40.TypicalDrivingCircuit(±10V,NoTrim) 24 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8517

ADS8517 www.ti.com................................................................................................................................................. SLAS527A–SEPTEMBER2008–REVISEDJUNE2009 REFERENCE The ADS8517 can operate with the internal 2.5 V reference or an external reference. An external reference connected to pin 5 (REF) bypasses the internal reference. The external reference must drive the 6-kΩ resistor that separates pin 5 from the internal reference (see the front page diagram). The load varies with the difference between the internal and external reference voltages. The internal reference is approximately 2.5 V (range is from 2.48 V to 2.52 V). The external reference voltage can vary from 2.3 V to 2.7 V. The reference, whether internal or external, is buffered internally with the output on pin 4 (CAP). Figure 41 shows characteristic impedancesattheinputandoutputofthebufferwithallcombinationsofpower-downand reference power-down. The reference voltage determines the size of the least significant bit (LSB). The larger reference voltages producealargerLSB,whichcanimproveSNR.SmallerreferencevoltagescandegradeSNR. ZCAP CAP CDAC (Pin 4) Buffer ZREF Internal REF Reference (Pin 5) PWRD 0 PWRD 0 PWRD 1 PWRD 1 REFD 0 REFD 1 REFD 0 REFD 1 ZCAPW 1 1 200 200 ZREFW 6k 1 M 6k 1 M Figure41.CharacteristicImpedancesoftheInternalBuffer The ADS8517 is factory-tested with 2.2 m F capacitors connected to pin 4 (CAP) and pin 5 (REF). Each capacitor should be placed as close as possible to the pin. The capacitor on pin 5 band-limits the internal reference noise. A smaller capacitor can be used, but it may degrade SNR and SINAD. The capacitor on pin 4 stabilizes the reference buffer and provides switching charge to the CDAC during conversion. Capacitors smaller than 1 m F may cause the buffer to become unstable and not hold sufficient charge for the CDAC. The devices are tested to specifications with 2.2 m F, making larger capacitors unnecessary (Figure 42 shows how capacitor values larger than 2.2 m F have little effect on improving performance). The equivalent series resistance (ESR) of these compensation capacitors is also critical; keep the total ESR under 3 Ω. See the Typical Characteristics section concerninghowESRaffectsperformance. 77000000 66000000 s − (cid:1) 55000000 e m Ti 44000000 p U − er 33000000 w o P 22000000 11000000 00 00..11 11 1100 110000 CAP − Pin Value − (cid:1)F Figure42.Power-DowntoPower-UpTimeversusCapacitorValueonCAP Neither the internal reference nor the buffer should be used to drive an external load. Such loading can degrade performance, as shown in Figure 41. Any load on the internal reference causes a voltage drop across the 6-kΩ resistor and affects gain. The internal buffer is capable of driving ±2-mA loads, but any load can cause perturbationsofthereferenceattheCDAC,thusdegradingperformance. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):ADS8517

ADS8517 SLAS527A–SEPTEMBER2008–REVISEDJUNE2009................................................................................................................................................. www.ti.com POWER-DOWN TheADS8517hasanalogpower-downandreferencepower-downcapabilitiesviaPWRD (pin 25) and REFD (pin 26), respectively. PWRD and REFD high powers down all analog circuitry, maintaining data from the previous conversion in the internal registers, provided that the data have not already been shifted out through the serial port. Typical power consumption in this mode is 50 m W. Power recovery is typically 1 ms, using a 2.2-m F capacitor connected to CAP. Figure 42 shows power-down to power-up recovery time relative to the capacitor value on CAP. With +5 V applied to V , the digital circuitry of the ADS8517 remains active at all times, DIG regardlessofPWRDandREFDstates. PWRD PWRD high powers down all of the analog circuitry except for the reference. Data from the previous conversion are maintained in the internal registers and can still be read. With PWRD high, a convert command yields meaninglessdata. REFD REFD high powers down the internal 2.5-V reference. All other analog circuitry, including the reference buffer, is active. REFD should be high when using an external reference to minimize power consumption and the loading effects on the external reference. See Figure 41 for the characteristic impedance of the reference buffer input for bothREFDhighandlow.Theinternalreferenceconsumesapproximately5mW. 26 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8517

ADS8517 www.ti.com................................................................................................................................................. SLAS527A–SEPTEMBER2008–REVISEDJUNE2009 LAYOUT POWER For host processors that are able to advantage of a lower interface supply voltage, the ADS8517 offers a wide range of voltages—from 5.5V to as low as 1.65V. The ADS8517 should be considered as an analog component because, as noted in the Electrical Characteristics, it uses 95% of its power for the analog circuitry. If the interface is at the same +5V as the analog supply, the two +5-V supplies should be separate. Connecting V DIG (pin 28) directly to a digital supply can reduce converter performance because of switching noise from the digital logic.Forbestperformance,the+5-Vsupplyshouldbeproducedfromwhicheveranalogsupplyis present for the restoftheanalogsignalconditioning.Ifa+12-Vor+15-Vsuppyispresentinthesystem,asimple+5-V regulator can be used. Although it is not suggested, if the digital supply in the system must be used to power the converter,besureitisproperlyfiltered. POWER-ON SEQUENCE Care must be taken with power sequencing when the interface and analog supplies are different. Refer to the Absolute Maximum Ratings for details. The analog supply should be powered on before the digital supply (used for the interface). It is important that the voltage difference between V and the digital inputs does not exceed DIG the limit of –0.3V to V + 0.3V. All digital inputs should be kept inactive (logic low) until the digital (interface) DIG supplyissteady. GROUNDING Three ground pins are present on the ADS8517. DGND is the digital supply ground. AGND2 is the analog supply ground. AGND1 is the ground to which all analog signals internal to the A/D converter are referenced. AGND1 is more susceptible to current induced voltage drops and must have the path of least resistance back to the power supply. To achieve optimum performance, all the ground pins of the A/D converter should be tied to an analog ground plane, separated from the system digital logic ground. Both analog and digital ground planes should be tied to the system ground as near to the power supplies as possible. This configuration helps to prevent dynamic digital groundcurrentsfrommodulatingtheanaloggroundthroughacommonimpedancetopowerground. SIGNAL CONDITIONING TheADS8517featureshigh-impedanceinputsastheresultof the resistive input attenuation circuit. For ±10V, 0V to 5V, and 0V to 4V inputs, the equivalent input impedances are 45.7kΩ, 20kΩ and 21.4kΩ respectively. Lower cost op amps may be used to drive the ADC inputs because the driving requirement is not as high compared to other converters. This input circuit not only reduces the power consumption on the signal conditioning op amp, but it also works as a buffer to attenuate any charge injection resulting from the operation of the CDAC FET sampleswitches,eventhoughthedesignofthoseFETswitchesisoptimizedtogiveminimalchargeinjection. Another benefit provided by the ADS8517 high-impedance front-end is assured ±25V overvoltage protection. In mostcases,thisinternalprotectioneliminatestheneedforexternalinputprotectioncircuitry. INTERMEDIATE LATCHES The ADS8517 does have 3-state outputs for the parallel port, but intermediate latches should be used if the bus is active during conversion. If the bus is not active during conversion, the 3-state outputs can be used to isolate theA/Dconverterfromotherperipheralsonthesamebus. Intermediate latches are beneficial on any monolithic A/D converter. The ADS8517 has an internal LSB size of 38 m V (with a 2.5-V internal reference). Transients from fast-switching signals on the parallel port, even when the A/D converter is 3-stated, can be coupled through the substrate to the analog circuitry, causing degradation of converterperformance. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):ADS8517

ADS8517 SLAS527A–SEPTEMBER2008–REVISEDJUNE2009................................................................................................................................................. www.ti.com APPLICATION INFORMATION TRANSITION NOISE Apply a dc input to the ADS8517 and initiate 1000 conversions. The digital output of the converter varies in output codes because of the internal noise of the ADS8517. This variance is true for all 16-bit SAR converters. The transition noise specification found in the Electrical Characteristics section is a statistical figure that representstheonesigmalimitorrmsvalueoftheseoutputcodes. Using a histogram to plot the output codes, the distribution should appear bell-shaped, with the peak of the bell curve representing the nominal output code for the input voltage value. The ±1s , ±2s , and ±3s distributions represent 68.3%, 95.5%, and 99.7%, respectively, of all codes. Multiplying the transition noise (TN) by 6 yields the ±3s distribution, or 99.7%, of all codes. Statistically, up to three codes could fall outside the five-code distribution when executing 1000 conversions. The ADS8517 has a TN of 0.8 LSBs, which yields five output codesfora±3s distribution.Figure43shows16,384conversionhistogramresults. 7740 4230 3855 16 288 247 8 7FFD 7FFE 7FFF 8000 8001 8002 8003 Figure43.Histogramof16,384ConversionswithV =0Vin±10VBipolarRange IN AVERAGING The noise of the converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise is reduced by a factor of 1/√n where n is the number of averages. For example, averaging four conversion results reduces the TN by 1/2 to 0.4 LSBs. Averaging should only be used for input signals with frequenciesneardc. Foracsignals, a digital filter can be used to low-pass filter and decimate the output codes. This action works in a similarmannertoaveraging:foreverydecimationby2,thesignal-to-noiseratioimprovesby3dB. 28 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8517

ADS8517 www.ti.com................................................................................................................................................. SLAS527A–SEPTEMBER2008–REVISEDJUNE2009 ADS8517 AS AN SPI MASTER DEVICE (INT/EXT TIED LOW) Figure 44 shows a simple interface between the ADS8517 and an SPI-equipped microcontroller or TMS320 series digital signal processor (DSP) when using the internal serial data clock. This interface assumes that the microcontroller or DSP is configured as an SPI slave, is capable of receiving 16-bit transfers, and that the ADS8517istheonlyserialperipheralontheSPIbus. Microcontroller ADS8517 TOUT R/C SS BUSY MOSI SDATA SCLK DATACLK EXT/INT SPI Slave CS BYTE SPI Master NOTE:CPOL = 0 (inactive SCLK is LOW) CPHA = 0 or 1 (data valid on either SCLK edge) Figure44.ADS8517asSPIMaster To maintain synchronization with the ADS8517, the microcontroller slave select (SS) input should be connected to the BUSY output of the ADS8517. When a transition from high-to-low occurs on BUSY (indicating the current conversion is in process), the ADS8517 internal SCLK begins shifting the previous conversion data into the MOSI pin of the microcontroller. In this scenario, the CONV input to the ADS8517 can be controlled from an external trigger source, or a trigger generated by the microcontroller. The ADS8517 internal SCLK provides 2 ns (min) of setup time and 41 ns (min) of hold time on the SDATA output (see t and t in Table 6), allowing the d5 d6 microcontrollertosampledataoneithertherisingorfallingedgeofSCLK. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):ADS8517

ADS8517 SLAS527A–SEPTEMBER2008–REVISEDJUNE2009................................................................................................................................................. www.ti.com ADS8517 AS AN SPI SLAVE DEVICE (INT/EXT TIED HIGH) Figure 45 shows another interface between the ADS8517 and an SPI-equipped microcontroller or DSP in which thehostprocessoractsasanSPImasterdevice. Microcontroller ADS8517 VS TOUT R/C EXT/INT INT BUSY MOSI SDATA SCLK DATACLK CS SPI Master BYTE SPI Slave NOTE:CPOL = 0 (inactive SCLK is LOW) CPHA = 1 (data valid on SCLK falling edge) Figure45.ADS8517asSPISlave In this configuration, the data transfer from the ADS8517 is triggered by the rising edge of the serial data clock provided by the SPI master. The SPI interface should be configured to read valid SDATA on the falling edge of SCLK. When a minimum of 17 SCLKs are provided to the ADS8517, data can be strobed to the host processor ontherisingSCLKedgeprovidinga2ns(min)holdtime(seet inTable6). d8 When using an external interrupt to facilitate serial data transfers, as shown in Figure 45, there are two options fortheconfigurationoftheinterruptserviceroutine(ISR):falling-edge-triggeredorrising-edge-triggered. A falling-edge-triggered transfer would initiate an SPI transfer after the falling edge of BUSY, providing the host controllerwiththe previous conversion results, while the current conversion cycle is underway. The timing for this type of interface is described in detail in Figure 36. Care must be taken to ensure the entire 16-bit conversion result is retrieved from the ADS8517 before BUSY returns high to avoid the potential corruption of the current conversioncycle. A rising-edge-triggered transfer is the preferred method of obtaining the conversion results. This timing is depicted in Figure 35. This method of obtaining data ensures that SCLK is static during the conversion cycle and providesthehostprocessorwithcurrentcycleconversionresults. 8-BIT SPI INTERFACE For microcontrollers that only support 8-bit SPI transfers, it is recommended to configure the ADS8517 for SPI slave operation, as depicted in Figure 45. With the microcontroller configured as the SPI master, two 8-bit transfers are required to obtain full 16-bit conversion results from the ADS8517. The eight MSBs of the conversion result are considered valid on the falling SCLK edges of the first transfer, with the remaining four LSBsbeingvalidonthefirstfourfallingSCLKedgesinthesecondtransfer. 30 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8517

ADS8517 www.ti.com................................................................................................................................................. SLAS527A–SEPTEMBER2008–REVISEDJUNE2009 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromOriginal(September2008)toRevisionA ............................................................................................... Page • ChangeddatasheettoreflectTSSOP-28packageavailability............................................................................................. 1 • DeletedleadtemperaturespecificationfromAbsoluteMaximumRatings............................................................................ 2 Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):ADS8517

PACKAGE OPTION ADDENDUM www.ti.com 27-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS8517IBDW ACTIVE SOIC DW 28 20 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS8517I & no Sb/Br) B ADS8517IBPW ACTIVE TSSOP PW 28 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ADS8517I & no Sb/Br) B ADS8517IBPWR ACTIVE TSSOP PW 28 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ADS8517I & no Sb/Br) B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 27-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 22-Feb-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS8517IBPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 22-Feb-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS8517IBPWR TSSOP PW 28 2000 350.0 350.0 43.0 PackMaterials-Page2

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