ADS8365 ADS8365® www.ti.com.................................................................................................................................................... SBAS362C–AUGUST2006–REVISEDMARCH2008 16-Bit, 250kSPS, 6-Channel, Simultaneous Sampling SAR ANALOG-TO-DIGITAL CONVERTERS FEATURES 1 • SixInputChannels DESCRIPTION 2 • FullyDifferentialInputs The ADS8365 includes six, 16-bit, 250kSPS • SixIndependent16-BitADCs analog-to-digital converters (ADCs) with six fully differential input channels grouped into three pairs for • 4m sTotalThroughputperChannel high-speed simultaneous signal acquisition. Inputs to • LowPower: the sample-and-hold amplifiers are fully differential 200mWinNormalMode and are maintained differential to the input of the 5mWinNapMode ADC. This architecture provides excellent 50m WinPower-DownMode common-mode rejection of 80dB at 50kHz, which is importantinhigh-noiseenvironments. • TQFP-64PackagePackage The ADS8365 offers a flexible, high-speed parallel APPLICATIONS interface with a direct address mode, a cycle, and a • MotorControl FIFO mode. The output data for each channel is availableasa16-bitword. • Multi-AxisPositioningSystems • 3-PhasePowerControl CH A0+ CDAC CHA0- S/H Comp Amp SAR HOLDA CH A1+ CDAC Interface A0 CH A1- A1 S/H Comp A2 Amp Conversion and ADD Control NAP CH B0+ CH B0- CDAC RD S/H Comp WR Amp CS FD SAR EOC FIFO CLK HOLDB Reag6nixsdter RESET BYTE CH B1+ CDAC 16 CH B1- S/H Comp Amp Data Input/Output CH C0+ CDAC CH C0- S/H Comp Amp SAR HOLDC CH C1+ CDAC CH C1- S/H Comp Amp REFIN Internal REFOUT 2.5V Reference 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Alltrademarksarethepropertyoftheirrespectiveowners. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2006–2008,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

ADS8365 SBAS362C–AUGUST2006–REVISEDMARCH2008.................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION(1) MAXIMUM NO INTEGRAL MISSING LINEARITY CODES SPECIFIED TRANSPORT ERROR ERROR PACKAGE- PACKAGE TEMPERATURE PACKAGE ORDERING MEDIA, PRODUCT (LSB) (LSB) LEAD DESIGNATOR RANGE MARKING NUMBER QUANTITY ADS8365IPAG Tray,160 ADS8365 ±4 14 TQFP-64 PAG –40(cid:176) Cto+85(cid:176) C ADS8365AI Tapeand ADS8365IPAGR Reel,1500 (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumlocatedattheendofthisdatasheet,orsee theTIwebsiteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) ADS8365 UNIT Supplyvoltage,AGNDtoAV –0.3to6 V DD Supplyvoltage,BGNDtoBV –0.3to6 V DD Analoginputvoltagerange AGND–0.3toAV +0.3 V DD Referenceinputvoltagerange AGND–0.3toAV +0.3 V DD Digitalinputvoltagerange BGND–0.3toBV +0.3 V DD Groundvoltagedifferences,AGNDtoBGND ±0.3 V Voltagedifferences,BV toAGND –0.3to6 V DD Inputcurrenttoanypinexceptsupply –20to20 mA Powerdissipation SeeDissipationRatingsTable Operatingvirtualjunctiontemperaturerange,T –40to+150 (cid:176) C J Operatingfree-airtemperaturerange,T –40to+85 (cid:176) C A Storagetemperaturerange,T –65to+150 (cid:176) C STG (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximumratedconditionsforextendedperiodsmayaffectdevicereliability. DISSIPATION RATINGS DERATING FACTORABOVE T ≤+25(cid:176) C T =+70(cid:176) C T =+85(cid:176) C A A A BOARD PACKAGE Rq JC Rq JA TA=+25(cid:176) C POWERRATING POWERRATING POWERRATING Low-K(1) PAG 8.6(cid:176) C/W 68.5(cid:176) C/W 14.598mW/(cid:176) C 1824mW 1168mW 949mW High-K(2) PAG 8.6(cid:176) C/W 42.8(cid:176) C/W 23.364mW/(cid:176) C 2920mW 1869mW 1519mW (1) TheJEDECLowK(1s)boarddesignusedtoderivethisdatawasa3-inchx3-inch,two-layerboardwith2-ouncecoppertracesontop oftheboard. (2) TheJEDECHighK(2s2p)boarddesignusedtoderivethisdatawasa3-inchx3-inch,multilayerboardwith1-ounceinternalpowerand groundplanes,and2-ouncecoppertracesonthetopandbottomoftheboard. 2 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8365

ADS8365 www.ti.com.................................................................................................................................................... SBAS362C–AUGUST2006–REVISEDMARCH2008 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Supplyvoltage,AV toAGND 4.75 5 5.25 V DD Low-voltagelevels 2.7 3.6 V Supplyvoltage,BV toBGND DD 5Vlogiclevels 4.5 5 5.5 V Referenceinputvoltage 1.5 2.5 2.6 V Operatingcommon-modesignal,–IN 2.2 2.5 2.8 V Analoginputs,+IN–(–IN) 0 ±V V REF Operatingjunctiontemperaturerange,T –40 +125 (cid:176) C J ELECTRICAL CHARACTERISTICS: 100kSPS Overrecommendedoperatingfree-airtemperaturerangeat–40(cid:176) Cto+85(cid:176) C,AV =5V,BV =3V,V =internal+2.5V,f =2MHz,and DD DD REF CLK f =100kSPS,unlessotherwisenoted. SAMPLE ADS8365 PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT ANALOGINPUT Full-scalerange FSR +IN–(–IN) ±VREF V Operatingcommon-modesignal 2.2 2.8 V Inputresistance –IN=VREF 750 Ω Inputcapacitance –IN=VREF 25 pF Inputleakagecurrent –IN=VREF ±1 nA Differentialinputresistance –IN=VREF 1500 Ω Differentialinputcapacitance –IN=VREF 15 pF Atdc 84 dB Common-moderejectionratio CMRR VIN=±1.25VPPat50kHz 80 dB Bandwidth BW FSsinewave,–3dB 10 MHz DCACCURACY Resolution 16 Bits Nomissingcodes NMC 14 Bits Integrallinearityerror INL ±1.5 ±4 LSB Differentialnonlinearity DNL ±1.5 LSB Bipolaroffseterror VOS ±1 ±2.3 mV Bipolaroffseterrormatch Onlypair-wisematching 0.2 1 mV Bipolaroffseterrordrift TCVOS 0.8 ppm/(cid:176)C Gainerror GERR ReferencedtoVREF ±0.05 ±0.25 %FSR Gainerrormatch Onlypair-wisematching 0.005 0.05 %FSR Gainerrordrift TCGERR 2 ppm/(cid:176)C Noise 60 m Vrms Power-supplyrejectionratio PSRR 4.75V<AVDD<5.25V –87 dB SAMPLINGDYNAMICS ConversiontimeperADC tCONV 50kHz≤fCLK≤5MHz 3.2 320 m s Acquisitiontime tAQ fCLK=5MHz 800 ns Aperturedelay 5 ns Aperturedelaymatching 100 ps Aperturejitter 50 ps Clockfrequency 0.05 5 MHz (1) Alltypicalvaluesareat+25(cid:176) C. Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):ADS8365

ADS8365 SBAS362C–AUGUST2006–REVISEDMARCH2008.................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: 100kSPS (continued) Overrecommendedoperatingfree-airtemperaturerangeat–40(cid:176) Cto+85(cid:176) C,AV =5V,BV =3V,V =internal+2.5V,f =2MHz,and DD DD REF CLK f =100kSPS,unlessotherwisenoted. SAMPLE ADS8365 PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT ACACCURACY Totalharmonicdistortion THD VIN=±2.5VPPat50kHz –94 dB Spurious-freedynamicrange SFDR VIN=±2.5VPPat50kHz 95 dB Signal-to-noiseratio SNR VIN=±2.5VPPat10kHz 88 dB Signal-to-noise+distortion SINAD VIN=±2.5VPPat10kHz 87 dB Channel-to-channelisolation 95 dB Effectivenumberofbits ENOB 14.3 Bits VOLTAGEREFERENCEOUTPUT Referencevoltageoutput VOUT 2.475 2.5 2.525 V Initialaccuracy ±1 % Outputvoltagetemperaturedrift dVOUT/dT ±20 ppm/(cid:176)C f=0.1Hzto10Hz,CL=10m F 40 m VPP Outputvoltagenoise f=10Hzto10kHz,CL=10m F 8 m Vrms Power-supplyrejectionratio PSRR 60 dB Outputimpedance ROUT 2 kΩ Short-circuitcurrent ISC 1.25 mA Turn-onsettlingtime to0.1%atCL=0pF 100 m s VOLTAGEREFERENCEINPUT Referencevoltageinput VIN 1.5 2.5 2.6 V Referenceinputresistance 100 MΩ Referenceinputcapacitance 5 pF Referenceinputcurrent 1 µA DIGITALINPUTS(2) Logicfamily CMOS High-levelinputvoltage VIH 0.7· BVDD BVDD+0.3 V Low-levelinputvoltage VIL –0.3 0.3· BVDD V Inputcurrent IIN VI=BVDDorGND ±50 nA Inputcapacitance CI 5 pF DIGITALOUTPUTS(2) Logicfamily CMOS High-leveloutputvoltage VOH BVDD=4.5V,IOH=–100m A 4.44 V Low-leveloutputvoltage VOL BVDD=4.5V,IOL=100m A 0.5 V High-impedancestateoutputcurrent IOZ CS=BVDD,VI=BVDDorGND ±50 nA Outputcapacitance CO 5 pF Loadcapacitance CL 30 pF DIGITALINPUTS(3) Logicfamily LVCMOS High-levelinputvoltage VIH BVDD=3.6V 2 BVDD+0.3 V Low-levelinputvoltage VIL BVDD=2.7V –0.3 0.8 V Inputcurrent IIN VI=BVDDorGND ±50 nA Inputcapacitance CI 5 pF (2) Appliesfor5.0Vnominalsupply:BV (min)=4.5VandBV (max)=5.5V. DD DD (3) Appliesfor3.0Vnominalsupply:BV (min)=2.7VandBV (max)=3.6V. DD DD 4 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8365

ADS8365 www.ti.com.................................................................................................................................................... SBAS362C–AUGUST2006–REVISEDMARCH2008 ELECTRICAL CHARACTERISTICS: 100kSPS (continued) Overrecommendedoperatingfree-airtemperaturerangeat–40(cid:176) Cto+85(cid:176) C,AV =5V,BV =3V,V =internal+2.5V,f =2MHz,and DD DD REF CLK f =100kSPS,unlessotherwisenoted. SAMPLE ADS8365 PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT DIGITALOUTPUTS(4) Logicfamily LVCMOS High-leveloutputvoltage VOH BVDD=2.7V,IOH=–100m A BVDD–0.2 V Low-leveloutputvoltage VOL BVDD=2.7V,IOL=100m A 0.2 V High-impedancestateoutputcurrent IOZ CS=BVDD,VI=BVDDorGND ±50 nA Outputcapacitance CO 5 pF Loadcapacitance CL 30 pF DATAFORMAT BitDB4=1 Binarytwo'scomplement Dataformat BitDB4=0 Straightbinarycoding POWERSUPPLY Analogsupplyvoltage AVDD 4.75 5.25 V Low-voltagelevels 2.7 3.6 V BufferI/Osupplyvoltage BVDD 5Vlogiclevels 4.5 5.5 V Analogoperatingsupplycurrent AIDD 38 45 mA BVDD=3V 60 90 m A BufferI/Ooperatingsupplycurrent BIDD BVDD=5V 100 150 m A BVDD=3V 190 225 mW BVDD=5V 190 225 mW Powerdissipation Napmodeenabled 5 mW Powerdownenabled 50 m W (4) Appliesfor3.0Vnominalsupply:BV (min)=2.7VandBV (max)=3.6V. DD DD Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):ADS8365

ADS8365 SBAS362C–AUGUST2006–REVISEDMARCH2008.................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: 250kSPS Overrecommendedoperatingfree-airtemperaturerangeat–40(cid:176) Cto+85(cid:176) C,AV =5V,BV =3V,V =internal+2.5V,f =5MHz,and DD DD REF CLK f =250kSPS,unlessotherwisenoted SAMPLE ADS8365 PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT ANALOGINPUT Full-scalerange FSR +IN–(–IN) ±VREF V Operatingcommon-modesignal 2.2 2.8 V Inputresistance –IN=VREF 750 Ω Inputcapacitance –IN=VREF 25 pF Inputleakagecurrent –IN=VREF ±1 nA Differentialinputresistance –IN=VREF 1500 Ω Differentialinputcapacitance –IN=VREF 15 pF Atdc 84 dB Common-moderejectionratio CMRR VIN=±1.25VPPat50kHz 80 dB Bandwidth BW FSsinewave,–3dB 10 MHz DCACCURACY Resolution 16 Bits Nomissingcodes NMC 14 Bits Integrallinearityerror INL ±3 ±8 LSB Differentialnonlinearity DNL Specifiedfor14bit ±1.5 LSB Bipolaroffseterror VOS ±1 ±2.3 mV Bipolaroffseterrormatch Onlypair-wisematching 0.2 1 mV Bipolaroffseterrordrift TCVOS 0.8 ppm/(cid:176)C Gainerror GERR ReferencedtoVREF ±0.05 ±0.25 %FSR Gainerrormatch Onlypair-wisematching 0.005 0.05 %FSR Gainerrordrift TCGERR 2 ppm/(cid:176)C Noise 60 m Vrms Power-supplyrejectionratio PSRR 4.75V<AVDD<5.25V –87 dB SAMPLINGDYNAMICS ConversiontimeperADC tCONV 50kHz≤fCLK≤5MHz 3.2 320 m s Acquisitiontime tAQ fCLK=5MHz 800 ns Throughputrate 250 kSPS Aperturedelay 5 ns Aperturedelaymatching 100 ps Aperturejitter 50 ps Clockfrequency 0.05 5 MHz ACACCURACY Totalharmonicdistortion THD VIN=±2.5VPPat50kHz –94 dB Spurious-freedynamicrange SFDR VIN=±2.5VPPat50kHz 95 dB Signal-to-noiseratio SNR VIN=±2.5VPPat10kHz 88 dB Signal-to-noise+distortion SINAD VIN=±2.5VPPat10kHz 87 dB Channel-to-channelisolation 95 dB Effectivenumberofbits ENOB 14.3 Bits (1) Alltypicalvaluesareat+25(cid:176) C. 6 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8365

ADS8365 www.ti.com.................................................................................................................................................... SBAS362C–AUGUST2006–REVISEDMARCH2008 ELECTRICAL CHARACTERISTICS: 250kSPS (continued) Overrecommendedoperatingfree-airtemperaturerangeat–40(cid:176) Cto+85(cid:176) C,AV =5V,BV =3V,V =internal+2.5V,f =5MHz,and DD DD REF CLK f =250kSPS,unlessotherwisenoted SAMPLE ADS8365 PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT VOLTAGEREFERENCEOUTPUT Referencevoltageoutput VOUT 2.475 2.5 2.525 V Initialaccuracy ±1 % Outputvoltagetemperaturedrift dVOUT/dT ±20 ppm/(cid:176)C f=0.1Hzto10Hz,CL=10m F 40 m VPP Outputvoltagenoise f=10Hzto10kHz,CL=10m F 8 m Vrms Power-supplyrejectionratio PSRR 60 dB Outputimpedance ROUT 2 kΩ Short-circuitcurrent ISC 1.25 mA Turn-onsettlingtime to0.1%atCL=0pF 100 m s VOLTAGEREFERENCEINPUT Referencevoltageinput VIN 1.5 2.5 2.6 V Referenceinputresistance 100 MΩ Referenceinputcapacitance 5 pF Referenceinputcurrent 1 µA DIGITALINPUTS(2) Logicfamily CMOS High-levelinputvoltage VIH 0.7· BVDD BVDD+0.3 V Low-levelinputvoltage VIL –0.3 0.3· BVDD V Inputcurrent IIN VI=BVDDorGND ±50 nA Inputcapacitance CI 5 pF DIGITALOUTPUTS(2) Logicfamily CMOS High-leveloutputvoltage VOH BVDD=4.5V,IOH=–100m A 4.44 V Low-leveloutputvoltage VOL BVDD=4.5V,IOL=100m A 0.5 V High-impedancestateoutputcurrent IOZ CS=BVDD,VI=BVDDorGND ±50 nA Outputcapacitance CO 5 pF Loadcapacitance CL 30 pF DIGITALINPUTS(3) Logicfamily LVCMOS High-levelinputvoltage VIH BVDD=3.6V 2 BVDD+0.3 V Low-levelinputvoltage VIL BVDD=2.7V –0.3 0.8 V Inputcurrent IIN VI=BVDDorGND ±50 nA Inputcapacitance CI 5 pF DIGITALOUTPUTS(3) Logicfamily LVCMOS High-leveloutputvoltage VOH BVDD=2.7V,IOH=–100m A BVDD–0.2 V Low-leveloutputvoltage VOL BVDD=2.7V,IOL=100m A 0.2 V High-impedancestateoutputcurrent IOZ CS=BVDD,VI=BVDDorGND ±50 nA Outputcapacitance CO 5 pF Loadcapacitance CL 30 pF (2) Appliesfor5.0Vnominalsupply:BV (min)=4.5VandBV (max)=5.5V. DD DD (3) Appliesfor3.0Vnominalsupply:BV (min)=2.7VandBV (max)=3.6V. DD DD Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):ADS8365

ADS8365 SBAS362C–AUGUST2006–REVISEDMARCH2008.................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: 250kSPS (continued) Overrecommendedoperatingfree-airtemperaturerangeat–40(cid:176) Cto+85(cid:176) C,AV =5V,BV =3V,V =internal+2.5V,f =5MHz,and DD DD REF CLK f =250kSPS,unlessotherwisenoted SAMPLE ADS8365 PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT DATAFORMAT BitDB4=1 Binarytwo'scomplement Dataformat BitDB4=0 Straightbinarycoding POWERSUPPLY Analogsupplyvoltage AVDD 4.75 5.25 V Low-voltagelevels 2.7 3.6 V BufferI/Osupplyvoltage BVDD 5Vlogiclevels 4.5 5.5 V Analogoperatingsupplycurrent AIDD 40 48 mA BVDD=3V 150 225 m A BufferI/Ooperatingsupplycurrent BIDD BVDD=5V 250 375 m A BVDD=3V 200 240 mW BVDD=5V 201 241 mW Powerdissipation Napmodeenabled 5 mW Powerdownenabled 50 m W EQUIVALENT INPUT CIRCUIT AV BV Diode Turn-on Voltage: 0.35V DD DD R C ON (SAMPLE) 750W 20pF A D IN IN AGND BGND Equivalent Analog Input Circuit Equivalent Digital Input Circuit 8 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8365

ADS8365 www.ti.com.................................................................................................................................................... SBAS362C–AUGUST2006–REVISEDMARCH2008 PIN CONFIGURATION PAGPACKAGE TQFP-64 (TOPVIEW) -H A0 H A0+ EFIN EFOUT GND VDD OLDC OLDB OLDA 0 1 2 DD ESET VDD GND C C R R A A H H H A A A A R B B 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CH A1- 1 48 D0 CH A1+ 2 47 D1 AV 3 46 D2 DD AGND 4 45 D3 SGND 5 44 D4 CH B0+ 6 43 D5 CH B0- 7 42 D6 AV 8 41 D7 DD ADS8365 AGND 9 40 D8 SGND 10 39 D9 CH B1- 11 38 D10 CH B1+ 12 37 D11 AV 13 36 D12 DD AGND 14 35 D13 SGND 15 34 D14 CH C0+ 16 33 D15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 -H C0 -H C1 H C1+ NAP AGND AVDD BYTE BVDD BGND FD EOC CLK RD WR CS BGND C C C TERMINALFUNCTIONS TERMINAL NAME NO. I/O(1) DESCRIPTION CHA1– 1 AI InvertinginputchannelA1 CHA1+ 2 AI NoninvertinginputchannelA1 AVDD 3 P Analogpowersupply AGND 4 P Analogground SGND 5 P SignalGround CHB0+ 6 AI NoninvertinginputchannelB0 CHB0– 7 AI InvertinginputchannelB0 AVDD 8 P Analogpowersupply AGND 9 P Analogground SGND 10 P Signalground CHB1– 11 AI InvertinginputchannelB1 CHB1+ 12 AI NoninvertinginputchannelB1 AVDD 13 P Analogpowersupply AGND 14 P Analogground SGND 15 P Signalground CHC0+ 16 AI NoninvertinginputchannelC0 CHC0– 17 AI InvertinginputchannelC0 CHC1– 18 AI InvertinginputchannelC1 (1) AI=AnalogInput,AO=AnalogOutput,DI=DigitalInput,DO=DigitalOutput,DIO=DigitalInput/Output,andP=PowerSupply Connection. Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):ADS8365

ADS8365 SBAS362C–AUGUST2006–REVISEDMARCH2008.................................................................................................................................................... www.ti.com TERMINALFUNCTIONS(continued) TERMINAL NAME NO. I/O(1) DESCRIPTION CHC1+ 19 AI NoninvertinginputchannelC1 NAP 20 DI Napmode.Lowlevelorunconnected=normaloperation;highlevel=Napmode. AGND 21 P Analogground AVDD 22 P +5Vpowersupply BYTE 23 DI 2x8outputcapability(activehigh) BVDD 24 P Powersupplyfordigitalinterfacefrom3Vto5V BGND 25 P Bufferdigitalground FD 26 DO Firstdata(A0data) EOC 27 DO Endofconversion(activelow) AnexternalCMOScompatibleclockcanbeappliedtotheCLKinputtosynchronizetheconversionprocesstoan CLK 28 DI externalsource. RD 29 DI Read(activelow) WR 30 DI Write(activelow) CS 31 DI Chipselect(activelow) BGND 32 P Bufferdigitalground D15 33 DO Databit15(MSB) D14 34 DO Databit14 D13 35 DO Databit13 D12 36 DO Databit12 D11 37 DO Databit11 D10 38 DO Databit10 D9 39 DO Databit9 D8 40 DO Databit8 D7 41 DIO Databit7(softwareinput7) D6 42 DIO Databit6(softwareinput6) D5 43 DIO Databit5(softwareinput5) D4 44 DIO Databit4(softwareinput4) D3 45 DIO Databit3(softwareinput3) D2 46 DIO Databit2(softwareinput2) D1 47 DIO Databit1(softwareinput1) D0 48 DIO Databit0(softwareinput0)(LSB) BGND 49 P Bufferdigitalground BVDD 50 P Powersupplyfordigitalinterfacefrom3Vto5V RESET 51 DI Globalreset(activelow) ADD 52 DI Addressmodeselect A2 53 DI Addressline3 A1 54 DI Addressline2 A0 55 DI Addressline1 HOLDA 56 DI HoldcommandA(activelow) HOLDB 57 DI HoldcommandB(activelow) HOLDC 58 DI HoldcommandC(activelow) AVDD 59 P Analogpowersupply AGND 60 P Analogground REFOUT 61 AO Referenceoutput;attach0.1m Fand10m Fcapacitors REFIN 62 AI Referenceinput CHA0+ 63 AI NoninvertinginputchannelA0 CHA0– 64 AI InvertinginputchannelA0 10 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8365

ADS8365 www.ti.com.................................................................................................................................................... SBAS362C–AUGUST2006–REVISEDMARCH2008 TIMING INFORMATION t C1 CLK 1 2 16 17 18 19 20 1 2 t W1 CONVERSION ACQUISITION tD1 tCONV tACQ HOLDX t W3 t W2 EOC CS tD4 tW6 tD5 RD t W5 t t D7 D6 D15–D8 Bits 15–8 Bits 15–8 D7–D0 Bits 7–0 Bits 7–0 BYTE Figure1.ReadandConvertTiming CS WR WRorCS DB7:0 t t t D10 W6 D11 Figure2.WriteTiming Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):ADS8365

ADS8365 SBAS362C–AUGUST2006–REVISEDMARCH2008.................................................................................................................................................... www.ti.com TIMING CHARACTERISTICS(1)(2)(3)(4) Overrecommendedoperatingfree-airtemperaturerange,T toT ,AV =5V,REF =REF ,V =internal+2.5V, MIN MAX DD IN OUT REF f =5MHz,f =250kSPS,andBV =2.7to5V,unlessotherwisenoted, CLK SAMPLE DD SYMBOL DESCRIPTION MIN TYP MAX UNIT t Acquisitiontime 0.8 m s ACQ t Conversiontime 3.2 m s CONV t CycletimeofCLK 200 ns C1 t (5) DelaytimeofrisingedgeofCLKafterfallingedgeofHOLDX 10 ns D1 BV =5V 20 ns DD t DelaytimeoffirstholdafterRESET D2 BV =3V 40 ns DD t DelaytimeoffallingedgeofRDafterfallingedgeofCS 0 ns D4 t DelaytimeofrisingedgeofCSafterrisingedgeofRD 0 ns D5 BV =5V 40 ns DD t DelaytimeofdatavalidafterfallingedgeofRD D6 BV =3V 60 ns DD BV =5V 5 ns DD t DelaytimeofdataholdfromrisingedgeofRD D7 BV =3V 10 ns DD BV =5V 50 ns DD t DelaytimeofRDhighafterCSlow D8 BV =3V 60 ns DD BV =5V 10 ns DD t DelaytimeofRDlowafteraddresssetup D9 BV =3V 20 ns DD BV =5V 10 ns DD t DelaytimeofdatavalidtoWRlow D10 BV =3V 20 ns DD BV =5V 10 ns DD t DelaytimeofWRorCShightodatarelease D11 BV =3V 20 ns DD t PulsewidthCLKhightimeorlowtime 60 ns W1 BV =5V 15 ns DD t PulsewidthofHOLDXhightimetoberecognizedagain W2 BV =3V 30 ns DD BV =5V 20 ns DD t PulsewidthofHOLDXlowtime W3 BV =3V 30 ns DD BV =5V 20 ns DD t PulsewidthofRESET W4 BV =3V 40 ns DD BV =5V 30 ns DD t PulsewidthofRDhightime W5 BV =3V 40 ns DD BV =5V 50 ns DD t PulsewidthofRDandCSbothlowtime W6 BV =3V 70 ns DD (1) Assuredbydesign. (2) Allinputsignalsarespecifiedwithrisetimeandfalltime=5ns(10%to90%ofBV )andtimedfromavoltagelevelof(V +V )/2. DD IL IH (3) SeeFigure1. (4) BYTEisasynchronous;whenBYTEis0,bits15to0appearatDB15toDB0.WhenBYTEis1,bits15to8appearonDB7toDB0.RD mayremainLOWbetweenchangesinBYTE. (5) Onlyimportantwhensynchronizationtoclockisimportant. 12 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8365

ADS8365 www.ti.com.................................................................................................................................................... SBAS362C–AUGUST2006–REVISEDMARCH2008 TYPICAL CHARACTERISTICS AtT =+25(cid:176) C,AV =+5V,BV =+3V,V =internal+2.5V,f =5MHz,andf =250kSPS,unlessotherwisenoted. A DD DD REF CLK SAMPLE INTEGRALLINEARITYERROR DIFFERENTIALLINEARITYERROR vsCODE(100kSPS) vsCODE(100kSPS) 4 2.0 3 1.5 2 1.0 B) 1 B) S S NL (L 0 NL (L 0.5 I 1 D 0 2 -0.5 3 4 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65535 0 8192 16384 24576 32768 40960 49152 57344 65535 Code Code Figure3. Figure4. MINIMUMANDMAXIMUMINLOFALLCHANNELS MINIMUMANDMAXIMUMINLOFALLCHANNELS vsTEMPERATURE(100kSPS) vsTEMPERATURE(250kSPS) 1.5 1.5 Max 1.0 1.0 Max 0.5 0.5 0 0 B) B) S S L (L -0.5 L (L -0.5 IN -1.0 Min IN -1.0 Min -1.5 -1.5 -2.0 -2.0 -2.5 -2.5 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) Figure5. Figure6. MINIMUMANDMAXIMUMDNLOFALLCHANNELS MINIMUMANDMAXIMUMDNLOFALLCHANNELS vsTEMPERATURE(100kSPS) vsTEMPERATURE(250kSPS) 3.0 3.0 2.5 2.5 Max 2.0 Max 2.0 1.5 1.5 B) 1.0 B) 1.0 S S L (L 0.5 L (L 0.5 DN 0 DN 0 -0.5 -0.5 Min Min -1.0 -1.0 -1.5 -1.5 -2.0 -2.0 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) Figure7. Figure8. Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):ADS8365

ADS8365 SBAS362C–AUGUST2006–REVISEDMARCH2008.................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) AtT =+25(cid:176) C,AV =+5V,BV =+3V,V =internal+2.5V,f =5MHz,andf =250kSPS,unlessotherwisenoted. A DD DD REF CLK SAMPLE FREQUENCYSPECTRUM FREQUENCYSPECTRUM (16384pointFFT,f =10kHz,–0.2dB) (16384pointFFT,f =45kHz,–0.2dB) IN IN 0 0 -20 -20 -40 -40 dB) -60 dB) -60 e ( e ( d -80 d -80 u u mplit -100 mplit -100 A A -120 -120 -140 -140 -160 -160 0 25 50 75 100 125 0 25 50 75 100 125 Frequency (kHz) Frequency (kHz) Figure9. Figure10. SIGNAL-TO-NOISERATIOAND SPURIOUS-FREEDYNAMICRANGEAND SIGNAL-TO-NOISE+DISTORTION TOTALHARMONICDISTORTION vsINPUTFREQUENCY(ALLCHANNELS) vsINPUTFREQUENCY(ALLCHANNELS) 100 120 115 95 D (dB) 90 D (dB) 111005 SFDR SINA 85 SNR d TH 100 THD and SINAD R an 95 R 80 D N F S S 90 75 85 70 80 1 10 100 1 10 100 Frequency (kHz) Frequency (kHz) Figure11. Figure12. SIGNAL-TO-NOISERATIOAND SPURIOUS-FREEDYNAMICRANGEAND SIGNAL-TO-NOISE+DISTORTION TOTALHARMONICDISTORTION vsTEMPERATURE(ALLCHANNELS) vsTEMPERATURE(ALLCHANNELS) 90.0 107 89.5 105 89.0 NR (dB) 8888..50 HD (dB) 103 SFDR S T D and 8877..50 SNR R and 101 THD A D 99 N 86.5 F SI SINAD S 86.0 97 85.5 85.0 95 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) Figure13. Figure14. 14 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8365

ADS8365 www.ti.com.................................................................................................................................................... SBAS362C–AUGUST2006–REVISEDMARCH2008 TYPICAL CHARACTERISTICS (continued) AtT =+25(cid:176) C,AV =+5V,BV =+3V,V =internal+2.5V,f =5MHz,andf =250kSPS,unlessotherwisenoted. A DD DD REF CLK SAMPLE OFFSETOFALLCHANNELS OFFSETMATCHINGOFCHANNELPAIRS vsTEMPERATURE vsTEMPERATURE -0.8 0.25 0.20 -0.9 0.15 -1.0 C0 mV) 0.10 Offset (mV) --11..12 CBB110 AA01 Offset Matching ( --000...0015500 AB -1.3 -0.15 C -0.20 -1.4 -0.25 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) Figure15. Figure16. GAINERROROFALLCHANNELS GAIN-ERRORMATCHINGOFCHANNELPAIRS vsTEMPERATURE vsTEMPERATURE 100 100 B1 A0 B0 R) 50 A1 R) 50 m FS 0 m FS 0 CB or (pp C1 ch (pp A Err -50 C0 Mat -50 Gain -100 Gain -100 -150 -150 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) Figure17. Figure18. REFERENCEVOLTAGEOUTPUT ANALOGSUPPLYCURRENT vsTEMPERATURE vsTEMPERATURE 2.498 42 40 2.496 250kSPS 38 (V)T mA) EFOU 2.494 DA ( 36 100kSPS R D V I 34 2.492 32 2.490 30 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) Figure19. Figure20. Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):ADS8365

ADS8365 SBAS362C–AUGUST2006–REVISEDMARCH2008.................................................................................................................................................... www.ti.com INTRODUCTION 5ns. The average delta of repeated aperture delay The ADS8365 is a high-speed, low-power, values (also known as aperture jitter) is typically six-channel simultaneous sampling and converting, 50ps. These specifications reflect the ability of the 16-bit ADC that operates from a single +5V supply. ADS8365tocaptureacinputsignals accurately at the The input channels are fully differential with a typical exactsamemomentintime. common-mode rejection of 80dB. The ADS8365 contains six 4m s successive approximation ADCs, six REFERENCE differential sample-and-hold amplifiers, an internal +2.5V reference with REF and REF pins, and a Under normal operation, REF (pin 61) can be IN OUT OUT high-speed parallel interface. There are six analog directly connected to REF (pin 62) to provide an IN inputsthataregrouped into three channel pairs (A, B, internal +2.5V reference to the ADS8365. The and C). There are six ADCs, one for each input that ADS8365 can operate, however, with an external can be sampled and converted simultaneously, thus reference in the range of 1.5V to 2.6V, for a preserving the relative phase information of the corresponding full-scale range of 3.0V to 5.2V, as signals on both analog inputs. Each pair of channels long as the input does not exceed the AV + 0.3V DD has a hold signal (HOLDA, HOLDB, and HOLDC) to limit. allow simultaneous sampling on each channel pair, The reference output of the ADS8365 has an on four or on all six channels. The part accepts a impedance of 2kΩ. The high impedance reference differential analog input voltage in the range of –V REF input can be driven directly. For an external resistive to +V , centered on the common-mode voltage REF load, an additional buffer is required. A load (see the Analog Input section). The ADS8365 also capacitance of 0.1m F to 10m F should be applied to accepts bipolar input ranges when a level shift circuit the reference output to minimize noise. If an external isusedatthefrontend(seeFigure26). reference is used, the three input buffers provide A conversion is initiated on the ADS8365 by bringing isolation between the external reference and the the HOLDX pin low for a minimum of 20ns. HOLDX CDACs. These buffers are also used to recharge all low places the sample-and-hold amplifiers of the X thecapacitorsofallCDACsduringconversion. channels in the hold state simultaneously and the conversion process is started on each channel. The ANALOG INPUT EOC output goes low for half a clock cycle when the conversion is latched into the output register. The Theanaloginputisbipolarand fully differential. There data can be read from the parallel output bus are two general methods of driving the analog input following the conversion by bringing both RD and CS of the ADS8365: single-ended or differential, as low. Conversion time for the ADS8365 is 3.2m s when shown in Figure 21 and Figure 22. When the input is a 5MHz external clock is used. The corresponding single-ended, the –IN input is held at the acquisition time is 0.8m s. To achieve the maximum common-mode voltage. The +IN input swings around output data rate (250kSPS), the read function can be the same common voltage and the peak-to-peak performed during the next conversion. NOTE: This amplitude is the (common-mode + VREF) and the mode of operation is described in more detail in the (common-mode–VREF).ThevalueofVREFdetermines TimingandControlsectionofthisdatasheet. the range over which the common-mode voltage may vary(seeFigure23). SAMPLE AND HOLD Single-Ended Input The sample-and-hold amplifiers on the ADS8365 allow the ADCs to accurately convert an input sine -V to +V wave of full-scale amplitude to 16-bit resolution. The REF REF ADS8365 peak-to-peak input bandwidth of the sample-and-hold amplifiers is Common greater than the Nyquist rate (Nyquist = 1/2 of the Voltage sampling rate) of the ADC, even when the ADC is operatedatitsmaximumthroughputrateof250kSPS. Differential Input The typical small-signal bandwidth of the sample-and-hold amplifiers is 10MHz. Typical V REF aperture delay time (or the time it takes for the peak-to-peak ADS8365 ADS8365 to switch from the sample to the hold mode Common V following the negative edge of the HOLDX signal) is Voltage peRaEFk-to-peak Figure21.MethodsofDrivingtheADS8365 Single-EndedorDifferential 16 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8365

ADS8365 www.ti.com.................................................................................................................................................... SBAS362C–AUGUST2006–REVISEDMARCH2008 CM+V +IN REF +V REF CMVoltage -IN = CM Voltage -V REF CM-V t REF Single-Ended Inputs +IN CM+1/2V REF +V REF CMVoltage -V REF -IN CM-1/2V t REF Differential Inputs NOTES: (+IN)(cid:1)(−IN) Common−mode voltage (Differential mode) = . Common−mode voltage (Single−ended mode) = −IN 2 Themaximumdifferentialvoltagebetween+INand–INoftheADS8365isV .SeeFigure23andFigure24fora REF furtherexplanationofthecommonvoltagerangeforsingle-endedanddifferentialinputs. Figure22.UsingtheADS8365intheSingle-EndedandDifferentialInputModes 5 AVDD= 5V 5 4.55 AVDD= 5V mon-Mode Voltage Range (V) 4321 13..28Single-Ended Input 22..37 mon-Mode Voltage Range (V) 4321 Differential Input 41..00 Com 0 Com 0 0.45 -1 -1 2.6 2.6 1.0 1.5 2.0 2.5 3.0 1.0 1.5 2.0 2.5 3.0 V (V) V (V) REF REF Figure23.Single-EndedInput:Common-Mode Figure24.DifferentialInput:Common-Mode VoltageRangevsV VoltageRangevsV REF REF When the input is differential, the amplitude of the In each case, care should be taken to ensure that the input is the difference between the +IN and –IN input, output impedance of the sources driving the +IN and or: (+IN) – (–IN). The peak-to-peak amplitude of each –IN inputs are matched. Often, a small capacitor input is ±1/2V around this common voltage. (20pF) between the positive and negative input helps REF However, since the inputs are 180(cid:176) out-of-phase, the to match the impedance. Otherwise, a mismatch may peak-to-peak amplitude of the differential voltage is result in offset error, which will change with both +V to –V . The value of V also determines temperatureandinputvoltage. REF REF REF the range of the voltage that may be common to both The input current on the analog inputs depends on a inputs,asshowninFigure24. number of factors, such as sample rate or input Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):ADS8365

ADS8365 SBAS362C–AUGUST2006–REVISEDMARCH2008.................................................................................................................................................... www.ti.com voltage. Essentially, the current into the ADS8365 BIPOLAR INPUTS charges the internal capacitor array during the The differential inputs of the ADS8365 were designed sampling period. After this capacitance has been fully toacceptbipolarinputs(–V and +V ) around the charged, there is no further input current. The source REF REF common-mode voltage (2.5V), which corresponds to of the analog input voltage must be able to charge a 0V to 5V input range with a 2.5V reference. By the input capacitance (25pF) to a 16-bit settling level using a simple op amp circuit featuring four, within three clock cycles if the minimum acquisition high-precision external resistors, the ADS8365 can time is used. When the converter goes into the hold be configured to accept a bipolar input range. The mode, the input impedance is greater than 1GΩ. conventional ±2.5V, ±5V, and ±10V input ranges Care must be taken regarding the absolute analog could be interfaced to the ADS8365 using the resistor input voltage. The +IN and –IN inputs should always valuesshowninFigure26. remain within the range of AGND – 0.3V to AV + DD 0.3V. R The OPA365 is a good choice for driving the analog 1 inputsina5V,single-supplyapplication. 4kW 1.2kW TRANSITION NOISE 20kW OPA227 +IN Bipolar 1.2kW The transition noise of the ADS8365 itself is low, as Input -IN shown in Figure 25 These histograms were R ADS8365 generated by applying a low-noise dc input and 2 initiating 8000 conversions. The digital output of the OPA227 ADC will vary in output code due to the internal noise REFOUT(pin 61) 2.5V of the ADS8365; this feature is true for all 16-bit, successive approximation register (SAR) type ADCs. BIPOLAR INPUT R1 R2 Using a histogram to plot the output codes, the ±10V 1kW 5kW ±5V 2kW 10kW distribution should appear bell-shaped, with the peak ±2.5V 4kW 20kW of the bell curve representing the nominal code for the input value. The ±1s , ±2s , and ±3s distributions representthe68.3%,95.5%,and 99.7%, respectively, Figure26.LevelShiftCircuitforBipolarInput ofallcodes.The transition noise can be calculated by Ranges dividing the number of codes measured by 6, yielding the ±3s distribution, or 99.7%, of all codes. TIMING AND CONTROL Statistically, up to three codes could fall outside the distribution when executing 1000 conversions. The ADS8365 uses an external clock (CLK, pin 28) Remember, in order to achieve this low-noise that controls the conversion rate of the CDAC. With a performance, the peak-to-peak noise of the input 5MHz external clock, the ADC sampling rate is signalandreferencemustbe<50m V. 250kSPS which corresponds to a 4m s maximum throughput time. Acquisition and conversion take a totalof20clockcycles. 4000 3379 3500 3290 3000 es 2500 c n e 2000 urr cc 1500 O 1000 649 603 500 42 37 0 32782 32783 32784 32785 32786 32787 Code Figure25.8000ConversionHistogramofaDC Input 18 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8365

ADS8365 www.ti.com.................................................................................................................................................... SBAS362C–AUGUST2006–REVISEDMARCH2008 THEORY OF OPERATION andalltheoutputregisters,abortsany The ADS8365 contains six 16-bit ADCs that can conversioninprocess,andclosesthe operate simultaneously in pairs. The three hold samplingswitches.Theresetsignalmuststay signals (HOLDA, HOLDB, and HOLDC) initiate the lowforatleast20ns(seeFigure27,t ).The conversion on the specific channels. A simultaneous W4 resetsignalshouldbebackhighforatleast hold on all six channels can occur with all three hold 20ns(Figure27,t )beforestartingthenext signals strobed together. The converted values are D2 conversion(negativeholdedge). saved in six registers. For each read operation, the ADS8365 outputs 16 bits of information (16 data or 3 EOC Endofconversiongoeslowwhennewdata channel address, data valid, and some fromtheinternalADCarelatchedintothe synchronization information). The address/mode outputregisters,whichusuallyhappens16.5 signals (A0, A1, and A2) select how the data are read clockcyclesafterholdinitiatedtheconversion. from the ADS8365. These address/mode signals can Itremainslowforhalfaclockcycle.Ifmore define a selection of a single channel, a cycle mode thanonechannelpairisconverted that cycles through all channels, or a FIFO mode that simultaneously,theA-channelsgetstoredto sequences the data determined by the order of the theregistersfirst(16.5clockcyclesafterhold), hold signals. The FIFO mode will allow the six followedbytheB-channelsoneclockcycle registers to be used by a single-channel pair; later,andfinallytheC-channelsanotherclock therefore, three locations for CH X0 and three cyclelater.Ifareading(bothRDandCSare locations for CH X1 can be updated before they are low)isinprocess,thenthelatchprocessis readfromthedevice. delayeduntilthereadoperationisfinished. FD FirstdataorA0dataarehighifchannelA0is EXPLANATION OF CLOCK, RESET, FD, AND chosentobereadnext.InFIFOmode,the EOC PINS channel(X0)thatiswrittentotheFIFOfirstis Clock Anexternalclockhastobeprovidedforthe latchedintotheA0register.Forexample, ADS8365.Themaximumclockfrequencyis whentheFIFOisempty,FDis0.Thefirst 5MHz.Theminimumclockcycleis200ns(see resultlatchedintotheFIFOregisterA0is, Figure1,t ),andtheclockhastoremainhigh therefore,chosentobereadnext,andFD C1 (Figure1,t )orlowforatleast60ns. rises.Afterthefirstchannelisread(oneto W1 threereadcycles,dependingonBYTEand RESET BringingtheRESETsignallowwillresetthe ADD),FDgoeslowagain. ADS8365.Resettingclearsthecontrolregister t C1 CLK tW1 tD1 HOLD A tW3 HOLD B tD2 tW2 HOLD C tW4 RESET Figure27.StartoftheConversion Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):ADS8365

ADS8365 SBAS362C–AUGUST2006–REVISEDMARCH2008.................................................................................................................................................... www.ti.com START OF A CONVERSION AND READING The ADS8365 can also convert one channel DATA continuously (see Figure 28). Therefore, HOLDA and HOLDC are kept high all the time. To gain acquisition By bringing one, two, or all three of the HOLDX time, the falling edge of HOLDB takes place just signals low, the input data of the corresponding before the rising edge of clock. One conversion channel X are immediately placed in the hold mode requires20clockcycles.Here,dataarereadafter the (5ns). The conversion of this channel X follows with next conversion is initiated by HOLDB. To read data the next rising edge of clock. If it is important to from channel B, A1 is set high and A2 is low. Since detect a hold command during a certain clock-cycle, A0 is low during the first reading (A2 A1 A0 = 010), thenthefallingedgeof the hold signal has to occur at data B0 are put to the output. Before the second RD, least 10ns before the rising edge of clock, as shown A0 switches high (A2 A1 A0 = 011) so that data from in Figure 27, t . The hold signal can remain low D1 channel B1 are read, as shown in Table 1. However, without initiating a new conversion. The hold signal reading data during the conversion or on a falling must be high for at least 15ns (as shown in holdedgemightcausealossinperformance. Figure 27, t ) before it is brought low again, and W2 holdmuststaylowforatleast20ns(Figure27,t ). W3 Table1.AddressControlforRDFunctions Once a particular hold signal goes low, further A2 A1 A0 CHANNELTOBEREAD impulses of this hold signal are ignored until the 0 0 0 CHA0 conversion is finished or the device is reset. When the conversion is finished (after 16 clock cycles) the 0 0 1 CHA1 sampling switches close and sample the selected 0 1 0 CHB0 channel. The start of the next conversion must be 0 1 1 CHB1 delayed to allow the input capacitor of the ADS8365 1 0 0 CHC0 to be fully charged. This delay time depends on the 1 0 1 CHC1 drivingamplifier,butshouldbeatleast800ns. CyclemodereadsregistersCHA0 1 1 0 toCHC1onsuccessivetransitions ofthereadline 1 1 1 FIFOmode CONVERSION ACQUISITION CLK 1 2 16 17 18 19 20 1 2 HOLD B EOC CS RD A0 Figure28.TimingofOneConversionCycle 20 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8365

ADS8365 www.ti.com.................................................................................................................................................... SBAS362C–AUGUST2006–REVISEDMARCH2008 Readingdata(RDandCS) CS being low tells the ADS8365 that the bus on the board is assigned to the ADS8365. If an ADC shares In general, the channel/data outputs are in tri-state. a bus with digital gates, there is a possibility that Both CS and RD must be low to enable these digital (high-frequency) noise will be coupled into the outputs. RD and CS must stay low together for at ADC. If the bus is just used by the ADS8365, CS can least 40ns (see Figure 1, t ) before the output data D6 be hardwired to ground. Reading data at the falling are valid. RD must remain HIGH for at least 30ns edgeofoneoftheHOLDXsignalsmightcausenoise. (see Figure 1, t ) before bringing it back low for a W5 subsequentreadcommand. BYTE The new data are latched into its output register 16.5 If there is only an 8-bit bus available on a board, then clockcyclesafter the start of a conversion (next rising BYTE can be set high (see Figure 29). In this case, edge of clock after the falling edge of HOLDX). Even the lower eight bits can be read at the output pins if the ADS8365 is forced to wait until the read D15 to D8 or D7 to D0 at the first RD signal, and the process is finished (RD signal going high) before the higher bits after the second RD signal. If the new data are latched into its output register, the ADS8365 is used in the cycle or the FIFO mode, then possibility still exists that the new data was latched to theaddressanddatavalidinformationisaddedto the the output register just before the falling edge of RD. data (if ADD is high). In this case, the address will be If a read process is initiated around 16.5 clock cycles read first, then the lower eight bits, and finally the after the conversion started, RD and CS should stay higher eight bits. If BYTE is low, then the ADS8365 low for at least 50ns (see Figure 1, t ) to get the W6 operates in the 16-bit output mode. Here, data are new data stored to its register and switched to the readbetweenpinsDB15andDB0.As long as ADD is output. low, with every RD impulse, data from a new channel are brought to the output. If ADD is high and the cycle or the FIFO mode is chosen; the first output word contains the address, while the second output wordcontainsthe16-bitdata. CS RD BYTE A0 A0 A1 A1 B0 B0 B1 C0 C1 A0 D7–D0 LOW HIGH LOW HIGH LOW HIGH Figure29.ReadingDatainCyclingMode Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):ADS8365

ADS8365 SBAS362C–AUGUST2006–REVISEDMARCH2008.................................................................................................................................................... www.ti.com ADDSignal In the cycle and the FIFO mode, it might be desirable If conversion timing between ADCs is not critical, Soft to have address information with the 16-bit output Trigger mode can allow all three HOLDX signals to data. Therefore, ADD can be set high. In this case, be triggered simultaneously. This simultaneous two RD signals (or three readings if the part is triggering can be done by tying all three HOLDX pins operated with BYTE being high) are necessary to high, and issuing a write (CS and WR low) with the read data of one channel, while the ADS8365 DB0, DB1, DB2, and DB7 bits low, and the reset bit provides channel information on the first RD signal (DB3) high. Writing a low to the reset bit (DB3) while (seeTable2andTable3). the RESET pin is high forces a device reset, and all HOLDX signals that occur during that time are SoftTriggerMode ignored. Signals NAP, ADD, A0, A1, A2, RESET, HOLDA, The HOLDX signals start conversion automatically on HOLDB, and HOLDC are accessible through the data the next clock cycle. The format of the two words that bus and control word. Bits NAP, ADD, A0, A1 and A2 canbewrittentotheADS8365areshowninTable4. are in an OR configuration with hardware pins. When Bits DB5 and DB4 do not have corresponding software configuration is used, these pins must be hardware pins. Bit DB5 = 1 enables Powerdown connected to ground. Conversely, the RESET, mode. Bit DB4 = 1 inverts the MSB of the output HOLDA, HOLDB, and HOLDC bits are in a NAND data, putting the output data in two's complement configuration with the hardware pins. When software format. When DB4 is low, the data is in straight configuration is used, these pins must be connected binaryformat. toBV . DD Table2.OverviewoftheOutputFormatsDependingonModeWhenADD=0 ADD=0 BYTE=0 BYTE=1 A2A1A0 1stRD 2ndRD 1stRD 2ndRD 3rdRD 000 DB15...DB0 No2ndRD DB7...DB0 DB15...DB8 No3rdRD 001 DB15...DB0 No2ndRD DB7...DB0 DB15...DB8 No3rdRD 010 DB15...DB0 No2ndRD DB7...DB0 DB15...DB8 No3rdRD 011 DB15...DB0 No2ndRD DB7...DB0 DB15...DB8 No3rdRD 100 DB15...DB0 No2ndRD DB7...DB0 DB15...DB8 No3rdRD 101 DB15...DB0 No2ndRD DB7...DB0 DB15...DB8 No3rdRD 110 DB15...DB0 No2ndRD DB7...DB0 DB15...DB8 No3rdRD 111 DB15...DB0 No2ndRD DB7...DB0 DB15...DB8 No3rdRD Table3.OverviewoftheOutputFormatsDependingonModeWhenADD=1 ADD=1 BYTE=0 BYTE=1 A2A1A0 1stRD 2ndRD 1stRD 2ndRD 3rdRD 000 DB15...DB0 No2ndRD DB7...DB0 DB15...DB8 No3rdRD 001 DB15...DB0 No2ndRD DB7...DB0 DB15...DB8 No3rdRD 010 DB15...DB0 No2ndRD DB7...DB0 DB15...DB8 No3rdRD 011 DB15...DB0 No2ndRD DB7...DB0 DB15...DB8 No3rdRD 100 DB15...DB0 No2ndRD DB7...DB0 DB15...DB8 No3rdRD 101 DB15...DB0 No2ndRD DB7...DB0 DB15...DB8 No3rdRD 110 100000000000DVA2A1A0 DB15...DB0 DVA2A1A0DB3DB2DB0 DB7...DB0 DB15...DB8 111 100000000000DVA2A1A0 DB15...DB0 DVA2A1A0DB3DB2DB0 DB7...DB0 DB15...DB8 Table4.ControlRegisterBits DB7(MSB) DB6 DB5 DB4 DB3 DB2 DB1 DB0(LSB) 1 NAP PD InvertMSB ADD A2 A1 A0 0 X X X RESET HOLDA HOLDB HOLDC 22 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8365

ADS8365 www.ti.com.................................................................................................................................................... SBAS362C–AUGUST2006–REVISEDMARCH2008 NAP AND POWERDOWN MODE CONTROL B1, C0, and finally, C1 before reading A0 again. Data from channel A0 are brought to the output first after a In order to minimize power consumption when the reset signal, or after powering up the device. The ADS8365 is not in use, two low-power options are third mode is a FIFO mode that is addressed with available. Nap mode minimizes power without (A2, A1, A0 = 111). Data of the channel that is shutting down the biasing circuitry and internal converted first is read first. So, if a particular channel reference, allowing immediate recovery after it is pair is most interesting and is converted more disabled. It can be enabled by either the NAP pin frequently (for example, to get a history of a particular going high, or setting DB6 in the data register high. channel pair), then there are three output registers Enabling Powerdown mode results in lower power perchannelavailabletostoredata. consumption than Nap mode, but requires a short recovery period after disabling. It can only be enabled If all the output registers are filled up with unread bysettingDB5inthedataregisterhigh. data and new data from an additional conversion must be latched in, then the oldest data is discarded. GETTING DATA Ifareadprocess is going on (RD signal low) and new data must be stored, then the ADS8365 waits until FlexibleOutputModes:A0A1,andA2. the read process is finished (RD signal going high) before the new data gets latched into its output The ADS8365 has three different output modes that register. Again, with the ADD signal, it can be chosen are selected with A2, A1, and A0. The A2, A1 and A0 whether the address should be added to the output pins are held with a transparent latch that triggers on data. a falling edge of the RD pin negative-ANDed with the CS pin (that is, if either RD or CS is low, the falling New data is always written into the next available edgeoftheotherwilllatchA0-2). register.Att (seeFigure31),the reset deletes all the 0 existing data. At t , the new data of the channels A0 When (A2, A1, A0) = 000 to 101, a particular channel 1 and A1 are put into registers 0 and 1. At t , a dummy can be directly addressed (see Table 1 and 2 read (RD low) is performed to latch the address data Figure 30). The channel address should be set at correctly. At t , the read process of channel A0 data least 10ns (see Figure 30, t ) before the falling edge 3 D9 is finished; therefore, these data are dumped and A1 ofRDandshouldnotchangeaslong as RD is low. In data are shifted to register 0. At t , new data are this standard address mode, ADD will be ignored, but 4 available, this time from channels B0, B1, C0, and shouldbeconnectedtoeithergroundorsupply. C1. These data are written into the next available When(A2,A1,A0)=110,the interface is running in a registers(registers1,2,3,and4). cycle mode (see Figure 29). Here, data 7 down to data 0 of channel A0 is read on the first RD signal, and data 15 down to data 8 on the second as BYTE is high. Then A1 on the second RD, followed by B0, CLK 16 17 18 19 20 1 2 t D1 HOLD X t ACQ EOC CS t t D8 D7 RD t D9 A0 Figure30.TimingforReadingData Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):ADS8365

ADS8365 SBAS362C–AUGUST2006–REVISEDMARCH2008.................................................................................................................................................... www.ti.com RESET EOC Conversion Conversion Conversion ChannelA Channels B and C Channel C RD Register 5 empty empty empty empty empty CHC1 Register 4 empty empty empty CHC1 empty CHC0 Register 3 empty empty empty CHC0 CHC1 CHC1 Register 2 empty empty empty CHB1 CHC0 CHC0 Register 1 empty CHA1 empty CHB0 CHB1 CHB1 Register 0 empty CHA0 CHA1 CHA1 CHB0 CHB0 t t t t t t t 0 1 2 3 4 5 6 Figure31.FunctionalityDiagramoftheFIFORegisters On t , the new read process of channel A1 data is second RD, the 16-bit data word can be read 5 finished. The new data of channel C0 and C1 at t (DB15…DB0). If BYTE = 1, then three RD impulses 6 areputontop(registers4and5). are needed. On the first RD impulse, data valid, the three address bits, and data bits DB3…DB0 (DV, A2, In Cycle mode and in FIFO mode, the ADS8365 A1, A0, DB3, DB2, DB1, DB0) are read, followed by offers the ability to add the address of the channel to the eight lower bits of the 16-bit data word the output data. Since there is only a 16-bit bus (db7…db0), and finally the higher eight data bits available (or 8-bit bus in the case BYTE is high), an (DB15…DB8). 1000 0000 0000 is added before the additional RD signal is necessary to get the address in case BYTE = 0, and DB3…DB0 is added information(seeTable2andTable3). after the address if BYTE = 1. This provides the In FIFO mode, a dummy read signal (RD) is required possibility to check if the counting of the RD signals after a reset signal to set the address bits inside the ADS8365 are still tracking with the external appropriately; otherwise, the first conversion will not interface(seeTable2andTable3). bevalid.ThisisonlynecessaryinFIFOmode. The data valid bit is useful for the FIFO mode. Valid data can simply be read until the data valid bit equals TheOutputCode(DB15…DB0) 0. The three address bits are listed in Table 5. If the In the standard address mode (A2 A1 A0 = FIFOisempty,16zeroesareloadedtotheoutput. 000…101), the ADS8365 has a 16-bit output word on pins DB15…DB0, if BYTE = 0. If BYTE = 1, then two Table5.AddressBitintheOutputData RD impulses are necessary to first read the lower DATAFROM... A2 A1 A0 bits, and then the higher bits on either DB7…DB0 or ChannelA0 0 0 0 DB15...DB8. ChannelA1 0 0 1 If the ADS8365 operates in Cycle or in FIFO mode ChannelB0 0 1 0 and ADD is set high, then the address of the channel ChannelB1 0 1 1 (A2A1A0) and a data valid (DV) bit are added to the data. If BYTE = 0, then the data valid and the ChannelC0 1 0 0 address of the channel is active during the first RD ChannelC1 1 0 1 impulse (1000 0000 0000 DV A2 A1 A0). During the 24 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8365

ADS8365 www.ti.com.................................................................................................................................................... SBAS362C–AUGUST2006–REVISEDMARCH2008 Binary Two's Complement (BTC) 0111111111111111 65535 0111111111111110 65534 0111111111111101 65533 e od 0000000000000001 32769 C Output 0000000000000000 32768 Step al git 1111111111111111 32767 Di 1000000000000010 2 1000000000000001 1 1000000000000000 0 VNFS = V -V = 0V 2.499962V 2.500038V VPFS = V + V = 5V CM REF CM REF 0.000038V VPFS-1LSB = 4.999924V VBPZ = 2.5V 0.000076V 4.999848V Unipolar Analog Input Voltage 0.000152V 1LSB = 76V V = 2.5V CM 16-BIT V = 2.5V REF Bipolar Input, Binary Two’s Complement Output: (BTC) Negative Full-Scale Code = VNFS = 8000H, Vcode = V -V CM REF Bipolar Zero Code = VBPZ = 0000H, Vcode = V CM Positive Full-Scale Code = VPFS = 7FFFH, Vcode = (V + V )-1LSB CM REF Figure32.IdealConversionCharacteristics(Condition:Single-Ended,V =chXX–=2.5V,V =2.5V) CM REF Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):ADS8365

ADS8365 SBAS362C–AUGUST2006–REVISEDMARCH2008.................................................................................................................................................... www.ti.com LAYOUT capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply. On average, For optimum performance, care should be taken with the ADS8365 draws very little current from an the physical layout of the ADS8365 circuitry. This external reference because the reference voltage is recommendation is particularly true if the CLK input is internally buffered. A bypass capacitor of 0.1m F and approachingthemaximumthroughputrate. 10m F are suggested when using the internal The basic SAR architecture is sensitive to glitches or reference(tiepin61directlytopin62). sudden changes on the power supply, reference, ground connections, and digital inputs that occur just GROUNDING prior to latching the output of the analog comparator. The AGND pins should be connected to a clean Thus, driving any single conversion for an n-bit SAR ground point. In all cases, this point should be the converter, there are n windows in which large analog ground. Avoid connections that are too close external transient voltages can affect the conversion to the grounding point of a microcontroller or digital result. Such glitches might originate from switching signal processor. If required, run a ground trace power supplies, nearby digital logic, or high-power directly from the converter to the power-supply entry devices. The degree of error in the digital output point. The ideal layout includes an analog ground depends on the reference voltage, layout, and the plane dedicated to the converter and associated exact timing of the external event. Their error can analogcircuitry.Threesignalgroundpins(SGND)are change if the external event changes in time with the input signal grounds that are on the same respecttotheCLKinput. potentialasanalogground. With this information in mind, power to the ADS8365 should be clean and well-bypassed. A 0.1m F ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1m F to 10m F capacitor is recommended. If needed, an even larger 26 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8365

ADS8365 www.ti.com.................................................................................................................................................... SBAS362C–AUGUST2006–REVISEDMARCH2008 APPLICATION INFORMATION DifferentconnectiondiagramstoDSPsormicrocontrollersareshowninFigure33throughFigure39. 5V 5V 2.048V REF3220 REF AVDD IN 100nF 5V V+ REF OUT -IN 100kW 20kW SENSE OPA343 OUT 100W 0.5V to 4.5V CH A0+ 100kW 40kW V 100W 1nF V +IN REF 2 REF IN CH A0- A0 2.5V ±10V 40kW REF 1 INA159 ADS8365 100W -IN OUT CH A1+ INA159 100W 1nF V IN +IN REF 1/2 CH A1- A1 CH B0+ CH B0- CH B1+ CH B1- CH C0+ CH C0- 100W -IN OUT CH C1+ INA159 100W 1nF V IN +IN REF 1/2 CH C1- C1 SGND AGND Figure33.±10VInputRangeByUsingtheINA159 Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):ADS8365

ADS8365 SBAS362C–AUGUST2006–REVISEDMARCH2008.................................................................................................................................................... www.ti.com ADS8365 3.3V C28xx BV DV DD DD 56 BVDD HOLDA PWM1 57 HOLDB PWM2 26 58 FD HOLDC PWM3 30 54 WR A0 EA0 23 53 ADD A1 EA1 55 52 BYTE A2 EA2 EA3 31 CS 8:1 OE IS 29 RD RE 27 EOC EXT_INT1 28 CLK MCLKX 51 RESET ADC_RST(MFSX) DATA [0] D0 ... 4..8. ... DATA [15] 33 D15 BGND VSS Figure34.TypicalC28xxConnection(HardwareControl) BVDD ADS8365 3.3V C28xx 56 HOLDA BVDD DVDD 57 HOLDB 58 HOLDC A2 26 FD A1 23 8:1 ADD A0 55 31 BYTE CS OE IS 54 29 A0 RD RE 53 A1 WR 30 WE 52 A2 EOC 27 EXT_INT1 28 CLK MCLKX DATA [0] 48 D0 ... ... ... DATA [15] 33 D15 BGND VSS Figure35.TypicalC28xxConnection(SoftwareControl) 28 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8365

ADS8365 www.ti.com.................................................................................................................................................... SBAS362C–AUGUST2006–REVISEDMARCH2008 ADS8365 3.3V C67xx BV DV BV DD DD DD 56 HOLDA TOUT1 30 57 WR HOLDB A2 53 58 A1 HOLDC A1 52 8:1 A2 A0 23 31 ADD CS OE IS 54 55 A0 BYTE BE0 29 RD RE 27 EOC INT0 28 CLK TOUT0 51 RESET DB_CNTL0 (ED27) DATA[0] 48 D0 ... ... ... DATA[15] 33 D15 BGND VSS Figure36.TypicalC67xxConnection(CycleMode—HardwareControl) BV 3.3V DD ADS8365 C67xx 56 HOLDA BV DV DD DD 57 HOLDB 58 HOLDC A2 26 FD A1 23 8:1 ADD A0 55 31 BYTE CS OE IS 54 29 A0 RD RE 53 A1 WR 30 WE 52 A2 EOC 27 INT0 28 CLK TOUT0 DATA[0] 48 D0 ... ... ... DATA[15] 33 D15 BGND VSS Figure37.TypicalC67xxConnection(SoftwareControl) Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):ADS8365

ADS8365 SBAS362C–AUGUST2006–REVISEDMARCH2008.................................................................................................................................................... www.ti.com 3.3V ADS8365 C54xx BV DV DD DD 56 BVDD HOLDA TOUT0 57 HOLDB A2 26 58 FD HOLDC A1 54 8:1 A0 A0 53 31 A1 CS OE IS 52 29 A2 30 WR RD 30 <1 23 ADD 27 (1G32) I/OSTRB 55 28 BYTE EOC INT0 51 CLK BCLKX1 RESET XF DATA [0..]. 4..8. D...0 DATA [15] 33 D15 BGND VSS Figure38.TypicalC54xxConnection(FIFOMode—HardwareControl) ADS8365 3.3V MSP430x1xx BVDD BVDD DVDD 56 HOLDA TACLK (P1.0) 30 57 WR HOLDB 52 58 ADD HOLDC 54 31 A1 CS P1.1 53 51 A2 RESET P1.2 23 27 BYTE EOC P1.3 (ADC_INT) 55 28 A0 CLK SMCLK (P1.4) 29 RD DATA[0..]. 4..8. P...2.0 DATA[7] 41 P2.7 BGND V SS Figure39.TypicalMSP430x1xxConnection(CycleMode—HardwareControl) 30 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8365

ADS8365 www.ti.com.................................................................................................................................................... SBAS362C–AUGUST2006–REVISEDMARCH2008 Part Change Notification # 20071210003 The ADS8365 device underwent a silicon change under Texas Instruments Part Change Notification (PCN) number 20071210003. Details of this change can be obtained from the Product Information Center at Texas Instruments or by contacting your local sales/distribution office. Devices with a date code of 81x and higher are coveredbythisPCN. Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):ADS8365

ADS8365 SBAS362C–AUGUST2006–REVISEDMARCH2008.................................................................................................................................................... www.ti.com Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(November2006)toRevisionC ........................................................................................... Page • AddedPartChangeNotificationinformation........................................................................................................................ 31 32 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8365

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS8365IPAG ACTIVE TQFP PAG 64 160 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 85 ADS8365AI & no Sb/Br) ADS8365IPAGG4 ACTIVE TQFP PAG 64 160 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 85 ADS8365AI & no Sb/Br) ADS8365IPAGR ACTIVE TQFP PAG 64 1500 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 85 ADS8365AI & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS8365IPAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS8365IPAGR TQFP PAG 64 1500 350.0 350.0 43.0 PackMaterials-Page2

MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 M 0,17 48 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 0,25 SQ 0,05 MIN 11,80 0°–7° 1,05 0,95 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282/C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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