ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 LOW-POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE FEATURES APPLICATIONS 1 • 2.7-Vto5.5-VAnalogSupply,LowPower: • Communications 2 – 15.5mW(1MHz,+VA=3V,+VBD=1.8V) • TransducerInterface • 1-MHzSamplingRate3V≤+VA≤5.5V, • MedicalInstruments 900-kHzSamplingRate2.7V≤+VA≤3V • Magnetometers • ExcellentDCPerformance: • IndustrialProcessControl ±1.0LSBTyp,±1.75LSBMaxINL • DataAcquisitionSystems ±0.5LSBTyp,±1LSBMaxDNL • AutomaticTestEquipment 16-BitNMCOverTemperature ±0.5mVMaxOffsetErrorat3V DESCRIPTION ±1mVMaxOffsetErrorat5V The ADS8329 is a low-power, 16-bit, 1-MSPS • ExcellentACPerformanceatfI=10kHzwith analog-to-digital converter (ADC) with a unipolar 93dBSNR,105dBSFDR,–102dBTHD input. The device includes a 16-bit capacitor-based • Built-InConversionClock(CCLK) SARADCwithinherentsample-and-hold. • 1.65Vto5.5VI/OSupply: The ADS8330 is based on the same core and SPI/DSPCompatibleSerial includes a 2-to-1 input MUX with programmable SCLKupto50MHz option of TAG bit output. Both the ADS8329 and ADS8330 offer a high-speed, wide voltage serial • ComprehensivePower-DownModes: interface and are capable of chain mode operation DeepPower-Down whenmultipleconvertersareused. NapPower-Down AutoNapPower-Down These converters are available in 4 × 4 QFN and 16-pin TSSOP packages, and are fully specified for • UnipolarInputRange:0VtoV REF operation over the industrial –40°C to +85°C • SoftwareReset temperaturerange. • GlobalCONVST(IndependentofCS) • ProgrammableStatus/PolarityEOC/INT LowPower,High-SpeedSARConverterFamily • 16-Pin4×4QFNand16-PinTSSOPPackages Type/Speed 500kSPS 1MSPS • Multi-ChipDaisyChainMode Single ADS8327 ADS8329 16-bitsingle-ended • ProgrammableTAGBitOutput Dual ADS8328 ADS8330 Single — ADS7279 • Auto/ManualChannelSelectMode(ADS8330) 14-bitsingle-ended Dual — ADS7280 Single — ADS7229 12-bitsingleended Dual — ADS7230 OUTPUT ADS8330 ADS8329 SAR LATCH SDO and +IN1 NC 3−STATE DRIVER + +IN0 +IN _ CDAC FS/CS CONVERSION SCLK COM −IN COMPARATOR and SDI CONTROL REF+ OSC LOGIC CONVST REF− EOC/INT/CDI 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Alltrademarksarethepropertyoftheirrespectiveowners. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2006–2009,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. ORDERINGINFORMATION(1) MAXIMUM MAXIMUM MAXIMUM INTEGRAL DIFFERENTIAL OFFSET TRANSPORT LINEARITY LINEARITY ERROR PACKAGE PACKAGE TEMPERATURE ORDERING MEDIA, MODEL (LSB) (LSB) (mV) TYPE DESIGNATOR RANGE INFORMATION QUANTITY ADS8329IRSAT Smalltapeandreel,250 4×4QFN-16 RSA ADS8329IRSAR Tapeandreel,3000 ADS8329I ±2.5 –1/+2 ±0.8 –40°Cto+85°C ADS8329IPW Tube,90 TSSOP-16 PW ADS8329IPWR Tapeandreel,2000 ADS8329IBRSAT Smalltapeandreel,250 4×4QFN-16 RSA ADS8329IBRSAR Tapeandreel,3000 ADS8329IB ±1.75 ±1 ±0.5 –40°Cto+85°C ADS8329IBPW Tube,90 TSSOP-16 PW ADS8329IBPWR Tapeandreel,2000 ADS8330IRSAT Smalltapeandreel,250 4×4QFN-16 RSA ADS8330IRSAR Tapeandreel,3000 ADS8330I ±2.5 –1/+2 ±0.8 –40°Cto+85°C ADS8330IPW Tube,90 TSSOP-16 PW ADS8330IPWR Tapeandreel,2000 ADS8330IBRSAT Smalltapeandreel,250 4×4QFN-16 RSA ADS8330IBRSAR Tapeandreel,3000 ADS8330IB ±1.75 ±1 ±0.5 –40°Cto+85°C ADS8330IBPW Tube,90 TSSOP-16 PW ADS8330IBPWR Tapeandreel,2000 (1) ForthemostcurrentpackageandorderinginformationseethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS Overoperatingfree-airtemperaturerange,unlessotherwisenoted.(1) UNIT +INtoAGND –0.3Vto+VA+0.3V Voltage –INtoAGND –0.3Vto+VA+0.3V +VAtoAGND –0.3Vto7V +REFtoAGND –0.3Vto+VA+0.3V Voltagerange –REFtoAGND –0.3Vto0.3V +VBDtoBDGND –0.3Vto7V AGNDtoBDGND –0.3Vto0.3V DigitalinputvoltagetoBDGND –0.3Vto+VBD+0.3V DigitaloutputvoltagetoBDGND –0.3Vto+VBD+0.3V T Operatingfree-airtemperaturerange –40°Cto+85°C A T Storagetemperaturerange –65°Cto+150°C stg Junctiontemperature(T max) +150°C J 4×4QFN-16 Powerdissipation (TJMax–TA)/q JA package q thermalimpedance +47°C/W JA TSSOP-16 Powerdissipation (TJMax–TA)/q JA package q thermalimpedance +86°C/W JA (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 2 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 ELECTRICAL CHARACTERISTICS T =–40°Cto85°C,+VA=4.5Vto5.5V,+VBD=1.65Vto5.5V,V =5V,andf =1MHz,unlessotherwisenoted. A REF SAMPLE PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ANALOGINPUT Full-scaleinputvoltage(1) +IN–(–IN)or(+INx–COM) 0 +VREF V +IN,+IN0,+IN1 AGND–0.2 +VA+0.2 Absoluteinputvoltage V –INorCOM AGND–0.2 AGND+0.2 Inputcapacitance 40 45 pF Noongoingconversion, Inputleakagecurrent –1 1 nA dcinput Atdc 109 Inputchannelisolation,ADS8330only dB VI=±1.25VPPat50kHz 101 SYSTEMPERFORMANCE Resolution 16 Bits Nomissingcodes 16 Bits INL Integral ADS8329IB,ADS8330IB –1.75 ±1.2 1.75 LSB(2) linearity ADS8329I,ADS8330I –2.5 ±1.5 2.5 DNL Differential ADS8329IB,ADS8330IB –1 ±0.4 1 LSB(2) linearity ADS8329I,ADS8330I –1 ±0.5 2 ADS8329IB,ADS8330IB –1 ±0.27 1 EO Offseterror(3) mV ADS8329I,ADS8330I –1.25 ±0.8 1.25 Offseterrordrift FSR=5V +0.4 ppm/°C EG Gainerror –0.25 –0.04 0.25 %FSR Gainerrordrift +0.75 ppm/°C Atdc 70 CMRR Common-moderejectionratio dB VI=0.4VPPat1MHz 50 Noise 33 m VRMS PSRR Power-supplyrejectionratio AtFFFFhoutputcode(3) 78 dB SAMPLINGDYNAMICS tCONV Conversiontime 18 CCLK tSAMPLE1 Manualtrigger 3 Acquisitiontime CCLK tSAMPLE2 Autotrigger 3 Throughputrate 1 MHz Aperturedelay 5 ns Aperturejitter 10 ps Stepresponse 100 ns Overvoltagerecovery 100 ns (1) Idealinputspan;doesnotincludegainoroffseterror. (2) LSBmeansleastsignificantbit. (3) Measuredrelativetoanidealfull-scaleinput[+IN–(–IN)]of4.096Vwhen+VA=5V. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) T =–40°Cto85°C,+VA=4.5Vto5.5V,+VBD=1.65Vto5.5V,V =5V,andf =1MHz,unlessotherwisenoted. A REF SAMPLE PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DYNAMICCHARACTERISTICS THD Totalharmonicdistortion(4) VIN=5VPPat10kHz –102 dB VIN=5VPPat100kHz –95 VIN=5VPPat10kHz 93 SNR Signal-to-noiseratio ADS8329/30IB 90 92 dB VIN=5VPPat100kHz ADS8329/30I 90 VIN=5VPPat10kHz 92 SINAD Signal-to-noise+distortion dB VIN=5VPPat100kHz 90 VIN=5VPPat10kHz 105 SFDR Spurious-freedynamicrange dB VIN=5VPPat100kHz 97 –3dBsmall-signalbandwidth 30 MHz CLOCK Internalconversionclockfrequency 21 22.9 24.5 MHz UsedasI/Oclockonly 50 SCLKexternalserialclock MHz AsI/Oclockandconversionclock 1 42 EXTERNALVOLTAGEREFERENCEINPUT Input VREF[(REF+)–(REF–)] 5.5V≥+VA≥4.5V 0.3 +VA VREF reference V range (REF–)–AGND –0.1 0.1 Resistance(5) Referenceinput 40 kΩ DIGITALINPUT/OUTPUT Logicfamily—CMOS VIH High-levelinputvoltage 5.5V≥+VBD≥4.5V 0.65×(+VBD) +VBD+0.3 V 0.35× VIL Low-levelinputvoltage 5.5V≥+VBD≥4.5V –0.3 (+VBD) V II Inputcurrent VI=+VBDorBDGND –50 50 nA CI Inputcapacitance 5 pF 5.5V≥+VBD≥4.5V, VOH High-leveloutputvoltage IO=100m A +VBD–0.6 +VBD V 5.5V≥+VBD≥4.5V, VOL Low-leveloutputvoltage IO=100m A 0 0.4 V CO Outputcapacitance 5 pF CL Loadcapacitance 30 pF Dataformat—straightbinary POWER-SUPPLYREQUIREMENTS Power-supply +VBD 1.65 3.3 5.5 V voltage +VA 4.5 5 5.5 V 1-MHzSamplerate 7.0 7.8 mA Supplycurrent NAP/Auto-NAPmode 0.3 0.5 Deeppower-downmode 4 50 nA BufferI/Osupplycurrent 1MSPS 1.7 mA +VA=5V,+VBD=5V 44 48 Powerdissipation mW +VA=5V,+VBD=1.8V 35 39.5 TEMPERATURERANGE TA Operatingfree-airtemperature –40 +85 °C (4) Calculatedonthefirstnineharmonicsoftheinputfrequency. (5) Canvary±30%. 4 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 ELECTRICAL CHARACTERISTICS T =–40°Cto85°C,+VA=2.7Vto3.6V,+VBD=1.65Vto1.5×(+VA),V =2.5V,f =1MHzfor3V≤+VA≤3.6V, A REF SAMPLE f =900kHzfor3V<+VA≤2.7Vusingexternalclock(unlessotherwisenoted) SAMPLE PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ANALOGINPUT Full-scaleinputvoltage(1) +IN–(–IN)or(+INx–COM) 0 +VREF V +IN,+IN0,+IN1 AGND–0.2 +VA+0.2 Absoluteinputvoltage V –INorCOM AGND–0.2 AGND+0.2 Inputcapacitance 40 45 pF Noongoingconversion, Inputleakagecurrent –1 1 nA DCInput Atdc 108 Inputchannelisolation,ADS8330only dB VI=±1.25VPPat50kHz 101 SYSTEMPERFORMANCE Resolution 16 Bits Nomissingcodes 16 Bits ADS8329IB, –1.75 ±1 1.75 INL Integrallinearity ADS8330IB LSB(2) ADS8329I,ADS8330I –2.5 ±1.5 2.5 ADS8329IB, DNL Differential ADS8330IB –1 ±0.5 1 LSB(2) linearity ADS8329I,ADS8330I –1 ±0.8 2 ADS8329IB, –0.5 ±0.05 0.5 EO Offseterror(3) ADS8330IB mV ADS8329I,ADS8330I –0.8 ±0.2 0.8 Offseterrordrift FSR=2.5V +0.8 ppm/°C EG Gainerror –0.25 –0.04 0.25 %FSR Gainerrordrift +0.5 ppm/°C Atdc 70 CMRR Common-moderejectionratio dB VI=0.4VPPat1MHz 50 Noise 33 m VRMS PSRR Power-supplyrejectionratio AtFFFFhoutputcode(3) 78 dB SAMPLINGDYNAMICS tCONV Conversiontime 18 CCLK tSAMPLE1 Manualtrigger 3 Acquisitiontime CCLK tSAMPLE2 Autotrigger 3 Throughputrate 1 MHz Aperturedelay 5 ns Aperturejitter 10 ps Stepresponse 100 ns Overvoltagerecovery 100 ns (1) Idealinputspan,doesnotincludegainoroffseterror. (2) LSBmeansleastsignificantbit. (3) Measuredrelativetoanidealfull-scaleinput[+IN–(–IN)]of2.5Vwhen+VA=3V. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) T =–40°Cto85°C,+VA=2.7Vto3.6V,+VBD=1.65Vto1.5×(+VA),V =2.5V,f =1MHzfor3V≤+VA≤3.6V, A REF SAMPLE f =900kHzfor3V<+VA≤2.7Vusingexternalclock(unlessotherwisenoted) SAMPLE PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DYNAMICCHARACTERISTICS THD Totalharmonicdistortion(4) VIN=2.5VPPat10kHz –102 dB VIN=2.5VPPat100kHz –93 VIN=2.5VPPat10kHz 89 SNR Signal-to-noiseratio dB VIN=2.5VPPat100kHz 88 VIN=2.5VPPat10kHz 88.5 SINAD Signal-to-noise+distortion dB VIN=2.5VPPat100kHz 88 VIN=2.5VPPat10kHz 104 SFDR Spurious-freedynamicrange dB VIN=2.5VPPat100kHz 94.2 –3dBsmall-signalbandwidth 30 MHz CLOCK Internalconversionclockfrequency 21 22.3 23.5 MHz UsedasI/Oclockonly 42 SCLKexternalserialclock MHz AsI/Oclockandconversionclock 1 42 EXTERNALVOLTAGEREFERENCEINPUT fSAMPLE≤500kSPS, 0.3 2.525 2.7V≤+VA<3V fSAMPLE≤500kSPS, 0.3 3 VREF[(REF+)– 3V≤+VA<3.6V VREF Irnapnugtereference (REF–)] fSAMPLE>500kSPS, 2.475 2.525 V 2.7V≤+VA<3V fSAMPLE>500kSPS, 2.475 3 3V≤+VA≤3.6V (REF–)–AGND –0.1 0.1 Resistance(5) Referenceinput 40 kΩ DIGITALINPUT/OUTPUT Logicfamily—CMOS VIH High-levelinputvoltage (+VA×1.5)V≥+VBD≥1.65V 0.65×(+VBD) +VBD+0.3 V VIL Low-levelinputvoltage (+VA×1.5)V≥+VBD≥1.65V –0.3 0.35×(+VBD) V II Inputcurrent VI=+VBDorBDGND –50 50 nA CI Inputcapacitance 5 pF (+VA×1.5)V≥+VBD≥1.65V, VOH High-leveloutputvoltage IO=100m A +VBD–0.6 +VBD V (+VA×1.5)V≥+VBD≥1.65V, VOL Low-leveloutputvoltage IO=100m A 0 0.4 V CO Outputcapacitance 5 pF CL Loadcapacitance 30 pF Dataformat—straightbinary (4) Calculatedonthefirstnineharmonicsoftheinputfrequency. (5) Canvary±30%. 6 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 ELECTRICAL CHARACTERISTICS (continued) T =–40°Cto85°C,+VA=2.7Vto3.6V,+VBD=1.65Vto1.5×(+VA),V =2.5V,f =1MHzfor3V≤+VA≤3.6V, A REF SAMPLE f =900kHzfor3V<+VA≤2.7Vusingexternalclock(unlessotherwisenoted) SAMPLE PARAMETER TESTCONDITIONS MIN TYP MAX UNIT POWER-SUPPLYREQUIREMENTS +VBD 1.65 +VA 1.5×(+VA) V Power-supply voltage +VA fs≤1MHz 3 3.6 V fs≤900kHz 2.7 3.6 1-MHzsamplerate, 5.1 6.1 3V≤+VA≤3.6V 900-kHzsamplerate, mA Supplycurrent 2.7V≤+VA≤3V 4.84 NAP/Auto-NAPmode 0.25 0.4 Deeppower-downmode 2 50 nA BufferI/Osupplycurrent 1MSPS,+VBD=1.8V 0.05 mA +VBD=1.8V,3V≤+VA≤3.6V 15.5 19 Powerdissipation mW +VBD=1.8V,2.7V≤+VA≤3V 13.2 TEMPERATURERANGE TA Operatingfree-airtemperature –40 +85 °C Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com TIMING CHARACTERISTICS Allspecificationstypicalat–40°Cto85°Cand+VA=+VBD=5V. (1)(2) PARAMETER MIN TYP MAX UNIT External, 0.5 21 f =1/2f CCLK SCLK f Frequency,conversionclock,CCLK MHz CCLK Internal, 21 22.9 24.5 f =1/2f CCLK SCLK t Setuptime,fallingedgeofCStoEOC 1 CCLK su(CSF-EOC) t Holdtime,fallingedgeofCStoEOC 0 ns h(CSF-EOC) t Pulseduration,CONVSTlow 40 ns wL(CONVST) t Setuptime,fallingedgeofCStoEOS 20 ns su(CSF-EOS) t Holdtime,fallingedgeofCStoEOS 20 ns h(CSF-EOS) t Setuptime,risingedgeofCStoEOS 20 ns su(CSR-EOS) t Holdtime,risingedgeofCStoEOS 20 ns h(CSR-EOS) Setuptime,fallingedgeofCStofirstfalling t 5 ns su(CSF-SCLK1F) SCLK t Pulseduration,SCLKlow 8 t –8 ns wL(SCLK) c(SCLK) t Pulseduration,SCLKhigh 8 t –8 ns wH(SCLK) c(SCLK) I/OClockonly 20 I/Oandconversionclock 23.8 2000 tc(SCLK) Cycletime,SCLK I/OClock,chainmode 20 ns I/Oandconversionclock, 23.8 2000 chainmode Delaytime,fallingedgeofSCLKtoSDO t 10-pFLoad 2 ns d(SCLKF-SDOINVALID) invalid Delaytime,fallingedgeofSCLKtoSDO t 10-pFLoad 10 ns d(SCLKF-SDOVALID) valid Delaytime,fallingedgeofCStoSDO t 10-pFLoad 8.5 ns d(CSF-SDOVALID) valid,SDOMSBoutput t Setuptime,SDItofallingedgeofSCLK 8 ns su(SDI-SCLKF) t Holdtime,SDItofallingedgeofSCLK 4 ns h(SDI-SCLKF) Delaytime,risingedgeofCS/FStoSDO t 5 ns d(CSR-SDOZ) 3-state Setuptime,16thfallingedgeofSCLK t 10 ns su(16thSCLKF-CSR) beforerisingedgeofCS/FS Delaytime,CDIhightoSDOhighindaisy t 10-pFLoad,chainmode 16 ns d(SDO-CDI) chainmode (1) Allinputsignalsarespecifiedwitht =t =1.5ns(10%to90%ofV )andtimedfromavoltagelevelof(V +V )/2. r f DD IL IH (2) Seetimingdiagrams. 8 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 TIMING CHARACTERISTICS Allspecificationstypicalat–40°Cto85°C,+VA=2.7V,+VBD=1.8V(unlessotherwisenoted) (1)(2) PARAMETER MIN TYP MAX UNIT External,3V≤+VA≤3.6V, 0.5 21 f =1/2f CCLK SCLK External,2.7V≤+VA≤3V, f Frequency,conversionclock,CCLK 0.5 18.9 MHz CCLK f =1/2f CCLK SCLK Internal, 20 22.3 23.5 f =1/2f CCLK SCLK t Setuptime,fallingedgeofCStoEOC 1 CCLK su(CSF-EOC) t Holdtime,fallingedgeofCStoEOC 0 ns h(CSF-EOC) t Pulseduration,CONVSTlow 40 ns wL(CONVST) t Setuptime,fallingedgeofCStoEOS 20 ns su(CSF-EOS) t Holdtime,fallingedgeofCStoEOS 20 ns h(CSF-EOS) t Setuptime,risingedgeofCStoEOS 20 ns su(CSR-EOS) t Holdtime,risingedgeofCStoEOS 20 ns h(CSR-EOS) Setuptime,fallingedgeofCStofirst t 5 ns su(CSF-SCLK1F) fallingSCLK t Pulseduration,SCLKlow 8 t –8 ns wL(SCLK) c(SCLK) t Pulseduration,SCLKhigh 8 t –8 ns wH(SCLK) c(SCLK) Allmodes, 23.8 2000 3V≤+VA≤3.6V t Cycletime,SCLK ns c(SCLK) Allmodes, 26.5 2000 2.7V≤+VA<3V Delaytime,fallingedgeofSCLKtoSDO t 10-pFLoad 7.5 ns d(SCLKF-SDOINVALID) invalid Delaytime,fallingedgeofSCLKtoSDO t 10-pFLoad 16 ns d(SCLKF-SDOVALID) valid 10-pFLoad, 13 Delaytime,fallingedgeofCStoSDO 2.7V≤+VA≤3V t ns d(CSF-SDOVALID) valid,SDOMSBoutput 10-pFLoad, 11 3V≤+VA≤3.6V t Setuptime,SDItofallingedgeofSCLK 8 ns su(SDI-SCLKF) t Holdtime,SDItofallingedgeofSCLK 4 ns h(SDI-SCLKF) Delaytime,risingedgeofCS/FStoSDO t 8 ns d(CSR-SDOZ) 3-state Setuptime,16thfallingedgeofSCLK t 10 ns su(16thSCLKF-CSR) beforerisingedgeofCS/FS Delaytime,CDIhightoSDOhighin t 10-pFLoad,chainmode 23 ns d(SDO-CDI) daisychainmode (1) Allinputsignalsarespecifiedwitht =t =1.5ns(10%to90%ofV )andtimedfromavoltagelevelof(V +V )/2. r f DD IL IH (2) Seetimingdiagrams. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com PIN ASSIGNMENTS ADS8329 ADS8330 RSAPACKAGE RSAPACKAGE (TOPVIEW) (TOPVIEW) -REF AGND -IN +IN -REF AGND COM +IN0 6 5 4 3 1 1 1 1 6 5 4 3 1 1 1 1 REF+ (REFIN) 1 12 RESERVED REF+ (REFIN) 1 12 +IN1 NC 2 11 +VA NC 2 11 +VA CONVST 3 10 +VBD CONVST 3 10 +VBD EOC/INT/CDI 4 9 SCLK EOC/INT/CDI 4 9 SCLK 5 6 7 8 5 6 7 8 FS/CS SDI SDO BDGND FS/CS SDI SDO DGND B CAUTION: The thermal pad is internally connected to the substrate. This pad can be connected to the analog groundorleftfloating.Keepthethermalpadseparatefromthedigitalground,ifpossible. ADS8329 ADS8330 PWPACKAGE PWPACKAGE (TOPVIEW) (TOPVIEW) +VA 1 16 +VBD +VA 1 16 +VBD RESERVED 2 15 SCLK +IN1 2 15 SCLK +IN 3 14 BDGND +IN0 3 14 BDGND -IN 4 13 SDO COM 4 13 SDO AGND 5 12 SDI AGND 5 12 SDI REF- 6 11 FS/CS REF- 6 11 FS/CS REF+ (REFIN) 7 10 EOC/INT/CDI REF+ (REFIN) 7 10 EOC/INT/CDI NC 8 9 CONVST NC 8 9 CONVST NC=Nointernalconnection 10 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 ADS8329TerminalFunctions NO. NAME QFN TSSOP I/O DESCRIPTION AGND 15 5 — Analogground BDGND 8 14 — Interfaceground CONVST 3 9 I Freezessampleandhold,startsconversionwithnextrisingedgeofinternalclock Statusoutput.IfprogrammedasEOC,thispinislow(default)whenaconversionisin progress.Ifprogrammedasaninterrupt(INT),thispinislowforapreprogrammed EOC/INT/CDI 4 10 O durationaftertheendofconversionandvaliddataaretobeoutput.Thepolarityof EOCorINTisprogrammable.Thispincanalsobeusedasachaindatainputwhen thedeviceisoperatedinchainmode. 5 11 I FramesyncsignalforTMS320DSPserialinterfaceorchipselectinputforSPI FS/CS interfaceslaveselect(SS–). +IN 13 3 I Noninvertinginput –IN 14 4 I Invertinginput,usuallyconnectedtoground NC 2 8 — Noconnection. REF+ 1 7 I Externalreferenceinput. REF– 16 6 I ConnecttoAGNDthroughindividualvia. RESERVED 12 2 I ConnecttoAGNDor+VA SCLK 9 15 I Clockforserialinterface SDI 6 12 I Serialdatain SDO 7 13 O Serialdataout +VA 11 1 Analogsupply,+2.7Vto+5.5VDC. +VBD 10 16 Interfacesupply ADS8330TerminalFunctions NO. NAME QFN TSSOP I/O DESCRIPTION AGND 15 5 — Analogground BDGND 8 14 — Interfaceground COM 14 4 I Commoninvertinginput,usuallyconnectedtoground CONVST 3 9 I Freezessampleandhold,startsconversionwithnextrisingedgeofinternalclock Statusoutput.IfprogrammedasEOC,thispinislow(default)whenaconversionisin progress.Ifprogrammedasaninterrupt(INT),thispinislowforapreprogrammed EOC/INT/CDI 4 10 O durationaftertheendofconversionandvaliddataaretobeoutput.Thepolarityof EOCorINTisprogrammable.Thispincanalsobeusedasachaindatainputwhen thedeviceisoperatedinchainmode. 5 11 I FramesyncsignalforTMS320DSPserialinterfaceorchipselectinputforSPI FS/CS interface +IN1 12 2 I Secondnoninvertinginput. +IN0 13 3 I Firstnoninvertinginput NC 2 8 — Noconnection. REF+ 1 7 I Externalreferenceinput. REF– 16 6 I ConnecttoAGNDthroughindividualvia. SCLK 9 15 I Clockforserialinterface SDI 6 12 I Serialdatain(conversionstartandresetpossible) SDO 7 13 O Serialdataout +VA 11 1 Analogsupply,+2.7Vto+5.5VDC. +VBD 10 16 Interfacesupply Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com MANUALTRIGGER / READ While Sampling (use internal CCLK, EOC andINTpolarity programmed as active low) CONVST Nth t wL(CONVST) OC OS OC OS EOC E E Nth E E (active low) t = 3 CCLKs min t = 18 CCLKs SAMPLE1 CONV t = 3 CCLKs min SAMPLE1 INT (active low) t t h(CSR-EOS) h(CSF-EOC) t h(CSF-EOC) t t h(CSF-EOS) su(CSF-EOC) t su(CSF-EOS) CS/FS 1 SCLK 1 . . . . . . . . . . . . . . . . . . . . 16 t = 20 ns min d(CSR-EOS) SDO Nth−1st Nth SDI 1101b 1101b READ Result READ Result Figure1.TimingforConversionandAcquisitionCyclesforManualTrigger(Readwhilesampling) AUTO TRIGGER / READ While Sampling (use internal CCLK, EOC andINTpolarity programmed as active low) CONVST= 1 EOC EOS EOC EOS Nth EOC EOS (active low) t = 18 CCLKs t = 3 CCLKs t = 18 CCLKs t = 3 CCLKs CONV SAMPLE2 CONV SAMPLE2 INT (active low) t t h(CSF-EOS) h(CSF-EOC) t t su(CSF-EOS) su(CSF-EOS) CS/FS SCLK 1 . . . . . . . . . . . . . . . . . . .16 1 . . . . . . . . . . . . . . . . . . .16 t 1 h(CSF-EOC) SDO N−2nd N−1st Nth SDI 1110b. . . . . . . . . . . . . . 1101b 1101b CONFIGURE READ Result READ Result Figure2.TimingforConversionandAcquisitionCyclesforAutotrigger(Readwhilesampling) 12 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 MANUALTRIGGER / READ While Converting (use internal CCLK, EOC andINTpolarity programmed as active low) CONVST Nth N−1st t wL(CONVST) S C S O Nth O O N + 1st E E E EOC (active low) tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs min INT (active low) t h(CSF-EOS) t t su(CSF-EOS) su(CSR-EOS) CS/FS tsu(CSF-EOC) th(CSF-EOC) SCLK 1 . . . . . . . . . . . . . . . . . . . .16 1 SDO N−1st N th SDI 1101b 1101b READ Result READ Result Figure3.TimingforConversionandAcquisitionCyclesforManualTrigger(Readwhileconverting) AUTO TRIGGER / READ While Converting (use internal CCLK, EOC andINTpolarity programmed as active low) CONVST= 1 EOC EOS EOC EOS N + 1st EOC EOS (active low) t = 18 CCLKs t = 18 CCLKs CONV CONV t = 3 CCLKs min t = 3 CCLKs min Nth SAMPLE2 SAMPLE2 INT (active low) tsu(CSF-EOS) th(CSF-EOS) t tsu(CSR-EOS) t h(CSF-EOS) h(CSR-EOS) CS/FS 1 . . . . . . . . . . . . . . . . . . 16 SCLK 1 . . . . . . . . . . . . . . . . . . .16 1 . . . . . . . . . . . . . . . . . . 16 tsu(CSR-EOS) SDO N−2nd ?? N−1st Nth SDI 1110b . . . . . . . . . . . . . . . 1101b 1101b CONFIGURE READ Result READ Result Figure4.TimingforConversionandAcquisitionCyclesforAutotrigger(Readwhileconverting) Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com 1 2 3 4 5 6 7 14 15 16 SCLK tc(SCLK) tsu(CSF−SCLK1F) twH(SCLK) tsu(16thSCLK−CSR) twL(SCLK) CS/FS td(SCLKF−SDOINVALID) td(CSR−SDOZ) td(CSF−SDOVALID) td(SCLKF−SDOVALID) Hi−Z SDO MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 LSB+2 LSB+1 LSB th(SDI−SCLKF) SDI MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 LSB+2 LSB+1 LSB tsu(SDI−SCLKF) Figure5.DetailedSPITransferTiming MANUALTRIGGER / READ While Sampling (use internal CCLKactive high, EOC andINTactive low, TAG enabled, auto channel select) Nth CH0 Nth CH1 CONVST t t wL(CONVST) wL(CONVST) C S O O EOC E E Nth CH0 Nth CH1 (active low) tCONV = 18 CCLKs tCONV = 18 CCLKs t = 3 CCLKs min SAMPLE1 INT (active low) t su(CSF-EOS) t h(CSF-EOC) CS/FS SCLK 1. . . . . . . . . . . . . . . . . . . . . . .16 17 1 . . . . . . . . . . . . . . . . . . . . . . . 16 17 t =20 ns MIN d(CSR-EOS) Hi−Z Hi−Z SDO N−1st CH1 Nth CH0 TAG = 1 TAG = 0 SDI 1101b 1101b READ Result READ Result Figure6.SimplifiedDualChannelTiming 14 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 TYPICAL CHARACTERISTICS At –40°C to 85°C, V [REF+ – (REF–)] = 5 V when +VA = +VBD = 5 V or V [REF+ – (REF–)] = 2.5 V when REF REF +VA = +VBD = 3 V, f = 42 MHz, or V = 2.5 when +VA = +VBD = 2.7 V, f = 37.8 MHz, f = dc for dc SCLK REF SCLK I curves, f = 100 kHz for ac curves with 5-V supply and f = 10 kHz for ac curves with 3-V supply (unless I I otherwisenoted). CROSSTALK DIFFERENTIALNONLINEARITY INTEGRALNONLINEARITY vs vs vs FREQUENCY FREE-AIRTEMPERATURE FREE-AIRTEMPERATURE 110 1 2 105 0.8 1.5 100 +VA= 5 V B Crosstalk -d 95 +VA= 5 V DNL- LSB 00..46 +VA= 3 V INL- LSB 1 +VA= 3 V 90 +VA= 5 V 0.5 0.2 85 +VA= 3 V 80 0 0 0 50 100 150 200 -40 -25 -10 5 20 35 50 65 80 -40 -25 -10 5 20 35 50 65 80 f - Frequency - kHz TA- Free-Air Temperature - °C TA- Free-Air Temperature - °C Figure7. Figure8. Figure9. DIFFERENTIALNONLINEARITY INTEGRALNONLINEARITY DIFFERENTIALNONLINEARITY vs vs vs EXTERNALCLOCKFREQUENCY EXTERNALCLOCKFREQUENCY EXTERNALCLOCKFREQUENCY 1 2 1 +VA= 5 V +VA= 5 V +VA= 3 V MAX 1.5 MAX MAX 0.5 1 0.5 0.5 B B B S S S DNL- L 0 MIN INL- L-0.50 MIN DNL- L 0 MIN -0.5 -1 -0.5 -1.5 -1 -2 -1 0.1 1 10 100 0.1 1 10 100 0.1 1 10 100 External Clock Frequency - MHz External Clock Frequency - MHz External Clock Frequency - MHz Figure10. Figure11. Figure12. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) INTEGRALNONLINEARITY OFFSETVOLTAGE OFFSETVOLTAGE vs vs vs EXTERNALCLOCKFREQUENCY FREE-AIRTEMPERATURE SUPPLYVOLTAGE 2 1 1 +VA= 3 V 1.5 MAX 0.8 1 0.5 mV +VA= 5 V mV INL- LSB -00..505 MIN Offset Voltage - 0 +VA= 3 V Offset Voltage - 00..46 -1 -0.5 0.2 -1.5 -20.1 1 10 100 -1-40 -25 -10 5 20 35 50 65 80 02.7 3.2 3.7 4.2 4.7 5.2 External Clock Frequency - MHz TA- Free-Air Temperature - °C +VA- Supply Voltage - V Figure13. Figure14. Figure15. GAINERROR GAINERROR POWER-SUPPLYREJECTIONRATIO vs vs vs FREE-AIRTEMPERATURE SUPPLYVOLTAGE SUPPLYRIPPLEFREQUENCY 0 0.10 -80 B d -0.02 atio - -78 0.05 R %FSR -0.04 +VA= 5 V %FSR ection -76 Gain Error - -0.06 +VA= 3 V Gain Error - 0 er Supply Rej -74 +VA= 5 V -0.05 w -0.08 Po -72 R - +VA= 3 V R S -0.10 -0.10 P -70 -40 -25 -10 5 20 35 50 65 80 2.7 3.2 3.7 4.2 4.7 5.2 0 20 40 60 80 100 TA- Free-Air Temperature - °C +VA- Supply Voltage - V f - Frequency - kHz Figure16. Figure17. Figure18. SIGNAL-TO-NOISERATIO SIGNAL-TO-NOISEANDDISTORTION TOTALHARMONICDISTORTION vs vs vs INPUTFREQUENCY INPUTFREQUENCY INPUTFREQUENCY 95 95 -90 B d SNR - Signal-To-Noise Ratio - dB 88997913 +V+AV=A 3= V5 V AD - Signal-To-Noise and Distortion - 88997913 +V+AVA= =3 5V V THD - Total Harmonic Distortion - dB --11-009055 +V+AV=A 3= V5 V N 85 SI 85 -110 0 20 40 60 80 100 0 20 40 60 80 100 0 20 40 60 80 100 fi- Input Frequency - kHz fi-InputFrequency-kHz fi-InputFrequency-kHz Figure19. Figure20. Figure21. 16 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 TYPICAL CHARACTERISTICS (continued) SPURIOUS-FREEDYNAMICRANGE SIGNAL-TO-NOISERATIO SIGNAL-TO-NOISEANDDISTORTION vs vs vs INPUTFREQUENCY FULL-SCALERANGE FULL-SCALERANGE 110 100 100 B SFDR - Spurious Free Dynamic Range - dB 1111100000999990246802468 +V+AVA= =5 3V V SNR - Signal-To-Noise Ratio - dB 778899050505 fi=+ 1V0A k=H 3z V +VA= 5 V SINAD - Sigo-Nnal-Toise and Distortion - d 778899500505 fi= +1V0A k=H z3 V +VA= 5 V 0 20 40 60 80 100 0 1 2 3 4 5 0 1 2 3 4 5 fi-InputFrequency-kHz Full Scale Range - V Full Scale Range - V Figure22. Figure23. Figure24. TOTALHARMONICDISTORTION SPURIOUS-FREEDYNAMICRANGE TOTALHARMONICDISTORTION vs vs vs FULL-SCALERANGE FULL-SCALERANGE FREE-AIRTEMPERATURE -80 110 -90 THD - Total Harmonic Distortion - dB--11---0099850505 fi=+ V1A0 k=H 3z V +VA= 5 V DR - Spurious Free Dynamic Range - dB110890905055 f+iV=A 1=0 k3H Vz +VA= 5 V THD - Total Harmonic Distortion - dB --11-009505 +VA= 3+ VVA= 5 V F -110 S 80 -110 0 1 2 3 4 5 0 1 2 3 4 5 -40 -25 -10 5 20 35 50 65 80 Full Scale Range - V Full Scale Range - V TA- Free-Air Temperature - °C Figure25. Figure26. Figure27. SPURIOUS-FREEDYNAMICRANGE SIGNAL-TO-NOISERATIO SIGNAL-TO-NOISEANDDISTORTION vs vs vs FREE-AIRTEMPERATURE FREE-AIRTEMPERATURE FREE-AIRTEMPERATURE 110 95 95 B B d d s Free Dynamic Range - 110005 +VA= 3 V al-To-Noise Ratio - dB 899931 ++VVAA== 53 VV o-Noise and Distortion - 899913 +VA= 5 V u n T R - Spurio 95 +VA= 5 V SNR - Sig 87 D - Signal- 87 +VA= 3 V D A SF 90 85 SIN 85 -40 -25 -10 5 20 35 50 65 80 -40 -25 -10 5 20 35 50 65 80 -40 -25 -10 5 20 35 50 65 80 TA- Free-Air Temperature - °C TA- Free-Air Temperature - ºC TA- Free-Air Temperature - ºC Figure28. Figure29. Figure30. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) EFFECTIVENUMBEROFBITS INTERNALCLOCKFREQUENCY INTERNALCLOCKFREQUENCY vs vs vs FREE-AIRTEMPERATURE SUPPLYVOLTAGE FREE-AIRTEMPERATURE 16 24 24 s of Bits - Bit15.50 cy - MHz 232.35 cy - MHz 232.35 mber +VA= 5 V quen quen Nu 15 Fre 22.5 Fre 22.5 NOB - Effective 14.50 +VA= 3 V Internal Clock 212.52 Internal Clock 212.52 E 14 21 21 -40 -25 -10 5 20 35 50 65 80 2.7 3.2 3.7 4.2 4.7 5.2 -40 -25 -10 5 20 35 50 65 80 TA- Free-Air Temperature - ºC +VA- Supply Voltage - V TA- Free-Air Temperature - ºC Figure31. Figure32. Figure33. ANALOGSUPPLYCURRENT ANALOGSUPPLYCURRENT ANALOGSUPPLYCURRENT vs vs vs SUPPLYVOLTAGE SUPPLYVOLTAGE SUPPLYVOLTAGE 400 10 7.5 fs= 1 MSPS NAPMode PD Mode urrent - mA 67..50 mCurrent -A 336200 Current - nA 86 C y y y 6.0 pl pl nalog Suppl 5.5 Analog Sup 224800 Analog Sup 24 A 5.0 4.5 200 0 2.7 3.2 3.7 4.2 4.7 5.2 2.7 3.2 3.7 4.2 4.7 5.2 2.7 3.2 3.7 4.2 4.7 5.2 +VA- Supply Voltage - V +VA- Supply Voltage - V +VA- Supply Voltage - V Figure34. Figure35. Figure36. ANALOGSUPPLYCURRENT ANALOGSUPPLYCURRENT ANALOGSUPPLYCURRENT vs vs vs SAMPLERATE SAMPLERATE FREE-AIRTEMPERATURE 500 7 Auto NAP PD Mode 7.5 fs= 1 MSPS mA 6 A 400 mA 7 +VA= 5 V Supply Current - 453 +V+AVA= =3 5V V mupply Current - 230000 +VA= 5 V Supply Current - 56..565 +VA= 3 V Analog 2 Analog S 100 +VA= 3 V Analog 5 1 4.5 0 4 1 10 100 1000 01 5 9 13 17 -40 -25 -10 5 20 35 50 65 80 Sample Rate - kHz Sample Rate - kHz TA- Free-Air Temperature - ºC Figure37. Figure38. Figure39. 18 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 TYPICAL CHARACTERISTICS (continued) ANALOGSUPPLYCURRENT vs FREE-AIRTEMPERATURE 0.4 NAPMode A 0.36 m nt - urre 0.32 +VA= 5 V C y pl up 0.28 S g +VA= 3 V o al n A 0.24 0.2 -40 -25 -10 5 20 35 50 65 80 TA- Free-Air Temperature - ºC Figure40. INL 1.75 +VA= 5 V 1.5 1.0 0.5 s - Bit 0 L N I -0.5 -1.0 -1.5 -1.75 0 10000 20000 30000 40000 50000 60000 Code Figure41. DNL 1 +VA= 5 V 0.5 s Bit - 0 L N D -0.5 -1 0 10000 20000 30000 40000 50000 60000 Code Figure42. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) INL 1.75 +VA= 3 V 1.5 1.0 0.5 s - Bit 0 L N I -0.5 -1.0 -1.5 -1.75 0 10000 20000 30000 40000 50000 60000 Code Figure43. DNL 1 +VA= 3 V 0.5 s Bit - 0 L N D -0.5 -1 0 10000 20000 30000 40000 50000 60000 Code Figure44. FFT 0 5 kHz Input, -20 +VA= 3 V, fs= 1 MSPS, -40 Vref= 2.5 V B d -60 e - ud -80 plit m-100 A -120 -140 -160 0 100 200 300 400 500 f - Frequency - kHz Figure45. 20 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 TYPICAL CHARACTERISTICS (continued) FFT 0 10 kHz Input, -20 +VA= 3 V, fs= 1 MSPS, -40 Vref= 2.5 V dB -60 e - d -80 u mplit-100 A -120 -140 -160 0 100 200 300 400 500 f - Frequency - kHz Figure46. FFT 0 100 kHz Input, -20 +VA= 3 V, fs= 1 MSPS, -40 Vref= 2.5 V B e - d -60 ud -80 plit m -100 A -120 -140 -160 0 100 200 300 400 500 f - Frequency - kHz Figure47. FFT 0 -20 5 kHz Input, +VA= 5 V, -40 fs= 1 MSPS, B Vref= 5 V d e - -60 d u plit -80 m A -100 -120 -140 -160 0 100 200 300 400 500 f - Frequency - kHz Figure48. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) FFT 20 0 10 kHz Input, +VA= 5 V, -20 fs= 1 MSPS, B -40 Vref= 5 V d de - -60 u plit -80 m A -100 -120 -140 -160 0 100 200 300 400 500 f - Frequency - kHz Figure49. FFT 0 100 kHz Input, -20 +VA= 5 V, -40 fs= 1 MSPS, Vref= 5 V B d -60 e - ud -80 mplit-100 A -120 -140 -160 0 100 200 300 400 500 f - Frequency - kHz Figure50. THEORY OF OPERATION The ADS8329/30 is a high-speed, low power, successive approximation register (SAR) analog-to-digital converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which inherentlyincludesasample/holdfunction. The ADS8329/30 has an internal clock that is used to run the conversion but can also be programmed to run the conversionbasedontheexternalserialclock,SCLK. The ADS8329 has one analog input. The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversionisinprogress,both+INand–INinputsaredisconnectedfromanyinternalfunction. TheADS8330 has two inputs. Both inputs share the same common pin, COM. The negative input is the same as the –IN pin for the ADS8329. The ADS8330 can be programmed to select a channel manually or can be programmedintotheautochannelselectmodetosweepbetweenchannel0and1automatically. ANALOG INPUT When the converter enters hold mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. The voltage on the –IN input is limited between AGND – 0.2 V and AGND + 0.2 V, allowing the input to reject small signals which are common to both the +IN and –IN inputs. The +IN input has a rangeof–0.2VtoV +0.2V.Theinputspan[+IN–(–IN)]islimitedto0VtoV . REF REF 22 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. The current into the ADS8329/30 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (45 pF) to a 16-bit settling level within the minimumacquisitiontime(120ns).Whentheconvertergoesintoholdmode, the input impedance is greater than 1GΩ. Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN and –IN inputs and the span [+IN – (–IN)] should be within the limits specified. Outside of these ranges, converter linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters should be used. Care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. If this is not observed, the two inputs could have different settling times. This may resultinanoffseterror,gainerror,andlinearityerrorwhichchangewithtemperatureandinputvoltage. Device in Hold Mode 40 pF 150 (cid:1) +IN 4 pF +VA 4 pF AGND 150 (cid:1) 40 pF −IN AGND Figure51.InputEquivalentCircuit Driver Amplifier Choice The analog input to the converter needs to be driven with a low noise, op-amp like the THS4031 or OPA365. An RC filter is recommended at the input pins to low-pass filter the noise from the source. Two resistors of 20 Ω and acapacitorof470pFarerecommended.Theinputtotheconverter is a unipolar input voltage in the range 0 V to V .Theminimum–3dBbandwidthofthedrivingoperationalamplifiercanbecalculatedto: REF f =(ln(2)×(n+1))/(2p ×t ) 3db ACQ where n is equal to 16, the resolution of the ADC (in the case of the ADS8329/30). When t = 120 ns ACQ (minimum acquisition time), the minimum bandwidth of the driving amplifier is 15.6 MHz. The bandwidth can be relaxed if the acquisition time is increased by the application. The OPA365, OPA827, or THS4031 from Texas Instruments are recommended. The THS4031 used in the source follower configuration to drive the converter is shown in the typical input drive configuration, Figure 52. For the ADS8330, a series resistor of 0Ω should be usedontheCOMpin(ornoresistoratall). Bipolar to Unipolar Driver In systems where the input is bipolar, the THS4031 can be used in the inverting configuration with an additional DC bias applied to its + input so as to keep the input to the ADS8329/30 within its rated operating voltage range. This configuration is also recommended when the ADS8329/30 is used in signal processing applications where good SNR and THD performance is required. The DC bias can be derived from the REF3225 or the REF3240 reference voltage ICs. The input configuration shown in Figure 53 is capable of delivering better than 91 dB SNR and–96dBTHDataninputfrequencyof10kHz.Incasebandpassfiltersareusedtofiltertheinput,careshould be taken to ensure that the signal swing at the input of the bandpass filter is small so as to keep the distortion introduced by the filter minimal. In such cases, the gain of the circuit shown in Figure 53 can be increased to keep the input to the ADS8329/30 large to keep the SNR of the system high. Note that the gain of the system from the + input to the output of the THS4031 in such a configuration is a function of the gain of the AC signal. A resistor divider can be used to scale the output of the REF3225 or REF3240 to reduce the voltage at the DC inputtoTHS4031tokeepthevoltageattheinputoftheconverterwithinitsratedoperatingrange. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com Input ADS8329 5 V Signal (0 V to 4 V) +VA 20W THS4031 +IN 470 pF -IN 50W 20W Figure52.UnipolarInputDriveConfiguration ADS8329 5 V 1V DC +VA 20W 600W THS4031 +IN 470 pF Input -IN (-2S Vig ntoa l2 V) 600W 20W Figure53.BipolarInputDriveConfiguration REFERENCE The ADS8329/30 can operate with an external reference with a range from 0.3 V to 5 V. A clean, low noise, well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A low noise band-gap reference like the REF3240 can be used to drive this pin. A 22-m F ceramic decoupling capacitor is required between the REF+ and REF– pins of the converter. These capacitors should be placed as close as possible to the pins of the device. The REF– should be connected to its own via to the analog ground plane with theshortestpossibledistance. CONVERTER OPERATION The ADS8329/30 has an oscillator that is used as an internal clock which controls the conversion rate. The frequency of this clock is 21 MHz minimum. The oscillator is always on unless the device is in the deep power-down state or the device is programmed for using SCLK as the conversion clock (CCLK). The minimum acquisition (sampling) time takes 3 CCLKs (this is equivalent to 120 ns at 24.5 MHz) and the conversion time takes18conversionclocks(CCLK)(» 780ns)tocompleteoneconversion. The conversion can also be programmed to run based on the external serial clock, SCLK, if is so desired. This allows a system designer to achieve system synchronization. The serial clock SCLK, is first reduced to 1/2 of its frequency before it is used as the conversion clock (CCLK). For example, with a 42-MHz SCLK this provides a 21-MHz clock for conversions. If it is desired to start a conversion at a specific rising edge of the SCLK when the external SCLK is programmed as the source of the conversion clock (CCLK) (and manual start of conversion is selected), the setup time between CONVST and that rising SCLK edge should be observed. This ensures the conversion is complete in 18 CCLKs (or 36 SCLKs). The minimum setup time is 20 ns to ensure synchronization between CONVST and SCLK. In many cases the conversion can start one SCLK period (or CCLK) later which results in a 19 CCLK (or 37 SCLK) conversion. The 20 ns setup time is not required once synchronization is relaxed. 24 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 The duty cycle of SCLK is not critical as long as it meets the minimum high and low time requirements of 8 ns. Since the ADS8329/30 is designed for high-speed applications, a higher serial clock (SCLK) must be supplied to be able to sustain the high throughput with the serial interface and so the clock period of SCLK must be at most 1 m s (when used as conversion clock (CCLK). The minimum clock frequency is also governed by the parasitic leakageofthecapacitivedigital-to-analog(CDAC)capacitorsinternaltotheADS8329/30. CFR_D10 Conversion Clock = 1 OSC (CCLK) SPI Serial Divider Clock (SCLK) = 0 1/2 Figure54.ConverterClock ManualChannelSelectMode The conversion cycle starts with selecting an acquisition channel by writing a channel number to the command register(CMR).Thiscycletimecanbeasshortas4serialclocks(SCLK). AutoChannelSelectMode Channel selection can also be done automatically if auto channel select mode is enabled. This is the default channel select mode. The dual channel converter, ADS8330, has a built-in 2-to-1 MUX. If the device is programmed for auto channel select mode then signals from channel 0 and channel 1 are acquired with a fixed order. Channel 0 is accessed first in the next cycle after the command cycle that configured CFR_D11 to 1 for auto channel select mode. This automatic access stops the cycle after the command cycle that sets CFR_D11 to 0. StartofaConversion The end of acquisition or sampling instance (EOS) is the same as the start of a conversion. This is initiated by bringing the CONVST pin low for a minimum of 40 ns. After the minimum requirement has been met, the CONVST pin can be brought high. CONVST acts independent of FS/CS so it is possible to use one common CONVST for applications requiring simultaneous sample/hold with multiple converters. The ADS8329/30 switches from sample to hold mode on the falling edge of the CONVST signal. The ADS8329/30 requires 18 conversion clock (CCLK) edges to complete a conversion. The conversion time is equivalent to 1500 ns with a 12-MHzinternalclock.TheminimumtimebetweentwoconsecutiveCONVSTsignalsis21CCLKs. A conversion can also be initiated without using CONVST if it is so programmed (CFR_D9 = 0). When the converter is configured as auto trigger, the next conversion is automatically started 3 conversion clocks (CCLK) after the end of a conversion. These 3 conversion clocks (CCLK) are used as the acquisition time. In this case thetimetocompleteoneacquisitionandconversioncycleis21CCLKs. Table1.DifferentTypesofConversion MODE SELECTCHANNEL STARTCONVERSION AutoChannelSelect(1) AutoTrigger Automatic NoneedtowritechannelnumbertotheCMR.Useinternalsequencerforthe Startaconversionbasedontheconversion ADS8330. clockCCLK. ManualChannelSelect ManualTrigger Manual WritethechannelnumbertotheCMR. StartaconversionwithCONVST. (1) AutochannelselectshouldbeusedwithautotriggerandalsowiththeTAGbitenabled. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com StatusOutputEOC/INT When the status pin is programmed as EOC and the polarity is set as active low, the pin works in the following manner: The EOC output goes LOW immediately following CONVST going LOW when manual trigger is programmed. EOC stays LOW throughout the conversion process and returns to HIGH when the conversion has ended. The EOC output goes low for 3 conversion clocks (CCLK) after the previous rising edge of EOC, if auto triggerisprogrammed. This status pin is programmable. It can be used as an EOC output (CFR_D[7:6] = 1, 1) where the low time is equal to the conversion time. This status pin can be used as INT. (CFR_D[7:6] = 1, 0) which is set LOW at the end of a conversion is brought to HIGH (cleared) by the next read cycle. The polarity of this pin, used as either function(EOCorINT),isprogrammablethroughCFR_D7. Power-DownModes The ADS8329/30 has a comprehensive built-in power-down feature. There are three power-down modes: Deep power-down mode, Nap power-down mode, and auto nap power-down mode. All three power-down modes are enabled by setting the related CFR bits. The first two power-down modes are activated when enabled. A wakeup command, 1011b, can resume device operation from a power-down mode. Auto nap power-down mode works slightly different. When the converter is enabled in auto nap power-down mode, an end of conversion instance (EOC)putsthedeviceintoautonappower-down.The beginning of sampling resumes operation of the converter. The contents of the configuration register is not affected by any of the power-down modes. Any ongoing conversionwhennapordeeppower-downisactivatedisaborted. 100 A (cid:1) − nt 10 e r r u C y pl p u S − A 1 V + 0.1 20 10020 20020 30020 40020 Settling Time − ns Figure55.TypicalAnalogSupplyCurrentDropvsTimeAfterPower-Down 26 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 DeepPower-DownMode Deep power-down mode can be activated by writing to configuration register bit CFR_D2. When the device is in deep power-down mode, all blocks except the interface are in power-down. The external SCLK is blocked to the analog block. The analog blocks no longer have bias currents and the internal oscillator is turned off. In this mode, supply current falls from 7 mA to 4 nA in 100 ns. The wake-up time after a power-down is 1 m s. When bit D2 in the configuration register is set to 0, the device is in deep power-down. Setting this bit to 1 or sending a wake-upcommandcanresumetheconverterfromthedeeppower-downstate. NapMode In nap mode the ADS8329/230 turns off biasing of the comparator and the mid-volt buffer. In this mode supply current falls from 7 mA in normal mode to about 0.3 mA in 200 ns after the configuration cycle. The wake-up (resume) time from nap power-down mode is 3 CCLKs (120 ns with a 24.5-MHz conversion clock). As soon as the CFR_D3 bit in the control register is set to 0, the device goes into nap power-down mode, regardless of the conversion state. Setting this bit to 1 or sending a wake-up command can resume the converter from the nap power-downstate. AutoNapMode Auto nap mode is almost identical to nap mode. The only difference is the time when the device is actually powered down and the method to wake up the device. Configuration register bit D4 is only used to enable/disable auto nap mode. If auto nap mode is enabled, the device turns off biasing after the conversion has finished, which means the end of conversion activates auto nap power-down mode. Supply current falls from 7 mA in normal mode to about 0.3 mA in 200 ns. A CONVST resumes the device and turns biasing on again in 3 CCLKs (120 ns with a 24.5-MHz conversion clock). The device can also be woken up by disabling auto nap mode when bit D4 of the configuration register is set to 1. Any channel select command 0XXXb, wake up commandorthesetdefaultmodecommand1111bcanalsowakeupthedevicefromautonappower-down. NOTE: 1. This wake-up command is the word 1011b in the command word. This command sets bits D2 and D3 to 1 in the configuration register but not D4. But a wake-up command does remove the device from either one of these power-down states, deep/nap/auto nap power-down. 2. Wake-uptimeisdefinedasthetimebetweenwhenthehostprocessortriestowakeupthe converterandwhenaconvertstartcanoccur. Table2.Power-DownModeComparisons POWER TYPEOF CONSUMPTION: RESUME POWER-DOWN 5V/3V ACTIVATEDBY ACTIVATIONTIME RESUMEPOWERBY TIME ENABLE Normaloperation 7mA/5.1mA Deeppower-down 4nA/2nA SettingCFR 100ns Wokenupbycommand1011b 1m s SetCFR Wokenupbycommand1011bto Nappower-down 0.3mA/0.25mA SettingCFR 200ns 3CCLKs SetCFR achieve6.6mAsince(1.3+12)/2=6.6 WokenupbyCONVST,anychannel Autonap EOC(endof 200ns selectcommand,defaultcommand 3CCLKs SetCFR power-down conversion) 1111b,orwakeupcommand1011b. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com CONVST N Converter State N+1 EOS EOC EOS EOC CoSntvaeterter N −th Conversion N+1 −th Sampling N+1 −th Conversion Read While Converting 20 ns MIN 1 CCLK MIN CS (For Read Result) Read N−1 −th Result Read While Sampling 0 ns MIN 20 ns MIN CS (For Read Result) Read N −th Result Figure56.ReadWhileConvertingversusReadWhileSampling(ManualTrigger) Manual Trigger CONVST N N+1 S C S C O O O O E E E E Converter State Resume N −th Sampling N −th Conversion Activation Resume N+1 −th Sampling N+1 −th Conversion Activation >=3CCLK =18 CCLK >=3CCLK =18 CCLK 20 ns MIN 1 CCLK MIN 20 ns MIN Read While Converting Read N−1 −th Read N −th CS Result Result 20 ns MIN Read While Sampling 20 ns MIN 0 ns MIN Read N−1 −th 20 ns MIN 20 ns MIN Read N −th CS Result Result 20 ns MIN 20 ns MIN Figure57.ReadWhileConvertingversusReadWhileSamplingwithDeeporNapPower-Down 28 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 Manual Trigger Case 1 40 ns MIN CONVST N N+1 EOC (programmed Active Low) EOS EOC EOS EOC Converter Resume N −th Sampling N −th Conversion POWERDOWN Resume N+1 −th Sampling N+1 −th Conversion POWERDOWN State >=3CCLK =18 CCLK >=3CCLK =18 CCLK 6 CCLKs 6 CCLKs Read While Converting 20 ns MIN 20 ns MIN Read N−1 −th Read N −th CS Result Result 20 ns MIN 20 ns MIN Read While Sampling 1 CCLK MIN 1 CCLK MIN 0 ns MIN Read N−1 −th Read N −th CS Result Result 20 ns MIN 20 ns MIN 40 ns MIN Manual Trigger Case 2 (wake up by CONVST) CONVST N N+1 EOC (programmed Active Low) OS OC OS OC E E E E CoSntvaeterter Resume N −th Sampling N −th Conversion PDOOWWENR Resume N+1 −th Sampling N+1 −th Conversion PDOOWWENR >=3CCLK =18 CCLK >=3CCLK =18 CCLK Read While Converting 20 ns MIN 20 ns MIN Read N−1 −th Read N −th CS Result Result Read While Sampling 20 ns MIN 20 ns MIN 20 ns MIN 0 ns MIN 20 ns MIN Read N−1 −th Read N −th CS Result Result 20 ns MIN 20 ns MIN Figure58.ReadWhileConvertingversusReadWhileSamplingwithAutoNapPower-Down TotalAcquisition+ConversionCycleTime: Automatic: =21CCLKs Manual: ≥21CCLKs Manual+deep ≥4SCLK+100m s+3CCLK+18CCLK+16SCLK+1m s power-down: Manual+nappower-down: ≥4SCLK+3CCLK+3CCLK+18CCLK+16SCLK Manual+autonap ≥4SCLK+3CCLK+3CCLK+18CCLK+16SCLK(usewakeuptoresume) power-down: Manual+autonap ≥1CCLK+3CCLK+3CCLK+18CCLK+16SCLK(useCONVSTtoresume) power-down: Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com DIGITAL INTERFACE The serial clock is designed to accommodate the latest high-speed processors with an SCLK frequency up to 50 MHz. Each cycle is started with the falling edge of FS/CS. The internal data register content which is made available to the output register at the EOC presented on the SDO output pin at the falling edge of FS/CS. This is theMSB. Output data are valid at the falling edge of SCLK with t delay so that the host processor d(SCLKF-SDOVALID) canreaditatthefallingedge.SerialdatainputisalsoreadatthefallingedgeofSCLK. The complete serial I/O cycle starts with the first falling edge of SCLK after the falling edge of FS/CS and ends 16 (see NOTE) falling edges of SCLK later. The serial interface is very flexible. It works with CPOL = 0 , CPHA = 1 or CPOL = 1, CPHA = 0. This means the falling edge of FS/CS may fall while SCLK is high. The same relaxation applies to the rising edge of FS/CS where SCLK may be high or low as long as the last SCLK falling edgehappensbeforetherisingedgeofFS/CS. NOTE: There are cases where a cycle is 4 SCLKs or up to 24 SCLKs depending on the read modecombination.SeeTable3fordetails. InternalRegister The internal register consists of two parts, 4 bits for the command register (CMR) and 12 bits for configuration dataregister(CFR). Table3.CommandSetDefinedbyCommandRegister(CMR)(1) WAKEUPFROM MINIMUMSCLKs D[15:12] HEX COMMAND D[11:0] AUTONAP REQUIRED R/W 0000b 0h Selectanaloginputchannel0(2) Don'tcare Y 4 W 0001b 1h Selectanaloginputchannel1(2) Don'tcare Y 4 W 0010b 2h Reserved Reserved – – – 0011b 3h Reserved Reserved – – – 0100b 4h Reserved Reserved – – – 0101b 5h Reserved Reserved – – – 0110b 6h Reserved Reserved – – – 0111b 7h Reserved Reserved – – – 1000b 8h Reserved Reserved – – – 1001b 9h Reserved Reserved – – – 1010b Ah Reserved Reserved – – – 1011b Bh Wakeup Don'tcare Y 4 W 1100b Ch ReadCFR Don'tcare – 16 R 1101b Dh Readdata Don'tcare – 16 R 1110 Eh WriteCFR CFRvalue – 16 W 1111b Fh Defaultmode(loadCFRwithdefaultvalue) Don'tcare Y 4 W (1) WhenSDOisnotin3-state(FS/CSlowandSCLKrunning),thebitsfromSDOarealwayspart(dependingonhowmanySCLKsare supplied)ofthepreviousconversionresult. (2) ThesetwocommandsapplytotheADS8330only. WRITING TO THE CONVERTER There are two different types of writes to the register, a 4-bit write to the CMR and a full 16-bit write to the CMR plus CFR. The command set is listed in Table 3. A simple command requires only 4 SCLKs and the write takes effect at the 4th falling edge of SCLK. A 16-bit write or read takes at least 16 SCLKs (see Table 6 for exceptions thatrequiremorethan16SCLKs). 30 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 ConfiguringtheConverterandDefaultMode The converter can be configuring with command 1110b (write to the CFR) or command 1111b (default mode). A write to the CFR requires a 4-bit command followed by 12-bits of data. A 4-bit command takes effect at the 4th fallingedgeofSCLK.ACFRwritetakeseffectatthe16thfallingedgeofSCLK. A default mode command can be achieved by simply tying SDI to +VBD. As soon as the chip is selected at least four 1s are clocked in by SCLK. The default value of the CFR is loaded into the CFR at the 4th falling edge of SCLK. CFRdefaultvaluesareall1s(exceptforCFR_D1,thisbitis ignored by the ADS8329 and is always read as a 0). ThesamedefaultvaluesapplyfortheCFRafterapower-onreset(POR)andSWreset. READING THE CONFIGURATION REGISTER The host processor can read back the value programmed in the CFR by issuing command 1100b. The timing is similar to reading a conversion result except CONVST is not used and there is no activity on the EOC/INT pin. TheCFRvaluereadbackcontainsthefirstfourMSBsofconversiondataplusvalid12-bitCFRcontents. Table4.ConfigurationRegister(CFR)Map SDIBIT CFR-D[11-0] DEFINITION Channelselectmode D11default=1 0:Manualchannelselectenabled.Usechannelselectcommandsto 1:Autochannelselectenabled.Allchannelsaresampledand accessadifferentchannel. convertedsequentiallyuntilthecycleafterthisbitissetto0. Conversionclock(CCLK)sourceselect D10default=1 0:Conversionclock(CCLK)=SCLK/2 1:Conversionclock(CCLK)=InternalOSC Trigger(conversionstart)select:startconversionattheendofsampling(EOS).IfD9=0,theD4settingisignored. D9default=1 0:Autotriggerautomaticallystarts(4internalclocksafterEOCinactive) 1:ManualtriggermanuallystartedbyfallingedgeofCONVST D8default=1 Don'tcare Don'tcare Pin10polarityselectwhenusedasanoutput(EOC/INT) D7default=1 0:EOCActivehigh/INTactivehigh 1:EOCactivelow/INTactivelow Pin10functionselectwhenusedasanoutput(EOC/INT) D6default=1 0:PinusedasINT 1:PinusedasEOC Pin10I/Oselectforchainmodeoperation D5default=1 0:Pin10isusedasCDIinput(chainmodeenabled) 1:Pin10isusedasEOC/INToutput Autonappower-downenable/disable(midvoltageandcomparatorshutdownbetweencycles).ThisbitsettingisignoredifD9=0. D4default=1 0:Autonappower-downenabled(notactivated) 1:Autonappower-downdisabled Nappower-down(midvoltageandcomparatorshutdownbetweencycles).Thisbitissetto1automaticallybywake-upcommand. D3default=1 0:Enable/activatedeviceinnappower-down 1:Removedevicefromnappower-down(resume) Deeppower-down.Thisbitissetto1automaticallybywake-upcommand. D2default=1 0:Enable/activatedeviceindeeppower-down 1:Removedevicefromdeeppower-down(resume) D1default= TAGbitenable.ThisbitisignoredbytheADS8329andisalwaysread0. 0:ADS8329 1:ADS8330 0:TAGbitdisabled. 1:TAGbitoutputenabled.TAGbitappearsatthe17thSCLK. Reset D0default=1 0:Systemreset 1:Normaloperation READING CONVERSION RESULT The conversion result is available to the input of the output data register (ODR) at EOC and presented to the output of the output register at the next falling edge of CS or FS. The host processor can then shift the data out via the SDO pin any time except during the quiet zone. This is 20 ns before and 20 ns after the end of sampling (EOS) period. End of sampling (EOS) is defined as the falling edge of CONVST when manual trigger is used or theendofthe3rdconversionclock(CCLK)afterEOCifautotriggerisused. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com The falling edge of FS/CS should not be placed at the precise moment (minimum of at least one conversion clock(CCLK)delay)attheendofaconversion(bydefaultwhenEOCgoeshigh),otherwisethe data is corrupt. If FS/CS is placed before the end of a conversion, the previous conversion result is read. If FS/CS is placed after theendofaconversion,thecurrentconversionresultisread. The conversion result is 16-bit data in straight binary format as shown in Table 4. Generally 16 SCLKs are necessary, but there are exceptions where more than 16 SCLKS are required (see Table 6). Data output from the serial output (SDO) is left adjusted MSB first. The trailing bits are filled with the TAG bit first (if enabled) plus allzeros.SDOremainslowuntilFS/CSisbroughthighagain. SDOisactivewhenFS/CSislow.TherisingedgeofFS/CS3-statestheSDOoutput. NOTE: Whenever SDO is not in 3-state (when FS/CS is low and SCLK is running), a portion of the conversion result is output at the SDO pin. The number of bits depends on how many SCLKs are supplied. For example, a manual select channel command cycle requires 4 SCLKs, therefore 4 MSBs of the conversion result are output at SDO. The exception is SDO outputs all 1s during the cycle immediately after any reset (POR or softwarereset). If SCLK is used as the conversion clock (CCLK) and a continuous SCLK is used, it is not possible to clock out all 16 SDO bits during the sampling time (6 SCLKs) because of the quiet zone requirement. In this case it is better toreadtheconversionresultduringtheconversiontime(36SCLKsor48SCLKsinautonapmode). Table5.IdealInputVoltagesandOutputCodes DESCRIPTION ANALOGVALUE DIGITALOUTPUT Full-scalerange V STRAIGHTBINARY REF Leastsignificantbit(LSB) V /65536 BINARYCODE HEXCODE REF Full-scale +V –1LSB 1111111111111111 FFFF REF Midscale V /2 1000000000000000 8000 REF Midscale–1LSB V /2–1LSB 0111111111111111 7FFF REF Zero 0V 0000000000000000 0000 TAGMode The ADS8330 includes a feature, TAG, that can be used as a tag to indicate which channel sourced the converted result. An address bit is added after the LSB read out from SDO indicating which channel the result came from if TAG mode is enabled. This address bit is 0 for channel 0 and 1 for channel 1. The converter requires more than the 16 SCLKs that are required for a 4 bit command plus 12 bit CFR or 16 data bits because oftheadditionalTAGbit. ChainMode The ADS8329/30 can operate as a single converter or in a system with multiple converters. System designers can take advantage of the simple high-speed SPI compatible serial interface by cascading them in a single chain when multiple converters are used. A bit in the CFR is used to reconfigure the EOC/INT status pin as a secondary serial data input, chain data input (CDI), for the conversion result from an upstream converter. This is chainmodeoperation.AtypicalconnectionofthreeconvertersisshowninFigure59. 32 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 Micro Controller INT GPIO1 GPIO2 GPIO3 SDOSCLK SDI SDISCLKCONVST SDISCLKCONVST SDI SCLKCONVST CS CS CS ADS8329 ADS8329 ADS8329 #1 #2 #3 EOC/INT SDO CDI SDO CDI SDO Program device #1 CFR_D[7:5] = XX0b Program device #2 and #3 CFR_D[7:5] = XX1b Figure59.MultipleConvertersConnectedUsingChainMode When multiple converters are used in chain mode, the first converter is configured in regular mode while the rest of the converters downstream are configured in chain mode. When a converter is configured in chain mode, the CDI input data goes straight to the output register, therefore the serial input data passes through the converter with a 16 SCLK (if the TAG feature is disabled) or a 24 SCLK delay, as long as CS is active. See Figure 60 for detailedtiming.Inthistimingtheconversionineachconvertersaredonesimultaneously. CascadedManual Trigger/Read While Sampling (Useinternal CCLK, EOC active low, andINTactive low) C S held lowduring the N times 16 bits transfer cycle. CONVST#1, CONVST#2, CONVST#3 S C S O O O EOC #1 E Nth E E (active low) INT#3 tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs min (activelow) t = 20 ns min d(CSR-EOS) CS/FS #1 SCLK #1, SCLK #2, 1. . . . . . . . . . . . . . . . . . 16 1. . . . . . . . . . . . . . . . . . 16 1 . . . . . . . . . . . . . . . . . . 16 SCLK #3 Hi-Z Hi-Z SDO #1, CDI #2 Nth from #1 t = 20 ns min d(CSR-EOS) CS/FS #2, CS/FS #3 t d(SDO-CDI) SDO #2, Hi-Z Hi-Z CDI #3 N−1th from #2 Nth from #1 Nth from #1 t Hi-Z d(SDO-CDI) Hi-Z SDO #3 Nth from #3 N−1th from #2 Nth from #1 SDI #1, SDI #2, SDI #3 1110............ 1101b 1101b CONFIGURE READ Result READ Result Figure60.SimplifiedCascadeModeTimingwithSharedCONVSTandContinuousCS Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com Care must be given to handle the multiple CS signals when the converters are operating in chain mode. The different chip select signals must be low for the entire data transfer (in this example 48 bits for three converters). The first 16-bit word after the falling chip select is always the data from the chip that received the chip select signal. Case1:Ifchipselectisnottoggled(CSstayslow),thenext16bitsaredatafromtheupstreamconverter,andso on.ThisisshowninFigure60.Ifthereisnoupstream converter in the chain, as converter #1 in the example, the samedatafromtheconverterisgoingtobeshownrepeatedly. Case 2: If the chip select is toggled during a chain mode data transfer cycle, as illustrated in Figure 61, the same datafromtheconverterisreadoutagainandagaininallthreediscrete16-bitcycles.Thisisnotadesiredresult. CascadedManual Trigger/Read While Sampling (Use internal CCLK, EOC, andINTpolarity programmed as active low) CSheld low during the N times 16 bits transfer cycle. CONVST#1, CONVST#2, CONVST#3 S C S O O O EOC #1 E Nth E E (active low) t = 3 CCLKs min INT#1 t = 18 CCLKs SAMPLE1 CONV t = 20 ns min t = 20 ns min (activelow) d(EOS-CSF) d(CSR-EOS) CS/FS #1 SCLK #1, SCLK #2, 1 16 1 16 1 16 SCLK #3 SDO #1, CDI #2 Nthfrom #1 Nth from #1 Nth from #1 t = t = d(EOS-CSF) d(CSR-EOS) CS/FS #2 20 ns min 20 ns min SCLK #2, SDO #2, CDI #3 N−1th from #2 Nth from #1 Nth from #1 CS/FS #3 td(EOS-CSF) = td(CSR-EOS) = 20 ns min 20 ns min SDO #3 SDI #1, Nth from #3 N−1th from #2 Nth from #1 SDI #2, SDI #3 1110............ 1101b 1101b CONFIGURE READ Result READ Result Figure61.SimplifiedCascadeModeTimingwithSharedCONVSTandDiscreteCS Figure 62 shows a slightly different scenario where CONVST is not shared by the second converter. Converters #1 and #3 have the same CONVST signal. In this case, converter #2 simply passes previous conversion data downstream. 34 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 CascadedManual Trigger/Read While Sampling (Use internal CCLK, EOC active low andINTactive low) CSheld low during the N times 16 bits transfer cycle. CONVST#1, Note : old data shown. CONVST#3 CONVST#2 = 1 S C S O O O EOC #1 E Nth E E (active low) INT#1 tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs min (activelow) t = 20 ns min CS/FS #1 d(CSR-EOS) SCLK #1, SCLK #2, 1 . . . . . . . . . . . . . . . . . .16 1. . . . . . . . . . . . . . . . . .16 1 . . . . . . . . . . . . . . . . . .16 SCLK #3 Hi-Z Hi-Z SDO #1, CDI #2 Nth from #1 t = 20 ns min d(CSR-EOS) CS/FS #2, CS/FS #3 t d(SDO-CDI) SDO #2, Hi-Z Hi-Z CDI #3 N−1th from #2 Nth from #1 t d(SDO-CDI) SDO #3 Hi-Z Hi-Z SDI #1, Nth from #3 N−1th from #2 Nth from #1 SDI #2, SDI #3 1110............ 1101b 1101b CONFIGURE READ Result READ Result Figure62.SimplifiedCascadeTiming(SeparateCONVST) The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG bit,chainmode,andthewayachannelisselected(thatis,autochannelselect).ThisislistedinTable6. Table6.RequiredSCLKsForDifferentReadOutModeCombinations CHAINMODE AUTOCHANNEL NUMBEROFSCLKPERSPI ENABLEDCFR.D5 SELECTCFR.D11 TAGENABLEDCFR.D1 READ TRAILINGBITS 0 0 0 16 None 0 0 1 ≥17 MSBisTAGbitpluszero(s) 0 1 0 16 None 0 1 1 ≥17 TAGbitplus7zeros 1 0 0 16 None 1 0 1 24 TAGbitplus7zeros 1 1 0 16 None 1 1 1 24 TAGbitplus7zeros Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com SCLK skew between converters and data path delay through the converters configured in chain mode can affect the maximum frequency of SCLK. The delay can also be affected by supply voltage and loading. It may be necessarytoslowdowntheSCLKwhenthedevicesareconfiguredinchainmode. ADS8329#3 CDI SDO Serial data output Logic D Logic Q Logic Delay Delay Delay Plus PAD <=8.3ns Plus PAD 2.7 ns 8.3 ns CLK ADS8329#2 CDI SDO Logic Logic D Q Logic Delay Delay Delay Plus PAD <=8.3ns Plus PAD 2.7 ns 8.3 ns CLK ADS8329#1 CDI SDO Logic Logic D Q Logic Serial data Delay Delay Delay input Plus PAD <=8.3ns Plus PAD 2.7 ns 8.3 ns CLK SCLK input Figure63.TypicalDelayThroughConvertersConfiguredinChainMode RESET The converter has two reset mechanisms, a power-on reset (POR) and a software reset using CFR_D0. These twomechanismsareNOR-edinternally.Whenareset(softwareorPOR)isissued, all register data are set to the default values (all 1s) and the SDO output (during the cycle immediately after reset) is set to all 1s. The state machineisresettothepower-onstate. SW RESET CDI POR SET SAR Shift Intermediate Output SDO Register Latch Register SCLK Conversion Clock Latched by End Of Latched by Falling Edge of CS Conversion CS EOC EOC Figure64.DigitalOutputUnderResetCondition 36 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 When the device is powered up, the POR sets the device to default mode when AVDD reaches 1.5V. When the device is powered down, the POR circuit requires AVDD to remain below 125mV for at least 350ms to ensure proper discharging of internal capacitors and to correct the behavior of the ADC when powered up again. If AVDD drops below 400mV but remains above 125mV, the internal POR capacitor does not discharge fully and the device requires a software reset to perform correctly after the recovery of AVDD (this condition is shown as theundefinedzoneinFigure65). AVDD (V) 5.500 5.000 Specified Supply 4.000 Voltage Range 3.000 2.700 2.000 POR 1.500 Trigger Level 1.000 0.400 Undefined Zone 0.125 0 0.350 t (s) Figure65.RelevantVoltageLevelsforPOR Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 SLAS516C–DECEMBER2006–REVISEDJULY2009................................................................................................................................................... www.ti.com APPLICATION INFORMATION TYPICAL CONNECTION Analog +5 V 4.7 (cid:1)F AGND Ext Ref Input 22 (cid:1)F AGND Analog Input +VA REF+ REF−AGND IN+ IN− FS/CS SDO Interface SDI Supply Host SCLK +1.8 V ADS8329 Processor BDGND CONVST 4.7 (cid:1)F +VBD EOC/INT Figure66.TypicalCircuitConfiguration Part Change Notification # 20071101001 The ADS8329 and ADS8330 devices underwent a silicon change under Texas Instruments Part Change Notification (PCN) number 20071101001. Details on this part change can be obtained from the Product Information Center at Texas Instruments or by contacting your local sales/distribution office. Devices with a date codeof82xxandhigherarecoveredbythisPCN. 38 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8329ADS8330

ADS8329 ADS8330 www.ti.com................................................................................................................................................... SLAS516C–DECEMBER2006–REVISEDJULY2009 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(March2008)toRevisionC .................................................................................................. Page • Added12-and14-bitrowstofamilytable............................................................................................................................. 1 • Added+REFtoAGNDand–REFtoAGNDrowstotheVoltagerangeparameteroftheAbsoluteMaximumRatings table....................................................................................................................................................................................... 2 • Changedconditionsfor4.5-VElectricalCharacteristics........................................................................................................ 3 • ChangedtypandmaxspecificationsfortheV [(REF+)–(REF–)]parameterinthe4.5-VElectricalCharacteristics...... 4 REF • ChangedNAP/Auto-NAPandDeeppower-downtestconditionsoftheSupplyCurrentparameterinthe4.5-V ElectricalCharacteristics........................................................................................................................................................ 4 • Changedconditionsforthe2.7-VElectricalCharacteristics.................................................................................................. 5 • ChangedV [(REF+)–(REF–)]parameterinthe2.7-VElectricalCharacteristics............................................................. 6 REF • ChangedNAP/Auto-NAPandDeeppower-downtestconditionsoftheSupplyCurrentparameterinthe Power-SupplyRequirementssectionofthe2.7-VElectricalCharacteristicstable................................................................ 7 • CorrectedtypoinFigure1................................................................................................................................................... 12 • ChangedSDOtraceofFigure2.......................................................................................................................................... 12 • CorrectedtypoinFigure3................................................................................................................................................... 13 • ChangedSDOtraceinFigure4.......................................................................................................................................... 13 • CorrectedtypoinFigure6................................................................................................................................................... 14 • AddedlastsentencetoDriverAmplifierChoicesection...................................................................................................... 23 • UpdatedFigure52............................................................................................................................................................... 24 • UpdatedFigure53............................................................................................................................................................... 24 • ChangedfifthsentenceofDeepPower-DownModesection.............................................................................................. 27 • ChangedsecondsentenceofNapModesection................................................................................................................ 27 • ChangedfifthsentenceofAutoNapModesection............................................................................................................. 27 • ChangedpowerconsumptionandactivationtimecolumnvaluesofTable2...................................................................... 27 • AddedFigure65andcorrespondingparagraphtoRESETsection.................................................................................... 37 ChangesfromRevisionA(March2008)toRevisionB .................................................................................................. Page • Added16-PinTSSOPtoFeaturesbullettoindicatenewpackageavailability..................................................................... 1 • Added16-PinTSSOPtothirdDescriptionparagraphbullettoindicatenewpackageavailability........................................ 1 • ChangedtheOrderingInformationtabletoreflectTSSOPpackageavailability................................................................... 2 • ChangedAbsoluteMaximumRatingstabletoreflectTSSOPpackageavailability.............................................................. 2 • AddedpinoutsforPWpackageforbothADS8329andADS8330...................................................................................... 10 • AddedTSSOPcolumntotheADS8329TerminalFunctionstable...................................................................................... 11 • AddedTSSOPcolumntotheADS8330TerminalFunctionstable...................................................................................... 11 • ChangedthePartChangeNotificationsection.................................................................................................................... 38 Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):ADS8329ADS8330

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS8329IBPW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8329I A B ADS8329IBRSAR ACTIVE QFN RSA 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8329I A ADS8329IBRSAT ACTIVE QFN RSA 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8329I A ADS8329IBRSATG4 ACTIVE QFN RSA 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8329I A ADS8329IPW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8329I A ADS8329IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8329I A ADS8329IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8329I A ADS8329IRSAR ACTIVE QFN RSA 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8329I A ADS8329IRSAT ACTIVE QFN RSA 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8329I A ADS8330IBPW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8330I A B ADS8330IBPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8330I A B ADS8330IBPWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8330I A B ADS8330IBRSAR ACTIVE QFN RSA 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8330I A ADS8330IBRSAT ACTIVE QFN RSA 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8330I A ADS8330IPW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8330I A Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS8330IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8330I A ADS8330IRSAT ACTIVE QFN RSA 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 8330I A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS8329IBRSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS8329IBRSAT QFN RSA 16 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS8329IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS8329IRSAR QFN RSA 16 2000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS8329IRSAT QFN RSA 16 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS8330IBPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS8330IBRSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS8330IBRSAT QFN RSA 16 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS8330IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS8330IRSAT QFN RSA 16 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS8329IBRSAR QFN RSA 16 3000 350.0 350.0 43.0 ADS8329IBRSAT QFN RSA 16 250 210.0 185.0 35.0 ADS8329IPWR TSSOP PW 16 2000 350.0 350.0 43.0 ADS8329IRSAR QFN RSA 16 2000 350.0 350.0 43.0 ADS8329IRSAT QFN RSA 16 250 210.0 185.0 35.0 ADS8330IBPWR TSSOP PW 16 2000 350.0 350.0 43.0 ADS8330IBRSAR QFN RSA 16 3000 350.0 350.0 43.0 ADS8330IBRSAT QFN RSA 16 250 210.0 185.0 35.0 ADS8330IPWR TSSOP PW 16 2000 350.0 350.0 43.0 ADS8330IRSAT QFN RSA 16 250 210.0 185.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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