Product Sample & Technical Tools & Support & Reference Folder Buy Documents Software Community Design ADS8320 SBAS108E–MAY2000–REVISEDDECEMBER2016 ADS8320 16-Bit, High-Speed, 2.7-V to 5-V microPower Sampling Analog-to-Digital Converter 1 Features 3 Description • 100-kHzSamplingRate The ADS8320 device is a 16-bit, sampling analog-to- 1 digital (A/D) converter with ensured specifications • microPower: over a 2.7-V to 5.25-V supply range. It requires very – 1.8mWat100kHzand2.7V little power even when operating at the full 100-kHz – 0.3mWat10kHzand2.7V data rate. At lower data rates, the high speed of the device enables it to spend most of its time in the • PowerDown:3µA(Maximum) power-down mode. The average power dissipation is • 8-PinVSSOPPackage lessthan100mWat10-kHzdatarate. • Pin-CompatibletoADS7816andADS7822 The ADS8320 also features operation from 2 V to • Serial(SPI™/SSI)Interface 5.25 V, a synchronous serial (SPI/SSI compatible) interface, and a differential input. The reference 2 Applications voltage can be set to any level within the range of 500mVtoV . • Battery-OperatedSystems CC • RemoteDataAcquisition Ultra-low power and small size make the ADS8320 ideal for portable and battery-operated systems. It is • IsolatedDataAcquisition also a perfect fit for remote data acquisition modules, • SimultaneousSampling,MultichannelSystems simultaneous multi-channel systems, and isolated • IndustrialControls data acquisition. The ADS8320 is available in an 8-pinVSSOPpackage. • Robotics • VibrationAnalysis DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) ADS8320 VSSOP(8) 3.00mm×3.00mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. BlockDiagram SAR Control V REF D OUT +In CDAC Serial –In Interface DCLOCK CS/SHDN S/H Amp Comparator Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

ADS8320 SBAS108E–MAY2000–REVISEDDECEMBER2016 www.ti.com Table of Contents 1 Features.................................................................. 1 7.4 DeviceFunctionalModes........................................13 2 Applications........................................................... 1 8 ApplicationandImplementation........................ 16 3 Description............................................................. 1 8.1 ApplicationInformation............................................16 4 RevisionHistory..................................................... 2 8.2 TypicalApplications................................................16 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 22 6 Specifications......................................................... 4 10 Layout................................................................... 22 6.1 AbsoluteMaximumRatings......................................4 10.1 LayoutGuidelines.................................................22 6.2 ESDRatings..............................................................4 10.2 LayoutExample....................................................23 6.3 RecommendedOperatingConditions.......................4 10.3 PowerDissipation.................................................23 6.4 ThermalInformation..................................................4 11 DeviceandDocumentationSupport................. 27 6.5 ElectricalCharacteristics:V =5V.........................5 11.1 DocumentationSupport........................................27 CC 6.6 ElectricalCharacteristics:V =2.7V......................6 11.2 ReceivingNotificationofDocumentationUpdates27 CC 6.7 TypicalCharacteristics..............................................8 11.3 CommunityResources..........................................27 7 DetailedDescription............................................ 11 11.4 Trademarks...........................................................27 7.1 Overview.................................................................11 11.5 ElectrostaticDischargeCaution............................27 7.2 FunctionalBlockDiagram.......................................12 11.6 Glossary................................................................27 7.3 FeatureDescription.................................................12 12 Mechanical,Packaging,andOrderable Information........................................................... 27 4 Revision History ChangesfromRevisionD(March2007)toRevisionE Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection ................................................................................................. 1 • AddedThermalInformationtable........................................................................................................................................... 4 • ChangedApplicationCircuitssectionTo:TypicalConnectionDiagram.............................................................................. 11 2 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8320

ADS8320 www.ti.com SBAS108E–MAY2000–REVISEDDECEMBER2016 5 Pin Configuration and Functions DGKPackage 8-PinVSSOP TopView V 1 8 +V REF CC +In 2 7 DCLOCK ADS8320 –In 3 6 D OUT GND 4 5 CS/SHDN PinFunctions PIN TYPE(1) DESCRIPTION NO. NAME 1 V AI Referenceinput REF 2 +In AI Noninvertinginput 3 –In AI Invertinginput:Connecttogroundortoremotegroundsensepoint. 4 GND GND Ground 5 CS/SHDN DI ChipselectwhenLOW;ShutdownmodewhenHIGH. Theserialoutputdatawordiscomprisedof16bitsofdata.Inoperationthedataisvalidon 6 D DO thefallingedgeofD .ThesecondclockpulseafterthefallingedgeofCSenablesthe OUT CLOCK serialoutput.Afteronenullbitthedataisvalidforthenext16edges. 7 D DI Dataclocksynchronizestheserialdatatransferanddeterminesconversionspeed. CLOCK 8 +V PWR Powersupply CC (1) AI=AnalogInput,DI=DigitalInput,DO=DigitalOutput,GND=Ground,PWR=Power Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:ADS8320

ADS8320 SBAS108E–MAY2000–REVISEDDECEMBER2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V 6 V CC Analoginput –0.3 V +0.3 V CC Logicinput –0.3 6 °C Externalreferencevoltage 5.5 V Inputcurrenttoanypinexceptsupply ±10 mA Casetemperature 100 °C Junctiontemperature 150 °C Storagetemperature,T 125 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 ESD Ratings VALUE UNIT Electrostatic Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V V (ESD) discharge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT Lowvoltagelevels 2.7 3.3 Supplyvoltage,V toGND V CC 5-Vlogiclevels 4.75 5 5.25 Referenceinputvoltage,V 0.5 V V REF CC –INtoGND –0.1 0 0.5 Analoginputvoltage +INtoGND –0.1 V +0.1 V CC +INto–(–IN) 0 V REF Operatingtemperature,T –40 85 °C A 6.4 Thermal Information ADS8320 THERMALMETRIC(1) DGK(VSSOP) UNIT 8PINS R Junction-to-ambientthermalresistance 163.1 °C/W θJA R Junction-to-case(top)thermalresistance 56.6 °C/W θJC(top) R Junction-to-boardthermalresistance 83.4 °C/W θJB ψ Junction-to-topcharacterizationparameter 6.7 °C/W JT ψ Junction-to-boardcharacterizationparameter 82 °C/W JB R Junction-to-case(bottom)thermalresistance — °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 4 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8320

ADS8320 www.ti.com SBAS108E–MAY2000–REVISEDDECEMBER2016 6.5 Electrical Characteristics: V = 5 V CC at–40°Cto85°C,V =5V,–IN=GND,f =100kHz,andf =24×f (unlessotherwisenoted) REF SAMPLE CLK SAMPLE PARAMETER TESTCONDITIONS MIN TYP MAX UNIT RESOLUTION Resolution 16 Bits ANALOGINPUT Full-scaleinputspan +In–(–In) 0 VREF V +In –0.1 V +0.1 CC Absoluteinput V –In –0.1 1 Capacitance 45 pF Leakagecurrent 1 nA SYSTEMPERFORMANCE ADS8320E 14 Nomissingcodes Bits ADS8320EB 15 ADS8320E ±0.008% ±0.018% Integrallinearityerror FSR ADS8320EB ±0.006% ±0.012% ADS8320E ±1 ±2 Offseterror mV ADS8320EB ±0.5 ±1 Offsettemperaturedrift ±3 µV/°C ADS8320E ±0.05% Gainerror FSR ADS8320EB ±0.024% Gainerrortemperaturedrift ±0.3 ppm/°C Noise 20 µVrms Power-supplyrejectionratio 4.7V<V <5.25V 3 LSB(1) CC SAMPLINGDYNAMICS Clock Conversiontime 16 Cycles Clock Acquisitiontime 4.5 Cycles Throughputrate 100 kHz Clockfrequency 0.024 2.4 MHz DYNAMICCHARACTERISTICS ADS8320E –84 Totalharmonicdistortion V =5V at10kHz dB IN P-P ADS8320EB –86 ADS8320E 82 SINAD V =5V at10kHz dB IN P-P ADS8320EB 84 ADS8320E 84 Spurious-freedynamic V =5V at10kHz dB IN P-P ADS8320EB 86 ADS8320E 90 SNR dB ADS8320EB 92 REFERENCEINPUT Voltage 0.5 V V CC CS=GND,f =0Hz 5 SAMPLE Resistance GΩ CS=V 5 CC 40 80 Currentdrain f =0Hz 0.8 µA SAMPLE CS=V 0.1 3 CC (1) LSBmeansLeastSignificantBitwithVREFequalto2.5V,oneLSBis0.038mV. Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:ADS8320

ADS8320 SBAS108E–MAY2000–REVISEDDECEMBER2016 www.ti.com Electrical Characteristics: V = 5 V (continued) CC at–40°Cto85°C,V =5V,–IN=GND,f =100kHz,andf =24×f (unlessotherwisenoted) REF SAMPLE CLK SAMPLE PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DIGITALINPUT/OUTPUT Logicfamily CMOS V I =5µA 3 V +0.3 IH IH CC V I =5µA –0.3 0.8 IL IL Logiclevels V V I =–250µA 4 OH OH V I =250µA 0.4 OL OL Dataformat StraightBinary POWERSUPPLYREQUIREMENTS V Specifiedperformance 4.75 5.25 V CC V (2) 2 5.25 V CC 900 1700 Quiescentcurrent µA f =10kHz(3)(4) 200 SAMPLE Powerdissipation 4.5 8.5 mW Powerdown CS=V 0.3 3 µA CC (2) SeeTypicalCharacteristicsformoreinformation. (3) f =2.4MHz,CS=V for216clockcyclesoutofevery240. CLK CC (4) SeePowerDissipationformoreinformationregardinglowersamplerates. 6.6 Electrical Characteristics: V = 2.7 V CC at–40°Cto85°C,V =5V,–IN=GND,f =100kHz,andf =24×f (unlessotherwisenoted) REF SAMPLE CLK SAMPLE PARAMETER TESTCONDITIONS MIN TYP MAX UNIT RESOLUTION Resolution 16 Bits ANALOGINPUT Full-scaleinputspan +In–(–In) 0 VREF V +In –0.1 V +0.1 CC Absoluteinput V –In –0.1 0.5 Capacitance 45 pF Leakagecurrent 1 nA SYSTEMPERFORMANCE ADS8320E 14 Nomissingcodes Bits ADS8320EB 15 ADS8320E ±0.008% ±0.018% Integrallinearityerror FSR ADS8320EB ±0.006% ±0.012% ADS8320E ±1 ±2 Offseterror mV ADS8320EB ±0.5 ±1 Offsettemperaturedrift ±3 µV/°C ADS8320E ±0.05% Gainerror FSR ADS8320EB ±0.024% Gainerrortemperaturedrift ±0.3 ppm/°C Noise 20 ppm/°C Power-supplyrejectionratio 2.7V<V <3.3V 3 LSB(1) CC (1) LSBmeansLeastSignificantBitwithVREFequalto2.5V,oneLSBis0.038mV. 6 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8320

ADS8320 www.ti.com SBAS108E–MAY2000–REVISEDDECEMBER2016 Electrical Characteristics: V = 2.7 V (continued) CC at–40°Cto85°C,V =5V,–IN=GND,f =100kHz,andf =24×f (unlessotherwisenoted) REF SAMPLE CLK SAMPLE PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SAMPLINGDYNAMICS Clock Conversiontime 16 Cycles Clock Acquisitiontime 4.5 Cycles Throughputrate 100 kHz Clockfrequency 0.024 2.4 MHz DYNAMICCHARACTERISTICS ADS8320E –86 Totalharmonicdistortion V =2.7V at1kHz dB IN P-P ADS8320EB –88 ADS8320E 84 SINAD V =2.7V at1kHz dB IN P-P ADS8320EB 86 ADS8320E 86 Spurious-freedynamic V =2.7V at1kHz dB IN P-P ADS8320EB 88 ADS8320E 88 SNR dB ADS8320EB 90 REFERENCEINPUT Voltage 0.5 V V CC CS=GND,f =0Hz 5 SAMPLE Resistance GΩ CS=V 5 CC 20 50 Currentdrain µA CS=V 0.1 3 CC DIGITALINPUT/OUTPUT LogicFamily CMOS V I =5µA 2 V +0.3 IH IH CC V I =5µA –0.3 0.8 IL IL Logiclevels V V I =–250µA 2.1 OH OH V I =250µA 0.4 OL OL Dataformat StraightBinary POWERSUPPLYREQUIREMENTS V Specifiedperformance 2.7 3.3 V CC 2 5.25 V (2) V CC See(3) 2 2.7 650 1300 Quiescentcurrent µA f =10kHz(4)(5) 100 SAMPLE Powerdissipation 1.8 3.8 mW Powerdown CS=V 0.3 3 µA CC (2) SeeTypicalCharacteristicsformoreinformation. (3) ThemaximumclockrateoftheADS8320islessthan2.4MHzinthispowersupplyrange. (4) f =2.4MHz,CS=V for216clockcyclesoutofevery240. CLK CC (5) SeePowerDissipationformoreinformationregardinglowersamplerates. Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:ADS8320

ADS8320 SBAS108E–MAY2000–REVISEDDECEMBER2016 www.ti.com 6.7 Typical Characteristics 2.0 3.0 1.0 2.0 0.0 B) B) LS–1.0 LS 1.0 y ( y ( arit–2.0 arit 0.0 e e n n Li–3.0 Li n n –1.0 o o egral N––45..00 N –2.0 nt I –6.0 –3.0 0000 4000 8000 C000 FFFF 0000 4000 8000 C000 FFFF H H H H H H H H H H Hex Code Hex Code Figure1.IntegralNon-Linearity(INL)vsCode(25°C) Figure2.DifferentialNon-LinearityErrorvsCode(25°C) 1200 600 1000 500 5V A) A) µ 800 n 400 ent ( 2.7V ent ( 5V urr 600 urr 300 C C y y ppl 400 ppl 200 u u S S 200 100 0 0 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 Temperature (°C) Temperature (°C) Figure3.SupplyCurrentvsTemperature Figure4.Power-DownSupplyCurrent Code(25°C) 1200 1000 1000 A) Current (µ 800 Rate (kHz) 100 scent 600 mple 10 e a ui S Q 400 200 1 1 2 3 4 5 1 2 3 4 5 V (V) V (V) CC CC Figure5.QuiescentCurrentvsV Figure6.MaximumSampleRatevsV CC CC 8 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8320

ADS8320 www.ti.com SBAS108E–MAY2000–REVISEDDECEMBER2016 Typical Characteristics (continued) 6 3 V = 5V 5 CC 2 B) 4 B) S S L 3 L 1 et ( C ( 5V Offs 2 +25 0 n 1 m 2.7V nge i 0 a fro (cid:237)1 Cha –1 Delt (cid:237)2 –2 –3 (cid:237)3 1 2 3 4 5 (cid:237)50 (cid:237)25 0 25 50 75 100 Reference Voltage (V) Temperature (°C) Figure7.ChangeInOffsetvsReferenceVoltage Figure8.ChangeInOffsetvsTemperature 5 6 V = 5V CC 4 4 e in Gain (LSB) 321 om 25°C (LSB) 20 5V Chang 0 Delta fr –2 –1 –4 2.7V –2 –6 1 2 3 4 5 –50 –25 0 25 50 75 100 Reference Voltage (V) Temperature (°C) Figure9.ChangeInGainErrorvsReferenceVoltage Figure10.ChangeInGainErrorvsTemperature 0 10 –20 9 VCC = 5V B) 8 –40 LS 7 B) e ( e (d –60 Nois 6 Amplitud ––18000 k-to-Peak 543 a Pe 2 –120 1 –140 0 0 10 20 30 40 50 0.1 1 10 Frequency (kHz) Reference Voltage (V) Figure11.FrequencySpectrum(8192PointFFT, Figure12.Peak-to-PeakNoisevsReferenceVoltage FIN=10.120kHz,–0.3dB) Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:ADS8320

ADS8320 SBAS108E–MAY2000–REVISEDDECEMBER2016 www.ti.com Typical Characteristics (continued) 100 0 Signal-to-Noise Ratio 90 –10 namic Rangese Ratio (dB) 876000 Spurious-Free Dynamic Range stortion (dB) –––234000 urious-Free Dyd Signal-to-Noi 54320000 al Harmonic Di ––––56780000 Span 10 Tot –90 0 –100 1 10 50 100 1 10 100 Frequency (kHz) Frequency (kHz) Figure13.Spurious-FreeDynamicRangeandSignal-to- Figure14.TotalHarmonicDistortionvsFrequency NoiseRatiovsFrequency 100 90 dB) 90 dB) 80 Distortion) ( 876000 Distortion) ( 7600 Noise + 4500 Noise + 50 Signal-to-( 321000 Signal-to-( 4300 0 20 1 10 50 100 –40 –35 –30 –25 –20 –15 –10 –5 0 Frequency (kHz) Input Level (dB) Figure15.Signal-to-(Noise+Distortion)vsFrequency Figure16.Signal-to-(Noise+Distortion)vsInputLevel 70 70 60 60 A) A) µ 50 µ nt ( nt ( 50 e e urr 40 urr 5V ce C 30 5V ce C 40 n n e e er er 30 ef 20 ef R 2.7V R 2.7V 20 10 0 10 0 20 40 60 80 100 –50 –25 0 25 50 75 100 Sample Rate (kHz) Temperature (°C) Figure17.ReferenceCurrentvsSampleRate Figure18.ReferenceCurrentvsTemperature 10 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8320

ADS8320 www.ti.com SBAS108E–MAY2000–REVISEDDECEMBER2016 7 Detailed Description 7.1 Overview The ADS8320 device is a classic successive approximation register (SAR) analog-to-digital (A/D) converter. The architecture is based on capacitive redistribution, which inherently includes a sample and hold function. The converter is fabricated on a 0.6µm CMOS process. The architecture and process allow the ADS8320 to acquire and convert an analog signal at up to 100,000 conversions per second while consuming less than 4.5 mW from +V . CC The ADS8320 requires an external reference, an external clock, and a single power source (V ). The external CC reference can be any voltage between 500 mV and V . The value of the reference voltage directly sets the CC rangeoftheanaloginput.ThereferenceinputcurrentdependsontheconversionrateoftheADS8320. The external clock can vary between 24 kHz (1-kHz throughput) and 2.4 MHz (100-kHz throughput). The duty cycleoftheclockisessentiallyunimportant,aslongastheminimumhighandlowtimesareatleast200ns (V = 2.7 V or greater). The minimum clock frequency is set by the leakage on the capacitors internal to the CC ADS8320. The analog input is provided to two input pins: +In and –In. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnectedfromanyinternalfunction. The digital result of the conversion is clocked out by the D input and is provided serially, most significant bit CLOCK first, on the D pin. The digital data that is provided on the D pin is for the conversion currently in OUT OUT progress—there is no pipeline delay. It is possible to continue to clock the ADS8320 after the conversion is complete and to obtain the serial data least significant bit first. See Device Functional Modes for more information. 7.1.1 TypicalConnectionDiagram Figure 19 shows a basic data acquisition system. The ADS8320 input range is 0 V to V , as the reference input CC is connected directly to the power supply. The 5-Ω resistor and 1-µF to 10-µF capacitor filter the microcontroller noise on the supply, as well as any high-frequency noise from the supply itself. The exact values must be picked suchthatthefilterprovidesadequaterejectionofthenoise. +2.7 V to +5.25 V 5 (cid:159) +1µF to 10 µF ADS8320 VREF VCC +1µF to 0.1µF 10 µF +In CS Microcontroller –In D OUT GND DCLOCK Copyright © 2016, Texas Instruments Incorporated Figure19. TypicalConnectionDiagramWithADS8320 Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:ADS8320

ADS8320 SBAS108E–MAY2000–REVISEDDECEMBER2016 www.ti.com 7.2 Functional Block Diagram SAR Control V REF D OUT +In CDAC Serial –In Interface DCLOCK CS/SHDN S/H Amp Comparator Copyright © 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 AnalogInput The+Inand–Ininputpinsallowforadifferentialinputsignal.Unlikesomeconvertersofthistype,the –Ininputis not resampled later in the conversion cycle. When the converter goes into the hold mode, the voltage difference between+Inand–Iniscapturedontheinternalcapacitorarray. The range of the –In input is limited to –0.1 V to 1 V (–0.1 V to 0.5 V when using a 2.7-V supply). Because of this, the differential input can be used to reject only small signals that are common to both inputs. Thus, the –In input is best used to sense a remote signal ground that may move slightly with respect to the local ground potential. The input current on the analog inputs depends on a number of factors: sample rate, input voltage, source impedance, and power-down mode. Essentially, the current into the ADS8320 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (45 pF) to a 16-bit settling level within 4.5 clock cycles. When the converter goes into the hold mode or while it is in the power down mode, theinputimpedanceisgreaterthan1GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the –In input must not drop below GND – 100 mV or exceed GND + 1 V. The +In input must always remain within the range of GND – 100 mV to V + 100 mV. Outside of these ranges, the converter linearity may not meet CC specifications.Tominimizenoise,lowbandwidthinputsignalswithlowpassfiltersmustbeused. 7.3.2 ReferenceInput The external reference sets the analog input range. The ADS8320 operates with a reference in the range of 500 mVtoV .Thereareseveralimportantimplicationsofthis. CC As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the Least Significant Bit (LSB) size and is equal to the reference voltage divided by 65,536. This means that any offset or gain error inherent in the A/D converter appears to increase, in terms of LSB size, asthereferencevoltageisreduced. The noise inherent in the converter also appears to increase with lower LSB size. With a 5-V reference, the internal noise of the converter typically contributes only 1.5-LSB peak-to-peak of potential error to the output code. When the external reference is 500 mV, the potential error contribution from the internal noise is 10 times larger (15 LSBs). The errors due to the internal noise are gaussian in nature and can be reduced by averaging consecutiveconversionresults. For more information regarding noise, see Figure 12. Note that the Effective Number of Bits (ENOB) figure is calculated based on the converter’s signal-to-(noise + distortion) ratio with a 1-kHz, 0-dB input signal. SINAD is relatedtoENOBasshowninEquation1. 12 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8320

ADS8320 www.ti.com SBAS108E–MAY2000–REVISEDDECEMBER2016 Feature Description (continued) SINAD=6.02×ENOB+1.76 (1) With lower reference voltages, extra care must be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is lower, the converter is also more sensitive to external sources of error such as nearby digital signals and electromagnetic interference. 7.3.3 Noise The noise floor of the ADS8320 itself is extremely low, as can be seen from Figure 20 and Figure 21, and is much lower than competing A/D converters. It was tested by applying a low-noise DC input and a 5-V reference totheADS8320andinitiating5000conversions.ThedigitaloutputoftheA/Dconvertervariesinoutputcodedue to the internal noise of the ADS8320. This is true for all 16-bit SAR-type A/D converters. Using a histogram to plot the output codes, the distribution must appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. The ±1σ, ±2σ, and ±3σ distributions represents the 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise can be calculated by dividing the number of codes measured by 6 and this yields the ±3σ distribution or 99.7% of all codes. Statistically, up to 3 codes could fall outside the distribution when executing 1000 conversions. The ADS8320, with < 3 output codes for the ±3σ distribution, yields a <±0.5-LSB transition noise. Remember, to achieve this low-noise performance, the peak-to-peak noise oftheinputsignalandreferencemustbe<50 µV. 2510 2490 4864 0 0 0 0 0 0 72 64 0 1 2 3 4 5 6 1 2 3 4 5 6 Code Code Figure20.Histogramof5000ConversionsofaDCInputat Figure21.Histogramof5000ConversionsofaDCInputat theCodeTransition theCodeCenter 7.3.4 Averaging The noise of the A/D converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise is reduced by a factor of 1/√n, where n is the number of averages. For example, averaging four conversion results reduces the transition noise by 1/2 to ±0.25 LSBs. Averaging must only be usedforinputsignalswithfrequenciesnearDC. For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a similarmannertoaveraging;foreverydecimationby2,thesignal-to-noiseratioimproves3dB. 7.4 Device Functional Modes 7.4.1 SignalLevels The digital inputs of the ADS8320 can accommodate logic levels up to 5.5 V regardless of the value of V . CC Thus,theADS8320canbepoweredat3Vandstillacceptinputsfromlogicpoweredat5V. The CMOS digital output (D ) swings 0 V to V . If V is 3 V and this output is connected to a 5-V CMOS OUT CC CC logic input, then that IC may require more supply current than normal and may have a slightly longer propagation delay. Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:ADS8320

ADS8320 SBAS108E–MAY2000–REVISEDDECEMBER2016 www.ti.com Device Functional Modes (continued) 7.4.2 SerialInterface The ADS8320 communicates with microprocessors and other digital systems through a synchronous 3-wire serialinterface,asshowninFigure3andTable1.TheD signalsynchronizesthedatatransferwitheachbit CLOCK being transmitted on the falling edge of D . Most receiving systems capture the bitstream on the rising edge CLOCK of D . However, if the minimum hold time for D is acceptable, the system can use the falling edge of CLOCK OUT D tocaptureeachbit. CLOCK A falling CS signal initiates the conversion and data transfer. The first 4.5 to 5.0 clock periods of the conversion cycle are used to sample the input signal. After the fifth falling D edge, D is enabled and outputs a LOW CLOCK OUT value for one clock period. For the next 16 D periods, D outputs the conversion result, most significant CLOCK OUT bit first. After the least significant bit (B0) has been output, subsequent clocks repeat the output data but in a leastsignificantbitfirstformat. After the most significant bit (B15) has been repeated, D tri-states. Subsequent clocks has no effect on the OUT converter.Anewconversionisinitiatedonlywhen CShasbeentakenHIGHandreturnedLOW. Table1.TimingSpecifications(V =2.7VandAbove, –40°Cto85°C) CC MIN TYP MAX UNIT Clock t Analoginputsampletime 4.5 5 SMPL Cycles Clock t Conversiontime 16 CONV Cycles t Throughputrate 100 kHz CYC t CSfallingtoD LOW 0 ns CSD CLOCK t CSfallingtoD rising 20 ns SUCS CLOCK t D fallingtocurrentD notvalid 5 15 ns hDO CLOCK OUT t D fallingtonextD notvalid 30 50 ns dDO CLOCK OUT t CSrisingtoD Tri-state 70 100 ns dis OUT t D fallingtoD 20 50 ns en CLOCK OUT t D falltime 5 25 ns f OUT t D risetime 7 25 ns r OUT 14 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8320

ADS8320 www.ti.com SBAS108E–MAY2000–REVISEDDECEMBER2016 7.4.3 DataFormat The output data from the ADS8320 is in straight binary format, as shown in Table 2. This table represents the idealoutputcodeforthegiveninputvoltageanddoesnotincludetheeffectsofoffset,gainerror,ornoise. Table2.IdealInputVoltages DESCRIPTION ANALOGVALUE Full-scalerange V REF Leastsignificantbit(LSB) V /65,536 REF Full-scale V –1LSB REF Midscale V /2 REF Midscale–1LSB V /2–1LSB REF Zero 0V Table3.IdealOutputCodes DIGITALOUTPUT STRAIGHTBINARY BINARYCODE HEXCODE 1111111111111111 FFF 1000000000000000 8000 0111111111111111 7FFF 0000000000000000 0000 Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:ADS8320

ADS8320 SBAS108E–MAY2000–REVISEDDECEMBER2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information To maximize the performance of data acquisition (DAQ) system based on a high-precision, successive approximation register (SAR), and analog-to-digital converter (ADC), the input driver and the reference driver circuits must be designed properly and must be optimized. This section introduces some application circuits designed using the ADS8320, and the detailed information for the some general principles designing these circuitscanbereferredtotherelateddocumentation. 8.2 Typical Applications 8.2.1 UniversalSensorIFSARBoosterPack BoosterPack interface J1 TIDA-00564 3.3 V U1 T REF5030 SPI CLK 3.3 V 3.3 V 3 V U3 U2 + Sensor 100 T interface 10M T LMP7716 J3 _ 1n ADS8320 1.57 V SPI CS SPI MISO J2 BoosterPack interface Figure22. BlockDiagramforUniversalSensorIFSARBoosterPack 16 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8320

ADS8320 www.ti.com SBAS108E–MAY2000–REVISEDDECEMBER2016 Typical Applications (continued) 8.2.1.1 DesignRequirements This TI Design is a universal sensor IF based on a successive approximation register (SAR) ADC built in a Booster Pack form factor to be easily connected to TI LaunchPad for development and testing. The analog front end (AFE) of the board has been designed for sensors with low output voltage range and high output impedance such as thermopiles, infrared (IR) thermometers, thermocouple amplifiers, pH electrode buffers, piezoelectric accelerometers,andmanyothers. ThisapplicationcircuitforADS8320isdesignedtoachievethekeyspecifications: • 16-bit100KHz • Low-inputreferrednoiseandlow-inputbias(100fA) • Idealchoiceforhigh-impedanceoutputsensors 8.2.1.2 DetailedDesignProcedure The ADS8320 was selected in this design because it best matches the design’s input requirements and high performance. The maximum throughput rate of the ADS8320 is 100 ksps, the resolution is equal to 16 bits, and the input range of the ADS8320 is equal to the reference voltage supplied to the converter. In this design, the reference voltage is equal to 3 V. The REF5030 features low noise, very low drift, and high initial accuracy for high-performance data converters. The output of the REF5030 is 3 V, which fixes the voltage range of the ADC andcanprovideastablereferencevoltagetomaintaintheaccuracy. Because the system is targeted for high-impedance output sensors, CMOS or JFET input amplifiers are preferable. The LMP7716 is a CMOS amplifier with low-input referred noise and low-input bias current, which make it an ideal choice for sensor interfaces such as thermopiles, IR thermometers, thermocouple amplifiers, and pH electrode buffers. To ensure the amplifier settles in enough time for the ADC to complete the signal acquisition. The gain bandwidth product of the amplifier is high enough to make sure that the input signal bandwidth is accounted for, and the amplifier is stable with the filter load. The amplifier has a fast slew rate to chargethefilterchangesandtoquicklyreacttochangesoftheinput. A low-pass filter must be placed between the input of the ADC and input amplifier. Choosing the capacitor and resistor values play an important role to have a good AFE design. CFLT serves two purposes. Firstly, this capacitor stores energy to charge the ADC internal sampling capacitor. Secondly, CFLT provides a place for the internal capacitor’s charge to go. Due to the storage capabilities of CFLT, this design guide sometimes refers to this capacitor as the flywheel capacitor. CFLT has this alternative name because, like a flywheel, it stores energy for the acquisition time of the ADC. Another name used to describe CFLT is charge reservoir. This TI design has a CFLT equal to 1 nF. This capacitor must be a high-quality capacitor with low voltage and frequency coefficients. The recommended capacitor type is C0G. As a check, make sure the filter capacitor value chosen is atleast20timestheinternalcapacitorvalueofADC.Inthiscase,thevalueismorethan20timesthesize. The external R | C in the low-pass filter must settle within the ADC acquisition time. As a rule of thumb, set FLT FLT theexternalR |C settlingtimeconstantabitfasterthanideal(forexample,60%)toallowamarginforerror FLT FLT of the op-amp load transient and the small signal settling time. TI design has an RFLT equal to 100 Ω. The detaileddiscussionandcalculationcanbefoundinUniversalSensorIFSARBoosterPack(TIDUAI7). Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:ADS8320

ADS8320 SBAS108E–MAY2000–REVISEDDECEMBER2016 www.ti.com Typical Applications (continued) 8.2.1.3 ApplicationCurves 8.2.1.3.1 StaticTest(DC) Figure23showstheerror,whichisthemeasuredoutputvoltageminustheidealoutputvoltage. 0.003 0.0025 0.002 0.0015 0.001 R O 0.0005 R R 0 E -0.0005 -0.001 -0.0015 -0.002 -0.0025 -15 -12 -9 -6 -3 0 3 6 9 12 15 Vin(V) Figure23. Error(MeasuredV MinusIdealV )vsInputVoltage OUT OUT 8.2.1.3.2 DynamicTest(AC) For the dynamic test, sine wave is applied at the input of the board with fixed amplitude equal to –1 dBFS and a varyingfrequencyof0.5kHz,1kHz,5kHz,and10kHz.Figure24 showsthetestresultfor0.5kHz. Figure24. FFTat500Hz(InputSignal –1dBFS) Forstep-by-stepdesignprocedure,circuitschematics,billofmaterials,printedcircuitboard(PCB)files, simulationresults,andtestresults,refertoTIPrecisionDesignTIDA-00564,UniversalSensorIFSARBooster PackReferenceDesign. 18 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8320

ADS8320 www.ti.com SBAS108E–MAY2000–REVISEDDECEMBER2016 8.2.2 WirelessMotorMonitor(WMM) Remote TMP103 CC2600 / monitoring Temperature 6LoPan (e.g. iPad) sensor I2C UART TPL5100 SPI MSP430 Nano timer Flash memory FR5969 Li-ion battery TPL0501 BQ25570 Potentiometer Piezo vibration sensor TPS22969 Load switch ADS8320 TPS7A7 16-bit ADC LDO Copyright © 2016, Texas Instruments Incorporated Figure25. SystemBlockDiagramforWirelessMotorMonitor(WMM) 8.2.2.1 DesignRequirements ThisapplicationcircuitforADS8320isdesignedtoachievethekeyspecifications: • 16-bit100KHz • 4-KFFTforvibrationspectral • Optimizedforultra-lowsleep-modecurrent:I <45-nA(typical;BQ-harvesterinsmartmode) Q 8.2.2.2 DetailedDesignProcedure This TI Design is inspired by the need to monitor the health of motors and machines to accurately predict and schedulemaintenance(orreplacement)whileminimizingcostanddowntimeduringindustrialproduction. This design uses a Piezo vibration sensor to monitor machine vibrations, and a 16-bit precision SAR ADC, ADS8320, is connected to the Piezo shock sensor signal chain for signal acquisition. Because Piezo sensors have high-impedance output nodes, so it’s important to carefully design the analog front-end (AFE) circuitry to reduce the noise and increase the sensitivity of the system, also drive ADS8320 and settle the signal properly duringtheacquisitiontime. Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:ADS8320

ADS8320 SBAS108E–MAY2000–REVISEDDECEMBER2016 www.ti.com 8.2.2.3 ApplicationCurves Whentestingthesystemwithaportablespeaker,thetestresultgraphwith4-KFFTisshowninFigure26. Figure26. AndroidScreenShotofFFTat600-HzExcitationWithPortableSpeaker When testing the system with a shaker calibrated with a accelerometer, the ADC is used and the AFE gain is set to 11, then configure the software to output 0.1-g of vibration at 500 KHz (or 1.5 KHz, and 2.5 KHz) as depicted inFigure27. 20 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8320

ADS8320 www.ti.com SBAS108E–MAY2000–REVISEDDECEMBER2016 Figure27. BLEReceivedFFTat500-Hz0.1-gExcitation(X2.4=Hertz) Forstep-by-stepdesignprocedure,circuitschematics,billofmaterials,printedcircuitboard(PCB)files, simulationresults,andtestresults,refertoTIPrecisionDesignTIDM-WLMOTORMONITOR,WirelessMotor MonitorReferenceDesign. Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:ADS8320

ADS8320 SBAS108E–MAY2000–REVISEDDECEMBER2016 www.ti.com 9 Power Supply Recommendations The ADS8320 is designed to operate using a simple power supply voltage from 2.0 V to 5.25 V, but the specifications are ensured over a 2.7-V to 5.25-V supply range. This supply must be well regulated and bypassed. A ceramic decoupling capacitor must be placed on the supply pin as close as possible to the ADS8320 package. In addition, a 1-µF to 10-µF capacitor and a 5-Ω or 10-Ω series resistor may be used to low- passfilteranoisysupply. 10 Layout 10.1 Layout Guidelines For optimum performance, care must be taken with the physical layout of the ADS8320 circuitry. This is particularly true if the reference voltage is low and/or the conversion rate is high. At a 100-kHz conversion rate, the ADS8320 makes a bit decision every 416 ns. That is, for each subsequent bit decision, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, andtheinputtothecomparatorsettledtoa16-bitlevelallwithinoneclockcycle. TIrecommendsfollowingtheselayoutguidelines: • Aprinted-circuitboard(PCB)withatleastfourlayerstokeepallcriticalcomponentsonthetoplayer. • Analog input signals and the reference input signals must be kept away from noise sources. Crossing digital lines with the analog signal path must be avoided. The analog input and the reference signals are routed on totheleftsideoftheboardandthedigitalconnectionsareroutedontherightsideofthedevice. • Due to the dynamic currents that occur during conversion and data transfer, the supply pin (+V ) must have CC a decoupling capacitor that keeps the supply voltage stable. A 1-µF ceramic decoupling capacitor is recommendedforthesupplypin. • A layout that interconnects the converter and accompanying capacitors with the low inductance path is critical for achieving optimal performance. Using 15-mil vias to interconnect components to a solid analog ground plane at the subsequent inner layer minimizes stray inductance. Avoid placing vias between the supply pin and the decoupling capacitor. Any inductance between the supply capacitor and the supply pin of the converter must be kept to less than 5 nH by placing the capacitor within 0.2 inches from the supply or input pinsoftheADS8320andbyusing20-miltraces. • DynamiccurrentsarealsopresentattheREFpinduringtheconversionphase.Therefore,gooddecouplingis critical to achieve optimal performance. The inductance between the reference capacitor and the REF pin must be kept to less than 2 nH by placing the capacitor within 0.1 inches from the REFIN pin and by using 20-miltraces. • Asingle10-µF,X7R-grade,0805-sizeceramiccapacitorwithatleasta10-Vratingforgoodperformanceover temperaturerange. • A small, 0.1-Ω to 0.47-Ω, 0603-size resistor placed in series with the reference capacitor keeps the overall impedancelowandconstant,especiallyatveryhighfrequencies. • Avoid using additional lower value capacitors because the interactions between multiple capacitors can affect theADCperformanceathighersamplingrates. • Place the RC filters immediately next to the input pins. Among surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic capacitorsprovidesthemoststableelectricalpropertiesovervoltage,frequency,andtemperaturechanges. • The GND pin on the ADS8320 must be placed on a clean ground plane. In many cases, this is the analog ground. 22 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8320

ADS8320 www.ti.com SBAS108E–MAY2000–REVISEDDECEMBER2016 10.2 Layout Example External VCC Reference GND 10µF 1µF 0.1~0.47(cid:13) REF V C GND C 47(cid:13) VREF +VCC +IN DCLOCK 47(cid:13) -IN DOUT 47(cid:13) GND /CS/SHDN GND GND Figure28. LayoutExample 10.3 Power Dissipation The architecture of the converter, the semiconductor fabrication process, and a careful design allow the ADS8320 to convert at up to a 100kHz rate while requiring very little power. Still, for the absolute lowest power dissipation,thereareseveralthingstokeepinmind. The power dissipation of the ADS8320 scales directly with conversion rate. Therefore, the first step to achieving thelowestpowerdissipationistofindthelowestconversionratethatsatisfiestherequirementsofthesystem. In addition, the ADS8320 is in power-down mode under two conditions: when the conversion is complete and whenever CS is HIGH (as shown in Figure 29). Ideally, each conversion must occur as quickly as possible, preferably at a 2.4-MHz clock rate. This way, the converter spends the longest possible time in the power-down mode. This is very important as the converter not only uses power on each D transition (as is typical for CLOCK digital CMOS components), but also uses some current for the analog circuitry, such as the comparator. The analogsectiondissipatespowercontinuously,untilthepower-downmodeisentered. ThefollowingtimingdiagramsandtestcircuitspertaintotheparametersinTable1. Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:ADS8320

ADS8320 SBAS108E–MAY2000–REVISEDDECEMBER2016 www.ti.com Power Dissipation (continued) Complete Cycle CS/SHDN t SUCS Power Down Sample Conversion DCLOCK t CSD Use positive clock edge for data transfer Hi-Z Hi-Z DOUT 0 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (MSB) (LSB) t t SMPL CONV Minimum22clockcyclesrequiredfor16-bitconversion.Shownare24clockcycles. IfCSremainsLOWattheendofconversion,anewdatastreamwithLSB-firstisshiftedoutagain. Figure29. ADS8320BasicTimingDiagrams 1.4V 3 N(cid:159) DOUT Test Point 100 pF C LOAD Copyright © 2016, Texas Instruments Incorporated Figure30. LoadCircuitfort ,t,andt dDO r f V D OH OUT V OL t t r f Figure31. VoltageWaveformsforD RiseandFallTimes,t,t OUT r f DCLOCK V IL t dDO V OH D OUT V OL t hDO Figure32. VoltageWaveformsforD DelayTimes,t OUT dDO 24 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8320

ADS8320 www.ti.com SBAS108E–MAY2000–REVISEDDECEMBER2016 Power Dissipation (continued) Test Point V CC 3 N(cid:159) t Waveform 2, t dis en D OUT t Waveform 1 100 pF dis C LOAD Copyright © 2016, Texas Instruments Incorporated Waveform1isforanoutputwithinternalconditionssuchthattheoutputisHIGHunlessdisabledbytheoutput control.(2)Waveform2isforanoutputwithinternalconditionssuchthattheoutputisLOWunlessdisabledbythe outputcontrol. Figure33. LoadCircuitfort ,t,andt Table1 dDO r f V CS/SHDN IH DOUT 90% Waveform 1 t dis DOUT 10% Waveform 2 Figure34. VoltageWaveformsfort dis CS/SHDN DCLOCK 1 4 5 DOUT V OL B11 t en Figure35. VoltageWaveformsfort en Figure 36 shows the current consumption of the ADS8320 versus sample rate. For this graph, the converter is clocked at 2.4 MHz regardless of the sample rate; CS is HIGH for the remaining sample period. Figure 37 also shows current consumption versus sample rate. However, in this case, the D period is 1/24th of the sample CLOCK period—CSisHIGHforoneD cycleoutofevery16. CLOCK Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:ADS8320

ADS8320 SBAS108E–MAY2000–REVISEDDECEMBER2016 www.ti.com Power Dissipation (continued) 1000 1000 T = 25°C A f = 2.4MHz CLK A) A) ent (µ 100 VCC= 5.0V VCC = 2.7V ent (µ 100 Curr VREF= 5.0V VREF= 2.5V Curr y y pl pl Sup 10 Sup 10 TA = 25°C V = 5.0V CC V = 5.0V REF f = 24 (cid:135)(cid:3)I CLK SAMPLE 1 1 0.1 1 10 100 0.1 1 10 100 Sample Rate (kHz) Sample Rate (kHz) Figure36.MaintainingfCLKattheHighestPossibleRate Figure37.ScalingfCLKReducesSupplyCurrentOnly AllowsSupplyCurrenttoDropLinearlyWithSampleRate SlightlyWithSampleRate There is an important distinction between the power-down mode that is entered after a conversion is complete andthefullpower-downmodewhichisenabledwhenCSisHIGH.CSLOWshutsdownonlytheanalogsection. The digital section is completely shut down only when CS is HIGH. Thus, if CS is left LOW at the end of a conversion and the converter is continually clocked, the power consumption is not as low as when CS is HIGH. Figure38showsmoreinformation. Power dissipation can also be reduced by lowering the power-supply voltage and the reference voltage. The ADS8320 operates over a V range of 2 V to 5.25 V. However, at voltages below 2.7 V, the converter does not CC run at a 100-kHz sample rate. See Typical Characteristics for more information regarding power supply voltage andmaximumsamplerate. 1000 T = 25°C A V = 5.0V 800 CC V = 5.0V REF A) f = 24 (cid:135)(cid:3)I nt (µ 600 CLK SAMPLE e urr 400 CS LOW (GND) C y pl up 200 S 0.0 CS HIGH (V ) 0.250 CC 0.00 0.1 1 10 100 Sample Rate (kHz) ShutdowncurrentwithCSLOWvarieswithsamplerate Figure38. ShutdownCurrentWith CSHIGHis50nA(Typically,RegardlessoftheClock) 10.3.1 ShortCycling AnotherwayofsavingpoweristousetheCSsignaltoshortcycletheconversion.BecausetheADS8320places the latest data bit on the D line as it is generated, the converter can easily be short cycled. This term means OUT that the conversion can be terminated at any time. For example, if only 14 bits of the conversion result are required,thentheconversioncanbeterminated(bypullingCSHIGH)afterthe14thbithasbeenclockedout. This technique can be used to lower the power dissipation (or to increase the conversion rate) in those applications where an analog signal is being monitored until some condition becomes true. For example, if the signal is outside a predetermined range, the full 16-bit conversion result may not be required. If so, the conversion can be terminated after the first n bits, where n might be as low as 3 or 4. This results in lower power dissipationinboththeconverterandtherestofthesystem,astheyspendmoretimeinthepower-downmode. 26 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8320

ADS8320 www.ti.com SBAS108E–MAY2000–REVISEDDECEMBER2016 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 RelatedDocumentation Forrelateddocumentationseethefollowing: • UniversalSensorIFSARBoosterPack(TIDUAI7) • TIPrecisionDesignTIDU032, CapacitiveLoadDriveSolutionusinganIsolationResistor(TIDU032) 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.4 Trademarks SPI,E2EaretrademarksofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:ADS8320

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS8320E/250 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A20 & no Sb/Br) ADS8320E/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A20 & no Sb/Br) ADS8320E/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A20 & no Sb/Br) ADS8320E/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A20 & no Sb/Br) ADS8320EB/250 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A20 & no Sb/Br) ADS8320EB/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A20 & no Sb/Br) ADS8320EB/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A20 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ADS8320 : NOTE: Qualified Version Definitions: Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS8320E/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8320E/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8320EB/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8320EB/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS8320E/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS8320E/2K5 VSSOP DGK 8 2500 350.0 350.0 43.0 ADS8320EB/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS8320EB/2K5 VSSOP DGK 8 2500 350.0 350.0 43.0 PackMaterials-Page2

None

None

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated