ADS831 ADS831 ¤ SBAS087A – MAY 2001 8-Bit, 80MHz Sampling TM ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION (cid:1) HIGH SNR: 49dB The ADS831 is a pipeline, CMOS Analog-to-Digital (A/D) con- (cid:1) INTERNAL OR EXTERNAL REFERENCE verter that operates from a single +5V power supply. This con- OPTION verter provides excellent performance with a single-ended input and can be operated with a differential input (cid:1) SINGLE-ENDED OR for added spurious performance. This high performance converter DIFFERENTIAL ANALOG INPUT includes an 8-bit quantizer, high bandwidth (cid:1) PROGRAMMABLE INPUT RANGE: track/hold, and a high accuracy internal reference. It also allows for 1Vp-p/2Vp-p the user to disable the internal reference and utilize external (cid:1) LOW POWER: 275mW references. This external reference option provides excellent gain and offset matching when used in multi-channel applications or in (cid:1) LOW DNL: 0.35LSB applications where DC full scale range adjustment is required. (cid:1) SINGLE +5V SUPPLY OPERATION The ADS831 employs digital error correction techniques to pro- (cid:1) SSOP-20 PACKAGE vide excellent differential linearity for demanding imaging appli- cations. Its low distortion and high SNR give the extra margin APPLICATIONS needed for medical imaging, communications, video, and test instrumentation. (cid:1) MEDICAL IMAGING The ADS831 is specified at a maximum sampling frequency of (cid:1) VIDEO DIGITIZING 80MHz and a single-ended input range of 1.5V to 3.5V. The (cid:1) COMPUTER SCANNERS ADS831 is available in an SSOP-20 package and is pin-for-pin compatible with the 8-bit, 60MHz ADS830. (cid:1) COMMUNICATIONS (cid:1) DISK-DRIVE CONTROL +V CLK VDRV S ADS831 Timing Circuitry VIN IN T/H Pip8e-Blinited CoErrrercotrion O3-uStptauttes D•••0 IN A/D Core Logic D7 (Opt) Internal Reference Int/Ext Optional External Reference Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 1998, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com

ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC +V .......................................................................................................+6V DISCHARGE SENSITIVITY S Analog Input.............................................................–0.3V to (+V + 0.3V) S Logic Input...............................................................–0.3V to (+V + 0.3V) S This integrated circuit can be damaged by ESD. Texas Instruments Case Temperature.........................................................................+100°C Junction Temperature....................................................................+150°C recommends that all integrated circuits be handled with Storage Temperature.....................................................................+150°C appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. DEMO BOARD ORDERING INFORMATION ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more PRODUCT DEMO BOARD susceptible to damage because very small parametric changes could ADS831 DEM-ADS831E cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER(1) RANGE MARKING NUMBER MEDIA ADS831E SSOP-20 (QSOP) 349 –40°C to +85°C ADS831E ADS831E Rails " " " " " ADS831E/1K Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “ADS831E/1K” will get a single 1000-piece Tape and Reel. ELECTRICAL CHARACTERISTICS At T = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 80MHz, and external reference, unless otherwise noted. A ADS831E PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 8 Guaranteed Bits SPECIFIED TEMPERATURE RANGE Ambient Air –40 to +85 °C ANALOG INPUT Standard Single-Ended Input Range 2Vp-p 1.5 3.5 V Optional Single-Ended Input Range 1Vp-p 2 3 V Common-Mode Voltage 2.5 V Optional Differential Input Range 2Vp-p 2 3 V Analog Input Bias Current 1 µA Input Impedance 1.25 || 5 MΩ || pF Track-Mode Input Bandwidth –3dBFS 300 MHz CONVERSION CHARACTERISTICS Sample Rate 10k 80M Samples/s Data Latency 4 Clk Cyc DYNAMIC CHARACTERISTICS Differential Linearity Error (largest code error) f = 1MHz ±0.25 ±1.0 LSB f = 10MHz ±0.35 LSB No Missing Codes Guaranteed Integral Nonlinearity Error, f = 1MHz ±0.5 ±2.0 LSBs Spurious Free Dynamic Range(1) f = 1MHz (–1dB input) 67 dBFS(2) f = 10MHz (–1dB input) 50 65 dBFS Two-Tone Intermodulation Distortion(3) f = 9.5MHz and 9.9MHz (–7dB each tone) –57 dBc Signal-to-Noise Ratio (SNR) Referred to Full Scale f = 1MHz 49 dB f = 10MHz 46 49 dB Signal-to-(Noise + Distortion) (SINAD) Referred to Full Scale f = 1MHz 48.5 dB f = 10MHz 44 48.5 dB Effective Number of Bits(4), f = 1MHz 7.8 Bits Output Noise Input Tied to Common-Mode 0.2 LSBs rms Aperture Delay Time 3 ns Aperture Jitter 1.2 ps rms Overvoltage Recovery Time 2 ns Full-Scale Step Acquisition Time 2.5 ns ADS831 2 SBAS087A

ELECTRICAL CHARACTERISTICS (Cont.) At T = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 80MHz, and external reference, unless otherwise noted. A ADS831E PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS Logic Family CMOS Compatible Convert Command Start Conversion Rising Edge of Convert Clock High Level Input Current(5) (V = 5V) 100 µA IN Low Level Input Current (V = 0V) 10 µA IN High Level Input Voltage +3.5 V Low Level Input Voltage +1.0 V Input Capacitance 5 pF DIGITAL OUTPUTS Logic Family CMOS/TTL Compatible Logic Coding Straight Offset Binary Low Output Voltage (I = 50µA) VDRV = 5V +0.1 V OL Low Output Voltage, (I = 1.6mA) +0.2 V OL High Output Voltage, (I = 50µA) +4.9 V OH High Output Voltage, (I = 0.5mA) +4.8 V OH Low Output Voltage, (I = 50µA) VDRV = 3V +0.1 V OL High Output Voltage, (I = 50µA) +2.8 V OH Output Capacitance 5 pF ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted) f = 2.5MHz S Zero Error (Referred to –FS) at 25°C –2.5 ±0.5 +2.5 %FS Zero Error Drift (Referred to –FS) ±53 ppm/°C Gain Error(6) at 25°C –2.5 ±0.5 +2.5 %FS Gain Error Drift(6) ±75 ppm/°C Power Supply Rejection of Gain ∆ V = ±5% 55 dB S Internal REFT Tolerance Deviation from Ideal 3.0V ±10 ±100 mV Internal REFB Tolerance Deviation from Ideal 2.0V ±10 ±100 mV External REFT Voltage Range REFB + 0.8 3.0 V – 1.25 V S External REFB Voltage Range 1.25 2.0 REFT – 0.8 V Reference Input Resistance REFT to REFB 800 Ω POWER SUPPLY REQUIREMENTS Supply Voltage: +V Operating +4.75 +5.0 +5.25 V S Supply Current: +I Operating 58 70 mA S Power Dissipation: VDRV = 5V External Reference 290 350 mW VDRV = 3V External Reference 275 mW VDRV = 5V Internal Reference 310 mW VDRV = 3V Internal Reference 285 mW Thermal Resistance, θ JA SSOP-20 115 °C/W NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full Scale. (3) Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (4) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (5) A 50kΩ pull-down resistor is inserted internally. (6) Excludes internal reference. ADS831 3 SBAS087A

PIN CONFIGURATION PIN DESCRIPTIONS PIN DESIGNATOR DESCRIPTION Top View SSOP 1 GND Ground 2 Bit 1 Data Bit 1 (D7) (MSB) GND 1 20 VDRV 3 Bit 2 Data Bit 2 (D6) 4 Bit 3 Data Bit 3 (D5) Bit 1 (MSB) 2 19 +VS 5 Bit 4 Data Bit 4 (D4) 6 Bit 5 Data Bit 5 (D3) Bit 2 3 18 GND 7 Bit 6 Data Bit 6 (D2) Bit 3 4 17 IN 8 Bit 7 Data Bit 7 (D1) 9 Bit 8 Data Bit 8 (D0) (LSB) Bit 4 5 16 IN ADS831 10 CLK Convert Clock Bit 5 6 15 CM 11 RSEL Input Range Select: HI = 2V; LO = 1V 12 INT/EXT Reference Select: HI = External; LO = Internal Bit 6 7 14 REFT 13 REFB Bottom Reference 14 REFT Top Reference Bit 7 8 13 REFB 15 CM Common-Mode Voltage Output 16 IN Complementary Input Bit 8 (LSB) 9 12 INT/EXT 17 IN Analog Input CLK 10 11 RSEL 18 GND Ground 19 +V +5V Supply S 20 VDRV Output Logic Driver Supply Voltage TIMING DIAGRAM N+1 N+2 N+4 Analog In N+3 N+7 N N+5 N+6 tD tCONV tL tH Clock 4 Clock Cycles t 2 Data Out N–4 N–3 N–2 N–1 N N+1 N+2 N+3 Data Invalid t 1 SYMBOL DESCRIPTION MIN TYP MAX UNITS t Convert Clock Period 12.5 100µs ns CONV t Clock Pulse Low 5.8 6.25 ns L t Clock Pulse High 5.8 6.25 ns H t Aperture Delay 3 ns D t Data Hold Time, C = 0pF 3.9 ns 1 L t New Data Delay Time, C = 15pF max 5.9 12 ns 2 L ADS831 4 SBAS087A

TYPICAL CHARACTERISTICS At T = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 80MHz, and external reference, unless otherwise noted. A SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 0 –10 fIN = 1MHz –10 fIN = 10MHz SNR = 49dBFS SNR = 49dBFS –20 SFDR = 68dBFS –20 SFDR = 67dBFS B) –30 B) –30 d d e ( –40 e ( –40 d d u u nit –50 nit –50 g g a a M –60 M –60 –70 –70 –80 –80 –90 –90 0 10 20 30 40 0 10 20 30 40 Frequency (MHz) Frequency (MHz) SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE (Single-Ended, 1Vp-p) 0 0 –10 SNfINR = = 2 409MdHBzFS –10 SNfINR = = 1 409MdHBzFS –20 SFDR = 66dBFS –20 SFDR = 66dBFS B) –30 B) –30 d d e ( –40 e ( –40 d d u u nit –50 nit –50 g g a a M –60 M –60 –70 –70 –80 –80 –90 –90 0 10 20 30 40 0 10 20 30 40 Frequency (MHz) Frequency (MHz) TWO-TONE INTERMODULATION DISTORTION DIFFERENTIAL LINEARITY ERROR 0 0.5 –10 ff1 == 99..59MMHHzz aatt ––77ddBBFFSS fIN = 10MHz 2 –20 IMD(3) = –57dBc R) 0.25 S –30 BF B) d –40 S nitude ( –50 DLE (L 0 ag –60 M –70 –0.25 –80 –90 –0.5 0 10 20 30 40 0 64 128 192 256 Frequency (MHz) Output Code ADS831 5 SBAS087A

TYPICAL CHARACTERISTICS (Cont.) At T = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 80MHz, and external reference, unless otherwise noted. A DIFFERENTIAL LINEARITY ERROR INTEGRAL LINEARITY ERROR 1.0 1.0 fIN = 20MHz fIN = 1MHz 0.5 0.5 0.25 B) B) S S E (L 0 E (L 0 L L D I –0.25 –0.5 –0.5 –1.0 –1.0 0 64 128 192 256 0 64 128 192 256 Output Code Output Code DYNAMIC PERFORMANCE vs INPUT FREQUENCY POWER DISSIPATION vs TEMPERATURE 80 350 VDRV = +5V 70 SFDR W) 330 S) m Internal Reference SNR (dBF 60 ssipation ( 310 DR, SNR er Di 290 External Reference F w S 50 o P 270 40 250 0.1 1 10 100 –50 –25 0 25 50 75 100 Input Frequency (MHz) Temperature (°C) OUTPUT NOISE HISTOGRAM (DC Input) 800k 600k s nt u 400k o C 200k 0 N–2 N–1 N N+1 N+2 Output Code ADS831 6 SBAS087A

APPLICATION INFORMATION individual application requirements and system structure. For example, communication applications often process a THEORY OF OPERATION band of frequencies that does not include DC, whereas in The ADS831 is a high-speed CMOS A/D converter which imaging applications, the previously restored DC level must employs a pipelined converter architecture consisting of 6 be maintained correctly up to the A/D converter. Features on internal stages. Each stage feeds its data into the digital error the ADS831, such as the input range select (RSEL pin) or correction logic ensuring excellent differential linearity and the option for an external reference, provide the needed no missing codes at the 8-bit level. The output data becomes flexibility to accommodate a wide range of applications. In valid on the rising clock edge (see Timing Diagram). The any case, the ADS831 should be configured such that the pipeline architecture results in a data latency of 4 clock application objectives are met while observing the headroom cycles. requirements of the driving amplifier in order to yield the best overall performance. The analog input of the ADS831 is a differential track and hold, as shown in Figure 1. The differential topology along with tightly matched capacitors produce a high level of ac INPUT CONFIGURATIONS performance while sampling at very high rates. AC-Coupled, Single-Supply Interface The ADS831 allows its analog inputs to be driven either Figure 2 shows the typical circuit for an ac-coupled analog single-ended or differentially. The typical configuration for input configuration of the ADS831 where all components the ADS831 is for the single-ended mode in which the input are powered from a single +5V supply. track and hold performs a single-ended to differential con- With the RSEL pin connected HIGH, the full scale input version of the analog input signal. range is set to 2Vp-p. In this configuration, the top and Both inputs (IN, IN) require external biasing using a com- bottom references (REFT, REFB) provide an output voltage mon-mode voltage that is typically at the mid-supply level of +3.0V and +2.0V, respectively. Two resistors ( 2 x 1kΩ) (+VS/2). are used to create a common-mode voltage (VCM) of ap- proximately +2.5V to bias the inputs of the driving ampli- The following application discussion focuses on the single- fier. Using the OPA681 on a single +5V supply, its ideal ended configuration. Typically, its implementation is easier common-mode point is +2.5V. This coincides with the to achieve and the rated specifications for the ADS831 are recommended common-mode input level for the ADS831 characterized using the single-ended mode of operation. thus, obviating the need for a coupling capacitor between the amplifier and the converter. Even though the OPA681 has an DRIVING THE ANALOG INPUT ac gain of +2, the dc gain is only +1 due to the blocking The ADS831 achieves excellent ac performance either in the capacitor at resistor R . G single-ended or differential mode of operation. The selection The addition of a small series resistor (R ) between the S for the optimum interface configuration will depend on the output of the op amp and the input of the ADS831 will be beneficial in almost all interface configurations. This will de-couple the op amp’s output from the capacitive load and Op Amp Bias V avoid gain peaking, which can result in increased noise. For CM best spurious and distortion performance, the resistor value should be kept below 75Ω. The series resistor in combina- φ1 φ1 tion with the 47pF capacitor establishes a passive low-pass C H filter limiting the bandwidth for the wideband noise thus C φ2 help improving the SNR performance. I IN φ1 φ2 φ1 OUT AC-Coupled, Dual Supply Interface The circuit provided in Figure 3 shows typical connections IN OUT φ1 for the analog input in case the selected amplifier operates C I on dual supplies. This might be necessary to take full C φ2 advantage of very low distortion operational amplifiers, like H φ1 φ1 the OPA642. The advantage is that the driving amplifier can be operated with a ground referenced bipolar signal swing. Input Clock (50%) Op Amp V This will keep the distortion performance at its lowest since CM Bias the signal range stays within the linear region of the op amp and sufficient headroom to the supply rails can be main- Internal Non-overlapping Clock tained. By capacitively coupling the single-ended signal to φ1 φ2 φ1 the input of the ADS831, its common-mode requirements can easily be satisfied with two resistors connected between the top and bottom reference. FIGURE 1. Simplified Circuit of Input Track and Hold with Timing Diagram. ADS831 7 SBAS087A

1kΩ +5V VCM = +2.5VDC 1kΩ +5V 0.1µF R REFB REFT RSEL +VS S +2.0V +3.0V V 39Ω IN OPA681 IN 47pF +V IN 0V R ADS831 F –V 402Ω IN CM IN R 402GΩ 0.1µF INT/EXT GND 0.1µF FIGURE 2. AC-Coupled Input Configuration for a 2Vp-p Full-Scale Range and a Common-Mode Voltage, V , at +2.5V CM Derived From the Internal Top (REFT) and Bottom Reference (REFB). The OPA680 can be used in place of the OPA681 if a voltage feedback amplifier is preferred. +5V 1kΩ +5V REFT RSEL +V R S V 24.9SΩ 0.1µF +3.0V IN OPA642 IN 47pF –5V ADS831 R 402FΩ 1kΩ CM IN RG 0.1µF REFB 402Ω +2.0V INT/EXT GND FIGURE 3. AC-Coupling the Dual Supply Amplifier OPA642 to the ADS831 for a 2Vp-p Full-Scale Input Range. For applications requiring the driving amplifier to provide a ately biased using the +2.5V common-mode voltage avail- signal amplification with a gain ≥ 5, consider using decom- able at the CM pin. One-half of the amplifier (OPA2681) pensated voltage feedback op amps, such as the OPA643, or buffers the REFB pin and drives the voltage divider R , R . 1 2 current feedback op amps OPA681 and OPA658. Because of the op amp’s noise gain of +2V/V, assuming R = R , the common-mode voltage (V ) has to be re- DC-Coupled with Level Shift F IN CM scaled to +1.25V, resulting in the correct DC level of +2.5V Several applications may require that the bandwidth of the for the signal input (IN). Any DC voltage differences signal path includes DC, in which case the signal has to be between the IN and IN inputs of the ADS831 effectively DC-coupled to the A/D converter. In order to accomplish produce an offset, which can be corrected for by adjusting this, the interface circuit has to provide a DC level shift to the resistor values of the divider, R and R . The selection the analog input signal. The circuit shown in Figure 4 1 2 criteria for a suitable op amp should include the supply employs a dual op amp, A1, to drive the input of the voltage, input bias current, output voltage swing, distortion, ADS831 and level shift the signal to be compatible with and noise specification. Note that in this example the overall the selected input range. With the RSEL pin tied to the signal phase is inverted. To re-establish the original signal supply and the INT/EXT pin to ground, the ADS831 is polarity, it is always possible to interchange the IN and IN configured for a 2Vp-p input range and uses the internal connections. references. The complementary input (IN) may be appropri- ADS831 8 SBAS087A

+5V R F 499Ω R 499INΩ R RSEL +VS S V 39Ω IN 1/2 OPA2681 IN 2Vp-p 47pF ADS831 NOTE: RF = RIN, G = –1 CM (+2.5V) IN 0.1µF +5V REFB REFT (+2.0V) (+3.0V) INT/EXT R 50Ω 3012Ω 0.1µF 1/2 VCM = +1.25V OPA2681 0.1µF R 1 499Ω R F 1kΩ FIGURE 4. DC-Coupled Interface Circuit with Dual Current-Feedback Amplifier OPA2681. The OPA2680 can be used in place of the OPA2681 if a voltage feedback amplifier is preferred. cuit. The component values of the R-C lowpass may be SINGLE ENDED-TO-DIFFERENTIAL CONFIGURATION optimized depending on the desired roll-off frequency. The (Transformer Coupled) resistor across the secondary side (R ) should be calculated If the application requires a signal conversion from a single- T using the equation R = n2 x R to match the source ended source to feed the ADS831 differentially, a RF trans- T G impedance (R ) for good power transfer and VSWR. former might be a good solution. The selected transformer G must have a center tap in order to apply the common-mode DC voltage necessary to bias the converter inputs. REFERENCE OPERATION AC grounding the center tap will generate the differential Figure 6 depicts the simplified model of the internal refer- signal swing across the secondary winding. Consider a step- ence circuit. The internal blocks are the bandgap voltage up transformer to take advantage of a signal amplification reference, the drivers for the top and bottom reference, and without the introduction of another noise source. Further- more, the reduced signal swing from the source may lead to RSEL +V INT/EXT S an improved distortion performance. The differential input configuration may provide a notice- ADS831 50kΩ 50kΩ able advantage of achieving good SFDR performance over a wide range of input frequencies. In this mode both inputs Bandgap Reference and Logic of the ADS831 see closely matched impedances, and the V REF differential signal swing is reduced to half of the swing required for single-ended drive. Figure 5 shows the sche- matic for the suggested transformer coupled interface cir- +1 +1 R G 0.1µF 1:n 22Ω V IN IN 47pF 400Ω 400Ω RT ADS831 22Ω REFT CM REFB IN CM RSEL INT/EXT 47pF +5V + 10µF 0.1µF Bypass Capacitors: 0.1µF || 2.2µF each FIGURE 6. Equivalent Reference Circuit with Recommended FIGURE 5. Transformer Coupled Input. Reference Bypassing. ADS831 9 SBAS087A

the resistive reference ladder. The bandgap reference circuit The common-mode voltage available at the CM pin may be includes logic functions that allow to set the analog input used as a bias voltage to provide the appropriate offset for swing of the ADS831 to either a 1Vp-p or 2Vp-p full-scale the driving circuitry. However, care must be taken not to range simply by tying the RSEL pin to a LOW or HIGH appreciably load this node, which is not buffered and has a potential, respectively. While operating the ADS831 in the high impedance. An alternative way of generating a com- external reference mode, the buffer amplifiers for REFT and mon-mode voltage is given in Figure 7. Here, two external REFB are disconnected from the reference ladder. precision resistors (1% tolerance or better) are located As shown, the ADS831 has internal 50kΩ pull-up resistors between the top and bottom reference pins. The common- mode voltage, CMV, will appear at the midpoint. at the Range Select pin (RSEL) and Reference Select pin (INT/EXT). Leaving those pins open configures the ADS831 for a 2Vp-p input range and external reference operation. EXTERNAL REFERENCE OPERATION Setting the ADS831 up for internal reference mode requires For even more design flexibility, the internal reference can to bring the INT/EXT pin LOW. be disabled and an external reference voltage be used. The The reference buffers can be utilized to supply up to 1mA utilization of an external reference may be considered for (sink and source) to external circuitry. To ensure proper applications requiring higher accuracy, improved tempera- operation with any reference configurations, it is necessary ture performance, or a wide adjustment range of the to provide solid bypassing at the reference pins in order to converter’s full-scale range. Especially in multichannel keep the clock feedthrough to a minimum (Figure 6). All applications, the use of a common external reference has the bypassing capacitors should be located as close to their benefit of obtaining better matching of the full-scale range respective pins as possible. between converters. The external references can vary as long as the value of the external top reference REFT stays within the range of EXT (V – 1.25V) and (REFB + 0.8V), and the external bottom S reference REFB stays within 1.25V and (REFT – 0.8V), EXT as shown in Figure 8. ADS831 REFT REFB The full-scale input signal range (FSR) of the ADS831 is +3.0V +2.0V determined by the voltage difference across the reference R1 R2 pins REFT and REFB (FSR = REFT – REFB), while the 1kΩ 1kΩ common-mode voltage is defined by CMV = (REFT + + + REFB)/2. In order to maintain good ac performance, it is 2.2µF 0.1µF 0.1µF 2.2µF CMV recommended that the typical common-mode voltage be +2.5V kept at +2.5V while setting the external reference voltages. It is possible, however, to deviate from this common-mode level without significantly impacting the performance. In FIGURE 7. Alternative Circuit to Generate Common-Mode particular, DC-coupled applications may benefit from a Voltage. lower CMV as it increases the signal headroom of the +5V A - Short for 1Vp-p Input Range B A B - Short for 2Vp-p Input Range (Default) +VS INT/EXT RSEL GND V IN IN ADS831 CMV IN REFT GND REFB External Top Reference External Bottom Reference REFT = REFB +0.8V to +3.75V REFB = REFT –0.8V to +1.25V FIGURE 8. Configuration Example for External Reference Operation. ADS831 10 SBAS087A

driving amplifier. The internal reference ladder has a nomi- Digital Output Driver (VDRV) nal impedance of 800Ω. Depending on the selected refer- The ADS831 features a dedicated supply pin for the output ence voltages, the required drive current will vary accord- logic drivers, VDRV, which is not internally connected to ingly and the external reference circuitry should be designed the other supply pins. Setting the voltage at VDRV to +5V to supply the maximum required current. or +3V the ADS831 produces corresponding logic levels and can directly interface to the selected logic family. The output stages are designed to supply sufficient current to DIGITAL INPUTS AND OUTPUTS drive a variety of logic families. However, it is recom- Clock Input Requirements mended to use the ADS831 with +3V logic supply. This will Clock jitter is critical to the SNR performance of high speed, lower the power dissipation in the output stages due to the high resolution Analog to Digital Converters. It leads to lower output swing and reduce current glitches on the supply aperture jitter (t ) which adds noise to the signal being line which may affect the ac performance of the converter. A converted. The ADS831 samples the input signal on the In some applications, it might be advantageous to decouple rising edge of the CLK input. Therefore, this edge should the VDRV pin with additional capacitors or a pi-filter. have the lowest possible jitter. The jitter noise contribution to total SNR is given by the following equation. If this value GROUNDING AND DECOUPLING is near your system requirements, input clock jitter must be Proper grounding and bypassing, short lead length, and the reduced. use of ground planes are particularly important for high 1 frequency designs. Multilayer PC boards are recommended Jitter SNR=20log rms signal to rms noise for best performance since they offer distinct advantages 2πƒ t IN A like minimizing ground impedance, separation of signal layers by ground layers, etc. The ADS831 should be treated Where: ƒIN is Input Signal Frequency as an analog component. Whenever possible, the supply pins tA is rms Clock Jitter should be powered by the analog supply. This will ensure the most consistent results since digital supply lines often Particularly in udersampling applications, special consider- carry high levels of noise which otherwise would be coupled ation should be given to clock jitter. The clock input should into the converter and degrade the achievable performance. All ground connections on the ADS831 are internally joined be treated as an analog input in order to achieve the highest together, obviating the design of split ground planes. The level of performance. Any overshoot or undershoot of the ground pins (1, 18) should directly connect to an analog clock signal may cause degradation of the performance. ground plane which covers the PC board area around the When digitizing at high sampling rates, the clock should converter. While designing the layout, it is important to keep have a 50% duty cycle (t = t ), along with fast rise and fall H L the analog signal traces separated from any digital lines to times of 2ns or less. prevent noise coupling onto the analog signal path. Because Digital Outputs of its high sampling rate, the ADS831 generates high fre- The output data format of the ADS831 is in positive Straight quency current transients and noise (clock feedthrough) that Offset Binary code, see Table I. This format can easily are fed back into the supply and reference lines. This converted into the Two’s Binary Complement code by requires that all supply and reference pins are sufficiently inverting the MSB. bypassed. Figure 9 shows the recommended decoupling scheme for the ADS831. In most cases, 0.1µF ceramic chip capacitors at each pin are adequate to keep the impedance SINGLE-ENDED INPUT (2Vp-p) STRAIGHT OFFSET BINARY (IN = CMV) (SOB) low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual supply pin. +FS (IN = +3.5V) 1111 1111 Therefore, they should be located as close to the supply pins +1/2 FS 1100 0000 +1LSB 1000 0001 as possible. In addition, a larger bipolar capacitor (1µF to Bipolar Zero (IN = 2.5V) 1000 0000 22µF) should be placed on the PC board in proximity of the –1LSB 0111 1111 converter circuit. –1/2 FS 0100 0000 –FS (IN = +1.5V) 0000 0000 TABLE I. Coding Table for the ADS831. ADS831 It is recommended to keep the capacitive loading on the data GND +V GND VDRV S lines as low as possible (≤ 15pF). Higher capacitive loading 1 19 18 20 will cause larger dynamic currents as the digital outputs are 0.1µF 0.1µF changing. Those high current surges can feed back to the analog portion of the ADS831 and affect the performance. If 10µF necessary, external buffers or latches close to the converter’s + output pins may be used to minimize the capacitive loading. They also provide the added benefit of isolating the ADS831 +5V +3/+5V from any digital noise activities on the bus coupling back high frequency noise. FIGURE 9. Recommended Bypassing for the Supply Pins. ADS831 11 SBAS087A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS831E ACTIVE SSOP DBQ 20 50 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS831E & no Sb/Br) ADS831E/2K5 ACTIVE SSOP DBQ 20 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS831E & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS831E/2K5 SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS831E/2K5 SSOP DBQ 20 2500 350.0 350.0 43.0 PackMaterials-Page2

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