(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12) (cid:13)(cid:8)(cid:14)(cid:3)(cid:15)(cid:3) (cid:16)(cid:17)(cid:18) (cid:15)(cid:17)(cid:18)(cid:19)(cid:20) (cid:3)(cid:1)(cid:20) (cid:1)(cid:21)(cid:1)(cid:16)(cid:17)(cid:22)(cid:8)(cid:11)(cid:17)(cid:8)(cid:2)(cid:10)(cid:22)(cid:10)(cid:11)(cid:1)(cid:16) (cid:23)(cid:17)(cid:21)(cid:24)(cid:19)(cid:20)(cid:11)(cid:19)(cid:20) FEATURES APPLICATIONS (cid:1) 4 MHz Sample Rate, 12-Bit Resolution (cid:1) Optical Networking (DWDM, MEMS Based (cid:1) Zero Latency Switching) (cid:1) Unipolar, Pseudo Differential Input, Range: (cid:1) Spectrum Analyzers − 0 V to 2.5 V (cid:1) High Speed Data Acquisition Systems (cid:1) High Speed Parallel Interface (cid:1) (cid:1) High Speed Close-Loop Systems 71 dB SNR and −88.5 dB THD at 1 MHz I/P (cid:1) (cid:1) Telecommunication Power Dissipation 95 mW at 4 MSPS (cid:1) Nap Mode (10 mW Power Dissipation) (cid:1) Ultra-Sound Detection (cid:1) Power Down (10 (cid:1)W) (cid:1) Internal Reference (cid:1) Internal Reference Buffer (cid:1) 48-Pin TQFP and QFN Packages DESCRIPTION The ADS7881 is a 12-bit 4-MSPS A-to-D converter with The −IN swing of ±200 mV is useful to compensate for 2.5-V internal reference. The device includes a capacitor ground voltage mismatch between the ADC and sensor based SAR A/D converter with inherent sample and hold. and also to cancel common-mode noise. With nap mode The device offers a 12-bit parallel interface with an enabled, the device operates at lower power when used at additional byte mode that provides easy interface with 8-bit lower conversion rates. The device is available in 48-pin processors. The device has a pseudo-differential input TQFP and QFN packages. stage. SAR BYTE Output Latches and +IN + CDAC 3-State _ −IN Drivers 12/8-Bit Parallel Comparator Data Output Bus REFIN CONVST CLOCK Conversion and BUSY Control Logic CS REFOUT 2.5 V RD Internal Reference PWD/RST A_PWD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:15)(cid:20)(cid:17)(cid:2)(cid:25)(cid:23)(cid:11)(cid:10)(cid:17)(cid:21) (cid:2)(cid:1)(cid:11)(cid:1) (cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"(cid:26)(cid:29)(cid:27) (cid:26)# $%(cid:30)(cid:30)&(cid:27)" !# (cid:29)(cid:28) ’%()(cid:26)$!"(cid:26)(cid:29)(cid:27) *!"&+ (cid:15)(cid:30)(cid:29)*%$"# Copyright  2003 − 2005, Texas Instruments Incorporated $(cid:29)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31) "(cid:29) #’&$(cid:26)(cid:28)(cid:26)$!"(cid:26)(cid:29)(cid:27)# ’&(cid:30) ",& "&(cid:30)(cid:31)# (cid:29)(cid:28) (cid:11)&-!# (cid:10)(cid:27)#"(cid:30)%(cid:31)&(cid:27)"# #"!(cid:27)*!(cid:30)* .!(cid:30)(cid:30)!(cid:27)"/+ (cid:15)(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION MAXIMUM MAXIMUM NO MISSING INTEGRAL DIFFERENTIAL CODES AT PACKAGE PACKAGE TEMPERATURE ORDERING TRANSPORT MODEL LINEARITY LINEARITY RESOLUTION TYPE DESIGNATOR RANGE INFORMATION MEDIA QUANTITY (LSB) (LSB) (BIT) Tape and reel ADS7881IPFBT 4488--PPiinn 250 ±±11 ±±11 1122 PPFFBB −−4400°°CC ttoo 8855°°CC TQFP Tape and reel ADS7881IPFBR 1000 AADDSS77888811 Tape and reel ADS7881IRGZT 4488--PPiinn 250 ±±11 ±±11 1122 RRGGZZ −−4400°°CC ttoo 8855°°CC QFN Tape and reel ADS7881IRGZR 2500 NOTE: For most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range(1) UNIT +IN to AGND −0.3 V to +VA + 0.1 V −IN to AGND −0.3 V to 0.5 V +VA to AGND −0.3 V to 7 V +VBD to BDGND −0.3 V to 7 V Digital input voltage to GND −0.3 V to (+VBD + 0.3 V) Digital output to GND −0.3 V to (+VBD + 0.3 V) Operating temperature range −40°C to 85°C Storage temperature range −65°C to 150°C Junction temperature (TJmax) 150°C Power dissipation (TJ Max–TA)/ θJA TTQQFFPP aanndd QQFFNN ppaacckkaaggeess θJA Thermal impedance 86°C/W Vapor phase (60 sec) 215°C LLeeaadd tteemmppeerraattuurree,, ssoollddeerriinngg Infrared (15 sec) 220°C (1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 SPECIFICATIONS TA = −40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V, Vref = 2.5 V, fsample = 4 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span(1) +IN – (−IN) 0 Vref V +IN −0.2 Vref + 0.2 AAbbssoolluuttee iinnppuutt rraannggee VV −IN −0.2 +0.2 Input capacitance 27 pF Input leakage current 500 pA SYSTEM PERFORMANCE Resolution 12 Bits No missing codes 12 Bits Integral linearity(2) −1 ±0.6 1 LSB(3) Differential linearity −1 ±0.6 1 LSB(3) Offset error(4) External reference −1.5 ±0.25 1.5 mV Gain error(4) External reference −2 ±0.75 2 mV With common mode input signal = 200 Common-mode rejection ratio 60 dB mVp−p at 1 MHz At FF0H output code, Power supply rejection 80 dB +VA = 4.75 V to 5.25 V , Vref = 2.50 V SAMPLING DYNAMICS +VDB = 5 V 185 200 nsec CCoonnvveerrssiioonn ttiimmee +VDB = 3 V 205 nsec +VDB = 5 V 50 65 nsec AAccqquuiissiittiioonn ttiimmee +VDB = 3 V 45 nsec Maximum throughput rate 4 MHz Aperture delay 2 nsec Aperture jitter 20 psec Step response 50 nsec Over voltage recovery 50 nsec DYNAMIC CHARACTERISTICS VIN = 2.496 Vp−p at 100 kHz/2.5 Vref −91 TToottaall hhaarrmmoonniicc ddiissttoorrttiioonn(((555))) VIN = 2.496 Vp−p at 1 MHz/2.5 Vref −88.5 −86 ddBB VIN = 2.496 Vp−p at 1.8 MHz/2.5 Vref 74 VIN = 2.496 Vp−p at 100 kHz/2.5 Vref 71.5 SSNNRR VIN = 2.496 Vp−p at 1 MHz/2.5 Vref 69 71 ddBB VIN = 2.496 Vp−p at 1.8 MHz/2.5 Vref 69.7 VIN = 2.496 Vp−p at 100 kHz/2.5 Vref 71.5 SSIINNAADD VIN = 2.496 Vp−p at 1 MHz/2.5 Vref 69 71 ddBB VIN = 2.496 Vp−p at 1.8 MHz/2.5 Vref 68.3 SFDR VIN = 2.496 Vp−p at 1 MHz/2.5 Vref 90 dB −3 dB Small signal bandwidth 50 MHz EXTERNAL REFERENCE INPUT Input VREF range 2.4 2.5 2.6 V Resistance(6) To internal reference voltage 500 kΩ 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 SPECIFICATIONS Continued TA = −40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V, Vref = 2.5 V, fsample = 4 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL REFERENCE OUTPUT From 95% (+VA), with 1-µF storage Start-up time 120 msec capacitor on REFOUT to AGND VREF Range IOUT=0 2.47 2.5 2.53 V Source current Static load 10 µA Line regulation +VA = 4.75 V to 5.25 V 1 mV Drift IOUT = 0 25 PPM/C DIGITAL INPUT/OUTPUT Logic family CMOS VIH IIH = 5 µA +VBD −1 +VBD + 0.3 V VIL IIL = 5 µA −0.3 0.8 V LLooggiicc lleevveell VOH IOH = 2 TTL loads +VBD − 0.6 +VBD V VOL IOL = 2 TTL loads 0 0.4 V Straight Data format Binary POWER SUPPLY REQUIREMENTS +VBD 2.7 3.3 5.25 V PPoowweerr ssuuppppllyy vvoollttaaggee +VA 4.75 5 5.25 V Supply current, +VA, 4 MHz sample rate 19 22 mA Power dissipation, 4 MHz sample rate +VA = 5 V 95 110 mW NAP MODE Supply current, +VA 2 3 mA Power-up time(7) 60 nsec POWER DOWN Supply current, +VA 2 2.5 µA Power down time(8) From simulation results 10 µsec 1-µF Storage capacitor on REFOUT to Power up time 25 msec AGND Invalid conversions after power up or reset 4 Numbers TEMPERATURE RANGE Operating free-air −40 85 °C (1)Ideal input span; does not include gain or offset error. (2)This is endpoint INL, not best fit. (3)LSB means least significant bit. (4)Measured relative to actual measured reference. (5)Calculated on the first nine harmonics of the input frequency. (6)Can vary ±20%. (7)Minimum acquisition time for first sampling after the end of nap state must be 60 nsec more than normal. (8)Time required to reach level of 2.5 µA. 4

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 TIMING REQUIREMENTS All specifications typical at −40°C to 85°C, +VA = +5 V, +VBD = +5 V (see Notes 1, 2, 3, and 4) PARAMETER SYMBOL MIN TYP MAX UNITS REF FIG. Conversion time t(conv) 185 200 ns 5 Acquisition time t(acq) 50 65 ns 5 SAMPLING AND CONVERSION START Hold time CS low to CONVST high (with BUSY high) th1 10 ns 3 Delay CONVST high to acquisition start td1 2 4 5 ns 1 Hold time, CONVST high to CS high with BUSY low th2 10 ns 1 Hold time, CONVST low to CS high th3 10 ns 1 Delay CONVST low to BUSY high td2 40 ns 1 CS width for acquisition or conversion to start tw3 20 ns 2 Delay CS low to acquisition start with CONVST high td3 2 4 5 ns 2 Pulse width, from CS low to CONVST low for acquisition to start tw1 20 ns 2 Delay CS low to BUSY high with CONVST low td4 40 ns 2 Quiet sampling time(3) 25 ns CONVERSION ABORT Setup time CONVST high to CS low with BUSY high ts1 15 ns 4 Delay time CS low to BUSY low with CONVST high td5 20 ns 4 DATA READ Delay RD low to data valid with CS low td6 25 ns 5 Delay BYTE high to LSB word valid with CS and RD low td7 25 ns 5 Delay time RD high to data 3-state with CS low td9 25 ns 5 Delay time end of conversion to BUSY low td11 20 ns 5 Quiet sampling time RD high to CONVST low t1 25 ns 5 Delay CS low to data valid with RD low td8 25 ns 6 Delay CS high to data 3-state with RD low td10 25 ns 6 Quiet sampling time CS low to CONVST low t2 25 ns 6 BACK-TO-BACK CONVERSION Delay BUSY low to data valid td12 10 ns 7, 8 Pulse width, CONVST high tw4 60 ns 7, 8 Pulse width, CONVST low tw5 20 ns 7 POWER DOWN/RESET Pulse width, low for PWD/RST to reset the device tw6 45 6140 ns 10 Pulse width, low for PWD/RST to power down the device tw7 7200 ns 9 Delay time, power up after PWD/RST is high td13 25 ms 9 (1)All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. (2)See timing diagram. (3)Quiet period before conversion start, no data bus activity including data bus 3-state is allowed in this period. (4)All timings are measured with 20 pF equivalent loads on all data bits and BUSY pin. 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 PIN ASSIGNMENTS PFB PACKAGE (TOP VIEW) T T S S RD EFM EFM VA GND GND VA S D ONV YTE WD/_PW R R + A A + C R C B PA 48 47 46 45 44 43 42 41 40 39 38 37 REFIN 1 36 BUSY REFOUT 2 35 BDGND NC 3 34 +VBD +VA 4 33 NC AGND 5 32 NC +IN 6 31 NC −IN 7 30 NC AGND 8 29 DB0 +VA 9 28 DB1 +VA 10 27 DB2 AGND 11 26 DB3 AGND 12 25 BDGND 13 14 15 16 17 18 19 20 21 22 23 24 A D D 1 0 9 8 7 6 5 4 D +V AGN AGN DB1 DB1 DB DB DB DB DB DB +VB NC − No connection RGZ PACKAGE (TOP VIEW) D D YND N SGB 0123G UDV CC C C BBBBD BB+ NN N N DDDDB 48 4746 4544 4342 4140 393837 A_PWD 1 36 +VBD PWD/RST 2 35 DB4 BYTE 3 34 DB5 CONVST 4 33 DB6 RD 5 32 DB7 CS 6 31 DB8 +VA 7 30 DB9 AGND 8 29 DB10 AGND 9 28 DB11 +VA 10 27 AGND REFM 11 26 AGND REFM 12 25 +VA 13 14 151617 18 1920 21 222324 N T CA D N N D A A DD EFI OU N+V GN +I −I GN +V +V GNGN R F A A AA E R NC − No internal connection NOTE: The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 6

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 TERMINAL FUNCTIONS NAME NO. PFB NO. RGZ I/O DESCRIPTION 8-Bit Bus 16-Bit Bus DDAATTAA BBUUSS BYTE = 0 BYTE = 1 BYTE = 0 DB11 16 28 O D11 (MSB) D3 D11 (MSB) DB10 17 29 O D10 D2 D10 DB9 18 30 O D9 D1 D9 DB8 19 31 O D8 D0 (LSB) D8 DB7 20 32 O D7 0 D7 DB6 21 33 O D6 0 D6 DB5 22 34 O D5 0 D5 DB4 23 35 O D4 0 D4 DB3 26 38 O D3 0 D3 DB2 27 39 O D2 0 D2 DB1 28 40 O D1 0 D1 DB0 29 41 O D0 (LSB) 0 D0 (LSB) CONTROL PINS CS 42 6 I Chip select. Active low signal enables chip operation like acquisition start, conver- sion start, bus release from 3-state. Refer to the timing diagrams for more details. CONVST 40 4 I Conversion start. The rising edge starts the acquisition. The falling edge of this input ends the acquisition and starts the conversion. Refer to the timing diagrams for more details. Active low synchronization pulse for the parallel output. When CS is low, this serves RD 41 5 I as the output enable and puts the previous conversion results on the bus. A_PWD 37 1 I Nap mode enable, active low PWD/RST 38 2 I Active low input, acts as device power down/device reset signal. BYTE 39 3 I Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Lower byte D[3:0] is folded back to high byte so D3 is available in D11 place. STATUS OUTPUT BUSY 36 48 O Status output. High when a conversion is in progress. POWER SUPPLY +VBD 24, 34 36, 46 − Digital power supply for all digital inputs and outputs. Refer to Table 3 for layout guidelines. BDGND 25, 35 37, 47 − Digital ground for all digital inputs and outputs. Short to analog ground plane below the device. 4, 9, 10, 13, 7, 10, 16, +VA − Analog power supplies. Refer to Table 3 for layout guidelines. 43, 46 21, 22, 25 AGND 5, 8, 11, 12, 8, 9, 17, − Analog ground pins. Short to analog ground plane below the device. 14, 15, 44, 45 20, 23, 24, 26, 27 ANALOG INPUT +IN 6 18 I Noninverting analog input channel −IN 7 19 I Inverting analog input channel REFIN 1 13 I Reference (positive) input. Needs to be decoupled with REFM pin using 0.1-µF by- pass capacitor and 1-µF storage capacitor. REFOUT 2 14 O Internal reference output. To be shorted to REFIN pin when internal reference is used. Do not connect to REFIN pin when external reference is used. Always needs to be decoupled with AGND using 0.1-µF bypass capacitor. REFM 47, 48 11, 12 I Reference ground. Connect to analog ground plane. NC 3, 30, 31, 32, 15, 42, 43, − No connection 33 44, 45 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 DESCRIPTION AND TIMING DIAGRAMS SAMPLING AND CONVERSION START There are three ways to start sampling. The rising edge of CONVST starts sampling with CS and BUSY being low (see Figure 1) or it can be started with the falling edge of CS when CONVST is high and BUSY is low (see Figure 2). Sampling can also be started with an internal conversion end (before BUSY falling edge) with CS being low and CONVST high before an internal conversion end (see Figure 3). Also refer to the section DEVICE OPERATION AND DATA READ IN BACK-TO-BACK CONVERSION for more details. A conversion can be started two ways (a conversion start is the end of sampling). Either with the falling edge of CONVST when CS is low (see Figure 1) or the falling edge of CS when CONVST is low (see Figure 2). A clean and low jitter falling edge of these respective signals triggers a conversion start and is important to the performance of the converter. The BUSY pin is brought high immediately following the CONVST falling edge. BUSY stays high throughout the conversion process and returns low when the conversion has ended. th2 th3 CS CONVST td1 td2 BUSY t(acq) Figure 1. Sampling and Conversion Start Control With CONVST Pin tw3 tw3 CS td4 CONVST td3 tw1 BUSY t(acq) Figure 2. Sampling and Conversion Start Control With CS Pin CS th1 tw5 CONVST tw4 BUSY td2 t(acq) Figure 3. Sampling Start With CS Low and CONVST High (Back-to-Back) 8

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 CONVERSION ABORT The falling edge of CS aborts the conversion while BUSY is high and CONVST is high (see Figure 4). The device outputs FE0 (hex) to indicate a conversion abort. td5 BUSY tsu1 CONVST CS RD D11−D0 1111 1110 0000 Figure 4. Conversion Abort DATA READ Two conditions need to be satisfied for a read operation. Data appears on the D11 through D0 pins (with D11 MSB) when both CS and RD are low. Figure 5 and Figure 6 illustrate the device read operation. The bus is three-stated if any one of the signals is high. td2 t1 tw5 CONVST t(conv) td1 + t(acq) BUSY td11 CS RD BYTE td6 td7 td9 D11−D0 D11−4 & D3−0 D3−0 Figure 5. Read Control Via CS and RD There are two output formats available. Twelve bit data appears on the bus during a read operation while BYTE is low. When BYTE is high, the lower byte (D3 through D0 followed by all zeroes) appears on the data bus with D3 in the MSB. This feature is useful for interfacing with eight bit microprocessors and microcontrollers. 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 t2 CONVST BUSY td1 + t(acq) Conversion No N td2 CS BYTE td7 td10 D11−D0 D11−4 & D3−0 D3−0 Data For Conv. N−1 Data For Conv. N td8 Figure 6. Read Control Via CS and RD Tied to BDGND DEVICE OPERATION AND DATA READ IN BACK-TO-BACK CONVERSION The following two figures illustrate device operation in back-to-back conversion mode. It is possible to operate the device at any throughput in this mode, but this is the only mode in which the device can be operated at throughputs exceeding 3.5 MSPS. A conversion starts on the CONVST falling edge. The BUSY output goes high after a delay (td2). Note that care must be taken not to abort the conversion (see Figure 4) apart from timing restrictions shown in Figure 7 and Figure 8. The conversion ends within the conversion time, t(conv), after the CONVST falling edge. The new acquisition can be immediately started without waiting for the BUSY signal to go low. This can be ensured with a CONVST high pulse width that is more than or equal to (t0 – t(conv) + 10 nsec) which is tw4 for a 4-MHz operation. Sample N CONVST tw4 tw5 t(acq) Conversion N BUSY td12 t(conv) + td11 D11−D0 Data For Conversion N−1 (Data read Without Latency) t0 = 250 ns for 4 MSPS Operation Figure 7. Back-To-Back Operation With CS and RD Low 10

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 CS th1 Sample N CONVST tw4 tw3 t(acq) t(conv) + td11 Conversion N BUSY td12 Data For Conversion N−1 D11−D0 (Data read Without Latency) t0 = 250 ns for 4 MSPS Operation Figure 8. Back-To-Back operation With CS Toggling and RD Low NAP MODE The device can be put in nap mode following the sequences shown in Figure 9. This provides substantial power saving while operating at lower sampling rates. While operating the device at throughput rates lower than 3.2 MSPS, A_PWD can be held low (see Figure 9). In this condition, the device goes into the nap state immediately after BUSY goes low and remains in that state until the next sampling starts. The minimum acquisition time is 60 nsec more than t as defined in the timing (acq) requirements section. Alternately, A_PWD can be toggled any time during operation (see Figure 10). This is useful when the system acquires data at the maximum conversion speed for some period of time (back-to-back conversion) and it does not acquire data for some time while the acquired data is being processed. During this period, the device can be put in the nap state to save power. The device remains in the nap state as long as A_PWD is low with BUSY being low and sampling has not started. The minimum acquisition time for the first sampling after the nap state is 60 nsec more than t as defined in the timing requirements section. (acq) A_PWD (Held Low) BUSY SAMPLE (Internal) t(acq) + 60 ns NAP (Internal Active High) NOTE: The SAMPLE (Internal) signal is generated as described in the Sampling and Conversion Start section. Figure 9. Device Operation While A_PWD is Held Low 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 A_PWD BUSY SAMPLE (Internal) t(acq) + 60 ns NAP (Internal Active High) NOTE: The SAMPLE (Internal) signal is generated as described in the Sampling and Conversion Start section. Figure 10. Device Operation While A_PWD is Toggling POWERDOWN/RESET A low level on the PWD/RST pin puts the device in the powerdown phase. This is an asynchronous signal. As shown in Figure 11, the device is in the reset phase for the first t period after a high-to-low transition of w6 PWD/RST. During this period the output code is FE0 (hex) to indicate that the device is in the reset phase. The device powers down if the PWD/RST pin continues to be low for a period of more than tw7. Data is not valid for the first four conversions after a power-up (see Figure 11) or an end of reset (see Figure 12). The device is initialized during the first four conversions. tw7 PWD/RST Valid Conversions First 4 Invalid Conversions BUSY 1 2 3 4 5 td13 D11−D0 1111 1110 0000 Power Down RESET Phase Phase Invalid Data Valid Data Figure 11. Device Power Down tw6 45 ns PWD/RST Valid Conversions First 4 Invalid Conversions BUSY 1 2 3 4 5 D11−D0 1111 1110 0000 RESET Phase Invalid Data Valid Data Figure 12. Device Reset 12

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 TYPICAL CHARACTERISTICS(1) EFFECTIVE NUMBER OF BITS HISTOGRAM vs (DC CODE SPREAD AT THE CENTER OF CODE) FREE-AIR TEMPERATURE 140000 12 +VA = 5 V, Count = 130879 s fi = 100 kHz, 120000 +CVoBdeD == 250 V4,8, − Bit 11.9 ++VVAB D= =5 5V ,V TA = 25(cid:1)C s 11.8 100000 Bit of 11.7 r 80000 be 11.6 nt m u u o N 11.5 C 60000 e v cti 11.4 e 40000 Eff 11.3 − B 11.2 20000 Count Count Count Count NO = 0 = 1 = 192 = 0 E 11.1 0 11 2046 2047 2048 2049 2050 −40 −20 0 20 40 60 80 Code TA − Free-Air Temperature − °C Figure 13 Figure 14 SIGNAL-TO-NOISE AND DISTORTION SIGNAL-TO-NOISE RATIO vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 72 72 fi = 100 kHz, fi = 100 kHz, B d +VA = 5 V, 71.9 +VA = 5 V, − +VBD = 5 V +VBD = 5 V n B rtio 71.8 − d 71.8 oise and Disto 71.6 o-Noise Ratio 777111...567 nal-to-N 71.4 Signal-t 71.4 g − 71.3 Si R − N D 71.2 S 71.2 A N SI 71.1 71 71 −40 −20 0 20 40 60 80 −40 −20 0 20 40 60 80 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 15 Figure 16 (1)At sample rate = 4 MSPS, Vref = 2.5 V external, unless otherwise specified. 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 SPURIOUS FREE DYNAMIC RANGE TOTAL HARMONIC DISTORTION vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 105 −85 B fi = 100 kHz, fi = 100 kHz, d +VA = 5 V, +VA = 5 V, e − +VBD = 5 V dB +VBD = 5 V ang 100 n − R o mic orti −90 a st n Di Dy c e 95 ni e o r m F s ar u H R − Spurio 90 HD − Total −95 D T F S 85 −100 −40 −20 0 20 40 60 80 −40 −20 0 20 40 60 80 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 17 Figure 18 EFFECTIVE NUMBER OF BITS SIGNAL-TO-NOISE AND DISTORTION vs vs INPUT FREQUENCY INPUT FREQUENCY 12 73 +VA = 5 V, s +VA = 5 V, s − Bit +TAVB =D 2 5=° 5C ,V, on − dB 72 +TAVB =D 2 5=° 5C ,V, Bit 11.5 orti 71 er of d Dist 70 b n m a Nu 11 ois 69 ve o-N cti al-t 68 e n − Eff 10.5 − Sig 67 B D O A N N 66 E SI 10 65 0 300 600 900 1200 1500 1800 0 300 600 900 1200 1500 1800 fi − Input Frequency − kHz fi − Input Frequency − kHz Figure 19 Figure 20 14

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 SIGNAL-TO-NOISE RATIO SPURIOUS FREE DYNAMIC RANGE vs vs INPUT FREQUENCY INPUT FREQUENCY 73 105 +VA = 5 V, +VA = 5 V, B B 72 +TAVB =D 2 5=° 5C ,V, e − d 100 +TAVB =D 2 5=° 5C ,V, o − d 71 Rang 95 Rati mic 90 e 70 a s n Noi Dy 85 o- 69 ee nal-t s Fr 80 g 68 u − Si urio 75 R 67 Sp SN R − 70 66 D F 65 S 65 60 0 300 600 900 1200 1500 1800 0 300 600 900 1200 1500 1800 fi − Input Frequency − kHz fi − Input Frequency − kHz Figure 21 Figure 22 TOTAL HARMONIC DISTORTION GAIN ERROR vs vs INPUT FREQUENCY SUPPLY VOLTAGE −60 0.9 +VBD = 5 V, +VA = 5 V, −65 +VBD = 5 V, TA = 25°C, dB TA = 25°C, − n −70 V 0.85 o m storti −75 or − Di rr onic −80 ain E 0.8 m G r − Ha −85 G al E ot − T −90 0.75 D H T −95 −100 0.7 0 300 600 900 1200 1500 1800 4.75 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 5.2 5.25 fi − Input Frequency − kHz +VA − Supply Voltage − V Figure 23 Figure 24 15

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 OFFSET ERROR GAIN ERROR vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 0.5 1.5 +VBD = 5 V, +VA = 5 V, TA = 25°C, +VBD = 5 V, 1.25 0.4 V V m m − 1 or − 0.3 rror r E Er n et Gai 0.75 Offs 0.2 − G − E 0.5 O E 0.1 0.25 0 0 4.75 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 5.2 5.25 −40 −20 0 20 40 60 80 +VA − Supply Voltage − V TA − Free-Air Temperature − °C Figure 25 Figure 26 OFFSET ERROR POWER DISSIPATION vs vs FREE-AIR TEMPERATURE SAMPLE RATE 1 100 +VA = 5 V, +VA = 5 V, 90 +VBD = 5 V, 0.75 +VBD = 5 V TA = 25°C, W 80 0.5 − m NAP Disabled V n 70 m o − 0.25 ati or sip 60 NAP Enabled − Offset ErrEO−0.205 − Power DisPD 345000 −0.5 20 −0.75 10 −1 0 −40 −20 0 20 40 60 80 0 500 1000 1500 2000 2500 3000 3500 4000 TA − Free-Air Temperature − °C Sample Rate − KSPS Figure 27 Figure 28 16

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 POWER DISSIPATION DIFFERENTIAL NONLINEARITY vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 97 1 +VA = 5 V, +VA = 5 V, +VBD = 5 V Bits 0.75 +VBD = 5 V Max W 96 − ation − m nearity 00.2.55 ssip 95 onli Di N Power 94 ential −0.205 − er PD Diff −0.5 Min − 93 L N D −0.75 92 −1 −40 −20 0 20 40 60 80 −40 −20 0 20 40 60 80 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 29 Figure 30 INTEGRAL NONLINEARITY INTERNAL REFERENCE OUTPUT vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 1 2.505 +VA = 5 V, +VA = 5 V, 0.75 +VBD = 5 V 2.5045 +VBD = 5 V − Bits 0.5 Max ut − V 2.504 rity Outp 2.5035 ea 0.25 e nlin renc 2.503 No 0 efe 2.5025 egral −0.25 ernal R 2.502 NL − Int −0.5 Min − Intref 22.5.500115 I V −0.75 2.5005 −1 2.5 −40 −20 0 20 40 60 80 −40 −20 0 20 40 60 80 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 31 Figure 32 17

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 INTERNAL REFERENCE OUTPUT vs SUPPLY VOLTAGE 2.505 +VBD = 5 V, 2.5045 TA = 25(cid:1)C V ut − 2.504 p ut 2.5035 O e nc 2.503 e r e ef 2.5025 R al 2.502 n r e nt 2.5015 − I ef 2.501 r V 2.5005 2.5 4.75 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 5.2 5.25 +VA − Supply Voltage − V Figure 33 DIFFERENTIAL NONLINEARITY 1 +VA = 5 V, 0.8 +VBD = 5 V, 0.6 TA = 25°C, 0.4 Sample Rate = 4 MSPS B S 0.2 L − 0 L N −0.2 D −0.4 −0.6 −0.8 −1 0 1028 2056 3084 4096 Code Figure 34 INTEGRAL NONLINEARITY 1 0.8 +VA = 5 V, 0.6 +VBD = 5 V, 0.4 TA = 25°C, 0.2 Sample Rate = 4 MSPS B S L 0 L − −0.2 FIGURE 36 N −0.4 I −0.6 −0.8 −1 0 1028 2056 3084 4096 Code Figure 35 18

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 FFT 20 0 +VA = 5 V, − dB −20 +TAVB =D 2 5=° 5C ,V, e −40 Sample Rate = 4 MSPS d u −60 mplit −80 A al −100 gn −120 FIGURE 37 Si −140 −160 0 0.4 0.8 1.2 1.6 2 f − Frequency − MHz Figure 36 19

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 PRINCIPLES OF OPERATION The ADS7881 is a member of a family of high-speed successive approximation register (SAR) analog-to-digital converters (ADC). The architecture is based on charge redistribution, which inherently includes a sample/hold function. The conversion clock is generated internally. The conversion time is 200 ns max (at 5 V +VBD). The analog input is provided to two input pins: +IN and −IN. (Note that this is pseudo differential input and there are restrictions on –IN voltage range.) When a conversion is initiated, the difference voltage between these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. REFERENCE The ADS7881 has a built-in 2.5-V (nominal value) reference but can operate with an external reference. When an internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with an 0.1-µF decoupling capacitor and a 1-µF storage capacitor between pin 2 (REFOUT) and pins 47, 48 (REFM). The internal reference of the converter is buffered . There is also a buffer from REFIN to CDAC. This buffer provides isolation between the external reference and the CDAC and also recharges the CDAC during conversion. It is essential to decouple REFOUT to AGND with a 0.1-µF capacitor while the device operates with an external reference. ANALOG INPUT When the converter enters hold mode, the voltage difference between the +IN and −IN inputs is captured on the internal capacitor array. The voltage on the −IN input is limited to between –0.2 V and 0.2 V, thus allowing the input to reject a small signal which is common to both the +IN and −IN inputs. The +IN input has a range of –0.2 V to (+V +0.2 V). The input span (+IN – (−IN)) is limited from 0 V to VREF. ref The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, signal frequency, and source impedance. Essentially, the current into the ADS7881 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current (this may not happen when a signal is moving continuously). The source of the analog input voltage must be able to charge the input capacitance (27 pF) to better than a 12-bit settling level with a step input within the acquisition time of the device. The step size can be selected equal to the maximum voltage difference between two consecutive samples at the maximum signal frequency. (Refer to Figure 39 for the suggested input circuit.) When the converter goes into hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, both −IN and +IN inputs should be within the limits specified. Outside of these ranges, the converter’s linearity may not meet specifications. Care should be taken to ensure that +IN and −IN see the same impedance to the respective sources. (For example, both +IN and −IN are connected to a decoupling capacitor through a 21-Ω resistor as shown in Figure 39.) If this is not observed, the two inputs could have different settling times. This may result in an offset error, gain error, or linearity error which changes with temperature and input voltage. DIGITAL INTERFACE TIMING AND CONTROL Refer to the SAMPLING AND CONVERSION START section and the CONVERSION ABORT section. READING DATA The ADS7881 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active when CS and RD are both low. There is a minimal quiet sampling period requirement around the falling edge of CONVST as stated in the timing requirements section. Data reads or bus three-state operations should not be attempted within this period. Any other combination of CS and RD three-states the parallel output. Refer to Table 1 for ideal output codes. 20

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 Table 1. Ideal Input Voltages and Output Codes(1) DESCRIPTION ANALOG VALUE BINARY CODE HEX CODE Full scale Vref − 1 LSB 1111 1111 1111 FFF Midscale Vref/2 1000 0000 0000 800 Midscale − 1 LSB Vref/2 − 1 LSB 0111 1111 1111 7FF Zero 0 V 0000 0000 0000 000 (1)Full-scale range = Vref and least significant bit (LSB) = Vref/4096 The output data appears as a full 12-bit word (D11−D0) on pins DB11 – DB0 (MSB−LSB) if BYTE is low. READING THE DATA IN BYTE MODE The result can also be read on an 8-bit bus for convenience by using pins DB11−DB4. In this case two reads are necessary; the first as before, leaving BYTE low and reading the 8 most significant bits on pins DB11−DB4, and then bringing BYTE high. When BYTE is high, the lower bits (D3−D0) followed by all zeros are on pins DB11 − DB4 (refer to Table 2). These multi-word read operations can be performed with multiple active RD signals (toggling) or with RD tied low for simplicity. Table 2. Conversion Data Read Out DATA READ OUT BBYYTTEE DB11 − DB4 DB3 − DB0 High D3 − D0, 0000 All zeroes Low D11 − D4 D3 − D0 Also refer to the DATA READ and DEVICE OPERATION AND DATA READ IN BACK-TO-BACK CONVERSION sections for more details. Reset Refer to the POWERDOWN/RESET section for the device reset sequence. It is recommended to reset the device after power on. A reset can be issued once the power has reached 95% of its final value. PWD/RST is an asynchronous active low input signal. A current conversion is aborted no later than 45 ns after the converter is in the reset mode. In addition, the device outputs a FE0 code to indicate a reset condition. The converter returns back to normal operation mode immediately after the PWD/RST input is brought high. Data is not valid for the first four conversions after a device reset. Powerdown Refer to the POWERDOWN/RESET section for the device powerdown sequence. The device enters powerdown mode if a PWD/RST low duration is extended for more than a period of t . w7 The converter goes back to normal operation mode no later than a period of t after the PWD/RST input is d13 brought high. After this period, normal conversion and sampling operation can be started as discussed in previous sections. Data is not valid for the first four conversions after a device reset. Nap Mode Refer to the NAP MODE section in the DESCRIPTION AND TIMING DIAGRAMS section for information. 21

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 APPLICATION INFORMATION LAYOUT For optimum performance, care should be taken with the physical layout of the ADS7881 circuitry. As the ADS7881 offers single-supply operation, it is often used in close proximity with digital logic, micro-controllers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve acceptable performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to the end of sampling (within quiet sampling time) and just prior to latching the output of the analog comparator during the conversion phase. Thus, driving any single conversion for an n-bit SAR converter, there are n+1 windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. On average, the ADS7881 draws very little current from an external reference as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and 1-µF storage capacitor are recommended from REFIN (pin 1) directly to REFM (pin 48). The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog ground. Avoid connections which are too close to the grounding point of a micro-controller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry. As with the AGND connections, +VA should be connected to a 5-V power supply plane that is separate from the connection for +VBD and digital logic until they are connected at the power entry point onto the PCB. Power to the ADS7881 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible. See Table 3 for the placement of capacitor. In addition to a 0.1-µF capacitor, a 1-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors, all designed to essentially low-pass filter the 5-V supply, removing the high frequency noise. Table 3. Power Supply Decoupling Capacitor Placement POWER SUPPLY PLANE CCOONNVVEERRTTEERR AANNAALLOOGG SSIIDDEE CCOONNVVEERRTTEERR DDIIGGIITTAALL SSIIDDEE SUPPLY PINS Pairs of pins that require a shortest path to decoupling (4,5), (9,8), (10,11), (13, 15), (43, 44) (46, 45) (24, 25), (34, 35) capacitors Pins that require no decoupling 14, 12 Analog 5 V +VA 1 µF 0.1 µF ADS7881 AGND AGND 0.1 µF REFOUT External REFIN Reference in 1 µF 0.1 µF AGND REFM 21 Ω +IN Analog Input Circuit 21 Ω −IN Figure 37. Using External Reference 22

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:6) www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 Analog 5 V +VA 1 µF 0.1 µF ADS7881 AGND AGND REFOUT REFIN 1 µF 0.1 µF AGND REFM 21 Ω +IN Analog Input Circuit 21 Ω −IN Figure 38. Using Internal Reference 130 pF 604 Ω Signal Input 604 Ω _ 12 Ω 21 Ω 2.5 V DC 3 kΩ 100 Ω THS4211 +IN + 150 pF 21 Ω ADS7881 −IN 1 kΩ 1 nF AGND AGND Figure 39. Typical Analog Input Circuit GPIO CS GPIO BYTE GPIO CONVST Microcontroller ADS7881 P[7:0] DB[11:4] RD RD INT BUSY Figure 40. Interfacing With Microcontroller 23

PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS7881IPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 ADS7881IPFBT TQFP PFB 48 250 180.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 ADS7881IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS7881IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS7881IPFBR TQFP PFB 48 1000 350.0 350.0 43.0 ADS7881IPFBT TQFP PFB 48 250 213.0 191.0 55.0 ADS7881IRGZR VQFN RGZ 48 2500 350.0 350.0 43.0 ADS7881IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 PackMaterials-Page2

GENERIC PACKAGE VIEW RGZ 48 VQFN - 1 mm max height 7 x 7, 0.5 mm pitch PLASTIC QUADFLAT PACK- NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224671/A www.ti.com

PACKAGE OUTLINE RGZ0048A VQFN - 1 mm max height PLASTIC QUADFLAT PACK- NO LEAD 7.1 A B 6.9 7.1 PIN 1 INDEX AREA 6.9 (0.1) TYP SIDE WALL DETAIL OPTIONAL METAL THICKNESS 1 MAX C SEATING PLANE 0.05 0.08 C 0.00 2X 5.5 5.15±0.1 (0.2) TYP 13 24 44X 0.5 12 25 SEE SIDE WALL DETAIL SYMM 2X 5.5 1 36 0.30 PIN1 ID 48X 0.18 (OPTIONAL) 48 37 SYMM 0.1 C A B 0.5 48X 0.3 0.05 C 4219044/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGZ0048A VQFN - 1 mm max height PLASTIC QUADFLAT PACK- NO LEAD 2X (6.8) ( 5.15) SYMM 48X (0.6) 48 35 48X (0.24) 44X (0.5) 1 34 SYMM 2X 2X (5.5) (6.8) 2X (1.26) 2X (1.065) (R0.05) TYP 23 12 21X (Ø0.2) VIA TYP 13 22 2X (1.26) 2X (1.065) 2X (5.5) LAND PATTERN EXAMPLE SCALE: 15X 0.07 MAX 0.07 MIN SOLDER MASK ALL AROUND ALL AROUND OPENING EXPOSED METAL EXPOSED METAL METAL SOLDER MASK METAL UNDER OPENING NON SOLDER MASK SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4219044/B 08/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGZ0048A VQFN - 1 mm max height PLASTIC QUADFLAT PACK- NO LEAD 2X (6.8) SYMM ( 1.06) 48X (0.6) 48X (0.24) 44X (0.5) SYMM 2X 2X (5.5) (6.8) 2X (0.63) 2X (1.26) (R0.05) TYP 2X 2X (0.63) (1.26) 2X (5.5) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 67% PRINTED COVERAGE BY AREA SCALE: 15X 4219044/B 08/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 M 0,17 36 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ Gage Plane 6,80 9,20 SQ 8,80 0,25 0,05 MIN 0°–7° 1,05 0,95 0,75 Seating Plane 0,45 0,08 1,20 MAX 4073176/B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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