ADS7865 www.ti.com SBAS441C–OCTOBER2008–REVISEDAPRIL2012 Dual, 12-Bit, 3+3 or 2+2 Channel, Simultaneous Sampling Analog-to-Digital Converter CheckforSamples:ADS7865 FEATURES DESCRIPTION 1 • SixPseudo-orFourFullyDifferentialInputs The ADS7865 is a dual, 12-bit, 2MSPS analog-to- 2 digitalconverter(ADC)withfourfullydifferentialorsix • SNR:71.7dB,THD:–87dB pseudo-differential input channels grouped into two • ProgrammableChannelSequencer pairs for high-speed, simultaneous signal acquisition. • ProgrammableandBufferedInternal2.5V Inputs to the sample-and-hold (S/H) amplifiers are Reference fully differential and are maintained differentially to the input of the ADC. This architecture provides • FlexiblePower-DownFeatures excellent common-mode rejection of 72dB at 100kHz, • VariablePower-SupplyRanges:2.7Vto5.5V which is a critical performance characteristic in noisy • Low-PowerOperation:44mWMaximumat5V environments. • OperatingTemperatureRange: The ADS7865 is pin-compatible with the ADS7862, –40°Cto+125°C but offers additional features such as a programmable channel sequencer and reference • Pin-CompatibleUpgradefortheADS7862 output, flexible supply voltage (2.7V to 5.5V for AV DD andBV ),apseudo-differentialinputmultiplexerwith APPLICATIONS DD three channels per ADC, and several power-down • MotorControl features. • Multi-AxisPositioningSystems The ADS7865 is offered in a TQFP-32 package. It is • Three-PhasePowerControl specified over the extended operating temperature rangeof–40°Cto+125°C. SAR BV AV DD DD CHA0+ CHA0- DB[11:0] Input S/H CDAC MUX CHA1+ e CHA1- Comparator nterfac CS el I CLOCK CHB0+ all CHB0- Par WR Input S/H CDAC MUX RD CHB1+ CHB1- Comparator BUSY CONVST REF IN BGND SAR REFOUT 10-Bit DAC 2.5V Reference AGND 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Alltrademarksarethepropertyoftheirrespectiveowners. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2008–2012,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

ADS7865 SBAS441C–OCTOBER2008–REVISEDAPRIL2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document,orvisitthedeviceproductfolderatwww.ti.com. ABSOLUTE MAXIMUM RATINGS(1) Overoperatingfree-airtemperaturerange,unlessotherwisenoted. ADS7865 UNIT Supplyvoltage,AVDDtoAGND –0.3to+6 V Supplyvoltage,BVDDtoBGND –0.3to+6 V Supplyvoltage,BVDDtoAVDD 1.5×AVDD V AnalogandreferenceinputvoltagewithrespecttoAGND AGND–0.3toAVDD+0.3 V DigitalinputvoltagewithrespecttoBGND BGND–0.3toBVDD+0.3 V Groundvoltagedifference|AGND–BGND| 0.3 V Inputcurrenttoallpinsexceptpower-supplypins –10to+10 mA Maximumvirtualjunctiontemperature,TJ +150 °C Humanbodymodel(HBM), ±4000 V JEDECstandard22,testmethodA114-C.01,allpins ESDratings Chargeddevicemodel(CDM), ±1500 V JEDECstandard22,testmethodC101,allpins (1) Stressesabovetheseratingsmaycausepermanentdamage.Exposuretoabsolutemaximumconditionsforextendedperiodsmay degradedevicereliability.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyond thosespecifiedisnotimplied. RECOMMENDED OPERATING CONDITIONS Overoperatingfree-airtemperaturerange,unlessotherwisenoted. ADS7865 PARAMETER MIN NOM MAX UNIT Supplyvoltage,AVDDtoAGND 2.7 5.0 5.5 V Lowvoltagelevels 2.7 3.6 V Supplyvoltage,BVDDtoBGND 5Vlogiclevels 4.5 5.0 5.5 V ReferenceinputvoltageonREFIN 0.5 2.5 2.525 V Analogdifferentialinputvoltage(CHXX+)–(CHXX–) –VREF +VREF V Operatingambienttemperaturerange,TA –40 +125 °C THERMAL CHARACTERISTICS(1) Overoperatingfree-airtemperaturerange,unlessotherwisenoted. PARAMETER ADS7865 UNIT θJA Junction-to-airthermalresistance High-Kthermalresistance 56.4 °C/W θJC Junction-to-casethermalresistance 20.8 °C/W PD DevicepowerdissipationatAVDD=5VandBVDD=3.3V 44 mW (1) TestedinaccordancewiththeHigh-KthermalmetricdefinitionsofEIA/JESD51-3forleadedsurface-mountpackageswitha3×3via array. 2 Copyright©2008–2012,TexasInstrumentsIncorporated

ADS7865 www.ti.com SBAS441C–OCTOBER2008–REVISEDAPRIL2012 ELECTRICAL CHARACTERISTICS AtT =–40°Cto+125°C;overentirepower-supplyvoltagerange,V =2.5V(internal),f =32MHz,andf =2MSPS, A REF CLK DATA unlessotherwisenoted. ADS7865 PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT RESOLUTION 12 Bits ANALOGINPUT FSR Full-scaledifferentialinputrange (CHxx+)–(CHxx–) –V +V V REF REF V Absoluteinputvoltage CHxx+orCHxx–toAGND –0.1 AV +0.1 V IN DD C Inputcapacitance CHxx+orCHxx–toAGND 2 pF IN C Differentialinputcapacitance 4 pF ID I Inputleakagecurrent –50 50 nA IL CMRR Common-moderejectionratio BothADCs,dcto100kHz 72 dB DCACCURACY –40°C<T <+125°C –1.25 ±0.6 +1.25 LSB A INL Integralnonlinearity –40°C<T <+85°C –1 ±0.5 +1 LSB A DNL Differentialnonlinearity –1 ±0.4 +1 LSB Inputoffseterror –3 ±0.5 +3 LSB V OS Match –3 ±0.5 +3 LSB dV /dT Inputoffsetthermaldrift ±2 μV/°C OS Gainerror –0.6 0.15 +0.6 % G ERR Match –0.6 ±0.1 +0.6 % G /dT Gainerrorthermaldrift ±2 ppm/°C ERR PSRR Power-supplyrejectionratio AV =5V 70 dB DD ACACCURACY SINAD Signal-to-noise+distortion V =5V at100kHz 69 71.3 dB IN PP SNR Signal-to-noiseratio V =5V at100kHz 70 71.7 dB IN PP THD Totalharmonicdistortion V =5V at100kHz –87 –74 dB IN PP SFDR Spurious-freedynamicrange V =5V at100kHz 74 88 dB IN PP SAMPLINGDYNAMICS t ConversiontimeperADC 1MHz<f ≤32MHz 13 Clocks CONV CLK t Acquisitiontime 62.5 ns ACQ f Datarate 1MHz<f ≤32MHz 62.5 2000 kSPS DATA CLK Aperturedelay 6 ns t A Match 50 ps t Aperturejitter 50 ps AJIT f ClockfrequencyonCLOCK 1 32 MHz CLK (1) AllvaluesatT =+25°C. A Copyright©2008–2012,TexasInstrumentsIncorporated 3

ADS7865 SBAS441C–OCTOBER2008–REVISEDAPRIL2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AtT =–40°Cto+125°C;overentirepower-supplyvoltagerange,V =2.5V(internal),f =32MHz,andf =2MSPS, A REF CLK DATA unlessotherwisenoted. ADS7865 PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT INTERNALVOLTAGEREFERENCE Resolution ReferenceoutputDACresolution 10 Bits Over20%to100%DACrange 0.496 2.515 V DAC=0x3FF, V Referenceoutputvoltage 2.485 2.500 2.515 V REFOUT –40°C<T <+125°C A DAC=0x3FFat+25°C 2.495 2.500 2.505 V dV /dT Referencevoltagedrift ±10 ppm/°C REFOUT DNL DACdifferentiallinearityerror –4 ±1 4 LSB DAC INL DACintegrallinearityerror –4 ±0.5 4 LSB DAC V DACoffseterror V =0.5V –4 ±1 4 LSB OSDAC REFOUT PSRR Power-supplyrejectionratio 73 dB I Referenceoutputdccurrent –2 +2 mA REFOUT Referenceoutputshort-circuit I 50 mA REFSC current t Referenceoutputsettlingtime 0.5 ms REFON VOLTAGEREFERENCEINPUT V Referenceinputvoltagerange 0.5 2.525 V REF I Referenceinputcurrent 50 μA REF C Referenceinputcapacitance 10 pF REF DIGITALINPUTS Logicfamily CMOS V High-levelinputvoltage 0.7×BV BV +0.3 V IH DD DD V Low-levelinputvoltage –0.3 0.3×BV V IL DD I Inputcurrent V =BV toBGND –50 +50 nA IN I DD C Inputcapacitance 5 pF I DIGITALOUTPUTS Logicfamily CMOS V High-leveloutputvoltage I =–100μA BV –0.2 V OH OH DD V Low-leveloutputvoltage I =100μA 0.2 V OL OH High-impedance-stateoutput I V =BV toBGND –50 +50 nA OZ current I DD C Outputcapacitance 5 pF O C Loadcapacitance 30 pF L 4 Copyright©2008–2012,TexasInstrumentsIncorporated

ADS7865 www.ti.com SBAS441C–OCTOBER2008–REVISEDAPRIL2012 ELECTRICAL CHARACTERISTICS (continued) AtT =–40°Cto+125°C;overentirepower-supplyvoltagerange,V =2.5V(internal),f =32MHz,andf =2MSPS, A REF CLK DATA unlessotherwisenoted. ADS7865 PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT POWERSUPPLY AV Analogsupplyvoltage AV toAGND 2.7 5.0 5.5 V DD DD BV BufferI/Osupplycurrent BV toBGND 2.7 3.0 5.5 V DD DD AV =2.7V 4.1 6.0 mA DD AV =5V 5.6 7.5 mA DD AV =2.7V,NAPpower-down 0.9 1.6 mA DD AI Analogsupplycurrent DD AV =5V,NAPpower-down 1.1 1.8 mA DD AV =2.7V,deeppower-down 0.001 mA DD AV =5V,deeppower-down 0.001 mA DD BV =2.7V,C =10pF 0.6 1.7 mA DD LOAD BI BufferI/Osupplycurrent DD BV =3.3V,C =10pF 0.8 1.9 mA DD LOAD AV =2.7V,BV =2.7V 12.7 21 mA DD DD P Powerdissipation D AV =5.0V,BV =3.0V 30.6 44 mW DD DD EQUIVALENT INPUT CIRCUIT R = 200W R = 50W SER SW CHXX+ C = 5pF C = 2pF PAR S C = 5pF C = 2pF PAR S CHXX- R = 200W R = 50W SER SW Copyright©2008–2012,TexasInstrumentsIncorporated 5

ADS7865 SBAS441C–OCTOBER2008–REVISEDAPRIL2012 www.ti.com DEVICE INFORMATION PBSPACKAGE TQFP-32 (TOPVIEW) + - + - - + - + 0 0 1 1 0 0 1 1 A A A A B B B B H H H H H H H H C C C C C C C C 32 31 30 29 28 27 26 25 REF 1 24 BV IN DD REFOUT 2 23 BGND AGND 3 22 WR AVDD 4 21 RD DB11 5 20 CS DB10 6 19 CLOCK DB9 7 18 CONVST DB8 8 17 BUSY 9 10 11 12 13 14 15 16 B7 B6 B5 B4 B3 B2 B1 B0 D D D D D D D D TERMINALFUNCTIONS PINNUMBER NAME DESCRIPTION 1 REF Referencevoltageinput.Aceramiccapacitorof470nF(min)isrequiredatthisterminal. IN 2 REF Referencevoltageoutput.Theprogrammableinternalvoltagereferenceoutputisavailableonthispin. OUT 3 AGND Analogground.Connecttoanaloggroundplane. 4 AV Analogpowersupply,2.7Vto5.5V.DecoupletoAGNDwitha1μFceramiccapacitor. DD 5 DB11 Databit11,MSB 6 DB10 Databit10 7 DB9 Databit9 8 DB8 Databit8 9 DB7 Databit7 10 DB6 Databit6 11 DB5 Databit5 12 DB4 Databit4 13 DB3 Databit3 14 DB2 Databit2 15 DB1 Databit1 16 DB0 Databit0 ADCbusyindicator.BUSYgoeshighwhentheinputsareinholdmodeandreturnstolowafterthe 17 BUSY conversionhasbeenfinished. Conversionstart.TheADCswitchesfromthesampleintotheholdmodeonthefallingedgeof 18 CONVST CONVST,independentofthestatusoftheCLOCK.Theconversionitselfstartswiththenextrising edgeofCLOCK. 19 CLOCK Externalclockinput. Chipselect.Whenlow,theparallelinterfaceofthedeviceisactive;whenhigh,inputsignalsare 20 CS ignoredandoutputsignalsare3-state. Readdata.Fallingedgeactivesynchronizationpulsefortheparalleldataoutputs.RDonlytriggers, 21 RD whenCSislow. 22 WR Writedata.Risingedgelatchesintheparalleldatainputs.WRonlytriggers,whenCSislow. 6 Copyright©2008–2012,TexasInstrumentsIncorporated

ADS7865 www.ti.com SBAS441C–OCTOBER2008–REVISEDAPRIL2012 TERMINALFUNCTIONS(continued) PINNUMBER NAME DESCRIPTION 23 BGND BufferI/Oground.Connecttodigitalgroundplane. 24 BV BufferI/Opowersupply,2.7Vto5.5V.DecoupletoBGNDwitha1μFceramiccapacitor. DD 25 CHB1+ NoninvertinganaloginputchannelB1 26 CHB1– InvertinganaloginputchannelB1 27 CHB0+ NoninvertinganaloginputchannelB0 28 CHB0– InvertinganaloginputchannelB0 29 CHA1– InvertinganaloginputchannelA1 30 CHA1+ NoninvertinganaloginputchannelA1 31 CHA0– InvertinganaloginputchannelA0 32 CHA0+ NoninvertinganaloginputchannelA0 TIMINGCHARACTERISTICS ConversionCycle tCONV 1 14 16 CLOCK tCLK t1 tCLKH tCLKL tACQ CONVST t2 t3 BUSY t4 t5 CS t6 t7 t8 t6 t7 WR t9 t14 RD t10 t12 t11 t13 DB[11:0] CHAx CHBx Input Output Output Data Previous ConversionResults Figure1. InterfaceTimingDiagram Copyright©2008–2012,TexasInstrumentsIncorporated 7

ADS7865 SBAS441C–OCTOBER2008–REVISEDAPRIL2012 www.ti.com TIMING REQUIREMENTS(1) ADS7865 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t Conversiontime f =32MHz 13 t CONV CLOCK CLK t Acquisitiontime 62.5 ns ACQ f CLOCKfrequency 1 32 MHz CLK t CLOCKperiod 31.25 1000 ns CLK t CLOCKlowtime 9.4 ns CLKL t CLOCKhightime 9.4 ns CLKH t CONVSTlowtime 20 ns 1 CONVSTfallingedgetoBUSYhigh t2 delay(2) 3 ns t CONVSThightime 20 ns 3 t RDfallingedgetoBUSYhighsetuptime 1 t 4 CLK t 14thCLOCKrisingedgetoBUSYlowdelay 3 ns 5 SeeFigure1 CSfallingedgetoRDorWRfallingedge t 0 ns 6 setuptime CSrisingedgetoRDorWRrisingedge t 0 ns 7 holdtime t WRlowtime 10 ns 8 t RDhightimebetweentworeadaccesses 10 ns 9 t RDfallingedgetooutputdatavaliddelay 20 ns 10 t Outputdataholdtime 5 ns 11 t Inputdatasetuptime 10 ns 12 t Inputdataholdtime 5 ns 13 InputdatastillvalidtoCONVSTfallingedge t 31.25 ns 14 setuptime (1) Allinputsignalsarespecifiedwitht =t =1.5ns(10%to90%ofBV )andtimedfromavoltagelevelof(V +V )/2. R F DD IL IH (2) Notapplicableinauto-Nappower-downmode. CLOCK Cycle1 Cycle2 10ns 10ns 5ns 5ns CONVST A B C NOTE:AllCONVSTcommandsthatoccurmorethan10nsbeforetherisingedgeofcycle'1'oftheexternalclock(Region'A')initiatea conversionontherisingedgeofcycle'1'.AllCONVSTcommandsthatoccur5nsaftertherisingedgeofcycle'1'or10nsbeforetherising edgeofcycle'2'(Region'B')initiateaconversionontherisingedgeofcycle'2'.AllCONVSTcommandsthatoccur5nsaftertherisingedge ofcycle'2'(Region'C')initiateaconversionontherisingedgeofthenextclockperiod. TheCONVSTpinshouldneverbeswitchedfromLOWtoHIGHintheregion10nsbeforetherisingedgeoftheCLOCKand5nsafterthe risingedge(grayareas).IfCONVSTistoggledinthisgrayarea,theconversioncouldbeginoneitherthesamerisingedgeoftheCLOCKor thefollowingedge. Figure2. CONVSTTiming 8 Copyright©2008–2012,TexasInstrumentsIncorporated

ADS7865 www.ti.com SBAS441C–OCTOBER2008–REVISEDAPRIL2012 TYPICAL CHARACTERISTICS Overtheentiresupplyvoltagerange;V =2.5V(internal),f =32MHz,andf =2MSPS,unlessotherwisenoted. REF CLK DATA INTEGRALNONLINEARITYvs INTEGRALNONLINEARITYvs DATARATE TEMPERATURE 1.00 1.00 0.75 0.75 0.50 0.50 Positive Positive B) 0.25 B) 0.25 S S L (L 0 L (L 0 IN -0.25 IN -0.25 Negative Negative -0.50 -0.50 -0.75 -0.75 -1.00 -1.00 0.50 0.75 1.00 1.25 1.50 1.75 2.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Data Rate (MSPS) Figure3. Figure4. INTEGRALNONLINEARITYvsCODE DIFFERENTIALNONLINEARITYvsCODE 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 B) 0.2 B) 0.2 S S INL (L -0.02 DNL (L -0.02 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 Code Code Figure5. Figure6. DIFFERENTIALNONLINEARITYvs DIFFERENTIALNONLINEARITYvs DATARATE TEMPERATURE 1.00 1.00 0.75 0.75 0.50 0.50 Positive B) 0.25 B) 0.25 S Positive S L (L 0 L (L 0 N N D -0.25 D -0.25 Negative Negative -0.50 -0.50 -0.75 -0.75 -1.00 -1.00 0.50 0.75 1.00 1.25 1.50 1.75 2.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 Data Rate (MSPS) Temperature (°C) Figure7. Figure8. Copyright©2008–2012,TexasInstrumentsIncorporated 9

ADS7865 SBAS441C–OCTOBER2008–REVISEDAPRIL2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Overtheentiresupplyvoltagerange;V =2.5V(internal),f =32MHz,andf =2MSPS,unlessotherwisenoted. REF CLK DATA OFFSETERRORANDOFFSETMATCHvs OFFSETERRORANDOFFSETMATCHvs ANALOGSUPPLYVOLTAGE TEMPERATURE 1.0 2.0 B) 0.8 B) S OffsetMatch S 1.5 L L ch ( 0.6 ch ( 1.0 Mat 0.4 Offset Error Mat Offset Match et 0.2 et 0.5 s s Offset Error Off 0 Off 0 and -0.2 and -0.5 or -0.4 or Err Err -1.0 et -0.6 et Offs -0.8 Offs -1.5 -1.0 -2.0 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 -40 -25 -10 5 20 35 50 65 80 95 110 125 AV (V) Temperature (°C) DD Figure9. Figure10. GAINERRORANDGAINMATCHvs GAINERRORANDGAINMATCHvs ANALOGSUPPLYVOLTAGE TEMPERATURE 0.5 0.20 Gain Error %) 0.4 %) 0.15 ch ( 0.3 ch ( 0.10 Mat 0.2 Gain Error Mat Gain Match n 0.1 n 0.05 ai ai d G 0 Gain Match d G 0 n n or a -0.1 or a -0.05 ain Err --00..23 ain Err -0.10 G -0.4 G -0.15 -0.5 -0.20 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 -40 -25 -10 5 20 35 50 65 80 95 110 125 AV (V) Temperature (°C) DD Figure11. Figure12. COMMON-MODEREJECTIONRATIOvs COMMON-MODEREJECTIONRATIOvs ANALOGSUPPLYVOLTAGE TEMPERATURE 74.0 74.0 73.5 73.5 73.0 73.0 B) 72.5 B) 72.5 d d R ( 72.0 R ( 72.0 R R M M C 71.5 C 71.5 71.0 71.0 70.5 70.5 70.0 70.0 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 -40 -25 -10 5 20 35 50 65 80 95 110 125 AV (V) Temperature (°C) DD Figure13. Figure14. 10 Copyright©2008–2012,TexasInstrumentsIncorporated

ADS7865 www.ti.com SBAS441C–OCTOBER2008–REVISEDAPRIL2012 TYPICAL CHARACTERISTICS (continued) Overtheentiresupplyvoltagerange;V =2.5V(internal),f =32MHz,andf =2MSPS,unlessotherwisenoted. REF CLK DATA FREQUENCYSPECTRUM FREQUENCYSPECTRUM (4096PointFFT;f =100kHz) (4096PointFFT;f =100kHz,f =1.5MSPS) IN IN SAMPLE 0 0 -20 -20 -40 -40 B) B) d d e ( -60 e ( -60 d d u u plit -80 plit -80 m m A A -100 -100 -120 -120 -140 -140 0 200k 400k 600k 800k 1M 0 100 200 300 400 500 600 700 750 Frequency (Hz) Frequency (kHz) Figure15. Figure16. SIGNAL-TO-NOISERATIOANDDISTORTION SIGNAL-TO-RATIOANDDISTORTION vsINPUTSIGNALFREQUENCY vsTEMPERATURE 74 73.0 72.5 73 72.0 72 B) B) 71.5 D (d 71 D (d 71.0 AVDD= 5V A AV = 5V A N DD N SI SI 70.5 70 AV = 2.7V DD AV = 2.7V 70.0 DD 69 69.5 68 69.0 10 30 40 70 90 110 130 150 170 190 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 f (kHz) Temperature (°C) IN Figure17. Figure18. SIGNAL-TO-NOISERATIO SIGNAL-TO-NOISERATIO vsINPUTSIGNALFREQUENCY vsTEMPERATURE 74 73.0 73 72.5 72 72.0 R (dB) 71 AVDD= 5V R (dB) 71.5 AVDD= 5V SN SN AVDD= 2.7V 70 71.0 AV = 2.7V DD 69 70.5 68 70.0 10 30 50 70 90 110 130 150 170 190 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 f (kHz) Temperature (°C) IN Figure19. Figure20. Copyright©2008–2012,TexasInstrumentsIncorporated 11

ADS7865 SBAS441C–OCTOBER2008–REVISEDAPRIL2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Overtheentiresupplyvoltagerange;V =2.5V(internal),f =32MHz,andf =2MSPS,unlessotherwisenoted. REF CLK DATA TOTALHARMONICDISTORTION TOTALHARMONICDISTORTION vsINPUTSIGNALFREQUENCY vsTEMPERATURE -76 -78 -78 -80 -80 -82 -82 B) AV = 5V B) d DD d D ( -84 D ( -84 H H T -86 T AVDD= 5V AV = 2.7V -86 DD -88 -88 -90 AV = 2.7V DD -92 -90 10 30 40 70 90 110 130 150 170 190 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 f (kHz) Temperature (°C) IN Figure21. Figure22. SPURIOUS-FREEDYNAMICRANGE SPURIOUS-FREEDYNAMICRANGE vsINPUTSIGNALFREQUENCY vsTEMPERATURE 94 92 92 AVDD= 5V 90 90 AV = 5V DD R (dB) 8886 AVDD= 2.7V R (dB) 88 SFD 84 SFD 86 AVDD= 2.7V 82 84 80 78 82 10 30 40 70 90 110 130 150 170 190 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 f (kHz) Temperature (°C) IN Figure23. Figure24. ANALOGSUPPLYCURRENT DIGITALSUPPLYCURRENT vsTEMPERATURE vsTEMPERATURE 8 2.0 1.8 7 AV = 5V DD 1.6 6 1.4 A) 5 A) 1.2 m m BV = 3.3V AV(DD 43 AVDD= 2.7V IBV(DD 10..08 DDBV = 2.7V DD 0.6 2 0.4 1 0.2 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Temperature (°C) Figure25. Figure26. 12 Copyright©2008–2012,TexasInstrumentsIncorporated

ADS7865 www.ti.com SBAS441C–OCTOBER2008–REVISEDAPRIL2012 TYPICAL CHARACTERISTICS (continued) Overtheentiresupplyvoltagerange;V =2.5V(internal),f =32MHz,andf =2MSPS,unlessotherwisenoted. REF CLK DATA ANALOGSUPPLYCURRENT ANALOGSUPPLYCURRENT vsDATARATE vsTEMPERATURE (Auto-NAPMode) (Auto-NAPMode) 6 1.8 1.6 5 1.4 AV = 5V DD 4 1.2 mA) Reference ON mA) 1.0 V(DD 3 V(DD 0.8 AVDD= 2.7V A A 2 0.6 Reference OFF 0.4 1 0.2 0 0 0 500 1000 1500 -40 -25 -10 5 20 35 50 65 80 95 110 125 Data Rate (kSPS) Temperature (°C) Figure27. Figure28. ANALOGSUPPLYCURRENT vsDATARATE REFERENCEOUTPUTVOLTAGE (DeepPower-DownMode) vsTEMPERATURE 3500 2.505 2.504 3000 2.503 2500 2.502 m(A)DD 2000 Clock ON F(V)OUT 22..550010 V 1500 E A R 2.499 V 1000 2.498 2.497 500 Clock OFF 2.496 0 2.495 0 10 20 30 40 50 60 70 -40 -25 -10 5 20 35 50 65 80 95 110 125 Data Rate (kSPS) Temperature (°C) Figure29. Figure30. Copyright©2008–2012,TexasInstrumentsIncorporated 13

ADS7865 SBAS441C–OCTOBER2008–REVISEDAPRIL2012 www.ti.com APPLICATION INFORMATION GENERAL DESCRIPTION CHx1+ The ADS7865 includes two 12-bit analog-to-digital converters (ADCs) that operate based on the CHx1- Input ADC+ successive-approximation register (SAR) principle. CHx0+ MUX ADC- The ADCs sample and convert simultaneously. CHx0- Conversion time can be as low as 406.25ns. Adding the acquisition time of 62.5ns and an additional clock cycle for setup/hold time requirements and skew Figure31. InputMultiplexerConfiguration resultsinamaximumconversionrateof2MSPS. Each ADC has a fully differential 2:1 multiplexer front- Table1.FullyDifferential2:1Multiplexer end. In many common applications, all negative input Configuration signals remain at the same constant voltage (for example, 2.5V). In this type of application, the C1 C0 ADC+ ADC– multiplexer can be used in a pseudo-differential 3:1 0 0 CHx0+ CHx0– mode, where CHx0– functions as a common-mode 1 1 CHx1+ CHx1– input and the remaining three inputs (CHx0+, CHx1–, and CHx1+) operate as separate inputs referred to Table2.Pseudo-Differential3:1Multiplexer thecommon-modeinput. Configuration TheADS7865alsoincludesa2.5Vinternalreference. C1 C0 ADC+ ADC– The reference drives a 10-bit digital-to-analog 0 0 CHx0+ CHx0– converter (DAC), allowing the voltage at the REF OUT pin to be adjusted via the internal DAC register in 0 1 CHx1– CHx0– 2.44mV steps. A low-noise operational amplifier with 1 0 CHx1+ CHx0– unity-gain buffers the DAC output voltage and drives The input path for the converter is fully differential theREF pin. OUT and provides a common-mode rejection of 72dB at The ADS7865 offers a parallel interface that is pin- 100kHz. The high CMRR also helps suppress noise compatible with the ADS7862. However, instead of inharshindustrialenvironments. the A0 pin of the ADS7862 that controls channel Each of the 2pF sample-and-hold capacitors (shown selection, the ADS7865 offers a write data input (WR) as C in the Equivalent Input Circuit ) is connected pin that supports additional functions described in the S via switches to the multiplexer output. Opening the Digital section of this data sheet (see also the switches holds the sampled data during the ADS7862Compatibilitysection). conversion process. After finishing the conversion, both capacitors are pre-charged for the duration of ANALOG one clock cycle to the voltage present at the REF IN This section discusses the analog input circuit, the pin. After the pre-charging, the multiplexer outputs ADCs,andthereferencedesignofthedevice. are connected to the sampling capacitors again. The voltage at the analog input pin is usually different AnalogInputs from the reference voltage; therefore, the sample capacitors must be charged to within one-half LSB for Each ADC is fed by an input multiplexer, as shown in 12-bit accuracy during the acquisition time t (see Figure 31. Each multiplexer is either used in a fully- ACQ theTimingCharacteristics). differential 2:1 configuration (as described in Table 1) orapseudo-differential3:1configuration(asshownin Acquisition time is indicated with the BUSY signal Table 2). The channel selection is performed using being held low. It starts by closing the input switches bits C1 and C0 in the configuration register (see also (after finishing the previous conversion and pre- theConfigurationRegistersection). charging) and finishes with the rising edge of the CONVST signal. If the ADS7865 operates at full speed,theacquisitiontimeistypically62.5ns. 14 Copyright©2008–2012,TexasInstrumentsIncorporated

ADS7865 www.ti.com SBAS441C–OCTOBER2008–REVISEDAPRIL2012 The minimum –3dB bandwidth of the driving Analog-to-DigitalConverter(ADC) operational amplifier can be calculated as shown in The ADS7865 includes two SAR-type, 2MSPS, 12-bit Equation 1, with n = 12 being the resolution of the ADCs (shown in the Functional Block Diagram on the ADS7865: frontpageofthisdatasheet). ln(2)´(n + 1) f = -3dB 2p´t CONVST ACQ (1) Theanaloginputsareheldwiththefallingedgeofthe With t = 62.5ns, the minimum bandwidth of the ACQ CONVST (conversion start) signal. The setup time of driving amplifier is 23MHz. The required bandwidth CONVST referred to the next rising edge of CLOCK can be lower if the application allows a longer (system clock) is 10ns (minimum). The conversion acquisitiontime. automatically starts with the rising CLOCK edge. A gain error occurs if a given application does not CONVST should not be issued during a conversion, fulfill the settling requirement shown in Equation 1. As thatis,whenBUSYishigh. a result of pre-charging the capacitors, linearity and THDarenotdirectlyaffected,however. CLOCK The OPA365 from Texas Instruments is The ADC uses an external clock in the range of recommended as a driver; in addition to offering the 1MHz to 32MHz. 12 clock cycles are needed for a required bandwidth, it provides a low offset and also completeconversion;thefollowingclockcycleisused offersexcellentTHDperformance. for pre-charging the sample capacitors and a minimum of two clock cycles are required for the The phase margin of the driving operational amplifier sampling. With a minimum of 16 clocks used for the is usually reduced by the ADC sampling capacitor. A entire process, one clock cycle is left for the required resistor placed between the capacitor and the setup and hold times along with some margin for amplifier limits this effect; therefore, an internal 200Ω delay caused by layout. The clock input can remain resistor (R ) is placed in series with the switch. The SER low between conversions (after applying the 16th switch resistance (R ) is typically 50Ω (see the SW falling edge to complete a running conversion). It can EquivalentInputCircuit). also remain low after applying the 14th falling edge The differential input voltage range of the ADC is during a DAC register write access if the device is not ±V ,thevoltageattheREF pin. required to perform a conversion (for example, during REF IN aninitiationphaseafterpower-up). It is important to keep the voltage to all inputs within the 0.1V limit below AGND and above AV while not The CLOCK duty cycle should be 50%. However, the DD allowing dc current to flow through the inputs. Current ADS7865 functions properly with a duty cycle is only necessary to recharge the sample-and-hold between30%and70%. capacitors. Copyright©2008–2012,TexasInstrumentsIncorporated 15

ADS7865 SBAS441C–OCTOBER2008–REVISEDAPRIL2012 www.ti.com RESET reference stable (see the previous discussion of REF ). For applications that use an external The ADS7865 features an internal power-on-reset IN reference source, the internal reference can be (POR) function. When the device is powered up, the disabled using bit RP in the SDI Register (see the POR sets the device to default mode when AVDD Digital section). The settling time of the REF pin is reaches1.8V. OUT 500μs (max) with the reference capacitor connected. The default value of the REF pin after power-up is REF OUT IN 2.5V. The reference input is not buffered and is directly For operation with a 2.7V analog supply and a 2.5V connected to the ADC. The converter generates reference, the internal reference buffer requires a rail- spikes on the reference input voltage because of to-rail input and output. Such buffers typically contain internal switching. Therefore, an external capacitor to two input stages; when the input voltage passes the the analog ground (AGND) should be used to mid-range area, a transition occurs at the output stabilize the reference input voltage. This capacitor because of switching between the two input stages. should be at least 470nF. Ceramic capacitors (X5R In this voltage range, rail-to-rail amplifiers generally type) with values up to 1μF are commonly available showaverypoorpower-supplyrejection. asSMDin0402size. As a result of this poor performance, the ADS7865 REF buffer has a fixed transition at DAC code 509 OUT (0x1FD). At this code, the DAC may show a jump of The ADS7865 includes a low-drift, 2.5V internal upto10mVinitstransferfunction. reference source. This source feeds a 10-bit string DAC that is controlled via the DAC register. As a Table 3 lists some examples of internal reference result of this architecture, the voltage at the REF DACsettings. OUT pin is programmable in 2.44mV steps and can be adjusted to specific application requirements without Table3.ReferenceDACSettingExamples theuseofadditionalexternalcomponents. DECIMAL HEXADECIMAL However, the DAC output voltage should not be VREFOUT CODE BINARYCODE CODE programmed below 0.5V to ensure the correct 0.500V 205 0011001101 CD functionality of the reference output buffer. This buffer 1.241V 508 0111111100 1FC is connected between the DAC and the REF pin, OUT 1.240V 509 0111111101 1FD and is capable of driving the capacitor at the REF IN 2.500V 1023 1111111111 3FF pin. A minimum of 470nF is required to keep the 16 Copyright©2008–2012,TexasInstrumentsIncorporated

ADS7865 www.ti.com SBAS441C–OCTOBER2008–REVISEDAPRIL2012 DIGITAL DP:Deeppower-downenable ('1'=deviceindeeppower-downmode) This section reviews the timing and control of the ADS7865parallelinterface. N:Nappower-downenable ('1'=deviceinnappower-downmode) ConfigurationRegister AN:AutoNappower-downenable The configuration register can be set by issuing a ('1'=deviceinautonappower-downmode) write access on the parallel interface. The data present on DB[11:0] are latched with the rising edge RP:Referencepower-down of WR. The data word width of the configuration ('1'=referenceisturnedoff) register is 12 bits; its structure is shown in Table 4. The default value of this register after power-up is Table7.A2,A1,andA0:DAC,Sequencer,and 0x000. SW-ResetControl Table4.ConfigurationRegisterMap A2 A1 A0 FUNCTION Configurationregister CONFIGURATIONREGISTERBIT 0 0 0 updateonly 11 10 9 8 7 6 5 4 3 2 1 0 WritetoreferenceDAC 0 0 1 C1 C0 R1 R0 DP N AN RP X(1) A2 A1 A0 registerwithnextaccess (1) X=Don'tcare. 0 1 0 Configurationregister updateonly Table5.C1andC0:ChannelSelection Readfromreference 0 1 1 DACregisterwithnext ADCA/B access C1 C0 POSITIVEINPUT NEGATIVEINPUT Writetosequencer 1 0 0 register 0 0 CHA0+/CHB0+ CHA0–/CHB0– 1 0 1 DeviceSW-reset 0 1 CHA1–/CHB1– CHA0–/CHB0– Readfromsequencer 1 0 CHA1+/CHB1+ CHA0–/CHB0– 1 1 0 register 1 1 CHA1+/CHB1+ CHA1–/CHB1– Configurationregister 1 1 1 updateonly Table6.R1andR0:RegisterUpdateEnable All enabled power-down features are activated by the R1 R0 FUNCTION rising edge of the WR pulse immediately after writing 0 0 Registerupdatedisabled totheconfigurationregister. 0 1 Registerupdateenabled Because two write accesses are required to program 1 0 Reservedforfactorytest(don’t the reference DAC and the sequencer registers, use) thesesettingsareupdatedwiththerisingedgeofWR 1 1 Registerupdatedisabled after the second write access. For more details, see the Sequencer Register and Programming the ReferenceDACsections. Copyright©2008–2012,TexasInstrumentsIncorporated 17

ADS7865 SBAS441C–OCTOBER2008–REVISEDAPRIL2012 www.ti.com Figure 32 shows a complete timing diagram The digital output code format of the ADS7865 is in consisting of a write access to set up the proper input binary twos complement, as shown in Table 8. channel, followed by an initiation of a conversion and Conversion results can be read out only once. A thereadaccessofbothconversionresults. second read access (without issuing a new conversion)resultsin000hastheoutputvalue. The input multiplexer updates with the rising edge of the WR input. The following falling edge of CONVST triggers the conversion of the previously selected channel. The data output register then updates with the falling edge of BUSY and can be read thereafter. 14 1 14 16 CLOCK CONVST WR CS RD DB[11:0] 100h Output Output D00h Output Output CHAx CHBx CHA0 CHB0 PreviousConversion Conversion of Conversion of BUSY of Both CHxx Both Differential CHx0 Both Differential CHx1 Figure32. ChannelSelectionTimingDiagram Table8.ADS7865OutputDataFormat DIFFERENTIALINPUTVOLTAGE INPUTVOLTAGEATCHXX+ HEXADECIMAL DESCRIPTION (CHXX+)–(CHXX–) (CHXX–=V =2.5V) BINARYCODE CODE REF Positivefull-scale V 5V 011111111111 7FF REF Midscale 0V 2.5V 000000000000 000 Midscale–1LSB –V /4096 2.49878V 111111111111 FFF REF Negativefull- –V 0V 100000000000 800 scale REF 18 Copyright©2008–2012,TexasInstrumentsIncorporated

ADS7865 www.ti.com SBAS441C–OCTOBER2008–REVISEDAPRIL2012 SequencerRegister A/B data of the second-last channel in the sequence, and so on. Trying to read out more results (2, 4, or 6) The ADS7865 features a programmable sequencer thantheactualsequencelengthresultsin000hatthe that controls the switching of the ADC input output of the converter. Older conversion results are multiplexer. To set up the sequencer, two write overwritten if all data of a completed sequence have accesses to the ADC are required. During the first not been read out before issuing a new conversion writeaccess,theprogrammingofthesequencermust start. Figure 34 shows an example where the be enabled by setting R[1:0] = '01' and A[2:0] = '100' sequencer is set to scan through the pseudo- in the Configuration Register. The data applied to the differential inputs of the ADS7865 beginning with data bus on the second write access contain the CHx1+, followed by CHx1– and CHx0+, while using a updatedSequencerRegistercontent. single CONVST and BUSY for the entire sequence. The structure of the Sequencer Register is shown in The internal LIFO pointer is reset with every BUSY Table9.Thedefaultvalueofthisregisterafterpower- signal rising edge. Therefore, to ensure proper data upis0x000. retrieval, the sequence results should either be read after completion of the entire sequence conversion or Detailed timing diagrams of the different sequencer between two consecutive conversions within the modesareshowninFigure33. sequence as indicated in Figure 34. Other read If the output data are read after the entire sequence optionsmaydeliverincorrectresults. has been converted, the output data are presented in LIFO manner (last in, first out); that is, the conversion results of ADC A is followed by ADC B data of the last channel in the sequence, followed by the ADC Table9.SequencerRegisterMap SEQUENCERREGISTERBIT 11 10 9 8 7 6 5 4 3 2 1 0 S1 S0 SL1 SL0 CH1 CM1 CH2 CM2 CH3 CM3 SP1 SP0 Table10. S1andS0:SequencerMode S1 S0 FUNCTION 0 X IndividualCONVSTandBUSYforeachconversion SingleCONVSTforentiresequenceandindividualBUSYforeach 1 0 conversion 1 1 SingleCONVSTandBUSYforentiresequence Table11.SL1andSL0:SequenceLength SL1 SL0 FUNCTION 0 0 Length=0:Sequencerdisabled 0 1 Length=1:Cx1(bits6/7)enabled 1 0 Length=2:Cx1(bits6/7)andCx2(bits4/5)enabled 1 1 Length=3:Cx1(bits6/7),Cx2(bits4/5),andCx3(bits2/3)enabled CH1:Signalinputofthefirstchannelinsequence;refertoTable12fordetails. CM1:Common-modeinputofthefirstchannelinsequence;refertoTable12fordetails. CH2:Signalinputofthesecondchannelinsequence;refertoTable12fordetails. CM2:Common-modeinputofthesecondchannelinsequence;refertoTable12fordetails. CH3:Signalinputofthethirdchannelinsequence;refertoTable12fordetails. CM3:Common-modeinputofthethirdchannelinsequence;refertoTable12fordetails. Copyright©2008–2012,TexasInstrumentsIncorporated 19

ADS7865 SBAS441C–OCTOBER2008–REVISEDAPRIL2012 www.ti.com Table12.ChannelSelection Table13.SP1andSP0:SequencePosition(Read- Only) ADCA/B SP1 SP0 FUNCTION COMMON-MODE CHx CMx SIGNALINPUT INPUT 0 0 Sequencerdisabled 0 0 CHA0+/CHB0+ CHA0–/CHB0– CH1/CM1(bits6/7)tobeconvertedat 0 1 nextfallingedgeofCONVST 0 1 CHA1–/CHB1– CHA0–/CHB0– CH2/CM2(bits4/5)tobeconvertedat 1 0 CHA1+/CHB1+ CHA0–/CHB0– 1 0 nextfallingedgeofCONVST 1 1 CHA1+/CHB1+ CHA1–/CHB1– CH3/CM3(bits2/3)tobeconvertedat 1 1 nextfallingedgeofCONVST Mode 0 (One-shot conversion start, one BUSY for whole sequence) CONVST BUSY Conv A Conv B Conv C Mode 1 (One-shot conversion start, one BUSY for each conversion) CONVST BUSY Conv A Conv B Conv C Mode 2 (One conversion start and one BUSY for each conversion) CONVST BUSY Conv A Conv B Conv C 5.5 t CLK Figure33. SequencerModes(Example:SL='11') 1 14 21 35 41 CLOCK CONVST WR CS RD DB[11:0] 0x104 0xF90 COHuAtp1u+t COHuBtp1u+t COHutAp1u-t COHutBp1u-t Conversion of Conversion of Conv. of BUSY Both CH1+ Both CH1- Both CH0+ Figure34. SequencerProgrammingExample 20 Copyright©2008–2012,TexasInstrumentsIncorporated

ADS7865 www.ti.com SBAS441C–OCTOBER2008–REVISEDAPRIL2012 ProgrammingtheReferenceDAC To verify the current DAC setting, a WR pulse must be generated while providing a control word The internal reference DAC can be set by issuing a containing R[1:0] = '01' and A[2:0] = '011' to initialize WR pulse while providing a control word with R[1:0] = the DAC read access. Thereafter, triggering the RD '01' and A[2:0] = '001' (see Table 4). Thereafter, a line causes the data bus to provide the 10-bit DAC second WR pulse must be generated with the data valueonDB[9:0]. bus bits DB[11:10] = '00' and DB[9:0] containing the actual 10-bit DAC value, with DB9 being the MSB Table 14 shows the content of this register; the (seeFigure35). default value after power-up is 0x3FF (see also Table3). Table14.DACRegisterContents DACREGISTERCONTENT 11 10 9 8 7 6 5 4 3 2 1 0 0 0 MSB Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 WR CS RD DB[11:0] b01xxxxx001 DACValue b01xxxxx011 DACValue Figure35. DACWriteandReadAccessTimingDiagram Copyright©2008–2012,TexasInstrumentsIncorporated 21

ADS7865 SBAS441C–OCTOBER2008–REVISEDAPRIL2012 www.ti.com Power-DownModesandReset The auto-nap power-down mode is very similar to the nap mode. The only differences are the methods The ADS7865 has a comprehensive built-in power- of powering down and waking up the device. The down feature. There are three power-down modes: Configuration Register bit AN is only used to deep power-down, nap power-down, and auto-nap enable/disable this feature. If the auto-nap mode is power-down. All three power-down modes are enabled, the ADS7865 turns off the biasing activated with the rising WR edge after having been automatically after finishing a conversion; thus, the activated by asserting the corresponding bit in the end of conversion actually activates the auto-nap Configuration Register (DP = '1', N = '1', or AN = '1'). power-down. The device powers down within 200ns All modes are deactivated by de-asserting the in this mode, as well. Triggering a new conversion by respective bit in the Configuration Register. The applying a CONVST pulse returns the device to contents of the Configuration Register are not normal operation and automatically starts a new affected by any of the power-down modes. Any conversion six CLOCK cycles later. Therefore, a ongoing conversion aborts when deep or nap power- complete conversion cycle takes 22 CLOCK cycles; down is initiated. Table 15 lists the differences among thus, the maximum throughput rate in auto-nap thethreepower-downmodes. power-downmodeisreducedto1.45MSPS. In deep power-down mode, all functional blocks To issue a device reset, a write access to the except the digital interface are disabled. The analog Configuration Register must be generated to set block has its bias currents turned off. In this mode, A[2:0] = '101'. With the rising edge of the WR input, the power dissipation reduces to 1μA within 2μs. The the entire device is forced into reset. After wake-uptimefromdeeppower-downmodeis1μs. approximately 20ns, the parallel interface becomes In nap power-down mode, the ADS7865 turns off activeagain. the biasing of the comparator and the mid-voltage buffer within 200ns. The device goes into nap power- downmoderegardlessoftheconversionstate. Table15.Power-DownModes POWER-DOWN ENABLED ACTIVATION RESUMED DISABLED TYPE BY ACTIVATEDBY TIME BY REACTIVATIONTIME BY Deep DP='1' RisingWRedge 2μs DP='0' 1μs DP='0' Nap N='1' RisingWRedge 200ns N='0' 6clocks N='0' Eachendof Auto-nap AN='1' 200ns CONVSTpulse 6clocks AN='0' conversion 22 Copyright©2008–2012,TexasInstrumentsIncorporated

ADS7865 www.ti.com SBAS441C–OCTOBER2008–REVISEDAPRIL2012 ADS7862 COMPATIBILITY DAC properly via the DAC register while removing theexternalresistors;or The ADS7865IPBS is pin-compatible with the • An additional external buffer between the resistor ADS7862Y. However, there are some differences divider and the required 470nF (minimum) between the two devices that must be considered capacitorontheREF input. when migrating from the ADS7862 to the ADS7865 in IN anexistingdesign. In the latter case, while the capacitor stabilizes the reference voltage during the entire conversion, the WRversusA0 buffer must recharge it by providing an average currentonly;thus,therequiredminimumbandwidthof One of the differences is that pin 22, which triggers thebuffercanbecalculatedusingEquation2: writing to the internal Configuration Register of the ADS7865 (WR), is used to select the input channel ln(2)´2 f = ontheADS7862(A0). -3dB 2p´16´t CLK (2) Channel selection on the ADS7865 can only be The buffer must also be capable of driving the 470nF performed by setting bits C[1:0] in the Configuration loadwhilemaintainingitsstability. Register or, automatically, by the sequencer (see the SequencerRegistersectionfordetails). Timing REF The only timing requirement that may cause the IN ADS7865 to malfunction in an existing ADS7862- TheADS7865offersanunbufferedREF inputwitha IN based design is the CONVST low time (t ) which is code-dependent input impedance while featuring a 1 specified to be 20ns minimum, while the ADS7862 programmable and buffered reference output works properly with a pulse as short as 15ns. All (REF ). The ADS7862 offers a high-impedance OUT other required minimum setup and hold times are (buffered) reference input. If an existing ADS7862- specified to be either the same as or lower than the based design uses the internal reference of the ADS7865; therefore, there are no conflicts with the device and relies on an external resistor divider to ADS7862requirements. adjust the input voltage range of the ADC, migration to the ADS7865 platform requires one of the following conditions: • A software change to set up the internal reference Copyright©2008–2012,TexasInstrumentsIncorporated 23

ADS7865 SBAS441C–OCTOBER2008–REVISEDAPRIL2012 www.ti.com APPLICATION INFORMATION ln(2)´(n + 1) f = The absolute minimum configuration of the ADS7865 FILTER 2´p´2´R´C (3) in an application is shown in Figure 36. In this case, It is recommended to use a capacitor value of at least the ADS7865 is used in dual-channel mode only, with 20pF. thedefaultsettingsofthedeviceafterpowerup. Keep the acquisition time in mind; the resistor value The input signal for the amplifiers must fulfill the can be calculated as shown in Equation 4 for each of common-mode voltage requirements of the ADS7865 the series resistors (with n = 12, the resolution of the in this configuration. The actual values of the ADS7865). resistors and capacitors depend on the bandwidth t andperformancerequirementsoftheapplication. R = ACQ ln(2)´(n + 1)´2´C (4) Those values can be calculated using Equation 3, withn=12beingtheresolutionoftheADS7865. BV DD 1mF 0.1mF ADS7865 AV BGND BV DD DD BGND CHB1+ DB[11:0] OPA2365 CHB1- BUSY AGND CHB0+ CLOCK Controller CHB0- WR Device CHA1+ RD CHA1- CONVST OPA2365 AGND CHA0+ CS CHA0- SDI BGND AGND REF M0 BV IN DD AV DD 470nF REFOUT M1 (min) AGND AV DD OPA2365 0.1mF (min) 1mF AGND OPA2365 AGND Figure36. MinimumADS7865Configuration 24 Copyright©2008–2012,TexasInstrumentsIncorporated

ADS7865 www.ti.com SBAS441C–OCTOBER2008–REVISEDAPRIL2012 LAYOUT Depending on the circuit density of the board, placement of the analog and digital components, and For optimum performance, care should be taken with the related current loops, a single solid ground plane the physical layout of the ADS7865 circuitry. This for the entire printed circuit board (PCB) or a caution is particularly true if the CLOCK input dedicated analog ground area may be used. In an approaches the maximum throughput rate. In this instanceofaseparatedanaloggroundarea,ensurea case, it is recommended to have a fixed phase low-impedance connection between the analog and relationshipbetweenCLOCKandCONVST. digital ground of the ADC by placing a bridge Additionally, the basic SAR architecture is quite underneath (or next to) the ADC. Otherwise, even sensitive to glitches or sudden changes on the power short undershoots on the digital interface with a value supply, reference, ground connections, and digital lower than –300mV may lead to conduction of ESD inputs that occur just before latching the output of the diodes, causing current flow through the substrate analog comparator. Therefore, when driving any anddegradingtheanalogperformance. single conversion for an n-bit SAR converter, there During the PCB layout process, care should also be are n windows in which large external transient taken to avoid any return currents crossing any voltages can affect the conversion result. Such sensitive analog areas or signals. No signal must glitches might originate from switching power exceed the limit of –300mV with regard to the supplies, nearby digital logic, or high-power devices. respective ground plane. Figure 37 illustrates the The degree of error in the digital output depends on recommended layout of the ground and power-supply the reference voltage, layout, and the exact timing of connections. the external event. These errors can change if the external event also changes in time with respect to Supply theCLOCKinput. The ADS7865 has two separate supplies: the BV With this possibility in mind, power to the ADS7865 DD pin for the digital interface and the AV pin for all should be clean and well-bypassed. A 0.1μF ceramic DD remainingcircuits. bypass capacitor should be placed as close to the device as possible. In addition, a 1μF to 10μF BV can range from 2.7V to 5.5V, allowing the DD capacitor is recommended. If needed, an even larger ADS7865 to easily interface with processors and capacitor and a 5Ω or 10Ω series resistor may be controllers. To limit the injection of noise energy from usedtolow-passfilteranoisysupply. external digital circuitry, BV should be filtered DD properly. Bypass capacitors of 0.1μF and 10μF If the reference voltage is external and originates should be placed between the BV pin and the from an operational amplifier, be sure that it can drive DD groundplane. the reference capacitor without oscillation. The connection between the output of the external AV supplies the internal analog circuitry. For DD reference driver and REF should be of low optimum performance, a linear regulator (for IN resistance (10Ω max) to minimize any code- example, the UA7805 family) is recommended to dependentvoltagedroponthispath. generate the analog supply voltage in the range of 2.7V to 5.5V for the ADS7865 and the necessary Grounding analogfront-endcircuitry. All ground (AGND and BGND) pins should be Bypasscapacitorsshouldbeconnectedtotheground connected to a clean ground reference. These plane such that the current is allowed to flow through connections should be kept as short as possible to the pad of the capacitor (that is, the vias should be minimize the inductance of these paths. It is placed on the opposite side of the connection recommended to use vias connecting the pads between the capacitor and the power-supply pin of directly to the ground plane. In designs without theADC). ground planes, the ground trace should be kept as wide as possible. Avoid connections that are too near DigitalInterface the grounding point of a microcontroller or digital To further optimize device performance, a series signalprocessor. resistor of 10Ω to 100Ω can be used on each digital pin of the ADS7865. In this way, the slew rates of the input and output signals are reduced, limiting the noiseinjectionfromthedigitalinterface. Copyright©2008–2012,TexasInstrumentsIncorporated 25

ADS7865 SBAS441C–OCTOBER2008–REVISEDAPRIL2012 www.ti.com Top View ADS7865I 32 31 30 29 28 27 26 25 REFIN BVDD 470 nF REFOUT BGND 0.1 1 AGND 22 mF mF to 1.0 0.1 mF mF AVDD 21 BVDD to 5 20 AV DD 6 19 7 18 8 17 9 10 11 12 13 14 15 16 LEGEND TOP layer; copper pour and traces lower layer; AGND area lower layer; BGND area via Figure37. OptimizedLayoutRecommendation 26 Copyright©2008–2012,TexasInstrumentsIncorporated

ADS7865 www.ti.com SBAS441C–OCTOBER2008–REVISEDAPRIL2012 REVISION HISTORY NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(May2010)toRevisionC Page • DeletedOrderingInformationtable....................................................................................................................................... 2 ChangesfromRevisionA(June2009)toRevisionB Page • Deletedfootnote2fromElectricalCharacteristicstable ....................................................................................................... 3 • ChangedRESETsectionofApplicationsInformation ........................................................................................................ 16 • AddedlastsentenceinfinalparagraphoftheConfigurationRegistersection ................................................................... 18 • ChangedlastparagraphofSequencerRegistersection .................................................................................................... 19 • UpdatedFigure33 .............................................................................................................................................................. 20 • UpdatedFigure34 .............................................................................................................................................................. 20 Copyright©2008–2012,TexasInstrumentsIncorporated 27

PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS7865IPBS ACTIVE TQFP PBS 32 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7865I A & no Sb/Br) ADS7865IPBSG4 ACTIVE TQFP PBS 32 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7865I A & no Sb/Br) ADS7865IPBSR ACTIVE TQFP PBS 32 1000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7865I A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS7865IPBSR TQFP PBS 32 1000 330.0 16.4 7.2 7.2 1.5 12.0 16.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS7865IPBSR TQFP PBS 32 1000 350.0 350.0 43.0 PackMaterials-Page2

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