ADS7844 ADS7844 ADS7844 SBAS100A – JANUARY 1998 – REVISED OCTOBER 2003 12-Bit, 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION (cid:1) SINGLE SUPPLY: 2.7V to 5V The ADS7844 is an 8-channel, 12-bit sampling analog-to- (cid:1) 8-CHANNEL SINGLE-ENDED OR digital converter (ADC) with a synchronous serial interface. 4-CHANNEL DIFFERENTIAL INPUT Typical power dissipation is 3mW at a 200kHz throughput (cid:1) UP TO 200kHz CONVERSION RATE rate and a +5V supply. The reference voltage (VREF) can be varied between 100mV and V , providing a corresponding (cid:1) ±1 LSB MAX INL AND DNL input voltage range of 0V to CVC . The device includes a REF (cid:1) NO MISSING CODES shutdown mode that reduces power dissipation to under (cid:1) 72dB SINAD 1µW. The ADS7844 is ensured down to 2.7V operation. (cid:1) SERIAL INTERFACE Low power, high speed, and onboard multiplexer make the (cid:1) 20-LEAD QSOP AND ADS7844 ideal for battery-operated systems such as personal digital assistants, portable multichannel data loggers, and 20-LEAD SSOP PACKAGES measurement equipment. The serial interface also provides (cid:1) ALTERNATE SOURCE FOR MAX147 low-cost isolation for remote data acquisition. The ADS7844 is available in a 20-lead QSOP package and the MAX147 APPLICATIONS equivalent 20-lead SSOP package and is ensured over the (cid:1) DATA ACQUISITION –40°C to +85°C temperature range. (cid:1) TEST AND MEASUREMENT (cid:1) INDUSTRIAL PROCESS CONTROL (cid:1) PERSONAL DIGITAL ASSISTANTS (cid:1) BATTERY-POWERED SYSTEMS CH0 CH1 SAR DCLK CH2 Eight CH3 Channel CS CH4 Multiplexer Comparator Serial SHDN CH5 Interface CDAC DIN CH6 and CH7 Control DOUT COM BUSY V REF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 1998-2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com

SPECIFICATION: +5V At T = –40°C to +85°C, +V = +5V, V = +5V, f = 200kHz, and f = 16 • f = 3.2MHz, unless otherwise noted. A CC REF SAMPLE CLK SAMPLE ADS7844E, N ADS7844EB, NB PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS ANALOG INPUT Full-Scale Input Span Positive Input - Negative Input 0 V ✻ ✻ V REF Absolute Input Range Positive Input –0.2 +V +0.2 ✻ ✻ V CC Negative Input –0.2 +1.25 ✻ ✻ V Capacitance 25 ✻ pF Leakage Current ±1 ✻ µA SYSTEM PERFORMANCE Resolution 12 ✻ Bits No Missing Codes 12 ✻ Bits Integral Linearity Error ±2 ±1 LSB(1) Differential Linearity Error ±0.8 ±0.5 ±1 LSB Offset Error ±3 ✻ LSB Offset Error Match 0.15 1.0 ✻ ✻ LSB Gain Error ±4 ±3 LSB Gain Error Match 0.1 1.0 ✻ ✻ LSB Noise 30 ✻ µVrms Power Supply Rejection 70 ✻ dB SAMPLING DYNAMICS Conversion Time 12 ✻ Clk Cycles Acquisition Time 3 ✻ Clk Cycles Throughput Rate 200 ✻ kHz Multiplexer Settling Time 500 ✻ ns Aperture Delay 30 ✻ ns Aperture Jitter 100 ✻ ps DYNAMIC CHARACTERISTICS Total Harmonic Distortion(2) V = 5V at 10kHz –76 –78 dB IN PP Signal-to-(Noise + Distortion) V = 5V at 10kHz 71 72 dB IN PP Spurious Free Dynamic Range V = 5V at 10kHz 76 78 dB IN PP Channel-to-Channel Isolation V = 5V at 50kHz 120 ✻ dB IN PP REFERENCE INPUT Range 0.1 +V ✻ ✻ V CC Resistance DCLK Static 5 ✻ GΩ Input Current 45 100 ✻ ✻ µA f = 12.5kHz 2.5 ✻ µA SAMPLE DCLK Static 0.001 3 ✻ ✻ µA DIGITAL INPUT/OUTPUT Logic Family CMOS ✻ Logic Levels V | I | ≤ +5µA 3.0 5.5 ✻ ✻ V IH IH V | I | ≤ +5µA –0.3 +0.8 ✻ ✻ V IL IL V I = –250µA 3.5 ✻ V OH OH V I = 250µA 0.4 ✻ V OL OL Data Format Straight Binary ✻ POWER SUPPLY REQUIREMENTS +V Specified Performance 4.75 5.25 ✻ ✻ V CC Quiescent Current 550 900 ✻ µA f = 12.5kHz 300 ✻ µA SAMPLE Power-Down Mode(3), CS = +V 3 ✻ µA CC Power Dissipation 4.5 ✻ mW TEMPERATURE RANGE Specified Performance –40 +85 ✻ ✻ °C ✻ Same specifications as ADS7844E, ADS7844N. NOTE: (1) LSB means Least Significant Bit. With V equal to +5.0V, one LSB is 1.22mV. (2) First five harmonics of the test frequency. (3) Auto power-down mode REF (PD1 = PD0 = 0) active or SHDN = GND. ADS7844 2 www.ti.com SBAS100A

SPECIFICATION: +2.7V At T = –40°C to +85°C, +V = +2.7V, V = +2.5V, f = 125kHz, and f = 16 • f = 2MHz, unless otherwise noted. A CC REF SAMPLE CLK SAMPLE ADS7844E, N ADS7844EB, NB PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS ANALOG INPUT Full-Scale Input Span Positive Input - Negative Input 0 V ✻ ✻ V REF Absolute Input Range Positive Input –0.2 +V +0.2 ✻ ✻ V CC Negative Input –0.2 +0.2 ✻ ✻ V Capacitance 25 ✻ pF Leakage Current ±1 ✻ µA SYSTEM PERFORMANCE Resolution 12 ✻ Bits No Missing Codes 12 ✻ Bits Integral Linearity Error ±2 ±1 LSB(1) Differential Linearity Error ±0.8 ±0.5 ±1 LSB Offset Error ±3 ✻ LSB Offset Error Match 0.15 1.0 ✻ ✻ LSB Gain Error ±4 ±3 LSB Gain Error Match 0.1 1.0 ✻ ✻ LSB Noise 30 ✻ µVrms Power Supply Rejection 70 ✻ dB SAMPLING DYNAMICS Conversion Time 12 ✻ Clk Cycles Acquisition Time 3 ✻ Clk Cycles Throughput Rate 125 ✻ kHz Multiplexer Settling Time 500 ✻ ns Aperture Delay 30 ✻ ns Aperture Jitter 100 ✻ ps DYNAMIC CHARACTERISTICS Total Harmonic Distortion(2) V = 2.5V at 10kHz –75 –77 dB IN PP Signal-to-(Noise + Distortion) V = 2.5V at 10kHz 71 72 dB IN PP Spurious Free Dynamic Range V = 2.5V at 10kHz 78 80 dB IN PP Channel-to-Channel Isolation V = 2.5V at 50kHz 100 ✻ dB IN PP REFERENCE INPUT Range 0.1 +V ✻ ✻ V CC Resistance DCLK Static 5 ✻ GΩ Input Current 13 40 ✻ ✻ µA f = 12.5kHz 2.5 ✻ µA SAMPLE DCLK Static 0.001 3 ✻ ✻ µA DIGITAL INPUT/OUTPUT Logic Family CMOS ✻ Logic Levels V | I | ≤ +5µA +V • 0.7 5.5 ✻ ✻ V IH IH CC V | I | ≤ +5µA –0.3 +0.8 ✻ ✻ V IL IL V I = –250µA +V • 0.8 ✻ V OH OH CC V I = 250µA 0.4 ✻ V OL OL Data Format Straight Binary ✻ POWER SUPPLY REQUIREMENTS +V Specified Performance 2.7 3.6 ✻ ✻ V CC Quiescent Current 280 650 ✻ ✻ µA f = 12.5kHz 220 ✻ µA SAMPLE Power-Down Mode(3), CS = +V 3 ✻ µA CC Power Dissipation 1.8 ✻ mW TEMPERATURE RANGE Specified Performance –40 +85 ✻ ✻ °C ✻ Same specifications as ADS7844E, ADS7844N. NOTE: (1) LSB means Least Significant Bit. With V equal to +2.5V, one LSB is 610mV. (2) First five harmonics of the test frequency. (3) Auto power-down mode REF (PD1 = PD0 = 0) active or SHDN = GND. ADS7844 3 SBAS100A www.ti.com

PACKAGE/ORDERING INFORMATION(1) MINIMUM RELATIVE MAXIMUM SPECIFIED ACCURACY GAIN ERROR TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT (LSB) (LSB) RANGE PACKAGE-LEAD DESIGNATOR NUMBER MEDIA, QUANTITY ADS7844E ±2 ±4 –40°C to +85°C QSOP-20 DBQ ADS7844E Rails, 56 " " " " " " ADS7844E/2K5 Tape and Reel, 2500 ADS7844N " " " SSOP-20 DB ADS7844N Rails, 68 " " " " " " ADS7844N/1K Tape and Reel,1000 ADS7844EB ±1 ±3 –40°C to +85°C QSOP-20 DBQ ADS7844EB Rails, 56 " " " " " " ADS7844EB/2K5 Tape and Reel, 2500 ADS7844NB " " " SSOP-20 DB ADS7844NB Rails, 68 " " " " " " ADS7844NB/1K Tape and Reel, 1000 NOTES: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet. PIN CONFIGURATION PIN DESCRIPTIONS Top View PIN NAME DESCRIPTION 1 CH0 Analog Input Channel 0. 2 CH1 Analog Input Channel 1. CH0 1 20 +V CC 3 CH2 Analog Input Channel 2. CH1 2 19 D 4 CH3 Analog Input Channel 3. CLK 5 CH4 Analog Input Channel 4. CH2 3 18 CS 6 CH5 Analog Input Channel 5. 7 CH6 Analog Input Channel 6. CH3 4 17 D IN 8 CH7 Analog Input Channel 7. CH4 5 16 BUSY 9 COM Ground reference for analog inputs. Sets zero code ADS7844 voltage in single ended mode. Connect this pin to ground CH5 6 15 DOUT or ground reference point. 10 SHDN Shutdown. When LOW, the device enters a very low CH6 7 14 GND power shutdown mode. CH7 8 13 GND 11 VREF Voltage Reference Input. See Specification Table for ranges. COM 9 12 +VCC 12 +VCC Power Supply, 2.7V to 5V. 13 GND Ground SHDN 10 11 V REF 14 GND Ground 15 D Serial Data Output. Data is shifted on the falling edge of OUT D . This output is high impedance when CLK CS is high. 16 BUSY Busy Output. Busy goes low when the DIN control bits are being read and also when the device is converting. ABSOLUTE MAXIMUM RATINGS(1) The Output is high impedance when CS is High. 17 D Serial Data Input. If CS is LOW, data is latched on rising +V to GND........................................................................–0.3V to +6V IN CC edge of D . Analog Inputs to GND............................................–0.3V to +V + 0.3V CLK CC Digital Inputs to GND...........................................................–0.3V to +6V 18 CS Chip Select Input. Active LOW. Data will not be clocked Power Dissipation..........................................................................250mW into DIN unless CS is low. When CS is high DOUT is high Maximum Junction Temperature...................................................+150°C impedance. Operating Temperature Range........................................–40°C to +85°C 19 CLK External Clock Input. The clock speed determines the Storage Temperature Range.........................................–65°C to +150°C conversion rate by the equation fCLK = 16 • fSAMPLE. Lead Temperature (soldering, 10s)...............................................+300°C 20 +VCC Power Supply NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ADS7844 4 www.ti.com SBAS100A

TYPICAL PERFORMANCE CURVES:+5V At T = +25°C, +V = +5V, V = +5V, f = 200kHz, and f = 16 • f = 3.2MHz, unless otherwise noted. A CC REF SAMPLE CLK SAMPLE FREQUENCY SPECTRUM FREQUENCY SPECTRUM (4096 Point FFT; fIN = 1,123Hz, –0.2dB) (4096 Point FFT; fIN = 10.3kHz, –0.2dB) 0 0 –20 –20 Amplitude (dB) –––468000 Amplitude (dB) –––468000 –100 –100 –120 –120 0 25 50 75 100 0 25 50 75 100 Frequency (kHz) Frequency (kHz) SIGNAL-TO-NOISE RATIO AND SIGNAL-TO- SPURIOUS FREE DYNAMIC RANGE AND TOTAL (NOISE+DISTORTION) vs INPUT FREQUENCY HARMONIC DISTORTION vs INPUT FREQUENCY 74 85 –85 SNR SFDR 73 B) 80 –80 and SINAD (d 7721 SINAD SFDR (dB) 75 THD –75 THD (dB) R 70 SN 70 –70 69 68 65 –65 1 10 100 1 10 100 Input Frequency (kHz) Input Frequency (kHz) EFFECTIVE NUMBER OF BITS CHANGE IN SIGNAL-TO-(NOISE+DISTORTION) vs INPUT FREQUENCY vs TEMPERATURE 12.0 0.6 0.4 11.8 s Bit B) ber of 11.6 5°C (d 0.2 Num m +2 0.0 Effective 1111..42 Delta fro –0.2 –0.4 f = 10kHz, –0.2dB IN 11.0 –0.6 1 10 100 –40 –20 0 20 40 60 80 100 Input Frequency (kHz) Temperature (°C) ADS7844 5 SBAS100A www.ti.com

TYPICAL PERFORMANCE CURVES:+2.7V At T = +25°C, +V = +2.7V, V = +2.5V, f = 125kHz, and f = 16 • f = 2MHz, unless otherwise noted. A CC REF SAMPLE CLK SAMPLE FREQUENCY SPECTRUM FREQUENCY SPECTRUM (4096 Point FFT; fIN = 1,129Hz, –0.2dB) (4096 Point FFT; fIN = 10.6kHz, –0.2dB) 0 0 –20 –20 B) –40 B) –40 Amplitude (d ––6800 Amplitude (d ––6800 –100 –100 –120 –120 0 15.6 31.3 46.9 62.5 0 15.6 31.3 46.9 62.5 Frequency (kHz) Frequency (kHz) SIGNAL-TO-NOISE RATIO AND SIGNAL-TO- SPURIOUS FREE DYNAMIC RANGE AND TOTAL (NOISE+DISTORTION) vs INPUT FREQUENCY HARMONIC DISTORTION vs INPUT FREQUENCY 78 90 –90 SNR 85 –85 74 SFDR 80 –80 B) d 70 R and SINAD ( 6662 SINAD SFDR (dB) 776505 THD –––776505 THD (dB) SN 60 –60 58 55 –55 54 50 –50 1 10 100 1 10 100 Input Frequency (kHz) Input Frequency (kHz) EFFECTIVE NUMBER OF BITS CHANGE IN SIGNAL-TO-(NOISE+DISTORTION) vs INPUT FREQUENCY vs TEMPERATURE 12.0 0.4 f = 10kHz, –0.2dB IN 11.5 0.2 s Bit B) Number of 1110..05 m +25°C (d –00..02 Effective 10.0 Delta fro –0.4 9.5 –0.6 9.0 –0.8 1 10 100 –40 –20 0 20 40 60 80 100 Input Frequency (kHz) Temperature (˚C) ADS7844 6 www.ti.com SBAS100A

TYPICAL PERFORMANCE CURVES:+2.7V (CONT) At T = +25°C, +V = +2.7V, V = +2.5V, f = 125kHz, and f = 16 • f = 2MHz, unless otherwise noted. A CC REF SAMPLE CLK SAMPLE POWER DOWN SUPPLY CURRENT SUPPLY CURRENT vs TEMPERATURE vs TEMPERATURE 400 140 350 120 µA) 300 nA) 100 nt ( nt ( e e urr 250 urr 80 C C pply 200 pply 60 u u S S 150 40 100 20 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 Temperature (˚C) Temperature (˚C) INTEGRAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE 1.00 1.00 0.75 0.75 0.50 0.50 ILE (LSB) 00..2050 DLE (LSB) 00..2050 –0.25 –0.25 –0.50 –0.50 –0.75 –0.75 –1.00 –1.00 000H 800H FFFH 000H 800H FFFH Output Code Output Code CHANGE IN GAIN vs TEMPERATURE CHANGE IN OFFSET vs TEMPERATURE 0.15 0.6 0.10 0.4 B) B) S S L 0.05 L 0.2 C ( C ( 5˚ 5˚ 2 0.00 2 0.0 + + m m o o a fr –0.05 a fr –0.2 elt elt D D –0.10 –0.4 –0.15 –0.6 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 Temperature (˚C) Temperature (˚C) ADS7844 7 SBAS100A www.ti.com

TYPICAL PERFORMANCE CURVES (CONT) At T = +25°C, +V = +2.7V, V = +2.5V, f = 125kHz, and f = 16 • f = 2MHz, unless otherwise noted. A CC REF SAMPLE CLK SAMPLE REFERENCE CURRENT vs SAMPLE RATE REFERENCE CURRENT vs TEMPERATURE 14 18 12 16 µnt (A) 10 µnt (A) 14 Curre 8 Curre 12 nce 6 nce e e 10 efer 4 efer R R 8 2 0 6 0 25 50 75 100 125 –40 –20 0 20 40 60 80 100 Sample Rate (kHz) Temperature (˚C) SUPPLY CURRENT vs +V MAXIMUM SAMPLE RATE vs +V CC CC 320 1M 300 f = 12.5kHz SAMPLE µent (A) 228600 VREF = +VCC ate (Hz) 100k y Curr 240 mple R uppl 220 Sa 10k S V = +V 200 REF CC 180 1k 2 2.5 3 3.5 4 4.5 5 2 2.5 3 3.5 4 4.5 5 +VCC (V) +VCC (V) ADS7844 8 www.ti.com SBAS100A

THEORY OF OPERATION ANALOG INPUT Figure 2 shows a block diagram of the input multiplexer on The ADS7844 is a classic successive approximation register the ADS7844. The differential input of the converter is (SAR) analog-to-digital (A/D) converter. The architecture is derived from one of the eight inputs in reference to the COM based on capacitive redistribution which inherently includes pin or four of the eight inputs. Table I and Table II show the a sample/hold function. The converter is fabricated on a relationship between the A2, A1, A0, and SGL/DIF control 0.6µs CMOS process. bits and the configuration of the analog multiplexer. The The basic operation of the ADS7844 is shown in Figure 1. control bits are provided serially via the DIN pin, see the The device requires an external reference and an external Digital Interface section of this data sheet for more details. clock. It operates from a single supply of 2.7V to 5.25V. The When the converter enters the hold mode, the voltage external reference can be any voltage between 100mV and difference between the +IN and –IN inputs (see Figure 2) is +V . The value of the reference voltage directly sets the CC captured on the internal capacitor array. The voltage on the input range of the converter. The average reference input –IN input is limited between –0.2V and 1.25V, allowing the current depends on the conversion rate of the ADS7844. input to reject small signals which are common to both the The analog input to the converter is differential and is +IN and –IN input. The +IN input has a range of –0.2V to provided via an eight-channel multiplexer. The input can be +V + 0.2V. CC provided in reference to a voltage on the COM pin (which The input current on the analog inputs depends on the is generally ground) or differentially by using four of the conversion rate of the device. During the sample period, the eight input channels (CH0 - CH7). The particular configura- source must charge the internal sampling capacitor (typi- tion is selectable via the digital interface. A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 0 0 0 +IN –IN 0 0 0 +IN –IN 1 0 0 +IN –IN 0 0 1 +IN –IN 0 0 1 +IN –IN 0 1 0 +IN –IN 1 0 1 +IN –IN 0 1 1 +IN –IN 0 1 0 +IN –IN 1 0 0 –IN +IN 1 1 0 +IN –IN 1 0 1 –IN +IN 0 1 1 +IN –IN 1 1 0 –IN +IN 1 1 1 +IN –IN 1 1 1 –IN +IN TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH). TABLE II. Differential Channel Control (SGL/DIF LOW). +2.7V to +5V ADS7844 0.1µF 1µF to 10µF 1 CH0 +V 20 CC 2 CH1 D 19 Serial/Conversion Clock CLK 3 CH2 CS 18 Chip Select Single-ended or differential 4 CH3 D 17 Serial Data In analog inputs IN 5 CH4 BUSY 16 6 CH5 D 15 Serial Data Out OUT 7 CH6 GND 14 8 CH7 GND 13 9 COM +V 12 CC 10 SHDN V 11 REF 1µF to 10µF FIGURE 1. Basic Operation of the ADS7844. ADS7844 9 SBAS100A www.ti.com

Likewise, the noise or uncertainty of the digitized output will A2-A0 increase with lower LSB size. With a reference voltage of (shown 000B)(1) 100mV, the LSB size is 24µV. This level is below the internal noise of the device. As a result, the digital output CH0 code will not be stable and vary around a mean value by a CH1 number of LSBs. The distribution of output codes will be CH2 gaussian and the noise can be reduced by simply averaging CH3 consecutive conversion results or applying a digital filter. CH4 With a lower reference voltage, care should be taken to CH5 provide a clean layout including adequate bypassing, a clean CH6 (low noise, low ripple) power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is lower, CH7 +IN Converter the converter will also be more sensitive to nearby digital −IN signals and electromagnetic interference. The voltage into the V input is not buffered and directly REF drives the capacitor digital-to-analog converter (CDAC) portion of the ADS7844. Typically, the input current is 13µA with a 2.5V reference. This value will vary by microamps depending on the result of the conversion. The reference current diminishes directly with both conversion rate and reference voltage. As the current from the reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period will not reduce overall current drain from the reference. COM DIGITAL INTERFACE NOTE: (1) See Truth Tables, Table 1, SGL/DIF and Table 2 for address coding. (shown HIGH) Figure 3 shows the typical operation of the ADS7844’s digital interface. This diagram assumes that the source of the digital signals is a microcontroller or digital signal processor FIGURE 2. Simplified Diagram of the Analog Input. with a basic serial interface (note that the digital inputs are over-voltage tolerant up to 5.5V, regardless of +V ). Each CC cally 25pF). After the capacitor has been fully charged, there communication between the processor and the converter is no further input current. The rate of charge transfer from consists of eight clock cycles. One complete conversion can the analog source to the converter is a function of conversion be accomplished with three serial communications, for a rate. total of 24 clock cycles on the DCLK input. The first eight clock cycles are used to provide the control REFERENCE INPUT byte via the DIN pin. When the converter has enough information about the following conversion to set the input The external reference sets the analog input range. The multiplexer appropriately, it enters the acquisition (sample) ADS7844 will operate with a reference in the range of mode. After three more clock cycles, the control byte is 100mV to +V . Keep in mind that the analog input is the CC complete and the converter enters the conversion mode. At difference between the +IN input and the –IN input as shown this point, the input sample/hold goes into the hold mode. in Figure 2. For example, in the single-ended mode, a 1.25V The next twelve clock cycles accomplish the actual analog- reference, and with the COM pin grounded, the selected input to-digital conversion. A thirteenth clock cycle is needed for channel (CH0 - CH7) will properly digitize a signal in the the last bit of the conversion result. Three more clock cycles range of 0V to 1.25V. If the COM pin is connected to 0.5V, are needed to complete the last byte (DOUT will be LOW). the input range on the selected channel is 0.5V to 1.75V. These will be ignored by the converter. There are several critical items concerning the reference input and its wide voltage range. As the reference voltage is re- Control Byte duced, the analog voltage weight of each digital output code is also reduced. This is often referred to as the LSB (least Also shown in Figure 3 is the placement and order of the significant bit) size and is equal to the reference voltage control bits within the control byte. Tables III and IV give divided by 4096. Any offset or gain error inherent in the A/D detailed information about these bits. The first bit, the ‘S’ bit, converter will appear to increase, in terms of LSB size, as the must always be HIGH and indicates the start of the control reference voltage is reduced. For example, if the offset of a byte. The ADS7844 will ignore inputs on the DIN pin until given converter is 2 LSBs with a 2.5V reference, then it will the start bit is detected. The next three bits (A2 - A0) select typically be 10 LSBs with a 0.5V reference. In each case, the the active input channel or channels of the input multiplexer actual offset of the device is the same, 1.22mV. (see Tables I and II and Figure 2). ADS7844 10 www.ti.com SBAS100A

Bit 7 Bit 0 The SGL/DIF bit controls the multiplexer input mode: either (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) single-ended (HIGH) or differential (LOW). In single-ended S A2 A1 A0 — SGL/DIF PD1 PD0 mode, the selected input channel is referenced to the COM pin. In differential mode, the two selected inputs provide a TABLE III.Order of the Control Bits in the Control Byte. differential input. See Tables I and II and Figure 2 for more information. The last two bits (PD1 - PD0) select the power- down mode as shown in Table V. If both inputs are HIGH, BIT NAME DESCRIPTION the device is always powered up. If both inputs are LOW, the 7 S Start Bit. Control byte starts with first HIGH bit on device enters a power-down mode between conversions. DIN. A new control byte starts with every 15th clock cycle. When a new conversion is initiated, the device will resume 6 - 4 A2 - A0 Channel Select Bits. Along with the SGL/DIF bit, normal operation instantly—no delay is needed to allow the these bits control the setting of the multiplexer input device to power up and the very first conversion will be as detailed in Tables I and II. valid. 3 — Not Used. 16-Clocks per Conversion 2 SGL/DIF Single-Ended/Differential Select Bit. Along with bits A2 - A0, this bit controls the setting of the multiplexer The control bits for conversion n+1 can be overlapped with input as detailed in Tables I and II. conversion ‘n’ to allow for a conversion every 16 clock 1 - 0 PD1 - PD0 Power-Down Mode Select Bits. See Table V for cycles, as shown in Figure 4. This figure also shows possible details. serial communication occurring with other serial peripherals TABLE IV.Descriptions of the Control Bits within the between each byte transfer between the processor and the Control Byte. converter. This is possible provided that each conversion completes within 1.6ms of starting. Otherwise, the signal that has been captured on the input sample/hold may droop enough to affect the conversion result. In addition, the ADS7844 is fully powered while other serial communica- tions are taking place. CS t ACQ DCLK 1 8 1 8 1 8 DIN S A2 A1 A0 SDGIFL/ PD1 PD0 (START) Idle Acquire Conversion Idle BUSY DOUT 11 10 9 8 7 6 5 4 3 2 1 0 Zero Filled... (MSB) (LSB) FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port. CS DCLK 1 8 1 8 1 8 1 DIN S S CONTROL BITS CONTROL BITS BUSY DOUT 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 FIGURE 4. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK delay required with dedicated serial port. ADS7844 11 SBAS100A www.ti.com

PD1 PD0 Description SYMBOL DESCRIPTION MIN TYP MAX UNITS 0 0 Power-down between conversions. When each t Acquisition Time 1.5 µs conversion is finished, the converter enters a low ACQ t DIN Valid Prior to DCLK Rising 100 ns power mode. At the start of the next conversion, DS the device instantly powers up to full power. There tDH DIN Hold After DCLK HIGH 10 ns is no need for additional delays to assure full t DCLK Falling to DOUT Valid 200 ns DO operation and the very first conversion is valid. t CS Falling to DOUT Enabled 200 ns DV 0 1 Reserved for future use. t CS Rising to DOUT Disabled 200 ns TR 1 0 Reserved for future use. tCSS CS Falling to First DCLK Rising 100 ns t CS Rising to DCLK Ignored 0 ns 1 1 No power-down between conversions, device al- CSH ways powered. tCH DCLK HIGH 200 ns t DCLK LOW 200 ns CL TABLE V. Power-Down Selection. t DCLK Falling to BUSY Rising 200 ns BD t CS Falling to BUSY Enabled 200 ns BDV t CS Rising to BUSY Disabled 200 ns Digital Timing BTR TABLE VI. Timing Specifications (+V = +2.7V to 3.6V, Figure 5 and Tables VI and VII provide detailed timing for CC T = –40°C to +85°C, C = 50pF). the digital interface of the ADS7844. A LOAD SYMBOL DESCRIPTION MIN TYP MAX UNITS 15-Clocks per Conversion t Acquisition Time 900 ns ACQ Figure 6 provides the fastest way to clock the ADS7844. t DIN Valid Prior to DCLK Rising 50 ns DS This method will not work with the serial interface of most tDH DIN Hold After DCLK HIGH 10 ns microcontrollers and digital signal processors as they are tDO DCLK Falling to DOUT Valid 100 ns generally not capable of providing 15 clock cycles per serial tDV CS Falling to DOUT Enabled 70 ns t CS Rising to DOUT Disabled 70 ns transfer. However, this method could be used with field TR t CS Falling to First DCLK Rising 50 ns programmable gate arrays (FPGAs) or application specific CSS t CS Rising to DCLK Ignored 0 ns integrated circuits (ASICs). Note that this effectively in- CSH t DCLK HIGH 150 ns CH creases the maximum conversion rate of the converter be- t DCLK LOW 150 ns CL yond the values given in the specification tables, which t DCLK Falling to BUSY Rising 100 ns BD assume 16 clock cycles per conversion. t CS Falling to BUSY Enabled 70 ns BDV t CS Rising to BUSY Disabled 70 ns BTR TABLE VII. Timing Specifications (+V = +4.75V to CC +5.25V, T = –40°C to +85°C, C = 50pF). A LOAD CS t tCSS tCH CL tBD tBD tD0 tCSH DCLK t t DH DS DIN PD0 t t BDV BTR BUSY t t DV TR DOUT 11 10 FIGURE 5. Detailed Timing Diagram. CS DCLK 1 15 1 15 1 DIN S A2 A1 A0 SDGIFL/ PD1 PD0 S A2 A1 A0 SDGIFL/ PD1 PD0 S A2 A1 A0 BUSY DOUT 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2 FIGURE 6. Maximum Conversion Rate, 15-Clocks per Conversion. ADS7844 12 www.ti.com SBAS100A

Data Format The ADS7844 output data is in straight binary format as 1000 shown in Figure 7. This figure shows the ideal output code f = 16 • f for the given input voltage and does not include the effects CLK SAMPLE of offset, gain, or noise. µA) 100 nt ( e urr FS = Full-Scale Voltage = V C 1 LSB = VREF/4096 REF ply 10 fCLK = 2MHz p 1 LSB Su TA = 25°C +V = +2.7V 11...111 CC V = +2.5V REF 11...110 PD1 = PD0 = 0 1 e 11...101 1k 10k 100k 1M d ut Co fSAMPLE (Hz) p ut O 00...010 FIGURE 8. Supply Current vs Directly Scaling the Fre- 00...001 quency of DCLK with Sample Rate or Keeping 00...000 DCLK at the Maximum Possible Frequency. 0V FS – 1 LSB Input Voltage(1) (V) Note 1: Voltage at converter input, after 14 T = 25°C multiplexer: +IN–(–IN). See Figure 2. A 12 +VCC = +2.7V FIGURE 7. Ideal Input Voltages and Output Codes. VREF = +2.5V 10 f = 16 • f POWER DISSIPATION nt (µA) 8 PCDLK1 = PD0 S=A M0PLE e There are three power modes for the ADS7844: full power Curr 6 CS LOW (PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B), ply 4 (GND) p u and shutdown (SHDN LOW). The affects of these modes S 2 varies depending on how the ADS7844 is being operated. For 0 CS HIGH (+VCC) example, at full conversion rate and 16 clocks per conver- 0.09 0.00 sion, there is very little difference between full power mode 1k 10k 100k 1M and auto power-down. Likewise, if the device has entered f (Hz) SAMPLE auto power-down, a shutdown (SHDN LOW) will not lower power dissipation. FIGURE 9. Supply Current vs State of CS. When operating at full-speed and 16-clocks per conversion (as shown in Figure 4), the ADS7844 spends most of its time Operating the ADS7844 in auto power-down mode will acquiring or converting. There is little time for auto power- result in the lowest power dissipation, and there is no down, assuming that this mode is active. Thus, the differ- conversion time “penalty” on power-up. The very first ence between full power mode and auto power-down is conversion will be valid. SHDN can be used to force an negligible. If the conversion rate is decreased by simply immediate power-down. slowing the frequency of the DCLK input, the two modes remain approximately equal. However, if the DCLK fre- quency is kept at the maximum rate during a conversion, but LAYOUT conversion are simply done less often, then the difference between the two modes is dramatic. Figure 8 shows the For optimum performance, care should be taken with the difference between reducing the DCLK frequency (“scal- physical layout of the ADS7844 circuitry. This is particu- ing” DCLK to match the conversion rate) or maintaining larly true if the reference voltage is low and/or the conver- DCLK at the highest frequency and reducing the number of sion rate is high. conversion per second. In the later case, the converter The basic SAR architecture is sensitive to glitches or sudden spends an increasing percentage of its time in power-down changes on the power supply, reference, ground connec- mode (assuming the auto power-down mode is active). tions, and digital inputs that occur just prior to latching the If DCLK is active and CS is LOW while the ADS7844 is in output of the analog comparator. Thus, during any single auto power-down mode, the device will continue to dissipate conversion for an n-bit SAR converter, there are n “win- some power in the digital logic. The power can be reduced dows” in which large external transient voltages can easily to a minimum by keeping CS HIGH. The differences in affect the conversion result. Such glitches might originate supply current for these two cases are shown in Figure 9. from switching power supplies, nearby digital logic, and ADS7844 13 SBAS100A www.ti.com

high power devices. The degree of error in the digital output The ADS7844 architecture offers no inherent rejection of depends on the reference voltage, layout, and the exact noise or voltage variation in regards to the reference input. timing of the external event. The error can change if the This is of particular concern when the reference input is tied external event changes in time with respect to the DCLK to the power supply. Any noise and ripple from the supply input. will appear directly in the digital results. While high fre- quency noise can be filtered out as discussed in the previous With this in mind, power to the ADS7844 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should paragraph, voltage variation due to line frequency (50Hz or 60Hz) can be difficult to remove. be placed as close to the device as possible. In addition, a 1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may The GND pin should be connected to a clean ground point. be used to lowpass filter a noisy supply. In many cases, this will be the “analog” ground. Avoid The reference should be similarly bypassed with a 0.1µF connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a capacitor. Again, a series resistor and large capacitor can be ground trace directly from the converter to the power supply used to lowpass filter the reference voltage. If the reference entry point. The ideal layout will include an analog ground voltage originates from an op amp, make sure that it can plane dedicated to the converter and associated analog drive the bypass capacitor without oscillation (the series circuitry. resistor can help in this case). The ADS7844 draws very little current from the reference on average, but it does place larger demands on the reference circuitry over short periods of time (on each rising edge of DCLK during a conversion). ADS7844 14 www.ti.com SBAS100A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS7844E ACTIVE SSOP DBQ 20 50 Green (RoHS NIPDAU Level-2-260C-1 YEAR ADS7844E & no Sb/Br) ADS7844E/2K5 ACTIVE SSOP DBQ 20 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS7844E & no Sb/Br) ADS7844E/2K5G4 ACTIVE SSOP DBQ 20 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS7844E & no Sb/Br) ADS7844EB ACTIVE SSOP DBQ 20 50 Green (RoHS NIPDAU Level-2-260C-1 YEAR ADS7844E & no Sb/Br) B ADS7844EB/2K5 ACTIVE SSOP DBQ 20 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR ADS7844E & no Sb/Br) B ADS7844EBG4 ACTIVE SSOP DBQ 20 50 Green (RoHS NIPDAU Level-2-260C-1 YEAR ADS7844E & no Sb/Br) B ADS7844EG4 ACTIVE SSOP DBQ 20 50 Green (RoHS NIPDAU Level-2-260C-1 YEAR ADS7844E & no Sb/Br) ADS7844N ACTIVE SSOP DB 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR ADS7844N & no Sb/Br) ADS7844N/1K ACTIVE SSOP DB 20 1000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS7844N & no Sb/Br) ADS7844N/1KG4 ACTIVE SSOP DB 20 1000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS7844N & no Sb/Br) ADS7844NB ACTIVE SSOP DB 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR ADS7844N & no Sb/Br) B ADS7844NB/1K ACTIVE SSOP DB 20 1000 Green (RoHS NIPDAU Level-2-260C-1 YEAR ADS7844N & no Sb/Br) B ADS7844NB/1KG4 ACTIVE SSOP DB 20 1000 Green (RoHS NIPDAU Level-2-260C-1 YEAR ADS7844N & no Sb/Br) B ADS7844NBG4 ACTIVE SSOP DB 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR ADS7844N & no Sb/Br) B ADS7844NG4 ACTIVE SSOP DB 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR ADS7844N & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS7844E/2K5 SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 ADS7844EB/2K5 SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 ADS7844N/1K SSOP DB 20 1000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 ADS7844NB/1K SSOP DB 20 1000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS7844E/2K5 SSOP DBQ 20 2500 367.0 367.0 38.0 ADS7844EB/2K5 SSOP DBQ 20 2500 367.0 367.0 38.0 ADS7844N/1K SSOP DB 20 1000 367.0 367.0 38.0 ADS7844NB/1K SSOP DB 20 1000 367.0 367.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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