® ADS7835 For most current data sheet and other product information, visit www.burr-brown.com 12-Bit, High-Speed, Low Power Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION l 500kHz THROUGHPUT RATE The ADS7835 is a 12-bit, sampling analog-to-digi- l 2.5V INTERNAL REFERENCE tal converter (A/D) complete with sample-and-hold (S/H), internal 2.5V reference, and synchronous l LOW POWER: 17.5mW serial interface. Typical power dissipation is 17.5mW l SINGLE SUPPLY +5V OPERATION at a 500kHz throughput rate. The device can be l SERIAL INTERFACE placed into a power-down mode which reduces dis- l GUARANTEED NO MISSING CODES sipation to just 2.5mW. The input range is –VREF to +V , and the internal reference can be overdriven l MSOP-8 REF by an external voltage. l – V INPUT RANGE REF Low power, small size, and high speed make the ADS7835 ideal for battery-operated systems such APPLICATIONS as wireless communication devices, portable multi- channel data loggers, and spectrum analyzers. The l BATTERY-OPERATED SYSTEMS serial interface also provides low cost isolation for l DIGITAL SIGNAL PROCESSING remote data acquisition. The ADS7835 is avail- able in an MSOP-8 package and is guaranteed over l HIGH-SPEED DATA ACQUISITION the –40(cid:176) C to +85(cid:176) C temperature range. l WIRELESS COMMUNICATION SYSTEMS CLK SAR CONV 2kW – 2.5V CDAC Serial Input Interface DATA 2kW S/H Amp Comparator Buffer Internal +2.5V Ref V REF 10kW – 30% International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® ©1998 Burr-Brown Corporation PDS-11478B ADPSrin7ted8 i3n U5.S.A.May, 2000 SBAS102

SPECIFICATIONS At T = –40(cid:176)C to +85(cid:176)C, +V = +5V, f = 500kHz, f = 16 • f , and internal +2.5V reference, unless otherwise specified. A CC SAMPLE CLK SAMPLE ADS7835E ADS7835EB PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 12 [ Bits ANALOG INPUT(1) Input Voltage Range – 2.5V with the 2.5V –V +V [ [ V REF REF Internal Reference Input Capacitance 25 [ pF Input Resistance During Conversion (CONV = LOW) 2 [ kW SYSTEM PERFORMANCE No Missing Codes 12 [ Bits Integral Linearity – 1 – 2 – 0.5 – 1 LSB(2) Differential Linearity – 0.8 – 0.5 – 1 LSB Bipolar Offset Error – 2 – 10 – 1 – 5 LSB Positive Fulll-Scale Error(3) At 25(cid:176)C – 12 – 20 – 7 – 12 LSB –40(cid:176)C to +85(cid:176)C – 35 – 25 LSB Negative Full-Scale Error(3) At 25(cid:176)C – 12 – 20 – 7 – 12 LSB –40(cid:176)C to +85(cid:176)C – 35 – 25 LSB Noise 200 [ m Vrms Power Supply Rejection Ratio Worst-Case D , +V = 5V – 5% 0.3 [ LSB CC SAMPLING DYNAMICS Conversion Time 1.625 [ m s Acquisition Time 0.350 [ m s Throughput Rate 500 [ kHz Aperture Delay 5 [ ns Aperture Jitter 30 [ ps Step Response 375 [ ns DYNAMIC CHARACTERISTICS Signal-to-Noise Ratio V = 5Vp-p at 10kHz 72 [ dB IN Total Harmonic Distortion(4) V = 5Vp-p at 10kHz –78 –72 –82 –75 dB IN Signal-to-(Noise+Distortion) V = 5Vp-p at 10kHz 68 70 70 72 dB IN Spurious Free Dynamic Range V = 5Vp-p at 10kHz 72 78 75 82 dB IN REFERENCE OUTPUT Voltage I = 0 2.475 2.50 2.525 2.48 [ 2.52 V OUT Source Current(5) Static Load 50 [ m A Line Regulation 4.75V £ V £ 5.25V 0.2 [ mV CC REFERENCE INPUT Range 2.3 2.9 [ [ V Resistance(6) To Internal Reference Voltage 10 [ kW DIGITAL INPUT/OUTPUT Logic Family CMOS [ Logic Levels: V I £ +5m A 3.0 +V + 0.3 [ [ V IH IH CC V I £ +5m A –0.3 0.8 [ [ V IL IL V I = –500m A 3.5 [ V OH OH V I = 500m A 0.4 [ V OL OL Data Format Binary Two’s Complement [ POWER SUPPLY REQUIREMENT +V Specified Performance 4.75 5.25 [ [ V CC Quiescent Current f = 500kHz 3.5 [ mA SAMPLE Power-Down 0.5 [ mA Power Dissipation 17.5 30 [ [ mW Power-Down 2.5 [ mW TEMPERATURE RANGE Specified Performance –40 +85 [ [ (cid:176)C [ Specifications same as ADS7835E. NOTES: (1) Ideal input span, does not include gain or offset error. (2) LSB means Least Significant Bit, with V equal to +2.5V, one LSB is 1.22mV. (3) Measured REF relative to an ideal positive full scale of 2.499V for positive full-scale error. Measured relative to an ideal negative full scale of –2.499V for negative full-scale error. (4) Calculated on the first nine harmonics of the input frequency. (5) If the internal reference is required to source current to an external load, the reference voltage will change due to the internal 10kW resistor. (6) Can vary – 30%. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS7835 2

ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC +V to GND............................................................................–0.3V to 6V DISCHARGE SENSITIVITY CC Analog Inputs to GND.............................................................–5.3 to +5.3 Digital Inputs to GND...............................................–0.3V to (V + 0.3V) CC Electrostatic discharge can cause damage ranging from per- Power Dissipation..........................................................................325mW Maximum Junction Temperature...................................................+150(cid:176)C formance degradation to complete device failure. Burr-Brown Operating Temperature Range.........................................–40(cid:176)C to +85(cid:176)C Corporation recommends that all integrated circuits be Storage Temperature Range..........................................–65(cid:176)C to +150(cid:176)C handled and stored using appropriate ESD protection meth- Lead Temperature (soldering, 10s)...............................................+300(cid:176)C ods. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum condi- ESD damage can range from subtle performance degrada- tions for extended periods may affect device reliability. tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small PIN CONFIGURATION parametric changes could cause the device not to meet published specifications. Top View V 1 8 +V REF CC A 2 7 CLK IN ADS7835 GND 3 6 DATA GND 4 5 CONV MSOP-8 PIN ASSIGNMENTS PIN NAME DESCRIPTION 1 V Reference Output. Decouple to ground with a 0.1m F ceramic capacitor and a 2.2m F tantalum capacitor. REF 2 A – 2.5V Input IN 3 GND Ground 4 GND Ground 5 CONV Convert Input. Controls the sample/hold mode, start of conversion, start of serial data transfer, type of serial transfer, and power- down mode. See the Digital Interface section for more information. 6 DATA Serial Data Output. The 12-bit conversion result is serially transmitted most significant bit first with each bit valid on the rising edge of CLK. By properly controlling the CONV input, it is possibly to have the data transmitted least significant bit first. See the Digital Interface section for more information. 7 CLK Clock Input. Synchronizes the serial data transfer and determines conversion speed. 8 +V Power Supply. Decouple to ground with a 0.1m F ceramic capacitor and a 10m F tantalum capacitor. CC PACKAGE/ORDERING INFORMATION MAXIMUM MAXIMUM INTEGRAL DIFFERENTIAL LINEARITY LINEARITY PACKAGE SPECIFICATION ERROR ERROR DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT (LSB) (LSB) PACKAGE NUMBER(1) RANGE MARKING(2) NUMBER(3) MEDIA ADS7835E – 2 N/S(4) MSOP-8 337 –40(cid:176)C to +85(cid:176)C B35 ADS7835E/250 Tape and Reel " " " " " " " ADS7835E/2K5 Tape and Reel ADS7835EB – 1 – 1 MSOP-8 337 –40(cid:176)C to +85(cid:176)C B35 ADS7835EB/250 Tape and Reel " " " " " " " ADS7835EB/2K5 Tape and Reel ADS7835P – 2 N/S(4) Plastic DIP-8 006 –40(cid:176)C to +85(cid:176)C ADS7835P ADS7835P Rails ADS7835PB – 1 – 1 " " " ADS7835PB ADS7835PB Rails NOTE: (1) For detail drawing and dimension table, please see end of data sheet or Package Drawing File on Web. (2) Performance Grade information is marked on the reel. (3) Models with a slash(/) are available only in Tape and reel in quantities indicated (e.g. /250 indicates 250 units per reel, /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of ”ADS7835E/2K5“ will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to the www.burr-brown.com web site under Applications and Tape and Reel Orientation and Dimensions. (4) N/S = Not Specified, typical only. However, 12-Bits no missing codes is guaranteed over temperature. ® 3 ADS7835

TYPICAL PERFORMANCE CURVES At T = +25(cid:176)C, +V = +5V, f = 500kHz, f = 16 • f , and internal +2.5V reference, unless otherwise specified. A CC SAMPLE CLK SAMPLE CHANGE IN FULL-SCALE ERRORS CHANGE IN BIPOLAR OFFSET ERROR vs TEMPERATURE vs TEMPERATURE 1.0 0.6 Negative Full-Scale Error 0.4 0.0 B) B) 0.2 S S C (L –1.0 C (L 0.0 °+25 –2.0 °+25 –0.2 m m Delta fro –3.0 Positive Full-Scale Error Delta fro ––00..46 –4.0 –0.8 –1.0 –5.0 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) POWER-DOWN SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 470 3.8 A) 460 3.7 µ upply Current ( 444543000 Current (mA) 333...654 fSAMPLE = 500kHz n S 420 ply 3.3 w p wer-Do 410 Su 3.2 fSAMPLE = 125kHz o 400 3.1 P 390 3.0 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) CHANGE IN INTEGRAL and DIFFERENTIAL LINEARITY SUPPLY CURRENT vs SAMPLE RATE vs SAMPLE RATE 4.0 0.5 3.9 B) 0.4 S ent (mA) 333...876 500kHz (L 000...321 ChLainnegaer iitny I(nLtSeBg)ral Supply Curr 333...543 om f = SAMPLE ––000...012 Change in Differential 3.2 a fr –0.3 Linearity (LSB) 3.1 Delt –0.4 3.0 –0.5 100 200 300 400 500 600 700 0 100 200 300 400 500 600 700 Sample Rate (kHz) Sample Rate (kHz) ® ADS7835 4

TYPICAL PERFORMANCE CURVES (Cont.) At T = +25(cid:176)C, +V = +5V, f = 500kHz, f = 16 • f , and internal +2.5V reference, unless otherwise specified. A CC SAMPLE CLK SAMPLE CHANGE END-POINT ERRORS PEAK-TO-PEAK NOISE vs EXTERNAL REFERENCE VOLTAGE vs EXTERNAL REFERENCE VOLTAGE 4.0 0.90 3.0 0.85 B) 2.5V (LS 21..00 Negative Full-Scale Error se (LSB) 00..8705 m V = REF –01..00 Peak Noi 00/.7605 o –2.0 o- Delta fr –3.0 Paonsdi tBiviep oFlaurll -OSfcfsaelet EErrrroorr Peak-t 0.60 –4.0 0.55 –5.0 0.50 2.2 2.4 2.6 2.8 3.0 2 2.1 2.2 2.3 2.4 2.5 External Reference Voltage (V) External Reference Voltage (V) POWER SUPPLY REJECTION RATIO FREQUENCY SPECTRUM vs POWER SUPPLY RIPPLE FREQUENCY (4096 Point FFT; f = 977Hz, –0.2dB) IN 30 0 V) mV/ 25 –20 o ( Rati 20 B) –40 ply Rejection 1150 Amplitude (d ––8600 p u S er 5 –100 w o P 0 –120 1 10 100 1k 10k 100k 1M 0 50 100 150 200 250 Power Supply Ripple Frequency (Hz) Frequency (kHz) FREQUENCY SPECTRUM FREQUENCY SPECTRUM (4096 Point FFT; f = 9.77kHz, –0.2dB) (4096 Point FFT; f = 99.7kHz, –0.2dB) IN IN 0 0 –20 –20 B) –40 B) –40 d d e ( e ( ud –60 ud –60 plit plit m m A –80 A –80 –100 –100 –120 –120 0 50 100 150 200 250 0 50 100 150 200 250 Frequency (kHz) Frequency (kHz) ® 5 ADS7835

TYPICAL PERFORMANCE CURVES (Cont.) At T = +25(cid:176)C, +V = +5V, f = 500kHz, f = 16 • f , and internal +2.5V reference, unless otherwise specified. A CC SAMPLE CLK SAMPLE SIGNAL-TO-NOISE and SPURIOUS FREE DYNAMIC RANGE and SIGNAL-TO-(NOISE + DISTORTION) TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY vs INPUT FREQUENCY 75 90 SNR 73 85 B) B) AD (d 71 HD (d 80 SFDR SIN 69 SINAD d T and R an 75 THD[ R 67 D N F S S 70 65 [ First nine harmonics of the input frequency 63 65 1 10 100 1000 1 10 100 1000 Input Frequency (kHz) Input Frequency (kHz) CHANGE IN SIGNAL-TO-NOISE and CHANGE IN SPURIOUS FREE DYNAMIC RANGE SIGNAL-TO-(NOISE+DISTORTION) and TOTAL HARMONIC DISTORTION vs TEMPERATURE vs TEMPERATURE 0.5 2.0 C (dB) 0.4 fIN = 10kHz, –0.2dB C (dB) 1.5 fIN = 10kHz, –0.2dB °m +25 00..32 °m +25 1.0 D Deltas fro –000...101 SNR D Deltas fro –000...505 THD* NA –0.2 TH d SI –0.3 SINAD and –1.0 SFDR SNR an ––00..45 SFDR ––12..50 o* fF tihrset nininpeu th farermquoenniccsy –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) CHANGE IN BIPOLAR OFFSET ERROR vs SAMPLE RATE 1.0 0.8 A) m z ( 0.6 H k 0 0 0.4 5 m o a fr 0.2 elt D 0.0 –0.2 0 100 200 300 400 500 600 700 Sample Rate (kHz) ® ADS7835 6

THEORY OF OPERATION the device is in the sample or hold mode. When sampling, the input has a 4kW input impedance to the reference. The The ADS7835 is a high speed Successive Approximation source of the analog input voltage must be able to charge the Register (SAR) analog-to-digital converter (A/D) with an input impedance (typically 25pF || 1kW) to a 12-bit settling internal 2.5V bandgap reference. The architecture is based level within the same period. This can be as little as 350ns on capacitive redistribution which inherently includes a S/H in some operating modes. When the converter is in the hold function. The converter is fabricated on a 0.6m CMOS mode, the input impedance switches to approximately 2kW process. See Figure 1 for the basic operating circuit for the to ground. ADS7835. Care must be taken regarding the input voltage on the A IN The ADS7835 requires an external clock to run the conver- pin. The input signal should remain within –5.3V and +5.3V sion process. This clock can vary between 200kHz (12.5kHz (with a 5V supply) to avoid damaging the converter. throughput) and 8MHz (500kHz throughput). The duty cycle of the clock is unimportant as long as the minimum HIGH REFERENCE and LOW times are at least 50ns and the clock period is at The reference voltage on the V pin directly sets the full- least 125ns. The minimum clock frequency is set by the REF scale range of the analog input. The ADS7835 can operate leakage on the capacitors internal to the ADS7835. with a reference in the range of 2.3V to 2.9V, for a full-scale The analog input to the ADS7835 is single-ended. The range of – 2.3V to – 2.9V. ADS7835 provides a true bipolar input where the input will swing below ground. When using the internal 2.5V refer- The voltage at the VREF pin is internally buffered and this ence the input range is – 2.5V (within – 20mV for the low buffer drives the CDAC portion of the converter. This is grade and – 12mV for the high grade). When using an important because the buffer greatly reduces the dynamic external reference the input range is –V to +V . The load placed on the reference source. However, the voltage at REF REF ADS7835 will accept an external reference with a range of VREF will still contain some noise and glitches from the SAR 2.3V to 2.9V. conversion process. These can be reduced by carefully bypassing the V pin to ground as outlined in the sections The digital result of the conversion is provided in a serial REF that follow. manner, synchronous to the CLK input. The provided result is Most Significant Bit (MSB) first and represents the result of the conversion currently in progress—there is no pipeline INTERNAL REFERENCE delay. By properly controlling the CONV and CLK inputs, The ADS7835 contains an on-board 2.5V reference, result- it is possible to obtain the digital result Least Significant Bit ing in a –2.5V to +2.5V input range on the analog input. The (LSB) first. Specification table gives the various specifications for the internal reference. This reference can be used to supply a small amount of source current to an external load, but the ANALOG INPUT load should be static. Due to the internal 10kW resistor, a The analog input (pin 2) of the ADS7835 is connected to a dynamic load will cause variations in the reference voltage, 2k W x 2kW voltage divider. This divider allows the ADS7835 and will dramatically affect the conversion result. Note that to accept bipolar inputs while operating from a single 5V even a static load will reduce the internal reference voltage supply. The divider is connected to the output buffer of the seen at the buffer input. The amount of reduction depends on internal +2.5V supply. When the input is at +full-scale the load and the actual value of the internal “10kW ” resistor. (+2.5V), the voltage at the input to the CDAC (Capacitive The value of this resistor can vary by – 30%. Digital-to-Analog Converter) is also +2.5V resulting in negligible input current. When the input is at –full-scale The VREF pin should be bypassed with a 0.1m F capacitor (–2.5V), the voltage at the input of the CDAC is 0V placed as close as possible to the ADS7835 package. In resulting in 1.25mA of current being sourced out of the addition, a 2.2m F tantalum capacitor should be used in input pin. It is recommended that a buffer be placed parallel with the ceramic capacitor. Placement of this ca- between the analog input signal and the input of the ADS7835. pacitor, while not critical to performance, should be placed as close to the package as possible. The input impedance of the ADS7835 depends on whether +5V + + 2.2µF 0.1µF ADS7835 0.1µF 10µF 1 V +V 8 REF CC – 2.5V 2 A CLK 7 Serial Clock Analog Input IN from 3 GND DATA 6 Serial Data Microcontroller or DSP 4 GND CONV 5 Convert Start FIGURE 1. Basic Operation of the ADS7835. ® 7 ADS7835

the CLK may be kept LOW or HIGH. EXTERNAL REFERENCE The asynchronous nature of CONV to CLK raises some The internal reference is connected to the V pin and to the interesting possibilities, but also some design consider- REF internal buffer via a 10kW series resistor. Thus, the reference ations. Figure 3 shows that CONV has timing restraints in voltage can easily be overdriven by an external reference relation to CLK (t and t ). However, if these times CKCH CKCS voltage. The voltage range for the external voltage is 2.3V are violated (which could happen if CONV is completely to 2.9V, corresponding to an analog input range of 2.3V to asynchronous to CLK), the converter will perform a conver- 2.9V in both cases. sion correctly, but the exact timing of the conversion is indeterminate. Since the setup and hold time between CONV While the external reference will not source significant current into the V pin, it does have to drive the 10kW and CLK has been violated in this example, the start of REF conversion could vary by one clock cycle. (Note that the series resistor that is terminated into the 2.5V internal start of conversion can be detected by using a pull-up reference (the exact value of the resistor will vary up to – 30% from part to part). In addition, the V pin should resistor on DATA. When DATA drops out of high imped- REF still be bypassed to ground with at least a 0.1m F ceramic ance and goes LOW, the conversion has started and that capacitor (placed as close to the ADS7835 as possible). The reference will have to be stable with this capacitive load. SYMBOL DESCRIPTION MIN TYP MAX UNITS Depending on the particular reference and A/D conversion t Acquisition Time 350 ns ACQ speed, additional bypass capacitance may be required, such t Conversion Time 1.625 m s CONV as the 2.2m F tantalum capacitor shown in Figure 1. tCKP Clock Period 125 5000 ns t Clock LOW 50 ns Reasons for choosing an external reference over the internal CKL t Clock HIGH 50 ns reference vary, but there are two main reasons. One is to CKH t Clock Falling to Current Data 5 15 ns CKDH achieve a given input range. The other is to provide greater Bit No Longer Valid stability over temperature. (The internal reference is typi- t Clock Falling to Next Data Valid 30 50 ns CKDS cally 20ppm/(cid:176) C which translates into a full-scale drift of t CONV LOW 40 ns CVL roughly one output code for every 12(cid:176) C. This does not take tCVH CONV HIGH 40 ns into account other sources of full-scale drift.) If greater tCKCH CONV Hold after Clock Falls(1) 10 ns t CONV Setup to Clock Falling(1) 10 ns stability over temperature is needed, then an external refer- CKCS t Clock Falling to DATA Enabled 20 50 ns ence with lower temperature drift will be required. CKDE t Clock Falling to DATA 70 100 ns CKDD High Impedance DIGITAL INTERFACE tCKSP Clock Falling to Sample Mode 5 ns t Clock Falling to Power-Down Mode 50 ns Figure 2 shows the serial data timing and Figure 3 shows the CKPD t CONV Falling to Hold Mode 5 ns basic conversion timing for the ADS7835. The specific CVHD (Aperture Delay) timing numbers are listed in Table I. There are several t CONV Rising to Sample Mode 5 ns CVSP important items in Figure 3 which give the converter addi- t CONV Rising to Full Power-up 50 ns CVPU tional capabilities over typical 8-pin converters. First, the t CONV Changing State to DATA 70 100 ns CVDD High Impedance transition from sample mode to hold mode is synchronous to t CONV Changing State to 50 ns the falling edge of CONV and is not dependent on CLK. CVPD Power-Down Mode Second, the CLK input is not required to be continuous t CONV Falling to Start of CLK 5 m s DRP during the sample mode. After the conversion is complete, (for hold droop < 0.1 LSB) Note: (1) This timing is not required under some situations. See text for more information. TABLE I. Timing Specifications (T = –40(cid:176) C to +85(cid:176) C, A C = 30pF). LOAD t CKP t t CKH CKL CLK t CKDS t CKDH DATA FIGURE 2. Serial Data and Clock Timing. ® ADS7835 8

clock cycle is the first of the conversion.) tween conversions. In addition, if CONV is completely asynchronous to CLK Figure 4 shows the typical method for placing the A/D into and CLK is continuous, there is the possibility that CLK will the power-down mode. If CONV is kept LOW during the transition just prior to CONV going LOW. If this occurs conversion and is LOW at the start of the 13th clock cycle, faster than the 10ns indicated by t , there is a chance that the device enters the power-down mode. It remains in this CKCH some digital feedthrough may be coupled onto the hold mode until the rising edge of CONV. Note that CONV must capacitor. This could cause a small offset error for that be HIGH for at least t in order to sample the signal ACQ particular conversion. properly as well as to power-up the internal nodes. Thus, there are two basic ways to operate the ADS7835. There are two different methods for clocking the ADS7835. CONV can be synchronous to CLK and CLK can be con- The first involves scaling the CLK input in relation to the tinuous. This would be the typical situation when interfacing conversion rate. For example, an 8MHz input clock and the the converter to a digital signal processor. The second timing shown in Figure 3 results in a 500kHz conversion method involves having CONV asynchronous to CLK and rate. Likewise, a 1.6MHz clock would result in a 100kHz gating the operation of CLK (a non-continuous clock). This conversion rate. The second method involves keeping the method would be more typical of an SPI-like interface on a clock input as close to the maximum clock rate as possible microcontroller. This method would also allow CONV to be and starting conversions as needed. This timing is similar to generated by a trigger circuit and to initiate (after some that shown in Figure 4. As an example, a 50kHz conversion delay) the start of CLK. These two methods are covered rate would require 160 clock periods per conversion instead under the DSP Interfacing and SPI Interfacing sections of of the 16 clock periods used at 500kHz. this data sheet. The main distinction between the two is the amount of time that the ADS7835 remains in power-down. In the first mode, POWER-DOWN TIMING the converter only remains in power-down for a small number of clock periods (depending on how many clock The conversion timing shown in Figure 3 does not result in periods there are per each conversion). As the conversion the ADS7835 going into the power-down mode. If the rate scales, the converter always spends the same percentage conversion rate of the device is high (approaching 500kHz), of time in power-down. Since less power is drawn by the there is very little power that can be saved by using the digital logic, there is a small decrease in power consump- power-down mode. However, since the power-down mode tion, but it is very slight. This effect can be seen in the incurs no conversion penalty (the very first conversion is valid) at lower sample rates, significant power can be saved by allowing the device to go into power-down mode be- t t CVL CVCK CONV t CKCS t CKCH CLK 14 15 16 1 2 3 4 11 12 13 14 15 16 1 (1) t t CKDE CKDD D11 D0 DATA D10 D9 D2 D1 (MSB) (LSB) t ACQ t t CVHD CKSP SAMPLE/HOLD SAMPLE HOLD SAMPLE HOLD MODE (2) t CONV INTERNAL CONVERSION IDLE CONVERSION IN PROGRESS IDLE(3) STATE NOTES: (1) Clock periods 14 and 15 are shown for clarity, but are not required for proper operation of the ADS7835, provided that the minimum t time is met. The CLK input may remain HIGH or LOW during this period. (2) The transition from sample mode to hold ACQ mode occurs on the falling edge of CONV. This transition is not dependent on CLK. (3) The device remains fully powered when operated as shown. If the sample time is longer than 3 clock periods, power consumption can be reduced by allowing the device to enter a power-down mode. See the Power-Down Timing section for more information. FIGURE 3. Basic Conversion Timing. ® 9 ADS7835

CONV CLK 1 2 3 12 13 D11 D0 DATA (MSB) D10 D1 (LSB) t t CVSP ACQ SAMPLE/HOLD SAMPLE HOLD SAMPLE HOLD MODE (3) INTERNAL CONVERSION IDLE CONVERSION IN PROGRESS IDLE STATE t t CKPD CVPU POWER MODE FULL POWER LOW POWER FULL POWER (1) (2) NOTES: (1) The low power mode (“power-down”) is entered when CONV remains LOW during the conversion and is still LOW at the start of the 13th clock cycle. (2) The low power mode is exited when CONV goes HIGH. (3) When in power-down, the transition from hold mode to sample mode is initiated by CONV going HIGH. FIGURE 4. Power-Down Timing. t CVH CONV t CKCH CLK 1 2 3 12 13 14 23 24 t CKCS t CVDD D11 D0 D11 DATA (MSB) D10 D1 (LSB) D1 D10 (MSB) LOW... (1) (2) SAMPLE/HOLD MODE SAMPLE HOLD INTERNAL CONVERSION IDLE CONVERSION IN PROGRESS IDLE STATE t CVPD POWER MODE FULL POWER LOW POWER (3) NOTES: (1) The serial data can be transmitted LSB-first by pulling CONV LOW during the 13th clock cycle. (2) After the MSB has been transmitted, the DATA output pin will remain LOW until CONV goes HIGH. (3) When CONV is taken LOW to initiate the LSB first transfer, the converter enters the power-down mode. FIGURE 5. Serial Data “LSB-First” Timing. typical performance curve “Supply Current vs Sample Rate.” in power-down an increasing percentage of time. This re- duces total power consumption by a considerable amount. In contrast, the second method (clocking at a fixed rate) For example, a 50kHz conversion rate results in roughly means that each conversion takes X clock cycles. As the 1/10 of the power (minus the reference) that is used at a time between conversions get longer, the converter remains ® ADS7835 10

500kHz conversion rate. HIGH. SHORT-CYCLE TIMING POWER WITH POWER WITH The conversion currently in progress can be “short-cycled” fSAMPLE CLK = 16 • fSAMPLE CLK = 8MHz with the technique shown in Figure 6. This term means that 500kHz 17.5mW 17.5mW the conversion will terminate immediately, before all 12 bits 250kHz 16.5mW 13.5mW have been decided. This can be a very useful feature when 100kHz 15.5mW 10.5mW a resolution of 12 bits is not needed. An example would be TABLE II. Power Consumption versus CLK Input. when the converter is being used to monitor an input voltage until some condition is met. At that time, the full resolution of the converter would then be used. Short-cycling the Table II offers a look at the two different modes of operation conversion can result in a faster conversion rate or lower and the difference in power consumption. power dissipation. LSB-FIRST DATA TIMING There are several very important items shown in Figure 6. Figure 5 shows a method to transmit the digital result in a The conversion currently in progress is terminated when LSB format. This mode is entered when CONV is pulled CONV is taken HIGH during the conversion and then taken HIGH during the conversion (before the end of the 12th LOW prior to t before the start of the 13th clock cycle. CKCH clock) and then pulled LOW during the 13th clock (when Note that if CONV goes LOW during the 13th clock cycle, D0, the LSB, is being transmitted). The next 11 clocks then the LSB-first mode will be entered (Figure 5). Additionally, repeat the serial data, but in an LSB-first format. The when CONV goes LOW, the DATA output immediately converter enters the power-down mode during the 13th transitions to high impedance. If the output bit that is present clock and resumes normal operation when CONV goes during that clock period is needed, CONV must not go LOW until the bit has been properly latched into the receiving (1) tCVL CONV t CVH CLK 1 2 3 4 5 6 7 t CVDD D11 DATA (MSB) D10 D9 D8 D7 D6 SAMPLE/HOLD SAMPLE HOLD MODE INTERNAL CONVERSION IDLE CONVERSION IN PROGRESS IDLE STATE t CVPD POWER MODE FULL POWER LOW POWER NOTE: (1) The conversion currently in progress can be stopped by pulling CONV LOW during the conversion. This must occur at least t prior to the start of the 13th clock cycle. The DATA output pin will tri-state and the device will enter the power-down CKCS mode when CONV is pulled LOW. FIGURE 6. Short-Cycle Timing. ® 11 ADS7835

logic. Figure 7 shows a timing diagram that might be used with a typical digital signal processor such as a TI DSP. For the Buffered Serial Port (BSP) on the TMS320C54X family, DATA FORMAT CONV would tied to BFSX, CLK would be tied to BCLKX, The ADS7835 output data is in Binary Two’s Complement and DATA would be tied to BDR. format as shown in Table III. This table shows the ideal output code for the given input voltage and does not include SPI/QSPI INTERFACING DESCRIPTION ANALOG INPUT DIGITAL OUTPUT Figure 8 shows the timing diagram for a typical Serial Full-Scale Input BINARY TWO’S Range –V to +V (1) COMPLEMENT Peripheral Interface (SPI) or Queued Serial Peripheral Inter- REF REF Least Significant Bit BINARY HEX face (QSPI). Such interfaces are found on a number of (LSB)(2) (–V to +V )/4096 CODE CODE REF REF microcontrollers from various manufacturers. CONV would +Full Scale 2.49878V 0111 1111 1111 7FF be tied to a general purpose I/O pin (SPI) or to a PCX pin Mid-Scale 0V 0000 0000 0000 000 Mid-Scale –1LSB –0.00122V 1111 1111 1111 FFF (QSPI), CLK would be tied to the serial clock, and DATA –Full Scale –2.49878V 1000 0000 0000 800 would be tied to the serial input data pin such as MISO NOTES: (1) –2.5V to +2.5V when the internal reference is used. (2) 1.22mV (Master In Slave Out). with a 2.5V reference. Note the time t shown in Figure 8. This represents the TABLE III. Ideal Input Voltages and Output Codes. DRP maximum amount of time between CONV going LOW and the start of the conversion clock. Since CONV going LOW the effects of offset, gain, or noise. places the S/H in the hold mode and because the hold capacitor loses charge over time, there is a requirement that DSP INTERFACING time t be met as well as the maximum clock period DRP CONV CLK 15 16 1 2 3 12 13 14 15 16 1 2 3 4 D11 D0 D11 DATA (MSB) D10 D1 (LSB) (MSB) D10 D9 FIGURE 7. Typical DSP Interface Timing. t t DRP ACQ CONV CLK 1 2 3 4 13 14 15 16 1 2 3 D11 D0 D11 DATA D10 D1 (MSB) (LSB) (MSB) FIGURE 8. Typical SPI/QSPI Interface Timing. ® ADS7835 12

(t ). larger capacitor and a 5W or 10W series resistor may be used CKP to lowpass filter a noisy supply. LAYOUT The ADS7835 draws very little current from an external reference on average as the reference voltage is internally For optimum performance, care should be taken with the buffered. However, glitches from the conversion process physical layout of the ADS7835 circuitry. This is particu- appear at the V input and the reference source must be REF larly true if the CLK input is approaching the maximum able to handle this. Whether the reference is internal or input rate. external, the V pin should be bypassed with a 0.1m F REF The basic SAR architecture is sensitive to glitches or sudden capacitor. An additional larger capacitor may also be used, changes on the power supply, reference, ground connec- if desired. If the reference voltage is external and originates tions, and digital inputs that occur just prior to latching the from an op amp, make sure that it can drive the bypass output of the analog comparator. Thus, during any single capacitor or capacitors without oscillation. conversion for an n-bit SAR converter, there are n “win- The GND pin should be connected to a clean ground point. dows” in which large external transient voltages can easily In many cases, this will be the “analog” ground. Avoid affect the conversion result. Such glitches might originate connections which are too near the grounding point of a from switching power supplies, nearby digital logic, and microcontroller or digital signal processor. If needed, run a high power devices. The degree of error in the digital output ground trace directly from the converter to the power supply depends on the reference voltage, layout, and the exact entry point. The ideal layout will include an analog ground timing of the external event. The error can change if the plane dedicated to the converter and associated analog external event changes in time with respect to the CLK circuitry. input. With this in mind, power to the ADS7835 should be clean and well bypassed. A 0.1m F ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1m F to 10m F capacitor is recommended. If needed, an even ® 13 ADS7835

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS7835E/250 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 B35 & no Sb/Br) ADS7835E/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 B35 & no Sb/Br) ADS7835E/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR B35 & no Sb/Br) ADS7835E/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR B35 & no Sb/Br) ADS7835EB/250 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR B35 & no Sb/Br) ADS7835EB/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR B35 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS7835E/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7835E/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7835EB/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS7835E/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS7835E/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 ADS7835EB/250 VSSOP DGK 8 250 210.0 185.0 35.0 PackMaterials-Page2

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