ADS7834 ADS7834 SBAS098A – JANUARY 1998 – REVISED SEPTEMBER 2003 12-Bit High-Speed, Low-Power Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION (cid:1) 500kHz THROUGHPUT RATE The ADS7834 is a 12-bit sampling analog-to-digital converter (cid:1) 2.5V INTERNAL REFERENCE (A/D) complete with sample/hold, internal 2.5V reference, and synchronous serial interface. Typical power dissipation (cid:1) LOW POWER: 11mW is 11mW at a 500kHz throughput rate. The device can be (cid:1) SINGLE-SUPPLY +5V OPERATION placed into a power-down mode that reduces dissipation to (cid:1) DIFFERENTIAL INPUT just 2.5mW. The input range is zero to the reference voltage, (cid:1) SERIAL INTERFACE and the internal reference can be overdriven by an external voltage. (cid:1) 12-BITS NO MISSING CODES Low power, small size, and high speed make the ADS7834 (cid:1) MINI-DIP-8 AND MSOP-8 ideal for battery-operated systems such as wireless (cid:1) 0V TO V INPUT RANGE REF communication devices, portable multi-channel data loggers, and spectrum analyzers. The serial interface also provides APPLICATIONS low-cost isolation for remote data acquisition. The ADS7834 is available in a plastic mini-DIP-8 or an MSOP-8 package (cid:1) BATTERY-OPERATED SYSTEMS and is ensured over the –40°C to +85°C temperature range. (cid:1) DIGITAL SIGNAL PROCESSING (cid:1) HIGH-SPEED DATA ACQUISITION (cid:1) WIRELESS COMMUNICATION SYSTEMS CLK SAR CONV +In CDAC Serial –In Interface DATA S/H Amp Comparator Buffer Internal +2.5V Ref V REF 10kΩ ±30% Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 1998-2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com

PACKAGE/ORDERING INFORMATION MAXIMUM MAXIMUM INTEGRAL DIFFERENTIAL LINEARITY LINEARITY SPECIFIED ERROR ERROR PACKAGE- PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT (LSB) (LSB) LEAD DESIGNATOR(1) RANGE MARKING(2) NUMBER(3) MEDIA, QUANTITY ADS7834E ±2 N/S(3) MSOP-8 DGK –40°C to +85°C C34 ADS7834E/250 Tape and Reel, 250 ADS7834E " " " " " " ADS7834E/2K5 Tape and Reel, 2500 ADS7834EB ±1 ±1 MSOP-8 DGK –40°C to +85°C C34 ADS7834EB/250 Tape and Reel, 250 ADS7834EB " " " " " " ADS7834EB/2K5 Tape and Reel, 2500 ADS7834P ±2 N/S(3) Plastic DIP-8 P –40°C to +85°C ADS7834P ADS7834P Rails ADS7834PB ±1 ±1 " " " ADS7834PB ADS7834PB Rails NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. (2) Performance Grade information is marked on the reel. (3) N/S = Not Specified, typical only. However, 12-Bits no missing codes is ensured over temperature. ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC +V to GND............................................................................–0.3V to 6V DISCHARGE SENSITIVITY CC Analog Inputs to GND..............................................–0.3V to (V + 0.3V) CC Digital Inputs to GND...............................................–0.3V to (V + 0.3V) CC Electrostatic discharge can cause damage ranging from Power Dissipation..........................................................................325mW Maximum Junction Temperature...................................................+150°C performance degradation to complete device failure. Texas Operating Temperature Range.........................................–40°C to +85°C Instruments recommends that all integrated circuits be handled Storage Temperature Range..........................................–65°C to +150°C and stored using appropriate ESD protection methods. Lead Temperature (soldering, 10s) ...............................................+300°C ESD damage can range from subtle performance degrada- NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum condi- tion to complete device failure. Precision integrated circuits tions for extended periods may affect device reliability. may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PIN CONFIGURATION Top View V 1 8 +V V 1 8 +V REF CC REF CC +IN 2 7 CLK +IN 2 7 CLK ADS7834 ADS7834 –IN 3 6 DATA –IN 3 6 DATA GND 4 5 CONV GND 4 5 CONV Plastic Mini-DIP-8 MSOP-8 PIN ASSIGNMENTS PIN NAME DESCRIPTION 1 V Reference Output. Decouple to ground with a 0.1µF ceramic capacitor and a 2.2µF tantalum capacitor. REF 2 +IN Noninverting Input. 3 –IN Inverting Input. Connect to ground or to remote ground sense point. 4 GND Ground. 5 CONV Convert Input. Controls the sample/hold mode, start of conversion, start of serial data transfer, type of serial transfer, and power down mode. See the Digital Interface section for more information. 6 DATA Serial Data Output. The 12-bit conversion result is serially transmitted most significant bit first with each bit valid on the rising edge of CLK. By properly controlling the CONV input, it is possibly to have the data transmitted least significant bit first. See the Digital Interface section for more information. 7 CLK Clock Input. Synchronizes the serial data transfer and determines conversion speed. 8 +V Power Supply. Decouple to ground with a 0.1µF ceramic capacitor and a 10µF tantalum capacitor. CC ADS7834 2 www.ti.com SBAS098A

SPECIFICATIONS At T = –40°C to +85°C, +V = +5V, f = 500kHz, f = 16 • f , internal reference, unless otherwise specified. A CC SAMPLE CLK SAMPLE ADS7834P, E ADS7834PB, EB PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS ANALOG INPUT Full-Scale Input Span(1) +IN – (–IN) 0 V ✻ ✻ V REF Absolute Input Range +IN –0.2 V +0.2 ✻ ✻ V REF –IN –0.2 +0.2 ✻ ✻ V Capacitance 25 ✻ pF Leakage Current 1 ✻ µA SYSTEM PERFORMANCE Resolution 12 ✻ Bits No Missing Codes 12 ✻ Bits Integral Linearity Error ±1 ±2 ±0.5 ±1 LSB(2) Differential Linearity Error ±0.8 ±0.5 ±1 LSB Offset Error ±2 ±5 ±1 ✻ LSB Gain Error(3) 25°C ±12 ±30 ±7 ±15 LSB –40°C to +85°C ±50 ±35 LSB Common-Mode Rejection DC, 0.2Vp-p 70 ✻ dB 1MHz, 0.2Vp-p 50 ✻ dB Noise 60 ✻ µVrms Power Supply Rejection Worst Case ∆, +V = 5V ±5% 1.2 ✻ LSB CC SAMPLING DYNAMICS Conversion Time 1.625 ✻ µs Acquisition Time 0.350 ✻ µs Throughput Rate 500 ✻ kHz Aperture Delay 5 ✻ ns Aperture Jitter 30 ✻ ps Step Response 350 ✻ ns DYNAMIC CHARACTERISTICS Signal-to-Noise Ratio V = 5Vp-p at 10kHz 72 ✻ dB IN Total Harmonic Distortion(4) V = 5Vp-p at 10kHz –78 –72 –82 –75 dB IN Signal-to-(Noise+Distortion) V = 5Vp-p at 10kHz 68 70 70 72 dB IN Spurious Free Dynamic Range V = 5Vp-p at 10kHz 72 78 75 82 dB IN Usable Bandwidth SNR > 68dB 350 ✻ kHz REFERENCE OUTPUT Voltage I = 0 2.475 2.50 2.525 2.48 ✻ 2.52 V OUT Source Current(5) Static Load 50 ✻ µA Drift I = 0 20 ✻ ppm/°C OUT Line Regulation 4.75V ≤ V ≤ 5.25V 0.6 ✻ mV CC REFERENCE INPUT Range 2.0 2.55 ✻ ✻ V Resistance(6) to Internal Reference Voltage 10 ✻ ✻ ✻ kΩ DIGITAL INPUT/OUTPUT Logic Family CMOS ✻ Logic Levels: V |I | ≤ +5µA 3.0 V +0.3 ✻ ✻ V IH IH CC V |I | ≤ +5µA –0.3 0.8 ✻ ✻ V IL IL V I = –500µA 3.5 ✻ ✻ V OH OH V I = 500µA 0.4 ✻ ✻ V OL OL Data Format Straight Binary ✻ POWER SUPPLY REQUIREMENT +V Specified Performance 4.75 5.25 ✻ ✻ V CC Quiescent Current f = 500kHz 2.2 ✻ mA SAMPLE Power-Down 0.5 ✻ mA Power Dissipation f = 500kHz 11 20 ✻ ✻ mW SAMPLE Power-Down 2.5 ✻ mW TEMPERATURE RANGE Specified Performance –40 +85 ✻ ✻ °C ✻ Specifications same as ADS7834P,E. NOTES: (1) Ideal input span, does not include gain or offset error. (2) LSB means Least Significant Bit, with V equal to +2.5V, one LSB is 610µV. (3) Measured REF relative to an ideal, full-scale input (+IN – (–IN)) of 2.499V. Thus, gain error includes the error of the internal voltage reference. (4) Calculated on the first nine harmonics of the input frequency. (5) If the internal reference is required to source current to an external load, the reference voltage will change due to the internal 10kΩ resistor. (6) Can vary ±30%. ADS7834 3 SBAS098A www.ti.com

TYPICAL PERFORMANCE CURVES At T = +25°C, V = +5V, f = 500kHz, f = 16 • f , and internal +2.5V reference, unless otherwise specified. A CC SAMPLE CLK SAMPLE FULL-SCALE ERROR vs TEMPERATURE OFFSET VOLTAGE vs TEMPERATURE 1 0.5 0 0.4 B) –1 B) 0.3 S S C (L –2 C (L 0.2 m +25° ––34 m +25° 0.1 Delta fro ––56 Delta fro –0.01 –7 –0.2 –8 –0.3 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) POWER-DOWN SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 470 2.3 A) 460 2.2 µ wn Supply Current ( 444443250000 ply Current (mA) 221...109 fSAMPLE = 500kHz er-do 410 Sup 1.8 fSAMPLE = 125kHz w Po 400 1.7 390 1.6 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) INTEGRAL LINEARITY and DIFFERENTIAL LINEARITY SUPPLY CURRENT vs SAMPLE RATE vs SAMPLE RATE 2.4 0.06 2.3 SB) 0.04 L mA) 2.2 kHz ( 0.02 Change in Integral y Current ( 22..10 = 500AMPLE ––00..00024 Linearity (LSB) Suppl 1.9 a from fS –0.06 ChaLningeea irnit yD (ifLfeSrBe)ntial 1.8 elt –0.08 D 1.7 –0.1 100 200 300 400 500 600 100 200 300 400 500 600 Sample Rate (kHz) Sample Rate (kHz) ADS7834 4 www.ti.com SBAS098A

TYPICAL PERFORMANCE CURVES (Cont.) At T = +25°C, V = +5V, f = 500kHz, f = 16 • f , and internal +2.5V reference, unless otherwise specified. A CC SAMPLE CLK SAMPLE FULL-SCALE ERROR OFFSET VOLTAGE vs EXTERNAL vs EXTERNAL REFERENCE VOLTAGE REFERENCE VOLTAGE 0.300 0.2 0.200 0.1 mV) 0.100 mV) 0 V ( V ( –0.1 5 0.000 5 = 2.EF –0.100 = 2.EF ––00..23 R R V –0.200 V m m –0.4 a fro –0.300 a fro –0.5 elt –0.400 elt –0.6 D D –0.500 –0.7 –0.600 –0.8 2.0 2.1 2.2 2.3 2.4 2.5 2.0 2.2 2.4 2.55 External Reference Voltage (V) External Reference Voltage (V) PEAK-TO-PEAK NOISE POWER SUPPLY REJECTION vs EXTERNAL REFERENCE VOLTAGE vs POWER SUPPLY RIPPLE FREQUENCY 0.90 30 0.85 V) 25 SB) 0.80 mV/ eak Noise (L 00./7750 y Rejection ( 2105 P 0.65 pl eak-to- 0.60 er Sup 10 P 0.55 Pow 5 0.50 0 2 2.1 2.2 2.3 2.4 2.5 1 10 100 1k 10k 100k 1M External Reference Voltage (V) Power Supply Ripple Frequency (Hz) FREQUENCY SPECTRUM FREQUENCY SPECTRUM (4096 Point FFT; f = 977Hz, –0.2dB) (4096 Point FFT; f = 9.77kHz, –0.2dB) IN IN 0 0 –20 –20 B) –40 B) –40 d d e ( e ( ud –60 ud –60 plit plit m m A –80 A –80 –100 –100 –120 –120 0 50 100 150 200 250 0 50 100 150 200 250 Frequency (kHz) Frequency (kHz) ADS7834 5 SBAS098A www.ti.com

TYPICAL PERFORMANCE CURVES (Cont.) At T = +25°C, V = +5V, f = 500kHz, f = 16 • f , and internal +2.5V reference, unless otherwise specified. A CC SAMPLE CLK SAMPLE SIGNAL-TO-NOISE RATIO and FREQUENCY SPECTRUM SIGNAL-TO-(NOISE+DISTORTION) (4096 Point FFT; fIN = 99.7kHz, –0.2dB) vs INPUT FREQUENCY 0.00 76 74 SNR –20 B) 72 d e (dB) –40 NAD ( 70 ud –60 SI 68 SINAD plit nd m a 66 A –80 R N S 64 –100 62 –120 60 0 50 100 150 200 250 1 10 100 1000 Frequency (kHz) Input Frequency (kHz) SPURIOUS FREE DYNAMIC RANGE SIGNAL-TO-NOISE and and TOTAL HARMONIC DISTORTION SIGNAL-TO-(NOISE+DISTORTION) vs INPUT FREQUENCY vs TEMPERATURE 95 –95 0.3 B) f = 10kHz, –0.2dB) 90 –90 C (d 0.2 IN 85 –85 25° 0.1 + 80 SFDR –80 m SFDR (dB) 7750 THD✻ ––7750 THD (dB) D Delta fro ––000..12. SNR 65 –65 NA SI –0.3 60 –60 d SINAD 55 ✻o fF airns ti nnpinuet fhreaqrmueonncicys –55 R an –0.4 N 50 –50 S –0.5 1 10 100 1000 –40 –20 0 20 40 60 80 100 Input Frequency (kHz) Temperature (°C) ADS7834 6 www.ti.com SBAS098A

THEORY OF OPERATION are common to both inputs. Thus, the –IN input is best used to sense a remote ground point near the source of the +IN The ADS7834 is a high-speed. successive approximation signal. If the source driving the +IN signal is nearby, the register (SAR) analog-to-digital converter (A/D) with an –IN should be connected directly to ground. internal 2.5V bandgap reference. The architecture is based The input current into the analog input depends on input on capacitive redistribution which inherently includes a voltage and sample rate. Essentially, the current into the sample/hold function. The converter is fabricated on a 0.6µ device must charge the internal hold capacitor (typically CMOS process. See Figure 1 for the basic operating circuit 20pF) during the sample period. After this capacitance has for the ADS7834. been fully charged, there is no further input current. The The ADS7834 requires an external clock to run the conver- source of the analog input voltage must be able to charge the sion process. This clock can vary between 200kHz (12.5kHz input capacitance to a 12-bit settling level within the sample throughput) and 8MHz (500kHz throughput). The duty cycle period—which can be as little as 350ns in some operating of the clock is unimportant as long as the minimum HIGH modes. While the converter is in the hold mode or after the and LOW times are at least 50ns and the clock period is at sampling capacitor has been fully charged, the input imped- least 125ns. The minimum clock frequency is set by the ance of the analog input is greater than 1GΩ. leakage on the capacitors internal to the ADS7834. Care must be taken regarding the input voltage on the +IN The analog input is provided to two input pins: +IN and –IN. and –IN pins. To maintain the linearity of the converter, the When a conversion is initiated, the differential input on these +IN input should remain within the range of GND – 200mV pins is sampled on the internal capacitor array. While a to V + 200mV. The –IN input should not drop below REF conversion is in progress, both inputs are disconnected from GND – 200mV or exceed GND + 200mV. Outside of these any internal function. ranges, the converter’s linearity may not meet specifications. The range of the analog input is set by the voltage on the V pin. With the internal 2.5V reference, the input range REF REFERENCE is 0V to 2.5V. An external reference voltage can be placed on V , overdriving the internal voltage. The range for the REF The reference voltage on the V pin directly sets the full- REF external voltage is 2.0V to 2.55V, giving an input voltage scale range of the analog input. The ADS7834 can operate range of 2.0V to 2.55V. with a reference in the range of 2.0V to 2.55V, for a full- The digital result of the conversion is provided in a serial scale range of 2.0V to 2.55V. manner, synchronous to the CLK input. The result is pro- The voltage at the V pin is internally buffered and this REF vided most significant bit first and represents the result of buffer drives the capacitor DAC portion of the converter. the conversion currently in progress—there is no pipeline This is important because the buffer greatly reduces the delay. By properly controlling the CONV and CLK inputs, dynamic load placed on the reference source. However, the it is possible to obtain the digital result least significant bit voltage at V will still contain some noise and glitches REF first. from the SAR conversion process. These can be reduced by carefully bypassing the V pin to ground as outlined in the REF ANALOG INPUT sections that follow. The +IN and –IN input pins allow for a differential input INTERNAL REFERENCE signal to be captured on the internal hold capacitor when the converter enters the hold mode. The voltage range on the The ADS7834 contains an onboard 2.5V reference, resulting –IN input is limited to –0.2V to 0.2V. Because of this, the in a 0V to 2.5V input range on the analog input. The differential input can be used to reject only small signals that specification table gives the various specifications for the +5V + + 2.2µF 0.1µF ADS7834 0.1µF 10µF 1 V +V 8 REF CC 0V to 2.5V 2 +IN CLK 7 Serial Clock Analog Input from 3 –IN DATA 6 Serial Data Microcontroller or DSP 4 GND CONV 5 Convert Start FIGURE 1. Basic Operation of the ADS7834. ADS7834 7 SBAS098A www.ti.com

internal reference. This reference can be used to supply a small amount of source current to an external load, but the t load should be static. Due to the internal 10kΩ resistor, a CKP t t CKH CKL dynamic load will cause variations in the reference voltage, CLK and will dramatically affect the conversion result. Note that even a static load will reduce the internal reference voltage t CKDS t CKDH seen at the buffer input. The amount of reduction depends on DATA the load and the actual value of the internal “10kΩ” resistor. The value of this resistor can vary by ±30%. The V pin should be bypassed with a 0.1µF capacitor FIGURE 2. Serial Data and Clock Timing. REF placed as close as possible to the ADS7834 package. In addition, a 2.2µF tantalum capacitor should be used in SYMBOL DESCRIPTION MIN TYP MAX UNITS parallel with the ceramic capacitor. Placement of this ca- t Acquisition Time 350 ns pacitor, while not critical to performance, should be placed ACQ t Conversion Time 1.625 µs as close to the package as possible. CONV t Clock Period 125 5000 ns CKP t Clock LOW 50 ns CKL EXTERNAL REFERENCE tCKH Clock HIGH 50 ns t Clock Falling to Current Data 5 15 ns The internal reference is connected to the V pin and to the CKDH REF Bit No Longer Valid internal buffer via a 10kΩ series resistor. Thus, the reference t Clock Falling to Next Data Valid 30 50 ns CKDS voltage can easily be overdriven by an external reference t CONV LOW 40 ns CVL voltage. The voltage range for the external voltage is 2.0V t CONV HIGH 40 ns CVH to 2.55V, corresponding to an analog input range of 2.0V to t CONV Hold after Clock Falls(1) 10 ns CKCH 2.55V. tCKCS CONV Setup to Clock Falling(1) 10 ns t Clock Falling to DATA Enabled 20 50 ns CKDE While the external reference will not source significant t Clock Falling to DATA 70 100 ns CKDD current into the VREF pin, it does have to drive the series High Impedance 10kΩ resistor that is terminated into the 2.5V internal t Clock Falling to Sample Mode 5 ns CKSP reference (the exact value of the resistor will vary up to tCKPD Clock Falling to Power-Down Mode 50 ns ±30% from part to part). In addition, the VREF pin should tCVHD CONV Falling to Hold Mode 5 ns still be bypassed to ground with at least a 0.1µF ceramic (Aperture Delay) t CONV Rising to Sample Mode 5 ns capacitor (placed as close to the ADS7834 as possible). The CVSP t CONV Rising to Full Power-up 50 ns CVPU reference will have to be stable with this capacitive load. t CONV Changing State to DATA 70 100 ns CVDD Depending on the particular reference and A/D conversion High Impedance speed, additional bypass capacitance may be required, such t CONV Changing State to 50 ns CVPD as the 2.2µF tantalum capacitor shown in Figure 1. Power-Down Mode t CONV Falling to Start of CLK 5 µs DRP Reasons for choosing an external reference over the internal (for hold droop < 0.1 LSB) reference vary, but there are two main reasons. One is to Note: (1) This timing is not required under some situations. See text for more information. achieve a given input range. For example, a 2.048V refer- TABLE I. Timing Specifications (T = –40°C to +85°C, ence provides for a 0V to 2.048V input range—or 500µV A C = 30pF). per LSB. The other is to provide greater stability over LOAD temperature. (The internal reference is typically 20ppm/°C which translates into a full-scale drift of roughly 1 output The asynchronous nature of CONV to CLK raises some code for every 12°C. This does not take into account other interesting possibilities, but also some design consider- sources of full-scale drift). If greater stability over tempera- ations. Figure 3 shows that CONV has timing restraints in ture is needed, then an external reference with lower tem- relation to CLK (tCKCH and tCKCS). However, if these times perature drift will be required. are violated (which could happen if CONV is completely asynchronous to CLK), the converter will perform a conver- sion correctly, but the exact timing of the conversion is DIGITAL INTERFACE indeterminate. Since the setup and hold time between CONV Figure 2 shows the serial data timing and Figure 3 shows the and CLK has been violated in this example, the start of basic conversion timing for the ADS7834. The specific conversion could vary by one clock cycle. (Note that the timing numbers are listed in Table I. There are several start of conversion can be detected by using a pull-up important items in Figure 3 which give the converter addi- resistor on DATA. When DATA drops out of high-imped- tional capabilities over typical 8-pin converters. First, the ance and goes LOW, the conversion has started and that transition from sample mode to hold mode is synchronous to clock cycle is the first of the conversion.) the falling edge of CONV and is not dependent on CLK. In addition if CONV is completely asynchronous to CLK Second, the CLK input is not required to be continuous and CLK is continuous, then there is the possibility that during the sample mode. After the conversion is complete, CLK will transition just prior to CONV going LOW. If this the CLK may be kept LOW or HIGH. ADS7834 8 www.ti.com SBAS098A

occurs faster than the 10ns indicated by t , then there is Figure 4 shows the typical method for placing the A/D into CKCH a chance that some digital feedthrough may be coupled onto the power-down mode. If CONV is kept LOW during the the hold capacitor. This could cause a small offset error for conversion and is LOW at the start of the 13 clock cycle, that particular conversion. then the device enters the power-down mode. It remains in this mode until the rising edge of CONV. Note that CONV Thus, there are two basic ways to operate the ADS7834. must be HIGH for at least t in order to sample the signal CONV can be synchronous to CLK and CLK can be con- ACQ properly as well as to power-up the internal nodes. tinuous. This would be the typical situation when interfacing the converter to a digital signal processor. The second There are two different methods for clocking the ADS7834. method involves having CONV asynchronous to CLK and The first involves scaling the CLK input in relation to the gating the operation of CLK (a non-continuous clock). This conversion rate. For example, an 8MHz input clock and the method would be more typical of an SPI-like interface on a timing shown in Figure 3 results in a 500kHz conversion microcontroller. This method would also allow CONV to be rate. Likewise, a 1.6MHz clock would result in a 100kHz generated by a trigger circuit and to initiate (after some conversion rate. The second method involves keeping the delay) the start of CLK. These two methods are covered clock input as close to the maximum clock rate as possible under DSP Interfacing and SPI Interfacing. and starting conversions as needed. This timing is similar to that shown in Figure 4. As an example, a 50kHz conversion rate would require 160 clock periods per conversion instead POWER-DOWN TIMING of the 16 clock periods used at 500kHz. The conversion timing shown in Figure 3 does not result in the ADS7834 going into the power-down mode. If the The main distinction between the two is the amount of time conversion rate of the device is high (approaching 500kHz), that the ADS7834 remains in power-down. In the first mode, then there is very little power that can be saved by using the the converter only remains in power-down for a small power-down mode. However, since the power-down mode number of clock periods (depending on how many clock incurs no conversion penalty (the very first conversion is periods there are per each conversion). As the conversion valid), at lower sample rates, significant power can be saved rate scales, the converter always spends the same percentage by allowing the device to go into power-down mode be- of time in power-down. Since less power is drawn by the tween conversions. digital logic, there is a small decrease in power consump- tion, but it is very slight. This effect can be seen in the typical performance curve “Supply Current vs Sample Rate.” t t CVL CVCK CONV t CKCS t CKCH CLK 14 15 16 1 2 3 4 11 12 13 14 15 16 1 (1) t t CKDE CKDD D11 D0 DATA D10 D9 D2 D1 (MSB) (LSB) t ACQ t t CVHD CKSP SAMPLE/HOLD SAMPLE HOLD SAMPLE HOLD MODE (2) t CONV INTERNAL CONVERSION IDLE CONVERSION IN PROGRESS IDLE(3) STATE NOTES: (1) Clock periods 14 and 15 are shown for clarity, but are not required for proper operation of the ADS7834, provided that the minimum t time is met. The CLK input may remain HIGH or LOW during this period. (2) The transition from sample mode to hold ACQ mode occurs on the falling edge of CONV. This transition is not dependent on CLK. (3) The device remains fully powered when operated as shown. If the sample time is longer than 3 clock periods, power consumption can be reduced by allowing the device to enter a power-down mode. See the power-down timing for more information. FIGURE 3. Basic Conversion Timing. ADS7834 9 SBAS098A www.ti.com

CONV CLK 1 2 3 12 13 D11 D0 DATA (MSB) D10 D1 (LSB) t t CVSP ACQ SAMPLE/HOLD SAMPLE HOLD SAMPLE HOLD MODE (3) INTERNAL CONVERSION IDLE CONVERSION IN PROGRESS IDLE STATE t t CKPD CVPU POWER MODE FULL POWER LOW POWER FULL POWER (1) (2) NOTES: (1) The low power mode (“power-down”) is entered when CONV remains LOW during the conversion and is still LOW at the start of the 13th clock cycle. (2) The low power mode is exited when CONV goes HIGH. (3) When in power-down, the transition from hold mode to sample mode is initiated by CONV going HIGH. FIGURE 4. Power-down Timing. t CVH CONV t CKCH CLK 1 2 3 12 13 14 23 24 t CKCS t CVDD D11 D0 D11 DATA (MSB) D10 D1 (LSB) D1 D10 (MSB) LOW... (1) (2) SAMPLE/HOLD MODE SAMPLE HOLD INTERNAL CONVERSION IDLE CONVERSION IN PROGRESS IDLE STATE t CVPD POWER MODE FULL POWER LOW POWER (3) NOTES: (1) The serial data can be transmitted LSB first by pulling CONV LOW during the 13th clock cycle. (2) After the MSB has been transmitted, the DATA output pin will remain LOW until CONV goes HIGH. (3) When CONV is taken LOW to initiate the LSB first transfer, the converter enters the power-down mode. FIGURE 5. Serial Data “LSB-First” Timing. In contrast, the second method (clocking at a fixed rate) total power consumption by a considerable amount. For means that each conversion takes X clock cycles. As the example, a 50kHz conversion rate results in roughly time between conversions get longer, the converter remains 1/10 of the power (minus the reference) that is used at a in power-down an increasing percentage of time. This reduces 500kHz conversion rate. ADS7834 10 www.ti.com SBAS098A

Table II offers a look at the two different modes of operation the conversion will terminate immediately, before all 12 bits and the difference in power consumption. have been decided. This can be a very useful feature when a resolution of 12 bits is not needed. An example would be when the converter is being used to monitor an input voltage POWER WITH POWER WITH until some condition is met. At that time, the full resolution f CLK = 16 • f CLK = 8MHz SAMPLE SAMPLE of the converter would then be used. Short-cycling the 500kHz 11mW 11mW conversion can result in a faster conversion rate or lower 250kHz 10mW 7mW power dissipation. 100kHz 9mW 4mW There are several very important items shown in Figure 6. TABLE II. Power Consumption versus CLK Input. The conversion currently in progress is terminated when CONV is taken HIGH during the conversion and then taken LSB FIRST DATA TIMING LOW prior to t before the start of the 13th clock cycle. CKCH Figure 5 shows a method to transmit the digital result in a Note that if CONV goes LOW during the 13th clock cycle, least-significant bit (LSB) format. This mode is entered then the LSB-first mode will be entered (Figure 5). Also, when CONV is pulled HIGH during the conversion (before when CONV goes LOW, the DATA output immediately the end of the 12th clock) and then pulled LOW during the transitions to high impedance. If the output bit that is present 13th clock (when D0, the LSB, is being transmitted). The during that clock period is needed, CONV must not go LOW next 11 clocks then repeat the serial data, but in an LSB first until the bit has been properly latched into the receiving format. The converter enters the power-down mode during logic. the 13th clock and resumes normal operation when CONV goes HIGH. DATA FORMAT The ADS7834 output data is in straight binary format as SHORT-CYCLE TIMING shown in Figure 7. This figure shows the ideal output code The conversion currently in progress can be “short-cycled” for the given input voltage and does not include the effects with the technique shown in Figure 6. This term means that of offset, gain, or noise. (1) tCVL CONV t CVH CLK 1 2 3 4 5 6 7 t CVDD D11 DATA (MSB) D10 D9 D8 D7 D6 SAMPLE/HOLD SAMPLE HOLD MODE INTERNAL CONVERSION IDLE CONVERSION IN PROGRESS IDLE STATE t CVPD POWER MODE FULL POWER LOW POWER NOTE: (1) The conversion currently in progress can be stopped by pulling CONV LOW during the conversion. This must occur at least t prior to the start of the 13th clock cycle. The DATA output pin will tri-state and the device will enter the power-down CKCS mode when CONV is pulled LOW. FIGURE 6. Short-cycle Timing. ADS7834 11 SBAS098A www.ti.com

microcontrollers form various manufacturers. CONV would be tied to a general purpose I/O pin (SPI) or to a PCX pin FS = Full-Scale Voltage = V REF (QSPI), CLK would be tied to the serial clock, and DATA 1 LSB = FS/4096 would be tied to the serial input data pin such as MISO (master in slave out). 1 LSB 11...111 Note the time t shown in Figure 9. This represents the 11...110 DRP maximum amount of time between CONV going LOW and e d 11...101 o the start of the conversion clock. Since CONV going LOW C ut places the sample and hold in the hold mode and because the p Out hold capacitor loses charge over time, there is a requirement 00...010 that time t be met as well as the maximum clock period DRP 00...001 (t ). CKP 00...000 LAYOUT 0V 2.499V(1) Input Voltage(2) (V) For optimum performance, care should be taken with the physical layout of the ADS7834 circuitry. This is particu- NOTES: (1) For external reference, value isV – 1 LSB. (2) Voltage at converter input: +IN – (–IN). REF larly true if the CLK input is approaching the maximum input rate. FIGURE 7. Ideal Input Voltages and Output Codes. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connec- tions, and digital inputs that occur just prior to latching the DSP INTERFACING output of the analog comparator. Thus, during any single Figure 8 shows a timing diagram that might be used with a conversion for an n-bit SAR converter, there are n “win- typical digital signal processor such as a TI DSP. For the dows” in which large external transient voltages can easily buffered serial port (BSP) on the TMS320C54X family, affect the conversion result. Such glitches might originate CONV would tied to BFSX, CLK would be tied to BCLKX, from switching power supplies, nearby digital logic, and and DATA would be tied to BDR. high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact SPI/QSPI INTERFACING timing of the external event. The error can change if the Figure 9 shows the timing diagram for a typical serial external event changes in time with respect to the CLK peripheral interface (SPI) or queued serial peripheral inter- input. face (QSPI). Such interfaces are found on a number of CONV CLK 15 16 1 2 3 12 13 14 15 16 1 2 3 4 D11 D0 D11 DATA (MSB) D10 D1 (LSB) (MSB) D10 D9 FIGURE 8. Typical DSP Interface Timing. t t DRP ACQ CONV CLK 1 2 3 4 13 14 15 16 1 2 3 D11 D0 D11 DATA D10 D1 (MSB) (LSB) (MSB) FIGURE 9. Typical SPI/QSPI Interface Timing. ADS7834 12 www.ti.com SBAS098A

With this in mind, power to the ADS7834 should be clean capacitor. An additional larger capacitor may also be used, and well bypassed. A 0.1µF ceramic bypass capacitor should if desired. If the reference voltage is external and originates be placed as close to the device as possible. In addition, a from an op-amp, make sure that it can drive the bypass 1µF to 10µF capacitor is recommended. If needed, an even capacitor or capacitors without oscillation. larger capacitor and a 5Ω or 10Ω series resistor my be used The GND pin should be connected to a clean ground point. to lowpass filter a noisy supply. In many cases, this will be the “analog” ground. Avoid The ADS7834 draws very little current from an external connections which are too near the grounding point of a reference on average as the reference voltage is internally microcontroller or digital signal processor. If needed, run a buffered. However, glitches from the conversion process ground trace directly from the converter to the power supply appear at the V input and the reference source must be entry point. The ideal layout will include an analog ground REF able to handle this. Whether the reference is internal or plane dedicated to the converter and associated analog external, the V pin should be bypassed with a 0.1µF circuitry. REF ADS7834 13 SBAS098A www.ti.com

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS7834E/250 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 C34 & no Sb/Br) ADS7834E/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 C34 & no Sb/Br) ADS7834E/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 C34 & no Sb/Br) ADS7834EB/250 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 C34 & no Sb/Br) ADS7834EB/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 C34 & no Sb/Br) ADS7834EB/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 C34 & no Sb/Br) ADS7834EB/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 C34 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS7834E/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7834E/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7834EB/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7834EB/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS7834E/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS7834E/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 ADS7834EB/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS7834EB/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 PackMaterials-Page2

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