(cid:2)(cid:17)(cid:14)(cid:14)(cid:20)(cid:2)(cid:14)(cid:13)(cid:18)(cid:12) (cid:4)(cid:14)(cid:13)(cid:8)(cid:17)(cid:7)(cid:16)(cid:15) ADS7822 (cid:10)(cid:14)(cid:13)(cid:11) (cid:5)(cid:9)(cid:19)(cid:6)(cid:15) (cid:3)(cid:12)(cid:15)(cid:16)(cid:14)(cid:17)(cid:11)(cid:9)(cid:12)(cid:16)(cid:15) ADS7822 ADS7822 SBAS062C–JANUARY1996–REVISEDAUGUST2007 12-Bit, 200kHz, microPower Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES 1 • 200kHzSamplingRate DESCRIPTION 2 • microPower: The ADS7822 is a 12-bit sampling analog-to-digital 1.6mWat200kHz (A/D) converter with ensured specifications over a 0.54mWat75kHz 2.7V to 5.25V supply range. It requires very little 0.06mWat7.5kHz powerevenwhenoperatingatthefull200kHzrate. At lower conversion rates, the high speed of the device • PowerDown:3μAmax enables it to spend most of its time in the • Mini-DIP-8,SO-8,andMSOP-8Packages power-down mode—the power dissipation is less • Pseudo-DifferentialInput than60μWat7.5kHz. • SerialInterface The ADS7822 also features operation from 2.0V to 5V, a synchronous serial interface, and a APPLICATIONS pseudo-differential input. The reference voltage can • Battery-OperatedSystems besettoanylevelwithintherangeof50mVtoVCC. • RemoteDataAcquisition Ultra low power and small size make the ADS7822 • IsolatedDataAcquisition ideal for battery-operated systems. It is also a perfect • SimultaneousSampling,MultichannelSystems fit for remote data-acquisition modules, simultaneous multichannel systems, and isolated data acquisition. The ADS7822 is available in a plastic mini-DIP-8, an SO-8,oranMSOP-8package. SAR Control V REF D OUT +In CDAC Serial -In Interface DCLOCK CS/SHDN S/H Amp Comparator 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Alltrademarksarethepropertyoftheirrespectiveowners. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©1996–2007,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

ADS7822 www.ti.com SBAS062C–JANUARY1996–REVISEDAUGUST2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION(1) MAXIMUM MAXIMUM INTEGRAL DIFFERENTIAL SPECIFIED TRANSPORT PACKAGE- PACKAGE PACKAGE ORDERING PRODUCT LINEARITY LINEARITY LEAD DESIGNATOR TEMPERATURE MARKING(2) NUMBER MEDIA, ERROR ERROR RANGE QUANTITY (LSB) (LSB) TapeandReel, ADS7822E/250 250 ADS7822E ±2 ±2 MSOP-8 DGK –40(cid:176)Cto+85(cid:176)C A22 TapeandReel, ADS7822E/2K5 2500 TapeandReel, ADS7822EB/250 250 ADS7822EB ±1 ±1 MSOP-8 DGK –40(cid:176)Cto+85(cid:176)C A22 TapeandReel, ADS7822EB/2K5 2500 TapeandReel, ADS7822EC/250 250 ADS7822EC ±0.75 ±0.75 MSOP-8 DGK –40(cid:176)Cto+85(cid:176)C A22 TapeandReel, ADS7822EC/2K5 2500 ADS7822P ±2 ±2 Plastic P –40(cid:176)Cto+85(cid:176)C ADS7822P ADS7822P Rails,50 DIP-8 ADS7822PB ±1 ±1 Plastic P –40(cid:176)Cto+85(cid:176)C ADS7822PB ADS7822PB Rails,50 DIP-8 ADS7822PC ±0.75 ±0.75 Plastic P –40(cid:176)Cto+85(cid:176)C ADS7822PC ADS7822PC Rails,50 DIP-8 ADS7822U Rails,100 ADS7822U ±2 ±2 SO-8 D –40(cid:176)Cto+85(cid:176)C ADS7822U TapeandReel, ADS7822U/2K5 2500 ADS7822UB Rails,100 ADS7822UB ±1 ±1 SO-8 D –40(cid:176)Cto+85(cid:176)C ADS7822UB TapeandReel, ADS7822UB/2K5 2500 ADS7822UC Rails,100 ADS7822UC ±0.75 ±0.75 SO-8 D –40(cid:176)Cto+85(cid:176)C ADS7822UC TapeandReel, ADS7822UC/2K5 2500 (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumlocatedattheendofthisdatasheet,orsee theTIwebsiteatwww.ti.com. (2) Performancegradeinformationismarkedonthereel. ABSOLUTE MAXIMUM RATINGS(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) ADS7822 UNIT V +6 V CC Analoginput –0.3toV +0.3 V CC Logicinput –0.3to6 V Casetemperature +100 (cid:176) C Junctiontemperature +150 (cid:176) C Storagetemperature +125 (cid:176) C Externalreferencevoltage +5.5 V (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximumratedconditionsforextendedperiodsmayaffectdevicereliability. 2 SubmitDocumentationFeedback Copyright©1996–2007,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7822

ADS7822 www.ti.com SBAS062C–JANUARY1996–REVISEDAUGUST2007 ELECTRICAL CHARACTERISTICS: +V = +2.7V CC At–40(cid:176) Cto+85(cid:176) C,+V =+2.7V,V =+2.5V,f =75kHz,andf =16· f ,unlessotherwisenoted. CC REF SAMPLE CLK SAMPLE ADS7822 ADS7822B ADS7822C PARAMETER TESTCONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX ANALOGINPUT Full-scaleinputspan +In–(–In) 0 VREF 0 VREF 0 VREF V Absoluteinputrange +In–GND –0.2 VCC+0.2 –0.2 VCC+0.2 –0.2 VCC+0.2 V –In–GND –0.2 +1.0 –0.2 +1.0 –0.2 +1.0 V Capacitance 25 25 25 pF Leakagecurrent ±1 ±1 ±1 μA SYSTEMPERFORMANCE Resolution 12 12 12 Bits Nomissingcodes 11 12 11 Bits Integrallinearityerror –2 ±0.5 +2 –1 ±0.5 +1 –0.75 ±0.25 +0.75 LSB(1) Differentiallinearityerror –2 ±0.5 +2 –1 ±0.5 +1 –0.75 ±0.25 +0.75 LSB Offseterror –3 +3 –3 +3 –1 +1 LSB Gainerror –3 +3 –3 +3 –1 +1 LSB Noise 33 33 33 μVrms Power-supplyrejection 82 82 82 dB SAMPLINGDYNAMICS Conversiontime 12 12 12 ClkCycles Acquisitiontime 1.5 1.5 1.5 ClkCycles Throughputrate 75 75 75 kHz DYNAMICCHARACTERISTICS Totalharmonicdistortion VIN=2.5VPPat1kHz –82 –82 –82 dB SINAD VIN=2.5VPPat1kHz 71 71 71 dB Spurious-freedynamicrange VIN=2.5VPPat1kHz 86 86 86 dB REFERENCEOUTPUT Voltagerange 0.05 VCC 0.05 VCC 0.05 VCC V Resistance CS=GND,fSAMPLE=0Hz 5 5 5 GΩ CS=VCC 5 5 5 GΩ Atcode710h 8 40 8 40 8 40 μA Currentdrain fSAMPLE=7.5kHz 0.8 0.8 0.8 μA CS=VCC 0.001 3 0.001 3 0.001 3 μA DIGITALINPUT/OUTPUT Logicfamily CMOS CMOS CMOS VIH IIH=+5μA 2.0 5.5 2.0 5.5 2.0 5.5 V Logiclevels VIL IIL=+5μA –0.3 0.8 –0.3 0.8 –0.3 0.8 V VOH IOH=–250μA 2.1 2.1 2.1 V VOL IOL=250μA 0.4 0.4 0.4 V Dataformat StraightBinary StraightBinary StraightBinary POWER-SUPPLYREQUIREMENTS Specifiedperformance 2.7 3.6 2.7 3.6 2.7 3.6 V VCC SeeNotes(2)and(3) 2.0 2.7 2.0 2.7 2.0 2.7 V SeeNote(3) 2.7 3.6 2.7 3.6 2.7 3.6 V Quienscentcurrent fSAMPLE=7.5kHz(4)(5) 20 20 20 μA fSAMPLE=75kHz(5) 200 325 200 325 200 325 μA Powerdown CS=VCC 3 3 3 μA TEMPERATURERANGE Specifiedperformance –40 +85 –40 +85 –40 +85 (cid:176)C (1) LSBmeansleastsignificantbit.WithV equalto+2.5V,oneLSBis0.61mV. REF (2) ThemaximumclockrateoftheADS7822islessthan1.2MHzinthispower-supplyrange. (3) SeetheTypicalCharacteristicsformoreinformation. (4) f =1.2MHz,CS=V for145clockcyclesoutofevery160. CLK CC (5) SeethePowerDissipationsectionformoreinformationregardinglowersamplerates. Copyright©1996–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):ADS7822

ADS7822 www.ti.com SBAS062C–JANUARY1996–REVISEDAUGUST2007 ELECTRICAL CHARACTERISTICS: +V = +5V CC At–40(cid:176) Cto+85(cid:176) C,+V =+5V,V =+5V,f =200kHz,andf =16· f ,unlessotherwisenoted. CC REF SAMPLE CLK SAMPLE ADS7822 ADS7822B PARAMETER TESTCONDITIONS UNIT MIN TYP MAX MIN TYP MAX ANALOGINPUT Full-scaleinputspan +In–(–In) 0 VREF 0 VREF V Absoluteinputrange +In–GND –0.2 VCC+0.2 –0.2 VCC+0.2 V –In–GND –0.2 +1.0 –0.2 +1.0 V Capacitance 25 25 pF Leakagecurrent ±1 ±1 μA SYSTEMPERFORMANCE Resolution 12 12 Bits Nomissingcodes 11 12 Bits Integrallinearityerror –2 +2 –1 +1 LSB(1) Differentiallinearityerror ±0.8 –1 ±0.5 +1 LSB Offseterror –3 +3 –3 +3 LSB Gainerror –4 +4 –3 +3 LSB Noise 33 33 μVrms Power-supplyrejection 70 70 dB SAMPLINGDYNAMICS Conversiontime 12 12 ClkCycles Acquisitiontime 1.5 1.5 ClkCycles Throughputrate 200 200 kHz DYNAMICCHARACTERISTICS Totalharmonicdistortion VIN=5VPPat10kHz –78 –78 dB SINAD VIN=5VPPat10kHz 71 71 dB Spurious-freedynamicrange VIN=5VPPat10kHz 79 79 dB REFERENCEOUTPUT Voltagerange 0.05 VCC 0.05 VCC V Resistance CS=GND,fSAMPLE=0Hz 5 5 GΩ CS=VCC 5 5 GΩ Atcode710h 40 100 40 100 μA Currentdrain fSAMPLE=12.5kHz 2.5 2.5 μA CS=VCC 0.001 3 0.001 3 μA DIGITALINPUT/OUTPUT Logicfamily CMOS CMOS VIH IIH=+5μA 3.0 5.5 3.0 5.5 V Logiclevels VIL IIL=+5μA –0.3 0.8 –0.3 0.8 V VOH IOH=–250μA 3.5 3.5 V VOL IOL=250μA 0.4 0.4 V Dataformat StraightBinary StraightBinary POWER-SUPPLYREQUIREMENTS VCC Specifiedperformance 4.75 5.25 4.75 5.25 V Quienscentcurrent fSAMPLE=200kHz 320 550 320 550 μA Powerdown CS=VCC 3 3 μA TEMPERATURERANGE Specifiedperformance –40 +85 –40 +85 (cid:176)C (1) LSBmeansleastsignificantbit.WithV equalto+5V,oneLSBis1.22mV. REF 4 SubmitDocumentationFeedback Copyright©1996–2007,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7822

ADS7822 www.ti.com SBAS062C–JANUARY1996–REVISEDAUGUST2007 PIN CONFIGURATION D,DGK,ORPPACKAGE SO,MSOP,orDIP (TOPVIEW) V 1 8 +V REF CC +In 2 7 DCLOCK ADS7822 -In 3 6 D OUT GND 4 5 CS/SHDN PINASSIGNMENTS PIN DESCRIPTION NAME NO. VREF 1 Referenceinput +In 2 Noninvertinginput –In 3 Invertinginput.Connecttogroundortoremotegroundsensepoint. GND 4 Ground CS/SHDN 5 Chipselectwhenlow;Shutdownmodewhenhigh. Theserialoutputdatawordiscomprisedof12bitsofdata.Inoperation,thedataarevalidonthefallingedgeofDCLOCK.The DOUT 6 secondclockpulseafterthefallingedgeofCSenablestheserialoutput.Afteronenullbit,thedataarevalidforthenextedges. DCLOCK 7 Dataclocksynchronizestheserialdatatransferanddeterminesconversionspeed. +VCC 8 Powersupply Copyright©1996–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):ADS7822

ADS7822 www.ti.com SBAS062C–JANUARY1996–REVISEDAUGUST2007 TYPICAL CHARACTERISTICS AtT =+25(cid:176) C,V =+2.7V,V =+2.5V,f =75kHz,f =16· f ,unlessotherwisespecified. A CC REF SAMPLE CLK SAMPLE INTEGRALLINEARITYERROR DIFFERENTIALLINEARITYERROR vsCODE vsCODE 1.00 1.00 B) 0.75 SB) 0.75 arity Error (LS 000...520050 earity Error (L 000...520050 e n Integral Lin ---000...257505 Differential Li ---000...257505 -1.00 -1.00 0 2048 4095 0 2048 4095 Code Code Figure1. Figure2. SUPPLYCURRENT POWER-DOWNSUPPLYCURRENT vsTEMPERATURE vsTEMPERATURE 350 120 300 100 A) A) m 250 n 80 nt ( nt ( e e urr 200 urr 60 C C pply 150 pply 40 u u S S 100 20 50 0 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) Figure3. Figure4. QUIESCENTCURRENT MAXIMUMSAMPLERATE vsV vsV CC CC 400 1000 350 A) nt (m 300 kHz) 100 Curre 250 Rate ( nt e esce 200 ampl 10 ui S Q 150 100 1 1 2 3 4 5 1 2 3 4 5 V (V) V (V) CC CC Figure5. Figure6. 6 SubmitDocumentationFeedback Copyright©1996–2007,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7822

ADS7822 www.ti.com SBAS062C–JANUARY1996–REVISEDAUGUST2007 TYPICAL CHARACTERISTICS (continued) AtT =+25(cid:176) C,V =+2.7V,V =+2.5V,f =75kHz,f =16· f ,unlessotherwisespecified. A CC REF SAMPLE CLK SAMPLE CHANGEINOFFSET CHANGEINOFFSET vsREFERENCEVOLTAGE vsTEMPERATURE 1.2 0.6 1.0 VV == 55VV CCCC 0.4 0.8 et (LSB) 00..64 C (LSB) 0.2 Offs 0.2 °25 0 n m Change i --000...024 Delta fro --00..24 -0.6 -0.8 -0.6 1 2 3 4 5 -50 -25 0 25 50 75 100 Reference Voltage (V) Temperature (°C) Figure7. Figure8. CHANGEINGAIN CHANGEINGAIN vsREFERENCEVOLTAGE vsTEMPERATURE 2.5 0.15 2.0 VVCCCC== 55VV 0.10 B) 1.5 B) n (LS 1.0 C (LS 0.05 Gai 0.5 °25 0 n m Change i -00..05 Delta fro -0.05 -0.10 -1.0 -1.5 -0.15 1 2 3 4 5 -50 -25 0 25 50 75 100 Reference Voltage (V) Temperature (°C) Figure9. Figure10. EFFECTIVENUMBEROFBITS PEAK-TO-PEAKNOISE vsREFERENCEVOLTAGE vsREFERENCEVOLTAGE 12.00 10 11.75 VCC= 5V 9 VCC= 5V ms) B) 8 of Bits (r 1111..5205 oise (LS 76 mber 11.00 eak N 5 ective Nu 1100..7550 Peak-to-P 432 Eff 10.25 1 10.00 0 0.1 1 10 0.1 1 10 Reference Voltage (V) Reference Voltage (V) Figure11. Figure12. Copyright©1996–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):ADS7822

ADS7822 www.ti.com SBAS062C–JANUARY1996–REVISEDAUGUST2007 TYPICAL CHARACTERISTICS (continued) AtT =+25(cid:176) C,V =+2.7V,V =+2.5V,f =75kHz,f =16· f ,unlessotherwisespecified. A CC REF SAMPLE CLK SAMPLE SPURIOUSFREEDYNAMICRANGEAND TOTALHARMONICDISTORTION SIGNAL-TO-NOISERATIOvsFREQUENCY vsFREQUENCY 100 0 90 Spurious Free Dynamic Range -10 80 dB) -20 d SNR (dB) 765000 Signal-to-Noise Ratio c Distortion ( ---345000 R an 40 moni -60 FD 30 Har -70 S 20 Total -80 10 -90 0 -100 1 10 100 1 10 100 Frequency (kHz) Frequency (kHz) Figure13. Figure14. SIGNAL-TO-(NOISE+DISTORTION) SIGNAL-TO-(NOISE+DISTORTION) vsFREQUENCY vsINPUTLEVEL 100 80 B) ortion) (dB) 987000 Distortion) (d 765000 st 60 + Di o e + 50 Rati 40 Signal-to-(Nois 43210000 gnal-to-(Noise 321000 Si 0 0 1 10 100 -40 -35 -30 -25 -20 -15 -10 -5 0 Frequency (kHz) Input Level (dB) Figure15. Figure16. REFERENCECURRENT REFERENCECURRENTvsTEMPERATURE vsSAMPLERATE (Code=710h) 14 14 12 12 Reference Current (A)m 10864 Reference Current (A) 1086 4 2 0 2 0 15 30 45 60 75 -50 -25 0 25 50 75 100 Sample Rate (kHz) Temperature (°C) Figure17. Figure18. 8 SubmitDocumentationFeedback Copyright©1996–2007,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7822

ADS7822 www.ti.com SBAS062C–JANUARY1996–REVISEDAUGUST2007 TYPICAL CHARACTERISTICS (continued) AtT =+25(cid:176) C,V =+2.7V,V =+2.5V,f =75kHz,f =16· f ,unlessotherwisespecified. A CC REF SAMPLE CLK SAMPLE POWER-SUPPLYREJECTION POWER-SUPPLYREJECTION vsRIPPLEFREQUENCY vsRIPPLEFREQUENCY 0 0 V = 2.7V V = 5V -10 RCipCple = 500mV -10 RCipCple = 500mV PP PP -20 VIN= 1.25VDC -20 VIN= 2.5VDC V = 2.5V V = 5V REF REF -30 -30 SR (dB) --4500 SR (dB) --4500 P P -60 -60 -70 -70 -80 PSR (dB) = 20log(500mV/DVO) -80 PSR (dB) = 20log(500mV/DVO) whereDV = change in digital result whereDV = change in digital result -90 O -90 O 1k 10k 100k 1M 10M 10 1 1k 10k 100k 1M 10M Ripple Frequency (Hz) Ripple Frequency (Hz) Figure19. Figure20. CHANGEININTEGRALLINEARITY ANDDIFFERENTIALLINEARITY vsREFERENCEVOLTAGE 0.20 B) VCC= 5V S 0.15 L e ( c n 0.10 Change in Integral e er Linearity (LSB) ef R 0.05 V 5 2. m + 0.00 o a fr -0.05 Change in Differential Delt Linearity (LSB) -0.10 1 2 3 4 5 Reference Voltage (V) Figure21. Copyright©1996–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):ADS7822

ADS7822 www.ti.com SBAS062C–JANUARY1996–REVISEDAUGUST2007 THEORY OF OPERATION The ADS7822 is a classic successive approximation The range of the –In input is limited to –0.2V to +1V. register (SAR) A/D converter. The architecture is Because of this, the differential input can be used to based on capacitive redistribution that inherently reject only small signals that are common to both includes a sample/hold function. The converter is inputs. Thus, the –In input is best used to sense a fabricated on a 0.6μ CMOS process. The architecture remote signal ground that may move slightly with and process allow the ADS7822 to acquire and respecttothelocalgroundpotential. convert an analog signal at up to 200,000 The input current on the analog inputs depends on a conversions per second while consuming very little number of factors: sample rate, input voltage, source power. impedance, and power-down mode. Essentially, the The ADS7822 requires an external reference, an current into the ADS7822 charges the internal external clock, and a single power source (V ). The capacitor array during the sample period. After this CC external reference can be any voltage between 50mV capacitance has been fully charged, there is no and V . The value of the reference voltage directly further input current. The source of the analog input CC sets the range of the analog input. The reference voltage must be able to charge the input capacitance input current depends on the conversion rate of the (25pF) to a 12-bit settling level within 1.5 clock ADS7822. cycles. When the converter goes into the hold mode or while it is in the power-down mode, the input The external clock can vary between 10kHz (625Hz impedanceisgreaterthan1GΩ. throughput) and 3.2MHz (200kHz throughput). The duty cycle of the clock is essentially unimportant as Care must be taken regarding the absolute analog long as the minimum high and low times are at least input voltage. To maintain the linearity of the 400ns for a supply range between 2.7V to 3.6V, or converter, the –In input should not drop below GND – 125ns for a supply range between 4.75V to 5.25V. 200mV or exceed GND + 1V. The +In input should The minimum clock frequency is set by the leakage always remain within the range of GND – 200mV to onthecapacitorsinternaltotheADS7822. V + 200mV. Outside of these ranges, the converter CC linearitymaynotmeetspecifications. The analog input is provided to two input pins: +In and –In. When a conversion is initiated, the REFERENCE INPUT differential input on these pins is sampled on the internal capacitor array. While a conversion is in The external reference sets the analog input range. progress, both inputs are disconnected from any The ADS7822 operates with a reference in the range internalfunction. of 50mV to V . There are several important CC implicationsofthis. The digital result of the conversion is clocked out by the DCLOCK input and is provided serially, most As the reference voltage is reduced, the analog significant bit first, on the D pin. The digital data voltage weight of each digital output code is reduced. OUT that is provided on the D pin is for the conversion This is often referred to as the LSB (least significant OUT currently in progress—there is no pipeline delay. It is bit) size and is equal to the reference voltage divided possible to continue to clock the ADS7822 after the by 4096. This means that any offset or gain error conversion is complete and to obtain the serial data inherent in the A/D converter will appear to increase, least significant bit first. See the Digital Interface in terms of LSB size, as the reference voltage is sectionformoreinformation. reduced. ANALOG INPUT The +In and –In input pins allow for a pseudo-differential input signal. Unlike some converters of this type, the –In input is not resampled later in the conversion cycle. When the converter goes into the hold mode, the voltage difference between +In and –In is captured on the internal capacitorarray. 10 SubmitDocumentationFeedback Copyright©1996–2007,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7822

ADS7822 www.ti.com SBAS062C–JANUARY1996–REVISEDAUGUST2007 Thenoiseinherentin the converter will also appear to DIGITAL INTERFACE increase with lower LSB size. With a 2.5V reference, theinternalnoiseoftheconvertertypicallycontributes SignalLevels only 0.32 LSB peak-to-peak of potential error to the The digital inputs of the ADS7822 can accommodate output code. When the external reference is 50mV, logic levels up to 6V regardless of the value of V . the potential error contribution from the internal noise CC Thus, the ADS7822 can be powered at 3V and still will be 50 times larger—16 LSBs. The errors due to acceptinputsfromlogicpoweredat5V. the internal noise are gaussian in nature and can be reducedbyaveragingconsecutiveconversionresults. The CMOS digital output (D ) will swing 0V to V . OUT CC If V is 3V and this output is connected to a 5V For more information regarding noise, consult the CC CMOS logic input, then that IC may require more typical characteristic curves Effective Number of Bits supply current than normal and may have a slightly vs Reference Voltage and Peak-to-Peak Noise vs longerpropagationdelay. Reference Voltage. Note that the effective number of bits (ENOB) figure is calculated based on the SerialInterface converter signal-to-(noise + distortion) ratio with a 1kHz, 0dB input signal. SINAD is related to ENOB as The ADS7822 communicates with microprocessors follows: and other digital systems via a synchronous 3-wire serial interface, as shown in Figure 22 and Table 1. SINAD=6.02•ENOB+1.76 The DCLOCK signal synchronizes the data transfer With lower reference voltages, extra care should be with each bit being transmitted on the falling edge of taken to provide a clean layout including adequate DCLOCK. Most receiving systems will capture the bypassing, a clean power supply, a low-noise bitstream on the rising edge of DCLOCK. However, if reference, and a low-noise input signal. Because the the minimum hold time for D is acceptable, the OUT LSB size is lower, the converter will also be more system can use the falling edge of DCLOCK to sensitive to external sources of error such as nearby captureeachbit. digitalsignalsandelectromagneticinterference. t CYC CS/SHDN t Power SUCS Down DCLOCK t CSD Null Null DOUT Hi-Z Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(1) Hi-Z Bit B11 B10 B9 B8 t (MSB) SMPL tCONV tDATA Note: (1) After completing the data transfer, if further clocks are applied withCSLOW, the A/D will output LSB-First data then followed with zeroes indefinitely. t CYC CS/SHDN tSUCS Power Down DCLOCK t CSD Null DOUT Hi-Z Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 Hi-Z (1) t (MSB) SMPL t t CONV DATA Note: (1) After completing the data transfer, if further clocks are applied withCSLOW, the A/D will output zeroes indefinitely. t : During this time, the bias current and the comparator power down and the reference input DATA becomes a high impedance node, leaving the CLK running to clock out LSB-first data or zeroes. Figure22.BasicTimingDiagrams Copyright©1996–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):ADS7822

ADS7822 www.ti.com SBAS062C–JANUARY1996–REVISEDAUGUST2007 Table1.TimingSpecifications(–40(cid:176) Cto+85(cid:176) C) VCC=2.7V VCC=5V SYMBOL DESCRIPTION UNITS MIN TYP MAX MIN TYP MAX tSMPL Analoginputsampletime 1.5 2.0 1.5 2.0 ClkCycles tCONV Conversiontime 12 12 ClkCycles tCYC Cycletime 16 16 ClkCycles tCSD CSfallingtoDCLOCKlow 0 0 ns tSUCS CSfallingtoDCLOCKrising 0.03 1000 0.03 1000 μs thDO DCLOCKfallingtocurrentDOUTnotvalid 15 15 ns tdDO DCLOCKfallingtonextDOUTvalid 130 200 85 150 ns tdis CSrisingtoDOUTtri-state 40 80 25 50 ns ten DCLOCKfallingtoDOUTenabled 75 175 50 100 ns tf DOUTfalltime 90 200 70 100 ns tr DOUTrisetime 110 200 60 100 ns 1.4V 3kW D VOH OUT V DOUT Test Point OL t t 100pF r f C LOAD Voltage Waveforms for D Rise and Fall Times, t, t OUT r f Load Circuit for t , t, and t dDO r f Test Point DCLOCK V V IL CC 3kW tdisWaveform 2, ten tdDO DOUT V t Waveform 1 OH 100pF dis D OUT C V LOAD OL t hDO Load Circuit for t and t dis en Voltage Waveforms for D Delay Times, t OUT dDO CS/SHDN VIH CS/SHDN D DCLOCK 1 2 OUT 90% Waveform 1(1) t dis DOUT 10% DOUT VOL B11 Waveform 2(2) t en Voltage Waveforms for t dis Voltage Waveforms for t en NOTES: (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control. Figure23.TimingDiagramsandTestCircuitsfortheParametersinTable1 12 SubmitDocumentationFeedback Copyright©1996–2007,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7822

ADS7822 www.ti.com SBAS062C–JANUARY1996–REVISEDAUGUST2007 A falling CS signal initiates the conversion and data transition(as is typical for digital CMOS components), transfer. The first 1.5 to 2.0 clock periods of the but also uses some current for the analog circuitry, conversion cycle are used to sample the input signal. such as the comparator. The analog section After the second falling DCLOCK edge, D is dissipates power continuously, until the power-down OUT enabled and outputs a low value for one clock period. modeisentered. For the next 12 DCLOCK periods, D outputs the OUT Figure 24 shows the current consumption of the conversionresult,mostsignificantbitfirst. ADS7822 versus sample rate. For this graph, the After the least significant bit (B0) has been output, converter is clocked at 1.2MHz regardless of the subsequent clocks repeat the output data, but in a sample rate—CS is high for the remaining sample least significant bit first format. After the most period. Figure 25 also shows current consumption significant bit (B11) has been repeated, DOUT will versus sample rate. However, in this case, the tri-state. Subsequent clocks have no effect on the DCLOCK period is 1/16th of the sample period—CS converter.Anewconversionisinitiated only when CS ishighforoneDCLOCKcycleoutofevery16. istakenhighandreturnedlow. 1000 DataFormat T = 25°C A f = 1.2MHz The output data from the ADS7822 is in straight CLK binary format, as shown in Table 2. This table A) represents the ideal output code for the given input mnt ( 100 vgoalitnageerroar,nodrdnooeisse.not include the effects of offset, Curre VCC= 5.0V VCC= 2.7V ply VREF= 5.0V VREF= 2.5V p 10 u Table2.IdealInputVoltagesandOutputCodes S DIGITALOUTPUT DESCRIPTION ANALOGVALUE STRAIGHTBINARY Full-Scalerange VREF 1 0.1 1 10 100 Leastsignificant bit(LSB) VREF/4096 BINARYCODE HEXCODE Sample Rate (kHz) Full-Scale VREF–1LSB 111111111111 FFF Midscale VREF/2 100000000000 800 Figure24.MaintainingfCLKattheHighest PossibleRateAllowstheSupplyCurrenttoDrop Midscale–1LSB VREF/2–1LSB 011111111111 7FF LinearlywiththeSampleRate Zero 0V 000000000000 000 POWER DISSIPATION 1000 The architecture of the converter, the semiconductor fabrication process, and a careful design allow the ADS7822 to convert at up to a 75kHz rate while A) m 100 requiring very little power. Still, for the absolute nt ( lowest power dissipation, there are several things to urre keepinmind. C y pl The power dissipation of the ADS7822 scales directly Sup 10 TA= 25°C with conversion rate. So, the first step to achieving V = 2.7V CC the lowest power dissipation is to find the lowest V = 2.5V REF conversion rate that will satisfy the requirements of fCLK= 16·fSAMPLE 1 thesystem. 0.1 1 10 100 In addition, the ADS7822 goes into power-down Sample Rate (kHz) mode under two conditions: when the conversion is complete and whenever CS is high (see Figure 22). Figure25.Scalingf ReducestheSupply CLK Ideally, each conversion should occur as quickly as CurrentOnlySlightlywiththeSampleRate possible; preferably, at a 1.2MHz clock rate. This way, the converter spends the longest possible time in the power-down mode. This is very important since the converter not only uses power on each DCLOCK Copyright©1996–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):ADS7822

ADS7822 www.ti.com SBAS062C–JANUARY1996–REVISEDAUGUST2007 There is an important distinction between the power-down mode that is entered after a conversion Power dissipation can also be reduced by lowering is complete and the full power-down mode that is the power-supply voltage and the reference voltage. enabled when CS is high. While both shutdown the The ADS7822 operates over a V range of 2.0V to analog section, the digital section is completely CC 5.25V. It will run up to a 200kHz throughput rate over shutdown only when CS is high. Thus, if CS is left a supply range of 4.75V to 5.25V; therefore, it can be low at the end of a conversion and the converter is clocked at up to 3.2MHz. However, at voltages below continually clocked, the power consumption will not 2.7V, the converter does not run at a 75kHz sample beaslowaswhenCSishigh;seeFigure26formore rate. See the Typical Characteristic curves for more information. information regarding power-supply voltage and maximumsamplerate. 10.0 T = 25°C A V = 2.7V ShortCycling CC 8.0 V = 2.5V REF A) fCLK= 16·fSAMPLE Another way of saving power is to use the CS signal m 6.0 to short-cycle the conversion. Because the ADS7822 nt ( places the latest data bit on the D line as it is e OUT urr 4.0 CSLOW (GND) generated, the converter can easily be short-cycled. C y This term means that the conversion can be pl p 2.0 terminated at any time. For example, if only eight bits u S of the conversion result are needed, then the 0.0 conversion can be terminated (by pulling CS high) CSHIGH (VCC) 0.050 aftertheeighthbithasbeenclockedout. 0.00 0.1 1 10 100 This technique can be used to lower the power Sample Rate (kHz) dissipation (or to increase the conversion rate) in those applications where an analog signal is being Figure26.ShutdownCurrentwithCSHighis monitored until some condition becomes true. For Typically50nA,RegardlessoftheClock. example, if the signal is outside a predetermined ShutdownCurrentwithCSLowvarieswith range, the full 12-bit conversion result may not be SampleRate. needed. If so, the conversion can be terminated after the first n-bits, where n might be as low as 3 or 4. This results in lower power dissipation in both the converter and the rest of the system, because they spendmoretimeinthepower-downmode. 14 SubmitDocumentationFeedback Copyright©1996–2007,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7822

ADS7822 www.ti.com SBAS062C–JANUARY1996–REVISEDAUGUST2007 LAYOUT Also, keep in mind that the ADS7822 offers no inherent rejection of noise or voltage variation in For optimum performance, care should be taken with regards to the reference input. This is of particular the physical layout of the ADS7822 circuitry. This is concern when the reference input is tied to the power particularly true if the reference voltage is low and/or supply. Any noise and ripple from the supply will the conversion rate is high. At a 75kHz conversion appear directly in the digital results. While rate, the ADS7822 makes a bit decision every 830ns. high-frequency noise can be filtered out as described If the supply range is limited to 4.75V to 5.25V, then in the previous paragraph, voltage variation due to up to a 200kHz conversion rate can be used, which the line frequency (50Hz or 60Hz), can be difficult to reduces the bit decision time to 312ns. That is, for remove. each subsequent bit decision, the digital output must be updated with the results of the last bit decision, The GND pin on the ADS7822 should be placed on a the capacitor array appropriately switched and clean ground point. In many cases, this will be the charged, and the input to the comparator settled to a analog ground. Avoid connecting the GND pin too 12-bitlevelallwithinoneclockcycle. close to the grounding point for a microprocessor, microcontroller, or digital signal processor. If needed, The basic SAR architecture is sensitive to spikes on run a ground trace directly from the converter to the the power supply, reference, and ground connections power-supply connection point. The ideal layout will that occur just prior to latching the comparator output. include an analog ground plane for the converter and Thus, during any single conversion for an n-bit SAR associatedanalogcircuitry. converter, there are n windows in which large external transient voltages can easily affect the APPLICATION CIRCUITS conversion result. Such spikes might originate from switching power supplies, digital logic, and Figure 27 and Figure 28 show some typical high-power devices, to name a few. This particular application circuits for the ADS7822. Figure 27 uses source of error can be very difficult to track down if an ADS7822 and a multiplexer to provide for a the glitch is almost synchronous to the converter flexible data acquisition circuit. A resistor string DCLOCK signal because the phase difference provides for various voltages at the multiplexer input. between the two changes with time and temperature, The selected voltage is buffered and driven into V . REF causingsporadicmisoperation. As shown in Figure 27, the input range of the ADS7822 is programmable to 100mV, 200mV, With this in mind, power to the ADS7822 should be 300mV, or 400mV. The 100mV range would be clean and well-bypassed. A 0.1μF ceramic bypass usefulforsensorssuchasthethermocoupleshown. capacitor should be placed as close to the ADS7822 package as possible. In addition, a 1μF to 10μF Figure 28 shows a basic data acquisition system. The capacitor and a 5Ω or 10Ω series resistor can be ADS7822 input range is 0V to V , as the reference CC usedtolowpassfilteranoisysupply. input is connected directly to the power supply. The 5Ω resistor and 1μF to 10μF capacitor filter the The reference should be similarly bypassed with a microcontroller noise on the supply, as well as any 0.1μF capacitor. Again, a series resistor and large high-frequency noise from the supply itself. The exact capacitor can be used to lowpass filter the reference values should be picked such that the filter provides voltage. If the reference voltage originates from an op adequaterejectionofthenoise. amp, be careful that the op amp can drive the bypass capacitor without oscillation (the series resistor can help in this case). Keep in mind that while the ADS7822 draws very little current from the reference on average, there are still instantaneous current demandsplacedontheexternalreferencecircuitry. Copyright©1996–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):ADS7822

ADS7822 www.ti.com SBAS062C–JANUARY1996–REVISEDAUGUST2007 +3V +3V +3V R 8 26kW 0.4V R 7 R 5W 9 R1 OPA237 1kW D1 519R5k02WkW 1RM6W 50R03kW VREF DCL0O.C1Cm2KF U2 10Cm1F Mux 1Rk1W0 00..32VV R TC1 TC2 0.C1m3F ADS7822 DCOSU/STHDN A0 1k1W1 0.1V Thermocouple A1 R TC3 1RkW4 10Cm4F 50R05W 0.C1m5F U1 P U3 1k1W2 ISO Thermal Block 3-Wire Interface U 4 Figure27.ThermocoupleApplicationUsingaMuxtoScaletheInputRangeoftheADS7822 +2.7V to +3.6V 5W + 1mF to 10mF ADS7822 V V REF CC +1mF to 0.1mF 10mF +In CS Microcontroller -In DOUT GND DCLOCK Figure28.BasicDataAcquisitionSystem 16 SubmitDocumentationFeedback Copyright©1996–2007,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7822

ADS7822 www.ti.com SBAS062C–JANUARY1996–REVISEDAUGUST2007 Revision History ChangesfromRevisionB(May2006)toRevisionC...................................................................................................... Page • Added–GNDtoabsoluteinputrangetestconditions.......................................................................................................... 3 • Added–GNDtoabsoluteinputrangetestconditions.......................................................................................................... 3 • ChangedV minfrom3.6Vto2.7V................................................................................................................................... 3 CC • ChangedV maxfrom5.25Vto3.6V................................................................................................................................ 3 CC • ChangedV minfrom3.6Vto2.7V................................................................................................................................... 3 CC • ChangedV maxfrom5.25Vto3.6V................................................................................................................................ 3 CC • ChangedV minfrom3.6Vto2.7V................................................................................................................................... 3 CC • ChangedV maxfrom5.25Vto3.6V................................................................................................................................ 3 CC • Added–GNDtoabsoluteinputrangetestconditions.......................................................................................................... 4 • Added–GNDtoabsoluteinputrangetestconditions.......................................................................................................... 4 Copyright©1996–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):ADS7822

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS7822E/250 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A22 & no Sb/Br) ADS7822E/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A22 & no Sb/Br) ADS7822E/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A22 & no Sb/Br) ADS7822E/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A22 & no Sb/Br) ADS7822EB/250 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A22 & no Sb/Br) ADS7822EB/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A22 & no Sb/Br) ADS7822EB/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A22 & no Sb/Br) ADS7822EB/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A22 & no Sb/Br) ADS7822EC/250 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A22 & no Sb/Br) ADS7822EC/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A22 & no Sb/Br) ADS7822EC/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 A22 & no Sb/Br) ADS7822U ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7822U ADS7822U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7822U ADS7822UB ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7822U B ADS7822UB/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7822U B ADS7822UB/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7822U B Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS7822UBG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7822U B ADS7822UC ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7822U C ADS7822UC/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7822U C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ADS7822 : •Automotive: ADS7822-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS7822E/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7822E/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7822EB/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7822EB/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7822EC/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7822EC/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7822U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ADS7822UB/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ADS7822UC/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS7822E/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS7822E/2K5 VSSOP DGK 8 2500 350.0 350.0 43.0 ADS7822EB/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS7822EB/2K5 VSSOP DGK 8 2500 350.0 350.0 43.0 ADS7822EC/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS7822EC/2K5 VSSOP DGK 8 2500 350.0 350.0 43.0 ADS7822U/2K5 SOIC D 8 2500 367.0 367.0 35.0 ADS7822UB/2K5 SOIC D 8 2500 367.0 367.0 35.0 ADS7822UC/2K5 SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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