ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE FEATURES APPLICATIONS 1 • 2.7Vto5.5VAnalogSupply,LowPower: • Communications 23 – 13.7mW(1MHz,+VA=3V,+VBD=1.8V) • TransducerInterface • 1MHzSamplingRate3V≤+VA≤5.5V, • MedicalInstruments 900kHzSamplingRate2.7V≤+VA≤3V • Magnetometers • ExcellentDCPerformance: • IndustrialProcessControl • DataAcquisitionSystems – ±0.15LSBTyp,±0.5LSBMaxINL • AutomaticTestEquipment – ±0.12LSBTyp,±0.5LSBMaxDNL – ±0.8mVMaxOffsetErrorat3V DESCRIPTION – ±1.25mVMaxOffsetErrorat5V The ADS7229 is a low-power, 12-bit, 1MSPS • ExcellentACPerformanceatf =10kHzwith I analog-to-digital converter (ADC) with a unipolar 73.9dBSNR,93.4dBSFDR,–88.5dBTHD input. The device includes a 12-bit capacitor-based • Built-InConversionClock(CCLK) successive approximation register (SAR) ADC with • 1.65Vto5.5VI/OSupply: inherentsample-and-hold. – SPI™/DSP-CompatibleSerialInterface The ADS7230 is based on the same core and includes a 2-to-1 input MUX with a programmable – SCLKupto50MHz TAG bit output option. Both the ADS7229 and • ComprehensivePower-DownModes: ADS7230 offer a high-speed, wide voltage serial – DeepPower-Down interface and are capable of daisy-chain mode operationwhenmultipleconvertersareused. – NapPower-Down – AutoNapPower-Down These devices are available in 4 × 4 QFN and • UnipolarInputRange:0VtoV TSSOP-16 packages, and are fully specified for REF operation over the industrial –40°C to +85°C • SoftwareReset temperaturerange. • GlobalCONVST(IndependentofCS) • ProgrammableStatus/PolarityEOC/INT LowPower,High-SpeedSARConverterFamily • 4×4QFN-16andTSSOP-16Packages Type/Speed 500kSPS 1MSPS • Multi-ChipDaisy-ChainMode Single ADS8327 ADS8329 16-bitsingle-ended • ProgrammableTAGBitOutput Dual ADS8328 ADS8330 • Auto/ManualChannelSelectMode(ADS7230) 14-bitsingle-ended Single — ADS7279 Dual — ADS7280 Single — ADS7229 12-bitsingle-ended Dual — ADS7230 ADS7230 ADS7229 SAR OLUATTPCUHT SDO and +IN1 NC TRI-STATE DRIVER + +IN0 +IN _ CDAC FS/CS CONVERSION COM -IN COMPARATOR and SCLK CONTROL SDI REF+ OSC LOGIC CONVST REF EOC/INT/CDI 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. SPIisatrademarkofMotorola,Inc. 2 Allothertrademarksarethepropertyoftheirrespectiveowners. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2008–2009,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION(1) MAXIMUM MAXIMUM MAXIMUM INTEGRAL DIFFERENTIAL OFFSET TRANSPORT LINEARITY LINEARITY ERROR PACKAGE PACKAGE TEMPERATURE ORDERING MEDIA, MODEL (LSB) (LSB) (mV) TYPE DESIGNATOR RANGE INFORMATION QUANTITY ADS7229IRSAT Smalltapeandreel,250 4×4QFN-16 RSA ADS7229IRSAR Tapeandreel,3000 ADS7229I ±0.5 ±0.5 ±1.25 –40°Cto+85°C ADS7229IPW Tube,90 TSSOP-16 PW ADS7229IPWR Tapeandreel,2000 ADS7230IRSAT Smalltapeandreel,250 4×4QFN-16 RSA ADS7230IRSAR Tapeandreel,3000 ADS7230I ±0.5 ±0.5 ±1.25 –40°Cto+85°C ADS7230IPW Tube,90 TSSOP-16 PW ADS7230IPWR Tapeandreel,2000 (1) ForthemostcurrentpackageandorderinginformationseethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS(1) Overoperatingfree-airtemperaturerange,unlessotherwisenoted. ADS7229,ADS7230 UNIT +INtoAGND –0.3to+VA+0.3 V Voltage –INtoAGND –0.3to+VA+0.3 V +VAtoAGND –0.3to7 V +REFtoAGND –0.3to+VA+0.3 V Voltagerange –REFtoAGND –0.3to0.3 V +VBDtoBDGND –0.3to7 V AGNDtoBDGND –0.3to0.3 V DigitalinputvoltagetoBDGND –0.3to+VBD+0.3 V DigitaloutputvoltagetoBDGND –0.3to+VBD+0.3 V T Operatingfree-airtemperaturerange –40to+85 °C A T Storagetemperaturerange –65to+150 °C STG T J Junctiontemperature +150 °C max 4×4QFN-16 Powerdissipation (TJmax–TA)/q JA package q thermalimpedance 47 °C/W JA TSSOP-16 Powerdissipation (TJmax–TA)/q JA package q thermalimpedance 86 °C/W JA (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 2 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 ELECTRICAL CHARACTERISTICS AtT =–40°Cto+85°C,+VA=4.5Vto5.5V,+VBD=+1.65Vto+5.5V,V =5V,andf =1MHz,unlessotherwise A REF SAMPLE noted. ADS7229,ADS7230 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ANALOGINPUT FSR Full-scaleinputvoltage(1) +IN–(–IN)or(+INx–COM) 0 VREF V +IN,+IN0,+IN1 AGND–0.2 +VA+0.2 Absoluteinputvoltage V –INorCOM AGND–0.2 AGND+0.2 Inputcapacitance 45 pF Noongoingconversion, Inputleakagecurrent 50 nA dcinput Atdc 109 Inputchannelisolation,ADS7230only dB VI=±1.25VPPat50kHz 101 SYSTEMPERFORMANCE Resolution 12 Bits NMC Nomissingcodes 12 Bits INL Integrallinearity –0.5 ±0.15 0.5 LSB(2) DNL Differentiallinearity –0.5 ±0.12 0.5 LSB(2) EO Offseterror(3) –1.25 ±0.3 1.25 mV Offseterrordrift FSR=5V ±0.2 ppm/°C EG Gainerror –0.1 ±0.002 0.1 %FSR Gainerrordrift ±0.5 ppm/°C Atdc 70 CMRR Common-moderejectionratio dB VI=0.4VPPat1MHz 50 Noise 33 m VRMS PSRR Power-supplyrejectionratio AtFFFFhoutputcode(3) 78 dB SAMPLINGDYNAMICS tCONV Conversiontime 18 CCLK tSAMPLE1 Manualtrigger 3 Acquisitiontime CCLK tSAMPLE2 Autotrigger 3 Throughputrate 1 MHz Aperturedelay 5 ns Aperturejitter 10 ps Stepresponse 100 ns Overvoltagerecovery 100 ns (1) Idealinputspan;doesnotincludegainoroffseterror. (2) LSBmeansleastsignificantbit. (3) Measuredrelativetoanidealfull-scaleinput[(+IN)–(–IN)]of4.096Vwhen+VA=5V. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) AtT =–40°Cto+85°C,+VA=4.5Vto5.5V,+VBD=+1.65Vto+5.5V,V =5V,andf =1MHz,unlessotherwise A REF SAMPLE noted. ADS7229,ADS7230 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DYNAMICCHARACTERISTICS THD Totalharmonicdistortion(4) VIN=5VPPat10kHz –88.5 dB VIN=5VPPat100kHz –85.5 VIN=5VPPat10kHz 73.9 SNR Signal-to-noiseratio dB VIN=5VPPat100kHz 72 73.8 VIN=5VPPat10kHz 73.7 SINAD Signal-to-noise+distortion dB VIN=5VPPat100kHz 73.3 VIN=5VPPat10kHz 93.4 SFDR Spurious-freedynamicrange dB VIN=5VPPat100kHz 90.5 –3dBsmall-signalbandwidth 30 MHz CLOCK Internalconversionclockfrequency 21 23 24.5 MHz UsedasI/Oclockonly 50 SCLKexternalserialclock MHz AsI/Oclockandconversionclock 1 42 EXTERNALVOLTAGEREFERENCEINPUT Input VREF[(REF+)–(REF–)] 0.3 +VA VREF reference V range (REF–)–AGND –0.1 0.1 Resistance(5) Referenceinput 40 kΩ DIGITALINPUT/OUTPUT Logicfamily—CMOS VIH High-levelinputvoltage 5.5V≥+VBD≥4.5V 0.65×(+VBD) +VBD+0.3 V 0.35× VIL Low-levelinputvoltage 5.5V≥+VBD≥4.5V –0.3 (+VBD) V II Inputcurrent VI=+VBDorBDGND –50 50 nA CI Inputcapacitance 5 pF 5.5V≥+VBD≥4.5V, VOH High-leveloutputvoltage IO=100m A +VBD–0.6 +VBD V 5.5V≥+VBD≥4.5V, VOL Low-leveloutputvoltage IO=100m A 0 0.4 V CO Outputcapacitance 5 pF CL Loadcapacitance 30 pF Dataformat—straightbinary POWER-SUPPLYREQUIREMENTS Power-supply +VBD 1.65 3.3 5.5 V voltage +VA 4.5 5 5.5 V 1MHzsamplerate 5.7 7.0 mA Supplycurrent NaporAutoNapmode 0.3 0.5 Deeppower-downmode 4 1 m A 1MSPS,BVDD=1.8V 0.1 0.5 BufferI/Osupplycurrent mA 1MSPS,BVDD=3V 0.5 1.2 AVDD=5V,BVDD=1.8V 28.8 36.5 Powerdissipation mW AVDD=5V,BVDD=3V 30.0 38.6 TEMPERATURERANGE TA Operatingfree-airtemperature –40 +85 °C (4) Calculatedonthefirstnineharmonicsoftheinputfrequency. (5) Canvary±30%. 4 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 ELECTRICAL CHARACTERISTICS AtT =–40°Cto+85°C,+VA=2.7Vto3.6V,+VBD=1.65Vto1.5×(+VA),V =2.5V,f =1MHzfor3V≤+VA≤ A REF SAMPLE 3.6V,andf =900kHzfor3V<+VA≤2.7Vusingexternalclock,unlessotherwisenoted. SAMPLE ADS7229,ADS7230 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ANALOGINPUT FSR Full-scaleinputvoltage(1) +IN–(–IN)or(+INx–COM) 0 VREF V +IN,+IN0,+IN1 AGND–0.2 +VA+0.2 Absoluteinputvoltage V –INorCOM AGND–0.2 AGND+0.2 Inputcapacitance 45 pF Noongoingconversion, Inputleakagecurrent 50 nA dcInput Atdc 108 Inputchannelisolation,ADS7230only dB VI=±1.25VPPat50kHz 101 SYSTEMPERFORMANCE Resolution 12 Bits Nomissingcodes 12 Bits INL Integrallinearity –0.5 ±0.15 0.5 LSB(2) DNL Differentiallinearity –0.5 ±0.12 0.5 LSB(2) EO Offseterror(3) –0.8 ±0.07 0.8 mV Offseterrordrift FSR=2.5V ±0.1 ppm/°C EG Gainerror –0.1 ±0.008 0.1 %FSR Gainerrordrift ±0.3 ppm/°C Atdc 70 CMRR Common-moderejectionratio dB VI=0.4VPPat1MHz 50 Noise 33 m VRMS PSRR Power-supplyrejectionratio AtFFFFhoutputcode(3) 78 dB SAMPLINGDYNAMICS tCONV Conversiontime 18 CCLK tSAMPLE1 Manualtrigger 3 Acquisitiontime CCLK tSAMPLE2 Autotrigger 3 2.7V≤+VA<3.0V 0.9 Throughputrate MHz 3.0V≤+VA≤3.64V 1 Aperturedelay 5 ns Aperturejitter 10 ps Stepresponse 100 ns Overvoltagerecovery 100 ns (1) Idealinputspan;doesnotincludegainoroffseterror. (2) LSBmeansleastsignificantbit. (3) Measuredrelativetoanidealfull-scaleinput[(+IN)–(–IN)]of2.5Vwhen+VA=3V. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) AtT =–40°Cto+85°C,+VA=2.7Vto3.6V,+VBD=1.65Vto1.5×(+VA),V =2.5V,f =1MHzfor3V≤+VA≤ A REF SAMPLE 3.6V,andf =900kHzfor3V<+VA≤2.7Vusingexternalclock,unlessotherwisenoted. SAMPLE ADS7229,ADS7230 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DYNAMICCHARACTERISTICS THD Totalharmonicdistortion(4) VIN=2.5VPPat10kHz –96.8 dB VIN=2.5VPPat100kHz –88.4 VIN=2.5VPPat10kHz 72 73.2 SNR Signal-to-noiseratio dB VIN=2.5VPPat100kHz 72 VIN=2.5VPPat10kHz 73.1 SINAD Signal-to-noise+distortion dB VIN=2.5VPPat100kHz 72.1 VIN=2.5VPPat10kHz 95.9 SFDR Spurious-freedynamicrange dB VIN=2.5VPPat100kHz 91.5 –3dBsmall-signalbandwidth 30 MHz CLOCK Internalconversionclockfrequency 21 23 23.5 MHz UsedasI/Oclockonly 42 SCLKexternalserialclock MHz AsI/Oclockandconversionclock 1 42 EXTERNALVOLTAGEREFERENCEINPUT fSAMPLE≤500kSPS, 0.3 2.525 2.7V≤+VA<3V fSAMPLE≤500kSPS, 0.3 3 3V≤+VA<3.6V Inputreference VREF[(REF+)–(REF–)] VREF range fSAMPLE>500kSPS, 2.475 2.525 V 2.7V≤+VA<3V fSAMPLE>500kSPS, 2.475 3 3V≤+VA≤3.6V (REF–)–AGND –0.1 0.1 Resistance(5) Referenceinput 40 kΩ DIGITALINPUT/OUTPUT Logicfamily—CMOS VIH High-levelinputvoltage (+VA×1.5)V≥+VBD≥1.65V 0.65×(+VBD) +VBD+0.3 V VIL Low-levelinputvoltage (+VA×1.5)V≥+VBD≥1.65V –0.3 0.35×(+VBD) V II Inputcurrent VI=+VBDorBDGND –50 50 nA CI Inputcapacitance 5 pF (+VA×1.5)V≥+VBD≥1.65V, VOH High-leveloutputvoltage IO=100m A +VBD–0.6 +VBD V (+VA×1.5)V≥+VBD≥1.65V, VOL Low-leveloutputvoltage IO=100m A 0 0.4 V CO Outputcapacitance 5 pF CL Loadcapacitance 30 pF Dataformat—straightbinary (4) Calculatedonthefirstnineharmonicsoftheinputfrequency. (5) Canvary±30%. 6 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 ELECTRICAL CHARACTERISTICS (continued) AtT =–40°Cto+85°C,+VA=2.7Vto3.6V,+VBD=1.65Vto1.5×(+VA),V =2.5V,f =1MHzfor3V≤+VA≤ A REF SAMPLE 3.6V,andf =900kHzfor3V<+VA≤2.7Vusingexternalclock,unlessotherwisenoted. SAMPLE ADS7229,ADS7230 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT POWER-SUPPLYREQUIREMENTS +VBD 1.65 +VA 1.5×(+VA) V Power-supply voltage +VA fs≤1MHz 3 3.6 V fs≤900kHz 2.7 3.6 1MHzsamplerate, 4.5 6.0 3V≤+VA≤3.6V 900kHzsamplerate, mA Supplycurrent 2.7V≤+VA≤3V 4.2 NaporAutoNapmode 0.25 0.4 Deeppower-downmode 0.001 1 m A 1MSPS,BVDD=1.8V 0.1 0.5 BufferI/Osupplycurrent mA 1MSPS,BVDD=3V 0.5 1.2 AVDD=3V,BVDD=1.8V 13.7 18.9 Powerdissipation mW AVDD=3V,BVDD=3V 15.0 21.6 TEMPERATURERANGE TA Operatingfree-airtemperature –40 +85 °C Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com TIMING CHARACTERISTICS(1)(2): 5V Allspecificationstypicalat–40°Cto+85°Cand+VA=+VBD=5V,unlessotherwisenoted. ADS7229,ADS7230 PARAMETER MIN TYP MAX UNIT External, 0.5 21 f =1/2f CCLK SCLK f Frequency,conversionclock,CCLK MHz CCLK Internal, 21 23 24.5 f =1/2f CCLK SCLK t Setuptime,fallingedgeofCStoEOC 1 CCLK 1 t Holdtime,fallingedgeofCStoEOC 0 ns 2 t Pulseduration,CONVSTlow 40 ns CL t Holdtime,fallingedgeofCStoEOS 20 ns 3 t Setuptime,risingedgeofCStoEOS 20 ns 4 t Holdtime,risingedgeofCStoEOS 20 ns 5 Setuptime,fallingedgeofCStofirstfalling t 5 ns 6 SCLK t Pulseduration,SCLKlow 8 t –8 ns SCLKL SCLK t Pulseduration,SCLKhigh 8 t –8 ns SCLKH SCLK I/Oclockonly 20 I/Oandconversionclock 23.8 2000 tSCLK Cycletime,SCLK I/Oclock,chainmode 20 ns I/Oandconversionclock, 23.8 2000 chainmode t Holdtime,fallingedgeofSCLKtoSDOinvalid 10pFload 2 ns H2 t Delaytime,fallingedgeofSCLKtoSDOvalid 10pFload 10 ns D1 Delaytime,fallingedgeofCStoSDOvalid, t 10pFload 8.5 ns D2 SDOMSBoutput t Setuptime,SDItofallingedgeofSCLK 8 ns S1 t Holdtime,SDItofallingedgeofSCLK 4 ns H1 Delaytime,risingedgeofCS/FStoSDOt t D3 5 ns D3 3-state Setuptime,16thfallingedgeofSCLKbefore t 10 ns 7 risingedgeofCS/FS (1) Allinputsignalsarespecifiedwitht =t =1.5ns(10%to90%ofVBD)andtimedfromavoltagelevelof(V +V )/2. r f IL IH (2) Seetimingdiagrams. 8 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 TIMING CHARACTERISTICS(1)(2): 1.8V Allspecificationstypicalat–40°Cto85°C,+VA=2.7V,and+VBD=1.8V,unlessotherwisenoted. ADS7229,ADS7230 PARAMETER MIN TYP MAX UNIT External,3V≤+VA≤3.6V, 0.5 21 f =1/2f CCLK SCLK External,2.7V≤+VA≤3V, f Frequency,conversionclock,CCLK 0.5 18.9 MHz CCLK f =1/2f CCLK SCLK Internal, 20 22.3 23.5 f =1/2f CCLK SCLK t Setuptime,fallingedgeofCStoEOC 1 CCLK 1 t Holdtime,fallingedgeofCStoEOC 0 ns 2 t Pulseduration,CONVSTlow 40 ns CL t Holdtime,fallingedgeofCStoEOS 20 ns 3 t Setuptime,risingedgeofCStoEOS 20 ns 4 t Holdtime,risingedgeofCStoEOS 20 ns 5 Setuptime,fallingedgeofCStofirstt falling t 6 5 ns 6 SCLK t Pulseduration,SCLKlow 8 t –8 ns SCLKL SCLK t Pulseduration,SCLKhigh 8 t –8 ns SCLKH SCLK Allmodes, 23.8 2000 3V≤+VA≤3.6V t Cycletime,SCLK ns SCLK Allmodes, 26.5 2000 2.7V≤+VA<3V t Holdtime,fallingedgeofSCLKtoSDOinvalid 10pFload 7.5 ns H2 t Delaytime,fallingedgeofSCLKtoSDOvalid 10pFload 16 ns D1 10pFload, 13 Delaytime,fallingedgeofCStoSDOvalid, 2.7V≤+VA≤3V t ns D2 SDOMSBoutput 10pFload, 11 3V≤+VA≤3.6V t Setuptime,SDItofallingedgeofSCLK 8 ns S1 t Holdtime,SDItofallingedgeofSCLK 4 ns H1 Delaytime,risingedgeofCS/FStoSDO t 8 ns D3 3-state Setuptime,16thfallingedgeofSCLKt t 7 10 ns 7 beforerisingedgeofCS/FS (1) Allinputsignalsarespecifiedwitht =t =1.5ns(10%to90%ofVBD)andtimedfromavoltagelevelof(V +V )/2. r f IL IH (2) Seetimingdiagrams. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com PIN ASSIGNMENTS ADS7229 ADS7230 RSAPACKAGE(QFN) RSAPACKAGE(QFN) (TOPVIEW) (TOPVIEW) -REF AGND -IN +IN -REF AGND COM +IN0 6 5 4 3 1 1 1 1 6 5 4 3 1 1 1 1 REF+ (REFIN) 1 12 RESERVED REF+ (REFIN) 1 12 +IN1 NC 2 11 +VA NC 2 11 +VA CONVST 3 10 +VBD CONVST 3 10 +VBD EOC/INT/CDI 4 9 SCLK EOC/INT/CDI 4 9 SCLK 5 6 7 8 5 6 7 8 FS/CS SDI SDO BDGND FS/CS SDI SDO DGND B CAUTION: The thermal pad is internally connected to the substrate. This pad can be connected to the analog groundorleftfloating.Keepthethermalpadseparatefromthedigitalground,ifpossible. ADS7229 ADS7230 PWPACKAGE(TSSOP) PWPACKAGE(TSSOP) (TOPVIEW) (TOPVIEW) +VA 1 16 +VBD +VA 1 16 +VBD RESERVED 2 15 SCLK +IN1 2 15 SCLK +IN 3 14 BDGND +IN0 3 14 BDGND -IN 4 13 SDO COM 4 13 SDO AGND 5 12 SDI AGND 5 12 SDI REF- 6 11 FS/CS REF- 6 11 FS/CS REF+ (REFIN) 7 10 EOC/INT/CDI REF+ (REFIN) 7 10 EOC/INT/CDI NC 8 9 CONVST NC 8 9 CONVST NC=Nointernalconnection 10 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 ADS7229TerminalFunctions NO. NAME QFN TSSOP I/O DESCRIPTION AGND 15 5 — Analogground BDGND 8 14 — Interfaceground CONVST 3 9 I Freezessample-and-hold,startsconversionwithnextrisingedgeofinternalclock Statusoutput.IfprogrammedasEOC,thispinislow(default)whenaconversionisin progress.Ifprogrammedasaninterrupt(INT),thispinislowforapreprogrammed EOC/INT/CDI 4 10 I/O durationaftertheendofconversionandvaliddataaretobeoutput.Thepolarityof EOCorINTisprogrammable.Thispincanalsobeusedasachaindatainputwhen thedeviceisoperatedindaisy-chainmode. FramesyncsignalforTMS320DSPserialinterfaceorchipselectinputforSPI FS/CS 5 11 I interfaceslaveselect(SS–). +IN 13 3 I Noninvertinginput –IN 14 4 I Invertinginput;usuallyconnectedtoground NC 2 8 — Noconnection REF+(REFIN) 1 7 I Externalreferenceinput REF– 16 6 I ConnecttoAGNDthroughindividualvia RESERVED 12 2 I ConnecttoAGNDor+VA SCLK 9 15 I Clockforserialinterface SDI 6 12 I Serialdatain SDO 7 13 O Serialdataout +VA 11 1 Analogsupply,+2.7Vto+5.5VDC +VBD 10 16 Interfacesupply ADS7230TerminalFunctions NO. NAME QFN TSSOP I/O DESCRIPTION AGND 15 5 — Analogground BDGND 8 14 — Interfaceground COM 14 4 I Commoninvertinginput;usuallyconnectedtoground CONVST 3 9 I Freezessample-and-hold,startsconversionwithnextrisingedgeofinternalclock Statusoutput.IfprogrammedasEOC,thispinislow(default)whenaconversionisin progress.Ifprogrammedasaninterrupt(INT),thispinislowforapreprogrammed EOC/INT/CDI 4 10 I/O durationaftertheendofconversionandvaliddataaretobeoutput.Thepolarityof EOCorINTisprogrammable.Thispincanalsobeusedasachaindatainputwhen thedeviceisoperatedindaisy-chainmode. FramesyncsignalforTMS320DSPserialinterfaceorchipselectinputforSPI FS/CS 5 11 I interface +IN1 12 2 I Secondnoninvertinginput +IN0 13 3 I Firstnoninvertinginput NC 2 8 — Noconnection. REF+(REFIN) 1 7 I Externalreferenceinput REF– 16 6 I ConnecttoAGNDthroughindividualvia SCLK 9 15 I Clockforserialinterface SDI 6 12 I Serialdatain(conversionstartandresetpossible) SDO 7 13 O Serialdataout +VA 11 1 Analogsupply,+2.7Vto+5.5VDC +VBD 10 16 Interfacesupply Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com MANUALTRIGGER/READWhile Sampling (use internal CCLK, EOC, andINTpolarity programmed as active low) CONVST Nth C S tCL C O O O E E E EOC Nth-1 NNtthh (active low) t = 3 CCLKs Min t =18 CCLKs SAMPLE1 CONV INT (active low) t t 2 4 FS/CS 1……………………16 1 SCLK SDO Nth-1 Nth SDI 1101b 1101b READ Result READ Result Figure1.TimingforConversionandAcquisitionCyclesforManualTrigger(ReadWhileSampling) MANUALTRIGGER/READWhile Converting (use internal CCLK, EOC, andINTpolarity programmed as active low) CONVST Nth N + 1st OS tCL OC OS E E E EOC Nth Nth + 1 (active low) t =18CCLKs t = 3 CCLKs Min CONV SAMPLE1 INT (active low) t 4 t 3 FS/CS 1……………………16 1 SCLK SDO Nth-1 Nth SDI 1101b 1101b READ Result READ Result Figure2.TimingforConversionandAcquisitionCyclesforManualTrigger(ReadWhileConverting) 12 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 AUTO TRIGGER/READ While Converting (use internal CCLK, EOC, andINTpolarity programmed as active low) CONVST= 1 S C S C S O O O O O E E E E E EOC N-1th NNtthh Nth + 1 (active low) t = 18 CCLKs t = t = 18 CCLKs t = CONV SAMPLE2 CONV SAMPLE2 3 CCLKs 3 CCLKs INT (active low) t 4 t 3 FS/CS 1……………………16 1……………………16 SCLK SDO N-2nd N-1st SDI 1101b 1101b READ Result READ Result Figure3.TimingforConversionandAcquisitionCyclesforAutotrigger(ReadWhileConverting) 1 2 3 4 11 12 13 14 15 16 SCLK t6 tSCLK tSCLKL tSCLKH t7 FS/CS tD2 tH2 tD3 SDO MSB MSB-1 MSB-2 MSB-3 LSB+1 LSB t D1 t H1 SDI orCDI MSB MSB-1 MSB-2 MSB-3 LSB+5 LSB+4 LSB+3 LSB+2 LSB+1 LSB t S1 Figure4.DetailedSPITransferTiming Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com MANUALTRIGGER/READWhile Converting (use internal CCLK, EOC, andINTpolarity programmed as active low, TAG enabled, auto channel select) CONVST Nth CH0 Nth CH1 OC OS tCL OC OS tCL OC E E E E E EOC Nth CH0 Nth CH1 (active low) t = 18 CCLKs t = t = 18 CCLKs t = CONV SAMPLE1 CONV SAMPLE1 3 CCLKs Min 3 CCLKs Min INT (active low) t 4 t 3 FS/CS 1……………………16 17 1……………………16 17 SCLK High-Z High-Z High-Z SDO N-1st CH1 Nth CH0 TAG = 1 TAG = 0 SDI 1101b 1101b READ Result READ Result Figure5.SimplifiedDualChannelTiming 14 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 TYPICAL CHARACTERISTICS At–40°Cto+85°C,V [(REF+)–(REF–)]=5Vwhen+VA=+VBD=5VorV [(REF+)–(REF–)]=2.5Vwhen+VA= REF REF +VBD=3V,f =42MHz,orV =2.5when+VA=+VBD=2.7V,f =37.8MHz,andf =dcfordccurves,f =100kHz SCLK REF SCLK I I foraccurveswith5Vsupply,andf =10kHzforaccurveswith3Vsupply,unlessotherwisenoted. I CROSSTALK DIFFERENTIALNONLINEARITY vsFREQUENCY vsFREE-AIRTEMPERATURE 110 0.30 105 0.25 B) 100 0.20 stalk (d 95 L (LSB) 0.15 3V Cros 90 5V DN 0.10 5V 85 0.05 3V 80 0 0 20 40 60 80 100 120 140 160 180 200 -40 -15 10 35 60 85 Frequency (kHz) Temperature (°C) Figure6. Figure7. INTEGRALNONLINEARITY DIFFERENTIALNONLINEARITY vsFREE-AIRTEMPERATURE vsEXTERNALCLOCKFREQUENCY 0.30 0.50 +VA = 5V 0.25 3V 0.25 0.20 DNL+ B) B) S S L (L 0.15 L (L 0 N N DNL- I D 0.10 5V -0.25 0.05 0 -0.50 -40 -15 10 35 60 85 0.1 1 10 100 Temperature (°C) f (MHz) SCLK Figure8. Figure9. INTEGRALNONLINEARITY DIFFERENTIALNONLINEARITY vsEXTERNALCLOCKFREQUENCY vsEXTERNALCLOCKFREQUENCY 0.50 0.50 +VA = 5V +VA = 3V 0.25 0.25 DNL+ B) INL+ B) S S INL (L 0 INL- DNL (L 0 DNL- -0.25 -0.25 -0.50 -0.50 0.1 1 10 100 0.1 1 10 100 f (MHz) f (MHz) SCLK SCLK Figure10. Figure11. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) At–40°Cto+85°C,V [(REF+)–(REF–)]=5Vwhen+VA=+VBD=5VorV [(REF+)–(REF–)]=2.5Vwhen+VA= REF REF +VBD=3V,f =42MHz,orV =2.5when+VA=+VBD=2.7V,f =37.8MHz,andf =dcfordccurves,f =100kHz SCLK REF SCLK I I foraccurveswith5Vsupply,andf =10kHzforaccurveswith3Vsupply,unlessotherwisenoted. I INTEGRALNONLINEARITY OFFSETVOLTAGE vsEXTERNALCLOCKFREQUENCY vsFREE-AIRTEMPERATURE 0.50 0.50 +VA = 3V 5V 0.25 INL+ V) 0.25 m INL (LSB) 0 INL- et Voltage ( 0 3V s -0.25 Off -0.25 -0.50 -0.50 0.1 1 10 100 -40 -15 10 35 60 85 f (MHz) Temperature (°C) SCLK Figure12. Figure13. OFFSETVOLTAGE GAINERROR vsSUPPLYVOLTAGE vsFREE-AIRTEMPERATURE 0.5 0.050 0.4 0.025 V) R) 3V m 0.3 S e ( %F et Voltag 0.2 n Error ( 0 5V Offs 0.1 Gai -0.025 0 -0.1 -0.050 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 -15 10 35 60 85 +VA Supply Voltage (V) Temperature (°C) Figure14. Figure15. GAINERROR POWER-SUPPLYREJECTIONRATIO vsSUPPLYVOLTAGE vsSUPPLYRIPPLEFREQUENCY 0.10 -70 5V -72 0.05 R) S 3V %F B) -74 d or ( 0 R ( n Err PSR -76 ai G -0.05 -78 -0.10 -80 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 10 20 30 40 50 60 70 80 90 100 +VA Supply Voltage (V) Frequency (kHz) Figure16. Figure17. 16 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 TYPICAL CHARACTERISTICS (continued) At–40°Cto+85°C,V [(REF+)–(REF–)]=5Vwhen+VA=+VBD=5VorV [(REF+)–(REF–)]=2.5Vwhen+VA= REF REF +VBD=3V,f =42MHz,orV =2.5when+VA=+VBD=2.7V,f =37.8MHz,andf =dcfordccurves,f =100kHz SCLK REF SCLK I I foraccurveswith5Vsupply,andf =10kHzforaccurveswith3Vsupply,unlessotherwisenoted. I SIGNAL-TO-NOISERATIO SIGNAL-TO-NOISEANDDISTORTION vsINPUTFREQUENCY vsINPUTFREQUENCY 80 80 78 78 B) 76 dB) 76 R (d 5V AD ( 5V N N S 74 SI 74 72 72 3V 3V 70 70 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 Input Frequency (kHz) Input Frequency (kHz) Figure18. Figure19. TOTALHARMONICDISTORTION SPURIOUS-FREEDYNAMICRANGE vsINPUTFREQUENCY vsINPUTFREQUENCY -80 100 3V -85 95 5V B) B) D (d -90 R (d 90 A D 5V N F SI S -95 85 3V -100 80 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 Input Frequency (kHz) Input Frequency (kHz) Figure20. Figure21. SIGNAL-TO-NOISERATIO SIGNAL-TO-NOISEANDDISTORTION vsFULL-SCALERANGE vsFULL-SCALERANGE 76 76 fIN= 10kHz 5V fIN= 10kHz 5V 74 74 B) 72 dB) 72 R (d 3V AD ( 3V N N S 70 SI 70 68 68 66 66 0 1 2 3 4 5 0 1 2 3 4 5 Full-Scale Range (V) Full-Scale Range (V) Figure22. Figure23. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) At–40°Cto+85°C,V [(REF+)–(REF–)]=5Vwhen+VA=+VBD=5VorV [(REF+)–(REF–)]=2.5Vwhen+VA= REF REF +VBD=3V,f =42MHz,orV =2.5when+VA=+VBD=2.7V,f =37.8MHz,andf =dcfordccurves,f =100kHz SCLK REF SCLK I I foraccurveswith5Vsupply,andf =10kHzforaccurveswith3Vsupply,unlessotherwisenoted. I TOTALHARMONICDISTORTION SPURIOUS-FREEDYNAMICRANGE vsFULL-SCALERANGE vsFULL-SCALERANGE -75 100 fIN= 10kHz fIN= 10kHz -80 95 3V 5V THD (dB) --8950 5V SFDR (dB) 90 3V 85 -95 -100 80 0 1 2 3 4 5 0 1 2 3 4 5 Full-Scale Range (V) Full-Scale Range (V) Figure24. Figure25. TOTALHARMONICDISTORTION SPURIOUS-FREEDYNAMICRANGE vsFREE-AIRTEMPERATURE vsFREE-AIRTEMPERATURE -80 100 3V -85 95 THD (dB) -90 5V SFDR (dB) 90 5V -95 85 3V -100 80 -40 -15 10 35 60 85 -40 -15 10 35 60 85 Temperature (°C) Temperature (°C) Figure26. Figure27. SIGNAL-TO-NOISERATIO SIGNAL-TO-NOISEANDDISTORTION vsFREE-AIRTEMPERATURE vsFREE-AIRTEMPERATURE 75 75 74 74 B) 5V dB) 5V NR (d 3V NAD ( S SI 73 73 3V 72 72 -40 -15 10 35 60 85 -40 -15 10 35 60 85 Temperature (°C) Temperature (°C) Figure28. Figure29. 18 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 TYPICAL CHARACTERISTICS (continued) At–40°Cto+85°C,V [(REF+)–(REF–)]=5Vwhen+VA=+VBD=5VorV [(REF+)–(REF–)]=2.5Vwhen+VA= REF REF +VBD=3V,f =42MHz,orV =2.5when+VA=+VBD=2.7V,f =37.8MHz,andf =dcfordccurves,f =100kHz SCLK REF SCLK I I foraccurveswith5Vsupply,andf =10kHzforaccurveswith3Vsupply,unlessotherwisenoted. I EFFECTIVENUMBEROFBITS INTERNALCLOCKFREQUENCY vsFREE-AIRTEMPERATURE vsSUPPLYVOLTAGE 12.50 24.0 Hz) 23.5 M 12.25 y ( Bits) 5V quenc 23.0 B ( 12.00 Fre 22.5 O k N c E Clo 22.0 11.75 nal 3V nter 21.5 I 11.50 21.0 -40 -15 10 35 60 85 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Temperature (°C) +VA Supply Voltage (V) Figure30. Figure31. INTERNALCLOCKFREQUENCY ANALOGSUPPLYCURRENT vsFREE-AIRTEMPERATURE vsSUPPLYVOLTAGE 24.0 7.0 f = 1MSPS MHz) 23.5 mA) 6.5 S equency ( 23.0 Current ( 6.0 al Clock Fr 2222..50 og Supply 55..50 n al nter 21.5 An 4.5 I 22.0 4.0 -40 -15 10 35 60 85 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Temperature (°C) +VA Supply Voltage (V) Figure32. Figure33. ANALOGSUPPLYCURRENT ANALOGSUPPLYCURRENT vsSUPPLYVOLTAGE vsSUPPLYVOLTAGE 400 10 NAP Mode PD Mode A) 360 A) 8 m n nt ( nt ( e e urr 320 urr 6 C C y y pl pl p p u 280 u 4 S S g g o o al al An 240 An 2 200 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 +VA Supply Voltage (V) +VA Supply Voltage (V) Figure34. Figure35. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) At–40°Cto+85°C,V [(REF+)–(REF–)]=5Vwhen+VA=+VBD=5VorV [(REF+)–(REF–)]=2.5Vwhen+VA= REF REF +VBD=3V,f =42MHz,orV =2.5when+VA=+VBD=2.7V,f =37.8MHz,andf =dcfordccurves,f =100kHz SCLK REF SCLK I I foraccurveswith5Vsupply,andf =10kHzforaccurveswith3Vsupply,unlessotherwisenoted. I ANALOGSUPPLYCURRENT ANALOGSUPPLYCURRENT vsSAMPLERATE vsSAMPLERATE 7 1.4 Auto NAP PD Mode A) 6 A) 1.2 m m nt ( 5 nt ( 1.0 5V e e Curr 4 Curr 0.8 Supply 3 5V Supply 0.6 3V og 2 og 0.4 al al n n A 3V A 1 0.2 0 0 1 10 100 1000 0 10 20 30 40 50 60 70 80 90 Sample Rate (kSPS) Sample Rate (kSPS) Figure36. Figure37. ANALOGSUPPLYCURRENT ANALOGSUPPLYCURRENT vsFREE-AIRTEMPERATURE vsFREE-AIRTEMPERATURE 7.0 0.35 f = 1MSPS NAP Mode S 6.5 5V A) 5V A) m m nt ( 6.0 nt ( 0.30 urre 5.5 urre C C y 5.0 y 0.25 pl pl p p Su 4.5 Su 3V og 3V og al 4.0 al 0.20 n n A A 3.5 3.0 0.15 -40 -15 10 35 60 85 -40 -15 10 35 60 85 Temperature (°C) Temperature (°C) Figure38. Figure39. INTEGRALNONLINEARITY DIFFERENTIALNONLINEARITY 0.25 0.25 +VA = 5V +VA = 5V 0.20 0.20 0.15 0.15 0.10 0.10 INL(Bits) -00..00550 DNL (Bits) -00..00550 -0.10 -0.10 -0.15 -0.15 -0.20 -0.20 -0.25 -0.25 0 1000 2000 3000 4000 0 1000 2000 3000 4000 Code Code Figure40. Figure41. 20 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 TYPICAL CHARACTERISTICS (continued) At–40°Cto+85°C,V [(REF+)–(REF–)]=5Vwhen+VA=+VBD=5VorV [(REF+)–(REF–)]=2.5Vwhen+VA= REF REF +VBD=3V,f =42MHz,orV =2.5when+VA=+VBD=2.7V,f =37.8MHz,andf =dcfordccurves,f =100kHz SCLK REF SCLK I I foraccurveswith5Vsupply,andf =10kHzforaccurveswith3Vsupply,unlessotherwisenoted. I INTEGRALNONLINEARITY DIFFERENTIALNONLINEARITY 0.25 0.25 +VA = 3V +VA = 3V 0.20 0.20 0.15 0.15 0.10 0.10 INL (Bits) -00..00505 DNL (Bits) -00..00505 -0.10 -0.10 -0.15 -0.15 -0.20 -0.20 -0.25 -0.25 0 1000 2000 3000 4000 0 1000 2000 3000 4000 Code Code Figure42. Figure43. FFT FFT 0 0 5kHz Input 10kHz Input -20 +VA = 3V -20 +VA = 3V -40 VfSRE=F 1=M 2S.5PVS -40 VfSRE=F 1=M 2S.5PVS dB) -60 dB) -60 e ( e ( ud -80 ud -80 plit plit m -100 m -100 A A -120 -120 -140 -140 -160 -160 0 100 200 300 400 500 0 100 200 300 400 500 Frequency (kHz) Frequency (kHz) Figure44. Figure45. FFT FFT 0 0 100kHz Input 5kHz Input -20 +VA = 3V -20 +VA = 5V f = 1MSPS f = 1MSPS -40 VS = 2.5V -40 SV = 5V REF REF dB) -60 dB) -60 e ( e ( ud -80 ud -80 plit plit m -100 m -100 A A -120 -120 -140 -140 -160 -160 0 100 200 300 400 500 0 100 200 300 400 500 Frequency (kHz) Frequency (kHz) Figure46. Figure47. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) At–40°Cto+85°C,V [(REF+)–(REF–)]=5Vwhen+VA=+VBD=5VorV [(REF+)–(REF–)]=2.5Vwhen+VA= REF REF +VBD=3V,f =42MHz,orV =2.5when+VA=+VBD=2.7V,f =37.8MHz,andf =dcfordccurves,f =100kHz SCLK REF SCLK I I foraccurveswith5Vsupply,andf =10kHzforaccurveswith3Vsupply,unlessotherwisenoted. I FFT FFT 0 0 10kHz Input 100kHz Input -20 +VA = 5V -20 +VA = 5V f = 1MSPS f = 1MSPS -40 SV = 5V -40 SV = 5V REF REF dB) -60 dB) -60 e ( e ( ud -80 ud -80 plit plit m -100 m -100 A A -120 -120 -140 -140 -160 -160 0 100 200 300 400 500 0 100 200 300 400 500 Frequency (kHz) Frequency (kHz) Figure48. Figure49. I/OSUPPLYCURRENT vsI/OSUPPLYVOLTAGE CODEHISTOGRAM 3.0 9000 REF = 2.5V 8000 2.5 7000 2.0 e 6000 A) od m C 5000 I(BVDD 11..50 Hits per 43000000 2000 0.5 1000 0 0 7799135791 357913579135 3 4 5 6 7 1.1.1.1.2.2.2.2.2.3. 3.3.3.3.4.4.4.4.4.5.5.5. BVDD (V) Output Code Figure50. Figure51. CODEHISTOGRAM 9000 REF = 5V 8000 7000 e 6000 d o C 5000 er p 4000 s Hit 3000 2000 1000 0 2330 2331 2332 2333 2334 Output Code Figure52. 22 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 THEORY OF OPERATION The ADS7229 and ADS7230 are two high-speed, low power, successive approximation register (SAR) analog-to-digital converters (ADCs) that use an external reference. The architecture is based on charge redistribution,whichinherentlyincludesasample-and-holdfunction. These devices have an internal clock that is used to run the conversion; these devices can also be programmed toruntheconversionbasedontheexternalserialclock,SCLK. The ADS7229 has one analog input. The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversionisinprogress,both+INand–INinputsaredisconnectedfromanyinternalfunction. TheADS7230 has two inputs. Both inputs share the same common pin, COM. The negative input is the same as the –IN pin for the ADS7229. The ADS7230 can be programmed to select a channel manually or can be programmedintotheautochannelselectmodetosweepbetweenchannel0andchannel1automatically. Throughoutthisdocument,thetermADS7229/30referstobothdevices,unlessspecificallynotedotherwise. ANALOG INPUT When the converter enters before hold mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. The voltage on the –IN input is limited between AGND – 0.2V and AGND + 0.2V, allowing the input to reject small signals that are common to both the +IN and –IN inputs. The +IN input has a rangeof–0.2Vto(V +0.2V).Theinputspan[(+IN)–(–IN)]islimitedto0VtoV . REF REF The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. The current into the ADS7229/30 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (45pF) to a 12-bit settling level within the minimum acquisition time (120ns). When the converter goes into hold mode, the input impedance is greater than 1GΩ. Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN and –IN inputs and the span [(+IN) – (–IN)] should be within the limits specified. Outside of these ranges, converter linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters should be used. Care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. If this input matching is not observed, the two inputs could have different settling times. This difference may result in an offset error, gain error, and linearity errors that change with temperature andinputvoltage. Device in Hold Mode 40pF 150W +IN 4pF +VA 4pF AGND 40pF 150W -IN AGND Figure53.InputEquivalentCircuit Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com Driver Amplifier Choice The analog input to the converter must be driven with a low-noise operational amplifier such as the THS4031 or OPA365. An RC filter is recommended at the input pins to low-pass filter the noise from the source. Two 20Ω resistors and a 470pF capacitor are recommended. The input to the converter is a unipolar input voltage in the rangeof0VtoV .Theminimum–3dBbandwidthofthedrivingoperationalamplifiercanbecalculatedas: REF f =(ln(2)×(n+1))/(2p ×t ) 3db ACQ wherenisequalto12,theresolution of the ADC (in the case of the ADS7229/30). When t = 120ns (minimum ACQ acquisition time), the minimum bandwidth of the driving amplifier is 12MHz. The bandwidth can be relaxed if the acquisition time is increased by the application. The OPA365 or THS4031 from Texas Instruments are recommended. The THS4031 used in the source follower configuration to drive the converter is shown in a typicalinputdriveconfiguration,Figure54.For the ADS7230, a series resistor of 0Ω should be used on the COM input(ornoresistoratall). Bipolar to Unipolar Driver In systems where the input is bipolar, the THS4031 can be used in the inverting configuration with an additional dc bias applied to its positive input to keep the input to the ADS7229/30 within the rated operating voltage range. This configuration is also recommended when the ADS7229/30 is used in signal processing applications where good SNR and THD performance are required. The dc bias can be derived from the REF5025 or the REF5040 reference voltage ICs. The input configuration shown in Figure 55 is capable of delivering better than 72dB SNR and –88.5dB THD at an input frequency of 10kHz. If bandpass filters are used to filter the input, care should be taken to ensure that the signal swing at the input of the bandpass filter is small in order to keep the distortion introduced by the filter minimal. In such cases, the gain of the circuit shown in Figure 55 can be increased to keep the input to the ADS7229/30 large in order to maintain a high SNR of the system. Note that the gain of the system from the positive input to the output of the THS4031 in such a configuration is a function of the ac signal gain. A resistor divider can be used to scale the output of the REF5025 or REF5040 to reduce the voltage at the dcinputtotheTHS4031tomaintainthevoltageattheconverterinputwithinitsratedoperatingrange. Input ADS7229 5V Signal (0V to 4V) +VA 20W THS4031 +IN 470pF -IN 50W 20W Figure54.UnipolarInputDriveConfiguration ADS7229 5V 1V DC +VA 20W THS4031 +IN 470pF Input -IN (-2SVig tnoa 2lV) 20W Figure55.BipolarInputDriveConfiguration 24 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 REFERENCE The ADS7229/30 must operate with an external reference with a range from 0.3V to 5V. A clean, low-noise, well-decoupled reference voltage on this pin is required to ensure good converter performance. A low-noise bandgap reference such as the REF5040 can be used to drive this pin. A 22m F ceramic decoupling capacitor is required between the REF+ and REF– pins of the converter. These capacitors should be placed as close as possible to the device pins. REF– should be connected to its own via to the analog ground plane with the shortest possible distance. A series resistor between the reference and the REF50xx is neither required (because the REF50xx is capable of driving a 22m F capacitor while maintaining stability) nor recommended (due toadditionalnonlinearity);seealsoFigure68. CONVERTER OPERATION The ADS7229/30 has an oscillator that is used as an internal clock that controls the conversion rate. The frequency of this clock is 21MHz minimum. The oscillator is always on unless the device is in the deep power-down state or the device is programmed for using SCLK as the conversion clock (CCLK). The minimum acquisition (sampling) time takes 3 CCLKs (equivalent to 143ns at 21MHz) and the conversion time takes 18 conversionclocks(CCLK)orapproximately857nsat21MHztocompleteoneconversion. The conversion can also be programmed to run based on the external serial clock, SCLK. This option allows a system designer to achieve system synchronization. The serial clock SCLK, is first reduced to 1/2 of its frequency before it is used as the conversion clock (CCLK). For example, with a 42MHz SCLK, this reduction provides a 21MHz clock for conversions. If it is desired to start a conversion at a specific rising edge of SCLK when the external SCLK is programmed as the source of the conversion clock (and manual conversion start is selected), the setup time between CONVST and that rising SCLK edge should be observed. This configuration ensures that the conversion is complete in 18 CCLKs (or 36 SCLKs). The minimum setup time is 20ns to ensure synchronization between CONVST and SCLK. In many cases, the conversion can start one SCLK period (or CCLK)later,whichresultsinaconversionof 19 CCLKs (or 37 SCLKs). The 20ns setup time is not required if the synchronizationisnotcriticalintheapplication. The duty cycle of SCLK is not critical as long as it meets the minimum high and low time requirements of 8ns. The ADS7229/30 is designed for high-speed applications; therefore, a higher serial clock (SCLK) must be supplied to be able to sustain the high throughput with the serial interface. As a result, the clock period of SCLK must be at most 1m s (when used as the conversion clock, CCLK). The minimum clock frequency is also governed by the parasitic leakage of the capacitive digital-to-analog (CDAC) capacitors internal to the ADS7229/30. CFR_D10 Conversion Clock = 1 OSC (CCLK) SPI Serial Divider Clock (SCLK) = 0 1/2 Figure56.ConverterClock ManualChannelSelectMode The conversion cycle starts with selecting an acquisition channel by writing a channel number to the command register,CMR.ThecommandlengthcanbeasshortasfourSCLKs. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com AutoChannelSelectMode Channel selection can also be done automatically if auto channel select mode is enabled. This mode is the default channel select mode. The dual channel converter, ADS7230, has an onboard 2-to-1 MUX. If the device is programmed for auto channel select mode, then signals from channel 0 and channel 1 are acquired with a fixed order. Channel 0 is accessed first in the next cycle after the command cycle that configured CFR_D11 to '1' for auto channel select mode. This automatic access stops the cycle after the command cycle that sets CFR_D11 to '0'. StartofaConversion Theendofsamplinginstance(EOS)oracquisitionisthesame as the start of a conversion. This event is initiated by bringing the CONVST pin low for a minimum of 40ns. After the minimum requirement has been met, the CONVST pin can be brought high. CONVST acts independently of FS/CS so it is possible to use one common CONVST for applications that require a simultaneous sample/hold with multiple converters. The ADS7229/30 switches from sample to hold mode on the falling edge of the CONVST signal. The ADS7229/30 requires 18 conversion clock (CCLK) edges to complete a conversion. The conversion time is equivalent to 857ns with a 21MHzinternalclock.TheminimumtimebetweentwoconsecutiveCONVSTsignalsis21CCLKs. A conversion can also be initiated without using CONVST if it is so programmed (CFR_D9 = 0). When the converter is configured as an auto trigger, the next conversion automatically starts three conversion clocks (CCLK) after the end of a conversion. These three conversion clocks are used as the acquisition time. In this case, the time to complete one acquisition and conversion cycle is 21 CCLKs. Table 1 summarizes the different conversionmodes. Table1.DifferentTypesofConversion MODE SELECTCHANNEL STARTCONVERSION AutoChannelSelect(1) AutoTrigger Automatic NoneedtowritechannelnumbertotheCMR.Useinternalsequencerforthe Startaconversionbasedontheconversion ADS7230. clockCCLK. ManualChannelSelect ManualTrigger Manual WritethechannelnumbertotheCMR. StartaconversionwithCONVST. (1) AutochannelselectshouldbeusedwiththeTAGbitenabled. StatusOutputEOC/INT When the status pin is programmed as EOC and the polarity is set as active low, the pin works in the following manner: The EOC output goes low immediately after CONVST goes low when the manual trigger is programmed. EOC stays low throughout the conversion process and returns high when the conversion ends. The EOC output goes low for three conversion clocks after the previous rising edge of EOC, if auto trigger is programmed. This status pin is programmable. It can be used as an EOC output (CFR_D[7:6] = 1, 1) where the low time is equal to the conversion time. This status pin can also be used as INT (CFR_D[7:6] = 1, 0), which is set low as the end of a conversion is brought high (cleared) by the next read cycle. The polarity of this pin, used as either function(EOCorINT),isprogrammablethroughCFR_D7. 26 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 Power-DownModes The ADS7229/30 has a comprehensive, built-in power-down feature. There are three power-down modes: Deep power-down mode, Nap power-down mode, and Auto nap power-down mode. All three power-down modes are enabled by setting the related CFR bits. The first two power-down modes are activated when enabled. A wakeup command, 1011b, resumes device operation from a power-down mode. Auto nap power-down mode works slightly differently. When the converter is enabled in Auto nap power-down mode, an end of conversion instance (EOC) puts the device into auto nap power-down. The beginning of sampling resumes converter operation. The contents of the configuration register are not affected by any of the power-down modes. Any ongoing conversion whennapordeeppower-downisactivatedisaborted. 100 A) m nt ( 10 e urr C y pl p u S 1 A V + 0.1 0 10000 20000 30000 40000 Settling Time (ns) Figure57.TypicalAnalogSupplyCurrentDropversusTimeAfterPower-Down DeepPower-DownMode Deep power-down mode can be activated by writing to configuration register bit CFR_D2. When the device is in Deep power-down mode, all blocks except the interface are in power-down. The external SCLK is blocked to the analog block. The analog blocks no longer have bias currents and the internal oscillator is turned off. In this mode, supply current falls from 5.7mA to 4nA in 100ns. The wake-up time after a deep power-down is 1m s. When bit D2 in the configuration register is set to '0', the device is in Deep power-down. Setting this bit to '1' or sendingawake-upcommandresumestheconverteroperationfromtheDeeppower-downstate. NapMode In Nap mode, the ADS7229/30 turns off biasing of the comparator and the mid-voltage buffer. In this mode, supply current falls from 5.7mA in normal mode to about 0.3mA in 200ns after the configuration cycle. The wake-up (resume) time from Nap power-down mode is 3 CCLKs (143ns with a 21MHz conversion clock). As soon as the CFR_D3 bit in the control register is set to '0', the device goes into Nap power-down mode, regardless of the conversion state. Setting this bit to '1' or sending a wake-up command resumes converter operationfromtheNappower-downstate. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com AutoNapMode Auto nap mode is almost identical to nap mode. The only difference is the time when the device is actually powered down and the method used to wake up the device. Configuration register bit D4 is only used to enable/disable Auto nap mode. If Auto nap mode is enabled, the device turns off the biasing after the conversion has finished; that is, the end of conversion activates Auto nap power-down mode. Supply current falls from 5.7mA in normal mode to about 0.3mA in 200ns. A CONVST command resumes the device and turns on the biasing on again in 3 CCLKs (143ns with a 21MHz conversion clock). The device can also be woken up by disabling auto nap mode when bit D4 of the configuration register is set to '1'. Any channel select command 0XXXb, a wake-up command, or the set default mode command 1111b can also wake up the device from Auto nappower-down.Table2comparesthevariouspower-downmodes. NOTE: 1. This wake-up command is the word 1011b in the command word. This command sets bits D2 and D3 to '1' in the configuration register, but not D4. A wake-up command removes thedevicefromanyofthesepower-downstates,Deep/Nap/Autonappower-down. 2. Wake-uptimeisdefinedasthetimebetweenwhenthehostprocessortriestowakeupthe converterandwhenaconversionstartcanoccur. Table2.Power-DownModeComparisons SUPPLY TIMETO TYPEOF CURRENT POWER-DOWN WAKE-UP POWER-DOWN AT5V/3V ACTIVATEDBY (ns) WAKE-UPBY TIME ENABLE Normaloperation 5.7mA/4.5mA Deeppower-down 4nA/1nA SettingCFR 100 Wokenupbycommand1011b 1m s SetCFR Nappower-down 0.3mA/0.25mA SettingCFR 200 Wokenupbycommand1011b 3CCLKs SetCFR WokenupbyCONVST,anychannel Autonap EOC(endof 0.3mA/0.25mA 200 selectcommand,defaultcommand 3CCLKs SetCFR power-down conversion) 1111b,orwakeupcommand1011b. 28 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 CONVST N Converter State N+1 EOS EOC EOS EOC CoSntvaeterter N−thConversion N+1−th Sampling N+1−th Conversion Read While Converting 20nsMIN 1CCLKMIN =t CS 1 (For Read Result) ReadN−1−thResult ReadWhile Sampling 0nsMIN 20nsMIN CS (For Read Result) ReadN−th Result Figure58.ReadWhileConvertingversusReadWhileSampling(ManualTrigger) Manual Trigger CONVST N N+1 S C S C O O O O E E E E Converter State Wake-Up N−thSampling N−th Conversion Activation Wake-Up N+1−th Sampling N+1−th Conversion Activation >=3CCLK =18 CCLK >=3CCLK =18 CCLK 20nsMIN 1CCLK MIN 20nsMIN Read While Converting ReadN−1−th ReadN−th CS Result Result 20nsMIN Read While Sampling 20nsMIN 0nsMIN ReadN−1−th 20nsMIN 20nsMIN ReadN−th CS Result Result 20nsMIN 20nsMIN Figure59.ReadWhileConvertingversusReadWhileSamplingwithDeeporNapPower-Down Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com 40ns MIN ManualTrigger(wakeupbyCONVST) CONVST N N+1 EOC (programmed ActiveLow) EOS EOC EOS EOC Converter Wake-Up N−thSampling N−thConversion POWERDOWN Wake-Up N+1−thSampling N+1−thConversion POWERDOWN State >=3CCLK =18CCLK >=3CCLK =18CCLK 6CCLKs 6CCLKs ReadWhileConverting 20ns MIN 20ns MIN Read N−1−th ReadN−th CS Result Result Figure60.ReadWhileConvertingwithAutoNapPower-Down TotalAcquisition+ConversionCycleTime: Autotrigger: =21CCLKs Manual: ≥21CCLKs Manual+deep ≥4SCLK+100m s+3CCLK+18CCLK+16SCLK+1m s power-down: Manual+nappower-down: ≥4SCLK+3CCLK+3CCLK+18CCLK+16SCLK Manual+autonap ≥1CCLK+3CCLK+3CCLK+18CCLK+16SCLK(useCONVSTtoresume) power-down: Manual+autonap ≥4SCLK+3CCLK+3CCLK+18CCLK+16SCLK(usewakeuptoresume) power-down: 30 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 DIGITAL INTERFACE The serial clock is designed to accommodate the latest high-speed processors with an SCLK frequency up to 50MHz.EachcyclestartswiththefallingedgeofFS/CS. The internal data register content that is made available to the output register at the EOC (presented on the SDO output pin at the falling edge of FS/CS) is the MSB. Output data are valid at the falling edge of SCLK with a t delay so that the host processor can d(SCLKF-SDOVALID) readitatthefallingedge.SerialdatainputisalsoreadatthefallingedgeofSCLK. The complete serial I/O cycle starts with the first falling edge of SCLK after the falling edge of FS/CS and ends 16 falling edges of SCLK later (see NOTE). The serial interface is very flexible. It works with CPOL = 0 , CPHA = 1 or CPOL = 1, CPHA = 0. This flexibility means the falling edge of FS/CS may fall while SCLK is high. The same relaxation applies to the rising edge of FS/CS where SCLK may be high or low as long as the last SCLK fallingedgeoccursbeforetherisingedgeofFS/CS. NOTE: There are cases where a cycle is 4 SCLKs or up to 24 SCLKs depending on the read modecombination.SeeTable3andTable6fordetails. InternalRegister The internal register consists of two parts, 4 bits for the command register (CMR) and 12 bits for configuration dataregister(CFR). Table3.CommandSetDefinedbyCommandRegister(CMR)(1) WAKE-UPFROM MINIMUMSCLKs D[15:12] HEX COMMAND D[11:0] AUTONAP REQUIRED R/W 0000b 0h Selectanaloginputchannel0(2) Don'tcare Y 4 W 0001b 1h Selectanaloginputchannel1(2) Don'tcare Y 4 W 0010b 2h Don'tcare Don'tcare – – – 0011b 3h Don'tcare Don'tcare – – – 0100b 4h Don'tcare Don'tcare – – – 0101b 5h Don'tcare Don'tcare – – – 0110b 6h Don'tcare Don'tcare – – – 0111b 7h Don'tcare Don'tcare – – – 1000b 8h Reservedforfactorytest,don'tuse Reserved – – – 1001b 9h Reservedforfactorytest,don'tuse Reserved – – – 1010b Ah Reservedforfactorytest,don'tuse Reserved – – – 1011b Bh Wakeup Don'tcare Y 4 W 1100b Ch ReadCFR Don'tcare – 16 R 1101b Dh Readdata Don'tcare – 12 R 1110 Eh WriteCFR CFRvalue – 16 W 1111b Fh Defaultmode(loadCFRwithdefaultvalue) Don'tcare Y 4 W (1) WhenSDOisnotin3-statemode(FS/CSlow),thebitsfromSDOarealwayspartofaconversionresult(dependingonhowmany SCLKsaresupplied). (2) ThesetwocommandsapplytotheADS7230only. WRITING TO THE CONVERTER There are two different types of writes to the register, a 4-bit write to the CMR and a full 16-bit write to the CMR plus CFR. The command set is listed in Table 3. A simple command requires only 4 SCLKs and the write takes effect at the fourth falling edge of SCLK. A 16-bit write or read takes at least 16 SCLKs (see Table 6 for exceptionsthatrequiremorethan16SCLKs). Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com ConfiguringtheConverterandDefaultMode The converter can be configuring with command 1110b (write to the CFR) or command 1111b (default mode). A writetotheCFRrequiresa4-bitcommandfollowed by 12 bits of data. A 4-bit command takes effect at the fourth fallingedgeofSCLK.ACFRwritetakeseffectatthe16thfallingedgeofSCLK. AdefaultmodecommandcanbeachievedbysimplytyingSDIto +VBD. As soon as the chip is selected, at least four'1'sareclockedinbySCLK.Thedefault value of the CFR is loaded into the CFR at the fourth falling edge of SCLK. CFR default values are all 1s (except for CFR_D1 on the ADS7229; this bit is ignored by the device and is always read as a '0'). The same default values apply for the CFR after a power-on reset (POR) and software reset. READING THE CONFIGURATION REGISTER The host processor can read back the value programmed in the CFR by issuing command 1100b. The timing is similar to reading a conversion result, except that CONVST is not used and there is no activity on the EOC/INT pin. The CFR value read back contains the first four MSBs of conversion data plus valid 12-bit CFR contents. Table4showstheConfigurationRegisterMap. Table4.ConfigurationRegister(CFR)Map SDIBIT CFR-D[11-0] DEFINITION Channelselectmode D11default=1 0:Manualchannelselectenabled.Usechannelselectcommandsto 1:Autochannelselectenabled.Allchannelsaresampledand accessadifferentchannel. convertedsequentiallyuntilthecycleafterthisbitissetto0. Conversionclock(CCLK)sourceselect D10default=1 0:Conversionclock(CCLK)=SCLK/2 1:Conversionclock(CCLK)=InternalOSC Trigger(conversionstart)select:startconversionattheendofsampling(EOS).IfD9=0,theD4settingisignored. D9default=1 0:Autotriggerautomaticallystarts(4internalclocksafterEOCinactive) 1:ManualtriggermanuallystartedbyfallingedgeofCONVST D8default=1 Don'tcare Don'tcare Pin10polarityselectwhenusedasanoutput(EOC/INT) D7default=1 0:EOCActivehigh/INTactivehigh 1:EOCactivelow/INTactivelow Pin10functionselectwhenusedasanoutput(EOC/INT) D6default=1 0:PinusedasINT 1:PinusedasEOC Pin10I/Oselectforchainmodeoperation D5default=1 0:Pin10isusedasCDIinput(chainmodeenabled) 1:Pin10isusedasEOC/INToutput Autonappower-downenable/disable(midvoltageandcomparatorshutdownbetweencycles).ThisbitsettingisignoredifD9=0. D4default=1 0:Autonappower-downenabled(notactivated) 1:Autonappower-downdisabled Nappower-down(midvoltageandcomparatorshutdownbetweencycles).Thisbitissetto1automaticallybywake-upcommand. D3default=1 0:Enable/activatedeviceinnappower-down 1:Removedevicefromnappower-down(resume) Deeppower-down.Thisbitissetto1automaticallybywake-upcommand. D2default=1 0:Enable/activatedeviceindeeppower-down 1:Removedevicefromdeeppower-down(resume) D1default= TAGbitenable.ThisbitisignoredbytheADS7229andisalwaysread0. 0:ADS7229 1:ADS7230 0:TAGbitdisabled. 1:TAGbitoutputenabled.TAGbitappearsatthe17thSCLK. Reset D0default=1 0:Systemreset 1:Normaloperation READING CONVERSION RESULT The conversion result is available to the input of the output data register (ODR) at EOC and presented to the output of the output register at the next falling edge of CS or FS. The host processor can then shift the data out via the SDO pin any time except during the quiet zone. This quite zone is 20ns before and 20ns after the end of sampling (EOS) period. In the quiet zone the FS/CS should be high, to avoid performance loss when switching from sampling-mode to hold-mode. End of sampling (EOS) is defined as the falling edge of CONVST when manualtriggerisusedortheendofthethirdconversionclock(CCLK)afterEOCifautotriggerisused. 32 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 The falling edge of FS/CS should not be placed at the precise moment of the end of a conversion; otherwise, the data may be corrupt. There must be a minimum of at least one conversion clock (CCLK) delay at the end of a conversion. If FS/CS is placed before the end of a conversion, the previous conversion result is read. If FS/CS is placedaftertheendofaconversion,thecurrentconversionresultisread. The conversion result is 12-bit data in straight binary format as shown in Table 5. Generally, 12 SCLKs are necessary, but there are exceptions where more than 12 SCLKS are required (see Table 6). Data output from the serial output (SDO) is left-adjusted, MSB first. The 12-bit conversion result is followed by '0000', the TAG bit (ifenabled),andadditionalzeros.SDOremainslowuntilFS/CSisbroughthighagain. Table5.IdealInputVoltagesandOutputCodes DIGITALOUTPUT DESCRIPTION ANALOGVALUE STRAIGHTBINARY Full-scalerange V REF BINARYCODE HEXCODE Leastsignificantbit(LSB) V /4096 REF Full-scale +V –1LSB 111111111111 FFF REF Midscale V /2 100000000000 800 REF Midscale–1LSB V /2–1LSB 011111111111 7FF REF Zero 0V 000000000000 000 SDOisactivewhenFS/CSislow.TherisingedgeofFS/CS3-statestheSDOoutput. NOTE: Whenever SDO is not in 3-state mode (that is, when FS/CS is low), a portion of the conversion result is output at the SDO pin. The number of bits depends on how many SCLKs are supplied. For example, a manual select channel command cycle requires 4SCLKs;therefore,4MSBsoftheconversionresultareoutput at SDO. The exception is that SDO outputs all 1s during the cycle immediately after any reset (POR or softwarereset). If SCLK is used as the conversion clock (CCLK) and a continuous SCLK is used, it is not possible to clock out all 12 SDO bits during the sampling time (6 SCLKs) because of the quiet zone requirement. In this case, it is better toreadtheconversionresultduringtheconversiontime(36SCLKsor48SCLKsinAutonapmode). TAGMode The ADS7230 includes a feature, TAG, that can be used as a tag to indicate which channel sourced the converted result. An address bit is added after the LSB read out from SDO that indicates which channel the result came from if TAG mode is enabled. This address bit is '0' for channel 0 and '1' for channel 1. The converterrequiresmorethanthe16SCLKsthatarerequiredfora4-bitcommandplus12-bit CFR or 12 data bits followedby'0000'becauseoftheadditionalTAGbit. ChainMode The ADS7229/30 can operate as a single converter or in a system with multiple converters. System designers can take advantage of the simple, high-speed, SPI-compatible serial interface by cascading the devices in a daisy-chainwhenmultipleconvertersareused.AbitintheCFRisused to reconfigure the EOC/INT status pin as a secondary serial data input, chain data input (CDI), for the conversion result from an upstream converter. This configurationischainmodeoperation.AtypicalconnectionofthreeconvertersisshowninFigure61. Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com Micro Controller INT GPIO1 GPIO2 GPIO3 SDOSCLK SDI SDISCLKCONVST SDISCLKCONVST SDI SCLK CONVST CS CS CS ADS7229 ADS7229 ADS7229 #1 #2 #3 EOC/INT SDO CDI SDO CDI SDO Program device #1 CFR_D[7:5] = XX0b Program device #2 and #3 CFR_D[7:5] = XX1b Figure61.MultipleConvertersConnectedUsingChainMode When multiple converters are used in daisy-chain mode, the first converter is configured in regular mode while the other converters are configured in chain mode. When a converter is configured in chain mode, the CDI input data go straight to the output register; therefore, the serial input data passes through the converter with a 16 SCLK delay (if the TAG feature is disabled) or a 24 SCLK delay, as long as CS is active. Figure 62 shows a detailedtimingdiagram.Inthistiming,theconversionsineachdeviceareperformedsimultaneously. Cascaded Manual Trigger/Read WhileSampling (Use internal CCLK, EOC, andINTprogrammed as active low) CSheld low during the N times 16 bits transfer cycle CommonCONVST S C S O O O E E E EOC #1 Nth (active low) t = 18 CCLKs CONV t = 3 CCLKs Min SAMPLE1 INT (active low) t 4 FS/CS#1 1……………………16 1……………………16 1……………………16 CommonSCLK SDO #1 Nth from#1 t 4 FS/CS#2 FS/CS#3 SDO #2 Nth from#2 Nth from#1 SDO #3 Nth from#3 Nth from#2 Nth from#1 SDI 1101b 1101b 1101b READ Result READ Result READ Result Figure62.SimplifiedCascadeModeTimingwithSharedCONVSTandContinuousCS Care must be given to handle the multiple CS signals when the converters operate in daisy-chain mode. The different chip select signals must be low for the entire data transfer (in this example, 48 bits for three converters). The first 16-bit word after the falling chip select is always the data from the chip that received the chip select signal. 34 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 Case1:Ifchipselectisnottoggled(CSstayslow),thenext16bitsaredatafromtheupstreamconverter,andso on. This configuration is shown in Figure 62. If there is no upstream converter in the chain, as with converter #1 intheexample,thesamedatafromtheconverteraregoingtobeshownrepeatedly. Case 2: If the chip select is toggled during a chain mode data transfer cycle, as illustrated in Figure 63, the same data from the converter are read out again and again in all three discrete 16-bit cycles. This result is not a desiredoutcome. CascadedManual Trigger/Read WhileSampling (Use internal CCLK, EOC, andINTprogrammed as active low) CommonCONVST S C S O O O EOC #1 E E E Nth (active low) t =18 CCLKs CONV t = 3 CCLKs Min SAMPLE1 INT (active low) t 4 FS/CS#1 1……………………16 1……………………16 1……………………16 CommonSCLK SDO #1 Nthfrom#1 Nthfrom#1 Nthfrom#1 t 4 FS/CS#2 SDO #2 Nthfrom#2 Nthfrom#1 Nthfrom#1 t 4 FS/CS#3 SDO #3 Nthfrom#3 Nthfrom#3 Nthfrom#3 SDI 1101b 1101b 1101b READ Result READ Result READResult Figure63.SimplifiedCascadeModeTimingwithSharedCONVSTandDiscreteCS Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com Figure 64 shows a slightly different scenario where CONVST is not shared by the second converter. Converters #1and#3havethesameCONVSTsignal.Inthiscase,converter#2simplypassesthe previous conversion data downstream. CascadedManualTrigger/ReadWhileSampling (Use internal CCLK, EOC, andINTprogrammed as active low) CSheld low during the N times 16 bits transfer cycle CONVST#1 CONVST#3 CONVST#2 = 1 S C S O O O E E E EOC #1 Nth (active low) t = 18 CCLKs CONV t = 3 CCLKs Min SAMPLE1 INT (active low) t 4 FS/CS#1 1……………………16 1……………………16 1……………………16 CommonSCLK SDO #1 Nth from#1 t 4 FS/CS#2 FS/CS#3 SDO #2 N-1th #2 Nth from#1 SDO #3 Nth from#3 N-1th #2 Nth from#1 SDI 1101b 1101b 1101b READ Result READ Result READ Result Figure64.SimplifiedCascadeTiming(SeparateCONVST) The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG bit, chain mode, and the way a channel is selected (that is, auto channel select). These possible configurations arelistedinTable6. Table6.RequiredSCLKsForDifferentReadOutModeCombinations CHAINMODE AUTOCHANNEL NUMBEROFSCLKPERSPI ENABLEDCFR.D5 SELECTCFR.D11 TAGENABLEDCFR.D1 READ TRAILINGBITS 0 0 0 12 None 0 0 1 ≥17 MSBisTAGbitpluszero(s) 0 1 0 12 None 0 1 1 ≥17 TAGbitplussevenzeros 1 0 0 16 None 1 0 1 24 TAGbitplussevenzeros 1 1 0 16 None 1 1 1 24 TAGbitplussevenzeros 36 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 SCLK skew between converters and data path delay through the converters configured in chain mode can affect the maximum frequency of SCLK. The delay can also be affected by supply voltage and loading. It may be necessary to slow down the SCLK when the devices are configured in chain mode. Figure 65 shows a typical delayprocessthroughmultipleconverterslinkedindaisy-chainmode. ADS7229#3 CDI SDO Serial data output Logic D Logic Q Logic Delay Delay Delay Plus PAD <=8.3ns Plus PAD 2.7ns 8.3ns CLK ADS7229#2 CDI SDO Logic Logic D Q Logic Delay Delay Delay Plus PAD <=8.3ns Plus PAD 2.7ns 8.3ns CLK ADS7229#1 CDI SDO Logic Logic D Q Logic Serial data Delay Delay Delay input Plus PAD <=8.3ns Plus PAD 2.7ns 8.3ns CLK SCLK input Figure65.TypicalDelayThroughConvertersConfiguredinChainMode RESET The converter has two reset mechanisms: a power-on reset (POR) and a software reset using CFR_D0. These twomechanismsareNOR-edinternally.Whenareset(softwareorPOR)isissued, all register data are set to the default values (all 1s) and the SDO output (during the cycle immediately after reset) is set to all 1s. The state machineisresettothepower-onstate.Figure66illustratesthedigitaloutputunderaresetcondition. SW RESET CDI POR SET SAR Shift Intermediate Output SDO Register Latch Register SCLK Conversion Clock Latched by End Of Latched by Falling Edge of CS Conversion CS EOC EOC Figure66.DigitalOutputUnderResetCondition Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com When the device is powered up, the POR sets the device to default mode when AVDD reaches 1.5V. When the device is powered down, the POR circuit requires AVDD to remain below 125mV for at least 350ms to ensure proper discharging of internal capacitors and to correct the behavior of the ADC when powered up again. If AVDD drops below 400mV but remains above 125mV, the internal POR capacitor does not discharge fully and the device requires a software reset to perform correctly after the recovery of AVDD (this condition is shown as theundefinedzoneinFigure67). AVDD (V) 5.500 5.000 Specified Supply 4.000 Voltage Range 3.000 2.700 2.000 POR 1.500 Trigger Level 1.000 0.400 Undefined Zone 0.125 0 0.350 t (s) Figure67.RelevantVoltageLevelsforPOR 38 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 www.ti.com............................................................................................................................................................... SBAS437A–MAY2008–REVISEDJUNE2009 APPLICATION INFORMATION TYPICAL CONNECTION Figure68showsatypicalcircuitconfigurationforthedevice. Analog Supply 4.7mF AGND 100nF Ext Ref Input 22mF AGND Analog Input +VAREF+ REF- AGND IN+ IN- FS/CS SDO SDI Interface SCLK Supply Host ADS7229 Processor BDGND CONVST 4.7mF +VBD EOC/INT/CDI 100nF Figure68.TypicalCircuitConfiguration Copyright©2008–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):ADS7229ADS7230

ADS7229 ADS7230 SBAS437A–MAY2008–REVISEDJUNE2009............................................................................................................................................................... www.ti.com Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromOriginal(May2008)toRevisionA ........................................................................................................... Page • Added+REFtoAGNDand–REFtoAGNDspecificationstoVoltagerangesectionofAbsoluteMaximumRatingstable. 2 • ChangedRevisedconditionsofthe5VElectricalCharacteristicsto+VA=4.5Vto5.5V..................................................... 3 • ChangedRevisedconditionsofthe5VElectricalCharacteristicsto+VA=4.5Vto5.5V..................................................... 4 • DeletedtypicalspecificationfromInputreferencerange,V [(REF+)–(REF–)]rowoftheExternalVoltage REF ReferenceInputsectionofthe5VElectricalCharacteristics ................................................................................................ 4 • ChangedtestconditionofSupplycurrent,PDmodetoDeeppower-downmodeinPower-SupplyRequirements sectionofthe5VElectricalCharacteristics............................................................................................................................ 4 • ChangedV rowofExternalVoltageReferenceInputsectioninthe2.5VElectricalCharacteristics................................ 6 REF • ChangedtestconditionofSupplycurrent,PDmodetoDeeppower-downmodeinPower-SupplyRequirements sectionofthe2.5VElectricalCharacteristics......................................................................................................................... 7 • CorrectedtypoinFigure2................................................................................................................................................... 12 • CorrectedtypoinFigure3................................................................................................................................................... 13 • CorrectedtypoinFigure5................................................................................................................................................... 14 • AddedlastsentencetotheDriverAmplifierChoicesection................................................................................................ 24 • UpdatedFigure54............................................................................................................................................................... 24 • UpdatedFigure55............................................................................................................................................................... 24 • ChangedfifthsentenceoftheDeepPower-DownModesection........................................................................................ 27 • ChangedSupplyCurrentspecificationofAutonappower-downrowofTable2................................................................ 28 • AddedFigure67andcorrespondingparagraphtotheRESETsection.............................................................................. 38 40 SubmitDocumentationFeedback Copyright©2008–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS7229ADS7230

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS7229IPW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7229I A ADS7229IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7229I A ADS7229IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7229I A ADS7229IRSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7229I A ADS7229IRSAT ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7229I A ADS7229IRSATG4 ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7229I A ADS7230IPW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7230I A ADS7230IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7230I A ADS7230IRSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7230I A ADS7230IRSAT ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS & no Sb/Br) 7230I A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS7229IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS7229IRSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS7229IRSAT QFN RSA 16 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS7230IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS7230IRSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS7230IRSAT QFN RSA 16 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS7229IPWR TSSOP PW 16 2000 350.0 350.0 43.0 ADS7229IRSAR QFN RSA 16 3000 350.0 350.0 43.0 ADS7229IRSAT QFN RSA 16 250 210.0 185.0 35.0 ADS7230IPWR TSSOP PW 16 2000 350.0 350.0 43.0 ADS7230IRSAR QFN RSA 16 3000 350.0 350.0 43.0 ADS7230IRSAT QFN RSA 16 250 210.0 185.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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