ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 12-/14-Bit, 160/250MSPS, Ultralow-Power ADC CheckforSamples:ADS4126,ADS4129,ADS4146,ADS4149 FEATURES DESCRIPTION 1 • MaximumSampleRate:250MSPS The ADS412x/4x are a family of 12-bit/14-bit 23 • UltralowPowerwith1.8VSingleSupply: analog-to-digital converters (ADCs) with sampling rates up to 250MSPS. These devices use innovative – 201mWTotalPowerat160MSPS design techniques to achieve high dynamic – 265mWTotalPowerat250MSPS performance, while consuming extremely low power • HighDynamicPerformance: at 1.8V supply. The devices are well-suited for multi-carrier, wide bandwidth communications – SNR:70.6dBFSat170MHz applications. – SFDR:84dBcat170MHz The ADS412x/4x have fine gain options that can be • DynamicPowerScalingwithSampleRate used to improve SFDR performance at lower • OutputInterface: full-scale input ranges, especially at high input – DoubleDataRate(DDR)LVDSwith frequencies. They include a dc offset correction loop ProgrammableSwingandStrength that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at – StandardSwing:350mV scaleddownpowerwithnolossinperformance. – LowSwing:200mV The ADS412x/4x are available in a compact QFN-48 – DefaultStrength:100ΩTermination package and are specified over the industrial – 2xStrength:50ΩTermination temperaturerange(–40°Cto+85°C) – 1.8VParallelCMOSInterfaceAlso Supported • ProgrammableGainupto6dBforSNR/SFDR Trade-Off • DCOffsetCorrection • SupportsLowInputClockAmplitudeDownTo 200mV PP • Package:QFN-48(7mm×7mm) ADS412x/ADS414xFamilyComparison SAMPLINGRATE WITHANALOGINPUTBUFFERS FAMILY 65MSPS 125MSPS 160MSPS 250MSPS 200MSPS 250MSPS ADS412x ADS4122 ADS4125 ADS4126 ADS4129 — ADS41B29 12-bitfamily ADS414x ADS4142 ADS4145 ADS4146 ADS4149 — ADS41B49 14-bitfamily 9-bit — — — — — ADS58B19 11-bit — — — — ADS58B18 — 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PowerPADisatrademarkofTexasInstrumentsIncorporated. 2 Allothertrademarksarethepropertyoftheirrespectiveowners. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2009–2011,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION(1) SPECIFIED PACKAGE- PACKAGE TEMPERATURE LEAD/BALL PACKAGE ORDERING TRANSPORTMEDIA, PRODUCT LEAD DESIGNATOR RANGE ECOPLAN(2) FINISH MARKING NUMBER QUANTITY GREEN(RoHS,no ADS4126IRGZR Tapeandreel,2500 ADS4126 QFN-48 RGZ –40°Cto+85°C Cu/NiPdAu AZ4126 Sb/Br) ADS4126IRGZT Tapeandreel,250 GREEN(RoHS,no ADS4129IRGZR Tapeandreel,2500 ADS4129 QFN-48 RGZ –40°Cto+85°C Cu/NiPdAu AZ4129 Sb/Br) ADS4129IRGZT Tapeandreel,250 GREEN(RoHS,no ADS4146IRGZR Tapeandreel,2500 ADS4146 QFN-48 RGZ –40°Cto+85°C Cu/NiPdAu AZ4146 Sb/Br) ADS4146IRGZT Tapeandreel,250 GREEN(RoHS,no ADS4149IRGZR Tapeandreel,2500 ADS4149 QFN-48 RGZ –40°Cto+85°C Cu/NiPdAu AZ4149 Sb/Br) ADS4149IRGZT Tapeandreel,250 (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orvisitthe deviceproductfolderatwww.ti.com. (2) EcoPlanistheplannedeco-friendlyclassification.Green(RoHS,noSb/Br):TIdefinesGreentomeanPb-Free(RoHScompatible)and freeofBromine-(Br)andAntimony-(Sb)basedflameretardants.RefertotheQualityandLead-Free(Pb-Free)Datawebsiteformore information. The ADS412x/4x family is pin-compatible with the previous generation ADS6149 family; this architecture enables easymigration.However,therearesomeimportantdifferencesbetweenthegenerations,summarizedinTable1. Table1.MIGRATINGFROMTHEADS6149FAMILY ADS6149FAMILY ADS4149FAMILY PINS Pin21isNC(notconnected) Pin21isNC(notconnected) Pin23isMODE Pin23isRESERVEDintheADS4149family.Itisreservedasadigitalcontrolpinforan(asyet)undefinedfunctioninthe next-generationADCseries. SUPPLY AVDDis3.3V AVDDis1.8V DRVDDis1.8V Nochange INPUTCOMMON-MODEVOLTAGE VCMis1.5V VCMis0.95V SERIALINTERFACE Protocol:8-bitregisteraddressand8-bitregisterdata Nochangeinprotocol Newserialregistermap EXTERNALREFERENCEMODE Supported Notsupported ADS61B49FAMILY ADS41B29/B49/ADS58B18FAMILY PINS Pin21isNC(notconnected) Pin21is3.3VAVDD_BUF(supplyfortheanaloginputbuffers) Pin23isadigitalcontrolpinfortheRESERVEDfunction. Pin23isMODE Pin23functionsasSNRBoostenable(B18only). SUPPLY AVDDis3.3V AVDDis1.8V,AVDD_BUFis3.3V DRVDDis1.8V Nochange INPUTCOMMON-MODEVOLTAGE VCMis1.5V VCMis1.7V SERIALINTERFACE Nochangeinprotocol Protocol:8-bitregisteraddressand8-bitregisterdata Newserialregistermap EXTERNALREFERENCEMODE Supported Notsupported 2 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 ABSOLUTE MAXIMUM RATINGS(1) Overoperatingfree-airtemperaturerange,unlessotherwisenoted. VALUE UNIT Supplyvoltagerange,AVDD –0.3to2.1 V Supplyvoltagerange,DRVDD –0.3to2.1 V VoltagebetweenAGNDandDRGND –0.3to0.3 V VoltagebetweenAVDDtoDRVDD(whenAVDDleadsDRVDD) 0to2.1 V VoltagebetweenDRVDDtoAVDD(whenDRVDDleadsAVDD) 0to2.1 V INP,INM –0.3tominimum(1.9,AVDD+0.3) V Voltageappliedtoinputpins CLKP,CLKM(2),DFS,OE –0.3toAVDD+0.3 V RESET,SCLK,SDATA,SEN –0.3to3.9 V Operatingfree-airtemperaturerange,T –40to+85 °C A Operatingjunctiontemperaturerange,T +125 °C J Storagetemperaturerange,T –65to+150 °C stg ESD,humanbodymodel(HBM) 2 kV (1) Stressesabovetheseratingsmaycausepermanentdamage.Exposuretoabsolutemaximumconditionsforextendedperiodsmay degradedevicereliability.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyond thosespecifiedisnotimplied. (2) WhenAVDDisturnedoff,itisrecommendedtoswitchofftheinputclock(orensurethevoltageonCLKP,CLKMislessthan|0.3V|. ThispreventstheESDprotectiondiodesattheclockinputpinsfromturningon. THERMAL INFORMATION ADS4126, ADS4129, ADS4146, THERMALMETRIC(1) ADS4149 UNITS RGZ 48PINS q Junction-to-ambientthermalresistance 29 JA q Junction-to-case(top)thermalresistance JCtop q Junction-to-boardthermalresistance 10 JB °C/W y Junction-to-topcharacterizationparameter 0.3 JT y Junction-to-boardcharacterizationparameter 9 JB q Junction-to-case(bottom)thermalresistance 1.13 JCbot (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com RECOMMENDED OPERATING CONDITIONS Overoperatingfree-airtemperaturerange,unlessotherwisenoted. ADS412x,ADS414x MIN TYP MAX UNIT SUPPLIES AVDD Analogsupplyvoltage 1.7 1.8 1.9 V DRVDD Digitalsupplyvoltage 1.7 1.8 1.9 V ANALOGINPUTS Differentialinputvoltagerange(1) 2 V PP Inputcommon-modevoltage V ±0.05 V CM Maximumanaloginputfrequencywith2V inputamplitude(2) 400 MHz PP Maximumanaloginputfrequencywith1V inputamplitude(2) 800 MHz PP CLOCKINPUT Inputclocksamplerate ADS4129/ADS4149 Low-speedmodeenabled(3) 20 80 MSPS Low-speedmodedisabled(3) >80 250 MSPS ADS4126/ADS4146 Low-speedmodeenabled(3) 20 80 MSPS Low-speedmodedisabled(3) >80 160 MSPS Inputclockamplitudedifferential(V –V ) CLKP CLKM Sinewave,ac-coupled 0.2 1.5 V PP LVPECL,ac-coupled 1.6 V PP LVDS,ac-coupled 0.7 V PP LVCMOS,single-ended,ac-coupled 1.8 V Inputclockdutycycle Low-speedmodeenabled 40 50 60 % Low-speedmodedisabled 35 50 65 % DIGITALOUTPUTS C MaximumexternalloadcapacitancefromeachoutputpintoDRGND 5 pF LOAD DifferentialloadresistancebetweentheLVDSoutputpairs(LVDS R 100 Ω LOAD mode) T Operatingfree-airtemperature –40 +85 °C A HIGHPERFORMANCEMODES(4)(5)(6) SettheMODE1registerbitstogetbestperformanceacrosssample Mode1 clockandinputsignalfrequencies. Registeraddress=03h,registerdata=03h SettheMODE2registerbittogetbestperformanceathighinput Mode2 signalfrequencies. Registeraddress=4Ah,registerdata=01h (1) With0dBgain.SeetheFineGainsectionintheApplicationInformationforrelationbetweeninputvoltagerangeandgain. (2) SeetheTheoryofOperationsectionintheApplicationInformation. (3) SeetheSerialInterfacesectionfordetailsonlow-speedmode. (4) Itisrecommendedtousethesemodestogetbestperformance.Thesemodescanbesetusingtheserialinterfaceonly. (5) SeetheSerialInterfacesectionfordetailsonregisterprogramming. (6) Notethatthesemodescannotbesetwhentheserialinterfaceisnotused(whentheRESETpinistiedhigh);seetheDevice Configurationsection. 4 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 ELECTRICAL CHARACTERISTICS: ADS4126/ADS4129 Typicalvaluesareat+25°C,AVDD=1.8V,DRVDD=1.8V,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain, andDDRLVDSinterface,unlessotherwisenoted.Minimumandmaximumvaluesareacrossthefulltemperaturerange: T =–40°CtoT =+85°C,AVDD=1.8V,andDRVDD=1.8V.Notethatafterreset,thedeviceisin0dBgainmode. MIN MAX ADS4126(160MSPS) ADS4129(250MSPS) PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT Resolution 12 12 Bits fIN=10MHz 70.2 69.8 dBFS fIN=70MHz 70 69.7 dBFS SNR(signal-to-noiseratio),LVDS fIN=100MHz 69.7 69.6 dBFS fIN=170MHz 66.5 69 65.8 69 dBFS fIN=300MHz 68 68 dBFS fIN=10MHz 70.1 69.7 dBFS fIN=70MHz 70 69.4 dBFS SINAD(signal-to-noiseanddistortionratio), LVDS fIN=100MHz 69.5 69.3 dBFS fIN=170MHz 65.5 68.7 65.5 68.7 dBFS fIN=300MHz 67.3 66.8 dBFS fIN=10MHz 88 87 dBc fIN=70MHz 87 82 dBc Spurious-freedynamicrange SFDR fIN=100MHz 86.3 81 dBc fIN=170MHz 72.5 82 70 80 dBc fIN=300MHz 77.5 75 dBc fIN=10MHz 87 85 dBc fIN=70MHz 85 80 dBc Totalharmonicdistortion THD fIN=100MHz 84 79 dBc fIN=170MHz 70 81 69 79 dBc fIN=300MHz 74.5 71.5 dBc fIN=10MHz 92 90 dBc fIN=70MHz 90 85 dBc Second-harmonicdistortion HD2 fIN=100MHz 88 84 dBc fIN=170MHz 72.5 88 70 84 dBc fIN=300MHz 78 74 dBc fIN=10MHz 88 87 dBc fIN=70MHz 87 82 dBc Third-harmonicdistortion HD3 fIN=100MHz 86 81 dBc fIN=170MHz 72.5 82 70 80 dBc fIN=300MHz 77 75 dBc fIN=10MHz 92 90 dBc fIN=70MHz 91 88 dBc Worstspur (otherthansecondandthirdharmonics) fIN=100MHz 90 90 dBc fIN=170MHz 76 90 75 88 dBc fIN=300MHz 88 88 dBc f1=46MHz,f2=50MHz, –88 –88 dBFS Two-toneintermodulation eachtoneat–7dBFS IMD distortion f1=185MHz,f2=190MHz, –86 –86 dBFS eachtoneat–7dBFS Recoverytowithin1%(offinal Clock Inputoverloadrecovery value)for6dBoverloadwith 1 1 cycles sine-waveinput ACpower-supplyrejectionratio PSRR For100mVPPsignalonAVDD >30 >30 dB supply,upto10MHz Effectivenumberofbits ENOB fIN=170MHz 11.2 11.2 LSBs Differentialnonlinearity DNL fIN=170MHz –0.85 ±0.2 2.5 –0.95 ±0.2 2.5 LSBs Integratednonlinearity INL fIN=170MHz ±0.25 3.5 ±0.5 5 LSBs Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS4146/ADS4149 Typicalvaluesareat+25°C,AVDD=1.8V,DRVDD=1.8V,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain, andDDRLVDSinterface,unlessotherwisenoted.Minimumandmaximumvaluesareacrossthefulltemperaturerange: T =–40°CtoT =+85°C,AVDD=1.8V,andDRVDD=1.8V.Notethatafterreset,thedeviceisin0dBgainmode. MIN MAX ADS4146(160MSPS) ADS4149(250MSPS) PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT Resolution 14 14 Bits fIN=10MHz 72.2 71.9 dBFS fIN=70MHz 72 71.4 dBFS SNR(signal-to-noiseratio),LVDS fIN=100MHz 71.5 71.4 dBFS fIN=170MHz 68.5 70.8 67.5 70.6 dBFS fIN=300MHz 69 69 dBFS fIN=10MHz 72 71.6 dBFS fIN=70MHz 71.8 71 dBFS SINAD(signal-to-noiseanddistortionratio), LVDS fIN=100MHz 71.4 70.9 dBFS fIN=170MHz 67.5 70.4 66 69.4 dBFS fIN=300MHz 68.2 67.4 dBFS fIN=10MHz 88 87 dBc fIN=70MHz 87 82 dBc Spurious-freedynamicrange SFDR fIN=100MHz 86 81 dBc fIN=170MHz 74.5 82 72 84 dBc fIN=300MHz 77 75 dBc fIN=10MHz 86.5 85 dBc fIN=70MHz 85 80 dBc Totalharmonicdistortion THD fIN=100MHz 84 79 dBc fIN=170MHz 72 81 71 80.5 dBc fIN=300MHz 74.5 71.5 dBc fIN=10MHz 91 89 dBc fIN=70MHz 90 85 dBc Second-harmonicdistortion HD2 fIN=100MHz 88 84 dBc fIN=170MHz 74.5 88 72 84 dBc fIN=300MHz 79 75 dBc fIN=10MHz 88 87 dBc fIN=70MHz 87 82 dBc Third-harmonicdistortion HD3 fIN=100MHz 86 81 dBc fIN=170MHz 74.5 82 72 82 dBc fIN=300MHz 77 75 dBc fIN=10MHz 91 90 dBc fIN=70MHz 90 88 dBc Worstspur (otherthansecondandthirdharmonics) fIN=100MHz 90 90 dBc fIN=170MHz 78 90 77 88 dBc fIN=300MHz 88 88 dBc f1=46MHz,f2=50MHz, –88 –88 dBFS Two-toneintermodulation eachtoneat–7dBFS IMD distortion f1=185MHz,f2=190MHz, –86 –86 dBFS eachtoneat–7dBFS Recoverytowithin1%(offinal Clock Inputoverloadrecovery value)for6dBoverloadwith 1 1 cycles sine-waveinput ACpower-supplyrejectionratio PSRR For100mVPPsignalonAVDD >30 >30 dB supply,upto10MHz Effectivenumberofbits ENOB fIN=170MHz 11.5 11.3 LSBs Differentialnonlinearity DNL fIN=170MHz –0.95 ±0.5 –0.95 ±0.5 LSBs Integratednonlinearity INL fIN=170MHz ±2 ±4.5 ±2 ±5 LSBs 6 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 ELECTRICAL CHARACTERISTICS: GENERAL Typicalvaluesareat+25°C,AVDD=1.8V,DRVDD=1.8V,50%clockdutycycle,and0dBgain,unlessotherwisenoted. Minimumandmaximumvaluesareacrossthefulltemperaturerange:T =–40°CtoT =+85°C,AVDD=1.8V,and MIN MAX DRVDD=1.8V. ADS4126/ADS4146(160MSPS) ADS4129/ADS4149(250MSPS) PARAMETER MIN TYP MAX MIN TYP MAX UNIT ANALOGINPUTS Differentialinputvoltagerange 2 2 VPP Differentialinputresistance(atdc);seeFigure114 >1 >1 MΩ Differentialinputcapacitance;seeFigure115 4 4 pF Analoginputbandwidth 550 550 MHz Analoginputcommon-modecurrent(perinputpin) 0.6 0.6 µA/MSPS Common-modeoutputvoltage VCM 0.95 0.95 V VCMoutputcurrentcapability 4 4 mA DCACCURACY Offseterror –15 2.5 15 –15 2.5 15 mV Temperaturecoefficientofoffseterror 0.003 0.003 mV/°C Gainerrorasaresultofinternalreference inaccuracyalone EGREF –2 2 –2 2 %FS Gainerrorofchannelalone EGCHAN –0.2 –0.2 –1 %FS TemperaturecoefficientofEGCHAN 0.001 0.001 Δ%/°C POWERSUPPLY IAVDD 72 83 99 113 mA Analogsupplycurrent IDRVDD(1) Outputbuffersupplycurrent 39.5 51 47 mA LVDSinterfacewith100Ωexternaltermination LowLVDSswing(200mV) IDRVDD Outputbuffersupplycurrent 51 63 59 72 mA LVDSinterfacewith100Ωexternaltermination StandardLVDSswing(350mV) IDRVDDoutputbuffersupplycurrent(1)(2) CMOSinterface(2) 26 35 mA 8pFexternalloadcapacitance fIN=2.5MHz Analogpower 130 179 mW LVDSinterface,lowLVDSswing 71.1 84.6 mW Digitalpower CMOSinterface(2) 47 63 mW 8pFexternalloadcapacitance fIN=2.5MHz Globalpower-down 10 25 10 25 mW Standby 185 185 mW (1) ThemaximumDRVDDcurrentwithCMOSinterfacedependsontheactualloadcapacitanceonthedigitaloutputlines.Notethatthe maximumrecommendedloadcapacitanceoneachdigitaloutputlineis10pF. (2) InCMOSmode,theDRVDDcurrentscaleswiththesamplingfrequency,theloadcapacitanceonoutputpins,inputfrequency,andthe supplyvoltage(seetheCMOSInterfacePowerDissipationsectionintheApplicationInformation). Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com DIGITAL CHARACTERISTICS Typicalvaluesareat+25°C,AVDD=1.8V,DRVDD=1.8V,and50%clockdutycycle,unlessotherwisenoted.Minimumand maximumvaluesareacrossthefulltemperaturerange:T =–40°CtoT =+85°C,AVDD=1.8V,andDRVDD=1.8V. MIN MAX ADS4126,ADS4129,ADS4146,ADS4149 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DIGITALINPUTS(RESET,SCLK,SDATA,SEN,OE) High-levelinputvoltage RESET,SCLK,SDATA,and 1.3 V SENsupport1.8Vand3.3V Low-levelinputvoltage CMOSlogiclevels 0.4 V High-levelinputvoltage OEonlysupports1.8VCMOS 1.3 V Low-levelinputvoltage logiclevels 0.4 V High-levelinputcurrent:SDATA,SCLK(1) VHIGH=1.8V 10 µA High-levelinputcurrent:SEN VHIGH=1.8V 0 µA Low-levelinputcurrent:SDATA,SCLK VLOW=0V 0 µA Low-levelinputcurrent:SEN VLOW=0V 10 µA DIGITALOUTPUTS(CMOSINTERFACE:D0TOD13,OVR_SDOUT) High-leveloutputvoltage DRVDD–0.1 DRVDD V Low-leveloutputvoltage 0 0.1 V DIGITALOUTPUTS(LVDSINTERFACE:DA0P/MTODA13P/M,DB0P/MTODB13P/M,CLKOUTP/M) High-leveloutputvoltage(2) VODH StandardswingLVDS 270 +350 430 mV Low-leveloutputvoltage(2) VODL StandardswingLVDS –430 –350 –270 mV High-leveloutputvoltage(2) VODH LowswingLVDS +200 mV Low-leveloutputvoltage(2) VODL LowswingLVDS –200 mV Outputcommon-modevoltage VOCM 0.85 1.05 1.25 V (1) SDATAandSCLKhaveaninternal180kΩpull-downresistor. (2) Withanexternal100Ωtermination. 8 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 PIN CONFIGURATION (LVDS MODE) RGZPACKAGE(1) QFN-48 (TOPVIEW) P M 1_ 1_ P M P M P M P M P M 1 1 _ _ _ _ _ _ _ _ _ _ D D 9 9 7 7 5 5 3 3 1 1 _ _ D D D D D D D D D D 0 0 _ _ _ _ _ _ _ _ _ _ 1 1 8 8 6 6 4 4 2 2 0 0 D D D D D D D D D D D D 48 47 46 45 44 43 42 41 40 39 38 37 DRGND 1 36 DRGND DRVDD 2 35 DRVDD OVR_SDOUT 3 34 NC CLKOUTM 4 33 NC CLKOUTP 5 32 NC DFS 6 31 NC OE 7 30 RESET AVDD 8 29 SCLK AGND 9 28 SDATA CLKP 10 27 SEN CLKM 11 26 AVDD AGND 12 25 AGND 13 14 15 16 17 18 19 20 21 22 23 24 M D P M D D D D C D D D C N N N N D N D N D E D V G I I G V G V V V V A A A A A A R A E S E R (1) ThePowerPADisconnectedtoDRGND. Figure1. ADS412xLVDSPinout Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com RGZPACKAGE(2) QFN-48 (TOPVIEW) P M P M 3_ 3_ 1_ 1_ P M P M P M P M 1 1 1 1 _ _ _ _ _ _ _ _ D D D D 9 9 7 7 5 5 3 3 _ _ _ _ D D D D D D D D 2 2 0 0 _ _ _ _ _ _ _ _ 1 1 1 1 8 8 6 6 4 4 2 2 D D D D D D D D D D D D 48 47 46 45 44 43 42 41 40 39 38 37 DRGND 1 36 DRGND DRVDD 2 35 DRVDD OVR_SDOUT 3 34 D0_D1_P CLKOUTM 4 33 D0_D1_M CLKOUTP 5 32 NC DFS 6 31 NC OE 7 30 RESET AVDD 8 29 SCLK AGND 9 28 SDATA CLKP 10 27 SEN CLKM 11 26 AVDD AGND 12 25 AGND 13 14 15 16 17 18 19 20 21 22 23 24 M D P M D D D D C D D D C N N N N D N D N D E D V G I I G V G V V V V A A A A A A R A E S E R (2) ThePowerPAD™isconnectedtoDRGND. Figure2. ADS414xLVDSPinout ADS412x,ADS414xPinAssignments(LVDSMode) #OF PINNAME PINNUMBER PINS FUNCTION DESCRIPTION AVDD 8,18,20,22,24,26 6 I 1.8Vanalogpowersupply AGND 9,12,14,17,19,25 6 I Analogground CLKP 10 1 I Differentialclockinput,positive CLKM 11 1 I Differentialclockinput,negative INP 15 1 I Differentialanaloginput,positive INM 16 1 I Differentialanaloginput,negative Outputsthecommon-modevoltage(0.95V)thatcanbeusedexternallytobiasthe VCM 13 1 O analoginputpins. SerialinterfaceRESETinput. Whenusingtheserialinterfacemode,theinternalregistersmustinitializethrough hardwareRESETbyapplyingahighpulseonthispinorbyusingthesoftwarereset RESET 30 1 I option;refertotheSerialInterfacesection. WhenRESETistiedhigh,theinternalregistersareresettothedefaultvalues.Inthis condition,SENcanbeusedasananalogcontrolpin. RESEThasaninternal180kΩpull-downresistor. ThispinfunctionsasaserialinterfaceclockinputwhenRESETislow.WhenRESETis SCLK 29 1 I high,SCLKhasnofunctionandshouldbetiedtoground.Thispinhasaninternal 180kΩpull-downresistor. ThispinfunctionsasaserialinterfacedatainputwhenRESETislow.WhenRESETis SDATA 28 1 I high,SDATAfunctionsasaSTANDBYcontrolpin(seeTable9).Thispinhasan internal180kΩpull-downresistor. ThispinfunctionsasaserialinterfaceenableinputwhenRESETislow.WhenRESET SEN 27 1 I ishigh,SENhasnofunctionandshouldbetiedtoAVDD.Thispinhasaninternal 180kΩpull-upresistortoAVDD. 10 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 ADS412x,ADS414xPinAssignments(LVDSMode)(continued) #OF PINNAME PINNUMBER PINS FUNCTION DESCRIPTION Outputbufferenableinput,activehigh;thispinhasaninternal180kΩpull-upresistorto OE 7 1 I DRVDD. Dataformatselectinput.ThispinsetstheDATAFORMAT(twoscomplementoroffset DFS 6 1 I binary)andtheLVDS/CMOSoutputinterfacetype.SeeTable7fordetailedinformation. RESERVED 23 1 I Digitalcontrolpin,reservedforfutureuse CLKOUTP 5 1 O Differentialoutputclock,true CLKOUTM 4 1 O Differentialoutputclock,complement RefertoFigure1and D0_D1_P 1 O DifferentialoutputdataD0andD1multiplexed,true Figure2 RefertoFigure1and D0_D1_M 1 O DifferentialoutputdataD0andD1multiplexed,complement Figure2 RefertoFigure1and D2_D3_P 1 O DifferentialoutputdataD2andD3multiplexed,true Figure2 RefertoFigure1and D2_D3_M 1 O DifferentialoutputdataD2andD3multiplexed,complement Figure2 RefertoFigure1and D4_D5_P 1 O DifferentialoutputdataD4andD5multiplexed,true Figure2 RefertoFigure1and D4_D5_M 1 O DifferentialoutputdataD4andD5multiplexed,complement Figure2 RefertoFigure1and D6_D7_P 1 O DifferentialoutputdataD6andD7multiplexed,true Figure2 RefertoFigure1and D6_D7_M 1 O DifferentialoutputdataD6andD7multiplexed,complement Figure2 RefertoFigure1and D8_D9_P 1 O DifferentialoutputdataD8andD9multiplexed,true Figure2 RefertoFigure1and D8_D9_M 1 O DifferentialoutputdataD8andD9multiplexed,complement Figure2 RefertoFigure1and D10_D11_P 1 O DifferentialoutputdataD10andD11multiplexed,true Figure2 RefertoFigure1and D10_D11_M 1 O DifferentialoutputdataD10andD11multiplexed,complement Figure2 RefertoFigure1and D12_D13_P 1 O DifferentialoutputdataD12andD13multiplexed,true Figure2 RefertoFigure1and D12_D13_M 1 O DifferentialoutputdataD12andD13multiplexed,complement Figure2 Thispinfunctionsasanout-of-rangeindicatorafterreset,whenregisterbit OVR_SDOUT 3 1 O READOUT=0,andfunctionsasaserialregisterreadoutpinwhenREADOUT=1. DRVDD 2,35 2 I 1.8Vdigitalandoutputbuffersupply DRGND 1,36,PAD 2 I Digitalandoutputbufferground RefertoFigure1and NC — — Donotconnect Figure2 Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com PIN CONFIGURATION (CMOS MODE) RGZPACKAGE(3) QFN-48 (TOPVIEW) 1 0 1 1 9 8 7 6 5 4 3 2 1 0 D D D D D D D D D D D D 48 47 46 45 44 43 42 41 40 39 38 37 DRGND 1 36 DRGND DRVDD 2 35 DRVDD OVR_SDOUT 3 34 NC UNUSED 4 33 NC CLKOUT 5 32 NC DFS 6 31 NC OE 7 30 RESET AVDD 8 29 SCLK AGND 9 28 SDATA CLKP 10 27 SEN CLKM 11 26 AVDD AGND 12 25 AGND 13 14 15 16 17 18 19 20 21 22 23 24 M D P M D D D D C D D D C N N N N D N D N D E D V G I I G V G V V V V A A A A A A R A E S E R (3) ThePowerPADisconnectedtoDRGND. Figure3. ADS412xCMOSPinout 12 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 RGZPACKAGE(4) QFN-48 (TOPVIEW) 3 2 1 0 1 1 1 1 9 8 7 6 5 4 3 2 D D D D D D D D D D D D 48 47 46 45 44 43 42 41 40 39 38 37 DRGND 1 36 DRGND DRVDD 2 35 DRVDD OVR_SDOUT 3 34 D1 UNUSED 4 33 D0 CLKOUT 5 32 NC DFS 6 31 NC OE 7 30 RESET AVDD 8 29 SCLK AGND 9 28 SDATA CLKP 10 27 SEN CLKM 11 26 AVDD AGND 12 25 AGND 13 14 15 16 17 18 19 20 21 22 23 24 M D P M D D D D C D D D C N N N N D N D N D E D V G I I G V G V V V V A A A A A A R A E S E R (4) ThePowerPADisconnectedtoDRGND. Figure4. ADS414xCMOSPinout ADS412x,ADS414xPinAssignments(CMOSMode) #OF PINNAME PINNUMBER PINS FUNCTION DESCRIPTION AVDD 8,18,20,22,24,26 6 I 1.8Vanalogpowersupply AGND 9,12,14,17,19,25 6 I Analogground CLKP 10 1 I Differentialclockinput,positive CLKM 11 1 I Differentialclockinput,negative INP 15 1 I Differentialanaloginput,positive INM 16 1 I Differentialanaloginput,negative Outputsthecommon-modevoltage(0.95V)thatcanbeusedexternallytobiasthe VCM 13 1 O analoginputpins. SerialinterfaceRESETinput. Whenusingtheserialinterfacemode,theinternalregistersmustinitializethrough hardwareRESETbyapplyingahighpulseonthispinorbyusingthesoftwarereset RESET 30 1 I option;refertotheSerialInterfacesection. WhenRESETistiedhigh,theinternalregistersareresettothedefaultvalues.Inthis condition,SENcanbeusedasananalogcontrolpin. RESEThasaninternal180kΩpull-downresistor. ThispinfunctionsasaserialinterfaceclockinputwhenRESETislow.WhenRESETis SCLK 29 1 I high,SCLKhasnofunctionandshouldbetiedtoground.Thispinhasaninternal 180kΩpull-downresistor. ThispinfunctionsasaserialinterfacedatainputwhenRESETislow.WhenRESETis SDATA 28 1 I high,SDATAfunctionsasaSTANDBYcontrolpin(seeTable9).Thispinhasan internal180kΩpull-downresistor. ThispinfunctionsasaserialinterfaceenableinputwhenRESETislow.WhenRESET SEN 27 1 I ishigh,SENhasnofunctionandshouldbetiedtoAVDD.Thispinhasaninternal 180kΩpull-upresistortoAVDD. Outputbufferenableinput,activehigh;thispinhasaninternal180kΩpull-upresistorto OE 7 1 I DRVDD. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com ADS412x,ADS414xPinAssignments(CMOSMode)(continued) #OF PINNAME PINNUMBER PINS FUNCTION DESCRIPTION Dataformatselectinput.ThispinsetstheDATAFORMAT(twoscomplementoroffset DFS 6 1 I binary)andtheLVDS/CMOSoutputinterfacetype.SeeTable7fordetailedinformation. RESERVED 23 1 I Digitalcontrolpin,reservedforfutureuse CLKOUT 5 1 O CMOSoutputclock RefertoFigure3and D0 1 O 12-bit/14-bitCMOSoutputdata Figure4 RefertoFigure3and D1 1 O 12-bit/14-bitCMOSoutputdata Figure4 RefertoFigure3and D2 1 O 12-bit/14-bitCMOSoutputdata Figure4 RefertoFigure3and D3 1 O 12-bit/14-bitCMOSoutputdata Figure4 RefertoFigure3and D4 1 O 12-bit/14-bitCMOSoutputdata Figure4 RefertoFigure3and D5 1 O 12-bit/14-bitCMOSoutputdata Figure4 RefertoFigure3and D6 1 O 12-bit/14-bitCMOSoutputdata Figure4 RefertoFigure3and D7 1 O 12-bit/14-bitCMOSoutputdata Figure4 RefertoFigure3and D8 1 O 12-bit/14-bitCMOSoutputdata Figure4 RefertoFigure3and 12-bit/14-bitCMOSoutputdata D9 1 O Figure4 RefertoFigure3and D10 1 O 12-bit/14-bitCMOSoutputdata Figure4 RefertoFigure3and D11 1 O 12-bit/14-bitCMOSoutputdata Figure4 RefertoFigure3and D12 1 O 12-bit/14-bitCMOSoutputdata Figure4 RefertoFigure3and D13 1 O 12-bit/14-bitCMOSoutputdata Figure4 Thispinfunctionsasanout-of-rangeindicatorafterreset,whenregisterbit OVR_SDOUT 3 1 O READOUT=0,andfunctionsasaserialregisterreadoutpinwhenREADOUT=1. DRVDD 2,35 2 I 1.8Vdigitalandoutputbuffersupply DRGND 1,36,PAD 2 I Digitalandoutputbufferground UNUSED 4 1 — UnusedpininCMOSmode RefertoFigure3and NC — — Donotconnect Figure4 14 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 FUNCTIONAL BLOCK DIAGRAM DDR LVDS AVDD AGND DRVDD DRGND Interface CLKP CLKOUTP CLOCKGEN CLKM CLKOUTM D0_D1_P D0_D1_M D2_D3_P D2_D3_M Low-Latency Mode D4_D5_P (Default After Reset) INP D4_D5_M Sampling 12-Bit DDR Circuit ADC Serializer INM Common D6_D7_P Digital Functions D6_D7_M D8_D9_P D8_D9_M Control VCM Reference D10_D11_P Interface D10_D11_M OVR_SDOUT ADS4129 T K N A S OE SE CL SE AT DF E S D R S Figure5. ADS412xBlockDiagram Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com DDR LVDS AVDD AGND DRVDD DRGND Interface CLKP CLKOUTP CLOCKGEN CLKM CLKOUTM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M Low-Latency Mode D6_D7_P (Default After Reset) INP D6_D7_M Sampling 14-Bit DDR Circuit ADC Serializer INM Common D8_D9_P Digital Functions D8_D9_M D10_D11_P D10_D11_M VCM Reference Control D12_D13_P Interface D12_D13_M OVR_SDOUT ADS4149 T K N A S OE SE CL SE AT DF E S D R S Figure6. ADS414xBlockDiagram 16 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 TIMING CHARACTERISTICS Dn_Dn + 1_P Logic 0 Logic 1 V V ODL ODH Dn_Dn + 1_M V OCM GND (1) Withexternal100Ωtermination. Figure7. LVDSOutputVoltageLevels TIMING REQUIREMENTS: LVDS and CMOS Modes(1) Typicalvaluesareat+25°C,AVDD=1.8V,DRVDD=1.8V,samplingfrequency=250MSPS,sinewaveinputclock, C =5pF(2),andR =100Ω(3),unlessotherwisenoted.Minimumandmaximumvaluesareacrossthefulltemperature LOAD LOAD range:T =–40°CtoT =+85°C,AVDD=1.8V,andDRVDD=1.7Vto1.9V. MIN MAX PARAMETER CONDITIONS MIN TYP MAX UNIT t Aperturedelay 0.6 0.8 1.2 ns A Variationofaperture Betweentwodevicesatthesametemperatureand ±100 ps delay DRVDDsupply t Aperturejitter 100 f rms J S TimetovaliddataaftercomingoutofSTANDBY 5 25 µs mode Wakeuptime TimetovaliddataaftercomingoutofPDNGLOBAL 100 500 µs mode Clock Low-latencymode(defaultafterreset) 10 cycles ADClatency(4) Low-latencymodedisabled(gainenabled,offset 16 Clock correctiondisabled) cycles Low-latencymodedisabled(gainandoffset Clock 17 correctionenabled) cycles DDRLVDSMODE(5)(6) t Datasetuptime(3) Datavalid(7)tozero-crossingofCLKOUTP 0.75 1.1 ns SU tH Dataholdtime(3) Zero-crossingofCiLnKvOalUidT(7P) todatabecoming 0.35 0.6 ns Inputclockrisingedgecross-overtooutputclock Clockpropagation t risingedgecross-over 3 4.2 5.4 ns PDI delay 1MSPS≤samplingfrequency≤250MSPS Betweentwodevicesatthesametemperatureand Variationoft ±0.6 ns PDI DRVDDsupply (1) Timingparametersareensuredbydesignandcharacterizationbutarenotproductiontested. (2) C istheeffectiveexternalsingle-endedloadcapacitancebetweeneachoutputpinandground. LOAD (3) R isthedifferentialloadresistancebetweentheLVDSoutputpair. LOAD (4) Athigherfrequencies,t isgreaterthanoneclockperiodandoveralllatency=ADClatency+1. PDI (5) Measurementsaredonewithatransmissionlineof100Ωcharacteristicimpedancebetweenthedeviceandtheload.Setupandhold timespecificationstakeintoaccounttheeffectofjitterontheoutputdataandclock. (6) TheLVDStimingsareunchangedforlowlatencydisabledandenabled. (7) Datavalidreferstoalogichighof1.26Vandalogiclowof0.54V. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com TIMING REQUIREMENTS: LVDS and CMOS Modes(1) (continued) Typicalvaluesareat+25°C,AVDD=1.8V,DRVDD=1.8V,samplingfrequency=250MSPS,sinewaveinputclock, C =5pF(2),andR =100Ω(3),unlessotherwisenoted.Minimumandmaximumvaluesareacrossthefulltemperature LOAD LOAD range:T =–40°CtoT =+85°C,AVDD=1.8V,andDRVDD=1.7Vto1.9V. MIN MAX PARAMETER CONDITIONS MIN TYP MAX UNIT DDRLVDSMODE(continued) Dutycycleofdifferentialclock,(CLKOUTP– LVDSbitclockduty CLKOUTM) 42 48 54 % cycle 1MSPS≤samplingfrequency≤250MSPS Risetimemeasuredfrom–100mVto+100mV Datarisetime, t ,t Falltimemeasuredfrom+100mVto–100mV 0.14 ns RISE FALL Datafalltime 1MSPS≤samplingfrequency≤250MSPS Outputclockrise Risetimemeasuredfrom–100mVto+100mV t , CLKRISE time, Falltimemeasuredfrom+100mVto–100mV 0.14 ns t CLKFALL Outputclockfalltime 1MSPS≤samplingfrequency≤250MSPS Outputenable(OE)to t TimetovaliddataafterOEbecomesactive 50 100 ns OE datadelay PARALLELCMOSMODE(8)(9) Inputclocktodata Inputclockrisingedgecross-overtostartofdata tSTART delay valid(10) 1.1 ns t Datavalidtime Timeintervalofvaliddata(10) 2.5 3.2 ns DV Inputclockrisingedgecross-overtooutputclock Clockpropagation t risingedgecross-over 4 5.5 7 ns PDI delay 1MSPS≤samplingfrequency≤200MSPS Outputclockduty Dutycycleofoutputclock,CLKOUT 47 % cycle 1MSPS≤samplingfrequency≤200MSPS Risetimemeasuredfrom20%to80%ofDRVDD Datarisetime, t ,t Falltimemeasuredfrom80%to20%ofDRVDD 0.35 ns RISE FALL Datafalltime 1≤samplingfrequency≤250MSPS Outputclockrise Risetimemeasuredfrom20%to80%ofDRVDD t , CLKRISE time, Falltimemeasuredfrom80%to20%ofDRVDD 0.35 ns t CLKFALL Outputclockfalltime 1≤samplingfrequency≤200MSPS Outputenable(OE)to t TimetovaliddataafterOEbecomesactive 20 40 ns OE datadelay (8) Forf >200MSPS,itisrecommendedtouseanexternalclockfordatacaptureinsteadofthedeviceoutputclocksignal(CLKOUT). S (9) Lowlatencymodeenabled. (10) Datavalidreferstoalogichighof1.26Vandalogiclowof0.54V. 18 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 Table2.LVDSTimingAcrossSamplingFrequencies SAMPLING SETUPTIME(ns) HOLDTIME(ns) FREQUENCY (MSPS) MIN TYP MAX MIN TYP MAX 230 0.85 1.25 0.35 0.6 200 1.05 1.55 0.35 0.6 185 1.1 1.7 0.35 0.6 160 1.6 2.1 0.35 0.6 125 2.3 3 0.35 0.6 80 4.5 5.2 0.35 0.6 Table3.CMOSTimingAcrossSamplingFrequencies(LowLatencyEnabled) TIMINGSPECIFIEDWITHRESPECTTOOUTPUTCLOCK SAMPLING t (ns) t (ns) t (ns) FREQUENCY SETUP HOLD PDI (MSPS) MIN TYP MAX MIN TYP MAX MIN TYP MAX 200 1.6 2.2 1.8 2.5 4 5.5 7 185 1.8 2.4 1.9 2.7 4 5.5 7 160 2.3 2.9 2.2 3 4 5.5 7 125 3.1 3.7 3.2 4 4 5.5 7 80 5.4 6 5.4 6 4 5.5 7 Table4.CMOSTimingAcrossSamplingFrequencies(LowLatencyDisabled) TIMINGSPECIFIEDWITHRESPECTTOOUTPUTCLOCK SAMPLING t (ns) t (ns) t (ns) FREQUENCY SETUP HOLD PDI (MSPS) MIN TYP MAX MIN TYP MAX MIN TYP MAX 200 1 1.6 2 2.8 4 5.5 7 185 1.3 2 2.2 3 4 5.5 7 160 1.8 2.5 2.5 3.3 4 5.5 7 125 2.5 3.2 3.5 4.3 4 5.5 7 80 4.8 5.5 5.7 6.5 4 5.5 7 Table5.CMOSTimingAcrossSamplingFrequencies(LowLatencyEnabled) TIMINGSPECIFIEDWITHRESPECTTOINPUTCLOCK t (ns) t (ns) SAMPLINGFREQUENCY START DV (MSPS) MIN TYP MAX MIN TYP MAX 250 1.1 2.5 3.2 230 0.7 2.9 3.5 200 –0.3 3.5 4.2 185 –1 3.9 4.5 170 –1.5 4.3 5 Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com Table6.CMOSTimingAcrossSamplingFrequencies(LowLatencyDisabled) TIMINGSPECIFIEDWITHRESPECTTOINPUTCLOCK t (ns) t (ns) SAMPLINGFREQUENCY START DV (MSPS) MIN TYP MAX MIN TYP MAX 250 1.6 2.5 3.2 230 1.1 2.9 3.5 200 0.3 3.5 4.2 185 0 3.9 4.5 170 –1.3 4.3 5 N + 12 N + 2 N + 3 N + 4 N + 11 N + 1 Sample N N + 10 Input Signal t A CLKP Input Clock CLKM CLKOUTM CLKOUTP t t PDI H DDR LVDS 10 Clock Cycles(1) tSU Output Data(2) E O E O E O E O E O E O E O E O E O E O (DXP, DXM) N-10 N-9 N-8 N-7 N-6 N + 1 N + 2 N t PDI CLKOUT t Parallel CMOS 10 Clock Cycles(1) SU t H Output Data N-10 N-9 N-8 N-7 N-1 N N + 1 (1) ADC latency in low-latency mode. At higher sampling frequencies, t is greater than one clock cycle which then makes the overall DPI latency=ADClatency+1. (2) E=Evenbits(D0,D2,D4,etc).O=Oddbits(D1,D3,D5,etc). Figure8. LatencyDiagram 20 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 CLKM Input Clock CLKP t PDI CLKOUTP Output Clock CLKOUTM t t t t SU H SU H Output Dn_Dn + 1_P Data Pair Dn_Dn + 1_M Dn(1) Dn + 1(1) (1) Dn=bitsD0,D2,D4,etc.Dn+1=BitsD1,D3,D5,etc. Figure9. LVDSModeTiming CLKM Input Clock CLKP t PDI Output CLKOUT Clock t t SU H Output Data Dn Dn(1) CLKM Input Clock CLKP t START t DV Output Data Dn Dn(1) Dn=bitsD0,D1,D2,etc. Figure10. CMOSModeTiming Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com DEVICE CONFIGURATION The ADS412x/4x have several modes that can be configured using a serial programming interface, as described in Table 7, Table 8, and Table 9. In addition, the devices have two dedicated parallel pins for quickly configuring commonly used functions. The parallel pins are DFS (analog 4-level control pin) and OE (digital control pin). The analogcontrolpinscanbeeasilyconfiguredusingasimpleresistordivider(with10%toleranceresistors). Table7.DFS:AnalogControlPin DESCRIPTION VOLTAGEAPPLIEDONDFS (DataFormat/OutputInterface) 0,+100mV/–0mV Twoscomplement/DDRLVDS (3/8)AVDD±100mV Twoscomplement/parallelCMOS (5/8)AVDD±100mV Offsetbinary/parallelCMOS AVDD,+0mV/–100mV Offsetbinary/DDRLVDS Table8.OE:DigitalControlPin VOLTAGEAPPLIEDONOE DESCRIPTION 0 Outputdatabuffersdisabled AVDD Outputdatabuffersenabled Whentheserialinterfaceisnotused,theSDATApincanalsobeusedasadigitalcontrolpintoplacethedevice in standby mode. To enable this, the RESET pin must be tied high. In this mode, SEN and SCLK do not have anyalternativefunctions.KeepSENtiedhighandSCLKtiedlowontheboard. Table9.SDATA:DigitalControlPin VOLTAGEAPPLIEDONSDATA DESCRIPTION 0 Normaloperation Logichigh Deviceentersstandby AVDD (5/8) AVDD 3R (5/8) AVDD GND AVDD 2R (3/8) AVDD (3/8) AVDD 3R To Parallel Pin Figure11. SimplifiedDiagramtoConfigureDFSPin 22 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 SERIAL INTERFACE The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA are latched at every falling edge of SCLK when SEN is active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register address and the remaining eight bits are the register data. The interface can work with SCLK frequency from20MHzdowntoverylowspeeds(afewHertz)andalsowithnon-50%SCLKdutycycle. RegisterInitialization After power-up, the internal registers must be initialized to the default values. This initialization can be accomplishedinoneoftwoways: 1. EitherthroughhardwareresetbyapplyingahighpulseonRESETpin(ofwidthgreaterthan10ns),asshown inFigure12;or 2. By applying a software reset. When using the serial interface, set the RESET bit (D7 in register 00h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In thiscase,theRESETpiniskeptlow. Register Address Register Data SDATA A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 t DH t t SCLK DSU SCLK t t SLOADS SLOADH SEN RESET Figure12. SerialInterfaceTiming SERIAL INTERFACE TIMING CHARACTERISTICS Typicalvaluesat+25°C,minimumandmaximumvaluesacrossthefulltemperaturerange:T =–40°CtoT =+85°C, MIN MAX AVDD=1.8V,andDRVDD=1.8V,unlessotherwisenoted. PARAMETER MIN TYP MAX UNIT f SCLKfrequency(equalto1/t ) >dc 20 MHz SCLK SCLK t SENtoSCLKsetuptime 25 ns SLOADS t SCLKtoSENholdtime 25 ns SLOADH t SDATAsetuptime 25 ns DSU t SDATAholdtime 25 ns DH Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com Serial Register Readout The serial register readout function allows the contents of the internal registers to be read back on the OVR_SDOUT pin. This readback may be useful as a diagnostic check to verify the serial interface communicationbetweentheexternalcontrollerandtheADC. After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default. When thereadoutmodeisenabled,OVR_SDOUToutputsthecontentsoftheselectedregisterserially: 1. Set the READOUT register bit to '1'. This setting puts the device in serial readout mode and disables any further writes to the internal registers except the register at address 0. Note that the READOUT bit itself is also located in register 0. The device can exit readout mode by writing READOUT = 0. Only the contents of theregisterataddress0cannotbereadintheregisterreadoutmode. 2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be read. 3. Thedeviceseriallyoutputsthecontents(D7toD0)oftheselectedregisterontheOVR_SDOUTpin. 4. TheexternalcontrollercanlatchthecontentsatthefallingedgeofSCLK. 5. To exit the serial readout mode, the reset register bit READOUT = 0 enables writes into all registers of the device.Atthispoint,theOVR_SDOUTpinbecomesanover-rangeindicatorpin. Register Address A[7:0] = 0x00 Register Data D[7:0] = 0x01 SDATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SCLK SEN OVR_SDOUT(1) a) Enable Serial Readout (READOUT = 1) Register Address A[7:0] = 0x43 Register Data D[7:0] = XX (don’t care) SDATA A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK SEN OVR_SDOUT(2) 0 1 0 0 0 0 0 0 b) Read Contents of Register 0x43. This Register Has Been Initialized with 0x40(device is put in global power-down mode). (1) TheOVR_SDOUTpinfunctionsasOVR(READOUT=0). (2) TheOVR_SDOUTpinfunctionsasaserialreadout(READOUT=1). Figure13. SerialReadoutTimingDiagram 24 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 RESET TIMING CHARACTERISTICS Power Supply AVDD, DRVDD t 1 RESET t t 2 3 SEN NOTE:AhighpulseontheRESETpinisrequiredintheserialinterfacemodeincaseofinitializationthroughhardwarereset.Forparallel interfaceoperation,RESETmustbepermanentlytiedhigh. Figure14. ResetTimingDiagram RESET TIMING REQUIREMENTS Typicalvaluesat+25°Candminimumandmaximumvaluesacrossthefulltemperaturerange:T =–40°CtoT =+85°C, MIN MAX unlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Delayfrompower-upofAVDDandDRVDDtoRESET t Power-ondelay 1 ms 1 pulseactive PulsewidthofactiveRESETsignalthatresetsthe 10 ns t Resetpulsewidth 2 serialregisters 1(1) µs t DelayfromRESETdisabletoSENactive 100 ns 3 (1) Theresetpulseisneededonlywhenusingtheserialinterfaceconfiguration.Ifthepulsewidthisgreaterthan1µs,thedevicecould entertheparallelconfigurationmodebrieflyandthenreturnbacktoserialinterfacemode. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com SERIAL REGISTER MAP Table10summarizesthefunctionssupportedbytheserialinterface. Table10.SerialInterfaceRegisterMap(1) REGISTER DEFAULTVALUE ADDRESS AFTERRESET REGISTERDATA A[7:0](Hex) D[7:0](Hex) D7 D6 D5 D4 D3 D2 D1 D0 00 00 0 0 0 0 0 0 RESET READOUT 01 00 LVDSSWING 0 0 03 00 0 0 0 0 0 0 HIGHPERFMODE1 DISABLE 25 00 GAIN TESTPATTERNS GAIN LVDS LVDSDATA 26 00 0 0 0 0 0 0 CLKOUT STRENGTH STRENGTH EN 3D 00 DATAFORMAT OFFSET 0 0 0 0 0 CORR 3F 00 CUSTOMPATTERNHIGHD[13:6] 40 00 CUSTOMPATTERND[5:0] 0 0 EN EN CMOSCLKOUT 41 00 LVDSCMOS CLKOUT CLKOUTRISEPOSN CLKOUT STRENGTH RISE FALL DISLOW 42 00 CLKOUTFALLPOSN 0 0 STBY 0 0 LATENCY PDN 43 00 0 0 PDNOBUF 0 0 ENLVDSSWING GLOBAL HIGHPERF 4A 00 0 0 0 0 0 0 0 MODE2 BF 00 OFFSETPEDESTAL 0 0 FREEZE CF 00 OFFSET 0 OFFSETCORRTIMECONSTANT 0 0 CORR DF 00 0 0 LOWSPEED 0 0 0 0 (1) Multiplefunctionsinaregistercanbeprogrammedinasinglewriteoperation. DESCRIPTION OF SERIAL REGISTERS For best performance, two special mode register bits must be enabled: HI PERF MODE 1 and HI PERF MODE 2. RegisterAddress00h(Default=00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RESET READOUT Bits[7:2] Alwayswrite'0' Bit1 RESET:Softwareresetapplied Thisbitresetsallinternalregisterstothedefaultvaluesandself-clearsto0(default=1). Bit0 READOUT:Serialreadout Thisbitsetstheserialreadoutoftheregisters. 0=Serialreadoutofregistersdisabled;theOVR_SDOUTpinfunctionsasanover-voltage indicator. 1=Serialreadoutenabled;theOVR_SDOUTpinfunctionsasaserialdatareadout. 26 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 RegisterAddress01h(Default=00h) 7 6 5 4 3 2 1 0 LVDSSWING 0 0 Bits[7:2] LVDSSWING:LVDSswingprogrammability(1) 000000=DefaultLVDSswing;±350mVwithexternal100Ω termination 011011=LVDSswingincreasesto±410mV 110010=LVDSswingincreasesto±465mV 010100=LVDSswingincreasesto±570mV 111110=LVDSswingdecreasesto±200mV 001111=LVDSswingdecreasesto±125mV Bits[1:0] Alwayswrite'0' (1) TheENLVDSSWINGregisterbitsmustbesettoenableLVDSswingcontrol. RegisterAddress03h(Default=00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 HIPERFMODE1 Bits[7:2] Alwayswrite'0' Bits[1:0] HIPERFMODE1:Highperformancemode1 00=Defaultperformanceafterreset 01=Donotuse 10=Donotuse 11=Forbestperformanceacrosssamplingclockandinputsignalfrequencies,settheHIGHPERF MODE1bits Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com RegisterAddress25h(Default=00h) 7 6 5 4 3 2 1 0 GAIN DISABLEGAIN TESTPATTERNS Bits[7:4] GAIN:Gainprogrammability Thesebitssetthegainprogrammabilityin0.5dBsteps. 0000=0dBgain(defaultafterreset) 0111=3.5dBgain 0001=0.5dBgain 1000=4.0dBgain 0010=1.0dBgain 1001=4.5dBgain 0011=1.5dBgain 1010=5.0dBgain 0100=2.0dBgain 1011=5.5dBgain 0101=2.5dBgain 1100=6dBgain 0110=3.0dBgain Bit3 DISABLEGAIN:Gainsetting Thisbitsetsthegain. 0=Gainenabled;gainissetbytheGAINbitsonlyiflow-latencymodeisdisabled 1=Gaindisabled Bits[2:0] TESTPATTERNS:Datacapture Thesebitsverifydatacapture. 000=Normaloperation 001=Outputsall0s 010=Outputsall1s 011=Outputstogglepattern IntheADS4146/49,outputdataD[13:0]isanalternatingsequenceof01010101010101and 10101010101010. IntheADS4126/29,outputdataD[11:0]isanalternatingsequenceof010101010101and 101010101010. 100=Outputsdigitalramp InADS4149/46,outputdataincrementsbyoneLSB(14-bit)everyclockcyclefromcode0to code16383 InADS4129/26,outputdataincrementsbyoneLSB(12-bit)every4thclockcyclefromcode0to code4095 101=Outputcustompattern(useregisters3Fhand40hforsettingthecustompattern) 110=Unused 111=Unused 28 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 RegisterAddress26h(Default=00h) 7 6 5 4 3 2 1 0 LVDSCLKOUT LVDSDATA 0 0 0 0 0 0 STRENGTH STRENGTH Bits[7:2] Alwayswrite'0' Bit1 LVDSCLKOUTSTRENGTH:LVDSoutputclockbufferstrength ThisbitdeterminestheexternalterminationtobeusedwiththeLVDSoutputclockbuffer. 0=100Ω externaltermination(defaultstrength) 1=50Ω externaltermination(2xstrength) Bit0 LVDSDATASTRENGTH:LVDSdatabufferstrength ThisbitdeterminestheexternalterminationtobeusedwithalloftheLVDSdatabuffers. 0=100Ω externaltermination(defaultstrength) 1=50Ω externaltermination(2xstrength) RegisterAddress3Dh(Default=00h) 7 6 5 4 3 2 1 0 ENOFFSET DATAFORMAT 0 0 0 0 0 CORR Bits[7:6] DATAFORMAT:Dataformatselection Thesebitsselectsthedataformat. 00=TheDFSpincontrolsdataformatselection 10=Twoscomplement 11=Offsetbinary Bit5 ENABLEOFFSETCORR:Offsetcorrectionsetting Thisbitsetstheoffsetcorrection. 0=Offsetcorrectiondisabled 1=Offsetcorrectionenabled Bits[4:0] Alwayswrite'0' RegisterAddress3Fh(Default=00h) 7 6 5 4 3 2 1 0 CUSTOM CUSTOM CUSTOM CUSTOM CUSTOM CUSTOM CUSTOM CUSTOM PATTERND13 PATTERND12 PATTERND11 PATTERND10 PATTERND9 PATTERND8 PATTERND7 PATTERND6 Bits[7:0] CUSTOMPATTERN(1) Thesebitssetthecustompattern. (1) FortheADS414x,outputdatabits13to0areCUSTOMPATTERND[13:0].FortheADS412x,outputdatabits11to0areCUSTOM PATTERND[13:2]. RegisterAddress40h(Default=00h) 7 6 5 4 3 2 1 0 CUSTOM CUSTOM CUSTOM CUSTOM CUSTOM CUSTOM 0 0 PATTERND5 PATTERND4 PATTERND3 PATTERND2 PATTERND1 PATTERND0 Bits[7:2] CUSTOMPATTERN(1) Thesebitssetthecustompattern. Bits[1:0] Alwayswrite'0' (1) FortheADS414x,outputdatabits13to0areCUSTOMPATTERND[13:0].FortheADS412x,outputdatabits11to0areCUSTOM PATTERND[13:2]. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com RegisterAddress41h(Default=00h) 7 6 5 4 3 2 1 0 ENCLKOUT ENCLKOUT LVDSCMOS CMOSCLKOUTSTRENGTH CLKOUTRISEPOSN RISE FALL Bits[7:6] LVDSCMOS:Interfaceselection Thesebitsselecttheinterface. 00=TheDFSpincontrolstheselectionofeitherLVDSorCMOSinterface 10=TheDFSpincontrolstheselectionofeitherLVDSorCMOSinterface 01=DDRLVDSinterface 11=ParallelCMOSinterface Bits[5:4] CMOSCLKOUTSTRENGTH ControlsstrengthofCMOSoutputclockonly. 00=Maximumstrength(recommendedandusedforspecifiedtimings) 01=Mediumstrength 10=Lowstrength 11=Verylowstrength Bit3 ENABLECLKOUTRISE 0=Disablescontrolofoutputclockrisingedge 1=Enablescontrolofoutputclockrisingedge Bits[2:1] CLKOUTRISEPOSN:CLKOUTrisecontrol Controlspositionofoutputclockrisingedge LVDSinterface: 00=Defaultposition(timingsarespecifiedinthiscondition) 01=Setupreducesby500ps,holdincreasesby500ps 10=Datatransitionisalignedwithrisingedge 11=Setupreducesby200ps,holdincreasesby200ps CMOSinterface: 00=Defaultposition(timingsarespecifiedinthiscondition) 01=Setupreducesby100ps,holdincreasesby100ps 10=Setupreducesby200ps,holdincreasesby200ps 11=Setupreducesby1.5ns,holdincreasesby1.5ns Bit0 ENABLECLKOUTFALL 0=Disablescontrolofoutputclockfalledge 1=Enablescontrolofoutputclockfalledge 30 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 RegisterAddress42h(Default=00h) 7 6 5 4 3 2 1 0 DISLOW CLKOUTFALLCTRL 0 0 STBY 0 0 LATENCY Bits[7:6] CLKOUTFALLCTRL Controlspositionofoutputclockfallingedge LVDSinterface: 00=Defaultposition(timingsarespecifiedinthiscondition) 01=Setupreducesby400ps,holdincreasesby400ps 10=Datatransitionisalignedwithrisingedge 11=Setupreducesby200ps,holdincreasesby200ps CMOSinterface: 00=Defaultposition(timingsarespecifiedinthiscondition) 01=Fallingedgeisadvancedby100ps 10=Fallingedgeisadvancedby200ps 11=Fallingedgeisadvancedby1.5ns Bits[5:4] Alwayswrite'0' Bit3 DISLOWLATENCY:Disablelowlatency Thisbitdisableslow-latencymode, 0=Lowlatencymodeisenabled.Digitalfunctionssuchasgain,testpatternsandoffsetcorrection aredisabled 1=Low-latencymodeisdisabled.Thissettingenablesthedigitalfunctions.SeetheDigital FunctionsandLowLatencyModesection. Bit2 STBY:Standbymode Thisbitsetsthestandbymode. 0=Normaloperation 1=OnlytheADCandoutputbuffersarepowereddown;internalreferenceisactive;wake-uptime fromstandbyisfast Bits[1:0] Alwayswrite'0' Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com RegisterAddress43h(Default=00h) 7 6 5 4 3 2 1 0 0 PDNGLOBAL 0 PDNOBUF 0 0 ENLVDSSWING Bit0 Alwayswrite'0' Bit6 PDNGLOBAL:Power-down Thisbitsetsthestateofoperation. 0=Normaloperation 1=Totalpowerdown;theADC,internalreferences,andoutputbuffersarepowereddown;slow wake-uptime. Bit5 Alwayswrite'0' Bit4 PDNOBUF:Power-downoutputbuffer Thisbitsettheoutputdataandclockpins. 0=Outputdataandclockpinsenabled 1=Outputdataandclockpinspowereddownandputinhigh-impedancestate Bits[3:2] Alwayswrite'0' Bits[1:0] ENLVDSSWING:LVDSswingcontrol 00=LVDSswingcontrolusingLVDSSWINGregisterbitsisdisabled 01=Donotuse 10=Donotuse 11=LVDSswingcontrolusingLVDSSWINGregisterbitsisenabled RegisterAddress4Ah(Default=00h) 7 6 5 4 3 2 1 0 HIPERF 0 0 0 0 0 0 0 MODE2 Bits[7:1] Alwayswrite'0' Bit[0] HIPERFMODE2:Highperformancemode2 Thisbitisrecommendedforhighinputsignalfrequenciesgreaterthan230MHz. 0=Defaultperformanceafterreset 1=Forbestperformancewithhigh-frequencyinputsignals,settheHIGHPERFMODE2bit 32 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 RegisterAddressBFh(Default=00h) 7 6 5 4 3 2 1 0 OFFSETPEDESTAL 0 0 Bits[7:2] OFFSETPEDESTAL Thesebitssettheoffsetpedestal. Whentheoffsetcorrectionisenabled,thefinalconvergedvalueaftertheoffsetiscorrectedisthe ADCmid-codevalue.Apedestalcanbeaddedtothefinalconvergedvaluebyprogrammingthese bits. ADS414xVALUE PEDESTAL 011111 31LSB 011110 30LSB 011101 29LSB — — 000000 0LSB — — 111111 –1LSB 111110 –2LSB — — 100000 –32LSB Bits[1:0] Alwayswrite'0' Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com RegisterAddressCFh(Default=00h) 7 6 5 4 3 2 1 0 FREEZE BYPASS OFFSET OFFSET OFFSETCORRTIMECONSTANT 0 0 CORR CORR Bit7 FREEZEOFFSETCORR Thisbitsetsthefreezeoffsetcorrection. 0=Estimationofoffsetcorrectionisnotfrozen(bitENOFFSETCORRmustbeset) 1=Estimationofoffsetcorrectionisfrozen(bitENOFFSETCORRmustbeset).Whenfrozen,the lastestimatedvalueisusedforoffsetcorrectioneveryclockcycle.SeeOFFSETCORRECTION, OffsetCorrection. Bit6 Alwayswrite'0' Bits[5:2] OFFSETCORRTIMECONSTANT Thesebitssettheoffsetcorrectiontimeconstantforthecorrectionlooptimeconstantinnumberof clockcycles. VALUE TIMECONSTANT(NumberofClockCycles) 0000 1M 0001 2M 0010 4M 0011 8M 0100 16M 0101 32M 0110 64M 0111 128M 1000 256M 1001 512M 1010 1G 1011 2G Bits[1:0] Alwayswrite'0' RegisterAddressDFh(Default=00h) 7 6 5 4 3 2 1 0 0 0 LOWSPEED 0 0 0 0 Bits[7:1] Alwayswrite'0' Bit0 LOWSPEED:Low-speedmode 00,01,10=Low-speedmodedisabled(defaultstateafterreset);thissettingisrecommendedfor samplingratesgreaterthan80MSPS. 11=Low-speedmodeenabled;thissettingisrecommendedforsamplingrateslessthanorequal to80MSPS. 34 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 TYPICAL CHARACTERISTICS: ADS4126 At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. FFTFOR10MHzINPUTSIGNAL FFTFOR170MHzINPUTSIGNAL 0 0 SFDR = 94dBc SFDR = 82.5dBc SNR = 70dBFS SNR = 69.2dBFS -20 SINAD = 70dBFS -20 SINAD = 68.9dBFS THD = 93dBc THD = 80.7dBc B) -40 B) -40 d d e ( e ( ud -60 ud -60 plit plit m m A -80 A -80 -100 -100 -120 -120 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80 Frequency (MHz) Frequency (MHz) Figure15. Figure16. FFTFOR300MHzINPUTSIGNAL FFTFORTWO-TONEINPUTSIGNAL 0 0 SFDR = 78.3dBc -10 Each Tone at-7dBFS Amplitude -20 SSINNRA D= =67 6.67ddBBFFSS --2300 ffIINN12== 118950MMHHzz THD = 75.3dBc -40 Two-Tone IMD = 89dBFS B) -40 B) -50 SFDR = 93dBFS e (d e (d -60 ud -60 ud -70 plit plit -80 Am -80 Am -90 -100 -110 -100 -120 -130 -120 -140 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80 Frequency (MHz) Frequency (MHz) Figure17. Figure18. SFDRvsINPUTFREQUENCY SNRvsINPUTFREQUENCY 95 71.0 70.5 90 -2dBFSInput, 0dB Gain 70.0 69.5 85 69.0 c) S) B 80 F 68.5 d B FDR ( 75 NR (d 6687..05 -1dBFSInput, 1dB Gain S S 67.0 70 66.5 65 -1dBFSInput, 1dB Gain 66.0 -2dBFSInput, 0dB Gain 65.5 60 65.0 0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500 Input Frequency (MHz) Input Frequency (MHz) Figure19. Figure20. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4126 (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. SFDRvsINPUTFREQUENCY(CMOS) SNRvsINPUTFREQUENCY(CMOS) 90 71.5 88 71.0 86 70.5 84 70.0 c) 82 S) B F d 80 B 69.5 DR ( 78 R (d 69.0 F N S 76 S 68.5 74 68.0 72 70 67.5 68 67.0 0 50 100 150 200 250 300 350 0 50 100 150 200 250 300 350 Input Frequency (MHz) Input Frequency (MHz) Figure21. Figure22. SFDRACROSSGAINANDINPUTFREQUENCY SINADACROSSGAINANDINPUTFREQUENCY 88 71 170MHz 150MHz 170MHz 70 84 69 150MHz R (dBc) 8706 300MHz 220MHz D (dBFS) 6687 220MHz D A 66 F N 400MHz 300MHz S 72 SI 65 400MHz 64 68 63 500MHz 500MHz 64 62 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Gain (dB) Gain (dB) Figure23. Figure24. PERFORMANCEACROSSINPUTAMPLITUDE(Single PERFORMANCEACROSSINPUTAMPLITUDE(Single Tone) Tone) 105 74 105 74 SFDR (dBFS) SFDR (dBFS) 95 73 95 73 S) 85 72 S) 85 72 F F B S B S FDR (dBc, d 7655 SNR (dBFS) 7710 NR (dBFS) FDR (dBc, d 7655 SNR (dBFS) 7710 NR (dBFS) S 55 69 S 55 69 SFDR (dBc) SFDR (dBc) 45 68 45 68 Input Frequency = 40.1MHz Input Frequency = 170.1MHz 35 67 35 67 -50 -40 -30 -20 -10 0 -50 -40 -30 -20 -10 0 Input Amplitude (dBFS) Input Amplitude (dBFS) Figure25. Figure26. 36 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 TYPICAL CHARACTERISTICS: ADS4126 (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. PERFORMANCEvsINPUTCOMMON-MODEVOLTAGE SFDRACROSSTEMPERATUREvsAVDDSUPPLY 90 71.0 88 SNR 87 88 70.5 86 AVDD = 1.8V AVDD = 1.9V AVDD = 1.85V 86 70.0 Bc) SFDR SN Bc) 85 d R d R ( 84 69.5 (d R ( 84 D B D F F F S S S 83 82 69.0 ) AVDD = 1.75V AVDD = 1.7V 82 80 68.5 81 Input Frequency = 40MHz f = 40MHz IN 78 68.0 80 0.80 0.85 0.90 0.95 1.00 1.05 1.10 -40 -15 10 35 60 85 Input Common-Mode Voltage (V) Temperature (°C) Figure27. Figure28. SNRACROSSTEMPERATUREvsAVDDSUPPLY PERFORMANCEACROSSDRVDDSUPPLYVOLTAGE 72.0 87 73.0 f = 40MHz IN 71.5 86 72.5 SFDR AVDD = 1.7V, 1.85V 71.0 85 72.0 FS) Bc) SN B d R R (d 70.5 AVDD = 1.75V, 1.8V, 1.9V DR ( 84 71.5 (dB N F F S 70.0 S 83 71.0 S) SNR 69.5 82 70.5 f = 40MHz IN 69.0 81 70.0 -40 -15 10 35 60 85 1.70 1.75 1.80 1.85 1.90 Temperature (°C) DRVDD Supply (V) Figure29. Figure30. PERFORMANCEACROSSDRVDDSUPPLYVOLTAGE (CMOS) PERFORMANCEACROSSINPUTCLOCKAMPLITUDE 87 73.0 90 78 86 76 86 72.5 82 74 SFDR SFDR (dBc) 85 72.0 78 72 Bc) SN Bc) SN d R d 74 70 R R ( 84 71.5 (d R ( (d D B D 70 68 B SF 83 71.0 FS) SF 66 SNR (dBFS) 66 FS) SNR 62 64 82 70.5 58 62 Input Frequency = 170MHz 81 70.0 54 60 1.70 1.75 1.80 1.85 1.90 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 DRVDD Supply (V) Differential Clock Amplitude (V ) PP Figure31. Figure32. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4126 (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. PERFORMANCEACROSSINPUTCLOCKDUTYCYCLE INTEGRALNONLINEARITY 86 72.0 0.3 85 71.5 0.2 84 71.0 0.1 HD (dBc) 83 THD SNR 70.5 SNR (dBF NL (LSB) 0 T S I 82 70.0 ) -0.1 81 69.5 -0.2 Input Frequency = 10MHz 80 69.0 -0.3 25 30 35 40 45 50 55 60 65 70 75 0 500 1000 1500 2000 2500 3000 3500 4000 Input Clock Duty Cycle (%) Output Code (LSB) Figure33. Figure34. DIFFERENTIALNONLINEARITY 0.20 0.15 0.10 B) 0.05 S L (L 0 N D -0.05 -0.10 -0.15 -0.20 0 500 1000 1500 2000 2500 3000 3500 4000 Output Code (LSB) Figure35. 38 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 TYPICAL CHARACTERISTICS: ADS4129 At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. FFTFOR10MHzINPUTSIGNAL FFTFOR170MHzINPUTSIGNAL 0 0 SFDR = 87.7dBc SFDR = 87.2dBc SNR = 70.3dBFS SNR = 69.6dBFS -20 SINAD = 70.2dBFS -20 SINAD = 69.4dBFS THD = 83.5dBc THD = 83.9dBc B) -40 B) -40 d d e ( e ( ud -60 ud -60 plit plit m m A -80 A -80 -100 -100 -120 -120 0 25 50 75 100 125 0 25 50 75 100 125 Frequency (MHz) Frequency (MHz) Figure36. Figure37. FFTFOR300MHzINPUTSIGNAL FFTFORTWO-TONEINPUTSIGNAL 0 0 SFDR = 79.3dBc -10 Each Tone at -20 SINASDN R= =6 76.85ddBBFFSS --2300 -7dBfFINS1 =A m18p5liMtuHdez THD = 76.3dBc -40 fIN2= 190MHz B) -40 B) -50 Two-Tone IMD = 90dBFS e (d e (d -60 SFDR = 94dBFS ud -60 ud -70 plit plit -80 Am -80 Am -90 -100 -110 -100 -120 -130 -120 -140 0 25 50 75 100 125 0 25 50 75 100 125 Frequency (MHz) Frequency (GHz) Figure38. Figure39. SFDRvsINPUTFREQUENCY SNRvsINPUTFREQUENCY 95 71.0 70.5 90 -2dBFSInput, 0dB Gain -1dBFSInput, 1dB Gain 70.0 85 69.5 c) S) 69.0 B 80 F d B 68.5 DR ( 75 -2dBFSInput, 0dB Gain R (d 68.0 -1dBFSInput, 1dB Gain F N S S 67.5 70 67.0 66.5 65 66.0 60 65.5 0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500 Input Frequency (MHz) Input Frequency (MHz) Figure40. Figure41. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4129 (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. SFDRvsINPUTFREQUENCY(CMOS) SNRvsINPUTFREQUENCY(CMOS) 90 71.0 70.5 86 70.0 Bc) 82 FS) 69.5 d B DR ( R (d 69.0 SF 78 SN 68.5 68.0 74 67.5 70 67.0 0 50 100 150 200 250 300 350 0 50 100 150 200 250 300 350 Input Frequency (MHz) Input Frequency (MHz) Figure42. Figure43. SFDRACROSSGAINANDINPUTFREQUENCY SINADACROSSGAINANDINPUTFREQUENCY 90 71 150MHz 170MHz 70 86 150MHz 69 R (dBc) 8728 220MHz D (dBFS) 6687 220MHz 170MHz SFD 74 300MHz SINA 66 300MHz 400MHz 65 70 400MHz 64 500MHz 500MHz 66 63 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Gain (dB) Gain (dB) Figure44. Figure45. PERFORMANCEACROSSINPUTAMPLITUDE(Single PERFORMANCEACROSSINPUTAMPLITUDE(Single Tone) Tone) 105 72.0 105 74 SFDR (dBFS) SFDR (dBFS) 95 71.5 95 73 S) 85 71.0 S) 85 72 F SNR (dBFS) F B S B S FDR (dBc, d 7655 7700..50 NR (dBFS) FDR (dBc, d 7655 SFDR (dBc) 7710 NR (dBFS) S 55 69.5 S 55 69 SFDR (dBc) SNR (dBFS) 45 69.0 45 68 Input Frequency = 40.1MHz Input Frequency = 170.1MHz 35 68.5 35 67 -50 -40 -30 -20 -10 0 -50 -40 -30 -20 -10 0 Input Amplitude (dBFS) Input Amplitude (dBFS) Figure46. Figure47. 40 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 TYPICAL CHARACTERISTICS: ADS4129 (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. PERFORMANCEvsINPUTCOMMON-MODEVOLTAGE SFDRACROSSTEMPERATUREvsAVDDSUPPLY 94 72.0 87 Input Frequency = 40MHz AVDD = 1.8V 92 71.5 86 90 71.0 85 dBc) 88 SNR 70.5 SNR dBc) 84 AVDD = 1.9V R ( 86 70.0 (d R ( AVDD = 1.85V FD BF FD 83 S 84 69.5 S) S AVDD = 1.75V SFDR 82 82 69.0 80 68.5 81 f = 40MHz AVDD = 1.7V IN 78 68.0 80 0.80 0.85 0.90 0.95 1.00 1.05 1.10 -40 -15 10 35 60 85 Input Common-Mode Voltage (V) Temperature (°C) Figure48. Figure49. SNRACROSSTEMPERATUREvsAVDDSUPPLY PERFORMANCEACROSSDRVDDSUPPLYVOLTAGE 72.0 88 72.0 f = 40MHz IN 71.5 87 71.5 71.0 SFDR 86 71.0 FS) 70.5 Bc) SNR SN B d R R (d 70.0 DR ( 85 70.5 (dB N F F S 69.5 AVDD = 1.7V S 84 70.0 S) AVDD = 1.75V 69.0 AVDD = 1.8V 83 69.5 68.5 AVDD = 1.85V AVDD = 1.9V fIN= 40MHz 68.0 82 69.0 -40 -15 10 35 60 85 1.70 1.75 1.80 1.85 1.90 Temperature (°C) DRVDD Supply (V) Figure50. Figure51. PERFORMANCEACROSSDRVDDSUPPLYVOLTAGE (CMOS) PERFORMANCEACROSSINPUTCLOCKAMPLITUDE 88 72.0 90 74 88 73 SFDR (dBc) 87 71.5 SFDR 86 72 84 71 86 71.0 Bc) SN Bc) 82 70 SN d R d R R ( 85 70.5 (d R ( 80 69 (d D B D B SF 84 SNR 70.0 FS) SF 78 SNR (dBFS) 68 FS) 76 67 74 66 83 69.5 72 65 Input Frequency = 170MHz 82 69.0 70 64 1.70 1.75 1.80 1.85 1.90 0.15 0.37 0.75 1.00 1.25 1.60 1.90 2.20 2.40 2.60 DRVDD Supply (V) Differential Clock Amplitude (V ) PP Figure52. Figure53. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4129 (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. PERFORMANCEACROSSINPUTCLOCKDUTYCYCLE INTEGRALNONLINEARITY 86 73.0 0.3 85 72.5 0.2 84 72.0 0.1 HD (dBc) 8832 THD 7711..50 SNR (dBF NL (LSB) 0 T 81 70.5 S I ) -0.1 SNR 80 70.0 -0.2 79 69.5 Input Frequency = 10MHz 78 69.0 -0.3 25 30 35 40 45 50 55 60 65 70 75 0 500 1000 1500 2000 2500 3000 3500 4000 Input Clock Duty Cycle (%) Output Code (LSB) Figure54. Figure55. DIFFERENTIALNONLINEARITY 0.3 0.2 0.1 B) S L (L 0 N D -0.1 -0.2 -0.3 0 500 1000 1500 2000 2500 3000 3500 4000 Output Code (LSB) Figure56. 42 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 TYPICAL CHARACTERISTICS: ADS4146 At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. FFTFOR10MHzINPUTSIGNAL FFTFOR170MHzINPUTSIGNAL 0 0 SFDR = 94dBc SFDR = 82.5dBc -10 -10 SNR = 72.25dBFS SNR = 70.8dBFS -20 SINAD = 72.20dBFS -20 SINAD = 70.4dBFS -30 THD = 91.29dBc -30 THD = 80.6dBc B) -40 B) -40 e (d -50 e (d -50 ud -60 ud -60 plit -70 plit -70 m m A -80 A -80 -90 -90 -100 -100 -110 -110 -120 -120 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80 Frequency (MHz) Frequency (MHz) Figure57. Figure58. FFTFOR300MHzINPUTSIGNAL FFTFORTWO-TONEINPUTSIGNAL 0 0 --1200 SISNSNAFRDD R== =66 877..848.dd1BBdFFBSSc ---123000 -7dBfFIENS1a c=Ah m1 T8po5lniMtueHd aezt -30 THD = 75.2dBc -40 fIN2= 190MHz B) -40 B) -50 Two-Tone IMD = 89.5dBFS e (d -50 e (d -60 SFDR = 95dBFS ud -60 ud -70 plit -70 plit -80 Am -80 Am -90 -100 -90 -110 -100 -120 -110 -130 -120 -140 0 10 20 30 40 50 60 70 80 0 25 50 75 100 125 Frequency (MHz) Frequency (MHz) Figure59. Figure60. SFDRvsINPUTFREQUENCY SNRvsINPUTFREQUENCY 95 74 -2dBFS Input, 0dB Gain 73 90 -2dBFSInput, 0dB Gain -1dBFSInput, 1dB Gain 72 85 71 c) S) dB 80 BF 70 DR ( 75 R (d 69 -1dBFSInput, 1dB Gain F N S S 68 70 67 65 66 60 65 0 50 100 150 200 250 300 350 400 450 500 0 100 200 300 400 500 600 Input Frequency (MHz) Input Frequency (MHz) Figure61. Figure62. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4146 (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. SFDRvsINPUTFREQUENCY(CMOS) SNRvsINPUTFREQUENCY(CMOS) 90 74 88 86 73 84 72 c) 82 S) B F d 80 B DR ( 78 R (d 71 F N S 76 S 70 74 72 69 70 68 68 0 50 100 150 200 250 300 350 0 50 100 150 200 250 300 350 Input Frequency (MHz) Input Frequency (MHz) Figure63. Figure64. SFDRACROSSGAINANDINPUTFREQUENCY SINADACROSSGAINANDINPUTFREQUENCY 88 73 170MHz 150MHz 170MHz 84 71 220MHz 150MHz R (dBc) 8706 300MHz 220MHz D (dBFS) 6697 300MHz D A F N 400MHz S 72 SI 65 400MHz 68 63 500MHz 500MHz 64 61 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Gain (dB) Gain (dB) Figure65. Figure66. PERFORMANCEACROSSINPUTAMPLITUDE(Single PERFORMANCEACROSSINPUTAMPLITUDE(Single Tone) Tone) 100 76 105 76 SFDR (dBFS) SFDR (dBFS) 90 75 95 75 80 74 85 74 S) S) F F B 70 73 S B 75 73 S d N d N FDR (dBc, 6500 SNR (dBFS) 7721 R (dBFS) FDR (dBc, 6555 SFDR (dBc) SNR (dBFS) 7721 R (dBFS) S S 40 70 45 70 SFDR (dBc) 30 69 35 69 Input Frequency = 40.1MHz Input Frequency = 170.1MHz 20 68 25 68 -60 -50 -40 -30 -20 -10 0 -60 -50 -40 -30 -20 -10 0 Input Amplitude (dBFS) Input Amplitude (dBFS) Figure67. Figure68. 44 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 TYPICAL CHARACTERISTICS: ADS4146 (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. PERFORMANCEvsINPUTCOMMON-MODEVOLTAGE SFDRACROSSTEMPERATUREvsAVDDSUPPLY 90 75.5 88 Input Frequency = 40MHz 88 75.0 87 AVDD = 1.85V AVDD = 1.8V 86 74.5 86 SFDR AVDD = 1.9V Bc) 84 74.0 SN Bc) 85 d R d R ( 82 73.5 (d R ( 84 D B D F F F S 80 73.0 S S 83 SNR ) AVDD = 1.75V AVDD = 1.7V 78 72.5 82 76 72.0 81 f = 40MHz IN 74 71.5 80 0.80 0.85 0.90 0.95 1.00 1.05 1.10 -40 -15 10 35 60 85 Input Common-Mode Voltage (V) Temperature (°C) Figure69. Figure70. SNRACROSSTEMPERATUREvsAVDDSUPPLY PERFORMANCEACROSSDRVDDSUPPLYVOLTAGE 75.0 88 75.5 74.5 87 75.0 AVDD = 1.8V 74.0 SFDR AVDD = 1.75V, 1.85V 86 74.5 FS) 73.5 Bc) SN B d R NR (d 73.0 AVDD = 1.7V AVDD = 1.9V FDR ( 85 SNR 74.0 (dBF S 72.5 S 84 73.5 S) 72.0 83 73.0 71.5 fIN= 40MHz fIN= 40MHz 71.0 82 72.5 -40 -15 10 35 60 85 1.70 1.75 1.80 1.85 1.90 Temperature (°C) DRVDD Supply (V) Figure71. Figure72. PERFORMANCEACROSSDRVDDSUPPLYVOLTAGE (CMOS) PERFORMANCEACROSSINPUTCLOCKAMPLITUDE 89 75.0 90 78 86 76 88 74.5 SFDR (dBc) SFDR 82 74 87 74.0 78 72 Bc) SN Bc) SN d R d 74 70 R R ( 86 73.5 (d R ( (d D B D 70 68 B SF FS SF SNR (dBFS) FS 85 73.0 ) 66 66 ) SNR 62 64 84 72.5 58 62 Input Frequency = 170MHz 83 72.0 54 60 1.70 1.75 1.80 1.85 1.90 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 DRVDD Supply (V) Differential Clock Amplitude (V ) PP Figure73. Figure74. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4146 (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. PERFORMANCEACROSSINPUTCLOCKDUTYCYCLE INTEGRALNONLINEARITY 88 75.0 1.0 87 74.5 0.8 0.6 86 74.0 0.4 THD (dBc) 888543 SNR 777332...505 SNR (dBFS INL (LSB) -00..202 ) THD -0.4 82 72.0 -0.6 81 71.5 -0.8 Input Frequency = 10MHz 80 71.0 -1.0 25 30 35 40 45 50 55 60 65 70 75 0 2k 4k 6k 8k 10k 12k 14k 16k Input Clock Duty Cycle (%) Output Code (LSB) Figure75. Figure76. DIFFERENTIALNONLINEARITY OUTPUTHISTOGRAMWITHINPUTSSHORTED 0.5 36 RMS = 1.137LSB 0.4 32 31.1 0.3 28 27.5 %) 0.2 e ( 24 23.1 B) 0.1 nc S e 20 DNL (L --00..012 ode Occurr 1162 12.2 C -0.3 8 4.8 -0.4 4 0.3 1.0 -0.5 0 0 2k 4k 6k 8k 10k 12k 14k 16k 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 Output Code (LSB) 82 82 82 82 82 82 82 82 82 82 82 82 82 82 82 Output Code (LSB) Figure77. Figure78. 46 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 TYPICAL CHARACTERISTICS: ADS4149 At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. FFTFOR10MHzINPUTSIGNAL FFTFOR170MHzINPUTSIGNAL 0 0 SFDR = 88.3dBc SFDR = 87.2dBc SNR = 72.4dBFS SNR = 71.3dBFS -20 SINAD = 72.2dBFS -20 SINAD = 71.2dBFS THD = 84dBc THD = 84.7dBc B) -40 B) -40 d d e ( e ( ud -60 ud -60 plit plit m m A -80 A -80 -100 -100 -120 -120 0 25 50 75 100 125 0 25 50 75 100 125 Frequency (MHz) Frequency (MHz) Figure79. Figure80. FFTFOR300MHzINPUTSIGNAL FFTFORTWO-TONEINPUTSIGNAL 0 0 --1200 SISNSNAFRDD R== =66 887..883.dd9BBdFFBSSc ---123000 -7dBfFIENS1a c=Ah m1 T8po5lniMtueHd aezt -30 THD = 76.6dBc -40 fIN2= 190MHz B) -40 B) -50 Two-Tone IMD = 89.5dBFS e (d -50 e (d -60 SFDR = 95dBFS ud -60 ud -70 plit -70 plit -80 Am -80 Am -90 -100 -90 -110 -100 -120 -110 -130 -120 -140 0 25 50 75 100 125 0 25 50 75 100 125 Frequency (MHz) Frequency (MHz) Figure81. Figure82. SFDRvsINPUTFREQUENCY SNRvsINPUTFREQUENCY 90 74 73 86 72 82 -2dBFS Input, 0dB Gain c) S) 71 B F d B DR ( 78 R (d 70 F N S S 69 74 -1dBFS Input, 1dB Gain 68 70 -1dBFS Input, 1dB Gain 67 -2dBFS Input, 0dB Gain 66 66 0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500 Input Frequency (MHz) Input Frequency (MHz) Figure83. Figure84. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4149 (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. SFDRvsINPUTFREQUENCY(CMOS) SNRvsINPUTFREQUENCY(CMOS) 90 74 73 86 72 Bc) 82 FS) 71 d B DR ( R (d 70 F 78 N S S 69 74 68 70 67 0 50 100 150 200 250 300 350 0 50 100 150 200 250 300 350 Input Frequency (MHz) Input Frequency (MHz) Figure85. Figure86. SFDRACROSSGAINANDINPUTFREQUENCY SINADACROSSGAINANDINPUTFREQUENCY 90 73 170MHz 150MHz 150MHz 72 86 170MHz 71 70 DR (dBc) 8728 300MHz 220MHz AD (dBFS) 6698 300MHz 220MHz F N 67 S 74 SI 66 400MHz 400MHz 65 70 500MHz 64 500MHz 66 63 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Gain (dB) Gain (dB) Figure87. Figure88. PERFORMANCEACROSSINPUTAMPLITUDE(Single PERFORMANCEACROSSINPUTAMPLITUDE(Single Tone) Tone) 100 76 100 76 SFDR (dBFS) 90 75 90 75 SFDR (dBFS) 80 74 80 74 S) S) F F B 70 73 S B 70 73 S d N d N FDR (dBc, 6500 SFDR (dBc) SNR (dBFS) 7721 R (dBFS) FDR (dBc, 6500 SNR (dBFS)SFDR (dBc) 7721 R (dBFS) S S 40 70 40 70 30 69 30 69 Input Frequency = 40.1MHz Input Frequency = 170.1MHz 20 68 20 68 -60 -50 -40 -30 -20 -10 0 -60 -50 -40 -30 -20 -10 0 Input Amplitude (dBFS) Input Amplitude (dBFS) Figure89. Figure90. 48 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 TYPICAL CHARACTERISTICS: ADS4149 (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. PERFORMANCEvsINPUTCOMMON-MODEVOLTAGE SFDRACROSSTEMPERATUREvsAVDDSUPPLY 92 75.0 88 Input Frequency = 40MHz AVDD = 1.8V 90 74.5 87 AVDD = 1.9V 88 74.0 86 SFDR Bc) 86 73.5 SN Bc) 85 d R d AVDD = 1.75V R ( 84 73.0 (d R ( 84 D B D AVDD = 1.85V F F F S 82 72.5 S S 83 ) SNR 80 72.0 82 AVDD = 1.7V 78 71.5 81 f = 40MHz IN 76 71.0 80 0.80 0.85 0.90 0.95 1.00 1.05 1.10 -40 -15 10 35 60 85 Input Common-Mode Voltage (V) Temperature (°C) Figure91. Figure92. SNRACROSSTEMPERATUREvsAVDDSUPPLY PERFORMANCEACROSSDRVDDSUPPLYVOLTAGE 74.0 89 75.0 73.5 88 74.5 AVDD = 1.85V 73.0 87 74.0 FS) AVDD = 1.8V, 1.9V Bc) SFDR SN B d R SNR (d 7722..50 AVDD = 1.75V AVDD = 1.7V SFDR ( 8865 SNR 7733..50 (dBFS) 71.5 84 72.5 fIN= 40MHz fIN= 40MHz 71.0 83 72.0 -40 -15 10 35 60 85 1.70 1.75 1.80 1.85 1.90 Temperature (°C) DRVDD Supply (V) Figure93. Figure94. PERFORMANCEACROSSDRVDDSUPPLYVOLTAGE (CMOS) PERFORMANCEACROSSINPUTCLOCKAMPLITUDE 89 75.0 90 74 88 73 SFDR (dBc) 88 74.5 86 72 SFDR 84 71 87 74.0 Bc) SN Bc) 82 70 SN d R d SNR (dBFS) R R ( 86 73.5 (d R ( 80 69 (d D B D B SF 85 73.0 FS) SF 78 68 FS) 76 67 SNR 74 66 84 72.5 72 65 Input Frequency = 170MHz 83 72.0 70 64 1.70 1.75 1.80 1.85 1.90 0.15 0.37 0.75 1.00 1.25 1.60 1.90 2.20 2.40 2.60 DRVDD Supply (V) Differential Clock Amplitude (V ) PP Figure95. Figure96. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 49 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4149 (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. PERFORMANCEACROSSINPUTCLOCKDUTYCYCLE INTEGRALNONLINEARITY 88 74.0 1.5 87 73.5 1.0 86 73.0 SNR 0.5 HD (dBc) 8854 THD 7722..50 SNR (dBF NL (LSB) 0 T 83 71.5 S I ) -0.5 82 71.0 -1.0 81 70.5 Input Frequency = 10MHz 80 70.0 -1.5 25 30 35 40 45 50 55 60 65 70 75 0 2k 4k 6k 8k 10k 12k 14k 16k Input Clock Duty Cycle (%) Output Code (LSB) Figure97. Figure98. DIFFERENTIALNONLINEARITY OUTPUTHISTOGRAMWITHINPUTSSHORTED 0.5 44 RMS = 0.999LSB 39.7 0.4 40 35.7 0.3 36 %) 32 B) 00..21 nce ( 28 DNL (LS --00..012 Code Occurre 22114062 12.6 -0.3 8 6.0 3.8 -0.4 4 0.2 1.4 0.7 -0.5 0 0 2k 4k 6k 8k 10k 12k 14k 16k 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 Output Code (LSB) 82 82 82 82 82 82 82 82 82 82 82 82 82 82 82 82 Output Code (LSB) Figure99. Figure100. 50 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 TYPICAL CHARACTERISTICS: COMMON At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. CMRRACROSSFREQUENCY CMRRSPECTRUM -20 0 -25 I5n0pmuVt FPrPeSqiugennacl yS =u p7e0rMimHpzosed -20 ffICNM== 7 100MMHHzz, 100mVPP fIN= 70MHz on Input Common-Mode Voltage SFDR = 81dBc -30 (0.95V) -40 AAmmpplliittuuddee ((ffIN) )= =--17d4BdFBSFS CMRR (dB) ---344505 Amplitude (dB) --6800 AAmmppfllCiittuuMdd=ee 1((ff0CIINNMM-+H ffzCCMM)) ==--8867ddBBFFSS fIN-fINfC+M f=C M60=M 8H0MzHz -100 -50 -55 -120 -60 -140 0 50 100 150 200 250 300 0 25 50 75 100 125 Frequency of Input Common-Mode Signal (MHz) Frequency (MHz) Figure101. Figure102. PSRRACROSSFREQUENCY ZOOMEDVIEWOFSPECTRUMWITHPSRRSIGNAL -20 0 Input Frequency = 10MHz fIN fIN= 10MHz -25 50mVPPSignal Applied on AVDD -20 Amplitude (ffPS)R =R-=1 1dMBFHSz IN Amplitude (f ) =-81dBFS -30 -40 Amplitude (f + f PSR)R =-67.7dBFS SRR (dB) --3450 plitude (dB) --6800 fIN-fPSRR fIN+ fPSARRmplitude (fIINN-fPPSSRRRR) =-68.8dBFS P PSRR (dB) on AVDD Supply Am fPSRR -45 -100 -50 -120 -55 -140 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 40 45 50 Frequency of Signal on AVDD (MHz) Frequency (MHz) Figure103. Figure104. POWERACROSSSAMPLINGFREQUENCY DRVDDCURRENTACROSSSAMPLINGFREQUENCY 200 70 180 AVDD Power (mW) 60 160 LVDS, 350mV Swing 140 mA) 50 W) 120 nt ( LVDS, 200mV Swing m e 40 er ( 100 Curr Pow 80 DD 30 DRVDD Power V 60 R 20 200mVLVDS D 40 CMOS, 8pF Load Capacitor DRVDDPower 10 20 350mVLVDS CMOS, 6pF Load Capacitor 0 0 0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250 Sampling Frequency (MSPS) Sampling Frequency (MSPS) Figure105. Figure106. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 51 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com TYPICAL CHARACTERISTICS: CONTOUR At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. SFDRACROSSINPUTANDSAMPLINGFREQUENCIES(1dBGain) AppliestoADS412xandADS414x 250 88 82 84 78 240 86 220 84 82 PS 84 82 84 74 70 S 200 86 M -cy 180 86 84 84 66 n 78 e u q 160 88 e 82 Fr 82 70 g 74 n 140 88 86 pli 78 m 84 a 120 S 74 - 66 fS 100 88 84 70 88 82 80 88 74 70 78 62 86 66 65 10 50 100 150 200 250 300 350 400 450 500 f -InputFrequency-MHz IN 60 65 70 75 80 85 90 SFDR-dBFS Figure107. 52 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 TYPICAL CHARACTERISTICS: CONTOUR (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. SFDRACROSSINPUTANDSAMPLINGFREQUENCIES(6dBGain) AppliestoADS412xandADS414x 250 240 86 84 82 72 86 80 76 220 84 84 PS 68 MS 200 82 84 - 72 cy 180 82 82 en 80 76 u 86 84 q 160 88 84 e Fr g n 140 mpli 86 86 86 82 80 76 a 120 S 72 88 - 72 fS 100 88 84 88 80 76 86 80 64 84 82 72 65 10 50 100 150 200 250 300 350 400 450 500 f -InputFrequency-MHz IN 60 65 70 75 80 85 90 SFDR-dBFS Figure108. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 53 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com TYPICAL CHARACTERISTICS: CONTOUR (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. ADS412xSNRACROSSINPUTANDSAMPLINGFREQUENCIES (1dBGain) 250 240 69.5 68.5 67 69 220 S P S 200 M 68 - ency 180 69.5 68.5 66 u eq 160 70 69 67 Fr g n 140 pli m a 120 68 S 68.5 - 66 S f 100 69.5 70 69 67 80 68.5 68 67 66 65 64 65 10 50 100 150 200 250 300 350 400 450 500 f -InputFrequency-MHz IN 62 63 64 65 66 67 68 69 70 71 SNR-dBFS Figure109. 54 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 TYPICAL CHARACTERISTICS: CONTOUR (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. ADS412xSNRACROSSINPUTANDSAMPLINGFREQUENCIES (6dBGain) 250 240 66 65 65.5 64.5 220 S P S 200 M - cy 180 n 66.5 66 65.5 e u 65 q 160 e Fr 64.5 g 66 n 140 pli 67 66.5 m a 120 S - 65.5 S f 100 65 66 64 80 65.5 64.5 67 66 65 63.563 65 10 50 100 150 200 250 300 350 400 450 500 f -InputFrequency-MHz IN 62 63 64 65 66 67 68 SNR-dBFS Figure110. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 55 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com TYPICAL CHARACTERISTICS: CONTOUR (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. ADS414x:SNRACROSSINPUTANDSAMPLINGFREQUENCIES (1dBGain) 250 68 240 71 69 70 220 71.5 S SP 200 70.5 67 M - cy 180 n ue 71 70 68 eq 160 72 71.5 69 Fr g n 140 70.5 pli 67 m a 120 70 S - 66 fS 100 68 71 69 71.5 72 80 72.5 70 67 70.5 68 66 65 64 65 10 50 100 150 200 250 300 350 400 450 500 f -InputFrequency-MHz IN 63 64 65 66 67 68 69 70 71 72 73 SNR-dBFS Figure111. 56 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 TYPICAL CHARACTERISTICS: CONTOUR (continued) At+25°C,AVDD=1.8V,DRVDD=1.8V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V differentialclock PP amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain,low-latencymode,DDRLVDSoutputinterface, and32k-pointFFT,unlessotherwisenoted.Notethatafterreset,thedeviceisin0dBgainmode. ADS414x:SNRACROSSINPUTANDSAMPLINGFREQUENCIES (6dBGain) 250 240 67 66 65 66.5 65.5 220 S P S 200 M - ency 180 67 66.5 66 65 u eq 160 67.5 65.5 g Fr 67 n 140 pli m 66.5 a 120 S - S 66.5 65 f 100 66 67.5 65.5 80 67 66 65.5 65 64.5 64 63.5 65 10 50 100 150 200 250 300 350 400 450 500 f -InputFrequency-MHz IN 62 63 64 65 66 67 68 SNR-dBFS Figure112. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 57 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The ADS412x/4x is a family of high-performance and low-power 12-bit and 14-bit ADCs with maximum sampling rates up to 250MSPS. The conversion process is initiated by a rising edge of the external input clock and the analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline, resulting in a data latency of 10 clock cycles. The output is available as 14-bit data or 12-bit data, in DDR LVDS mode or CMOS mode, and coded in either straight offset binary or binary twos complement format. ANALOG INPUT The analog input consists of a switched-capacitor-based, differential, sample-and-hold architecture. This differential topology results in very good ac performance even for high input frequencies at high sampling rates. The INP and INM pins must be externally biased around a common-mode voltage of 0.95V, available on the VCM pin. For a full-scale differential input, each input INP and INM pin must swing symmetrically between (VCM + 0.5V) and (VCM – 0.5V), resulting in a 2V differential input swing. The input sampling circuit has a high 3dB PP bandwidth that extends up to 550MHz (measured from the input pins to the sampled voltage). Figure 113 shows anequivalentcircuitfortheanaloginput. Sampling Switch L PKG 2nH Sampling 10W RCR Filter Capacitor INP CB1OpNFD 100W C1pPFAR2 1R5OWN CSAMP 2pF R 20E0SWR 3pF CPAR1 RON 3pF 0.5pF 15W L PKG C 2nH 100W RON 2SpAFMP 15W INM CBOND CPAR2 Sampling 1pF 1pF Capacitor R ESR 200W Sampling Switch Figure113. AnalogInputEquivalentCircuit DriveCircuitRequirements For optimum performance, the analog inputs must be driven differentially. This technique improves the common-mode noise immunity and even-order harmonic rejection. A 5Ω to 15Ω resistor in series with each input pin is recommended to damp out ringing caused by package parasitics. It is also necessary to present low impedance (less than 50Ω) for the common-mode switching currents. This impedance can be achieved by using tworesistorsfromeachinputterminatedtothecommon-modevoltage(VCM). Note that the device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the glitches caused by the opening and closing of the sampling capacitors. The cutoff frequency of the R-C filter involves a trade-off. A lower cutoff frequency (larger C) absorbs glitches better, but also reduces the input bandwidth and the maximum input frequency that can be supported. On the other hand, with no internal R-C filter, high input frequency can be supported but now the sampling glitches must be supplied by the external driving circuit. The inductance of the package bond wires limits the ability of the external driving circuit to support thesamplingglitches. 58 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 In the ADS412x/4x, the R-C component values have been optimized while supporting high input bandwidth (550MHz). However, in applications where very high input frequency support is not required, filtering of the glitchescanbeimprovedfurtherwithanexternalR-C-Rfilter;seeFigure116andFigure117). In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. While designing the drive circuit, the ADC impedance must be considered.Figure114andFigure115showtheimpedance(Z =R ||C )lookingintotheADCinputpins. IN IN IN 100.00 W) k ce ( 10.00 n a st si e R ut 1.00 p n al I enti 0.10 er Diff 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Input Frequency (GHz) Figure114. ADCAnalogInputResistance(R )AcrossFrequency IN 5.0 pF) 4.5 e ( nc 4.0 a acit 3.5 p a ut C 3.0 p al In 2.5 nti 2.0 e er Diff 1.5 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Input Frequency (GHz) Figure115. ADCAnalogInputCapacitance(C )AcrossFrequency IN Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 59 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com DrivingCircuit Two example driving circuit configurations are shown in Figure 116 and Figure 117—one optimized for low bandwidth and the other one for high bandwidth to support higher input frequencies. In Figure 116, an external R-C-R filter with 3.3pF is used to help absorb sampling glitches. The R-C-R filter limits the bandwidth of the drive circuit,makingitsuitableforlowinputfrequencies(upto250MHz).TransformerssuchasADT1-1WTorWBC1-1 canbeusedupto250MHz. For higher input frequencies, the R-C-R filter can be dropped. Together with the lower series resistors (5Ω to 10Ω), this drive circuit provides higher bandwidth to support frequencies up to 500MHz (as shown in Figure 117). AtransmissionlinetransformersuchasADTL2-18canbeused. Note that both the drive circuits have been terminated by 50Ω near the ADC side. The termination is accomplished by a 25Ω resistor from each input to the 0.95V common-mode (VCM) from the device. This terminationallowstheanaloginputstobebiasedaroundtherequiredcommon-modevoltage. 3.6nH 10Wto 15W INP T2 T1 0.1mF 0.1mF 25W 50W 3.3pF RIN CIN 25W 50W INM 1:1 1:1 10Wto 15W 3.6nH VCM ADS41xx Figure116. DriveCircuitwithLowBandwidth(forLowInputFrequencies) 5Wto 10W INP T2 T1 0.1mF 25W 0.1mF R C IN IN 25W INM 1:1 1:1 5Wto 10W VCM ADS41xx Figure117. DriveCircuitwithHighBandwidth(forHighInputFrequencies) 60 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonicperformance.ConnectingtwoidenticalRFtransformersback-to-backhelpsminimizethismismatchand good performance is obtained for high-frequency input signals. An additional termination resistor pair may be required between the two transformers, as shown in Figure 116 and Figure 117. The center point of this termination is connected to ground to improve the balance between the P (positive) and M (negative) sides. The values of the terminations between the transformers and on the secondary side must be chosen to obtain an effective50Ω (fora50Ω sourceimpedance). Figure 116 and Figure 117 use 1:1 transformers with a 50Ω source. As explained in the Drive Circuit Requirements section, this architecture helps to present a low source impedance to absorb sampling glitches. With a 1:4 transformer, the source impedance is 200Ω. The higher source impedance is unable to absorb the samplingglitcheseffectivelyandcanleadtodegradationinperformance(comparedtousing1:1transformers). In almost all cases, either a bandpass or low-pass filter is needed to get the desired dynamic performance, as shown in Figure 118. Such a filter presents low source impedance at the high frequencies corresponding to the samplingglitchandhelpsavoidtheperformancelosswiththehighsourceimpedance. 10W INP 100W Bandpass or 0.1mF Differential Low-Pass Input Signal Filter ADS41xx 100W INM 10W VCM Figure118. DriveCircuitwith1:4Transformer InputCommon-Mode To ensure a low-noise, common-mode reference, the VCM pin is filtered with a 0.1µF low-inductance capacitor connected to ground. The VCM pin is designed to directly drive the ADC inputs. Each ADC input pin sinks a common-modecurrentofapproximately0.6µAperMSPSofclockfrequency. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 61 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com CLOCK INPUT The ADS412x/4x clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or ac-coupling for LVPECL and LVDS clock sources. Figure 119 shows an equivalent circuit for the input clock. ClockBuff er L PKG 1nH 20W CLKP C B1OpNFD 5kW CEQ CEQ R ESR 100W 2pF VCM L PKG 1nH 5kW 20W CLKM C BOND 1pF R ESR 100W NOTE:C is1pFto3pFandistheequivalentinputcapacitanceoftheclockbuffer. EQ Figure119. InputClockEquivalentCircuit A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1mF capacitor, as shown in Figure 120. For best performance, the clock inputs must be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no changeinperformancewithanon-50%dutycycleclockinput.Figure121showsadifferentialcircuit. 0.1mF CMOS CLKP 0.1mF Clock Input CLKP Differential Sine-Wave, PECL, or LVDS VCM 0.1mF Clock Input CLKM 0.1mF CLKM Figure120. Single-EndedClockDrivingCircuit Figure121. DifferentialClockDrivingCircuit 62 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 DIGITAL FUNCTIONS AND LOW LATENCY MODE The device has several useful digital functions such as test patterns, gain, and offset correction. All of these functions require extra clock cycles for operation and increase the overall latency and power of the device. Alternately,thedevicehasalow-latencymodeinwhichtherawADCoutputisroutedtotheoutputdatapinswith a latency of 10 clock cycles. In this mode, the digital functions are bypassed. Figure 122 shows more details of theprocessingaftertheADC. The device is in low-latency mode after reset. In order to use any of the digital functions, first the low-latency modemustbedisabledbysettingtheDISLOWLATENCYregisterbitto'1'.Afterthis,therespectiveregisterbits mustbeprogrammedasdescribedinthefollowingsectionsandintheSerialRegisterMapsection. Output Interface 14-Bit ADC 14b 14b Digital Functions (Gain, Offset Correction, Test Patterns) DDR LVDS or CMOS DIS LOW LATENCY Pin Figure122. DigitalProcessingBlockDiagram GAIN FOR SFDR/SNR TRADE-OFF The ADS412x/4x include gain settings that can be used to get improved SFDR performance. The gain is programmable from 0dB to 6dB (in 0.5dB steps) using the GAIN register bits. For each gain setting, the analog inputfull-scalerangescalesproportionally,asshowninTable11. The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades approximately between 0.5dB and 1dB. The SNR degradation is reduced at high input frequencies. As a result, the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal degradationinSNR.Therefore,thegaincanbeusedtotrade-offbetweenSFDRandSNR. Afterareset,thedeviceisinlow-latencymodeandgainfunctionisdisabled.Tousegain: • First,disablethelow-latencymode(DISLOWLATENCY=1). • Thissettingenablesthegainandputsthedeviceina0dBgainmode. • Forothergainsettings,programtheGAINbits. Table11.Full-ScaleRangeAcrossGains GAIN(dB) TYPE FULL-SCALE(V ) PP 0 Defaultafterreset 2 1 Programmablegain 1.78 2 Programmablegain 1.59 3 Programmablegain 1.42 4 Programmablegain 1.26 5 Programmablegain 1.12 6 Programmablegain 1.00 Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 63 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com OFFSET CORRECTION The ADS412x/4x has an internal offset corretion algorithm that estimates and corrects dc offset up to ±10mV. The correction can be enabled using the EN OFFSET CORR serial register bit. Once enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loopisafunctionofthesamplingclockfrequency.ThetimeconstantcanbecontrolledusingtheOFFSETCORR TIMECONSTANTregisterbits,asdescribedinTable12. Table12.TimeConstantofOffsetCorrectionLoop TIMECONSTANT,TC CLK OFFSETCORRTIMECONSTANT (NumberofClockCycles) TIMECONSTANT,TC ×1/f (sec)(1) CLK S 0000 1M 4ms 0001 2M 8ms 0010 4M 16.7ms 0011 8M 33.5ms 0100 16M 67ms 0101 32M 134ms 0110 64M 268ms 0111 128M 537ms 1000 256M 1.1s 1001 512M 2.15s 1010 1G 4.3s 1011 2G 8.6s 1100 Reserved — 1101 Reserved — 1110 Reserved — 1111 Reserved — (1) Samplingfrequency,f =250MSPS. S After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. Once frozen, the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is disabledbyadefaultafterreset. Afterareset,thedeviceisinlow-latencymodeandoffsetcorrectionisdisabled.Touseoffsetcorrection: • First,disablethelow-latencymode(DISLOWLATENCY=1). • ThensetENOFFSETCORRto'1'andprogramtherequiredtimeconstant. Figure123showsthetimeresponseoftheoffsetcorrectionalgorithmafteritisenabled. OFFSET CORRECTION Time Response 8200 8190 8181 8180 Offset of 8192 8170 10 LSBs Final converged value B) 8160 Ocoffnsveet rcgoersr etoct ioountput de (LS 888111543000 Obeffgsients correction code of 8192 o C 8120 ut 8110 p ut 8100 O 8090 8080 8070 8060 8050 -5 5 15 25 35 45 55 65 75 85 95 105 Time (ms) Figure123. TimeResponseofOffsetCorrection 64 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 POWER DOWN TheADS412x/4xhasthreepower-downmodes:power-downglobal,standby,andoutputbufferdisable. Power-DownGlobal In this mode, the entire chip (including the ADC, internal reference, and the output buffers) are powered down, resulting in reduced total power dissipation of about 10mW. The output buffers are in a high-impedance state. The wake-up time from the global power-down to data becoming valid in normal mode is typically 100µs. To entertheglobalpower-downmode,setthePDNGLOBALregisterbit. Standby In this mode, only the ADC is powered down and the internal references are active, resulting in a fast wake-up time of 5µs. The total power dissipation in standby mode is approximately 185mW. To enter the standby mode, settheSTBYregisterbit. OutputBufferDisable The output buffers can be disabled and put in a high-impedance state; wakeup time from this mode is fast, approximately100ns.ThiscanbecontrolledusingthePDNOBUFregisterbitorusingtheOEpin. InputClockStop In addition, the converter enters a low-power mode when the input clock frequency falls below 1MSPS. The powerdissipationisapproximately80mW. POWER-SUPPLY SEQUENCE During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are separatedinthedevice.Externally,theycanbedrivenfromseparatesuppliesorfromasinglesupply. DIGITAL OUTPUT INFORMATION TheADS412x/4xprovideeither14-bitdataor12-bitdata,respectively,andanoutputclocksynchronizedwiththe data. OutputInterface Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be selectedusingtheLVDSCMOSserialinterfaceregisterbitorusingtheDFSpin. DDRLVDSOutputs In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits aremultiplexedandoutputoneachLVDSdifferentialpair,asshowninFigure124andFigure125. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 65 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com Pins Pins CLKOUTP Output Clock CLKOUTP CLKOUTM Output Clock CLKOUTM D0_D1_P Data Bits D0, D1 D0_D1_P D0_D1_M Data Bits D0, D1 LVDS Buffers DD22__DD33__MP Data Bits D2, D3 LVDS Buffers DDD220___DDD331___MPM Data Bits D2, D3 D4_D5_P Data Bits D4, D5 D4_D5_P 12-Bit D4_D5_M Data Bits D4, D5 ADC Data 14-Bit D4_D5_M ADC Data D6_D7_P Data Bits D6, D7 D6_D7_P D6_D7_M Data Bits D6, D7 D6_D7_M D8_D9_P Data Bits D8, D9 D8_D9_P D8_D9_M Data Bits D8, D9 D8_D9_M D10_D11_P Data Bits D10, D11 D10_D11_P D10_D11_M Data Bits D10, D11 ADS4129 D10_D11_M D12_D13_P Figure124. ADS412xLVDSDataOutputs Data Bits D12, D13 D12_D13_M ADS4149 Figure125. ADS414xLVDSDataOutputs 66 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 Even data bits (D0, D2, D4, etc.) are output at the falling edge of CLKOUTP and the odd data bits (D1, D3, D5, etc.) are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to captureall14databits,asshowninFigure126. CLKOUTP CLKOUTM D0_D1_P, D0 D1 D0 D1 D0_D1_M D2_D3_P, D2 D3 D2 D3 D2_D3_M D4_D5_P, D4 D5 D4 D5 D4_D5_M D6_D7_P, D6 D7 D6 D7 D6_D7_M D8_D9_P, D8 D9 D8 D9 D8_D9_M D10_D11_P, D10 D11 D10 D11 D10_D11_M D12_D13_P, D12 D13 D12 D13 D12_D13_M Sample N Sample N + 1 Figure126. DDRLVDSInterface Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 67 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com LVDSOutputDataandClockBuffers The equivalent circuit of each LVDS output buffer is shown in Figure 127. After reset, the buffer presents an outputimpedanceof100Ω tomatchwiththeexternal100Ωtermination. The V voltage is nominally 350mV, resulting in an output swing of ±350mV with 100Ω external termination. DIFF TheV voltageisprogrammableusingtheLVDSSWINGregisterbitsfrom±125mVto±570mV. DIFF Additionally, a mode exists to double the strength of the LVDS buffer to support 50Ω differential termination. This mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH registerbitsfordataandoutputclockbuffers,respectively. The buffer output impedance behaves in the same way as a source-side series termination. By absorbing reflectionsfromthereceiverend,ithelpstoimprovesignalintegrity. VDIFF High Low OUTP External 100WLoad OUTM 1.1V R OUT VDIFF Low High NOTE:Usethedefaultbufferstrengthtomatch100Ωexternaltermination(R =100Ω).Tomatchwitha50Ωexternaltermination,setthe OUT LVDSSTRENGTHbit(R =50Ω). OUT Figure127. LVDSBufferEquivalentCircuit ParallelCMOSInterface In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 128 depicts the CMOS outputinterface. Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this degradation, the CMOS output buffers are designed with controlled drive strength. The default drive strength ensures a wide data stable window (even at 250MSPS) is provided so the data outputs have minimal load capacitance.Itisrecommendedtouseshorttraces(onetotwoinchesor2,54cmto5,08cm)terminatedwithless than5pFloadcapacitance,asshowninFigure129. For sampling frequencies greater than 200MSPS, it is recommended to use an external clock to capture data. The delay from input clock to output data and the data valid times are specified for higher sampling frequencies. Thesetimingscanbeusedtodelaytheinputclockappropriatelyanduseittocapturedata. 68 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 Pins OVR CLKOUT D0 s er uff D1 B ut p ut O OS D2 M C D3 14-Bit ADC Data ¼ ¼ D11 D12 D13 ADS4149 Figure128. CMOSOutputInterface Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 69 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com Use External Clock Buffer (> 200MSPS) Input Clock Receiver (FPGA, ASIC, etc.) Flip-Flops CLKOUT CLKIN D0 D0_In s er uff D1 ut B D1_In p ut O S O D2 M D2_In C 14-Bit ADC Data D12 D12_In D13 D13_In ADS4149 Use short traces between ADC output and receiver pins (1 to 2 inches). Figure129. UsingtheCMOSDataOutputs CMOSInterfacePowerDissipation With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The maximum DRVDD current occurs when each output bit toggles between '0' and '1' every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of theanaloginputsignal. DigitalCurrentasaResultofCMOSOutputSwitching=C ×DRVDD×(N×f ) L AVG where: C =loadcapacitance, L N×F =averagenumberofoutputbitsswitching. (1) AVG Figure106showsthecurrentacrosssamplingfrequenciesat2MHzanaloginputfrequency. InputOver-VoltageIndication(OVRPin) The device has an OVR pin that provides information about analog input overload. At any clock cycle, if the sampled input voltage exceeds the positive or negative full-scale range, the OVR pin goes high. The OVR remains high as long as the overload condition persists. The OVR pin is a CMOS output buffer (running off DRVDDsupply),independentofthetypeofoutputdatainterface(DDRLVDSorCMOS). 70 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 For a positive overload, the D[13:0] output data bits are 3FFFh in offset binary output format and 1FFFh in twos complement output format. For a negative input overload, the output code is 0000h in offset binary output format and2000hintwoscomplementoutputformat. OutputDataFormat Two output data formats are supported: twos complement and offset binary. They can be selected using the DATA FORMAT serial interface register bit or controlling the DFS pin in parallel configuration mode. In the event ofaninputvoltageoverdrive,thedigitaloutputsgototheappropriatefull-scalelevel. BOARD DESIGN CONSIDERATIONS Grounding A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See the ADS414x, ADS412x EVM User Guide (SLWU067) for details on layout andgrounding. SupplyDecoupling Because the ADS412x/4x already include internal decoupling, minimal external decoupling can be used without loss in performance. Note that decoupling capacitors can help filter external power-supply noise, so the optimum number of capacitors depends on the actual application. The decoupling capacitors should be placed very close totheconvertersupplypins. ExposedPad In addition to providing a path for heat dissipation, the PowerPAD is also electrically internally connected to the digital ground. Therefore, it is necessary to solder the exposed pad to the ground plane for best thermal and electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SONPCBAttachment(SLUA271),bothavailablefordownloadattheTIwebsite(www.ti.com). Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 71 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com DEFINITION OF SPECIFICATIONS AnalogBandwidth–Theanaloginputfrequencyatwhichthepowerofthefundamentalisreducedby3dBwith respecttothelow-frequencyvalue. Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay is different across channels. The maximum variation is specified as aperturedelayvariation(channel-to-channel). ApertureUncertainty(Jitter)– Thesample-to-samplevariationinaperturedelay. ClockPulseWidth/DutyCycle– Thedutycycleofaclocksignalistheratioofthetimetheclocksignalremains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage.Aperfectdifferentialsine-waveclockresultsina50%dutycycle. Maximum Conversion Rate – The maximum sampling rate at which specified operation is given. All parametric testingisperformedatthissamplingrateunlessotherwisenoted. MinimumConversionRate– TheminimumsamplingrateatwhichtheADCfunctions. Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly 1LSBapart.TheDNListhedeviationofanysinglestepfromthisidealvalue,measuredinunitsofLSBs. IntegralNonlinearity(INL)– TheINListhedeviationoftheADCtransferfunctionfromabestfitlinedetermined byaleastsquarescurvefitofthattransferfunction,measuredinunitsofLSBs. Gain Error – Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as E andE . GREF GCHAN Toafirst-orderapproximation,thetotalgainerrorisE ~E +E . TOTAL GREF GCHAN Forexample,ifE =±0.5%,thefull-scaleinputvariesfrom(1– 0.5/100)xFS to(1+0.5/100)xFS . TOTAL ideal ideal Offset Error – The offset error is the difference, given in number of LSBs, between the ADC actual average idle channeloutputcodeandtheidealaverageidlechanneloutputcode.Thisquantityisoftenmappedintomillivolts. Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the changeperdegreeCelsiusoftheparameterfromT toT .Itiscalculatedbydividingthemaximumdeviation MIN MAX oftheparameteracrosstheT toT rangebythedifferenceT –T . MIN MAX MAX MIN Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (P ) to the noise floor power (P ), S N excludingthepoweratdcandthefirstnineharmonics. P SNR=10Log10 S P N (2) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scalerange. Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (P ) to the power S ofalltheotherspectralcomponentsincludingnoise(P )anddistortion(P ),butexcludingdc. N D P SINAD=10Log10 S P +P N D (3) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scalerange. 72 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the theoreticallimitbasedonquantizationnoise. SINAD - 1.76 ENOB= 6.02 (4) Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (P ) to the power of the S firstnineharmonics(P ). D P THD=10Log10 S P N (5) THDistypicallygiveninunitsofdBc(dBtocarrier). Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other spectralcomponent(eitherspurorharmonic).SFDRistypicallygiveninunitsofdBc(dBtocarrier). Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f 1 and f ) to the power of the worst spectral component at either frequency 2f – f or 2f – f . IMD3 is either given 2 1 2 2 1 in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB tofull-scale)whenthepowerofthefundamentalisextrapolatedtotheconverterfull-scalerange. DCPower-SupplyRejectionRatio(DCPSRR)–DCPSSRistheratioofthechangeinoffseterrortoachange inanalogsupplyvoltage.ThedcPSRRistypicallygiveninunitsofmV/V. AC Power-Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the supply voltage by the ADC. If ΔV is the change in supply voltage and ΔV is the resultant change of the SUP OUT ADCoutputcode(referredtotheinput),then: DV PSRR = 20Log10 OUT (Expressed in dBc) DV SUP (6) Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and negativeoverload.Thedeviationofthefirstfewsamplesaftertheoverload(fromtheexpectedvalues)isnoted. Common-Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input common-mode by the ADC. If ΔV is the change in the common-mode voltage of the input pins and ΔV is CM_IN OUT theresultingchangeoftheADCoutputcode(referredtotheinput),then: DV CMRR = 20Log10 OUT (Expressed in dBc) DV CM (7) Crosstalk (only for multi-channel ADCs) – This is a measure of the internal coupling of a signal from an adjacent channel into the channel of interest. It is specified separately for coupling from the immediate neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacentchannelinput.ItistypicallyexpressedindBc. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 73 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com REVISION HISTORY NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionF(October2010)toRevisionG Page • Updateddocumenttocurrentstandards .............................................................................................................................. 1 • Added125MSPSand65MSPScolumnstoADS412x/ADS414xFamilyComparisontable ................................................ 1 • ChangedClockInput,Low-speedmodeenabledminimumspecificationforbothADS4129/49andADS4126/46 rowsinElectricalCharacteristicstable ................................................................................................................................. 4 • ChangedDFregisteraddressandregisterdatainTable10 ............................................................................................. 26 • ChangedDFhregisterinDescriptionofSerialRegisterssection ...................................................................................... 34 • ChangedtitlesofFigure21andFigure22 ......................................................................................................................... 36 • ChangedtitlesofFigure42andFigure43 ......................................................................................................................... 40 • ChangedtitlesofFigure63andFigure64 ......................................................................................................................... 44 • ChangedtitlesofFigure85andFigure86 ......................................................................................................................... 48 • UpdatedFigure105andFigure106................................................................................................................................... 51 • UpdatedTable11 ............................................................................................................................................................... 63 ChangesfromRevisionE(September2010)toRevisionF Page • ChangedstatusofADS4129throughoutdocument ............................................................................................................. 1 • ChangedADS4129SNR,SINAD,SFDR,THD,andHD3f =170MHztypicalspecificationsinElectrical IN Characteristicstable ............................................................................................................................................................. 5 • AddedADS4129SNR,SINAD,SFDR,THD,HD2,HD3,andWorstspurf =170MHzminimumspecificationsin IN ElectricalCharacteristicstable .............................................................................................................................................. 5 • AddedADS4129DNLminimumandmaximumspecificationsinElectricalCharacteristicstable........................................ 5 • AddedADS4129INLmaximumspecificationinElectricalCharacteristicstable.................................................................. 5 • ChangedADS4129INLtypicalspecificationinElectricalCharacteristicstable ................................................................... 5 74 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS4126IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 AZ4126 & no Sb/Br) ADS4126IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 AZ4126 & no Sb/Br) ADS4129IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 AZ4129 & no Sb/Br) ADS4129IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 AZ4129 & no Sb/Br) ADS4146IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 AZ4146 & no Sb/Br) ADS4146IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 AZ4146 & no Sb/Br) ADS4149IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 AZ4149 & no Sb/Br) ADS4149IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 AZ4149 & no Sb/Br) ADS58B18IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 AZ58B18 & no Sb/Br) ADS58B18IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 AZ58B18 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS4126IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS4126IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS4129IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS4129IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS4146IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS4146IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS4149IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS4149IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS58B18IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS58B18IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS4126IRGZR VQFN RGZ 48 2500 350.0 350.0 43.0 ADS4126IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 ADS4129IRGZR VQFN RGZ 48 2500 350.0 350.0 43.0 ADS4129IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 ADS4146IRGZR VQFN RGZ 48 2500 350.0 350.0 43.0 ADS4146IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 ADS4149IRGZR VQFN RGZ 48 2500 350.0 350.0 43.0 ADS4149IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 ADS58B18IRGZR VQFN RGZ 48 2500 350.0 350.0 43.0 ADS58B18IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 PackMaterials-Page2

GENERIC PACKAGE VIEW RGZ 48 VQFN - 1 mm max height 7 x 7, 0.5 mm pitch PLASTIC QUADFLAT PACK- NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224671/A www.ti.com

PACKAGE OUTLINE RGZ0048D VQFN - 1 mm max height SCALE 1.900 PLASTIC QUAD FLATPACK - NO LEAD B 7.1 A 6.9 0.5 0.3 PIN 1 INDEX AREA 7.1 6.9 0.30 0.18 DETAIL OPTIONAL TERMINAL TYPICAL 1.0 0.8 C SEATING PLANE 0.05 0.00 0.08 C 5.6 0.1 2X 5.5 (0.2) TYP 13 24 44X 0.5 12 25 EXPOSED THERMAL PAD 2X 49 SYMM 5.5 SEE TERMINAL DETAIL 1 36 0.30 48X 48 37 0.18 PIN 1 ID SYMM 0.1 C A B (OPTIONAL) 0.5 48X 0.05 0.3 4219046/B 11/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGZ0048D VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 5.6) SYMM 48 37 48X (0.6) 1 36 48X (0.24) 6X (1.22) 44X (0.5) 10X (1.33) 49 SYMM (6.8) (R0.05) TYP ( 0.2) TYP VIA 12 25 13 24 10X (1.33) 6X (1.22) (6.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL OPENING EXPOSED METAL EXPOSED METAL SOLDER MASK METAL UNDER OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4219046/B 11/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGZ0048D VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD (0.665 TYP) (1.33) TYP 16X ( 1.13) 48 37 48X (0.6) 49 1 36 48X (0.24) 44X (0.5) (1.33) TYP (0.665) SYMM TYP (6.8) (R0.05) TYP 12 25 METAL TYP 13 24 SYMM (6.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 49 66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:15X 4219046/B 11/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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