ADS1258 ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 16-CHANNEL, 24-BIT ANALOG-TO-DIGITAL CONVERTER CheckforSamples:ADS1258-EP FEATURES 1 • 24Bits,NoMissingCodes APPLICATIONS 23 • Fixed-ChannelorAutomaticChannelScan • Medical,Avionics,andProcessControl • Fixed-ChannelDataRate:125kSPS • MachineandSystemMonitoring • Auto-ScanDataRate:23.7kSPS/Channel • FastScanMulti-ChannelInstrumentation • Single-ConversionSettledData • IndustrialSystems • 16Single-Endedor8DifferentialInputs • TestandMeasurementSystems • Unipolar(5V)orBipolar(±2.5V)Operation SUPPORTS DEFENSE, AEROSPACE, • LowNoise:2.8μV at1.8kSPS RMS AND MEDICAL APPLICATIONS • 0.0003%IntegralNonlinearity • ControlledBaseline • DCStability(typical): • OneAssembly/TestSite 0.02μV/°COffsetDrift,0.4ppm/°CGainDrift • OneFabricationSite • Open-SensorDetection • AvailableinMilitary(–55°C/125°C)and • ConversionControlPin Industrial(–40°C/105°C)TemperatureRanges(1) • MultiplexerOutputforExternalSignal • ExtendedProductLifeCycle Conditioning • ExtendedProduct-ChangeNotification • On-ChipTemperature,Reference,Offset,Gain, andSupplyVoltageReadback • ProductTraceability • 42-mWPowerDissipation • Standby,Sleep,andPower-DownModes • 8General-PurposeInputs/Outputs(GPIO) • 32.768-kHzCrystalOscillatororExternalClock (1) Customtemperaturerangesavailable DESCRIPTION TheADS1258isa16-channel(multiplexed),low-noise,24-bit,delta-sigma(ΔΣ)analog-to-digitalconverter(ADC) that provides single-cycle settled data at channel scan rates from 1.8k to 23.7k samples per second (SPS) per channel. A flexible input multiplexer accepts combinations of eight differential or 16 single-ended inputs with a full-scale differential range of 5 V or true bipolar range of ±2.5 V when operating with a 5-V reference. The fourth-order delta-sigma modulator is followed by a fifth-order sinc digital filter optimized for low-noise performance. The differential output of the multiplexer is accessible to allow signal conditioning prior to the input of the ADC. Internalsystemmonitorregistersprovidesupplyvoltage,temperature,referencevoltage,gain,andoffsetdata. An onboard PLL generates the system clock from a 32.768-kHz crystal, or can be overridden by an external clock source. A buffered system clock output (15.7 MHz) is provided to drive a microcontroller or additional converters. Serial digital communication is handled via an SPI™ -compatible interface. A simple command word structure controlschannelconfiguration,datarates,digitalI/O,monitorfunctions,etc. Programmablesensorbiascurrentsourcescanbeusedtobiassensorsorverifysensorintegrity. The ADS1258 operates from a unipolar 5-V or bipolar ±2.5-V analog supply and a digital supply compatible with interfacesrangingfrom2.7Vto5.25V.TheADS1258isavailableinQFN-48andQFP-48packages. 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. SPIisatrademarkofMotorola,Inc. 2 Allothertrademarksarethepropertyoftheirrespectiveowners. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2009–2011,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com AVDD V DVDD GPIO[7:0] REF Internal ADS1258 Monitoring GPIO 1 CS DRDY 16:1 24−Bit Digital SPI SCLK AnalogInputs … Analog ADC Filter Interface DIN Input DOUT MUX 16 START Oscillator Control RESET AINCOM PWDN AVSS MUX ADC Extclk 32.768kHz DGND OUT IN In/Out This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION(1) T Package(2) ORDERABLEPART TOP-SIDEMARKING A NUMBER 48/RTC Tape&Reelof250 ADS1258MRTCTEP 1258MEP –55°Cto125°C 48/PHP Trayof250 ADS1258MPHPTEP ADS1258MEP –40°Cto105°C 48/PHP Tape&Reel1000 ADS1258IPHPREP ADS1258IEP (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI Websiteatwww.ti.com. (2) Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesignguidelinesareavailableat www.ti.com/sc/package. ABSOLUTE MAXIMUM RATINGS Overoperatingfree-airtemperaturerange(unlessotherwisenoted).(1) ADS1258 UNIT AVDDtoAVSS –0.3to5.5 V AVSStoDGND –2.8to0.3 V DVDDtoDGND –0.3to5.5 V InputCurrent 100,Momentary mA InputCurrent 10,Continuous mA AnalogInputVoltage AVSS–0.3toAVDD+0.3 V DigitalInputVoltagetoDGND –0.3toDVDD+0.3 V MaximumJunctionTemperature 150 °C StorageTemperatureRange –60to150 °C (1) Stressesabovetheseratingsmaycausepermanentdamage.Exposuretoabsolutemaximumconditionsforextendedperiodsmay degradedevicereliability.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyond thosespecifiedisnotimplied. 2 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 ELECTRICAL CHARACTERISTICS AllspecificationsatT =–55°Cto125°C,AVDD=2.5V,AVSS=–2.5V,DVDD=3.3V,f =16MHz(externalclock)orf =15.729 A CLK CLK MHz(internalclock),OPA227bufferbetweenMUXoutputsandADCinputs,V =4.096V,andVREFN=–2.5V,unlessotherwisenoted. REF PARAMETER CONDITIONS MIN TYP(1) MAX UNIT AnalogMultiplexerInputs AIN0–AIN15, AVSS– AVDD+ AbsoluteInputVoltage AINCOMwithrespectto V 100mV 100mV DGND On-ChannelResistance 80 Ω Crosstalk fIN=1kHz –110 dB SBCS[1:0]=01 1.5 SensorBias(CurrentSource) μA SBCS[1:0]=11 24 1.5μA:24μARatioError 1 % ADCInput Full-ScaleInputVoltage (VIN=ADCINP–ADCINN) ±1.06VREF V AVSS– AVDD+ AbsoluteInputVoltage (ADCINP,ADCINN) V 100mV 100mV DifferentialInputImpedance 65 kΩ SystemPerformance Resolution NoMissingCodes 24 Bits DataRate,Fixed-ChannelMode 1.953 125 kSPS DataRate,Auto-ScanMode 1.805 23.739 kSPS IntegralNonlinearity(INL)(2) DifferentialInput 0.0003 0.0010 F%SRo(f3) ChoppingOff 20 OffsetError Shorted TA=–40°Cto105°C 1 10 μV ChoppingOn Inputs TA=–55°Cto125°C -650 650 ChoppingOff 0.5 OffsetDrift ShortedInputs μV/°C ChoppingOn 0.02 0.1 TA=–40°Cto105°C 0.1 0.5 GainError % TA=–55°Cto125°C -0.5 0.1 0.5 TA=–40°Cto105°C 0.4 2 GainDrift ppm/°C TA=–55°Cto125°C 0.4 Noise (seeTable4) Common-ModeRejection fCM=60Hz 90 100 dB AVDD,AVSS 70 85 Power-SupplyRejection fPS=60Hz dB DVDD 80 95 VoltageReferenceInput AVDD– ReferenceInputVoltage (VREF=VREFP–VREFN) 0.5 4.096 AVSS V NegativeReferenceInput(VREFN) AVSS–0.1V VREFP–0.5 V PositiveReferenceInput(VREFP) VREFN+0.5 AVDD+0.1V V ReferenceInputImpedance 40 kΩ SystemParameters ExternalReferenceReadingError 1 3 % AnalogSupplyReadingError 1 3 % Voltage TA=25°C 168 mV OnlyADS1258-EPtemperature 394 TemperatureSensorReading forced;testPCBinfree-air. Coefficient μV/°C ADS1258-EPandtestPCB 563 temperaturesforcedtogether. (1) T =25°Cfortypicalparameters. A (2) Beststraightlinefitmethod. (3) FSR=Full-scalerange=2.13V . REF Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AllspecificationsatT =–55°Cto125°C,AVDD=2.5V,AVSS=–2.5V,DVDD=3.3V,f =16MHz(externalclock)or A CLK f =15.729MHz(internalclock),OPA227bufferbetweenMUXoutputsandADCinputs,V =4.096V,andVREFN CLK REF =–2.5V,unlessotherwisenoted. PARAMETER CONDITIONS MIN TYP(1) MAX UNIT DigitalInput/Output VIH 0.7DVDD DVDD V VIL DGND 0.3DVDD V LogicLevels VOH IOH=2mA 0.8DVDD DVDD V VOL IOL=2mA DGND 0.2DVDD V InputLeakage VIN=DVDD,GND 10 μA Frequency 0.1 16 MHz MasterClockInput(CLKIO) DutyCycle 40 60 % CrystalFrequency 32.768 kHz CrystalOscillator ClockOutputFrequency 15.729 MHz (seetheCrystalOscillator Start-UpTime(ClockOutput 150 mS section) Valid) ClockOutputDutyCycle 40 60 % PowerSupply DVDD 2.7 5.25 V AVSS –2.6 0 V AVDD AVSS+4.75 AVSS+5.25 V External TA=–40°Cto105°C 0.25 0.6 Clock mA Operation TA=–55°Cto125°C 0.25 0.75 InternalOscillatorOperation, DVDDSupplyCurrent ClockOutputDisabled 0.04 mA InternalOscillatorOperation, ClockOutputEnabled(4) 1.4 mA Power-Down(5) 1 25 µA Converting 8.2 12 mA Standby 5.6 mA AVDD,AVSSSupplyCurrent Sleep 2.1 mA Power-Down 2 85 µA Converting 42 62 mW Standby 29 mW PowerDissipation Sleep 11 mW Power-Down 14 μW (4) CLKIOload=20pF. (5) NoclockappliedtoCLKIO. 4 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 PIN CONFIGURATION Top View P N QFN UT UT P N AIN4 AIN5 AIN6 AIN7 MUXO MUXO ADCIN ADCIN AIN8 AIN9 AIN10 AIN11 48 47 46 45 44 43 42 41 40 39 38 37 AIN3 1 36 AIN12 AIN2 2 35 AIN13 AIN1 3 34 AIN14 AIN0 4 33 AIN15 AVSS 5 32 AINCOM AVDD 6 31 VREFP ADS1258 PLLCAP 7 30 VREFN XTAL1 8 29 DGND XTAL2 9 28 DVDD PWDN 10 27 CS RESET 11 26 START CLKSEL 12 25 DRDY 13 14 15 16 17 18 19 20 21 22 23 24 CLKIO GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 SCLK DIN DOUT Top View AIN4 AIN5 AIN6 AIN7 MUXOUTP MUXOUTN ADCINP NIADCN I8AN AIN9 AIN10 AIN11 QFP 48 47 46 45 44 43 42 41 40 39 38 37 AIN3 1 36 AIN12 AIN2 2 35 AIN13 AIN1 3 34 AIN14 AIN0 4 33 AIN15 AVSS 5 32 AINCOM AVDD 6 ADS1258 31 VREFP PLLCAP 7 30 VREFN XTAL1 8 29 DGND XTAL2 9 28 DVDD PWDN 10 27 CS RESET 11 26 START CLKSEL 12 25 DRDY 13 14 15 16 17 18 19 20 21 22 23 24 CLKIO GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 SCLK DIN DOUT Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com PINASSIGNMENTS ANALOG/DIGITAL PIN# NAME INPUT/OUTPUT DESCRIPTION 1 AIN3 AnalogInput AnalogInput3:Single-EndedChannel3,DifferentialChannel1(–) 2 AIN2 AnalogInput AnalogInput2:Single-EndedChannel2,DifferentialChannel1(+) 3 AIN1 AnalogInput AnalogInput1:Single-EndedChannel1,DifferentialChannel0(–) 4 AIN0 AnalogInput AnalogInput0:Single-EndedChannel0,DifferentialChannel0(+) NegativeAnalogPowerSupply:0Vforunipolaroperation,–2.5Vforbipolaroperation. 5 AVSS Analog (InternallyconnectedtoexposedthermalpadofQFNpackage.) 6 AVDD Analog PositiveAnalogPowerSupply:5Vforunipolaroperation,2.5Vforbipolaroperation. 7 PLLCAP Analog PLLBypassCapacitor:Connect22nFcapacitortoAVSSwhenusingcrystaloscillator. 8 XTAL1 Analog 32.768-kHzCrystalOscillatorInput1;seetheChrystalOscillatorsection. 9 XTAL2 Analog 32.768-kHzCrystalOscillatorInput2;seetheChrystalOscillatorsection. 10 PWDN DigitalInput Power-DownInput:HoldlowforminimumoftwofCLKcyclestoengagelow-powermode. 11 RESET DigitalInput ResetInput:HoldlowforminimumoftwofCLKcyclestoresetthedevice. 12 CLKSEL DigitalInput ClockSelectInput:Low=ActivatesCrystalOscillator,fCLKoutputonCLKIO. High=DisablesCrystalOscillator,applyfCLKtoCLKIO. 13 CLKIO DigitalI/O SystemClockInput/Output(SeeCLKSELpin.) 14 GPIO0 DigitalI/O General-PurposeDigitalInput/Output0 15 GPIO1 DigitalI/O General-PurposeDigitalInput/Output1 16 GPIO2 DigitalI/O General-PurposeDigitalInput/Output2 17 GPIO3 DigitalI/O General-PurposeDigitalInput/Output3 18 GPIO4 DigitalI/O General-PurposeDigitalInput/Output4 19 GPIO5 DigitalI/O General-PurposeDigitalInput/Output5 20 GPIO6 DigitalI/O General-PurposeDigitalInput/Output6 21 GPIO7 DigitalI/O General-PurposeDigitalInput/Output7 22 SCLK DigitalInput SPIInterfaceClockInput:Dataclockedinonrisingedge,clockedoutonfallingedge. 23 DIN DigitalInput SPIInterfaceDataInput:Dataisinputtothedevice. 24 DOUT DigitalOutput SPIInterfaceDataOutput:Dataisoutputfromthedevice. 25 DRDY DigitalOutput DataReadyOutput:Activelow. 26 START DigitalInput StartConversionInput:Activehigh. 27 CS DigitalInput SPIInterfaceChipSelectInput:Activelow. 28 DVDD Digital DigitalPowerSupply:2.7Vto5.25V 29 DGND Digital DigitalGround 30 VREFN AnalogInput ReferenceInputNegative 31 VREFP AnalogInput ReferenceInputPositive 32 AINCOM AnalogInput AnalogInputCommon:Commoninputpintoallsingle-endedinputs. 33 AIN15 AnalogInput AnalogInput15:Single-EndedChannel15,DifferentialChannel7(–) 34 AIN14 AnalogInput AnalogInput14:Single-EndedChannel14,DifferentialChannel7(+) 35 AIN13 AnalogInput AnalogInput13:Single-EndedChannel13,DifferentialChannel6(–) 36 AIN12 AnalogInput AnalogInput12:Single-EndedChannel12,DifferentialChannel6(+) 37 AIN11 AnalogInput AnalogInput11:Single-EndedChannel11,DifferentialChannel5(–) 38 AIN10 AnalogInput AnalogInput10:Single-EndedChannel10,DifferentialChannel5(+) 39 AIN9 AnalogInput AnalogInput9:Single-EndedChannel9,DifferentialChannel4(–) 40 AIN8 AnalogInput AnalogInput8:Single-EndedChannel8,DifferentialChannel4(+) 41 ADCINN AnalogInput ADCDifferentialInput(–) 42 ADCINP AnalogInput ADCDifferentialInput(+) 43 MUXOUTN AnalogOutput MultiplexerDifferentialOutput(–) 44 MUXOUTP AnalogOutput MultiplexerDifferentialOutput(+) 45 AIN7 AnalogInput AnalogInput7:Single-EndedChannel7,DifferentialChannel3(–) 46 AIN6 AnalogInput AnalogInput6:Single-EndedChannel6,DifferentialChannel3(+) 47 AIN5 AnalogInput AnalogInput5:Single-EndedChannel5,DifferentialChannel2(–) 48 AIN4 AnalogInput AnalogInput4:Single-EndedChannel4,DifferentialChannel2(+) 6 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 PARAMETER MEASUREMENT INFORMATION CS(1) tCSPW tCSSC tSCLK t SPW SCLK tDIST tSPW DIN tDIHD tDOPD Hi-Z Hi-Z DOUT t t CSDO NOTE: (1)CScan be tied low. DOHD Figure1. SerialInterfaceTiming SERIALINTERFACETIMINGCHARACTERISTICS AtT =–40°Cto+105°C(1)andDVDD=2.7Vto5.25V,unlessotherwisenoted. A SYMBOL DESCRIPTION MIN MAX UNITS t SCLKPeriod 2 τ (2) SCLK CLK t SCLKHighorLowPulseWidth(exceedingmaxresetsSPIinterface) 0.8 4096(3) τ SPW CLK t CSLowtoFirstSCLK:SetupTime(4) 2.5 τ CSSC CLK t ValidDINtoSCLKRisingEdge:SetupTime 10 ns DIST t ValidDINtoSCLKRisingEdge:HoldTime 5 ns DIHD t SCLKFallingEdgetoValidNewDOUT:PropagationDelay(5) 20 ns DOPD t SCLKFallingEdgetoOldDOUTInvalid:HoldTime 0 ns DOHD t CSHightoDOUTInvalid(tri-state) 5 τ CSDO CLK t CSPulseWidthHigh 2 τ CSPW CLK (1) Ensuredbycharacterizationonly. (2) τ =masterclockperiod=1/f . CLK CLK (3) Programmableto256τ . CLK (4) CScanbetiedlow. (5) DOUTload=20pF||100kΩtoDGND. t DRDY DRDY tDDO DOUT Figure2. DRDYUpdateTiming DRDYUPDATETIMINGCHARACTERISTICS SYMBOL DESCRIPTION TYP UNITS t DRDYHighPulseWidthWithoutDataRead 1 τ DRDY CLK t ValidDOUTtoDRDYFallingEdge(CS=0) 0.5 τ DDO CLK Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com ADS125848/RTCPackageOperatingLifeDeratingChart 1000 WirebondVoiding Fail Mode 100 e Lif d e a m sti E of s ar Electromigration Fail Mode Ye 10 1 80 90 100 110 120 130 140 150 160 ContinuousT (°C) J Figure3. Notes: 1. Seedatasheetforabsolutemaximumandminimumrecommendedoperatingconditions. 2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnectlife). 8 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 TYPICAL CHARACTERISTICS AtT =+25°C,AVDD=+2.5V,AVSS=–2.5V,DVDD=+3.3V,f =16MHz(externalclock)orf =15.729MHz(internalclock),OPA227 A CLK CLK bufferbetweenMUXoutputsandADCinputs,VREFP=+2.048V,andVREFN=–2.048V,unlessotherwisenoted. READINGHISTOGRAM READINGHISTOGRAM 3000 4500 DRATE[1:0]=11 DRATE[1:0]=10 16384Points 4000 16384Points 2500 s s 3500 e e c c en 2000 en 3000 urr urr c c 2500 Oc 1500 Oc of of 2000 ber 1000 ber 1500 m m u u N N 1000 500 500 0 0 050505050505050505050 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 544332211 112233445 3 3 2 2 1 1 1 1 2 2 3 3 - --------- - - - - - - Offset(m V) Offset(m V) Figure4. Figure5. READINGHISTOGRAM READINGHISTOGRAM 3500 2500 DRATE[1:0]=00 DRATE[1:0]=01 3000 16384Points 16384Points 2000 s s ce 2500 ce n n e e curr 2000 curr 1500 c c O O of 1500 of er er 1000 b b m 1000 m u u N N 500 500 0 0 0 6 2 8 4 0 4 8 2 6 0 2 0 8 6 4 2 0 2 4 6 8 0 2 2 1 1 1 1 2 1 1 1 1 - - - - - - - - - Offset(m V) - - Offset(m V) Figure6. Figure7. NOISEHISTOGRAM NOISEvsINPUTVOLTAGE 20 20 50unitsfromtwoproductionlots. DRATE[1:0]=11 es 15 15 c en V) DRATE[1:0]=11 urr m( c e Oc 10 ois 10 erof MSN DRATE[1:0]=10 mb R u 5 5 DRATE[1:0]=01 N DRATE[1:0]=00 0 0 0 5 0 5 0 5 0 5 0 5 0 - 100 - 75 - 50 - 25 0 25 50 75 100 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 1 1 1 1 1 1 1 1 1 1 1 InputVoltage(%FS) RMSNoise(m V) Figure8. Figure9. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AtT =+25°C,AVDD=+2.5V,AVSS=–2.5V,DVDD=+3.3V,f =16MHz(externalclock)orf =15.729MHz(internal A CLK CLK clock),OPA227bufferbetweenMUXoutputsandADCinputs,VREFP=+2.048V,andVREFN=–2.048V,unlessotherwise noted. NOISEvsV NOISEvsSUPPLYVOLTAGE REF 16 20 DRATE[1:0]=11 14 18 12 DRATE[1:0]=11 16 V) V) 10 14 m( m( fromDVDD e e s DRATE[1:0]=10 s oi 8 oi 12 N N MS 6 MS 10 R DRATE[1:0]=01 R fromAVDD−AVSS 4 8 DRATE[1:0]=00 2 6 0 4 0.5 1.5 2.5 3.5 4.5 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V (V) DVDD,AVDD−AVSS(V) REF Figure10. Figure11. NOISEANDOFFSETvs NOISEvsTEMPERATURE COMMON-MODEINPUTVOLTAGE 20 20 5 DRATE[1:0]=11 OFFSET 18 CHOP=1 16 15 0 V) V) m( 14 m( V) e e Nois 12 Nois 10 NOISE - 5 mset( MS 10 MS Off R R OFFSET 8 5 CHOP=0 - 10 6 4 0 - 15 - 40 - 20 0 20 40 60 80 100 - 3 - 2 - 1 0 1 2 3 Temperature((cid:1)C) Common−ModeInputVoltage(V) Figure12. Figure13. OFFSETHISTOGRAM OFFSETDRIFTHISTOGRAM 200 80 311unitsfromoneproductionlot. 50unitsfromtwo 180 CHOP=1 productionlots. 160 Basedon20(cid:1)Cintervals es es 60 overtherangeof enc 140 enc - 40(cid:1)Cto+105(cid:1)C. urr 120 urr CHOP=1 Occ 100 Occ 40 of of er 80 er b b m 60 m u u 20 N N 40 20 0 0 0 8 6 4 2 0 2 4 6 8 0 098765432101234567890 1 1 1000000000 0000000001 - - - - -Offset(m V) 0.0.0.0.0.0.0.0.0.0. 0.0.0.0.0.0.0.0.0.0. ---------- OffsetDrift(m V/(cid:1)C) Figure14. Figure15. 10 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 TYPICAL CHARACTERISTICS (continued) AtT =+25°C,AVDD=+2.5V,AVSS=–2.5V,DVDD=+3.3V,f =16MHz(externalclock)orf =15.729MHz(internal A CLK CLK clock),OPA227bufferbetweenMUXoutputsandADCinputs,VREFP=+2.048V,andVREFN=–2.048V,unlessotherwise noted. OFFSETvsTEMPERATURE OFFSETvsV REF 20 10 CHOP=1,NoBuffer CHOP=1 8 6 V) 0 V) mNormalizedOffset( -- 2400 mNormalizedOffset( --- 420246 CHOP=0,NoBuffer - 8 50unitsfromtwoproductionlots. - 60 - 10 - 40 - 20 0 20 40 60 80 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Temperature((cid:1)C) V (V) REF Figure16. Figure17. OFFSETPOWER-ONWARMUP GAINERRORHISTOGRAM 10 80 Free−Air 320unitsfromoneproductionlot. 8 6 V) es 60 mdOffset( 420 Occurrenc 40 alize - 2 erof Norm -- 46 Numb 20 - 8 - 10 0 0 10 20 30 40 50 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TimeAfterPower−On(s) 1 3 5 7 9 11 13 15 17 19 AbsoluteGainError(ppm) Figure18. Figure19. GAINDRIFTHISTOGRAM GAINERRORvsTEMPERATURE 80 30 50unitsfromtwoproductionlots. Basedon20(cid:1)Cintervalsoverthe rangeof- 40(cid:1)Cto+105(cid:1)C. m) es 60 pp 20 c ( urren Error Occ 40 ain 10 G of d mber alize u 20 m 0 N or N 0 - 10 864 20864 20246802468 - 40 - 20 0 20 40 60 80 100 1.1.1. 1.1.0.0.0. 0. 0.0.0.0.1.1.1.1.1. Temperature((cid:1)C) - -------- GainDrift(ppm/(cid:1)C) Figure20. Figure21. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AtT =+25°C,AVDD=+2.5V,AVSS=–2.5V,DVDD=+3.3V,f =16MHz(externalclock)orf =15.729MHz(internal A CLK CLK clock),OPA227bufferbetweenMUXoutputsandADCinputs,VREFP=+2.048V,andVREFN=–2.048V,unlessotherwise noted. GAINERRORvsV GAINERRORPOWER-ONWARMUP REF 20 10 Free−Air 8 15 m) m) 6 (pp 10 (pp 4 Error 5 Error 2 ain 0 ain 0 G G malized - -150 malized -- 24 or or - 6 N - 15 N - 8 - 20 - 10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 10 20 30 40 50 60 V (V) TimeAfterPower−On(s) REF Figure22. Figure23. INTEGRALNONLINEARITYvsV INTEGRALNONLINEARITYvsINPUTLEVEL REF 10 10 V =5V 8 TRE=F- 40(cid:1)C, - 10(cid:1)C,+25(cid:1)C,+55(cid:1)C,+85(cid:1)C,+105(cid:1)C A 8 6 m) m) 4 (pp 6 (pp 2 Error Error 0 Linearity 4 Linearity -- 24 2 - 6 - 8 0 - 10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 - 5 - 4 - 3 - 2 - 1 0 1 2 3 4 5 V (V) V (V) REF IN Figure24. Figure25. INTEGRALNONLINEARITYvsTEMPERATURE OUTPUTSPECTRUM 8 0 f = 1kHz,-0.5dBFS -20 DRATE[1:0] = 11 -40 65536 Points 6 -60 L(ppm) 4 el (dBFS) -1-0800 N v I Le -120 2 -140 -160 0 -180 - 40 - 20 0 20 40 60 80 100 120 1 10 100 1k 10k 100k Temperature((cid:1)C) Frequency (Hz) Figure26. Figure27. 12 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 TYPICAL CHARACTERISTICS (continued) AtT =+25°C,AVDD=+2.5V,AVSS=–2.5V,DVDD=+3.3V,f =16MHz(externalclock)orf =15.729MHz(internal A CLK CLK clock),OPA227bufferbetweenMUXoutputsandADCinputs,VREFP=+2.048V,andVREFN=–2.048V,unlessotherwise noted. TEMPERATURESENSORVOLTAGEvsTEMPERATURE TEMPERATURESENSORREADINGHISTOGRAM 220 8 ADS1258 and Test PCB 50unitsfromtwoproductionlots. mV) 210 Temperatures Forced Together 7 TA=+25(cid:1)C nsor Voltage ( 211109870000 Occurrences 654 perature Se 111654000 TTeemstp PeOCranBtluy i rnAe DFFrSoe1rec2-eA5d8ir; Numberof 32 m Te 130 1 120 0 -40 -20 0 20 40 60 80 100 120 2345678901234567890123456 Temperature (°C) 1111111T1em2p2er2atu2re2R2ea2din2g2((cid:1)2C)3333333 Figure28. Figure29. SENSORBIASCURRENTSOURCERATIO SENSORBIASCURRENTSOURCERATIO HISTOGRAM vsTEMPERATURE 25 18 50unitsfromtwoproductionlots. 20 es 17 c n Occurre 15 mm(A/A) 16 erof 10 Ratio b m u 15 N 5 0 14 0 5 0 5 0 5 0 5 0 5 0 - 40 - 20 0 20 40 60 80 100 120 14. 14. 15. 15. 16. 16. 17. 17. 18. 18. 19. Temperature((cid:1)C) Ratio(m A/m A) Figure30. Figure31. SUPPLYCURRENTvsTEMPERATURE NOISEANDINLvsMASTERCLOCK 10 1.0 20 20 AVDD,AVSS DRATE[1:0]=11 A) 8 0.8 16 16 nt(m mA) V) Noise pm) SSCurre 6 0.6 Current( mNoise( 12 12 yError(p D,AV 4 0.4 VDD RMS 8 8 nearit D D Li AV 2 DVDD 0.2 4 4 Linearity 0 0 0 0 - 40 - 20 0 20 40 60 80 100 120 0.1 1 10 100 Temperature((cid:1)C) MasterClock(MHz) Figure32. Figure33. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com OVERVIEW The ADS1258 is a flexible, 24-bit, low-noise ADC V = (ADCINP – ADCINN), against the differential IN optimized for fast multi-channel, high-resolution reference input, V = (VREFP – VREFN). The REF measurement systems. The converter provides a digital filter receives the modulator signal and maximumchannelscanrateof23.7kSPS,providinga provides a low-noise digital output. The ADC channel complete16-channelscaninlessthan700μs. block controls the multiplexer Auto-Scan feature. Channel Auto-Scan occurs at a maximum rate of Figure 34 shows the block diagram of the ADS1258. 23.7kSPS. Slower scan rates can be used with The input multiplexer selects the analog input pins correspondingincreasesinresolution. connected to the multiplexer output pins (MUXOUTP/MUXOUTN). External signal conditioning Communication is handled over an SPI-compatible can be used between the multiplexer output pins and serial interface with a set of simple commands the ADC input pins (ADCINP/ADCINN) or the providing control of the ADS1258. Onboard registers multiplexer output can be routed internally to the ADC store the various settings for the input multiplexer, inputs without external circuitry. Selectable current sensor detect bias, data rate selection, etc. Either an sources within the input multiplexer can be used to external 32.768kHz crystal, connected to pins XTAL1 bias sensors or detect for a failed sensor. On-chip andXTAL2,oranexternalclockappliedtopinCLKIO system function readings provide readback of can be used as the clock source. When using the temperature,supplyvoltage,gain,offset,andexternal external crystal oscillator, the system clock is reference. available as an output for driving other devices or controllers. General-purpose digital I/Os (GPIO) The ADS1258 converter comprises a fourth-order, provideinputandoutputcontrolofeightpins. delta-sigma modulator followed by a programmable digital filter. The modulator measures the differential input signal, AVDD DVDD GPIO[7:0] CLKIO CLKSEL PLLCAP XTAL2 XTAL1 ClockControl GPIO AIN0 Sensor AIN1 Bias CS AIN2 SPI SCLK AIN3 Interface DIN AIN4 DOUT AIN5 SupplyMonitor Temperature AIN6 DRDY AIN7 Control PWDN 16−Channel AIN8 MUX ADCChannelControl Logic RESET AIN9 START AIN10 InternalRef AIN11 AIN12 ExtRefMonitor AIN13 AIN14 ADC DigitalFilter AIN15 AINCOM AVSS MUXOUTP MUXOUTN ADCINP ADCINN VREFN VREFP GND Figure34. ADS1258BlockDiagram 14 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 MULTIPLEXER INPUTS A simplified diagram of the input multiplexer is illustrated in Figure 36. The multiplexer connects one AVDD of 16 single-ended external inputs, one of eight differential external inputs, or one of the on-chip internalvariablestotheADCinputs.Theoutputofthe ESD channel multiplexer can be routed to external pins Diodes and then to the input of the ADC. This flexibility allows for use of external signal conditioning. See the VREFP ExternalMultiplexerLoopsection. 3pF Reff=40kW ESD diodes protect the analog inputs. To keep these (fCLK=16MHz) diodes from turning on, make sure the voltages on VREFN the input pins do not go below AVSS by more than ESD 100 mV, and likewise do not exceed AVDD by more Diodes than100mV: AVSS– 100mV <(AnalogInputs)< AVDD+100mV. AVSS Overdriving the multiplexer inputs may affect the conversions of other channels. See the Input Overload Protection description in the Hardware Figure35. SimplifiedReferenceInputCircuit ConsiderationssegmentoftheApplicationssection. The converter supports two modes of channel access ESD diodes protect the reference inputs. To keep through the multiplexer: the Auto-Scan mode and the these diodes from turning on, make sure the voltages Fixed-Channel mode. These modes are selected by on the reference pins do not go below AVSS by more the MUXMOD bit of register CONFIG0. The than 100mV, and likewise do not exceed AVDD by Auto-Scan mode scans through the selected 100mV,asdescribedinEquation1: channels automatically, with break-before-make AVSS(cid:2)100mV(cid:3)(cid:4)VREFP or VREFN(cid:5)(cid:3)AVDD(cid:1)100mV (1) switching. The Fixed-Channel mode requires the user A high-quality reference voltage is essential for to set the channel address for each channel achieving the best performance from the ADS1258. measured. Noise and drift on the reference degrade overall system performance. It is especially critical that VOLTAGE REFERENCE INPUTS special care be given to the circuitry that generates (VREFP, VREFN) the reference voltages and the layout when operating The voltage reference for the ADS1258 ADC is the in the low-noise settings (that is, with low data rates) differential voltage between VREFP and VREFN: to prevent the voltage reference from limiting V = VREFP – VREFN. The reference inputs use a performance. See the Reference Inputs description in REF structure similar to that of the analog inputs with the the Hardware Considerations segment of the circuitry on the reference inputs shown in Figure 35. Applicationssection. The load presented by the switched capacitor can be modeled with an effective resistance (R ) of 40 kΩ eff for f = 16 MHz. Note that the effective impedance CLK of the reference inputs loads an external reference withanon-zerosourceimpedance. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com VREFP VREFN Multiplexer Reference/GainMonitor AIN0 AIN1 AIN2 TemperatureSensorMonitor AVDD AIN3 1x 2x AIN4 AIN5 8x 1x AIN6 AVSS AIN7 SupplyMonitor AIN8 AVDD AVSS AIN9 AIN10 AIN11 NOTE:ESDdiodesnotshown. AIN12 Internal AVSS Reference AIN13 AIN14 AIN15 ADC AINCOM AVSS AVDD (AVDD- AVSS)/2 SensorBias OffsetMonitor P N P N T T N N UXOU UXOU ADCI ADCI M M Figure36. InputMultiplexer 16 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 ADC INPUTS As with the multiplexer and reference inputs, ESD diodes protect the ADC inputs. To keep these diodes The ADS1258 ADC inputs (ADCINP, ADCINN) from turning on, make sure the voltages on the input measure the input signal using internal capacitors pins do not go below AVSS by more than 100 mV, that are continuously charged and discharged. The and likewise do not exceed AVDD by more than 100 left side of Figure 38 shows a simplified schematic of mV. the ADC input circuitry; the right side of Figure 38 shows the input circuitry with the capacitors and switches replaced by an equivalent circuit. Figure 37 shows the ON/OFF timings of the switches shown in t SAMPLE Figure 38. S switches close during the input ON 1 sampling phase. With S closed, C charges to S1 1 A1 OFF ADCINP, C charges to ADCINN, and C charges to A2 B (ADCINP – ADCINN). For the discharge phase, S1 ON opensfirstandthenS closes.C andC discharge S 2 A1 A2 2 to approximately AVSS + 1.3 V and C discharges to OFF B 0V. This two-phase sample/discharge cycle repeats withaperiodoft =2/f . SAMPLE CLK Figure37. S andS SwitchTimingforFigure38 Thechargingoftheinputcapacitorsdrawsatransient 1 2 current from the source driving the ADS1258 ADC inputs. The average value of this current can be used to calculate an effective impedance (R ) where R = eff eff V /I . These impedances scale inversely with IN AVERAGE f . For example, if f is reduced by a factor of CLK CLK two,theimpedancesdouble. AVSS+1.3V AVSS+1.3V S 2 CA1=0.65pF ReffA=190kW S 1 Equivalent ADCINP Circuit ADCINP CB=1.6pF ReffB=78kW (fCLK=16MHz) S 1 ADCINN ADCINN C =0.65pF R =190kW A2 effA S 2 AVSS+1.3V AVSS+1.3V Reff=tSAMPLE/CX RAIN=ReffB||2ReffA NOTE:ESDinputdiodesnotshown. Figure38. SimplifiedADCInputStructure Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com MASTER CLOCK (f ) CLK The ADS1258 oversamples the analog input at a high rate. This requires a high-frequency master clock to 50W ClockOutput be supplied to the converter. As shown in Figure 39, CLKIO (15.729MHz) theclockcomesfromeitheraninternaloscillator(with externalcrystal),oranexternalclocksource. AVSS 0Vto- 2.5V CLKSEL XTAL1 XTAL2 PLLCAP CLKENB Bit 32.768kHz(1) 22nF 4.7pF 4.7pF Internal Master Clock (f ) CLK NOTE:(1)Parallelresonanttype,C =12.5pF,ESR=35kW (max). L Placethecrystalandloadcapacitorsascloseaspossibletothedevicepins. MUX CLKIO Figure40. CrystalOscillatorConnection Oscillator and PLL Table1.SystemClockSource CLKSEL CLKENB CLKSEL XTAL1 XTAL2 PLL PIN CLOCKSOURCE BIT CLKIOFUNCTION 32.768kHz Disabled 0 0 Figure39. ClockGenerationBlockDiagram CrystalOscillator (internallygrounded) 32.768kHz 0 1 Output(15.729MHz) CrystalOscillator The CLKSEL pin determines the source of the 1 ExternalClockInput X Input(16MHz) system clock, as shown in Table 1. The CLKIO pin functions as an input or as an output. When the Table2.ApprovedCrystalVendors CLKSEL pin is set to '1', CLKIO is configured as an input to receive the master clock. When the CLKSEL VENDOR CRYSTALPRODUCT pin is set to '0', the crystal oscillator generates the C-001R clock. The CLKIO pin can then be configured to Epson MC-30632.7680K-A0 output the master clock. When the clock output is not needed, it can be disabled to reduce device power FC-13532.7680KA-A0 consumption. ECS ECS-.327-12.5-17-TR CrystalOscillator ExternalClockInput An on-chip oscillator and Phase-Locked Loop (PLL) When using an external clock to operate the device, together with an external crystal can be used to apply the master clock to the CLKIO pin. For this generate the system clock. For this mode, tie the mode, the CLKSEL pin is tied high. CLKIO then CLKSEL pin low. A 22nF PLL filter capacitor, becomesaninput,asshowninFigure41. connected from the PLLCAP pin to the AVSS pin, is required. The internal clock of the PLL can be output to the CLKIO to drive other converters or controllers. 50W If not used, disable the clock output to reduce device CLKIO ClockInput (16MHz) power consumption; see Table 1 for settings. The clock output is enabled by a register bit setting 2.7V DVDD (default is ON). Figure 40 shows the oscillator to5V connections. Place these components as close to the CLKSEL XTAL1 XTAL2 PLLCAP pins as possible to avoid interference and coupling. Do not connect XTAL1 or XTAL2 to any other logic. NoConnection The oscillator start-up time may vary, depending on the crystal and ambient temperature. The user should Figure41. ExternalClockConnection verifytheoscillatorstart-uptime. 18 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 Make sure to use a clock source clean from jitter or rate—filter more for higher resolution, filter less for interference. Ringing or under/overshoot should be higher data rate. The filter is comprised of two avoided. A 50 Ω resistor in series with the CLKIO pin sections, a fixed filter followed by a programmable (placedclosetothesource)canoftenhelp. filter. Figure 42 shows the block diagram of the filter. Data is supplied to the filter from the analog ADC modulator at a rate of f /2. The fixed filter is a CLK fifth-order sinc filter with a decimation value of 64 that The ADC block of the ADS1258 is composed of two outputs data at a rate of f /128. The second stage blocks:amodulatorandadigitalfilter. CLK of the filter is a programmable averager (first-order sinc filter) with the number of averages set by the Modulator DRATE[1:0]bits. The modulator converts the analog input voltage into The data rate depends upon the system clock a Pulse Code Modulated (PCM) data stream. When frequency (f ) and the converter configuration. The the level of differential analog input (ADCINP – CLK data rate can be computed by Equation 2 or ADCINN) is near the level of the reference voltage, Equation3: the '1' density of the PCM data stream is at its highest.Whenthelevelofthedifferentialanaloginput DataRate(Auto-Scan): is near zero, the PCM '0' and '1' densities are nearly f CLK equal. The fourth-order modulator shifts the 128(411b(cid:3)DR(cid:2)4.265625(cid:2)TD)(cid:1)2CHOP (2) quantization noise to a high frequency (out of the passband)wherethedigitalfiltercaneasilyremoveit. DataRate(Fixed-ChannelMode): The modulator continuously chops the input, resulting fCLK in excellent offset and offset drift performance. It is 128(411b(cid:3)DR(cid:2)CHOP(4.265625(cid:2)TD))(cid:1)2CHOP (3) important to note that offset or offset drift originating from the external circuitry is not removed by the Where: modulator chopping. These errors can be effectively DR=DRATE[1:0]registerbits(binary). removed by using the external chopping feature of CHOP=Chopregisterbit. theADS1258(seetheExternalChoppingsection). TD = time delay value given in Table 5 from the DLY[2:0]registerbits(128/f periods). DigitalFilter CLK The programmable low-pass digital filter receives the modulator output and produces a high-resolution digital output. By adjusting the amount of filtering, tradeoffs can be made between resolution and data ModulatorRate=f /2 DataRate=f /128 DataRate(1)=f /(128×Num_Ave) CLK CLK CLK Analog sinc5 Programmable Modulator Filter Averager Num_Ave NOTE:(1)DatarateforFixed−ChannelMode,Chop=0,Delay=0. Figure42. BlockDiagramofDigitalFilter Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com Table 3 shows a listing of the averaging and data Figure 44 shows the response with averaging set to 4 rates for each of the four DRATE[1:0] register (DRATE[1:0] = 10). 4-reading, post-averaging settings for the Auto-Scan and Fixed-Channel modes, produces three equally-spaced notches between with CHOP, DLY = 0. Note that the data rate scales each main notch of the sinc5 filter. The frequency directly with f . For example, reducing f by 2x responseofDRATE[1:0]=01and00followsasimilar CLK CLK reducesthemaximumdatarateby2x. pattern, but with 15 and 63 equally-spaced notches betweenthemainsinc5notches,respectively. FREQUENCY RESPONSE The low-pass digital filter sets the overall frequency 0 DataRate response for the ADS1258. The filter response is the - 20 Auto−ScanMode product of the responses of the fixed and (23.739kSPS) programmable filter sections and is given by - 40 Equation4: DataRate (cid:3)H(cid:4)f(cid:5)(cid:3)(cid:2)(cid:3)Hsinc5(cid:4)f(cid:5)(cid:3)(cid:1)(cid:3)HAverager(cid:4)f(cid:5)(cid:3)(cid:2) n(dB) - 60 F(1ix2e5dk−SCPhSa)nnelMode ai - 80 5 G (cid:6) sin(cid:4)128(cid:1)(cid:1)f(cid:5) (cid:6) (cid:6) sin(cid:4)128(cid:1)(cid:1)Num_Ave(cid:1)f(cid:5) (cid:6) - 100 (cid:6) fCLK (cid:6) (cid:6) fCLK (cid:6) (cid:6)(cid:6)64(cid:1)sin(cid:4)2(cid:1)(cid:1)f(cid:5)(cid:6)(cid:6)(cid:1)(cid:6)(cid:6)Num_Ave(cid:1)sin(cid:4)128(cid:1)(cid:1)f(cid:5)(cid:6)(cid:6) - 120 f f CLK CLK (4) - 140 0 125 250 375 500 625 The digital filter attenuates noise on the modulator output including noise from within the ADS1258 and Frequency(kHz) external noise present within the ADS1258 input signal. Adjusting the filtering by changing the number Figure43. FrequencyResponse,DRATE[1:0]=11 of averages used in the programmable filter changes the filter bandwidth. With a higher number of averages, the bandwidth is reduced and more noise 0 isattenuated. DataRate - 20 Auto−ScanMode The low-pass filter has notches (or zeros) at the data (15.123kSPS) output rate and multiples thereof. The sinc5 part of - 40 the filter produces wide notches at fCLK/128 and DataRate multiples thereof. At these frequencies, the filter has B) - 60 Fixed−ChannelMode d zero gain. Figure 43 shows the response with no post n( (31.25kSPS) ai - 80 averaging. Note that in Auto-Scan mode, the data G rate is reduced while retaining the same frequency - 100 responseasinFixed-Channelmode. - 120 With programmable averaging, the wide notches produced by the sinc5 filter remain, but a number of - 140 0 125 250 375 500 625 narrow notches are superimposed in the response. The number of the superimposed notches is Frequency(kHz) determined by the number of readings averaged(minusone). Figure44. FrequencyResponse,DRATE[1:0]=10 Table3.DataRates(1) DATARATEAUTO-SCAN DATARATEFIXED-CHANNEL –3dBBANDWIDTH DRATE[1:0] Num_Ave(2) MODE(SPS)(3) MODE(SPS) (Hz) 11 1 23739 125000 25390 10 4 15123 31250 12402 01 16 6168 7813 3418 00 64 1831 1953 869 (1) f =16MHz,Chop=0,andDelay=0. CLK (2) Num_Aveisthenumberofaveragesperformedbythedigitalfiltersecondstage. (3) InAuto-Scanmode,thedataratelistedisforasinglechannel;theeffectivedatarateformultiplechannels(onaper-channelbasis)is thevalueshowninFigure43andFigure44dividedbythenumberofactivechannelsinascanloop. 20 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 ALIASING input. For most modes of operation, the analog input must be stable for one complete conversion cycle to The digital filter low-pass characteristic repeats at provide settled data. In Fixed-Channel mode multiples of the modulator rate of f /2. Figure 45 CLK (DRATE[1:0] = 11), the input must be stable for five shows the response plotted out to 16MHz at the data completeconversioncycles. rate of 125 kSPS (Fixed-Channel mode). Notice how the responses near DC, 8 MHz, and 16 MHz are the same. The digital filter attenuates high-frequency DataNotSettled SettledData noise on the ADS1258 inputs up to the frequency where the response repeats. However, noise or DRDY 1 2 frequency components present on the analog input where the response repeats alias into the passband. For most applications, an anti-alias filter is StepInput recommended to remove the noise. A simple first-order input filter with a pole at 200kHz provides–34dBrejectionatthefirstimagefrequency. Figure46. AsynchronousStep-InputSettling Time(DRATE[1:0]=10,01,00) 0 DRATE[1:0]=11 - 20 125kSPS Fixed−ChannelMode DataNotSettled SettledData - 40 DRDY 1 2 6 B) - 60 d ( n ai - 80 G StepInput - 100 - 120 Figure47. AsynchronousStep-InputSettling - 140 Time(Fixed-ChannelMode,DRATE[1:0]=11) 0 4 8 12 16 Frequency(MHz) NOISE PERFORMANCE Figure45. FrequencyResponseOutto16MHz The ADS1258 offers outstanding noise performance that can be optimized by adjusting the data rate. As the averaging is increased by reducing the data rate, Referring to Figure 43 and Figure 44, frequencies noise drops correspondingly. See Table 4 for present on the analog input above the Nyquist rate Input-Referred Noise, Noise-Free Resolution, and (sample rate/2) are first attenuated by the digital filter Effective Number of Bits (ENOB). The noise andthenaliasintothepassband. performance of low-level signals can be improved substantially by using external gain. Note that when SETTLING TIME Chop = 1, the data rate is reduced by 2x and the The design of the ADS1258 provides fully-settled noiseisreducedby1.4x. data when scanning through the input channels in ENOBisdefinedinEquation5: Auto-Scan mode. The DRDY flag asserts low when the data for each channel is ready. It may be ln(cid:3)FSR(cid:2)RMS Noise(cid:4) necessary to use the automatic switch time delay ENOB(cid:1) ln(2) (5) feature to provide time for settling of the external buffer and associated components after channel whereFSRisthefull-scalerange. switching. When the converter is started (START pin The data for the Noise-Free Resolution (bits) is transitions high or Start Command) with stable inputs, calculated in the same way as ENOB, except the first converter output is fully settled. When peak-to-peaknoiseisused. applying asynchronous step inputs, the settling time is somewhat different. The step-input settling time As seen in the illustration of Noise vs V REF diagrams (Figure 46 and Figure 47) show the (Figure 10), the converter noise is relatively constant converter step response with an asynchronous step versus the reference voltage. Optimum signal-to-noise ratio of the converter is achieved by using higher reference voltages (V = AVDD – REF MAX AVSS). Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com Table4.NoisePerformance(1) DATARATE EFFECTIVE DATARATE FIXED-CHANNEL INPUT-REFERRED NOISE-FREE NUMBER AUTO-SCANMODE MODE NOISE RESOLUTION OFBITS DRATE[1:0] (SPS) (SPS) (µV ) (Bits) (ENOB) RMS 11 23739 125000 12 16.8 19.5 10 15123 31250 7.9 17.4 20.1 01 6168 7813 4.5 18.2 20.9 00 1831 1953 2.8 18.9 21.6 (1) V =4.096V,f =16MHz,Chop=0,Delay=0,Inputsshorted,and2048samplesize. REF CLK Table5.EffectiveDataRateswithSwitch-TimeDelay(Auto-ScanMode)(1) TIMEDELAY TIMEDELAY DLY[2:0] (128/fCLKperiods) (μS) DRATE[1:0]=11 DRATE[1:0]=10 DRATE[1:0]=01 DRATE[1:0]=00 000 0 0 23739 15123 6168 1831 001 1 8 19950 13491 5878 1805 010 2 16 17204 12177 5614 1779 011 4 32 13491 10191 5151 1730 100 8 64 9423 7685 4422 1639 101 16 128 5878 5151 3447 1483 110 32 256 3354 3104 2392 1247 111 48 384 2347 2222 1831 1075 (1) Timedelayanddataratesscalewithf .IfChop=1,thedataratesarehalfthoseshown.f =16MHz,Auto-ScanMode. CLK CLK Use of the switch time delay register reduces the EXTERNAL MULTIPLEXER LOOP effective channel data rate. Table 5 shows the actual The external multiplexer loop consists of two data rates derived from Equation 2, when using the differential multiplexer output pins and two differential switchtimedelayfeature. ADC input pins. The user may use external When pulse converting, where one channel is components (buffering/filtering, single-ended to converted with each START pin pulse or each pulse differential conversion, etc.), forming a signal command, the application software may provide the conditioning loop. For best performance, the ADC required time delay between pulses. However, with inputshouldbebufferedanddrivendifferentially. Chop = 1, the switch time delay feature may still be To bypass the external multiplexer loop, connect the necessarytoallowforsettling. ADC input pins directly to the multiplexer output pins, In estimating the time delay that may be required, or select internal bypass connection (BYPASS = 0 of Table 6 lists the time delay-to-time constant ratio (t/τ) CONFIG0). Note that the multiplexer output pins are and the corresponding final settled data in % and activeregardlessofthebypasssetting. numberofbits. SWITCH TIME DELAY Table6.SettlingTime When using the ADS1258 in the Auto-Scan mode, FINALSETTLING FINALSETTLING where the converter automatically switches from one t/τ(1) (%) (Bits) channel to the next, the settling time of the external 1 63 2 signal conditioning circuit becomes important. If the 3 95 5 channel does not fully settle after the multiplexer channel is switched, the data may not be correct. The 5 99.3 7 ADS1258 provides a switch time delay feature which 7 99.9 10 automaticallyprovidesadelayafterchannelswitching 10 99.995 14 to allow the channel to settle before taking a reading. 15 99.9999 20 The amount of time delay required depends primarily 17 99.999994 24 onthesettlingtimeoftheexternalsignalconditioning. Additional consideration may be needed to account for the settling of the input source arising from the transientgeneratedfromchannelswitching. (1) Multipletimeconstantscanbeapproximatedby: (τ 2+τ 2+…). 1 2 22 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 SENSOR BIAS The current source is connected to the output of the multiplexer. For unselected channels, the current An integrated current source provides a means to source is not connected. This configuration means bias an external sensor (for example, a diode that when a new channel is selected, the current junction); or, it verifies the integrity of a sensor or source charges stray sensor capacitance, which may sensor connection. When the sensor fails to an open slow the rise of the sensor voltage. The automatic condition, the current sources drive the inputs of the switch time delay feature can be used to apply an converter to positive full-scale. The biasing is in the appropriate time delay before a conversion is started form of differential currents (programmable 1.5μA or to provide fully settled data (see the Switch Time 24μA),connectedtotheoutputofthemultiplexer. Delaysection). Figure 48 shows a simplified diagram of ADS1258 The time to charge the external capacitance is given input structure with the external sensor modeled as a inEquation6: resistance R between two input pins. The two 80Ω series resistoSrs, RMUX, model the ADS1258 internal dV(cid:1)ISDC resistances. R represents the effective input dt C (6) L resistance of the ADC input or external buffer. When It is also important to note that the low impedance the sensor bias is enabled, they source I to one SDC (65kΩ) of the direct ADC inputs or the impedance of selected input pin (connected to the MUXOUTP the external signal conditioning loads the current channel) and sink I from the other selected input SDC sources. This low impedance limits the ability of the pin (connected to the MUXOUTN channel). The current source to pull the inputs to positive full-scale signal measured with the biasing enabled equals the foropen-channeldetection. total IR drop: I [(2R + R )׀׀ R ]. Note that when SDC MUX S L the sensor is a direct short (that is, R = 0), there is S OPEN-SENSOR DETECTION still a small signal measured by the ADS1258 when thebiasingisenabled:ISDC[2RMUX׀׀ RL]. For open-sensor detection, set the biasing to either 1.5μA or 24μA. Then select the channel and read the output code. When a sensor opens, the positive input is pulled to AVDD and the negative input is pulled to AVDD AVSS. Because of this configuration, the output code trends toward positive full-scale. Note that the I SDC interaction of the multiplexer resistance with the current source may lead to degradation in converter 80W linearity. It is recommended to enable the current MUXOUTP ADCINP source only periodically to check for open inputs and discardtheassociateddata. R R S L 80W EXTERNAL DIODE BIASING ADCINN MUXOUTN The current source can be used to bias external diodes for temperature sensing. Scan the appropriate channels with the current source set to 24µA. I SDC Re-scan the same channels with the current source set to 1.5µA. The difference in diode voltage readings AVSS resulting from the two bias currents is directly proportionaltotemperature. Note that errors in current ratio, diode and cable Figure48. SensorBiasStructure resistance, or the non-ideality factor of the diode can lead to errors in temperature readings. These effects can be compensated by characterization or by calibratingthediodeatknowntemperatures. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com EXTERNAL CHOPPING GPIO DIGITAL PORT (GPIOx) The modulator of the ADS1258 incorporates a The ADS1258 has eight dedicated pins for chopping front-end which removes offset errors, General-Purpose Digital I/O (GPIO). The digital I/O providing excellent offset and offset drift performance. pins are individually configurable as either inputs or However, offset and offset drift originating from as outputs through the GPIOC (GPIO-Configure) external signal conditioning are not removed by the register. The GPIOD (GPIO-Data) register controls modulator. The ADS1258 has an additional chopping the level of the pins. When reading the GPIOD feature that removes external offset errors (CHOP = register, the data returned is the level of the pins, 1). whether they are programmed as inputs or outputs. As inputs, a write to the GPIOD has no effect. As With external chopping enabled, the converter takes outputs,awritetotheGPIODsetstheoutputvalue. tworeadingsinsuccessiononthesamechannel.The first reading is taken with one polarity and the second During Standby and Power-Down modes, the GPIO reading is taken with the opposite polarity. The remains active. If configured as inputs, they must be converter averages the two readings, canceling the driven (do not float). If configured as outputs, they offset,asshowninFigure49.Withchoppingenabled, continue to drive the pins. The GPIO pins are set as the effective reading is reduced to half of the nominal inputs after power-on or after a reset. Figure 50 readingrate. showstheGPIOportstructure. Multiplexer GPIOData(read) (chopping) MUXOUTP ADCINP AINn GPIOPin Optional Signal ADC GPIOData(write) Conditioning AINn MUXOUTN ADCINN GPIOControl Figure49. ExternalChopping Figure50. GPIOPortPin Note that since the inputs are reversed under control of the ADS1258, a delay time may be necessary to provide time for external signal conditioning to fully POWER-DOWN INPUT (PWDN) settle before the second phase of the reading sequencestarts(seetheSwitchtimeDelaysection). The PWDN pin is used to control the power-down mode of the converter. In power-down mode, all External chopping can be used to significantly reduce internal circuitry is deactivated including the oscillator total offset errors (to less than 10μV) and offset drift and the clock output. Hold PWDN low for at least two over temperature (to less than 0.2μV/°C). Note that f cycles to engage power-down. The register CLK chopping must be disabled (CHOP = 0) to take the settings are retained during power-down. When the internalmonitorreadings. pin is returned high, the converter requires a wake-up time before readings can be taken, as shown in the Power-Up Timing section. Note that in power-down mode, the inputs of the ADS1258 must still be driven andthedevicecontinuestodrivetheoutputs. 24 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 POWER-UP TIMING Table7.Wake-UpTimes When powering up the device or taking the PWDN tWAKE pin high to wake the device, a wake-up time is INTERNAL tWAKE CONDITION OSCILLATOR(1) EXTERNALCLOCK required before readings can be taken. When using the internal oscillator, the wake-up time is composed PWDNorCLKSEL tOSC 2/fCLK of the oscillator start-up time and the PLL lock time, AVDD–AVSS tOSC+218/fCLK 218/fCLK and if the supplies are also being powered, there is a reset interval time of 218 fCLK cycles. Note that CLKIO POWER-UP SEQUENCE is not valid during the wake-up period, as shown in Figure51. The analog and digital supplies should be applied beforeanyanalogordigitalinputisdriven.Thepower suppliesmaybesequencedinanyorder.Theinternal CLKIO t master reset signal is generated from the analog WAKE power supply (AVDD – AVSS), when the level reaches approximately 3.2 V. The power-up master reset signal is functionally the same as the Reset PWDN CommandandtheRESETinputpin. or ResetInput(RESET) CLKSEL When RESET is held low for at least two f cycles, CLK all registers are reset to their default values and the or digital filter is cleared. When RESET is released high, AVDD- AVSS(1) thedeviceisreadytoconvertdata. DeviceReady 3.2V,typical ClockSelectInput(CLKSEL) NOTE:(1)ShownwithDVDDstable. This pin selects the source of the system clock: the crystal oscillator or an external clock. Tie CLKSEL Figure51. DeviceWakeTimewith InternalOscillator low to select the crystal oscillator. When using an external clock (applied to the CLKIO pin), tie CLKSEL high. When using the device with an external clock, the wake-up time is 2/f periods when waking up with CLK ClockInput/Output(CLKIO) the PWDN pin and 218/f periods when powering CLK the supplies, all after a valid CLKIO is applied, as Thispinserveseitherasaclockoutputorclockinput, showninFigure52. depending on the state of the CLKSEL pin. When using an external clock, apply the clock to this pin and set the CLKSEL pin high. When using the t internal oscillator, this pin has the option of providing WAKE a clock output. The CLKENB bit of register CONFIG0 CLKIO enablestheclockoutput(defaultisenabled). StartInput(START) PWDN, CLKSEL The START pin is an input that controls the ADC process. When the START pin is taken high, the or converter starts converting the selected input channels. When the START pin is taken low, the AVDD- AVSS(1) DeviceReady 3.2V,typical conversion in progress runs to completion and the converter is stopped. The device then enters one of NOTE:(1)ShownwithDVDDstable. the two idle modes (see the Idle Modes section for more details). See the Conversion Control section for detailsofusingtheSTARTpin. Figure52. DeviceWakeTimewithExternalClock Table 7 summarizes the wake-up times using the internaloscillatorandtheexternalclockoperations. (1) Wake-uptimesfortheinternaloscillatoroperationaretypical andmayvarydependingoncrystalcharacteristicsandlayout capacitance.Theusershouldverifytheoscillatorstart-up times(t =oscillatorstart-uptime). OSC Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com DataReadyOutput(DRDY) DRDY is usually connected to an interrupt of a controller, DSP, or connected to a controller port pin The DRDY pin is an output that asserts low to for polling in a software loop. Channel data can be indicate when new channel data is available to read read without the use of DRDY. Read the data using (the previous conversion data is lost). DRDY returns the register format read and check the Status Byte high after the first falling edge of SCLK during a data when the NEW bit = 1, which indicates new channel read operation. If the data is not read (no SCLK data. pulses), DRDY remains low until new channel data is available once again. DRDY then pulses high, then OutputDataScalingandOver-Range lowtoindicatenewdataisavailable;seeFigure53. The ADS1258 is scaled such that the output data code resulting from an input voltage equal to ±V REF DRDY has a margin of 6.6% before clipping. This architecture allows operation of applied input signals atornearfull-scalewithoutoverloadingtheconverter. SCLK Specifically,thedeviceiscalibratedsothat: DRDYwithSCLK 1LSB=V /780000h, REF andtheoutputclipswhen: t DRDYPLS DRDY |VIN|≥1.06× VREF. Table 8 summarizes the ideal output codes versus inputsignals. SCLK DRDYwithoutSCLK 1 t = DRDYPLS f CLK Figure53. DRDYTiming (SeeFigure2fortheDRDYPulse) Table8.IdealOutputCodevsInputSignal INPUTSIGNALV IN (ADCINP–ADCINN) IDEALOUTPUTCODE(1) DESCRIPTION ≥+1.06V 7FFFFFh MaximumPositiveFull-ScaleBeforeOutputClipping REF +V 780000h V =+V REF IN REF +1.06V /(223 –1) 000001h +1LSB REF 0 000000h BipolarZero –1.06V /(223 –1) FFFFFFh –1LSB REF –V 87FFFFh V =–V REF IN REF ≤ –1.06V ×(223/223 –1) 800000h MaximumNegativeFull-ScaleBeforeOutputClipping REF (1) Excludeseffectsofnoise,linearity,offset,andgainerrors. 26 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 INTERNAL SYSTEM READINGS The scale factor of Equation 9 converts the code valuetoexternalreferencevoltage: AnalogPower-SupplyReading(VCC) ExternalReference(V)(cid:1) Code The analog power-supply voltage of the ADS1258 786432 (9) can be monitored by reading the VCC register. The This readback function can be used to check for supply voltage is routed internal to the ADS1258 and missing or an out-of-range reference. If the reference is measured and scaled using an internal reference. input pins are floating (not connected), internal The supply readback channel outputs the difference biasing pulls them to the AVSS supply. This causes between AVDD and AVSS (AVDD – AVSS), for both the output code to tend toward '0'. Bypass capacitors single and dual configurations. Note that it is required connected to the external reference pins may slow to disable chopping (CHOP = 0) prior to taking this the response of the pins when open. When reading reading. this register immediately after power-on, verify that The scale factor of Equation 7 converts the code the reference has settled to ensure an accurate valuetovolts: reading. Note that it is required to disable chopping (CHOP=0)priortotakingthisreading. TotalAnalogSupplyVoltage(V)(cid:1) Code 786432 (7) TemperatureReading(TEMP) When the power supply falls below the minimum The ADS1258 contains an on-chip temperature specified operating voltage, the full operation of the sensor. This sensor uses two internal diodes with one ADS1258 cannot be ensured. Note that when the diode having a current density of 16x of the other. total analog supply voltage falls to below The difference in current densities of the diodes approximately 4.3 V the returned data is set to zero. yields a difference voltage that is proportional to The SUPPLY bit in the status byte is then set. The bit absolutetemperature. is cleared when the total supply voltage rises approximately50mVhigherthanthelowertrippoint. As a result of the low thermal resistance of the package to the printed circuit board (PCB), the The digital supply (DVDD) may be monitored by internal device temperature tracks the PCB looping-back the supply voltage to an input channel. temperature closely. Note also that self-heating of the A resistor divider may be required for bipolar supply ADS1258 causes a higher reading than the operation to reduce the DVDD level to within the temperature of the surrounding PCB. Note that it is rangeoftheanalogsupply. required to disable chopping (CHOP = 0) prior to takingthisreading. GainReading(GAIN) The scale factor of Equation 10 converts the In this configuration, the external reference is temperature reading to °C. Before using the equation, connected both to the analog input and to the the temperature reading code must first be scaled to reference input of the ADC. The data from this μV. registerindicatesthegainofthedevice. Temp Reading(mV)-168,000mV The following scale factor (Equation 8) converts the Temperature(°C) = + 25°C Temp Sensor Coefficient codevaluetodevicegain: Code (10) DeviceGain(cid:3)V(cid:2)V(cid:4)(cid:1) 7864320 (8) Where Temp Sensor Coefficient = 563µV/°C (if the To correct the device gain error, the user software ADS1258 and test PCB temperatures are forced can divide each converter data value by the device together), or 394µV/°C (if only the ADS1258 gain. Note that this corrects only for gain errors temperatureisforcedandthetestPCBisinfree-air). originating within the ADC; system gain errors becauseofanexternalgainstageerrororbecauseof OffsetReading(OFFSET) reference errors are not compensated. Note that it is The differential output of the multiplexer is shorted required to disable chopping (CHOP = 0) also prior to together and set to a common-mode voltage of takingthisreading. (AVDD – AVSS)/2. Ideally, the code from this register function is 0h, but varies because of the noise of the ReferenceReading(REF) ADC and offsets stemming from the ADC and In this configuration, the external reference is externalsignalconditioning.Thisregistercanbeused connected to the analog input and an internal to calibrate or track the offset of the ADS1258 and reference is connected to the reference of the ADC. external signal conditioning. The chop feature of the The data from this register indicates the magnitude of ADC can automatically remove offset and offset drift theexternalreferencevoltage. fromtheexternalsignalconditioning;seetheExternal Choppingsection. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com CONVERSION CONTROL PulseConvertCommand The conversions of the ADS1258 are controlled by Figure55alsoshowsthestartofconversionswiththe the START pin. Conversions begin when the START rising edge of the START pin. If the START pin is pin is taken high and conversions are stopped when taken high, and then low prior to completion of the the START pin is taken low. For continuous conversion cycle (8 τ before DRDY asserts low), CLK conversions, tie the START pin high. The START pin only the current channel is converted and the device can also be tied low and the conversions controlled enters the standby or sleep modes waiting for a new by the PULSE convert command. The PULSE start condition. Figure 56 shows the START pin to convert command converts one channel (only) for DRDY timing. The same function of conversion each command sent. In this way, channel control is possible using the Pulse Convert command conversions can be stepped without the need to (with the START pin low). In this operation, the data toggletheSTARTpin. from one channel is converted with each Pulse Convert command. The Pulse convert command STARTPin takes effect when the command byte is completely shifted in (eighth falling edge of SCLK). After As shown in Figure 54, when the START pin is taken conversion, if more than one channel is enabled high, conversions start beginning with the current (Auto-Scan mode), the converter indexes to the next channel. The device continues to convert all of the selectedchannelaftercompletingtheconversion. programmed channels, in a continuous loop, until the START pin is taken low. When this occurs, the conversion in process completes, and the device DataReady,IndextoNextChannel enters the standby or sleep mode waiting for a new start condition. When DRDY asserts low, the Converting Idle Converting conversion data is ready. Figure 56 shows the DRDY START pin to DRDY timing. The order in which channel data is converted is described in Table 10. STARTPin When the last selected channel in the program list or has been converted, the device continues conversions starting with the highest priority channel. PulseConvert If there is only one channel selected in the Auto-Scan Command mode, the converter remains fixed on one channel. A Figure55. PulseConversion,Auto-ScanMode write operation to any of the multiplexer channel select registers sets the channel pointer to the highest priority channel (see Table 11). In Fixed-Channel mode, the channel pointer remains DRDY tSDSU fixed. t DRHD START Pin DataReady,IndextoNextChannel SYMBOL DESCRIPTION MIN UNIT IdleMode Converting Idle DRDY tSDSU StoT HAaRlTt F tuorDthRerD CYoSnevteurps ioTnimse 8 tCLK STARTPin tDRHD DtoR CDoYmtpol eSteT ACRuTrr eHnotl dC oTnimveersion 8 tCLK Figure56. STARTPinandDRDYTiming Figure54. ConversionControl,Auto-ScanMode 28 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 GPIOLinkedSTARTPinControl OPERATING MODES The START pin can be contolled directly by software The operating modes of the ADS1258 are defined in by connecting externally a GPIO port pin to the three basic states: Converting Mode, Idle Mode, and START pin. (Note that an external pull-down resistor Power-Down mode. In Converting mode, the device is recommended to keep the GPIO from floating until is actively converting channel data. The device power the GPIO is configured as an output). For this mode dissipation is the highest in this mode. This mode is of control, the START pin is effectively controlled by divided into two sub-modes: Auto-Scan and writing to the GPIO Data Register (GPIOD), with the Fixed-Channel. write operation setting or resetting the appropriate bit. The next mode is the Idle mode. In this mode, the The data takes effect on the eighth falling edge of the device is not converting channel data. The device data byte write. The START pin can then be remains active, waiting for input to start conversions. controlledbytheserialinterface. The power consumption is reduced from that of the Converting mode. This mode also has two InitialDelay sub-modes:StandbyandSleep. As seen in Figure 57, when a start convert condition The last mode is Power-Down mode. In this mode, all occurs, the first reading from ADS1258 is delayed for functions of the converter are disabled to reduce a number of clock cycles. This delay allows fully powerconsumptiontoaminimum. settled data to occur at the first data read. Data reads thereafter are available at the full data rate. The CONVERTINGMODES number of clock cycles delayed before the first reading is valid depends on the data rate setting, and The ADS1258 has two converting modes: Auto-Scan whether exiting the Standby or Sleep Mode. Table 9 and Fixed-Channel. In Auto-Scan mode, the channels liststhedelayedclockcyclesversusdatarate. to be measured are pre-selected in the address registersettings.Whenaconvertconditionispresent, the converter automatically measures and sequences Fully−SettledData through the channels either in a continuous loop or pulse-step fashion, depending on the trigger condition. DRDY In Fixed-Channel mode, the channel address is selected in the address register settings prior to InitialDelay acquiring channel data. When a convert condition is Start present, the device converts a single channel, either Condition continuously or in pulse-step fashion, depending on the trigger condition. The data rate in this mode is higher than in Auto-Scan Mode since the input Figure57. StartConditiontoFirstData channelsarenotindexedforeachreading. The selection of converting modes is set with bit MUXMODofregisterCONFIG0. Table9. StartConditiontoDRDYDelay,Chop=0,DLY[2:0]=000 INITIALDELAY(StandbyMode) INITIALDELAY(SleepMode) (f cycles) (f cycles) CLK CLK DRATE[1:0] Fixed-Channel Auto-Scan Fixed-Channel Auto-Scan 11 802 708 866 772 10 1186 1092 1250 1156 01 2722 2628 2786 2692 00 8866 8772 8930 8836 Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com Auto-ScanMode register prior to converting a different channel. Note that the AINCOM input and the internal system The ADS1258 provides 16 analog inputs, which can registerscannotbereferencedinthismode. be configured in combinations of eight differential inputs or 16 single-ended inputs, and provides an IdleModes additional five internal system measurements. Taken together, the device allows a total of 29 possible When the START pin is taken low, the device channel combinations. The converter automatically completes the conversion of the current channel and scans and measures the selected channels, either in then enters one of the Idle modes, Standby or Sleep. a continuous loop or pulse-step fashion, under the In the Standby mode, the internal biasing of the control of the START pin or Start command software. converter is reduced. This state provides the fastest The channels are selected for measurement in wake-up response when re-entering the run state. In registers MUXDIF, MUXSG0, MUXSG1, and Sleep mode, the internal biasing is reduced further to SYSRED. When any of these registers are written, provide lower power consumption than the Standby the internal channel pointer is set to the channel mode. This mode has a slower wake-up response addresswiththehighestpriority(seeTable11). when re-entering the Converting mode (see Table 9). Selection of these modes is set under bit IDLMOD of DRDY asserts low when the channel data is ready; registerCONFIG1. see Figure 55 and Figure 54. At the same time, the converter indexes to the next selected channel and, if POWER-DOWN MODE the START pin is high, starts a new channel conversion. Otherwise, if pulse converting, the device In power-down mode, both the analog and digital enterstheIdlemode. circuitryarecompletelydisabled. For example, if channels 3, 4, 7, and 8 are selected SERIAL INTERFACE for measurement in the list, the ADS1258 converts the channels in that order, skipping all other The ADS1258 is operated via an SPI-compatible channels. After channel 8 is converted, the device serial interface by writing data to the configuration starts over, beginning at the top of the channel list, registers, using commands to control the converter channel3. and finally reading back the channel data. The The following guidelines can be used when selecting interface consists of four signals: CS, SCLK, DIN, inputchannelsforAuto-Scanmeasurement: andDOUT. 1. For differential measurements, adjacent input ChipSelect(CS) pins (AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, etc.) are pre-set as differential pairs. Even number CS is an input that is used to select the device for channels from each pair represent the positive serial communication. CS is active low. When CS is inputtotheADCandoddnumberchannelswithin high,readorwritecommandsinprogressareaborted a pair represent the negative input (for example, and the serial interface is reset. Additionally, DOUT AIN0/AIN1: AIN0 is the positive channel, AIN1 is tri-states and inputs on DIN are ignored. DRDY thenegativechannel.) indicateswhendataisready,independentofCS. 2. For single-ended measurements use AIN0 The converter may be operated using CS to actively through AIN15 as single-ended inputs and select and deselect the device, or with CS tied low AINCOM is the shared common input among (always selected). CS must stay low for the entire them. Note: AINCOM does not need to be at read or write operation. When operating with CS tied ground potential. For example, AINCOM can be low, the number of SCLK pulses must be carefully tied to VREFP or VREFN; or any potential controlledtoavoidfalsecommandtransmission. between(AVSS–100mV)and(AVDD+100mV). 3. Combinations of differential, single-ended inputs, SerialClock(SCLK)Operation and internal system registers can be used in a The serial clock (SCLK) is an input which is used to scan. clock data into (DIN) and out of (DOUT) the ADS1258. This input is a Schmitt-trigger input that Fixed-ChannelMode has a high degree of noise immunity. However, it is In this mode, any of the 16 analog input channels recommended to keep SCLK as clean as possible to (AIN0–AIN15) can be selected for the positive ADC prevent glitches from inadvertently shifting the data. input and any analog input channels can be selected Data is shifted into DIN on the rising edge of SCLK for the negative ADC input. New channel and data is shifted out of DOUT on the falling edge of configurations must be selected by the MUXSCH SCLK. If SCLK is held inactive for 4096 or 256 f CLK cycles (SPIRST bit of register CONFIG0), read or 30 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 write operations in progress will terminate and the may be read at any time without concern to DRDY. SPI interface resets. This timeout feature can be The NEW bit of the STATUS byte indicates that the used to recover lost communication when a serial data register has been refreshed with new converter interface transmission is interrupted or inadvertently data since the last read operation. The data is shifted glitched. outMSBfirstaftertheSTATUSbyte. It should be noted that on system power-up, if the DataInput(DIN)andDataOutput(DOUT) ADS1258 interface signals are floating or undefined, Operation the interface could wake in an unknown state. This The data input pin (DIN) is used to input data to the condition is remedied by resetting the interface in ADS1258. The data output pin (DOUT) is used to three ways: toggle the RESET pin low then high; outputdatafromtheADS1258.DataonDINisshifted toggle the CS pin high then low; or hold SCLK into the converter on the rising edge of SCLK while inactivefor218+4096f cycles. CLK data is shifted out on DOUT on the falling edge of SCLK. DOUT is tri-stated when CS is high to allow ChannelDataReadDirect multipledevicestosharetheline. Channel data can be accessed from the ADS1258 in two ways: Direct data read or data read with register SPIBusSharing format. With Direct read, the DIN input pin is held TheADS1258canbeconnectedtoasharedSPIbus. inactive (high or low) for at least the first three SCLK DOUT tri-states when CS is deselected (high). When transitions. When the first three bits are 000 or 111, the ADS1258 is connected to a shared bus, data can the device detects a direct data read and channel be read only by the Channel Data Read command data is output. After the device defects this read format. format, commands are ignored until either CS is toggled, an SPI timeout occurs or the device is reset. COMMUNICATION PROTOCOL The Channel Data Read command does not have thisrequirement. CommunicatingtotheADS1258involvesshiftingdata into the device (via the DIN pin) or shifting data out of Concurrent with the first SCLK transition, channel the device (via the DOUT pin) under control of the data is output on the DOUT output pin. A total of 24 SCLKinput. or 32 SCLK transitions complete the data read operation. The number of shifts depend on whether ReadingDATA the status byte is enabled. The data must be completely shifted out before the next occurrence of DRDY goes low to indicate that new conversion data DRDY or the remaining data will be corrupted. It is is ready. The data may be read via a direct data read recommended to monitor DRDY to synchronize the (Channel Data Read Direct) or the data may be read start of the read operation to avoid data corruption. in a register format (Channel Data Read Register). A BeforeDRDYassertslow,theMSBoftheStatusbyte direct data read requires the data to be read before or the MSB of the data is output on DOUT (CS = '0'), the next occurrence of DRDY or the data will be as shown in Figure 58. In this format, reading the corrupted. This type of data read requires data a second time within the same DRDY frame synchronization with DRDY to avoid this conflict. returnsdata=0. When reading data in the register format, the data DRDY CS (3) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SCLK DOUT Status Byte(1) Data Byte 1 (MSB) Data Byte 3 (MSB) DIN (2) (hold inactive) NOTES:(1) Optional for Auto-Scan mode, disabled for Fixed-Channel mode. See Table 13, Status Byte. (2) After the channel data read operation,CSmust be toggled or an SPI timeout must occur before sending commands. (3) No SCLK activity. Figure58. ChannelDataReadDirect(NoCommand) Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com COMMAND DESCRIPTION SCLK falling edge (command byte completed), the MSB of the channel data is restarted on DOUT. The CommandsmaybesenttotheADS1258withCStied user clocks the data on the following rising edge of low. However, after the Channel Data Read Direct SCLK. A total of 40 SCLK transitions complete the operation, it is necessary to toggle CS or an SPI data read operation. Unlike the direct read mode, the timeout must occur to reset the interface before channel data can be read during a DRDY transition sendingacommand. without data corruption. This mode is recommended when DRDY is not used and the data is polled to ChannelDataReadCommand detect for the occurrence of new data or when CS is To read channel data in this mode (register format), tied low to avoid the necessity for an SPI timeout that the first three bits of the command byte to be shifted otherwise occurs when reading data directly. This into the device are 001. The MUL bit must be set option avoids conflicts with DRDY, as shown in because this command is a multiple byte read. The Figure59. remaining bits are don’t care but still must be clocked to the device. During this time, ignore any data that appear on DOUT until the command completes. This data should be ignored. Beginning with the eighth CS 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SCLK DIN CommandByte1 Don’tCare Don’tCare(1) DOUT Don’tCare Data(2) Data(2) NOTE:(1)Aftertheprescribednumberofregistersareread,thenoneormoreadditionalcommandscanbeissuedinsuccession. (2)Fourbytesforchanneldataregisterread.SeeTable13,StatusByte.Oneormorebytesforregisterdataread,dependingonMULbit. Figure59. RegisterandChannelData(RegisterFormat)Read 32 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 RegisterReadCommand Beginning with the eighth SCLK rising edge (command byte completed), the MSB of the data is To read register data, the first three bits of the shifted in. The remaining seven SCLK rising edges command byte to be shifted into the device are 010. complete the write to a single register. If MUL = '1', These bits are followed by the multiple register read the data to the next register can be written by bit (MUL). If MUL = '1', then multiple registers can be supplyingadditionalSCLKs.Theoperationterminates read in sequence beyond the desired register. If when the last register is accessed (address = 09h), MUL = '0', only data from the addressed register can asshowninFigure60. be read. The last four bits of the command word are the beginning register address bits. During this time, CONTROL COMMANDS the invalid data may appear on DOUT until the command is completed. This data should be ignored. PulseConvertCommand Beginning with the eighth falling edge of SCLK (command byte completed), the MSB of the register (SeeConversionControlsection) data is output on DOUT. The remaining eight SCLK transitions complete the read of a single register. If ResetCommand MUL = '1', the data from the next register can be read in sequence by supplying additional SCLKs. The The Reset command resets the ADC. All registers operation terminates when the last register is are reset to their default values. A conversion in accessed(address=09h);seeFigure59. process continues but is invalid when completed (DRDY low). This conversion data should be RegisterWriteCommand discarded. Note that the SPI interface may require reset for this command, or any command, to function. To write register data, the first three bits of the To ensure device reset under a possible locked SPI command byte to be shifted into the device are 011. interface condition, do one of the following: 1) toggle These bits are followed by the multiple register read CS high then low and send the reset command; or 2) bit (MUL). If MUL = '1', then multiple registers can be hold SCLK inactive for 256/f or 4096/f and send CLK CLK written in sequence beyond the desired register. If the reset command. The control commands are MUL = '0', only data to the addressed register can be illustratedinFigure61. written. The remaining four bits of the command word are the beginning register address bits. During this time, the invalid data may appear on DOUT until the commandiscompleted.Thisdatashouldbeignored. CS 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SCLK DIN CommandByte RegisterData(1) RegisterData(1)(2) NOTE:(1)OneormorebytesdependingonMULbit. (2)Aftertheprescribednumberofregistersareread,thenoneormoreadditionalcommandscanbeissuedinsuccession. Figure60. RegisterWriteOperation CS 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SCLK DIN Command1 Command2(1) Command3(1) NOTE:(1)Oneormorecommandscanbeissuedinsuccession. Figure61. ControlCommandOperation Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com CHANNEL DATA Thedatareadoperationoutputseitherfourbytes(onebyteforstatusandthreebytesfordata),orthreebytesfor data only. The selection of 4-byte or 3-byte data read is set by the bit STAT in register CONFIG0 (see Table 13, Status Byte, for options). In the 4-byte read, the first byte is the status byte and the following three bytes are the databytes.TheMSB(Data23)ofthedataisshiftedoutfirst. Table10.CHANNELDATAFORMAT BYTE BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 1 STATUS NEW OVF SUPPLY CHID4 CHID3 CHID2 CHID1 CHID0 2 MSB Data23 Data22 Data21 Data20 Data19 Data18 Data17 Data16 3 MSB-1 Data15 Data14 Data13 Data12 Data11 Data10 Data9 Data8 4 LSB Data7 Data6 Data5 Data4 Data3 Data2 Data1 Data0 STATUSBYTE BITSTATUS.7,NEW The NEW bit is set when the results of a Channel Data Read Command returns new channel data. The bit remains set indefinitely until the channel data is read. When the channel data is read again before the converter updates with new data, the previous data is output and the NEW bit is cleared. If the channel data is not read before the next conversion update, the data from the previous conversion is lost. As shown in Figure 62, the NEW bit emulates the operation of the DRDY output pin. To emulate the function of the DRDY output pin in software, the user reads data at a rate faster than the converter's data rate. The user then polls the NEW bit to detectfornewchanneldata. 0=Channeldatahasnotbeenupdatedsincethelastreadoperation. 1=Channeldatahasbeenupdatedsincethelastreadoperation. DRDY NEWBit DataReads (registerformat) Figure62. NEWBitOperation BITSTATUS.6OVF When this bit is set, this indicates the differential voltage applied to the ADC inputs have exceeded the range of the converter |V | > 1.06 V . During over-range, the output code of the converter clips to either positive FS IN REF (V ≥ 1.06 × V ) or negative FS (V ≤ –1.06 × V ). This bit, with the MSB of the data, can be used to IN REF IN REF detect positive or negative over-range conditions. Note that because of averaging incorporated within the digital filter, the absence of this bit does not assure that the modulator of the ADC has not saturated due to possible transientinputoverloadconditions. BITSTATUS.5SUPPLY This bit indicates that the analog power-supply voltage (AVDD – AVSS) is below a preset limit. The SUPPLY bit is set when the value falls below 4.3 V (typically) and is reset when the value rises 50mV higher (typically) than thelowertrippoint.TheoutputdataoftheADCmaynotbevalidunderlowpower-supplyconditions. BITSCHID[4:0]CHANNELIDBITS The Channel ID bits indicate the measurement channel of the acquired data. Note that for Fixed-Channel mode, the Channel ID bits are undefined. See Table 11 for the channel ID, the measurement priority, and the channel descriptionforAuto-ScanMode. 34 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 BITSDATA[23:0]OFDATABYTES The ADC output data are 24 bits wide (DATA[23:0]). DATA23 is the most significant bit (MSB) and DATA0 is the leastsignificantbit(LSB).Thedataiscodedinbinarytwoscomplementformat. Table11.ChannelIDandMeasurementOrder(Auto-ScanMode) BITSCHID[4:0] PRIORITY CHANNEL DESCRIPTION 00h 1(Highest) DIFF0(AIN0–AIN1) Differential0 01h 2 DIFF1(AIN2–AIN3) Differential1 02h 3 DIFF2(AIN4–AIN5) Differential2 03h 4 DIFF3(AIN6–AIN7) Differential3 04h 5 DIFF4(AIN8–AIN9) Differential4 05h 6 DIFF5(AIN10–AIN11) Differential5 06h 7 DIFF6(AIN12–AIN13) Differential6 07h 8 DIFF7(AIN14–AIN15) Differential7 08h 9 AIN0 Single-Ended0 09h 10 AIN1 Single-Ended1 0Ah 11 AIN2 Single-Ended2 0Bh 12 AIN3 Single-Ended3 0Ch 13 AIN4 Single-Ended4 0Dh 14 AIN5 Single-Ended5 0Eh 15 AIN6 Single-Ended6 0Fh 16 AIN7 Single-Ended7 10h 17 AIN8 Single-Ended8 11h 18 AIN9 Single-Ended9 12h 19 AIN10 Single-Ended10 13h 20 AIN11 Single-Ended11 14h 21 AIN12 Single-Ended12 15h 22 AIN13 Single-Ended13 16h 23 AIN14 Single-Ended14 17h 24 AIN15 Single-Ended15 18h 25 OFFSET OFFSET 1Ah 26 VCC AVDD–AVSSSupplies 1Bh 27 TEMP Temperature 1Ch 28 GAIN Gain 1Dh 29(Lowest) REF ExternalReference Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com COMMAND AND REGISTER DEFINITIONS Commands are used to read channel data, access the configuration registers, and control the conversion process. If the command is a register read or write operation, one or more data bytes follow the command byte. If bit MUL = 1 in the command byte, then multiple registers can be read or written in one command operation (see the MUL bit). Commands can be sent back-to-back without toggling CS; however, after a channel Data Read Direct operation, CS must be toggled or an SPI timeout must occur before sending a command. The data readbycommanddoesnotrequireCStobetoggled. The command byte consists of three fields: the Command Bits(C[2:0]), multiple register access bit (MUL), and theRegisterAddressBits(A[3:0]);seetheCommandByteregister. CommandByte 7 6 5 4 3 2 1 0 C2 C1 C0 MUL A3 A2 A1 A0 BitsC[2:0]—CommandBits Thesebitscodethecommandwithinthecommandbyte. C[2:0] DESCRIPTION COMMENTS 000 ChannelDataReadDirect(nocommand) ToggleCSorallowSPItimeoutbeforesendingcommand 001 ChannelDataReadCommand(registerformat) SetMUL=1;statusbytealwaysincludedindata 010 RegisterReadCommand 011 RegisterWriteCommand 100 PulseConvertCommand MUL,A[3:0]aredon'tcare 101 Reserved 110 ResetCommand MUL,A[3:0]don'tcare 111 ChannelDataReadDirect(nocommand) ToggleCSorallowSPItimeoutbeforesendingcommand Bit4MUL:MultipleRegisterAccess 0=DisableMultipleRegisterAccess 1=EnableMultipleRegisterAccess This bit enables the multiple register access. This option allows writing or reading more than one register in a single command operation. If only one register is to be read or written, set MUL = '0'. For multiple register access, set MUL = '1'. The read or write operation begins at the addressed register. The ADS1258 automatically increments the register address for each register data byte subsequently read or written. The multiple register readorwriteoperationscompleteafterregisteraddress=09h(deviceIDregister)hasbeenaccessed. Themultipleregisteraccessisterminatedinoneofthreeways: 1. TheusertakesCShigh.ThisactionresetstheSPIinterface. 2. TheuserholdsSCLKinactivefor4096f cycles.ThisactionresetstheSPIinterface. CLK 3. Register address = 09h has been accessed. This completes the command and the ADS1258 is then ready for a new command. Note for the Channel Data Read command, this bit must be set to read the four data bytes(onestatusbyteandthreedatabytes). A[3:0]RegisterAddressBits Thesebitsaretheregisteraddressesforaregisterreadorwriteoperation;seeTable12. 36 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 REGISTERS Table12.RegisterMap ADDRESS REGISTER DEFAULT BitsA[3:0] NAME VALUE BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 00h CONFIG0 0Ah 0 SPIRST MUXMOD BYPAS CLKENB CHOP STAT 0 01h CONFIG1 83h IDLMOD DLY2 DLY1 DLY0 SBCS1 SBCS0 DRATE1 DRATE0 02h MUXSCH 00h AINP3 AINP2 AINP1 AINP0 AINN3 AINN2 AINN1 AINN0 03h MUXDIF 00h DIFF7 DIFF6 DIFF5 DIFF4 DIFF3 DIFF2 DIFF1 DIFF0 04h MUXSG0 FFh AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 05h MUXSG1 FFh AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8 06h SYSRED 00h 0 0 REF GAIN TEMP VCC 0 OFFSET 07h GPIOC FFh CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0 08h GPIOD 00h DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 09h ID 8Bh ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 CONFIG0:CONFIGURATIONREGISTER0(Address=00h) 7 6 5 4 3 2 1 0 0 SPIRST MUXMOD BYPAS CLKENB CHOP STAT 0 Default=0Ah. Bit7 Mustbe0(default) Bit6 SPIRSTSPIInterfaceResetTimer Thisbitsetsthenumberoff cyclesinwhichSCLKisinactivetheSPIinterfacewillreset.This CLK placesalowerlimitonthefrequencyofSCLKinwhichtoreadorwritedatatothedevice.TheSPI interfaceonlyisresetandnotthedeviceitself.WhentheSPIinterfaceisreset,itisreadyforanew command. 0=ResetwhenSCLKinactivefor4096f cycles(256µs,f =16MHz)(default). CLK CLK 1=ResetwhenSCLKinactivefor256f cycles(16µs,f =16MHz). CLK CLK Bit5 MUXMOD ThisbitsetseithertheAuto-ScanorFixed-Channelmodeofoperation. 0=Auto-ScanMode(default) InAuto-Scanmode,theinputchannelselectionsareeightdifferentialchannels(DIFF0–DIFF7)and16 single-endedchannels(AIN0–AIN15).Additionally,fiveinternalmonitorreadingscanbeselected. TheseselectionsaremadeinregistersMUXDIF,MUXSG0,MUXSG1,andSYSRED.Inthismode, settingsinregisterMUXSCHhavenoeffect.SeetheAuto-ScanModesectionformoredetails. 1=Fixed-ChannelMode InFixed-Channelmode,anyoftheanaloginputchannelsmaybeselectedforthepositive measurementandthenegativemeasurementchannels.TheinputsareselectedinregisterMUXSCH. Inthismode,registersMUXDIF,MUXSG0,MUXSG1,andSYSREDhavenoeffect.Notethatitisnot possibletoselecttheinternalmonitorreadingsinthismode. Bit4 BYPAS ThisbitselectseithertheinternalorexternalconnectionfromthemultiplexeroutputtotheADCinput. 0=ADCinputsuseinternalmultiplexerconnection(default). 1=ADCinputsuseexternalADCinputs(ADCINPandADCINN). NotethattheTemperature,V ,Gain,andReferenceinternalmonitorreadingsautomaticallyusethe CC internalconnection,regardlessoftheBYPASsetting.TheOffsetreadingusesthesettingofBYPAS. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com Bit3 CLKENB ThisbitenablestheclockoutputonpinCLKIO.Theclockoutputoriginatesfromthedevicecrystal oscillatorandPLLcircuit. 0=ClockoutputonCLKIOdisabled. 1=ClockoutputonCLKIOenabled(default). Note:IftheCLKSELpinissetto'1',theCLKIOpinisaclockinputonly.Inthiscase,settingthisbit hasnoeffect. Bit2 CHOP Thisbitenablesthechoppingfeatureontheexternalmultiplexerloop. 0=ChoppingDisabled(default) 1=ChoppingEnabled Thechoppingfeaturecorrectsforoffsetoriginatingfromcomponentsusedintheexternalmultiplexer loop;seetheExternalChoppingsection. NotethatforInternalSystemreadings(Temperature,VCC,Gain,andReference),theCHOPbitmust be0. Bit1 STATStatusByteEnable WhenreadingchanneldatafromtheADS1258,astatusbyteisnormallyincludedwiththeconversion data.However,insomeADS1258operatingmodes,thestatusbytecanbedisabled.Table13,Status Byte,showsthemodesofoperationandthedatareadformatsinwhichthestatusbytecanbe disabled. 0=StatusByteDisabled 1=StatusByteEnabled(default) Table13.StatusByte CHANNELDATA CHANNELDATA MODE READCOMMAND READDIRECT Auto-Scan AlwaysEnabled Enabled/DisabledbySTATBit Fixed-Channel AlwaysEnabled(ByteisUndefined) AlwaysDisabled Bit0 Mustbe0 38 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 CONFIG1:CONFIGURATIONREGISTER1(Address=01h) 7 6 5 4 3 2 1 0 IDLMOD DLY2 DLY1 DLY0 SBCS1 SBCS0 DRATE1 DRATE0 Default=83h. Bit7 IDLMOD ThisbitselectstheIdlemodewhenthedeviceisnotconverting,StandbyorSleep.TheSleepmode offerslowerpowerconsumptionbuthasalongerwake-uptimetore-entertherunmode;seetheIdle Modessection. 0=SelectStandbyMode 1=SelectSleepMode(default) Bits DLY[2:0] 6–4 Thesebitssettheamountoftimetheconverterwilldelayafterindexingtoanewchannelbutbefore startinganewconversion.Thisvalueshouldbesetlargeenoughtoallowforthefullsettlingof externalfilteringorbufferingcircuitsusedbetweentheMUXOUTP,MUXOUTN,andADCINP, ADCINNpins;seetheSwitchTimeDelaysection.(default=000) Bits SBCS[1:0] 3–2 Thesebitssetthesensorbiascurrentsource. 0=SensorBiasCurrentSourceOff(default) 1=1.5µASource 3=24µASource Bits DRATE[1:0] 1–0 Thesebitssetthedatarateoftheconverter.Slowerreadingratesyieldincreasedresolution;see Table4.Theactualdataratesshowninthetablecanbeslower,dependingontheuseofSwitchTime DelayortheChopfeature.SeetheSwitchTimeDelaysection.Thereadingratescaleswiththe masterclockfrequency. DATARATE DATARATE AUTO-SCANMODE FIXED-CHANNELMODE DRATE[1:0] (SPS) (SPS) 11 23739 125000 10 15123 31250 01 6168 7813 00 1831 1953 f =16MHz,Chop=0,Delay=0. CLK Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com MUXSCH:MULTIPLEXERFIXED-CHANNELREGISTER(Address=02h) 7 6 5 4 3 2 1 0 AINP3 AINP2 AINP1 AINP0 AINN3 AINN2 AINN1 AINN0 Default=00h. ThisregisterselectstheinputchannelsofthemultiplexertobeusedfortheFixed-Channelmode.TheMUXMOD bit in register CONFIG0 must be set to '1'. In this mode, bits AINN[3:0] select the analog input channel for the negative ADC input, and bits AINP[3:0] select the analog input channel for the positive ADC input. See the Fixed-ChannelModesection. MUXDIF:MULTIPLEXERDIFFERENTIALINPUTSELECTREGISTER(Address=03h) 7 6 5 4 3 2 1 0 DIFF7 DIFF6 DIFF5 DIFF4 DIFF3 DIFF2 DIFF1 DIFF0 Default=00h. MUXSG0:MULTIPLEXERSINGLE-ENDEDINPUTSELECTREGISTER0(Address=04h) 7 6 5 4 3 2 1 0 AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 Default=FFh. MUXSG1:MULTIPLEXERSINGLE-ENDEDINPUTSELECTREGISTER1(Address=05h) 7 6 5 4 3 2 1 0 AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8 Default=FFh. SYSRED:SYSTEMREADINGSELECTREGISTER(Address=06h) 7 6 5 4 3 2 1 0 0 0 REF GAIN TEMP VCC 0 OFFSET Default=00h. These four registers select the input channels and the internal readings for measurement in Auto-Scan mode. For differential channel selections (DIFF0…DIFF7), adjacent input pins (AIN0/AIN1, AIN2/AIN3, etc.) are pre-set as differential inputs. All single-ended inputs are measured with respect to the AINCOM input. AINCOM may be set to any level within ±100 mV of the analog supply range. Channels not selected are skipped in the measurement sequence. Writing to any of these four registers resets the internal channel pointer to the channel withthehighestpriority(seeTable11).Notethatthebitsindicatedas'0'mustbesetto0. 0=Channelnotselectedwithinareadingsequence. 1=Channelselectedwithinareadingsequence. 40 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 GPIOC:GPIOCONFIGURATIONREGISTER(Address=07h) 7 6 5 4 3 2 1 0 CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0 Default=FFh. ThisregisterconfigurestheGPIOpinsasinputsorasoutputs.Notethatthedefaultconfigurationsoftheport pinsareinputsandassuchtheyshouldnotbeleftfloating.SeetheGPIODigitalPortsection. 0=GPIOisanoutput;1=GPIOisaninput(default). CIO[7:0]GPIOConfiguration bit7 CIO7,DigitalI/OConfigurationBitforPinGPIO7 bit6 CIO6,DigitalI/OConfigurationBitforPinGPIO6 bit5 CIO5,DigitalI/OConfigurationBitforPinGPIO5 bit4 CIO4,DigitalI/OConfigurationBitforPinGPIO4 bit3 CIO3,DigitalI/OConfigurationBitforPinGPIO3 bit2 CIO2,DigitalI/OConfigurationBitforPinGPIO2 bit1 CIO1,DigitalI/OConfigurationBitforPinGPIO1 bit0 CIO0,DigitalI/OConfigurationBitforPinGPIO0 GPIOD:GPIODATAREGISTER(Address=08h) 7 6 5 4 3 2 1 0 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 Default=00h. ThisregisterisusedtoreadandwritedatatotheGPIOportpins.Whenreadingthisregister,thedatareturned correspondstothestateoftheGPIOexternalpins,whethertheyareprogrammedasinputsorasoutputs.As outputs,awritetotheGPIODsetstheoutputvalue.Asinputs,awritetotheGPIODhasnoeffect.Seethe GPIODigitalPortsection. 0=GPIOislogiclow(default);1=GPIOislogichigh. DIO[7:0]GPIOData bit7 DIO7,DigitalI/ODatabitforPinGPIO7 bit6 DIO6,DigitalI/ODatabitforPinGPIO6 bit5 DIO5,DigitalI/ODatabitforPinGPIO5 bit4 DIO4,DigitalI/ODatabitforPinGPIO4 bit3 DIO3,DigitalI/ODatabitforPinGPIO3 bit2 DIO2,DigitalI/ODatabitforPinGPIO2 bit1 DIO1,DigitalI/ODatabitforPinGPIO1 bit0 DIO0,DigitalI/ODatabitforPinGPIO0 ID:DEVICEIDREGISTER(Address=09h) 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Default=8Bh. ID[7:0] IDBits Factory-programmedIDbits.Read-only. ExceptfortheID4bit,theIDbytecanchangeatanytimewithoutnotice. ID4:0=ADS1258,ADS1258-EP(24-BitADCs) ID4:1=ADS1158(16-BitADC) Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com APPLICATIONS HARDWARE CONSIDERATIONS The following summarizes the design and layout AVDD considerationswhenusingtheADS1258: BAT54SWTI a. Power Supplies: The converter accepts a single 10kW +5V supply (AVDD = 5 V and AVSS = AGND) or Input AINx dual, bipolar supplies (typically AVDD = 2.5 V, typ. AVSS = –2.5 V). Dual supply operation accommodates true bipolar input signals, within a AVSS ±2.5-V range. Note that the maximum negative input voltage to the multiplexer is limited to AVSS – 100 mV, and the maximum positive input Figure63. InputOverloadProtection voltage is limited to AVDD + 100 mV. The range for the digital power supply (DVDD) is 2.7 V to d. ADC Inputs: The external multiplexer loop of the 5.25 V. For all supplies, use a 10-μF tantalum ADS1258 allows for the inclusion of signal capacitor, bypassed with a 0.1-μF ceramic conditioningbetweentheoutputofthemultiplexer capacitor, placed close to the device pins. and the input of the ADC. Typically, an amplifier Alternatively, a single 10-μF ceramic capacitor is used to provide gain, buffering, and/or filtering can be used. The supplies should be relatively to the input signal. For best performance, the free from noise and should not be shared with ADC inputs should be driven differentially. A devices that produce voltage spikes (such as differential in/differential out or a relays, LED display drivers, etc.). If a switching single-ended-to-differential driver is recom- power supply is used, the voltage ripple should mended. If the driver uses higher supply voltages be low (< 2 mV). The analog and digital power than the device itself (for example, ±15V), suppliesmaybesequencedinanyorder. attention should be paid to power-supply sequencing and potential over-voltage fault b. Analog (Multiplexer) Inputs: The 16-channel conditions. Protection resistors and/or external analog input multiplexer can accommodate 16 clamp diodes may be used to protect the ADC single-ended inputs, eight differential input pairs, inputs. A 1-nF or higher capacitor should be used or combinations of either. These options permit directlyacrosstheADCinputs. freedom in choosing the input channels. The channels do not have to be used consecutively. e. Reference Inputs: It is recommended to use a Unassigned channels are skipped by the device. 10-μF tantalum with a 0.1-μF ceramic capacitor In the Fixed-Channel mode, any of the analog directly across the reference pins, VREFP and inputs (AIN0 to AIN15) can be addressed for the VREFN. The reference inputs should be driven positive input and for the negative input. The by a low-impedance source. For rated full-scale range of the device is 2.13 V , but the performance,thereferenceshouldhavelessthan REF absoluteanaloginputvoltageislimitedto100mV 3μVRMS broadband noise. For references with beyond the analog supply rails. Input signals higher noise, external filtering may be necessary. exceeding the analog supply rails (for example, Note that when exiting the sleep mode, the ±10 V) must be divided prior to the multiplexer device begins to draw a small current through the inputs. reference pins. Under this condition, the transient response of the reference driver should be fast c. Input Overload Protection: Overdriving the enough to settle completely before the first multiplexer inputs may affect the conversions of reading is taken, or simply discard the first other channels. In the case of input overload, severalreadings. external Schottky diode clamps and series resistor are recommended, as shown in Figure 61. 42 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 f. Clock Source: The ADS1258 requires a clock interface can be operated in a minimum signal for operation. The clock can originate from configuration without the use of CS (tie CS low; either the crystal oscillator or from an external see the Serial Interface and Communication clock source. The internal oscillator uses a PLL Protocolsections). circuit and an external 32.768-kHz crystal to j. GPIO: The ADS1258 has eight, user- generate a 15.7-MHz master clock. The PLL programmable digital I/O pins. These pins are requires a 22-nF capacitor from the PLLCAP pin controlled by register settings. The register to AVSS. The crystal and load capacitors should setting is default to inputs. If these pins are not be placed close to the pins as possible and kept used, tie them high or low (do not float input pins) away from other traces with AC components. A orconfigurethemasoutputs. buffered output of the 15.7-MHz clock can be k. QFNPackage:SeeApplicationReportSLUA271, used to drive other converters or controllers. An QFN/SON PCB Attachment for PCB layout external clock source can be used up to 16 MHz. recommendations, available for download at For best performance, the clock of the SPI www.ti.com. The exposed thermal pad of the interface controller and the converter itself should ADS1258 should be connected electrically to be on the same domain. This configuration AVSS. requiresthattheratiooftheSCLKtodeviceclock mustbelimitedto1,1/2,1/4,1/8,etc. CONFIGURATION GUIDE g. Digital Inputs: It is recommended to source terminate the digital inputs and outputs of the Configuration of the ADS1258 involves setting the device with a 50-Ω (typical) series resistor. The configuration registers via the SPI interface. After the resistors should be placed close to the driving device is configured for operation, channel data is end of the source (output pins, oscillator, logic read from the device through the same SPI interface. gates, DSP, etc). This placement helps to reduce The following is a suggested procedure for theringingandovershootonthedigitallines. configuringthedevice: h. Hardware Pins: START, DRDY, RESET, and 1. Reset the SPI Interface: Before using the SPI PWDN. These pins allow direct pin control of the interface, it may be necessary to recover the SPI ADS1258. The equivalent of the START and interface. To reset the interface, set CS high or DRDY pins is provided via commands through disableSCLKfor4096(256)f cycles. CLK the SPI interface; these pins may be left unused. 2. Stop the Converter: Set the START pin low to The device also has a RESET command. The stop the converter. Although not necessary for PWDN pin places the ADC into very low-power configuration, this command stops the channel state where the device is inactive. scanning sequence which then points to the first i. SPI Interface: The ADS1258 has an channelafterconfiguration. SPI-compatible interface. This interface consists 3. Reset the Converter: The reset pin can be of four signal lines: SCLK, DIN, DOUT, and CS. pulsed low or a Reset command can be sent. When CS is high, the DIN input is ignored and Although not necessary for configuration, reset the DOUT output tri-states. See Chip Select re-initializesthedeviceintoaknownstate. (CS ) for more details. The SPI Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com 4. Configure the Registers: The registers are Convertcommandsentthroughtheinterface. configured by writing to them either sequentially 7. Read Channel Data: The DRDY asserts low or as a group. The user may configure the when data is ready. The channel data can be software in either mode. Any write to the read at that time. If DRDY is not used, the Auto-Scan channel-select registers resets the updated channel data can be checked by reading channelpointertothechannelofhighestpriority. the NEW bit in the status byte. The status byte 5. Verify Register Data: The register data may be also indicates the origin of the channel data. If read back for verification of device the data for a given channel is not read before communications. DRDY asserts low again, the data for that 6. Start the Converter: The converter can be channel is lost and replaced with new channel started with the START pin or with a Pulse data. 44 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 DIGITAL INTERFACE CONNECTIONS The ADS1258 SPI-compatible interface easily ADS1258 TMS320R2811 connects to a wide variety of microcontrollers and DSPs. Figure 64 shows the basic connection to TI's MSP430 family of low-power microcontrollers. DIN SPISIMO Figure 65 shows the connection to microcontrollers with an SPI interface such as the 68HC11 family, or DOUT SPISOMI TI's MSC12xx family. Note that the MSC12xx DRDY XINT1 includes a high-resolution ADC; the ADS1258 can be SCLK SPICLK used to provide additional channels of measurement or add higher-speed connections. Finally, Figure 66 CS(1) SPISTA shows how to connect the ADS1258 to a TMS320x DSP. (1)CSmaybetiedlow. Figure66. ConnectiontoaTMS320R2811DSP ADS1258 MSP430 GPIOConnections DIN P1.3 The ADS1258 has eight general purpose input/output DOUT P1.2 (GPIO) pins. Each pin can be configured as an input or an output. Note that pins configured as inputs DRDY P1.0 should not float. The pins can be used to read key SCLK P1.6 pads, drive LED indicator, etc., by reading and writing theGPIOdataregister(GPIOD).SeeFigure67. CS(1) P1.4 (1)CSmaybetiedlow. 3.3V Figure64. ConnectiontoMSP430Microcontroller 10kW ADS1258 GPIOx (Input) KeyPad ADS1258 MSC12xxor 3.3V 68HC11 LEDIndicator DIN MOSI 470 DOUT MISO 4.7kW GPIOx DRDY INT (Output) SCLK SCK CS(1) IO (1)CSmaybetiedlow. Figure67. GPIOConnections Figure65. ConnectiontoMicrocontrollerswithan SPIInterface Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLink(s):ADS1258-EP

ADS1258-EP SBAS445D–MARCH2009–REVISEDMARCH2011 www.ti.com ANALOG INPUT CONNECTIONS When using Auto-Scan mode to sequence through the channels, the switch time delay feature Figure 68 shows the ADS1258 interfacing to (programmable by registers) can be used to provide high-level ±10V inputs, commonly used in industrial additionalsettlingtimeoftheexternalcomponents. environments.Inthiscase,bipolarpowersuppliesare used, avoiding the need for input signal level-shifting Figure 69 illustrates the ADS1258 interfacing to otherwise required when a single supply is used. The multiple pressure sensors having a resistor bridge input resistors serve both to reduce the level of the output. Each sensor is excited by the 5-V single 10V input signal to within the ADC range and also supply that also powers the ADS1258 and likewise is protecttheinputsfrominadvertentsignalover-voltage used as the ADS1258 reference input; the 6% input up to 30V. The external amplifiers convert the overrange capability accommodates input levels at or single-ended inputs to a fully differential output to above V . The ratiometric connection provides REF drive the ADC inputs. Driving the inputs differentially cancellation of excitation voltage drift and noise. For maintains good linearity performance. The 2.2-nF best performance, the 5-V supply should be free from capacitor at the ADC inputs is required to bypass the glitches or transients. The 5-V supply input amplifiers ADC sampling currents. The 2.5-V reference, (two OPA365s) form a differential input/differential REF3125, is filtered and buffered to provide a outputbufferwiththegainsetto10.Thechopfeature low-noise reference input to the ADC. The chop of the ADS1258 is used to reduce offset and offset feature of the ADC can be used to reduce offset and drift to very low levels. The 2.2-nF capacitor at the offsetdriftoftheamplifiers. ADC inputs is required to bypass the ADC sampling currents. The 47-Ω resistors isolate the op-amp For ±1V input signals, the input resistor divider can outputsfromthefiltercapacitor. be removed and replaced with a series protection resistor. For 20-mA input signals, the input resistor divider is replaced by a 50-Ω resistor, connected from eachinputtoAINCOM. - 2.5V +2.5V + 0.1m F 10m F 10m F 0.1m F + +2.5V +2.5V AVSS AVDD ±10V 9.09kW AIN0 OPA350 100W 10kW REFP REF3125 … 1kW … ADS1258 0.1m F + 10m F - 2.5V + 100m F 0.1m F 0.47m F ±10V 9.019kkWW AAIINN1C5OM MUXOUTN MUXOUTP ADCINP ADCINNREFN - 2.5V NOTE:0.1m Fcapacitorsnotshown. 2.2nF 47W +2.5V 10kW 20mAInput 10kW AINx OPA365 +2.5V 50W 47W - 2.5V OPA365 - 2.5V Figure68. Multichannel,±10VSingle-EndedInput,BipolarSupplyOperation 46 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1258-EP

ADS1258-EP www.ti.com SBAS445D–MARCH2009–REVISEDMARCH2011 +5V RFI + 0.1mF 10mF 2kW RFI AIN0 AVSS AVDD 2kW REFP RFI AIN1 + 10mF 0.1mF ¼ ¼ ¼ REFN 2kW ADS1258 RFI AIN14 2kW N P T T RFI AIN15 OU OU NP NN X X CI CI AINCOM MU MU AD AD RFI +5V 2.2nF 47W OPA365 R 2 10kW R NOTE: G = 1 + 2R2/R1. 2.2kW1 R2 0.1mF supply bypass capacitor not shown. 10kW 47W OPA365 Figure69. BridgeInput,Single-SupplyOperation Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLink(s):ADS1258-EP

PACKAGE OPTION ADDENDUM www.ti.com 5-Aug-2016 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS1258IPHPREP ACTIVE HTQFP PHP 48 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 105 AD1258IEP & no Sb/Br) ADS1258MPHPTEP ACTIVE HTQFP PHP 48 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -55 to 125 AD1258MEP & no Sb/Br) ADS1258MRTCTEP ACTIVE VQFN RTC 48 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -55 to 125 1258MEP & no Sb/Br) V62/09626-01XE ACTIVE VQFN RTC 48 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -55 to 125 1258MEP & no Sb/Br) V62/09626-01YE ACTIVE HTQFP PHP 48 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -55 to 125 AD1258MEP & no Sb/Br) V62/09626-02XE ACTIVE HTQFP PHP 48 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 105 AD1258IEP & no Sb/Br) V62/09626-02YE ACTIVE HTQFP PHP 48 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 105 AD1258IEP & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 5-Aug-2016 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ADS1258-EP : •Catalog: ADS1258 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS1258IPHPREP HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 ADS1258MRTCTEP VQFN RTC 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS1258IPHPREP HTQFP PHP 48 1000 350.0 350.0 43.0 ADS1258MRTCTEP VQFN RTC 48 250 213.0 191.0 55.0 PackMaterials-Page2

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