ADS1245 SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 Low-Power, 24-Bit Analog-to-Digital Converter FEATURES DESCRIPTION (cid:1) 20-Bit Effective Resolution The ADS1245 is a 24-bit, delta-sigma analog-to-digital (cid:1) converter (ADC). It offers excellent performance and very High-Impedance Buffered Input low power in an MSOP-10 package and is well suited for (cid:1) ±2.5V Differential Input Range demanding high-resolution measurements, especially in (cid:1) Pin-Compatible with ADS1244 portable and other space- and power-constrained (cid:1) systems. 0.0006% INL (typ), 0.0015% INL (max) (cid:1) The buffered input presents an impedance of 3GΩ, mini- Simple Two-Wire Serial Interface mizing measurement errors when using high-impedance (cid:1) Simultaneous 50Hz and 60Hz Rejection sources. The ADS1245 is compatible with ADS1244 and (cid:1) Single Conversions with Sleep Mode offers a direct upgrade path for designs requiring higher in- (cid:1) put impedance. Single-Cycle Settling (cid:1) Self-Calibration A third-order delta-sigma (∆Σ) modulator and digital filter (cid:1) form the basis of the ADC. The analog modulator has a Well Suited for Multi-Channel Systems ±2.5V differential input range. The digital filter rejects both (cid:1) Easily Connects to the MSP430 50Hz and 60Hz signals, completely settles in one cycle, (cid:1) Current Consumption: 158µA and outputs data at 15 samples per second (SPS). (cid:1) Analog Supply: 2.5V to 5.25V A simple, two-wire serial interface provides all the (cid:1) necessary control. Data retrieval, self-calibration, and Digital Supply: 1.8V to 3.6V Sleep mode are handled with a few simple waveforms. When only single conversions are needed, the ADS1245 APPLICATIONS can be shut down (Sleep mode) while idle between (cid:1) measurements to dramatically reduce the overall power Hand-Held Instrumentation dissipation. Multiple ADS1245s can be connected (cid:1) Portable Medical Equipment together to create a synchronously sampling multichannel (cid:1) Industrial Process Control measurement system. The ADS1245 is designed to easily (cid:1) connect to microcontrollers, such as the MSP430. Test and Measurement Systems The ADS1245 supports 2.5V to 5.25V analog supplies and 1.8V to 3.6V digital supplies. Power is typically less than 470µW in normal operation and less than 1µW during Sleep mode. VREFP VREFN AVDD DVDD CLK AINP DRDY/DOUT 3rd−Order Digital Serial Buffer Modulator Filter Interface AINN SCLK GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:3)(cid:9) (cid:4)(cid:10)(cid:7)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:16)(cid:17)(cid:18)(cid:11)(cid:14)(cid:12) (cid:11)(cid:19) (cid:20)(cid:21)(cid:15)(cid:15)(cid:22)(cid:12)(cid:18) (cid:17)(cid:19) (cid:14)(cid:13) (cid:23)(cid:21)(cid:24)(cid:25)(cid:11)(cid:20)(cid:17)(cid:18)(cid:11)(cid:14)(cid:12) (cid:26)(cid:17)(cid:18)(cid:22)(cid:27) (cid:1)(cid:15)(cid:14)(cid:26)(cid:21)(cid:20)(cid:18)(cid:19) Copyright  2003, Texas Instruments Incorporated (cid:20)(cid:14)(cid:12)(cid:13)(cid:14)(cid:15)(cid:16) (cid:18)(cid:14) (cid:19)(cid:23)(cid:22)(cid:20)(cid:11)(cid:13)(cid:11)(cid:20)(cid:17)(cid:18)(cid:11)(cid:14)(cid:12)(cid:19) (cid:23)(cid:22)(cid:15) (cid:18)(cid:28)(cid:22) (cid:18)(cid:22)(cid:15)(cid:16)(cid:19) (cid:14)(cid:13) (cid:7)(cid:22)(cid:29)(cid:17)(cid:19) (cid:8)(cid:12)(cid:19)(cid:18)(cid:15)(cid:21)(cid:16)(cid:22)(cid:12)(cid:18)(cid:19) (cid:19)(cid:18)(cid:17)(cid:12)(cid:26)(cid:17)(cid:15)(cid:26) (cid:30)(cid:17)(cid:15)(cid:15)(cid:17)(cid:12)(cid:18)(cid:31)(cid:27) (cid:1)(cid:15)(cid:14)(cid:26)(cid:21)(cid:20)(cid:18)(cid:11)(cid:14)(cid:12) (cid:23)(cid:15)(cid:14)(cid:20)(cid:22)(cid:19)(cid:19)(cid:11)(cid:12)! (cid:26)(cid:14)(cid:22)(cid:19) (cid:12)(cid:14)(cid:18) (cid:12)(cid:22)(cid:20)(cid:22)(cid:19)(cid:19)(cid:17)(cid:15)(cid:11)(cid:25)(cid:31) (cid:11)(cid:12)(cid:20)(cid:25)(cid:21)(cid:26)(cid:22) (cid:18)(cid:22)(cid:19)(cid:18)(cid:11)(cid:12)! (cid:14)(cid:13) (cid:17)(cid:25)(cid:25) (cid:23)(cid:17)(cid:15)(cid:17)(cid:16)(cid:22)(cid:18)(cid:22)(cid:15)(cid:19)(cid:27) www.ti.com

(cid:10)(cid:4)"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 ORDERING INFORMATION SPECIFIED PACKAGE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE−LEAD DESIGNATOR(1) TEMPERATURE MARKING NUMBER MEDIA, QUANTITY RANGE ADS1245IDGST Tape and Reel, 250 AADDSS11224455 MMSSOOPP--1100 DDGGSS −−4400°°CC ttoo ++8855°°CC BBHHII ADS1245IDGSR Tape and Reel, 2500 (1)For the most current specifications and package information, refer to our web site at www.ti.com. PIN ASSIGNMENTS ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) ADS1245 UNIT DGS PACKAGE AVDD to GND −0.3 to +6 V MSOP DVDD to GND −0.3 to +3.6 V (TOP VIEW) Input Current 100, momentary mA ADS1245 Input Current 10, continuous mA Analog Input Voltage to GND −0.5 to AVDD + 0.5 V GND 1 10 CLK Analog Input Voltage to GND −0.3 to DVDD + 0.3 V VREFP 2 9 SCLK Digital Output Voltage to GND −0.3 to DVDD + 0.3 V VREFN 3 8 DRDY/DOUT Maximum Junction Temperature +150 °C AINN 4 7 DVDD Operating Temperature Range −40 to +85 °C AINP 5 6 AVDD Storage Temperature Range −60 to +150 °C Lead Temperature (soldering, 10s) +300 °C (1)Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Terminal Functions TERMINAL This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be NAME NO. DESCRIPTION handled with appropriate precautions. Failure to observe GND 1 Analog and digital ground proper handling and installation procedures can cause damage. VREFP 2 Positive reference input ESD damage can range from subtle performance degradation to VREFN 3 Negative reference input complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could AINN 4 Negative analog input cause the device not to meet its published specifications. AINP 5 Positive analog input AVDD 6 Analog power supply, 2.5V to 5.25V DVDD 7 Digital power supply, 1.8V to 3.6V DRDY/DOUT 8 Dual-purpose output: Data ready: indicates valid data by going low. Data output: outputs data, MSB first, on the first rising edge of SCLK. SCLK 9 Serial clock input: clocks out data on the rising edge. Used to initiate calibration and Sleep mode (see text for more details). CLK 10 System clock input: typically 2.4576MHz 2

(cid:10)(cid:4)"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 ELECTRICAL CHARACTERISTICS All specifications at TA = −40°C to +85°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +1.25V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Input Full-scale input voltage range AINP − AINN ±2VREF V Absolute input range AINP, AINN with respect to GND GND + 0.1 AVDD − 1.25 V Differential input impedance fCLK = 2.4576MHz 3 GΩ System Performance Resolution No missing codes 24 Bits Data rate fCLK = 2.4576MHz 15 SPS(1) Integral nonlinearity (INL) Differential input signal, end point fit ±0.0006 ±0.0015 %FSR(2) Offset error 1 14 ppm of FSR Offset error drift(3) 0.01 ppm of FSR/°C Gain error(4) 0.005 0.1 % Gain error drift(3) 0.5 ppm/°C At DC 90 100 dB CCoommmmoonn--mmooddee rreejjeeccttiioonn fCM(5) = 50 ± 1Hz, fCLK = 2.4576MHz 100 dB fCM = 60 ± 1Hz, fCLK = 2.4576MHz 100 dB fSIG(6) = 50 ± 1Hz, fCLK = 2.4576MHz 60 dB NNoorrmmaall--mmooddee rreejjeeccttiioonn fSIG = 60 ± 1Hz, fCLK = 2.4576MHz 70 dB ppm of FSR, Input referred noise 2 RMS Analog power-supply rejection At DC, ∆AVDD = 5% 100 dB Digital power-supply rejection At DC, ∆AVDD = 5% 100 dB Voltage Reference Input Reference input voltage (VREF) VREF ≡ VREFP − VREFN 0.5 1.25 AVDD(7) V Negative reference input (VREFN) GND − 0.1 VREFP − 0.5 V Positive reference input (VREFP) VREFN + 0.5 AVDD + 0.1 V Voltage reference impedance fCLK = 2.4576MHz 1 MΩ Digital Input/Output VIH (CLK, SCLK) 0.8 DVDD 5.25 V VIL (CLK, SCLK) GND 0.2 DVDD V LLooggiicc lleevveellss VOH (DRDY, DOUT) IOH = 1mA DVDD − 0.4 DVDD V VOL (DRDY, DOUT) IOL = 1mA GND DVDD + 0.4 V Input leakage (CLK, SCLK) 0 < (CLK, SCLK) < DVDD ±10 µA CLK frequency (fCLK) 6 MHz CLK duty cycle 30 70 % Power Supply AVDD 2.7 5.25 V DVDD 1.8 3.6 V Sleep mode 0.1 1 µA AAVVDDDD ccuurrrreenntt AVDD = 3V 152 µA AVDD = 5V 158 250 µA Sleep mode, CLK stopped 0.1 µA DDVVDDDD ccuurrrreenntt Sleep mode, 2.4576MHZ CLK running 1.6 5 µA DVDD = 3V 5 10 µA Total power dissipation AVDD = DVDD = 3V 0.47 mW (1)SPS = samples per second. (2)FSR = full-scale range = 4VREF. (3)Recalibration can reduce these errors to the level of the noise. (4)Achieving specified gain error performance requires that calibration be performed with reference voltage input between (GND + 0.1V) and (AVDD − 1.25V). See Voltage Reference Inputs section. (5)fCM is the frequency of the common-mode input. (6)fSIG is the frequency of the input signal. (7)It will not be possible to reach the digital output full-scale code when VIN > 2VREF. 3

(cid:10)(cid:4)"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +1.25V, unless otherwise specified. ANALOGCURRENTvsTEMPERATURE DIGITALCURRENTvsTEMPERATURE 220 12 210 200 10 190 DVDD=+3V,fCLK=4.9152MHz 180 AVDD=+5V,f =4.9152MHz 8 A) CLK A) µ 170 µ ( ( nt 160 nt 6 e e urr 150 urr C C 140 AVDD=+3V,f =2.4576MHz 4 CLK 130 120 2 110 DVDD=+1.8V,fCLK=2.4576MHz 100 0 −45 −25 −5 15 35 55 75 95 −45 −25 −5 15 35 55 75 95 Temperature((cid:2)C) Temperature((cid:2)C) Figure 1 Figure 2 ANALOGCURRENTvsANALOGSUPPLY DIGITALCURRENTvsDIGITALSUPPLY 164 16 162 14 160 12 µA) 158 f =4.9152Hz A) 10 fCLK=4.9152MHz ( CLK µ ent 156 nt( 8 Curr 154 urre C 6 152 4 f =2.4576MHz 150 CLK fCLK=2.4576MHz 2 148 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 −45 −25 −5 15 35 55 75 95 AnalogSupply(V) DigitalSupply(V) Figure 3 Figure 4 INTEGRALNONLINEARITYvsANALOGSUPPLY V =1.25;f =2.4576MHz REF OSC 30 VCM=2.4or((AVDD−1.8)/2+0.3),whicheverissmaller 12.5 INTEGRALNONLINEARITYvsVIN 25 10.0 T=+25(cid:2)C 7.5 SR) 20 R) 5.0 pmofF 15 T=−40(cid:2)C mofFS 2.50 T=+85(cid:2)C p p L( (p −2.5 N 10 L I T=+25(cid:2)C IN −5.0 5 −7.5 T=−40(cid:2)C T=+85(cid:2)C −10.0 0 −12.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 −2.5 −1.5 −0.5 0.5 1.5 2.5 AVDD(V) V (V) IN Figure 5 Figure 6 4

(cid:10)(cid:4)"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +1.25V, unless otherwise specified. OFFSETvsTEMPERATURE GAINvsTEMPERATURE 5 1.00006 R) 4 1.00005 FS 3 1.00004 (ppmof 21 alized) 111...000000000000321 alizedOffset −−012 Gain(Norm 100...099099099099098 Norm −−34 00..9999999976 0.99995 −5 0.99994 −45 −25 −5 15 35 55 75 95 −45 −25 −5 15 35 55 75 95 Temperature((cid:2)C) Temperature((cid:2)C) Figure 7 Figure 8 NOISEvsINPUTSIGNAL NOISEvsTEMPERATURE 3.2 3.0 3.0 2.5 S) 2.8 S) M M R 2.6 R R, R, 2.0 S 2.4 S F F of 2.2 of 1.5 m m p 2.0 p p p ( ( 1.0 e 1.8 e s s oi oi N 1.6 N 0.5 1.4 1.2 0 −2.5 −1.5 −0.5 0.5 1.5 2.5 −45 −25 −5 15 35 55 75 95 V (V) Temperature((cid:2)C) IN Figure 9 Figure 10 HISTOGRAMOFOUTPUTDATA COMMON−MODEREJECTIONRATIO 900 vsFREQUENCY 160 800 140 s 700 e c n 120 e 600 ur cc 500 B) 100 O d of 400 R( 80 mber 300 CMR 60 u N 200 40 100 20 0 0 4209876543210123456789012 −1−1−1−−−−−−−−− 111 1 10 100 1k 10k 100k ppmofFSR Frequency(Hz) Figure 11 Figure 12 5

(cid:10)(cid:4)"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +1.25V, unless otherwise specified. ANALOGPOWER−SUPPLYREJECTIONRATIO DIGITALPOWER−SUPPLYREJECTIONRATIO vsFREQUENCY vsFREQUENCY 140 140 120 120 100 100 PSRR(dB) 8600 PSRR(dB) 8600 40 40 20 20 0 0 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k Frequency(Hz) Frequency(Hz) Figure 13 Figure 14 6

(cid:10)(cid:4)"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 OVERVIEW The ADS1245 accepts differential input signals, but can also measure unipolar signals. Note that the analog inputs The ADS1245 is an ADC comprised of a 3rd-order modulator (listed in the Electrical Characteristics table as Absolute followed by a digital filter. The modulator measures the Input Range) must remain between GND + 0.1V to differential input signal VIN = (AINP – AINN) against the AVDD − 1.25V. Exceeding this range will degrade linearity differential reference VREF = (VREFP – VREFN). Figure 15 and result in performance outside specified limits. shows a conceptual diagram. The differential reference is scaled internally so that the full-scale input range is ±2V . REF The digital filter receives the modulator signal and provides VOLTAGE REFERENCE INPUTS a low-noise digital output. The filter also sets the frequency (VREFP, VREFN) response of the converter and provides 50Hz and 60Hz The voltage reference used by the modulator is generated rejection while settling in a single conversion cycle. A from the voltage difference between VREFP and VREFN: two-wire serial interface indicates conversion completion and V = VREFP – VREFN. A simplified diagram of the REF provides the user with the output data. circuitry on the reference inputs is shown in Figure 17. The switches and capacitors can be modeled with an effective impedance equal to: VREFPVREFN (cid:1) (cid:2) t SAMPLE (cid:3)25pF(cid:4)1M(cid:1)forf (cid:4)2.4576MHz Σ 2 CLK V CLK REF 2 2VREF VREFP VREFN AINP X1 Digital Σ VIN Modulator Filterand DRDY/DOUT Serial SCLK AINN X1 Interface AVDD AVDD ESD S1 S1 Protection Figure 15. Conceptual Diagram of the ADS1245 25pF ANALOG INPUTS (AINP, AINN) The input signal to be measured is applied to the input pins AINP and AINN. The ADS1245 features a low-drift S chopper-stabilized buffer to achieve very high input 2 impedance. The input impedance can be modeled by resistors, as shown in Figure 16. The impedance scales t =128/f inversely with f frequency. For example, if the frequency SAMPLE CLK CLK ON of f is reduced by a factor of two, the impedances Zeff CLK A S 1 and Zeff will double. OFF B ON S 2 OFF AVDD/2 ZeffA=280GΩ Figure 17. Simplified Reference Input Circuitry AINP ZeffB=3.46GΩ The ADS1245 is specified for operation with V = 1.25V, REF AINN resulting in a full−scale input value of ±2.5V. However, the Zeff =280GΩ buffered analog inputs can accept voltages within the A range of 0.10V to 3.75V, resulting in a maximum V of IN AVDD/2 fCLK=2.4576MHz. ±3.65V. Input voltages can be accurately measured over this entire range if a voltage reference of 1.825V is pro- vided. In any case, digital output codes will clip to the full Figure 16. Effective Analog Input Impedances scale value if the absolute input voltage range exceeds 2V . REF 7

(cid:10)(cid:4)"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 To achieve optimal gain error performance, the reference subsequent SCLK rising edge. After all 24 bits have been input should be maintained within the range GND + 0.1V retrieved, the pin can be forced high with an additional to AVDD − 1.25V when performing a self-calibration. A SCLK. It will then stay high until new data is ready. This is calibration based on a reference input outside this voltage useful when polling on the status of DRDY/DOUT to range will result in gain errors exceeding specified values, determine when to begin data retrieval. but not more than 0.5%. Errors due to drift will remain within specified limits regardless of the calibration procedure. SERIAL CLOCK INPUT (SCLK) For best performance, bypass the voltage reference inputs This digital input shifts serial data out with each rising with a 0.1µF capacitor between VREFP and VREFN. edge. As with CLK, this input may be driven with 5V logic Place the capacitor as close as possible to the pins. regardless of the DVDD or AVDD voltage. There is hysteresis built into this input, but care should still be taken ESD diodes protect the inputs. To keep these diodes from to ensure a clean signal. Glitches or slow-rising signals turning on, make sure the voltages on the input pins do not can cause unwanted additional shifting. For this reason, it go below GND by more than 100mV, and likewise do not is best to make sure the rise-and-fall times of SCLK are exceed AVDD by 100mV. less than 50ns. CLOCK INPUT (CLK) FREQUENCY RESPONSE This digital input supplies the system clock to the ADS1245. The recommended CLK frequency is The ADS1245 frequency response for fCLK = 2.4576MHz is shown in Figure 18. The frequency response repeats at 2.4576MHz. This places the notches of the digital filter at multiples of 19.2kHz. The overall response is that of a 50Hz and 60Hz and sets the data rate at 15SPS. The CLK low-pass filter with a –3dB cutoff frequency of 13.7Hz. As frequency can be increased to speed up the data rate, but can be seen, the ADS1245 does a good job attenuating out the frequency notches will move proportionally in to 19kHz. For the best resolution, limit the input bandwidth frequency. CLK must be left running during normal to below this value to keep higher frequency noise from operation. It can be turned off during Sleep Mode to save affecting performance. Often, a simple RC filter on the power, but this is not required. The CLK input can be driven ADS1245 analog inputs is all that is needed. with 5V logic, regardless of the DVDD or AVDD voltage. Minimize the overshoot and undershoot on CLK for the best analog performance. A small resistor in series with CLK (10Ω to 100Ω) can often help. CLK can be generated 0 f =2.4576MHz from a number of sources including stand-alone crystal CLK −20 oscillators and microcontrollers. The MSP430, an ultra low power microcontroller, is especially well-suited for this −40 task. Using the MSP430 FLL clock generator available on B) −60 the 4xx family, it is easy to produce a 2.4576MHz clock d ( n from a 32.768kHz crystal. ai −80 G −100 DATA READY/DATA OUTPUT (DRDY/DOUT) −120 The digital output pin on the ADS1245 serves two −140 purposes. It indicates when new data is ready by going 0 9.6 19.2 low. Afterwards, on the first rising edge of SCLK, the Frequency(kHz) DRDY/DOUT pin changes function and begins outputting the conversion data, MSB first. Data is shifted out on each Figure 18. Frequency Response 8

(cid:10)(cid:4)"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 To help see the response at lower frequencies, Figure 19 The ADS1245 data rate and frequency response scale illustrates the response out to 180Hz. Notice that both directly with CLK frequency. For example, if fCLK 50Hz and 60Hz signals are rejected. This feature is very increases from 2.4576MHz to 4.9152MHz, the data rate useful for eliminating power line cycle interference during increases from 15sps to 30sps while the notches in the measurements. Figure 20 shows the ADS1245 response response at 50Hz and 60Hz move out to 100Hz and around these frequencies. 120Hz. SETTLING TIME 0 The ADS1245 has single-cycle settling. That is, the output −20 data is fully settled after a single conversion—there is no −40 fCLK=2.4576MHz need to wait for additional conversions before retrieving −60 the data when there is a change on the analog inputs. dB) −80 In order to realize single-cycle settling, synchronize ( ain −100 changes on the analog inputs to the conversion beginning, G −120 which is indicated by the falling edge of DRDY/DOUT. For example, when using a multiplexer in front of the −140 ADS1245, change the multiplexer inputs when −160 DRDY/DOUT goes low. Increasing the time between the −180 conversion beginning and the change on the analog inputs 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 (tDELAY) results in a settling error in the conversion data, as Frequency(Hz) shown in Figure 21. The settling error versus delay time is shown in Figure 22. If the input change is delayed to the point where the settling error is too high, simply ignore the Figure 19. Frequency Response to 180Hz first data result and wait for the second conversion, which will be fully settled. −40 10.000000 −50 1.000000 −60 fCLK=2.4576MHz %) 0.100000 dB) −70 Error( 0.010000 fCLK=2.4576MHz Gain( −−8900 Settling 00..000010010000 −100 0.000010 −110 0.000001 −120 0 2 4 6 8 10 12 14 16 45 50 55 60 65 DelayTime,t (ms) DELAY Frequency(Hz) Figure 20. Frequency Response Near Figure 21. Settling Error vs Delay Time 50Hz and 60Hz 9

(cid:10)(cid:4)"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 BeginNewConversion, PreviousConversionData CompletePreviousConversion NewConversionComplete DRDY/DOUT t DELAY V IN Figure 22. Analog Input Change Timing POWER−UP ready for retrieval. The time required before the first data is ready (t ) depends on how fast AVDD and DVDD ramp Self-calibration is performed at power-up to minimize offset 6 to their final value (t ). For most ramp rates, t + t ≈ 350ms and gain errors. In order for the self-calibration at power-up to 1 1 2 (f = 2.4576MHz). If the system environment is not stable work properly, make sure that both AVDD and DVDD increase CLK during power-up (the temperature is varying or the supply monotonically and are settled by t , as shown in Figure 23. 1 voltages are moving around), it is recommended that a SCLK must be held low during this time. Once calibration self-calibration be issued after everything is stable. is complete, DRDY/DOUT goes low, indicating data is AVDDandDVDD Datareadyafterpower−upcalibration. DRDY/DOUT SCLK t t 1 2 SYMBOL DESCRIPTION MIN MAX UNITS t1 (1) AVDD and DVDD settling time. 100 ms t2 (1) Wait time for calibration and first data 316 ms conversion. NOTE: (1) Values given for f = 2.4576MHz. For different CLK frequencies, CLK scale proportional to CLK period. Figure 23. Power-Up Timing 10

(cid:10)(cid:4)"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 DATA FORMAT DATA RETRIEVAL The ADS1245 outputs 24 bits of data in Binary Two’s The ADS1245 continuously converts the analog input Complement format. The least significant bit (LSB) has a signal. To retrieve data, wait until DRDY/DOUT goes low, weight of (2V )/(223 − 1). A positive full-scale input as shown in Figure 24. After this occurs, begin shifting out REF produces an output code of 7FFFFFh and the negative the data by applying SCLKs. Data is shifted out most full-scale input produces an output code of 8000000h. The significant bit (MSB) first. It is not required to shift out all the output clips at these codes for signals exceeding 24 bits of data, but the data must be retrieved before the full-scale. Table 1 summarizes the ideal output codes for new data is updated (see t ) or else it will be overwritten. 3 different input signals. Avoid data retrieval during the update period. DRDY/DOUT remains at the state of the last bit shifted out Table 1. Ideal Output Code vs Input Signal until it is taken high (see t ), indicating that new data is 7 being updated. INPUT SIGNAL VIN (AINP − AINN) IDEAL OUTPUT CODE(1) To avoid having DRDY/DOUT remain in the state of the ≥ +2VREF 7FFFFFH last bit, shift a 25th SCLK to force DRDY/DOUT high; see (cid:5)2VREF 000001H Figure 25. This technique is useful when a host controlling (223)(cid:6)1 the ADS1245 is polling DRDY/DOUT to determine when 0 000000H data is ready. (cid:6)2V FFFFFFH REF (223)(cid:6)1 (cid:1) (cid:2) (cid:7)(cid:6)2V 223 800000H REF (223)(cid:6)1 NOTE: (1) Excludes effects of noise, INL, offset, and gain errors. Data Dataisready. Newdataisready. MSB LSB DRDY/DOUT 23 22 21 0 t t 5 6 t t t 3 4 7 SCLK 1 24 t 4 t 8 SYMBOL DESCRIPTION MIN MAX UNITS t3 DRDY/DOUT low to first SCLK rising edge. 0 ns t4 SCLK positive or negative pulse width. 100 ns t5 (1) SCLK rising edge to new data bit valid; 50 ns propagation delay. t SCLK rising edge to old data bit valid: hold time. 0 ns 6 t Data updating, no read back allowed. 152 152 µs 7 t8 (2) Conversion time (1/data rate). 66.667 66.667 ms NOTES: (1) Load on DRDY/DOUT = 20pF||100kΩ. (2) Values given for f = 2.4576MHz. For different CLK frequencies, scale CLK proportional to CLK period. For example, for f = 4.9152MHz, t →33.333ms. CLK 8 Figure 24. Data Retrieval Timing 11

(cid:10)(cid:4)"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 Data Dataisready. Newdataisready. DRDY/DOUT 23 22 21 0 SCLK 1 24 25 25thSCLKtoforceDRDY/DOUThigh Figure 25. Data Retrieval with DRDY/DOUT Forced High Afterwards SELF-CALIBRATION When the calibration is complete, DRDY/DOUT will go low, indicating that new data is ready. There is no need to The user can initiate self-calibration at any time, though in alter the analog input signal applied to the ADS1245 during many applications the ADS1245 drift performance is good calibration; the inputs pins are disconnected within the enough that the self-calibration performing automatically ADC and the appropriate signals are automatically applied at power-up is all that is needed. To initiate a internally. The first conversion after a calibration is fully self-calibration, apply at least two additional SCLKs after settled and valid for use. The time required for a calibration retrieving 24 bits of data. Figure 26 shows the timing depends on two independent signals: the falling edge of pattern. The 25th SCLK will send DRDY/DOUT high. The SCLK and an internal clock derived from CLK. Variations falling edge of the 26th SCLK will begin the calibration in the internal calibration values will change the time cycle. Additional SCLK pulses may be sent after the 26th required for calibration (t ) within the range given by the SCLK, but minimizing activity on SCLK during calibration 9 provides best results. MIN/MAX specs. t12 and t13 described in the next section are likewise affected. Datareadyaftercalibration DRDY/DOUT 23 22 21 0 23 Calbegins SCLK 1 24 25 26 t 9 SYMBOL DESCRIPTION MIN MAX UNITS t9 (1) First data ready after calibration. 209 210 ms NOTE: (1) Values given for f = 2.4576MHz. For different CLK frequencies, CLK scale proportional to CLK period. Figure 26. Self-Calibration Timing 12

(cid:10)(cid:4)"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 SLEEP MODE Sleep Mode with Self-Calibration Self-calibration can be set to run immediately after exiting Sleep mode dramatically reduces power consumption (typically < 1µW with CLK stopped) by shutting down all of Sleep mode. This is useful when the ADS1245 is put in the active circuitry. To enter Sleep mode, simply hold Sleep mode for long periods of time and self-calibration is SCLK high after DRDY/DOUT goes low, as shown in desired afterwards to compensate for temperature or supply voltage changes. Figure 27. Sleep Mode can be initiated at any time during read-back; it is not necessary to retrieve all 24 bits of data To force a self-calibration with Sleep mode, shift 25 bits out beforehand. Once t11 has passed with SCLK held high, before taking SCLK high to enter Sleep mode. Sleep mode will activate. DRDY/DOUT stays high once Self-calibration begins after wakeup. Figure 28 shows the Sleep mode begins. SCLK must remain high to stay in appropriate timing. Note the extra time needed after Sleep mode. To exit Sleep mode (wakeup), set SCLK low. wakeup for calibration before data is ready. The first data The first data after exiting Sleep Mode is valid. It is not after Sleep mode with self-calibration is fully settled and necessary to stop CLK during Sleep mode, but doing so can be used. will further reduce the digital supply current. Datareadyafterwakeup SleepMode DRDY/DOUT 23 22 21 0 23 Wakeup SCLK 1 24 t 10 t t 11 12 SYMBOL DESCRIPTION MIN MAX UNITS t10( 1) SMCoLdKe. HIGH after DRDY/DOUT goes low to activate Sleep 0 63.7 ms t ( 1) 66.5 66.5 ms 11 Sleep Mode activation time. t12( 1) Data ready after wakeup. 71 72 ms NOTES: (1) Values given for f = 2.4576MHz. For different CLK frequencies, scale proportional to CLK CLK period. Figure 27. Sleep-Mode Timing; Can Be Used for SIngle Conversions Datareadyafterwakeupandcalibration SleepMode DRDY/DOUT 23 22 21 0 23 Wakeupandbegincal. SCLK 1 24 25 t t 11 13 SYMBOL DESCRIPTION MIN MAX UNITS t13( 1) Data ready after wakeup and calibration. 210 211 ms NOTE: (1) Values given for f = 2.4576MHz. For different CLK frequencies, scale CLK proportional to CLK period. Figure 28. Sleep-Mode with Self-Calibration on Wakeup Timing; Can Be Used for SIngle Conversions 13

(cid:10)(cid:4)"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 SINGLE CONVERSIONS to+5Vlogic When only single conversions are needed, Sleep mode +5V can be used to start and stop the ADS1245. To make a SN74LVCC3245A single conversion, first enter the Sleep Mode holding SCLK high. Now, when ready to start the conversion, take SCLK low. The ADS1245 will wake up and begin the from from 0.1µ+F R1 0+.1µF +5Vlogic +5Vlogic conversion. Wait for DRDY/DOUT to go low, and then retrieve the data. Afterwards, take SCLK high to stop the ADS1245 from converting and re−enter Sleep mode. 10 9 8 7 6 Continue to hold SCLK high until ready to start the next CLK SCLK DRDY/DOUT DVDD AVDD conversion. Operating in this fashion greatly reduces power consumption since the ADS1245 is shut down while ADS1245 idle between conversions. Self−calibrations can be performed prior to the start of the single conversions by using the waveform shown in Figure 28. GND VREFP VREFN AINN AINP 1 2 3 4 5 SINGLE-SUPPLY OPERATION It is possible to operate the ADS1245 with a single supply. For a 3V supply, simply connect AVDD and DVDD Figure 29. Example of the ADS1244 Running on a together. Figure 29 shows an example of the ADS1245 Single 5V Supply running on a single 5V supply. An external resistor, R , is 1 used to drop 5V supply down to a desired voltage level of DVDD. For example, if the desired DVDD supply voltage is 3V and AVDD is 5V, the value of R should be: 1 MULTI-CHANNEL SYSTEMS R1(cid:4)(5V(cid:6)3V)(cid:3)5(cid:2)A(cid:8)400k(cid:1) (1) Multiple ADS1245s can be operated in parallel to measure multiple input signals. Figure 30 shows an example of a where 5mA is a typical digital current consumption when two-channel system. For simplicity, the supplies and DVDD = 3V (refer to the typical characteristic Digital reference circuitry were not included. The same CLK Current vs Digital Supply). A buffer on DRDY/DOUT can signal should be applied to all devices. To be able to provide level−shifting if required. synchronize the ADS1245s, connect the same SCLK DVDD can be set to a desired voltage by choosing a proper signal to all devices as well. When ready to synchronize, value of R , but keep in mind that DVDD must be set 1 place all the devices in Sleep mode. Afterwards, a wakeup between 1.8V and 3.6V. Note that the maximum logic high command will synchronize all the ADS1245s; that is, they output of DRDY/DOUT is equal to DVDD, but both CLK will sample the input signals simultaneously and SCLK inputs can be driven with 5V logic regardless of the DVDD or AVDD voltage. Use 0.1mF capacitors to The DRDY/DOUT outputs will go low at approximately the bypass both AVDD and DVDD. same time after synchronization. The falling edges, indicating that new data is ready, will vary with respect to each other no more than timing specification t14. This variation is due to possible differences in the ADS1245 internal calibration settings. To account for this when using multiple devices, either wait for t14 to pass after seeing one device DRDY/DOUT go low, or wait until all DRDY/DOUTs have gone low before retrieving data. 14

(cid:10)(cid:4)"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 ADS1245 1 GND CLK 10 2 VREFP SCLK 9 3 VREFN DRDY/DOUT 8 OUT1 4 AINN DVDD 7 IN1 5 AINP AVDD 6 ADS1245 1 GND CLK 10 2 VREFP SCLK 9 3 VREFN DRDY/DOUT 8 OUT2 4 AINN DVDD 7 IN2 5 AINP AVDD 6 CLKandSCLK Sources OUT1 t 14 OUT2 SYMBOLDESCRIPTION MIN MAX UNITS Difference between DRDY/ t14 DOUTs going low in ± 500 µs multichannel systems. Figure 30. Example of Using Multiple ADS1245s in Parallel 15

(cid:10)(cid:4)"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 SUMMARY OF SERIAL INTERFACE WAVEFORMS DRDY/DOUT 23 22 21 0 MSB LSB SCLK 1 24 a. Data Retrieval DRDY/DOUT 23 22 21 0 SCLK 1 24 25 b. Data Retrieval with DRDY/DOUT Forced High Afterwards Datareadyaftercalibration DRDY/DOUT 23 22 21 0 Begincalibration SCLK 1 24 25 26 c. Self-Calibration Dataready SleepMode DRDY/DOUT 23 22 21 0 Wakeupand startconversion SCLK 1 24 d. Sleep Mode/Single Conversions Datareadyafter wakeupandcalibration SleepMode DRDY/DOUT 23 22 21 0 Wakeupand begincal. SCLK 1 24 25 e. Sleep Mode/Single Conversions with Self-Calibration on Wakeup Figure 31. Summary of Serial Interface Waveforms 16

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS1245IDGST ACTIVE VSSOP DGS 10 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 BHI & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS1245IDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS1245IDGST VSSOP DGS 10 250 210.0 185.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DGS0010A VSSOP - 1.1 mm max height SCALE 3.200 SMALL OUTLINE PACKAGE C 5.05 4.75 TYP SEATING PLANE A PIN 1 ID 0.1 C AREA 8X 0.5 10 1 3.1 2X 2.9 NOTE 3 2 5 6 0.27 10X 0.17 B 3.1 0.1 C A B 1.1 MAX 2.9 NOTE 4 0.23 TYP SEE DETAIL A 0.13 0.25 GAGE PLANE 0.15 0.7 0 - 8 0.05 0.4 DETAIL A TYPICAL 4221984/A 05/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187, variation BA. www.ti.com

EXAMPLE BOARD LAYOUT DGS0010A VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE 10X (1.45) 10X (0.3) SYMM (R0.05) TYP 1 10 SYMM 8X (0.5) 5 6 (4.4) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221984/A 05/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DGS0010A VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE 10X (1.45) SYMM (R0.05) TYP 10X (0.3) 1 10 SYMM 8X (0.5) 5 6 (4.4) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221984/A 05/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated