® ADS1201 ADS1201 High Dynamic Range DELTA-SIGMA MODULATOR FEATURES DESCRIPTION l 130dB DYNAMIC RANGE The ADS1201 is a precision, 130dB dynamic range, l FULLY DIFFERENTIAL INPUT delta-sigma (DS ) modulator operating from a single l TWO-WIRE INTERFACE +5V supply. The differential inputs are ideal for direct connection to transducers or low level signals. With l INTERNAL/EXTERNAL REFERENCE the appropriate digital filter and modulator rate, the l ON-CHIP SWITCHES FOR CALIBRATION device can be used to achieve 24-bit analog-to-digital (A/D) conversion with no missing codes. Effective resolution of 20 bits can be maintained with a digital APPLICATIONS filter bandwidth of 1kHz at a modulator rate of 320kHz. l INDUSTRIAL PROCESS CONTROL The ADS1201 is designed for use in high resolution l INSTRUMENTATION measurement applications including smart transmit- l SMART TRANSMITTERS ters, industrial process control, weigh scales, chroma- tography, and portable instrumentation. It is available l PORTABLE INSTRUMENTS in a 16-lead SOIC package. l WEIGH SCALES l PRESSURE TRANSDUCERS AV AGND REF REF V DD IN OUT BIAS +2.5V Bias BIAS Reference Generator EN REF EN A P Second-Order MOUT IN DS AINN Modulator MCLK CAL GAIN/OFFSET DV DGND DD International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ©1997 Burr-Brown Corporation PDS-1417C Printed in U.S.A. October, 1999 SBAS081

SPECIFICATIONS At T = +25(cid:176)C, AV = DV = +5V, MCLK = 320kHz, REF LOW, BIAS LOW, and external +2.5V reference, unless otherwise specified. A DD DD EN EN ADS1201U PARAMETER CONDITIONS MIN TYP MAX UNITS ANALOG INPUT Absolute Input Voltage Range 0 +5 V With V (1) –10 +10 V BIAS Differential Input Voltage Range –5 +5 V With V (1) –20 See Note 2 +20 V BIAS Input Impedance 250(4) kW Input Capacitance 8 pF Input Leakage Current 5 50 pA At T to T 1 nA MIN MAX SYSTEM PERFORMANCE Dynamic Range 10Hz Bandwidth(5) 130(6) dB 60Hz Bandwidth(5) 115(6) 120(6) dB 1kHz Bandwidth(5) 115(6) dB Integral Linearity Error 60Hz Bandwidth(5) – 0.0015 %FSR 1kHz Bandwidth(5) – 0.0015 %FSR Offset Error(2) See Note 7 m V Offset Drift(3) 1 m V/(cid:176)C Gain Error(2) See Note 7 ppm Gain Error Drift(3) 1 m V/(cid:176)C Common-Mode Rejection At DC 80 100 dB Power Supply Rejection 80 dB REFERENCE Internal Reference (REF ) 2.4 2.5 2.6 V OUT Drift 25 ppm/(cid:176)C Noise 50 m Vp-p Load Current Source or Sink –1 1 mA Output Impedance 2 W External Reference (REF ) 2.0 3.0 V IN Load Current 2.5 m A V Output Using Internal Reference 3.15 3.3 3.45 V BIAS Drift 50 ppm/(cid:176)C Load Current 10 mA DIGITAL INPUT/OUTPUT Logic Family TTL Compatible CMOS Logic Levels: V (MCLK) I = +5m A 2.0 DV +0.3 V IH IH DD V (MCLK) I = +5m A –0.3 0.8 V IL IL V (MOUT) I = 2 TTL Loads 2.4 V OH OH V (MOUT) I = 2 TTL Loads 0.4 V OL OL MCLK Frequency 0.02 1 MHz POWER SUPPLY REQUIREMENTS Power Supply Voltage Specified Performance 4.75 5.25 V Supply Current Analog Current 4.6 mA Digital Current 0.4 mA Additional Analog Current REF Enabled No Load 1.6 mA OUT V Enabled No Load 1 mA BIAS Total Power Dissipation REF , V Disabled 25 40 mW OUT BIAS TEMPERATURE RANGE Specified Performance –40 +85 (cid:176) C NOTES: (1) This range is set with external resistors and V (as described in the text). Other ranges are possible. (2) After the on-chip offset and gain BIAS calibration functions have been employed. (3) Re-calibration can reduce these errors. (4) Input impedance changes with MCLK. (5) Assume brick wall digital filter is used. (6) 20 Log (full scale/rms noise). (7) After calibration, these errors will be of the order of the effective resolution. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS1201 2

ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC Analog Input: Current................................................– 100mA, Momentary DISCHARGE SENSITIVITY – 10mA, Continuous Voltage...................................AGND –0.3V to AV +0.3V DD This integrated circuit can be damaged by ESD. Burr-Brown AV to DV ...........................................................................–0.3V to 6V DD DD AV to AGND.........................................................................–0.3V to 6V recommends that all integrated circuits be handled with DD DVDD to DGND.........................................................................–0.3V to 6V appropriate precautions. Failure to observe proper handling AGND to DGND................................................................................– 0.3V and installation procedures can cause damage. REF Voltage to AGND............................................–0.3V to AV +0.3V IN DD Digital Input Voltage to DGND..................................–0.3V to DVDD +0.3V ESD damage can range from subtle performance degradation Digital Output Voltage to DGND...............................–0.3V to DV +0.3V Lead Temperature (soldering, 10s)..............................................D D+300(cid:176)C to complete device failure. Precision integrated circuits may Internal Power Dissipation.............................................................500mW be more susceptible to damage because very small parametric changes could cause the device not to meet its published NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum specifications. conditions for extended periods may affect device reliability. PIN CONFIGURATION PIN DESCRIPTIONS PIN NO NAME DESCRIPTION Top View SOIC 1 AV Analog Input: Analog Supply, +5V nominal. DD 2 REF Analog Output: Internal Reference Voltage Output: OUT +2.5V nominal. 3 REF Analog Input: Reference Voltage Input. IN 4 NIC Not Internally Connected. 5 A P Analog Input: Noninverting Input. IN AVDD 1 16 REFEN 6 AINN Analog Input: Inverting Input. 7 AGND Analog Input: Analog Ground. REF 2 15 MOUT OUT 8 V Analog Output: Bias Voltage Output, nominally BIAS REF 3 14 MCLK +3.3V (with +2.5V reference). IN 9 BIAS Digital Input: Bias Voltage Enable Input (HIGH = EN NIC 4 13 DVDD enabled, LOW = disabled). ADS1201 10 GAIN/OFFSET Digital Input: Gain/Offset Calibration Select Input A P 5 12 DGND IN (with CAL LOW; HIGH = gain configuration, LOW = offset configuration). A N 6 11 CAL IN 11 CAL Digital Input: Calibration Control Input (HIGH = AGND 7 10 GAIN/OFFSET normal operation, LOW = gain or offset calibration configuration). VBIAS 8 9 BIASEN 12 DGND Digital Input: Digital Ground. 13 DV Digital Input: Digital Supply, +5V nominal. DD 14 MCLK Digital Input: Modulator Clock Input. CMOS compatible. 15 MOUT Digital Output: Modulator Output. 16 REF Digital Input: REF Voltage Enable Input EN OUT (HIGH = enabled, LOW = disabled). PACKAGE/ORDERING INFORMATION PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER(1) MEDIA ADS1201U SOL-16 211 –40(cid:176)C to +85(cid:176)C ADS1201U ADS1201U Rails " " " " " ADS1201U/1K Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “ADS1201U/1K” will get a single 1000-piece Tape and Reel. ® 3 ADS1201

TYPICAL PERFORMANCE CURVES At T = +25(cid:176)C, AV = DV = +5V, MCLK = 320kHz, REF LOW, BIAS LOW, and external +2.5V reference, unless otherwise specified. A DD DD EN EN rms NOISE LINEARITY 1.2 1.5 1.0 1 0.5 0 0.8 –0.5 m) m) p 0.6 p –1.0 p p ( ( –1.5 0.4 –2.0 –2.5 0.2 –3.0 0 –3.5 –5 –4 –3 –2 –1 0 1 2 3 4 5 –5 –4 –3 –2 –1 0 1 2 3 4 5 V (V) V (V) DIN DIN CMRR vs FREQUENCY PSRR vs FREQUENCY 110 70 68 105 B) B) 66 d d R ( R ( R R CM PS 64 100 62 95 60 0.1 1 10 100 1000 0.1 1.0 10 100 1k 10k 100k Frequency (Hz) Frequency (Hz) TYPICAL SINK CURRENT TYPICAL SOURCE CURRENT 30 30 25 25 20 20 A) A) m m (T 15 (T 15 U U O O I I 10 10 5 5 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 V (V) V (V) OL OL ® ADS1201 4

TYPICAL PERFORMANCE CURVES (Cont.) At T = +25(cid:176)C, AV = DV = +5V, MCLK = 320kHz, REF LOW, BIAS LOW, and external +2.5V reference, unless otherwise specified. A DD DD EN EN CMRR vs V DIN 110 105 100 B) d R ( 95 R M C 90 85 80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 V (V) DIN GENERAL DESCRIPTION THEORY OF OPERATION The ADS1201 is a single channel, second-order, CMOS The differential analog input of the ADS1201 is imple- analog modulator designed for high resolution conversions mented with a switched capacitor circuit. This switched from dc to 1000Hz. The output of the converter (MOUT) capacitor circuit implements a 2nd-order modulator stage provides a stream of digital ones and zeros. The time which digitizes the input signal into a binary output stream. average of this serial output is proportional to the analog The input stage of the converter can be configured to sample input voltage. The combination of an ADS1201 and a an analog signal or to perform a calibration which quantifies processor that is programmed to implement a digital filter offset and gain errors. The sample clock (MCLK) provides results in a high resolution A/D converter system. This the switched capacitor network and modulator clock signal system allows flexibility with the digital filter design and is for the A/D conversion process, as well as the output data capable of A/D conversion results that have a dynamic range framing clock. Different frequencies for this clock allows that exceeds 130dB (see Figure 1). for a variety of performance solutions in resolution and signal bandwidth. The analog input signal is continuously sampled by the A/D converter and compared to an internal or external voltage reference. A digital stream appears at the output of the converter. This digital stream accurately repre- sents the analog input voltage over time. Analog Supply 1 AV REF 16 DD EN 2 REF MOUT 15 OUT 10µF 3 REF MCLK 14 IN 0.1µF Digital Supply 4 NIC DV 13 DD 200W ADS1201 0.1µF Processor 5 A P DGND 12 IN 200W 6 A N CAL 11 IN 7 AGND GAIN/OFFSET 10 47pF 47pF 8 V BIAS 9 BIAS EN FIGURE 1. Connection Diagram for the ADS1201 Delta-Sigma Modulator Including External Processor. ® 5 ADS1201

1-Bit Data Stream Switched 2nd-Order Processor Capacitor Charge-Balancing for Analog A/D Converter Filtering Input Analog Inputs Programmable Gain Amp 2nd-Order Modulator VIN+ VREF 1-Bit DAC VIN– FIGURE 2. Block Diagram of the ADS1201. ANALOG INPUT STAGE out of the analog inputs exceed 10mA. In addition, the Analog Input linearity of the device is guaranteed only when the analog voltage applied to either input resides within the range The input design topology of the ADS1201 is based on a defined by AGND = > –30mV and < = AV + 30mV. If fully differential switched capacitor architecture. This input DD either of the inputs exceed these limits, the input protection stage provides the mechanism to achieve low system noise, diodes on the front end of the converter will begin to turn on. high common-mode rejection (100dB) and excellent power This will induce leakage paths resulting in nonlinearities in supply rejection. The input impedance of the analog input is the conversion process. dependent on the input capacitor and modulator clock fre- For this reason, the 0V to 5V input range must be used with quency (MCLK), which is also the sampling frequency of caution. Should AV be 4.75V, the analog input signal the converter. Figure 3 shows the basic input structure of the DD would swing outside the guaranteed specifications of the ADS1201. The relationship between the input impedance of device. Designs utilizing this mode of operation should the ADS1201 and the modulator clock frequency is: consider limiting the span to a slightly smaller range. Com- A InputImpedance(W =) 1E12 mon-mode voltages are also a significant concern and must IN 12•f be carefully analyzed. MCLK The input impedance becomes a consideration in designs Modulator where the source impedance of the input signal is signifi- The modulator sampling frequency (MCLK) can be oper- cant. In this case, it is possible for a portion of the signal to ated over a range of 20kHz to 1MHz. The frequency of be lost across this external source impedance. The impor- MCLK can be increased to improve the performance of the tance of this effect depends on the desired system perfor- converter or adjusted to comply with the clock requirements mance. of the application. There are two restrictions on the analog input signal to the The modulator topology is fundamentally a 2nd-order, charge- ADS1201. Under no conditions should the current into or balancing A/D converter, as the one conceptualized in Fig- ure 4. The analog input voltage and the output of the 1-bit 8kWR S(Wtyp) High DAC is differentiated, providing an analog voltage at X2 and X . The voltage at X and X are presented to their indi- A + Impedance 3 2 3 IN > 1GW vidual integrators. The output of these integrators progress in a negative or positive direction. When the value of the C INT 12pF (typ) signal at X equals the comparator reference voltage, the 4 V output of the comparator switches from negative to positive Switching Frequency CM or positive to negative, depending on its original state. When = MCLK the output value of the comparator switches from a HIGH to C INT 12pF (typ) LOW or vise versa, the 1-bit DAC responds on the next R SW clock pulse by changing its analog output voltage at X , 8kW (typ) High 6 causing the integrators to progress in the opposite direction. A – Impedance IN > 1GW The feedback of the modulator to the front end of the integrators force the value of the integrator output to track FIGURE 3. Input Impedance of the ADS1201. the average of the input. ® ADS1201 6

REFERENCE CIRCUIT ence is used, the correct connection configuration is shown There are two reference circuits included in the ADS1201 in Figure 5a. The capacitor in this circuit is absolutely converter: V (REF , REF ) and V . The circuitry required if low noise performance is desired. REF IN OUT BIAS for VREF is configured to allow the user to utilize the internal An external reference can be used to reduce the noise in the reference on the chip or provide an external reference to the conversion process. If an external reference is used, care converter (see Figure 5). The second reference, VBIAS, is should be taken to insure that the selected reference has low derived from VREF, whether it is internal or external. VBIAS noise performance. The appropriate connection circuit of an is exclusively an output reference. This ratiometric relation- external reference is shown in Figure 5b. The reference must ship between VREF and VBIAS reduces system errors when be configured with appropriate capacitors to reduce the high two separate bias voltages are required in the application. frequency noise that may be contributed by the reference. The input impedance of REF changes with the modulator IN clock frequency. The relationship is: REFERENCE INPUT (REF ) IN The reference input (REF ) of the ADS1201 can be config- IN 1E12 ured so that the 2.5V (nominal) internal or external reference TypicalREF InputImpedance= IN 50•f can be used in the conversion process. If the internal refer- MCLK f MCLK X(t) X2 X3 X4 Integrator 1 Integrator 2 MOUT f S V REF Comparator X 6 D/A Converter FIGURE 4. Block Diagram of a Second-Order Modulator. +5V 1 AV REF 16 1 AV REF 16 DD EN DD EN 2 REF MOUT 15 2 REF MOUT 15 OUT OUT External 3 REF MCLK 14 3 REF MCLK 14 IN V IN 1µF REF 1µF 4 NIC DV 13 4 NIC DV 13 DD DD ADS1201 ADS1201 5 A P DGND 12 5 A P DGND 12 IN IN 6 A N CAL 11 6 A N CAL 11 IN IN 7 AGND GAIN/OFFSET 10 7 AGND GAIN/OFFSET 10 8 V BIAS 9 8 V BIAS 9 BIAS EN BIAS EN (a) Internal Reference (b) External Reference FIGURE 5. Two Voltage Reference Connection Alternatives for the ADS1201. ® 7 ADS1201

The reference input voltage can vary between 2V and 3V. reference are given in the Specifications table. Note that this Higher reference voltages will cause the full-scale range to reference is not designed to sink or to source more than 1mA increase while the internal circuit noise of the converter of current. In addition, loading the reference with a dynamic remains approximately the same. This will increase the LSB or variable load is not recommended. This can result in weight but not the internal noise, resulting in increased small changes in reference voltage as the load changes. signal-to-noise ratio. Likewise, lower reference voltages will decrease the signal-to-noise ratio. VOLTAGE BIAS OUTPUT (V ) BIAS The internal reference, which generates +2.5V, can be dis- The V output voltage is dependent on the reference BIAS abled when an external reference is used. This internal input (REF ) voltage and is approximately 1.33 times as IN reference is disabled with the REFEN pin. When the refer- great. The output of VBIAS is used to bias input signals of ence is disabled, the supply current (AVDD) of the converter greater than 5V. If a resistor network is used in combination will reduce by approximately 1.6mA. with the V output, the signal range can be scaled and BIAS level shifted to match the input range of the ADS1201. REFERENCE OUTPUT (VREF ) Figure 6 shows a connection diagram which will allow the OUT ADS1201 to accept a – 10V input signal (20V full-scale The ADS1201 contains an internal +2.5V reference. When range). If BIAS is HIGH, the voltage at V will be using this feature, REF must be HIGH (see Figure 5). EN BIAS EN 3.3V (assumes a 2.5V nominal V ). Tolerances, drift, noise, and other specifications for this REF REF REF EN OUT LOW High Impedance HIGH 2.5V (nominal) TABLE I. Reference Enable. 1 AV REF 16 0.1µF DD EN 2 REF MOUT 15 Serial Data Out OUT 1µF 3 REF MCLK 14 Clock In R IN 1 3kW VIN+ 4 NIC DVDD 13 ADS1201 0.1µF R2 5 AINP DGND 12 3kW V – 6 A N CAL 11 IN IN R R 3 4 7 AGND GAIN/OFFSET 10 1kW 1kW 8 V BIAS 9 BIAS EN FIGURE 6. – 10V Bipolar Input Configuration Using V . BIAS t 1 t t 2 3 t 4 SYMBOL DESCRIPTION MIN TYP MAX UNITS t 5 t Clock Period 3125 ns 1 t Clock HIGH 1562.5 ns MCLK 2 t Clock LOW 1562.5 ns 3 t Clock Rise Time 6 ns t 4 6 t Clock Fall Time 6 ns 5 MOUT Data Valid Data Valid Data Valid Data Valid t6 DOUT Valid after Clock Rising Edge 400 ns FIGURE 7. Timing Diagram for the Digital Interface of the ADS1201. ® ADS1201 8

An input differential signal of 0V will ideally produce a BIAS V EN BIAS stream of ones and zeros that are HIGH 50% of the time and LOW High Impedance LOW 50% of the time. A differential input of 5V will HIGH 1.33V • V REF produce a stream of ones and zeros that are HIGH 90% of TABLE II. Bias Enable. the time. A differential input of –5V will produce a stream of ones and zeros that are HIGH 10% of the time. The input voltage versus the output modulator signal is shown in When enabled, the V circuitry consumes approximately BIAS Figure 8. 1mA with no external load. The maximum current into or out of V should not exceed 10mA. BIAS OFFSET and GAIN CALIBRATION On power-up, external signals may be present before V BIAS is enabled. This can create a situation in which a negative The ADS1201 offers a self-calibration function that is imple- voltage is applied to the analog inputs, reverse biasing the mented with the GAIN/OFFSET and CALEN pins. Both negative input protection diode of the ADS1201. This situ- conditions provide an output stream of data, similar to ation should not be a problem as long as the resistors R and normal operation where the converter is configured to sample 1 R2 limit the current being sourced by each analog input to be an input signal at AIN. under 10mA. A potential of 0V at the analog input pin (A P The offset and gain errors of the ADS1201 are calibrated IN or A N) should be used in the calculation. independently. For best operation, the offset should be IN calibrated first, followed by the gain. The calibration imple- DIGITAL OUTPUT mentation timing diagram is shown in Figure 9. The calibra- tion mode pins control the calibration functions of the The timing diagram for the ADS1201 data retrieval is shown ADS1201. in Figure 7. MCLK initiates the modulator process for the ADS1201 and is used as a system clock by the ADS1201, as Calibration should be performed once and then normal well as a framing clock for data out. The modulator output operation can be resumed. Calibration of offset and gain is data, which is a serial stream, is available on the MOUT pin. recommended immediately after power-on and whenever Typically, MOUT is read on the falling edge of MCLK. there is a “significant” change in the operating environment. Under any situation with MCLK, the duty cycle must be Significant changes in the operating environment include a kept constant for reliable, repeatable results. change of the MCLK frequency, MCLK duty cycle, power Modulator Output +FS (Analog Input) –FS (Analog Input) Analog Input FIGURE 8. Analog Input versus Modulator Output of the ADS1201. t t 9 8 CAL SYMBOL DESCRIPTION MIN TYP MAX UNITS t8 CAL and GAIN/OFFSET Rise Time 10 ns t t t9 CAL and GAIN/OFFSET Fall Time 10 ns 8 9 t t10 GAIN/OFFSET to CAL Setup Time 0 ns GAIN/OFFSET 10 t t11 GAIN/OFFSET to CAL Hold Time 2.5 TMCLK(1) ns 11 NOTE: (1) T is the clock period of MCLK. MCLK FIGURE 9. Timing Diagram for the Calibration Feature of the ADS1201. ® 9 ADS1201

The analog supply should be well regulated and low noise. GAIN/OFFSET CAL EN For designs requiring very high resolution from the ADS1201, 0 1 Normal Mode power supply rejection will be a concern. The requirements 0 0 Offset Calibration, Analog inputs shorted for the digital supply are not strict. However, high frequency to ground internally. noise on DV can capacitively couple into the analog DD 1 0 Full-Scale Calibration, Analog inputs are portion of the ADS1201. This noise can originate from referenced to V internally. REF switching power supplies, microprocessors or digital signal TABLE III. Calibration Enable. processors. For either supply, high frequency noise will generally be supply, V , or temperature. The amount of change which REF rejected by the external digital filter at integer multiples of could cause a re-calibration is dependent on the application MCLK. Just below and above these frequencies, noise will and effective resolution of the system. alias back into the pass-band of the digital filter, affecting The results of the calibration calculations are stored in two the conversion result. registers in the processor chip (see Figure 1). These two Inputs to the ADS1201, such as A , REF , and MCLK, IN IN calibration results can then be used to calibrate the input should not be present before the analog and digital supplies signal results with one of the following formulas: are on. Violating this condition could cause latch-up. If Equivalent Calibrated Output Code = FSC (FO – FO)/(FO – FO) these signals are present before the supplies are on, series 1 2 3 2 where FO = Filter output code of an applied input voltage resistors should be used to limit the input current. 1 FO2 = Filter output code of the offset calibration If one supply must be used to power the ADS1201, the FO3 = Filter output code of the gain calibration system’s analog supply should be used to power both AVDD FSC = Desired full-scale output and DVDD. Experimentation may be the best way to deter- mine the appropriate connection between AV and DV . With a simple sinc filter, the calibrated A/D conversion DD DD would equal: Equivalent Calibrated Input Voltage = (N – N) • V /(N – N ) GROUNDING 1 2 REF 3 2 where N1 = number of ones counted (or digital equivalent The analog and digital sections of the design should be after filtering) over given time (t ) with an applied input voltage M carefully and cleanly partitioned. Each section should have N = number of ones counted (or digital equivalent after filtering) 2 its own ground plane with no overlap between them. AGND during offset calibration where t = t 12 M should be connected to the analog ground plane as well as N = number of ones counted (or digital equivalent after filtering) 3 all other analog grounds. DGND should be connected to the during gain calibration where t = t 13 M digital ground plane and all digital signals referenced to this A system calibration can be performed by applying two plane. known voltage levels to the input of the converter. In this situation, the GAIN/OFFSET and CAL pins are not used. The ADS1201 pinout is such that the converter is cleanly EN Rather, the digital output of these two known voltages are separated into an analog and digital portion. This should accumulated by the processor. With this data, the processor allow simple layout of the analog and digital sections of the can determine the calibration register values that are appro- design. priate for the application. For a signal converter system, AGND and DGND of the ADS1201 can be connected together. Do not join the ground LAYOUT CONSIDERATIONS planes, but connect the two with a moderate signal trace underneath the converter. For multiple converters, connect POWER SUPPLIES the two ground planes at one location as central to all of the converters as possible. In some cases, experimentation may The ADS1201 requires the digital supply (DV ) to be no DD be required to find the best point to connect the two planes greater than the analog supply (AV ). Failure to observe DD together. Experimentation may be the best way to determine this condition could cause permanent damage to the the appropriate connection between AGND and DGND. ADS1201. The best scheme is to power the analog section of the design and AV from one +5V line and the digital DD section and DV from a separate +5V line (from the same DECOUPLING DD supply). If there are separate analog and digital power Good decoupling practices should be used for the ADS1201 supplies for the ADS1201, a good design approach would be and for all components in the design. All decoupling capaci- to have the analog supply come up first, followed by the tors, specifically the 0.1m F ceramic capacitors, should be digital supply. Another approach that can be used to control placed as close as possible to the pin being decoupled. A the analog and digital power supply differences is shown in 1m F and 10m F capacitor, in parallel with the 0.1m F ceramic Figure 10. In this circuit, a connection has been made capacitor, should be used to decouple AV to AGND. At between the ADS1201 supply pins via a 10W resistor. The a minimum, a 0.1m F ceramic capacitor shDoDuld be used to combination of this resistor and the decoupling capacitors decouple DV to DGND, as well as for the digital supply DD provides some filtering between DV and AV . DD DD on each digital component. ® ADS1201 10

+5V 10W 1 AV REF 16 + DD EN 10µF 0.1µF 2 REF MOUT 15 OUT 3 REF MCLK 14 IN 4 NIC DV 13 DD ADS1201 0.1µF 5 A P DGND 12 IN 6 A N CAL 11 IN 7 AGND GAIN/OFFSET 10 8 V BIAS 9 BIAS EN FIGURE 10. Power Supply Connection Using One Power Plane and One Digital Plane. +5V Isolated Power 6kW 0.1µF 10kW DSP 1 AV REF 16 DD EN MDATA Opto 2 REF MOUT 15 +5V OUT Coupler 3 REF MCLK 14 8 7 IN 100µA 100µA 1µF 4 NIC DVDD 13 SCLK ADS1201 0.1µF 1 2 5 AINP DGND 12 SDATA REF200 6 A N CAL 11 +5V 5 4 IN 7 AGND GAIN/OFFSET 10 Opto MCLK Coupler 8 V BIAS 9 BIAS EN 3 FIGURE 11. Bridge Transducer Interface with Current Excitation. ® 11 ADS1201

+5V +5V Isolated Power 8 7 REF200 100µA 100µA 0.1µF DSP 1 2 1 AV REF 16 DD EN MDATA Opto 2 REF MOUT 15 +5V OUT Coupler 3 REF MCLK 14 IN 1µF 4 NIC DVDD 13 SCLK ADS1201 0.1µF 5 A P DGND 12 SDATA IN PT100 6 A N CAL 11 +5V IN 7 AGND GAIN/OFFSET 10 Opto MCLK Coupler 12.5kW 8 V BIAS 9 BIAS EN FIGURE 12. PT100 Interface with Current Excitation. +5V 0.1µF 10kW DSP 1 AV REF 16 3 DD EN 1/2 1 OPA2237 2 REFOUT MOUT 15 MDATA 2 3 REF MCLK 14 MCLK IN 0.1µF 4 NIC DV 13 SCLK DD ADS1201 0.1µF 5 A P DGND 12 SDATA R IN G 6 A N CAL 11 IN 7 AGND GAIN/OFFSET 10 6 1/2 7 OPA2237 8 VBIAS BIASEN 9 5 FIGURE 13. Geophone Interface. ® ADS1201 12

+5V +5V Isolated Power 0.1µF 10kW DSP 1 AV REF 16 3 DD EN 1/2 1 Opto MDATA 2 OPA2237 2 REFOUT MOUT 15 Coupler +5V 10kW 3 REFIN MCLK 14 0.1µF 4 NIC DVDD 13 SCLK ADS1201 0.1µF RG 5 AINP DGND 12 SDATA 10kW 6 A N CAL 11 +5V IN 6 7 AGND GAIN/OFFSET 10 Opto MCLK 1/2 7 Coupler OPA2237 8 VBIAS BIASEN 9 5 FIGURE 14. Single-Supply, High Accuracy Thermocouple Interface. Floating Positive HV+ Supply Gate Drive 0.1µF 5.1V DSP 1 AVDD REFEN 16 MDATA Opto 2 REFOUT MOUT 15 Coupler +5V 3 REFIN MCLK 14 0.1µF 4 NIC DVDD 13 SCLK RSENSE ADS1201 0.1µF 5 AINP DGND 12 SDATA Motor RSENSE 6 AINN CAL 11 +5V 7 AGND GAIN/OFFSET 10 Opto MCLK Coupler 8 VBIAS BIASEN 9 HV– FIGURE 15. Motor Controller Sensing Circuit. ® 13 ADS1201

PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2008 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty ADS1201U ACTIVE SOIC DW 16 40 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) ADS1201U/1K ACTIVE SOIC DW 16 1000 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) ADS1201U/1KG4 ACTIVE SOIC DW 16 1000 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) ADS1201UG4 ACTIVE SOIC DW 16 40 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) ADS1201U/1K SOIC DW 16 1000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS1201U/1K SOIC DW 16 1000 346.0 346.0 33.0 PackMaterials-Page2

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