ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 Low-Power, 8-Channel, 16-Bit Analog Front-End for Biopotential Measurements CheckforSamples:ADS1194,ADS1196,ADS1198 FEATURES With its high levels of integration and exceptional 1 performance, the ADS1194/6/8 family enables the • EightLow-NoisePGAsand 23 creation of scalable medical instrumentation systems EightHigh-ResolutionADCs(ADS1198) atsignificantlyreducedsize,power,andoverallcost. • LowPower:0.55mW/channel The ADS1194/6/8 have a flexible input multiplexer • Input-ReferredNoise: per channel that can be independently connected to 12μVPP(150HzBW,G=6) the internally-generated signals for test, temperature, • InputBiasCurrent:200pA and lead-off detection. Additionally, any configuration of input channels can be selected for derivation of the • DataRate:125SPSto8kSPS right leg drive (RLD) output signal. The ADS1194/6/8 • CMRR:–105dB operate at data rates as high as 8kSPS, thereby • ProgrammableGain:1,2,3,4,6,8,or12 allowing the implementation of software pace detection. Lead-off detection can be implemented • SupportsAAMIEC11,EC13,IEC60601-1, internal to the device, either with a pull-up/pull-down IEC60601-2-27,andIEC60601-2-51Standards resistor or an excitation current sink/source. Three • Supplies:UnipolarorBipolar integrated amplifiers generate the Wilson Center – Analog:2.7Vto5.25V Terminal (WCT) and the Goldberger terminals (GCT) required for a standard 12-lead medical – Digital:1.65Vto3.6V electrocardiogram(ECG). • Built-InRightLegDriveAmplifier,Lead-Off Detection,WCT,TestSignals Multiple ADS1194/6/8 devices can be cascaded in high channel count systems in a daisy-chain • PaceDetectionChannelSelect configuration. • Built-InOscillatorandReference Package options include a tiny 8mm × 8mm, 64-ball • FlexiblePower-Down,StandbyMode BGA and a TQFP-64. Both packages are specified • SPI™-CompatibleSerialInterface overthetemperaturerangeof0°Cto+70°C. • OperatingTemperatureRange: REF 0°Cto+70°C Test Signals and Monitors Reference APPLICATIONS A1 ADC1 SPI SPI • MedicalInstrumentation(ECG)including: A2 ADC2 – Patientmonitoring;Holter,event,stress, A3 ADC3 andvitalsignsIncludingECG,AED, – ETevloekmeeddaicuidnieopotential(EAP),Sleepstudy INPUTS MUX AA45 AADDCC45 Control Oscillator CLK monitor G • HSiiggnha-PlrAeccqisuiiosnit,ioSnimultaneous,Multichannel AA76 AADDCC76 PIO AND CONTRO L A8 ADC8 DESCRIPTION To Channel The ADS1194/6/8 are a family of multichannel, WCT TWerimlsionnal ¼ ¼ simultaneous sampling, 16-bit, delta-sigma (ΔΣ) ¼ analog-to-digital converters (ADCs) with a built-in programmable gain amplifier (PGA), internal reference,andanonboardoscillator. RLD PACE 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. SPIisatrademarkofMotorola. 2 Allothertrademarksarethepropertyoftheirrespectiveowners. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2010–2011,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. FAMILYANDORDERINGINFORMATION(1) MAXIMUM OPERATING PACKAGE NUMBEROF ADC SAMPLERATE TEMPERATURE RESPIRATION PRODUCT OPTION CHANNELS RESOLUTION (kSPS) RANGE CIRCUITRY BGA 4 16 8 0°Cto+70°C No ADS1194 TQFP 4 16 8 0°Cto+70°C No BGA 6 16 8 0°Cto+70°C No ADS1196 TQFP 6 16 8 0°Cto+70°C No BGA 8 16 8 0°Cto+70°C No ADS1198 TQFP 8 16 8 0°Cto+70°C No ADS1294 BGA 4 24 32 0°Cto+70°C External ADS1294R BGA 4 24 32 –40°Cto+85°C Yes ADS1294 TQFP 4 24 32 –40°Cto+85°C External ADS1296 BGA 6 24 32 0°Cto+70°C External ADS1296R BGA 6 24 32 –40°Cto+85°C Yes ADS1296 TQFP 6 24 32 –40°Cto+85°C External ADS1298 BGA 8 24 32 0°Cto+70°C External ADS1298R BGA 8 24 32 –40°Cto+85°C Yes ADS1298 TQFP 8 24 32 –40°Cto+85°C External (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orvisitthe deviceproductfolderatwww.ti.com. ABSOLUTE MAXIMUM RATINGS(1) Overoperatingfree-airtemperaturerange,unlessotherwisenoted. ADS1194,ADS1196,ADS1198 UNIT AVDDtoAVSS –0.3to+5.5 V DVDDtoDGND –0.3to+3.9 V AVSStoDGND –3to+0.2 V V inputtoAVSS AVSS–0.3toAVDD+0.3 V REF AnaloginputtoAVSS AVSS–0.3toAVDD+0.3 V DigitalinputvoltagetoDGND –0.3toDVDD+0.3 V DigitaloutputvoltagetoDGND –0.3toDVDD+0.3 V Inputcurrent(momentary) 100 mA Inputcurrent(continuous) 10 mA Operating temperature ADS1194,ADS1196,ADS1198 0to+70 °C range Humanbodymodel(HBM) ±2000 V JEDECstandard22,testmethodA114-C.01,allpins ESDratings Chargeddevicemodel(CDM) ±500 V JEDECstandard22,testmethodC101,allpins Storagetemperaturerange –60to+150 °C Maximumjunctiontemperature(T) +150 °C J (1) Stressesabovetheseratingsmaycausepermanentdamage.Exposuretoabsolutemaximumconditionsforextendedperiodsmay degradedevicereliability.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyond thosespecifiedisnotimplied. 2 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 ELECTRICAL CHARACTERISTICS Minimum/maximumspecificationsapplyfrom0°Cto+70°C.Typicalspecificationsareat+25°C. AllspecificationsatDVDD=1.8V,AVDD–AVSS=3V,V =2.4V,externalf =2.048MHz,datarate=500SPS,and REF CLK gain=6,unlessotherwisenoted. ADS1194,ADS1196,ADS1198 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ANALOGINPUTS Full-scaledifferentialinputvoltage (AINP–AINN) ±VREF/GAIN V SeetheInputCommon-ModeRange Inputcommon-moderange subsectionofthePGASettingsandInput Rangesection Inputcapacitance 20 pF Input=1.5V,TA=+25°C ±200 pA Inputbiascurrent Input=1.5VTA=0°Cto+70°C ±1 nA Nolead-off 1000 MΩ DCinputimpedance Currentsourcelead-offdetection 500 MΩ Pull-upresistorlead-offdetection 10 MΩ PGAPERFORMANCE Gainsettings 1,2,3,4,6,8,12 Bandwidth SeeTable4 ADCPERFORMANCE Resolution Nomissingcodes 16 Bits Datarate 125 8000 SPS CHANNELPERFORMANCE DCPerformance Gain=6(1),10secondsofdata 12.2 µVPP Gain=6,256points,0.5secondsof Input-referrednoise data 12.6 µVPP Gainsettingsotherthan6 SeeNoiseMeasurementssection Integralnonlinearity Full-scalewithgain=6,bestfit ±1 LSB(2) Offseterror ±500 μV Offseterrordrift 2 μV/°C Gainerror Excludingvoltagereferenceerror ±0.2 ±0.5 %ofFS Gaindrift Excludingvoltagereferencedrift 5 ppm/°C Gainmatchbetweenchannels 0.3 %ofFS ACPerformance Common-moderejectionratio(CMRR) fCM=50Hz,60Hz(3) –100 –105 dB Power-supplyrejectionratio(PSRR) fPS=50Hz,60Hz 85 dB Crosstalk fIN=50Hz,60Hz –100 dB Signal-to-noiseratio(SNR) fIN=10Hzinput,gain=6 97 dB Totalharmonicdistortion(THD) 10Hz,–0.5dBFs –95 dB DIGITALFILTER –3dBbandwidth 0.262fDR Hz Digitalfiltersettling Fullsetting 4 Conversions (1) Noisedatameasuredina10-secondinterval.Testnotperformedinproduction.Input-referrednoiseiscalculatedwithinputshorted (withoutelectroderesistance)overa10-secondinterval. (2) InputreferredLSBinvolts=(2×V /(Gain*216)). REF (3) CMRRismeasuredwithacommon-modesignalofAVSS+0.3VtoAVDD–0.3V.Thevaluesindicatedaretheminimumoftheeight channels. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximumspecificationsapplyfrom0°Cto+70°C.Typicalspecificationsareat+25°C. AllspecificationsatDVDD=1.8V,AVDD–AVSS=3V,V =2.4V,externalf =2.048MHz,datarate=500SPS,and REF CLK gain=6,unlessotherwisenoted. ADS1194,ADS1196,ADS1198 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT RIGHTLEGDRIVE(RLD)AMPLIFIERANDPACEAMPLIFIERS RLDintegratednoise BW=150Hz 8 µVrms RLDGainbandwidthproduct 50kΩ||10pFload,gain=1 100 kHz Pacenoise BW=8kHz 20 µVrms PaceGainbandwidthproduct 50kΩ||10pFload,PGAgain=1 80 kHz RLDSlewrate 50kΩ||10pFload,gain=1 0.2 V/µs PaceSlewrate 50kΩ||10pFload,PGAgain=1 0.04 V/µs Paceamplifiercrosstalk CrosstalkbetweenPaceamplifiers 60 dB Paceamplifieroutputresistance 100 Ω AVDD=3V 50 µA MaximumPaceandRLDcurrent AVDD=5V 75 µA Short-circuittoGND(AVDD=3V) 270 µA Short-circuittosupply(AVDD=3V) 550 µA PaceandRLDamplifierdrivestrength Short-circuittoGND(AVDD=5V) 490 µA Short-circuittosupply(AVDD=5V) 810 µA Totalharmonicdistortion 60Hz,–0.5dBFS –70 dB Common-moderange AVSS+0.7 AVDD–0.3 V Common-moderesistormatching Internal200kΩresistormatching 0.1 % Short-circuitcurrent ±0.25 mA Quiescentpowerconsumption EitherRLDorPaceamplifier 20 μA WILSONCENTERTERMINAL(WCT)AMPLIFIER Inputvoltagenoisedensity SeeTable3 µVRMS Gainbandwidthproduct SeeTable3 kHz Slewrate SeeTable3 V/s Totalharmonicdistortion fIN=100Hz 90 dB Common-moderange AVSS+0.3 AVDD–0.3 V Quiescentpowerconsumption SeeTable3 μA LEAD-OFFDETECT Frequency SeeRegisterMapsectionforsettings 0,fDR/4 kHz Current SeeRegisterMapsectionforsettings 4,8,12,16 nA Currentaccuracy ±20 % Comparatorthresholdaccuracy ±30 mV EXTERNALREFERENCE 3VsupplyVREF=(VREFP–VREFN) 2.5 V Referenceinputvoltage 5VsupplyVREF=(VREFP–VREFN) 4.1 V Negativeinput(VREFN) AVSS V Positiveinput(VREFP) AVSS+2.5 V Inputimpedance 10 kΩ INTERNALREFERENCE RegisterbitCONFIG3.VREF_4V=0, 2.4 V AVDD≥2.7V Outputvoltage RegisterbitCONFIG3.VREF_4V=1, 4.0 V AVDD≥4.4V VREFaccuracy ±0.2 % Drift 35 ppm/°C Start-uptime 150 ms 4 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 ELECTRICAL CHARACTERISTICS (continued) Minimum/maximumspecificationsapplyfrom0°Cto+70°C.Typicalspecificationsareat+25°C. AllspecificationsatDVDD=1.8V,AVDD–AVSS=3V,V =2.4V,externalf =2.048MHz,datarate=500SPS,and REF CLK gain=6,unlessotherwisenoted. ADS1194,ADS1196,ADS1198 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SYSTEMMONITORS Analogsupplyreadingerror 2 % Digitalsupplyreadingerror 2 % Frompower-up 150 ms Devicewakeup STANDBYmode 9 ms Temperaturesensorreading,voltage 145 mV Temperaturesensorreading,coefficient 490 μV/°C TestSignal Signalfrequency SeeRegisterMapsectionforsettings fCLK/221,fCLK/220 Hz Signalvoltage SeeRegisterMapsectionforsettings ±1,±2 mV Accuracy ±2 % CLOCK Nominalfrequency 2.048 MHz Internaloscillatorclockfrequency TA=+25°C 0.5 % 0°C≤TA≤+70°C ±2 % Internaloscillatorstart-uptime 20 μs Internaloscillatorpowerconsumption 120 μW Externalclockinputfrequency CLKSELpin=0 0.5 2.048 2.25 MHz DIGITALINPUT/OUTPUT(DVDD=1.65Vto3.6V) VIH 0.8DVDD DVDD+0.1 V VIL –0.1 0.2DVDD V Logiclevel VOH IOH=–500μA DVDD–0.4 V VOL IOL=+500μA 0.4 V Inputcurrent(IIN) 0V<VDigitalInput<DVDD –10 +10 μA POWER-SUPPLYREQUIREMENTS Analogsupply(AVDD–AVSS) 2.7 3 5.25 V Digitalsupply(DVDD) 1.65 1.8 3.6 V AVDD–DVDD –2.1 3.6 V SUPPLYCURRENT(RLD,WCT,andPaceAmplifiersTurnedOff) AVDD–AVSS=3V 1.3 mA IAVDD AVDD–AVSS=5V 1.6 mA Normalmode(ADS1198) DVDD=3.0V 0.5 mA IDVDD DVDD=1.8V 0.3 mA Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximumspecificationsapplyfrom0°Cto+70°C.Typicalspecificationsareat+25°C. AllspecificationsatDVDD=1.8V,AVDD–AVSS=3V,V =2.4V,externalf =2.048MHz,datarate=500SPS,and REF CLK gain=6,unlessotherwisenoted. ADS1194,ADS1196,ADS1198 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT POWERDISSIPATION(AnalogSupply=3V,RLD,WCT,andPaceAmplifiersTurnedOff) Quiescentpowerdissipation ADS1194 Normalmode 3 3.3 mW ADS1196 Normalmode 3.6 4 mW ADS1198 Normalmode 4.3 4.8 mW Power-down 10 μW Standbymode 2 mW Quiescentchannelpower PGA+ADC 350 µW POWERDISSIPATION(AnalogSupply=5V,RLD,WCT,andPaceAmplifiersTurnedOff) Quiescentpowerdissipation ADS1194 Normalmode 5.7 mW ADS1196 Normalmode 6.9 mW ADS1198 Normalmode 8.2 mW Power-down 20 μW Standbymode,internalreference 4 mW Quiescentchannelpower PGA+ADC 620 µW TEMPERATURE Specifiedtemperaturerange 0 +70 °C Operatingtemperaturerange 0 +70 °C Storagetemperaturerange –60 +150 °C THERMAL INFORMATION ADS1194/6/8 ADS1194/6/8 THERMALMETRIC(1) PAG ZXG UNITS 64PINS 64PINS θ Junction-to-ambientthermalresistance 29 29 JA θ Junction-to-case(top)thermalresistance 10.4 10.4 JCtop θ Junction-to-boardthermalresistance 14.8 14.8 JB °C/W ψ Junction-to-topcharacterizationparameter 0.2 0.2 JT ψ Junction-to-boardcharacterizationparameter 8.2 8.2 JB θ Junction-to-case(bottom)thermalresistance n/a n/a JCbot (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 6 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 NOISE MEASUREMENTS The ADS1194/6/8 noise performance can be optimized by adjusting the data rate and PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value reduces the input-referred noise, which is particularly useful when measuring low-level biopotential signals. Table 1 summarizes the noise performance of the ADS1194/6/8, with a 3V analog power supply. Table 2 summarizes the noise performance of the ADS1194/6/8 with a 5V analog power supply. The data are representative of typical noise performance at T = +25°C. The data shown are the result of averaging the A readings from multiple devices and are measured with the inputs shorted together. A minimum of 1000 consecutive readings are used to calculate the peak-to-peak noise for each reading. For the two highest data rates, the noise is limited by quantization noise of the ADC and does not have a gaussian distribution. The ratio between rms noise and peak-to-peak noise for these two data rates are approximately 10. For the lower data rates,theratioisapproximately6.6. Table 1 and Table 2 show measurements taken with an internal reference. In many of the settlings, espeically at the lower data rates, the inherent device noise is less than 1LSB. For these cases, the noise is rounded up to 1LSB. The data are also representative of the ADS1194/6/8 noise performance when using a low-noise external referencesuchastheREF5025. Table1.Input-ReferredNoise(μV ) PP 3VAnalogSupplyand2.4VReference(1)(2) DRBITSOF OUTPUT –3dB CONFIG1 DATARATE BANDWIDTH PGA PGA PGA PGA PGA PGA PGA REGISTER (SPS) (Hz) GAIN=1 GAIN=2 GAIN=3 GAIN=4 GAIN=6 GAIN=8 GAIN=12 000 8000 2096 2930 1470 937 681 436 319 205 001 4000 1048 563 265 173 124 77 56 36 010 2000 524 104 51 33 24 17 13 9.5 011 1000 262 73.3 36.6 24.4 18.3 12.2 9.2 6.1 100 500 131 73.3 36.6 24.4 18.3 12.2 9.2 6.1 101 250 65 73.3 36.6 24.4 18.3 12.2 9.2 6.1 110 125 32.5 73.3 36.6 24.4 18.3 12.2 9.2 6.1 (1) Atleast1000consecutivereadingswereusedtocalculatethepeak-to-peaknoisevaluesinthistable. (2) Fordatarateslessthan2kSPS,thenoiseisroundedupto1LSB.Input-referredLSBinvolts=(2×V /(Gain×216)). REF Table2.Input-ReferredNoise(μV ) PP 5VAnalogSupplyand4VReference(1)(2) DRBITSOF OUTPUT –3dB CONFIG1 DATARATE BANDWIDTH PGA PGA PGA PGA PGA PGA PGA REGISTER (SPS) (Hz) GAIN=1 GAIN=2 GAIN=3 GAIN=4 GAIN=6 GAIN=8 GAIN=12 000 8000 2096 4923 2450 1598 1196 765 560 362 001 4000 1048 959 481 307 222 142 100 63 010 2000 524 166 81 52 40 26 19 12.3 011 1000 262 122.1 61.1 40.7 30.5 20.4 15.3 10.2 100 500 131 122.1 61.1 40.7 30.5 20.4 15.3 10.2 101 250 65 122.1 61.1 40.7 30.5 20.4 15.3 10.2 110 125 32.5 122.1 61.1 40.7 30.5 20.4 15.3 10.2 (1) Atleast1000consecutivereadingswereusedtocalculatethepeak-to-peaknoisevaluesinthistable. (2) Fordatarateslessthan2kSPS,thenoiseisroundedupto1LSB.Input-referredLSBinvolts=(2×V /(Gain×216)). REF Table3.TypicalWCTPerformance ANYONE ANYTWO ALLTHREE PARAMETER (A,B,orC) (A+B,A+C,orB+C) (A+B+C) UNIT Noise 563 404 330 nV RMS Power 36 40 44 μA –3dBBW 30 59 89 kHz Slewrate BWlimited BWlimited BWlimited — Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com PIN CONFIGURATIONS ZXGPACKAGE BGA-64 (TOPVIEW,SOLDERBUMPSONBOTTOMSIDE) H G F E D C B A IN1P IN2P IN3P IN4P IN5P IN6P IN7P IN8P 1 IN1N IN2N IN3N IN4N IN5N IN6N IN7N IN8N 2 TESTN_ TESTP_ VREFP VCAP4 PACE_OUT2 PACE_OUT1 WCT RLDINV RLDOUT RLDIN 3 VREFN RESV3 RESV2 RESV1 AVSS RLDREF AVDD AVDD 4 VCAP1 PWDN GPIO1 GPIO4 AVSS AVSS AVSS AVSS 5 VCAP2 RESET DAISY_IN GPIO3 DRDY AVDD AVDD AVDD 6 DGND START CS GPIO2 DGND DGND VCAP3 AVDD1 7 DIN CLK SCLK DOUT DVDD DVDD CLKSEL AVSS1 8 BGAPINASSIGNMENTS NAME TERMINAL FUNCTION DESCRIPTION IN8P(1) 1A Analoginput Differentialanalogpositiveinput8(ADS1198only) IN7P(1) 1B Analoginput Differentialanalogpositiveinput7(ADS1198only) IN6P(1) 1C Analoginput Differentialanalogpositiveinput6(ADS1196/8only) IN5P(1) 1D Analoginput Differentialanalogpositiveinput5(ADS1196/8only) IN4P(1) 1E Analoginput Differentialanalogpositiveinput4 IN3P(1) 1F Analoginput Differentialanalogpositiveinput3 IN2P(1) 1G Analoginput Differentialanalogpositiveinput2 IN1P(1) 1H Analoginput Differentialanalogpositiveinput1 IN8N(1) 2A Analoginput Differentialanalognegativeinput8(ADS1198only) IN7N(1) 2B Analoginput Differentialanalognegativeinput7(ADS1198only) IN6N(1) 2C Analoginput Differentialanalognegativeinput6(ADS1196/8only) IN5N(1) 2D Analoginput Differentialanalognegativeinput5(ADS1196/8only) IN4N(1) 2E Analoginput Differentialanalognegativeinput4 IN3N(1) 2F Analoginput Differentialanalognegativeinput3 IN2N(1) 2G Analoginput Differentialanalognegativeinput2 IN1N(1) 2H Analoginput Differentialanalognegativeinput1 (1) ConnectunusedanaloginputsIN1xtoIN8xtoAVDD. 8 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 BGAPINASSIGNMENTS(continued) NAME TERMINAL FUNCTION DESCRIPTION RLDIN 3A Analoginput RightlegdriveinputtoMUX.Ifunused,shorttoAVDD. RLDOUT 3B Analogoutput Rightlegdriveoutput RLDINV 3C Analoginput/output Rightlegdriveinvertinginput WCT 3D Analogoutput WilsonCenterTerminaloutput Internaltestsignal/single-endedbufferoutputbasedonregistersettings.If TESTP_PACE_OUT1 3E Analoginput/bufferoutput unused,shorttoAVDD. Internaltestsignal/single-endedbufferoutputbasedonregistersettings.If TESTN_PACE_OUT2 3F Analoginput/output unused,shorttoAVDD. VCAP4 3G Analogoutput Analogbypasscapacitor VREFP 3H Analoginput/output Positivereferencevoltage AVDD 4A Supply Analogsupply AVDD 4B Supply Analogsupply RLDREF 4C Analoginput Rightlegdrivenoninvertinginput AVSS 4D Supply Analogground RESV1 4E Digitalinput Reservedforfutureuse;musttietologiclow(DGND) RESV2 4F Analogoutput Reservedforfutureuse;leavefloating RESV3 4G Analogoutput Reservedforfutureuse;leavefloating VREFN 4H Analoginput Negativereferencevoltage AVSS 5A Supply Analogground AVSS 5B Supply Analogground AVSS 5C Supply Analogground AVSS 5D Supply Analogground GPIO4 5E Digitalinput/output General-purposeinput/outputpin GPIO1 5F Digitalinput/output General-purposeinput/outputpin PWDN 5G Digitalinput Power-down;activelow VCAP1 5H Analoginput/output Analogbypasscapacitor AVDD 6A Supply Analogsupply AVDD 6B Supply Analogsupply AVDD 6C Supply Analogsupply DRDY 6D Digitaloutput Dataready;activelow GPIO3 6E Digitalinput/output General-purposeinput/outputpin DAISY_IN(2) 6F Digitalinput Daisy-chaininput RESET 6G Digitalinput Systemreset;activelow VCAP2 6H — Analogbypasscapacitor AVDD1 7A Supply Analogsupplyforchargepump VCAP3 7B — Analogbypasscapacitor,internally-generatedAVDD+1.9V DGND 7C Supply Digitalground DGND 7D Supply Digitalground GPIO2 7E Digitalinput/output General-purposeinput/outputpin CS 7F Digitalinput SPIchipselect;activelow START 7G Digitalinput Startconversion DGND 7H Supply Digitalground AVSS1 8A Supply Analoggroundforchargepump CLKSEL 8B Digitalinput Masterclockselect DVDD 8C Supply Digitalpowersupply DVDD 8D Supply Digitalpowersupply DOUT 8E Digitaloutput SPIdataout SCLK 8F Digitalinput SPIclock CLK 8G Digitalinput/output Externalmasterclockinputorinternalclockoutput DIN 8H Digitalinput SPIdatain (2) WhenDAISY_INisnotused,tietologic'0'. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com PAGPACKAGE TQFP-64 (TOPVIEW) WCT RLDOUT RLDIN RLDINV RLDREF AVDD AVSS AVSS AVDD VCAP3 AVDD1 AVSS1 CLKSEL DGND DVDD DGND 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 IN8N 1 48 DVDD IN8P 2 47 DRDY IN7N 3 46 GPIO4 IN7P 4 45 GPIO3 IN6N 5 44 GPIO2 IN6P 6 43 DOUT IN5N 7 42 GPIO1 IN5P 8 41 DAISY_IN IN4N 9 40 SCLK IN4P 10 39 CS IN3N 11 38 START IN3P 12 37 CLK IN2N 13 36 RESET IN2P 14 35 PWDN IN1N 15 34 DIN IN1P 16 33 DGND 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 1 2 D S D D S P N 4 C 1 C 2 1 S OUT OUT AVD AVS AVD AVD AVS REF REF CAP N CAP N CAP ESV AVS _ _ V V V V V R E E C C A A P P _ _ P N T T S S E E T T PAGPINASSIGNMENTS NAME TERMINAL FUNCTION DESCRIPTION IN8N(1) 1 Analoginput Differentialanalognegativeinput8(ADS1198only) IN8P(1) 2 Analoginput Differentialanalogpositiveinput8(ADS1198only) IN7N(1) 3 Analoginput Differentialanalognegativeinput7(ADS1198only) IN7P(1) 4 Analoginput Differentialanalogpositiveinput7(ADS1198only) IN6N(1) 5 Analoginput Differentialanalognegativeinput6(ADS1196/8only) IN6P(1) 6 Analoginput Differentialanalogpositiveinput6(ADS1196/8only) IN5N(1) 7 Analoginput Differentialanalognegativeinput5(ADS1196/8only) IN5P(1) 8 Analoginput Differentialanalogpositiveinput5(ADS1196/8only) IN4N(1) 9 Analoginput Differentialanalognegativeinput4 IN4P(1) 10 Analoginput Differentialanalogpositiveinput4 IN3N(1) 11 Analoginput Differentialanalognegativeinput3 IN3P(1) 12 Analoginput Differentialanalogpositiveinput3 IN2N(1) 13 Analoginput Differentialanalognegativeinput2 IN2P(1) 14 Analoginput Differentialanalogpositiveinput2 IN1N(1) 15 Analoginput Differentialanalognegativeinput1 IN1P(1) 16 Analoginput Differentialanalogpositiveinput1 (1) ConnectunusedanaloginputsIN1xtoIN8xtoAVDD. 10 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 PAGPINASSIGNMENTS(continued) NAME TERMINAL FUNCTION DESCRIPTION TESTP_PACE_OUT1 17 Analoginput/bufferoutput Internaltestsignal/single-endedbufferoutputbasedonregistersettings TESTN_PACE_OUT2 18 Analoginput/output Internaltestsignal/single-endedbufferoutputbasedonregistersettings AVDD 19 Supply Analogsupply AVSS 20 Supply Analogground AVDD 21 Supply Analogsupply AVDD 22 Supply Analogsupply AVSS 23 Supply Analogground VREFP 24 Analoginput/output Positivereferencevoltage VREFN 25 Analoginput Negativereferencevoltage VCAP4 26 Analogoutput Analogbypasscapacitor NC 27 — Noconnection;leavefloating VCAP1 28 — Analogbypasscapacitor NC 29 — Noconnection;leavefloating VCAP2 30 — Analogbypasscapacitor RESV1 31 Digitalinput Reservedforfutureuse;musttietologiclow(DGND) AVSS 32 Supply Analogground DGND 33 Supply Digitalground DIN 34 Digitalinput SPIdatain PWDN 35 Digitalinput Power-down;activelow RESET 36 Digitalinput Systemreset;activelow CLK 37 Digitalinput/output Externalmasterclockinputorinternalclockoutput START 38 Digitalinput Startconversion CS 39 Digitalinput SPIchipselect;activelow SCLK 40 Digitalinput SPIclock DAISY_IN 41 Digitalinput Daisy-chaininput.Ifnotused,shorttologiczero(DGND). GPIO1 42 Digitalinput/output General-purposeinput/outputpin DOUT 43 Digitaloutput SPIdataout GPIO2 44 Digitalinput/output General-purposeinput/outputpin GPIO3 45 Digitalinput/output General-purposeinput/outputpin GPIO4 46 Digitalinput/output General-purposeinput/outputpin DRDY 47 Digitaloutput Dataready;activelow DVDD 48 Supply Digitalpowersupply DGND 49 Supply Digitalground DVDD 50 Supply Digitalpowersupply DGND 51 Supply Digitalground CLKSEL 52 Digitalinput Masterclockselect AVSS1 53 Supply Analogground AVDD1 54 Supply Analogsupply VCAP3 55 Analog Analogbypasscapacitor,internallygeneratedAVDD+1.9V AVDD 56 Supply Analogsupply AVSS 57 Supply Analogground AVSS 58 Supply Analoggroundforchargepump AVDD 59 Supply Analogsupplyforchargepump RLDREF 60 Analoginput Rightlegdrivenoninvertinginput RLDINV 61 Analoginput/output Rightlegdriveinvertinginput RLDIN 62 Analoginput RightlegdriveinputtoMUX RLDOUT 63 Analogoutput Rightlegdriveoutput WCT 64 Analogoutput WilsonCenterTerminaloutput Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com TIMING CHARACTERISTICS t CLK CLK t t CSSC t CSH CS SDECODE t t t SPWL SCCS SCLK t SPWH SCLK 1 2 3 8 1 2 3 8 t t t DIHD t DOHD DIST DOPD DIN t t CSDOD CSDOZ Hi-Z Hi-Z DOUT NOTE:SPIsettingsareCPOL=0andCPHA=1. Figure1. SerialInterfaceTiming t t DISCK2ST DISCK2HT DAISY_IN MSB LSB D1 D1 SCLK 1 2 3 152 153 154 155 t DOPD DOUT MSB LSB Don’t Care MSBD1 NOTE:Daisy-chaintimingisshownforthe8-channelADS1198. Figure2. Daisy-ChainInterfaceTiming Timing Requirements For Figure 1 and Figure 2 Specificationsapplyfrom0°Cto+70°C.LoadonD =20pF||100kΩ. OUT 2.7V≤DVDD≤3.6V 1.65V≤DVDD≤2.0V PARAMETER DESCRIPTION MIN TYP MAX MIN TYP MAX UNIT t Masterclockperiod 414 514 414 514 ns CLK t CSlowtofirstSCLK;setuptime 6 17 ns CSSC t SCLKperiod 50 66.6 ns SCLK t SCLKpulsewidth,highandlow 15 25 ns SPWH,L t DINvalidtoSCLKfallingedge;setuptime 10 10 ns DIST t ValidDINafterSCLKfallingedge;holdtime 10 11 ns DIHD t SCLKfallingedgetoinvalidDOUT;holdtime 10 10 ns DOHD t SCLKrisingedgetoDOUTvalid;setuptime 17 32 ns DOPD t CShighpulse 2 2 t CSH CLKs t CSlowtoDOUTdriven 8 20 ns CSDOD t EighthSCLKfallingedgetoCShigh 4 4 t SCCS CLKs t Commanddecodetime 4 4 t SDECODE CLKs t CShightoDOUTHi-Z 10 20 ns CSDOZ t DAISY_INvalidtoSCLKrisingedge;setuptime 10 10 ns DISCK2ST t DAISY_INvalidafterSCLKrisingedge;holdtime 10 10 ns DISCK2HT 12 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 TYPICAL CHARACTERISTICS AllplotsatT =+25°C,AVDD=3V,AVSS=0V,DVDD=1.8V,internalVREFP=2.4V,VREFN=AVSS,external A clock=2.048MHz,datarate=500SPS,andgain=6,unlessotherwisenoted. INLvsTEMPERATURE INLvsPGAGAIN 1 1 +70°C 0.8 0.8 +50°C SB) 0.6 +25°C SB) 0.6 y (L 0.4 0°C y (L 0.4 arit 0.2 arit 0.2 e e nlin 0 nlin 0 No -0.2 No -0.2 gral -0.4 gral -0.4 PGA 1 PGA 6 nte -0.6 nte -0.6 PGA 2 PGA 8 I I PGA 3 -0.8 -0.8 PGA 4 PGA 12 -1 -1 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Input (Normalized to Full-Scale Range) Input (Normalized to Full-Scale) Figure3. Figure4. FFTPLOT FFTPLOT 0 0 PGA Gain = 6 PGA Gain = 6 -20 THD =-92dB -20 THD =-96dB -40 SNR = 74dB -40 SNR = 96.7dB f = 8kSPS f = 500SPS FS) -60 DR FS) -60 DR B -80 B ude (d -100 ude (d -1-0800 plit -120 plit Am -140 Am -120 -160 -140 -180 -160 -200 -180 0 500 1000 1500 2000 2500 3000 3500 4000 0 50 100 150 200 250 Frequency (Hz) Frequency (Hz) Figure5. Figure6. CMRRvsFREQUENCY THDvsFREQUENCY -125 -110 Ratio (dB) --112105 n (dBc) --110050 mon-Mode Rejection ---111--1009905050 PPGGAA == 12 PPGGAA == 68 al Harmonic Distortio ---998505 PPGGAA == 12 PPGGAA == 68 Com -85 PPGGAA == 34 PGA = 12 Tot -80 PPGGAA == 34 PGA = 12 fDR= 4kSPS -80 -75 10 100 1k 10 100 1k Frequency (Hz) Frequency (Hz) Figure7. Figure8. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AllplotsatT =+25°C,AVDD=3V,AVSS=0V,DVDD=1.8V,internalVREFP=2.4V,VREFN=AVSS,external A clock=2.048MHz,datarate=500SPS,andgain=6,unlessotherwisenoted. PSRRvsFREQUENCY ADS1198CHANNELPOWER 105 9 f = 4kSPS B) DR 8 Ratio (d 10905 7 AVDD = 5V on W) 6 cti 90 m 5 ply Reje 85 Power ( 4 AVDD = 3V p 3 u 80 Gain = 1 S Gain = 6 Power- 75 GGaaiinn == 23 GGaaiinn == 812 21 Gain = 4 70 0 10 100 1k 0 1 2 3 4 5 6 7 8 Frequency (Hz) Number of Channels Enabled Figure9. Figure10. 16nALEADOFFCURRENTACCURACYDISTRIBUTION INPUTLEAKAGEvsINPUTVOLTAGE 140 120 Mean = 0.78 Occurrences 11208000 s= 0.92 e Current (pA) 1086000 of 60 ag umber 40 ut Leak 40 N p 20 In 20 0 0 -2 -1.3 -0.6 0.12 0.82 1.51 2.21 2.91 3.61 0.1 0.6 1.1 1.6 2.1 2.6 3.1 Error Current (nA) Input Common-Mode Voltage (V) Figure11. Figure12. INPUTLEAKAGECURRENTvsTEMPERATURE 1000 900 800 A) p 700 ent ( 600 Curr 500 e g 400 a k ea 300 L 200 100 0 0 10 20 30 40 50 60 70 Temperature (°C) Figure13. 14 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 OVERVIEW The ADS1194/6/8 are low-power, multichannel, simultaneously-sampling, 16-bit delta-sigma (ΔΣ) analog-to-digital converters (ADCs) with integrated programmable gain amplifiers (PGAs). These devices integrate various ECG-specific functions that make them well-suited for scalable electrocardiogram (ECG), electroencephalography (EEG), and electromyography (EMG) applications. The devices can also be used in high-performance,multichanneldataacquisitionsystemsbypoweringdowntheECG-specificcircuitry. The ADS1194/6/8 have a highly programmable multiplexer that allows for temperature, supply, input short, and RLD measurements. Additionally, the multiplexer allows any of the input electrodes to be programmed as the patient reference drive. The PGA gain can be chosen from one of seven settings (1, 2, 3, 4, 6, 8, and 12). The ADCs in the device offer data rates from 125SPS to 8kSPS. Communication to the device is accomplished using an SPI-compatible interface. The device provides four GPIO pins for general use. Multiple devices can be synchronizedusingtheSTARTpin. The internal reference can be programmed to either 2.4V or 4V. The internal oscillator generates a 2.048MHz clock. The versatile right leg drive (RLD) block allows the user to choose the average of any combination of electrodes to generate the patient drive signal. Lead-off detection can be accomplished either by using a pull-up/pull-down resistor or a current source/sink. An internal ac lead-off detection feature is also available. The device supports both hardware pace detection and software pace detection. The Wilson center terminal (WCT) blockcanbeusedtogeneratetheWCTpointofthestandard12-leadECG. THEORY OF OPERATION This section contains details of the ADS1194/6/8 internal functional elements; see Figure 14. The analog blocks are discussed first, followed by the digital interface. Blocks implementing ECG-specific functions are covered at theend. Throughoutthisdocument,f denotesthefrequencyofthesignalattheCLKpin,t denotestheperiodofthe CLK CLK signal at the CLK pin, f denotes the output data rate, t denotes the time period of the output data, and f DR DR MOD denotesthefrequencyatwhichthemodulatorsamplestheinput. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com DRDY CSSCLKDINDOUT CLKSEL CLK GPIO1 GPIO4GPIO3 GPIO2 PWDN RESET START D DVD GND SPI ntrolOscillator PACEAmplifier 1 G = 0.4 DPACEOUT1 o C VEFPREFN Reference DSADC1 DSADC2 DSADC3 DSADC4 DSADC5 DSADC6 DSADC7 DSADC8 PACEAmplifier 2 G = 0.4 PACEOUT2 R V mperature Sensor Input Power-Supply Signal PGA1 PGA2 PGA3 PGA4 PGA5 PGA6 PGA7 PGA8 RLDAmplifier RLDRLDRLDINVOUTREF Te UX FromWmuxc FromWmuxb FromWmuxa RLDIN M Source C B A Test Signal Off Excitation WCT Lead- D1 S1 D S V V A A D S D S V V A A EMIFilter EMIFilter EMIFilter EMIFilter EMIFilter EMIFilter EMIFilter EMIFilter IN1P IN1N IN2P IN2N IN3P IN3N IN4P IN4N IN5P IN5N IN6P IN6N IN7P IN7N IN8P IN8N WCT ADS1196 and ADS1198 Only ADS1198 Only Figure14. FunctionalBlockDiagram 16 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 EMI FILTER An RC filter at the input acts as an electromagnetic interference (EMI) filter on all of the channels. The –3dB filter bandwidthisapproximately3MHz. INPUT MULTIPLEXER The ADS1194/6/8 input multiplexers are very flexible and provide many configurable signal switching options. Figure 15 shows the multiplexer on a single channel of the device. Note that the device has eight such blocks, one for each channel. TEST_PACE_OUT1, TEST_PACE_OUT2, and RLD_IN are common to all eight blocks. VINP and VINN are separate for each of the eight blocks. This flexibility allows for significant device and sub-system diagnostics, calibration and configuration. Selection of switch settings for each channel is made by writing the appropriate values to the CHnSET[2:0] register (see the CHnSET: Individual Channel Settings section fordetails)andbywritingtheRLD_MEASbitintheCONFIG3register(seetheCONFIG3:ConfigurationRegister 3 subsection of the Register Map section for details). More details of the ECG-specific features of the multiplexer arediscussedintheInputMultiplexersubsectionoftheECG-SpecifcFunctions section. ADS119x INT_TEST MUX TESTP_PACE_OUT1 INT_TEST MUX[2:0] = 101 TestP MUX[2:0] =100 TempP MUX[2:0] =011 MvddP(1) From LoffP MUX[2:0] =000 VINP To PgaP MUX[2:0] =110 MUX[2:0] =010AND EMI RLD_MEAS MUX[2:0] =001 (AVDD + AVSS) Filter 2 MUX[2:0] =111 MUX[2:0] =000 MUX[2:0] =001 VINN To PgaN RLDIN MUX[2:0] =010AND From LoffN RLD_MEAS RLD_REF MUX[2:0] =011 MvddN(1) MUX[2:0] =100 TempN MUX[2:0] =101 TestN INT_TEST TESTN_PACE_OUT2 INT_TEST (1) MVDD monitor voltage supply depends on channel number; see the Supply Measurements (MVDDP, MVDDN) section. Figure15. InputMultiplexerBlockforOneChannel Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com DeviceNoiseMeasurements Setting CHnSET[2:0] = 001 sets the common-mode voltage of (AVDD – AVSS)/2 to both inputs of the channel. Thissettingcanbeusedtotesttheinherentnoiseofthedeviceintheusersystem. TestSignals(TestPandTestN) Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in subsystem verification at power-up.Thisfunctionalityallowstheentiresignalchaintobetestedout.Althoughthetestsignalsaresimilarto the CAL signals described in the IEC60601-2-51 specification, this feature is not intended for use in compliance testing. Control of the test signals is accomplished through register settings (see the CONFIG2: Configuration Register 2 subsection in the Register Map section for details). TEST_AMP controls the signal amplitude and TEST_FREQ controlsswitchingattherequiredfrequency. The test signals are multiplexed and transmitted out of the device at the TESTP_PACE_OUT1 and TESTN_PACE_OUT2 pins. A bit register, INT_TEST = 0, deactivates the internal test signals so that the test signal can be driven externally. This feature allows the calibration of multiple devices with the same signal. The test signal feature cannot be used in conjunction with the external hardware pace feature (see the External HardwareApproachsubsectionoftheECG-SpecificFunctionssectionfordetails). AuxiliaryDifferentialInput(TESTP_PACE_OUT1,TESTN_PACE_OUT2) When hardware pace detect is not used, the TESTP_PACE_OUT1 and TESPN_PACE_OUT2 signals can be used as a multiplexed differential input channel. These inputs can be multiplexed to any of the eight channels. The performance of the differential input signal fed through these pins is identical to the normal channel performance. TemperatureSensor(TempP,TempN) The ADS1194/6/8 contain an on-chip temperature sensor. This sensor uses two internal diodes with one diode having a current density 16x that of the other, as shown in Figure 16. The difference in current densities of the diodesyieldsadifferenceinvoltagethatisproportionaltoabsolutetemperature. As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal device temperature tracks the PCB temperature closely. Note that self-heating of the ADS1194/6/8 causes a higher readingthanthetemperatureofthesurroundingPCB. The scale factor of Equation 1 converts the temperature reading to °C. Before using this equation, the temperaturereadingcodemustfirstbescaledtoμV. Temperature Reading (mV)-145,300mV Temperature (°C) = + 25°C 490mV/°C (1) Temperature Sensor Monitor AVDD 1x 2x To MUX TempP To MUX TempN 8x 1x AVSS Figure16. MeasurementoftheTemperatureSensorintheInput 18 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 SupplyMeasurements(MVDDP,MVDDN) Setting CHnSET[2:0] = 011 sets the channel inputs to different supply voltages of the device. For channels 1, 2, 5, 6, 7, and 8, (MVDDP – MVDDN) is [0.5 × (AVDD – AVSS)]; for channel 3 and 4, (MVDDP – MVDDN) is DVDD/2.NotethattoavoidsaturatingthePGAwhilemeasuringpowersupplies,thegainmustbesetto'1'. Lead-OffExcitationSignals(LoffP,LoffN) The lead-off excitation signals are fed into the multiplexer before the switches. The comparators that detect the lead-off condition are also connected to the multiplexer block before the switches. For a detailed description of thelead-offblock,refertotheLead-OffDetectionsubsectionintheECG-SpecificFunctionssection. AuxiliarySingle-EndedInput TheRLD_INpinisprimarilyusedforroutingtherightlegdrivesignaltoanyoftheelectrodesincasetherightleg drive electrode falls off. However, the RLD_IN pin can be used as a multiple single-ended input channel. The signalattheRLD_INpincanbemeasuredwithrespecttothevoltageattheRLD_REFpinusinganyoftheeight channels. This measurement is done by setting the channel multiplexer setting to '010' and the RLD_MEAS bit of theCONFIG3registerto'1'. ANALOG INPUT The analog input to the ADS1198 is fully differential. Assuming PGA = 1, the differential input (INP – INN) can spanbetween–V to+V .NotethattheabsoluterangeforINPandINNmustbebetweenAVSS –0.3Vand REF REF AVDD + 0.3 V. Refer to Table 6 for an explanation of the correlation between the analog input and the digital codes. There are two general methods of driving the analog input of the ADS1198: single-ended or differential, asshowninFigure17andFigure18.Whentheinputissingle-ended,theINNinputisheldatthecommon-mode voltage, preferably at mid-supply. The INP input swings around the same common voltage and the peak-to-peak amplitude is the (common-mode + 1/2V ) and the (common-mode – 1/2V ). When the input is differential, REF REF the common-mode is given by (INP + INN)/2. Both the INP and INN inputs swing from (common-mode + 1/2V REF to common-mode – 1/2V ). For optimal performance, it is recommended that the ADS1198 be used in a REF differentialconfiguration. -1/2VREFto ADS1198 VREF +1/2VREF peak-to-peak ADS1198 Common Common V Voltage Voltage peRaEFk-to-peak Single-Ended Input Differential Input Figure17. MethodsofDrivingtheADS1198:Single-EndedorDifferential CM + 1/2V REF +1/2VREF INP CM Voltage -1/2V INN = CM Voltage REF CM-1/2VREF t Single-Ended Inputs INP +V CM + 1/2V REF REF CM Voltage CM-1/2V REF INN -VREF t Differential Inputs (INP) + (INN) Common-Mode Voltage (Differential Mode) = , Common-Mode Voltage (Single-Ended Mode) =INN. 2 Input Range (Differential Mode) = (AINP-AINN) = V -(-V ) = 2V . REF REF REF Figure18. UsingtheADS1198intheSingle-EndedandDifferentialInputModes Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com PGA SETTINGS AND INPUT RANGE The PGA is a differential input/differential output amplifier, as shown in Figure 19. It has seven gain settings (1, 2, 3, 4, 6, 8, and 12) that can be set by writing to the CHnSET register (see the CHnSET: Individual Channel Settings subsection of the Register Map section for details). The ADS1194/6/8 have CMOS inputs and hence have negligible current noise. Table 4 shows the typical values of bandwidths for various gain settings. Note that Table 4 shows the small-signal bandwidth. For large signals, the performance is limited by the slew rate of the PGA. From MuxP PgaP R 2 50kW R 1 20kW To ADC (for Gain = 6) R 2 50kW PgaN From MuxN Figure19. PGAImplementation Table4.PGAGainversusBandwidth NOMINALBANDWIDTHATROOM GAIN TEMPERATURE(kHz) 1 158 2 97 3 85 4 64 6 43 8 32 12 21 The resistor string of the PGA that implements the gain has 120kΩ of resistance for a gain of 6. This resistance provides a current path across the outputs of the PGA in the presence of a differential input signal. This current isinadditiontothequiescentcurrentspecifiedforthedeviceinthepresenceofdifferentialsignalatinput. InputCommon-ModeRange The usable input common-mode range of the front end depends on various parameters, including the maximum differentialinputsignal,supplyvoltage,PGAgain,etc.ThisrangeisdescribedinEquation2: Gain V Gain V AVDD-0.2- MAX_DIFF > CM > AVSS + 0.2 + MAX_DIFF 2 2 where: V =maximumdifferentialsignalattheinputofthePGA MAX_DIFF CM=common-moderange (2) Forexample: IfV =3V,gain=6,andV =350mV DD MAX_DIFF Then1.25V<CM <1.75V 20 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 InputDifferentialDynamicRange The differential (INP – INN) signal range depends on the analog supply and reference used in the system. This rangeisshowninEquation3. V ±V Max (INP-INN) < REF ; Full-Scale Range = REF Gain Gain (3) The 3V supply, with a reference of 2.4V and a gain of 6 for ECGs, is optimized for power with a differential input signal of approximately 300mV. For higher dynamic range, a 5V supply with a reference of 4V (set by the VREF_4VbitoftheCONFIG3register)canbeusedtoincreasethedifferentialdynamicrange. ADCΔΣModulator Each channel of the ADS1194/6/8 has a 16-bit ΔΣ ADC. This converter uses a second-order modulator optimized for low-power applications. The modulator samples the input signal at the rate of f = f /8. As in MOD CLK the case of any ΔΣ modulator, the noise of the ADS1194/6/8 is shaped until f /2, as shown in Figure 20. The MOD on-chip digital decimation filters explained in the next section can be used to filter out the noise at higher frequencies. These on-chip decimation filters also provide antialias filtering. This feature of the ΔΣ converters drasticallyreducesthecomplexityoftheanalogantialiasingfiltersthataretypicallyneededwithnyquistADCs. 0 −10 −20 B) −30 sity (d −−5400 n −60 e D −70 al −80 ctr −90 pe−100 S wer −−112100 Po−130 −140 −150 −160 0.001 0.01 0.1 1 Normalized Frequency (fIN/fMOD) G001 Figure20. ModulatorNoiseSpectrumUpTo0.5×f MOD Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com DIGITAL DECIMATION FILTER The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for higherdatarates.HigherdataratesaretypicallyusedinECGapplicationsforimplementsoftwarepacedetection andaclead-offdetection. The digital filter on each channel consists of a third-order sinc filter. The decimation ratio on the sinc filters can be adjusted by the DR bits in the CONFIG1 register (see the Register Map section for details). This setting is a globalsettingthataffectsallchannelsand,therefore,inadeviceallchannelsoperateatthesamedatarate. SincFilterStage(sinx/x) The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the filter from the modulator at the rate of f . The sinc filter attenuates the high-frequency noise of the modulator, MOD then decimates the data stream into parallel data. The decimation rate affects the overall data rate of the converter. Equation4showsthescaledZ-domaintransferfunctionofthesincfilter. 1-Z-N 3 H(z) = 1-Z-1 (4) ThefrequencydomaintransferfunctionofthesincfilterisshowninEquation5. 3 Npf sin f MOD H(f) = pf N´sin f MOD where: N=decimationratio (5) 22 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these frequencies, the filter has infinite attenuation. Figure 21 shows the frequency response of the sinc filter and Figure 22 shows the roll-off of the sinc filter. With a step change at input, the filter takes 3 × t to settle. The DR fourth DRDY pulse is settled data. After a rising edge of the START signal, the filter takes t time to give the SETTLE first data output. The settling time of the filters at various data rates are discussed in the START subsection of the SPI Interface section. Figure 23 and Figure 24 show the filter transfer function until f /2 and f /16, MOD MOD respectively, at different data rates. Figure 25 shows the transfer function extended until 4 × f . It can be seen MOD that the passband of the ADS1194/6/8 repeats itself at every f . The input R-C anti-aliasing filters in the MOD system should be chosen such that any interference in frequencies around multiples of f are attenuated MOD sufficiently. 0 0 -20 -0.5 -40 -1.0 B) -60 B) d d n ( n ( -1.5 ai -80 ai G G -2.0 -100 -120 -2.5 -140 -3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 Normalized Frequency (f /f ) Normalized Frequency (f /f ) IN DR IN DR Figure21.SincFilterFrequencyResponse Figure22.SincFilterRoll-Off 0 0 DR[2:0] = 110 DR[2:0] = 110 -20 -20 DR[2:0] = 000 DR[2:0] = 000 -40 -40 B) -60 B) -60 d d n ( n ( Gai -80 Gai -80 -100 -100 -120 -120 -140 -140 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 Normalized Frequency (f /f ) Normalized Frequency (f /f ) IN MOD IN MOD Figure23.TransferFunctionofOn-Chip Figure24.TransferFunctionofOn-Chip DecimationFiltersUntilf /2 DecimationFiltersUntilf /16 MOD MOD 10 DR[2:0] = 000 DR[2:0] = 110 -10 -30 B) -50 d n ( Gai -70 -90 -110 -130 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Normalized Frequency (f /f ) IN MOD Figure25.TransferFunctionofOn-ChipDecimationFilters Until4f forDR[2:0]=000andDR[2:0]=110 MOD Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com REFERENCE Figure 26 shows a simplified block diagram of the internal reference of the ADS1194/6/8. The reference voltage isgeneratedwithrespecttoAVSS.Whenusingtheinternalvoltagereference,connectVREFNtoAVSS. 22mF VCAP1 R1(1) Bandgap 2.4V or 4V VREFP R3(1) 10mF R2(1) VREFN AVSS To ADC Reference Inputs (1) ForV =2.4:R1=12.5kΩ,R2=25kΩ,andR3=25kΩ.ForV =4V:R1=10.5kΩ,R2=15kΩ,andR3=35kΩ. REF REF Figure26. InternalReference The external band-limiting capacitors determine the amount of reference noise contribution. For high-end ECG systems, the capacitor values should be chosen such that the bandwidth is limited to less than 10Hz, so that the reference noise does not dominate the system noise. When using a 3V analog supply, the internal reference must be set to 2.4V. In case of a 5V analog supply, the internal reference can be set to 4V by setting the VREF_4VbitintheCONFIG2register. Alternatively,theinternalreferencebuffercanbepowereddownandVREFPcanbeappliedexternally.Figure27 shows a typical external reference drive circuitry. Power-down is controlled by the PD_REFBUF bit in the CONFIG3 register. This power-down is also used to share internal references when two devices are cascaded. Bydefaultthedevicewakesupinexternalreferencemode. 100kW 10pF +5V 0.1mF 100W 100W OPA211 To VREFP Pin +5V VIN OUT 10mF 0.1mF REF5025 22mF 100mF 22mF TRIM Figure27. ExternalReferenceDriver 24 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 CLOCK The ADS1194/6/8 provide two different methods for device clocking: internal and external. Internal clocking is ideally suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room temperature. Over the specified temperature range the accuracy varies; see the Electrical Characteristics. Clock selectioniscontrolledbytheCLKSELpinandtheCLK_ENregisterbit. The CLKSEL pin selects either the internal or external clock. The CLK_EN bit in the CONFIG1 register enables and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 5. The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. It is recommended that duringpower-downtheexternalclockbeshutdowntosavepower. Table5.CLKSELPinandCLK_ENBit CONFIG1.CLK_EN CLKSELPIN BIT CLOCKSOURCE CLKPINSTATUS 0 X Externalclock Input:externalclock 1 0 Internalclockoscillator 3-state 1 1 Internalclockoscillator Output:internalclockoscillator DATA FORMAT The ADS1194/6/8 outputs 16 bits of data per channel in binary twos complement format, MSB first. The LSB has a weight of V /(215 – 1). A positive full-scale input produces an output code of 7FFFh and the negative REF full-scale input produces an output code of 8000h. The output clips at these codes for signals exceeding full-scale.Table6summarizestheidealoutputcodesfordifferentinputsignals. Table6.IdealInputCodeversusInputSignal(1) INPUTSIGNAL,V IN (AINP–AINN) IDEALOUTPUTCODE(2) ≥V 7FFFh REF +V /(215–1) 0001h REF 0 0000h –V /(215–1) FFFFh REF ≤–V (215/215–1) 8000h REF (1) Assumesgain=1. (2) Excludeseffectsofnoise,linearity,offset,andgainerror. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com SPI INTERFACE The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads conversion data, reads and writes registers, and controls the ADS1194/6/8 operation. The DRDY output is used asastatussignaltoindicatewhendataareready.DRDYgoeslowwhennewdataareavailable. ChipSelect(CS) Chip select (CS) selects the ADS1194/6/8 for SPI communication. CS must remain low for the entire duration of the serial communication. After the serial communication is finished, always wait eight or more t cycles before CLK taking CS high. When CS is taken high, the serial interface is reset, SCLK and DIN are ignored, and DOUT enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of whether CS is highorlow. SerialClock(SCLK) SCLK is the serial peripheral interface (SPI) serial clock. It is used to shift in commands and shift out data from the device. The serial clock (SCLK) features a Schmitt-triggered input and clocks data on the DIN and DOUT pinsintoandoutoftheADS1194/6/8.Eventhoughtheinputhashysteresis,itisrecommendedtokeepSCLKas clean as possible to prevent glitches from accidentally shifting the data. The absolute maximum limit for SCLK is specified in the Serial Interface Timing table. When shifting in commands with SCLK, make sure that the entire set of SCLKs is issued to the device. Failure to do so results in the device being placed into an unknown state, requiringCStobetakenhightorecover. For a single device, the minimum speed needed for the SCLK depends on the number of channels, number of bitsofresolution,andoutputdatarate.(Formultiplecascadeddevices,seetheStandardModesubsectionofthe MultipleDeviceConfigurationsection.) t <(t –4t )/(N ×N +24) SCLK DR CLK BITS CHANNELS For example, if the ADS1198 is used in a 500SPS mode (8 channels, 16-bit resolution), the minimum SCLK speedis80kHz. Data retrieval can be done either by putting the device in RDATAC mode or by issuing a RDATA command for data on demand. The above SCLK rate limitation applies to RDATAC. For the RDATA command, the limitation applies if data must be read in between two consecutive DRDY signals. The above calculation assumes that therearenoothercommandsissuedinbetweendatacaptures. DataInput(DIN) The data input pin (DIN) is used along with SCLK to send data to the ADS1194/6/8 (opcode commands and registerdata).ThedevicelatchesdataonDINonthefallingedgeofSCLK. 26 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 DataOutput(DOUT) Thedataoutputpin(DOUT)isusedwithSCLKtoreadconversionandregisterdatafromtheADS1194/6/8.Data on DOUT are shifted out on the rising edge of SCLK. DOUT goes to a high-impedance state when CS is high. In read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line also indicates when new data are available. This feature can be used to minimize the number of connections between the device and the system controller. The START signal must be high or the START command must be issuedbeforeretrievingdatafromthedevice. Figure28showsthedataoutputprotocolforADS1198. DRDY CS SCLK 152 SCLKs DOUT STAT CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 24-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit DIN Figure28. SPIBusDataOutputfortheADS1198(8-Channels) DataRetrieval Data retrieval can be accomplished in one of two methods. The read data continuous command can be used to setthedeviceinamodetoreadthedatacontinuouslywithoutsendingopcodes.Thereaddatacommandcanbe used to read just one data output from the device (see the SPI Command Definitions section for more details). TheconversiondataarereadbyshiftingthedataoutonDOUT.TheMSBofthedataonDOUTisclockedouton the first SCLK rising edge. DRDY returns to high on the first SCLK falling edge. DIN should remain low for the entirereadoperation. The number of bits in the data output depends on the number of channels and the number of bits per channel. For the ADS1198, the number of data outputs is (24 status bits + 16 bits × 8 channels = 152 bits) for all data rates. The format of the 24 status bits is: (1100 + LOFF_STATP + LOFF_STATN + bits[4:7] of the GPIO register). The data format for each channel data are twos complement and MSB first. When channels are powered down using the user register setting, the corresponding channel output is set to '0'. However, the sequence of channel outputs remains the same. For the ADS1194 and the ADS1196, the last four and two channel outputs shown in Figure 28 are zeros. Status and GPIO register bits are loaded into the 24-bit status word2t sbeforeDRDYgoeslow. CLK The ADS1194/6/8 also provide a multiple readback feature. The data can be read out multiple times by simply giving more SCLKs, in which case the MSB data byte repeats after reading the last byte. The DAISY_EN bit in CONFIG1registermustbesetto'1'formultiplereadbacks. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com DataReady(DRDY) DRDY is an output. When it transitions low, new conversion data are ready. The CS signal has no effect on the data ready signal. The behavior of DRDY is determined by whetehr the device is in RDATAC mode or the RDATA command is being used to read data on demand. (See the RDATAC: Read Data Continuous and RDATA: Read Data subsections of the SPI Command Definitions section for further detials). Regardless of the status of the CS signal, a rising edge on SCLK pulls DRDY high. Hence, when using multiple devices in the SPI bus, it is recommended that SCLK be gated with CS. When reading data with the RDATA command, the read operation can overlap the occurrence of the next DRDY without data corruption. The START pin or the START command is used to place the device either in normal data capture mode or pulse data capture mode. Figure 29 shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an ADS1198). DOUT is latched at the rising edge of SCLK. DRDY is pulled high at the falling edge of SCLK. Note that DRDY goes high on the first falling edge SCLK regardless of whether data are being retrieved from the device or a command isbeingsentthroughtheDINpin. DRDY DOUT Bit 151 Bit 150 Bit 149 SCLK Figure29. DRDYwithDataRetrieval(CS=0inRDATAMode) GPIO The ADS1194/6/8 have a total of four general-purpose digital I/O (GPIO) pins available in the normal mode of operation. The digital I/O pins are individually configurable as either inputs or as outputs through the GPIOC bits register. The GPIOD bits in the GPIO register control the level of the pins. When reading the GPIOD bits, the data returned are the level of the pins, whether they are programmed as inputs or outputs. When the GPIO pin is configured as an input, a write to the corresponding GPIOD bit has no effect. When configured as an output, a writetotheGPIODbitsetstheoutputvalue. If configured as inputs, these pins must be driven (do not float). The GPIO pins are set as inputs after power-on orafterareset.Figure30showstheGPIOportstructure. GPIO1 can be used as the PACEIN signal; GPIO2 is multiplexed with RESP_BLK signal; GPIO3 is multiplexed withtheRESPsignal;andGPIO4ismultiplexedwiththeRESP_PHsignal. GPIO Data (read) GPIO Pin GPIO Data (write) GPIO Control Figure30. GPIOPortPin Power-Down(PWDN) When PWDN is pulled low, all on-chip circuitry is powered down. To exit power-down mode, take the PWDN pin high. Upon exiting from power-down mode, the internal oscillator and the reference require a wake-up time. It is recommendedthatduringpower-downtheexternalclockisshutdowntosavepower. 28 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 Reset(RESET) There are two methods to reset the ADS1194/6/8: pull the RESET pin low, or send the RESET opcode command. When using the RESET pin, take it low to force a reset. Make sure to follow the minimum pulse width timing specifications before taking the RESET pin back high. The RESET command takes effect on the eighth SCLK falling edge of the opcode command. On reset it takes 18 CLK cycles to complete initialization of the configuration registers to the default states and start the conversion cycle. Note that an internal RESET is automatically issued to the digital filter whenever registers CONFIG1 and RESP are set to a new value with a WREGcommand. START The START pin must be set high for at least two t s, or the START command sent, to begin conversions. CLK When START is low, or if the START command has not been sent, the device does not issue a DRDY signal (conversionsarehalted). When using the START opcode to control conversion, hold the START pin low. The ADS1194/6/8 feature two modes to control conversion: continuous mode and single-shot mode. The mode is selected by SINGLE_SHOT (bit 3 of the CONFIG4 register). In multiple device configurations the START pin is used to synchronize devices (seetheMultipleDeviceConfigurationsubsectionoftheSPIInterface sectionformoredetails). SettlingTime The settling time (t ) is the time it takes for the converter to output fully settled data when START signal is SETTLE pulled high. Once START is pulled high, DRDY is also pulled high. The next falling edge of DRDY indicates that data are ready. Figure 31 shows the timing diagram and Table 7 shows the settling time for different data rates. The settling time depends on f and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1 CLK register). Table 6 describes the settling time as a function of t . Note that when START is held high and there CLK is a step change in the input signal, it takes 3 × t for the filter to settle to the new value. Settled data are DR available on the fourth DRDY pulse. This time must be considered when trying to measure narrow pace pulses forpacerdetection. START Pin t SETTLE or D IN START Opcode t DR 4/f CLK DRDY Figure31. SettlingTime Table7.SettlingTimeforDifferentDataRates DR[2:0] SETTLINGTIME UNIT 000 1160 t CLK 001 2312 t CLK 010 4616 t CLK 011 9224 t CLK 100 18440 t CLK 101 36872 t CLK 110 73736 t CLK Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com ContinuousMode Conversions begin when the START pin is taken high for at least two t s or when the START opcode CLK command is sent. As seen in Figure 32, the DRDY output goes high when conversions are started and goes low when data are ready. Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted. When the START pin is pulled low or the stop command is issued, the conversion in progress is allowed to complete. Figure 33 and Table 8 show the required timing of DRDY to the START pin and the START/STOP opcode commands when controlling conversions in this mode. To keep the converter running continuously, the START pin can be permanently tied high. Note that when switching from pulse mode to continuous mode, the START signal is pulsed or a STOP command must be issued followed by a START command. Thisconversionmodeisidealforapplicationsthatrequireafixedcontinuousstreamofconversionresults. START Pin or or START(1) STOP(1) DIN Opcode Opcode t DR t DRDY SETTLE (1) STARTandSTOPopcodecommandstakeeffectontheseventhSCLKfallingedge. Figure32. ContinuousConversionMode DRDYand DOUT tSDSU t DSHD START Pin or STOP Opcode STOP(1) STOP(1) (1) STARTandSTOPcommandstakeeffectontheseventhSCLKfallingedgeattheendoftheopcodetransmission. Figure33. STARTtoDRDYTiming Table8.TimingCharacteristicsforFigure33(1) SYMBOL DESCRIPTION MIN UNIT STARTpinloworSTOPopcodetoDRDYsetuptime t 16 1/f SDSU tohaltfurtherconversions CLK STARTpinloworSTOPopcodetocompletecurrent t 16 1/f DSHD conversion CLK (1) STARTandSTOPcommandstakeeffectontheseventhSCLKfallingedgeattheendoftheopcodetransmission. 30 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 Single-ShotMode The single-shot mode is enabled by setting the SINGLE_SHOT bit in CONFIG4 register to '1'. In single-shot mode, the ADS1194/6/8 perform a single conversion when the START pin is taken high for at least two t s, or CLK when the START opcode command is sent. As seen in Figure 34, when a conversion is complete, DRDY goes low and further conversions are stopped. Regardless of whether the conversion data are read or not, DRDY remains low. To begin a new conversion, take the START pin low and then back high, or transmit the START opcode again. Note that when switching from continuous mode to pulse mode, make sure the START signal is pulsedorissueaSTOPcommandfollowedbyaSTARTcommand. START t SETTLE 4 /f 4 /f CLK Data Updating CLK DRDY Figure34. DRDYwithNoDataRetrievalinSingle-ShotMode This conversion mode is provided for applications that require a non-standard or non-continuous data rate. Issuing a START command or toggling the START pin high resets the digital filter, effectively dropping the data rate by a factor of four. This mode leaves the system more susceptible to aliasing effects, requiring more complex analog or digital filtering. Loading on the host processor increases because it must toggle the START pinorsendaSTARTcommandtoinitiateanewconversioncycle. MULTIPLE DEVICE CONFIGURATION The ADS1194/6/8 are designed to provide configuration flexibility when multiple devices are used in a system. The SPI interface typically needs four signals: DIN, DOUT, SCLK, and CS. With one additional chip select signal per device, multiple devices can be connected together. The number of signals needed to interface n devices is 3+n. The right-leg drive amplifiers can be daisy-chained as explained in the RLD Configuration with Multiple Devices subsection of the ECG-Specific Functions section. To use the internal oscillator in a daisy-chain configuration, one of the devices must be set as the master for the clock source with the internal oscillator enabled (CLKSEL pin = 1) and the internal oscillator clock brought out of the device by setting the CLK_EN register bit. This master deviceclockisusedastheexternalclocksourcefortheotherdevices. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com When using multiple devices, the devices can be synchronized with the START signal. The delay from START to the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more details on the settling times). Figure 35 shows the behavior of two devices when synchronized with the START signal. There are two ways to connect multiple devices with a optimal number of interface pins: cascade mode and daisy-chainmode. ADS1198 1 START START1 DRDY DRDY1 CLK CLK ADS1198 2 START2 DRDY DRDY2 CLK CLK t SETTLE START DRDY 1 DRDY 2 Figure35. SynchronizingMultipleConverters 32 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 StandardMode Figure 36a shows a configuration with two devices cascaded together. One of the devices is an ADS1198 (eight-channel) and the other is an ADS1194 (four-channel). Together, they create a system with 12 channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected by the corresponding CS being driven to logic 1, the DOUT of this device is high-impedance. This structure allows the other device to take control of the DOUT bus. This configuration method is suitable for the majority of applications. DAISY-CHAIN MODE Daisy-chain mode is enabled by setting the DAISY_EN bit in the CONFIG1 register. Figure 36b shows the daisy-chain configuration. In this mode SCLK, DIN, and CS are shared across multiple devices. The DOUT of onedeviceishookeduptotheDAISY_INoftheotherdevice,therebycreatingachain.OneextraSCLKmustbe issued in between each data set. Also, when using daisy-chain mode the multiple readback feature is not available.ShorttheDAISY_INpintodigitalgroundifnotused.Figure2(Daisy-ChainInterfaceTiming)describes therequiredtimingfortheADS1198showninFigure36.DatafromtheADS1198appearfirstonDOUT,followed byadon’tcarebit,andfinallybythestatusanddatawordsfromtheADS1194. START(1) START DRDY INT START(1) START DRDY INT CLK CLK CS GPO0 CLK CLK CS GPO GPO1 ADS1198 SCLK SCLK ADS1198 SCLK SCLK (Device 0) DIN MOSI (Device 0) DIN MOSI DOUT MISO DAISY_IN0 DOUT0 MISO Host Processor Host Processor START DRDY DOUT1 DRDY CLK CS START CS SCLK SCLK CLK ADS1194 DIN DIN ADS1194 (Device 1) DOUT (Device 1) DAISY_IN1 0 a) Standard Configuration b) Daisy-Chain Configuration (1) Toreducepincount,settheSTARTpinlowandusetheSTARTserialcommandtosynchronizeandstartconversions. Figure36. MultipleDeviceConfigurations In a case where all devices in the chain operate in the same register setting, DIN can be shared as well and thereby reduce the SPI communication signals to four, regardless of the number of devices. However, because the individual devices cannot be programmed, the RLD driver cannot be shared among the multiple devices. Furthermore,anexternalclockmustbeused. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com Note that from Figure 2, the SCLK rising edge shifts data out of the ADS1194/6/8 on DOUT. The SCLK rising edge is also used to latch data into the device DAISY_IN pin down the chain. This architecture allows for a faster SCLK rate speed, but it also makes the interface sensitive to board level signal delays. The more devices in the chain, the more challenging it could become to adhere to setup and hold times. A star pattern connection of SCLK to all devices, minimizing length of DOUT, and other PCB layout techniques help. Placing delay circuits suchasbuffersbetweenDOUTandDAISY_INarewaystomitigatethischallenge.Oneotheroptionistoinserta D flip-flop between DOUT and DAISY_IN clocked on an inverted SCLK. Note also that daisy-chain mode requires some software overhead to recombine data bits spread across byte boundaries. Figure 37 shows a timingdiagramforthedaisy-chainmode. DOUT 1 MSB LSB DAISY_IN 1 1 0 SCLK 1 2 3 152 153 154 155 241 DOUT 0 MSB0 LSB0 XX MSB1 LSB1 Da ta from first device (ADS1198) Da ta from seconddevice (ADS1194) Figure37. Daisy-ChainTiming The maximum number of devices that can be daisy-chained depends on the data rate at which the device is beingoperated.ThemaximumnumberofdevicescanbeapproximatelycalculatedwithEquation6. f N = SCLK DEVICES f (N )(N ) + 24 DR BITS CHANNELS where: N =deviceresolution(dependsondatarate),and BITS N =numberofchannelsinthedevice(4,6,or8). (6) CHANNELS For example, when the ADS1198 (eight-channel, 16-bit version) is operated at a 2kSPS data rate with a 4MHz f ,15devicescanbedaisy-chained. SCLK 34 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 SPI COMMAND DEFINITIONS The ADS1194/6/8 provide flexible configuration control. The opcode commands, summarized in Table 9, control and configure the operation of the ADS1194/6/8. The opcode commands are stand-alone, except for the register read and register write operations that require a second command byte plus data. CS can be taken high or held low between opcode commands but must stay low for the entire command operation (especially for multi-byte commands). System opcode commands and the RDATA command are decoded by the ADS1194/6/8 on the seventh falling edge of SCLK. The register read/write opcodes are decoded on the eighth SCLK falling edge. Be suretofollowSPItimingrequirementswhenpullingCShighafterissuingacommand. Table9.CommandDefinitions COMMAND DESCRIPTION FIRSTBYTE SECONDBYTE SystemCommands WAKEUP Wake-upfromstandbymode.NOPcommandinnormalmode. 00000010(02h) STANDBY Enterstandbymode 00000100(04h) RESET Resetthedevice 00000110(06h) START Start/restart(synchronize)conversions 00001000(08h) STOP Stopconversion 00001010(0Ah) DataReadCommands EnableReadDataContinuousmode. RDATAC Thismodeisthedefaultmodeatpower-up.(1) 00010000(10h) SDATAC StopReadDataContinuouslymode 00010001(11h) RDATA Readdatabycommand;supportsmultiplereadback. 00010010(12h) RegisterReadCommands RREG Readnnnnnregistersstartingataddressrrrr 001rrrrr(2xh)(2) 000nnnnn (2) WREG Writennnnnregistersstartingataddressrrrr 010rrrrr(4xh)(2) 000nnnnn (2) (1) WheninRDATACmode,theRREGcommandisignored. (2) nnnnn=numberofregisterstoberead/written–1.Forexample,toread/writethreeregisters,setnnnn=0(0010).rrrr=starting registeraddressforread/writeopcodes. WAKEUP:ExitSTANDBYMode This opcode exits the low-power standby mode; see the STANDBY: Enter STANDBY Mode subsection of the SPI Command Definitions section. Time is required when exiting standby mode (see the Electrical Characteristics for details). There are no restrictions on the SCLK rate for this command and it can be issuedanytime.Anyfollowingcommandmustbesentafter4CLKcycles. STANDBY:EnterSTANDBYMode This opcode command enters the low-power standby mode. All parts of the circuit are shut down except for the reference section. The standby mode power consumption is specified in the Electrical Characteristics. There are norestrictionsontheSCLKrateforthiscommandanditcanbeissuedanytime. RESET:ResetRegisterstoDefaultValues This command resets the digital filter cycle and returns all register settings to the default values. See the Reset (RESET) subsection of the SPI Interface section for more details. There are no restrictions on the SCLK rate for this command and it can be issued any time. It takes 18 CLK cycles to execute the RESET command. Avoidsendinganycommandsduringthistime. START:StartConversions This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions are in progress this command has no effect. The STOP opcode command is used to stop conversions. If the STARTcommandisimmediatelyfollowedbyaSTOPcommandthenhaveagapof4CLKcyclesbetweenthem. When the START opcode is sent to the device, keep the START pin low until the STOP command is issued. (See the START subsection of the SPI Interface section for more details.) There are no restrictions on the SCLKrateforthiscommandanditcanbeissuedanytime. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com STOP:StopConversions This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP command is sent, the conversion in progress completes and further conversions are stopped. If conversions are alreadystopped,thiscommandhasnoeffect.TherearenorestrictionsontheSCLKrateforthiscommandandit canbeissuedanytime. RDATAC:ReadDataContinuous This opcode enables the output of conversion data on each DRDY without the need to issue subsequent read data opcodes. This mode places the conversion data in the output register and may be shifted out directly. The readdatacontinuousmodeisthedefaultmodeofthedeviceandthedevicedefaultsinthismodeonpower-up. RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, a SDATAC command must be issued before any other commands can be sent to the device. There is no restriction on the SCLK rate for this command. However, the subsequent data retrieval SCLKs or the SDATAC opcodecommandshouldwaitatleast4CLKcycles.ThetimingforRDATACisshowninFigure38.AsFigure38 shows, there is a keep out zone of 4 CLK cycles around the DRDY pulse where this command cannot be issued in.Ifnodataareretrievedfromthedevice,DOUTandDRDYbehavesimilarlyinthismode.Toretrievedatafrom the device after RDATAC command is issued, make sure either the START pin is high or the START command is issued. Figure 38 shows the recommended way to use the RDATAC command. RDATAC is ideally suited for applicationssuchasdataloggersorrecorderswhereregistersaresetonceanddonotneedtobere-configured. START DRDY CS SCLK t UPDATE DIN RDATAC Opcode Hi-Z DOUT Status Register + 8-Channel Data (152 Bits) Next Data (1) t =4/f .Donotreaddataduringthistime. UPDATE CLK Figure38. RDATACUsage SDATAC:StopReadDataContinuous This opcode cancels the Read Data Continuous mode. There is no restriction on the SCLK rate for this command,butthefollowingcommandmustwaitfor4CLKcycles. 36 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 RDATA:ReadData Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode). There is no restriction on the SCLK rate for this command, and there is no wait time needed for the subsequent commands or data retrieval SCLKs. To retrieve data from the device after RDATA command is issued, make sure either the START pin is high or the START command is issued. When reading data with the RDATA command, the read operation can overlap the occurrence of the next DRDY without data corruption. Figure 39 shows the recommended ways to use the RDATA command. RDATA is best suited for ECG and EEG type systems,whereregistersettingmustbereadorchangedoftenbetweenconversioncycles. START DRDY CS SCLK RDATA Opcode RDATA Opcode DIN Hi-Z DOUT StatusRegister+ 8-Channel Data (152Bits) Figure39. RDATAUsage SendingMulti-ByteCommands The ADS1194/6/8 serial interface decodes commands in bytes and requires four CLK cycles to decode and execute. Therefore, when sending multi-byte commands, a period of four CLKs must separate the end of one byte(oropcode)andthenext. Assume CLK is 2.048MHz, then t (4 t ) is 1.96µs. When SCLK is 16MHz, one byte can be transferred SDECODE CLK in 500ns. This byte transfer time does not meet the t specification; therefore, a delay must be inserted so SDECODE the end of the second byte arrives 1.46µs later. If SCLK is 4MHz, one byte is transferred in 2µs. Because this transfer time exceeds the t specification, the processor can send subsequent bytes without delay. In this SDECODE laterscenario,theserialportcanbeprogrammedtoceasesingle-bytetransferpercycletomultiplebytes. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com RREG:ReadFromRegister Thisopcodereadsregisterdata.TheRegisterReadcommandisatwo-byteopcodefollowedbytheoutputofthe register data. The first byte contains the command opcode and the register address. The second byte of the opcodespecifiesthenumberofregisterstoread–1. Firstopcodebyte:0010rrrr,whererrrristhestartingregisteraddress. Secondopcodebyte:000nnnnn,wherennnnnisthenumberofregisterstoread– 1. The17thSCLKrisingedgeoftheoperationclocksouttheMSBofthefirstregister,asshowninFigure40.When the device is in read data continuous mode it is necessary to issue a SDATAC command before RREG command can be issued. RREG command can be issued any time. However, because this command is a multi-byte command, there are restrictions on the SCLK rate depending on the way the SCLKs are issued. See the Serial Clock (SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for theentirecommand. CS(1) 1 9 17 25 SCLK DIN OPCODE 1 OPCODE 2 DOUT REG DATA REG DATA + 1 Figure40. RREGCommandExample:ReadTwoRegistersStartingfromRegister00h(IDRegister) (OPCODE1=00100000,OPCODE2=00000001) WREG:WritetoRegister This opcode writes register data. The Register Write command is a two-byte opcode followed by the input of the registerdata.Thefirstbytecontainsthecommandopcodeandtheregisteraddress. Thesecondbyteoftheopcodespecifiesthenumberofregisterstowrite– 1. Firstopcodebyte:0100rrrr,whererrrristhestartingregisteraddress. Secondopcodebyte:000nnnnn,wherennnnnisthenumberofregisterstowrite– 1. After the opcode bytes, the register data follows (in MSB-first format), as shown in Figure 41. WREG command can be issued any time. However, because this command is a multi-byte command, there are restrictions on the SCLK rate depending on the way the SCLKs are issued. See the Serial Clock (SCLK) subsection of the SPI Interfacesectionformoredetails.NotethatCSmustbelowfortheentirecommand. CS(1) 1 9 17 25 SCLK DIN OPCODE 1 OPCODE 2 REG DATA 1 REG DATA 2 DOUT Figure41. WREGCommandExample:WriteTwoRegistersStartingfrom00h(IDRegister) (OPCODE1=01000000,OPCODE2=00000001) 38 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 REGISTER MAP Table10describesthevariousADS1194/6/8registers. Table10.RegisterAssignments RESET VALUE ADDRESS REGISTER (Hex) BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 DeviceSettings(Read-OnlyRegisters) 00h ID XX DEV_ID5 DEV_ID4 DEV_ID3 1 0 DEV_ID2 DEV_ID1 DEV_ID0 GlobalSettingsAcrossChannels 01h CONFIG1 04 0 DAISY_EN CLK_EN 0 0 DR2 DR1 DR0 02h CONFIG2 20 0 0 1 INT_TEST 0 TEST_AMP TEST_FREQ1 TEST_FREQ0 RLD_LOFF_ 03h CONFIG3 40 PD_REFBUF 1 VREF_4V RLD_MEAS RLDREF_INT PD_RLD RLD_STAT SENS VLEAD_OFF_ 04h LOFF 00 COMP_TH2 COMP_TH1 COMP_TH0 ILEAD_OFF1 ILEAD_OFF0 FLEAD_OFF1 FLEAD_OFF0 EN Channel-SpecificSettings 05h CH1SET 00 PD1 GAIN12 GAIN11 GAIN10 0 MUXn2 MUXn1 MUXn0 06h CH2SET 00 PD2 GAIN22 GAIN21 GAIN20 0 MUX22 MUX21 MUX20 07h CH3SET 00 PD3 GAIN32 GAIN31 GAIN30 0 MUX32 MUX31 MUX30 08h CH4SET 00 PD4 GAIN42 GAIN41 GAIN40 0 MUX42 MUX41 MUX40 09h CH5SET(1) 00 PD5 GAIN52 GAIN51 GAIN50 0 MUX52 MUX51 MUX50 0Ah CH6SET(1) 00 PD6 GAIN62 GAIN61 GAIN60 0 MUX62 MUX61 MUX60 0Bh CH7SET(1) 00 PD7 GAIN72 GAIN71 GAIN70 0 MUX72 MUX71 MUX70 0Ch CH8SET(1) 00 PD8 GAIN82 GAIN81 GAIN80 0 MUX82 MUX81 MUX80 0Dh RLD_SENSP(2) 00 RLD8P(1) RLD7P(1) RLD6P(1) RLD5P(1) RLD4P RLD3P RLD2P RLD1P 0Eh RLD_SENSN(2) 00 RLD8N(1) RLD7N(1) RLD6N(1) RLD5N(1) RLD4N RLD3N RLD2N RLD1N 0Fh LOFF_SENSP(2) 00 LOFF8P LOFF7P LOFF6P LOFF5P LOFF4P LOFF3P LOFF2P LOFF1P 10h LOFF_SENSN(2) 00 LOFF8N LOFF7N LOFF6N LOFF5N LOFF4N LOFF3N LOFF2N LOFF1N 11h LOFF_FLIP 00 LOFF_FLIP8 LOFF_FLIP7 LOFF_FLIP6 LOFF_FLIP5 LOFF_FLIP4 LOFF_FLIP3 LOFF_FLIP2 LOFF_FLIP1 Lead-OffStatusRegisters(Read-OnlyRegisters) 12h LOFF_STATP 00 IN8P_OFF IN7P_OFF IN6P_OFF IN5P_OFF IN4P_OFF IN3P_OFF IN2P_OFF IN1P_OFF 13h LOFF_STATN 00 IN8N_OFF IN7N_OFF IN6N_OFF IN5N_OFF IN4N_OFF IN3N_OFF IN2N_OFF IN1N_OFF GPIOandOTHERRegisters 14h GPIO 0F GPIOD4 GPIOD3 GPIOD2 GPIOD1 GPIOC4 GPIOC3 GPIOC2 GPIOC1 15h PACE 00 0 0 0 PACEE1 PACEE0 PACEO1 PACEO0 PD_PACE 16h RESERVED 00 0 0 0 0 0 0 0 0 SINGLE_ WCT_TO_ PD_LOFF_ 17h CONFIG4 00 0 0 0 0 0 SHOT RLD COMP 18h WCT1 00 aVF_CH6 aVL_CH5 aVR_CH7 avR_CH4 PD_WCTA WCTA2 WCTA1 WCTA0 19h WCT2 00 PD_WCTC PD_WCTB WCTB2 WCTB1 WCTB0 WCTC2 WCTC1 WCTC0 (1) CH5SETandCH6SETarenotavailablefortheADS1194.CH7SETandCH8SETregistersarenotavailablefortheADS1194and ADS1196. (2) TheRLD_SENSP,PACE_SENSP,LOFF_SENSP,LOFF_SENSN,andLOFF_FLIPregistersbits[5:4]arenotavailableforthe ADS1194.Bits[7:6]arenotavailablefortheADS1194/6. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com UserRegisterDescription ID:IDControlRegister(Factory-Programmed,Read-Only) Address=00h BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 DEV_ID5 DEV_ID4 DEV_ID3 1 0 DEV_ID2 DEV_ID1 DEV_ID0 TheIDControlRegisterisprogrammedduringdevicemanufacturetoindicatedevicecharacteristics. Bits[7:5] DEV_ID[5:3]:Devicefamilyidentification Thesebitsindicatethedevicefamily. 000=Reserved 011=Reserved 100=Reserved 101=ADS119xdevicefamily 110=Reserved 111=Reserved Bit4 Thisbitreadshigh. Bit3 Thisbitreadslow. Bit2 DEV_ID2:Channelnumberidentification Thisbitreadshigh. Bits[1:0] DEV_ID[1:0]:Channelnumberidentification Thesebitsindicatesnumberofchannels. 00=4-channelADS1194 01=6-channelADS1196 10=8-channelADS1198 11=Reserved 40 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 CONFIG1:ConfigurationRegister1 Address=01h BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 0 DAISY_EN CLK_EN 0 0 DR2 DR1 DR0 Bit7 Mustalwaysbesetto'0' Bit6 DAISY_EN:Daisy-chain/multiplereadbackmode Thisbitdetermineswhichmodeisenabled. 0=Daisy-chainmode(default) 1=Multiplereadbackmode Bit5 CLK_EN:CLKconnection(1) ThisbitdeterminesiftheinternaloscillatorsignalisconnectedtotheCLKpinwhentheCLKSELpin=1. 0=Oscillatorclockoutputdisabled(default) 1=Oscillatorclockoutputenabled Bits[4:3] Mustalwaysbesetto'0' Bits[2:0] DR[2:0]:Outputdatarate. f =f /16. MOD CLK Thesebitsdeterminetheoutputdatarateofthedevice. (1) Additionalpowerwillbeconsumedwhendrivingexternaldevices. BIT DATARATE SAMPLERATE(1) 000 f /16 8kSPS MOD 001 f /32 4kSPS MOD 010 f /64 2kSPS MOD 011 f /128 1kSPS MOD 100(default) f /256 500SPS MOD 101 f /512 250SPS MOD 110 f /1024 125SPS MOD 111 DONOTUSE N/A (1) f =2.048MHz. CLK Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com CONFIG2:ConfigurationRegister2 Address=02h BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 0 0 1 INT_TEST 0 TEST_AMP TEST_FREQ1 TEST_FREQ0 ConfigurationRegister2configuresthetestsignalgeneration.SeetheInputMultiplexersectionformoredetails. Bits[7:6] Mustalwaysbesetto'0' Bits5 Mustalwaysbesetto'1' Bit4 INT_TEST:TESTsource ThisbitdeterminesthesourcefortheTestsignal. 0=Testsignalsaredrivenexternally(default) 1=Testsignalsaregeneratedinternally Bit3 Mustalwaysbesetto'0' Bit2 TEST_AMP:Testsignalamplitude ThesebitsdeterminetheCalibrationsignalamplitude. 0=–1×(VREFP–VREFN)/2.4mV(default) 1=–2×(VREFP–VREFN)/2.4mV Bits[1:0] TEST_FREQ[1:0]:Testsignalfrequency Thesebitsdeterminethecalibrationsignalfrequency. 00=Pulsedatf /221(default) CLK 01=Pulsedatf /220 CLK 10=Notused 11=Atdc 42 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 CONFIG3:ConfigurationRegister3 Address=03h BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 PD_REFBUF 1 VREF_4V RLD_MEAS RLDREF_INT PD_RLD RLD_LOFF_SENS RLD_STAT ConfigurationRegister3configuresmulti-referenceandRLDoperation. Bit7 PD_REFBUF:Power-downreferencebuffer Thisbitdeterminesthepower-downreferencebufferstate. 0=Power-downinternalreferencebuffer(default) 1=Enableinternalreferencebuffer Bit6 Mustalwaysbesetto'1'.Defaultis'1'atpower-up. Bit5 VREF_4V:Referencevoltage Thisbitdeterminesthereferencevoltage,VREFP. 0=VREFPissetto2.4V(default) 1=VREFPissetto4V(useonlywitha5Vanalogsupply) Bit4 RLD_MEAS:RLDmeasurement ThisbitenablesRLDmeasurement.TheRLDsignalmaybemeasuredwithanychannel. 0=Open(default) 1=RLD_INsignalisroutedtothechannelthathastheMUX_Setting010(V ) REF Bit3 RLDREF_INT:RLDREFsignal ThisbitdeterminestheRLDREFsignalsource. 0=RLDREFsignalfedexternally(default) 1=RLDREFsignal(AVDD–AVSS)/2generatedinternally Bit2 PD_RLD:RLDbufferpower ThisbitdeterminestheRLDbufferpowerstate. 0=RLDbufferispowereddown(default) 1=RLDbufferisenabled Bit1 RLD_LOFF_SENS:RLDsenseselection ThisbitenablestheRLDsensefunction. 0=RLDsenseisdisabled(default) 1=RLDsenseisenabled Bit0 RLD_STAT:RLDleadoffstatus ThisbitdeterminestheRLDstatus. 0=RLDisconnected(default) 1=RLDisnotconnected Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com LOFF:Lead-OffControlRegister Address=04h BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 COMP_TH2 COMP_TH1 COMP_TH0 VLEAD_OFF_EN ILEAD_OFF1 ILEAD_OFF0 FLEAD_OFF1 FLEAD_OFF0 TheLead-OffControlRegisterconfigurestheLead-Offdetectionoperation. Bits[7:5] COMP_TH[2:0]:Lead-offcomparatorthreshold Thesebitsdeterminethelead-offcomparatorthresholdlevelsetting.SeetheLead-OffDetectionsubsectionofthe ECG-SpecificFunctionssectionforadetaileddescription. Comparatorpositiveside 000=95%(default) 001=92.5% 010=90% 011=87.5% 100=85% 101=80% 110=75% 111=70% Comparatornegativeside 000=5%(default) 001=7.5% 010=10% 011=12.5% 100=15% 101=20% 110=25% 111=30% Bit4 VLEAD_OFF_EN:Lead-offdetectionmode Thisbitdeterminesthelead-offdetectionmode. 0=Currentsourcemodelead-off(default) 1=Pull-up/pull-downresistormodelead-off Bits[3:2] ILEAD_OFF[1:0]:Lead-offcurrentmagnitude Thesebitsdeterminethemagnitudeofcurrentforthecurrentlead-offmode. 00=4nA(default) 01=8nA 10=12nA 11=16nA Bits[1:0] FLEAD_OFF[1:0]:Lead-offfrequency Thesebitsdeterminethefrequencyoflead-offdetectforeachchannel. 00=WhenanybitsoftheLOFF_SENSPandLOFF_SENSNregistersareturnedon,makesureFLEAD_OFF[1:0]iseither setto'01'or'11'(default) 01=AClead-offdetectionatf /4 DR 10=Donotuse 11=DClead-offdetectionturnedon 44 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 CHnSET:IndividualChannelSettings(n=1:8) Address=05hto0Ch BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 PD GAIN2 GAIN1 GAIN0 0 MUXn2 MUXn1 MUXn0 The CH[1:8]SET Control Register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer section for details. CH[2:8]SET are similar to CH1SET, corresponding to the respective channels. Bit7 PD:Power-down Thisbitdeterminesthechannelpowermodeforthecorrespondingchannel. 0=Normaloperation(default) 1=Channelpower-down.Whenpoweringdownachannel,itisrecommendedthatthechannelbesettoinputshortby settingtheappropriateMUXn[2:0]=001oftheCHnSETregister. Bits[6:4] GAIN[2:0]:PGAgain ThesebitsdeterminethePGAgainsetting. 000=6(default) 001=1 010=2 011=3 100=4 101=8 110=12 Bit3 Alwayswrite'0' Bits[2:0] MUXn[2:0]:Channelinput Thesebitsdeterminethechannelinputselection. 000=Normalelectrodeinput(default) 001=Inputshorted(foroffsetornoisemeasurements) 010=UsedinconjunctionwithRLD_MEASbitforRLDmeasurements.SeetheRightLegDrive(RLDDCBiasCircuit) subsectionoftheECG-SpecificFunctionssectionformoredetails. 011=MVDDforsupplymeasurement 100=Temperaturesensor 101=Testsignal 110=RLD_DRP(positiveelectrodeisthedriver) 111=RLD_DRN(negativeelectrodeisthedriver) RLD_SENSP Address=0Dh BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 RLD8P RLD7P RLD6P RLD5P RLD4P RLD3P RLD2P RLD1P Thisregistercontrolstheselectionofthepositivesignalsfromeachchannelforrightlegdrivederivation.Seethe RightLegDrive(RLDDCBiasCircuit)subsectionoftheECG-SpecificFunctionssectionfordetails. Notethatregistersbits[5:4]arenotavailablefortheADS1194.Bits[7:6]arenotavailablefortheADS1194/6. RLD_SENSN Address=0Eh BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 RLD8N RLD7N RLD6N RLD5N RLD4N RLD3N RLD2N RLD1N This register controls the selection of the negative signals from each channel for right leg drive derivation. See theRightLegDrive(RLDDCBiasCircuit)subsectionoftheECG-SpecificFunctionssectionfordetails. Note that registers bits[5:4] are not available for the ADS1194. Bits[7:6] are not available for the ADS1194 and ADS1196. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com LOFF_SENSP Address=0Fh BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 LOFF8P LOFF7P LOFF6P LOFF5P LOFF4P LOFF3P LOFF2P LOFF1P This register selects the positive side from each channel for lead-off detection. See the Lead-Off Detection subsection of the ECG-Specific Functions section for details. Note that the LOFF_STATP register bits are only validifthecorrespondingLOFF_SENSPbitsaresetto'1'. Note that registers bits[5:4] are not available for the ADS1194. Bits[7:6] are not available for the ADS1194 and ADS1196. LOFF_SENSN Address=10h BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 LOFF8N LOFF7N LOFF6N LOFF5N LOFF4N LOFF3N LOFF2N LOFF1N This register selects the negative side from each channel for lead-off detection. See the Lead-Off Detection subsection of the ECG-Specific Functions section for details. Note that the LOFF_STATN register bits are only validifthecorrespondingLOFF_SENSNbitsaresetto'1'. Note that registers bits[5:4] are not available for the ADS1194. Bits[7:6] are not available for the ADS1194 and ADS1196. LOFF_FLIP Address=11h BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 LOFF_FLIP8 LOFF_FLIP7 LOFF_FLIP6 LOFF_FLIP5 LOFF_FLIP4 LOFF_FLIP3 LOFF_FLIP2 LOFF_FLIP1 This register controls the direction of the current used for lead-off derivation. See the Lead-Off Detection subsectionoftheECG-SpecificFunctionssectionfordetails. LOFF_STATP(Read-OnlyRegister) Address=12h BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 IN8P_OFF IN7P_OFF IN6P_OFF IN5P_OFF IN4P_OFF IN3P_OFF IN2P_OFF IN1P_OFF This register stores the status of whether the positive electrode on each channel is on or off. See the Lead-Off DetectionsubsectionoftheECG-SpecificFunctionssectionfordetails. '0' is lead-on (default) and '1' is lead-off. Ignore the LOFF_STATP values if the corresponding LOFF_SENSP bits arenotsetto'1'.WhentheLOFF_SENSEPbitsare'0',theLOFF_STATPbitsshouldbeignored. LOFF_STATN(Read-OnlyRegister) Address=13h BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 IN8N_OFF IN7N_OFF IN6N_OFF IN5N_OFF IN4N_OFF IN3N_OFF IN2N_OFF IN1N_OFF This register stores the status of whether the negative electrode on each channel is on or off. See the Lead-Off Detection subsection of the ECG-Specific Functions section for details. Ignore the LOFF_STATN values if the correspondingLOFF_SENSNbitsarenotsetto'1'. '0' is lead-on (default) and '1' is lead-off. When the LOFF_SENSEN bits are '0', the LOFF_STATP bits should be ignored. 46 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 GPIO:General-PurposeI/ORegister Address=14h BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 GPIOD4 GPIOD3 GPIOD2 GPIOD1 GPIOC4 GPIOC3 GPIOC2 GPIOC1 TheGeneral-PurposeI/ORegistercontrolstheactionofthethreeGPIOpins. Bits[7:4] GPIOD[4:1]:GPIOdata ThesebitsareusedtoreadandwritedatatotheGPIOports. Whenreadingtheregister,thedatareturnedcorrespondtothestateoftheGPIOexternalpins,whethertheyare programmedasinputsorasoutputs.Asoutputs,awritetotheGPIODsetstheoutputvalue.Asinputs,awritetothe GPIODhasnoeffect.GPIOisnotavailableincertainrespirationmodes. Bits[3:0] GPIOC[4:1]:GPIOcontrol(correspondingGPIOD) ThesebitsdetermineifthecorrespondingGPIODpinisaninputoroutput. 0=Output 1=Input(default) PACE:PACEDetectRegister Address=15h BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 0 0 0 PACEE1 PACEE0 PACEO1 PACEO0 PD_PACE ThisregisterprovidesthePACEcontrolsthatconfigurethechannelsignalusedtofeedtheexternalPACEdetect circuitry.SeethePaceDetectsubsectionoftheECG-SpecificFunctionssectionfordetails. Bits[7:5] Mustalwaysbesetto'0' Bits[4:3] PACEE[1:0]:PACEevenchannels ThesebitscontroltheselectionoftheevennumberchannelsavailableonTEST_PACE_OUT1.Notethatonlyonechannel maybeselectedatanytime. 00=Channel2(default) 01=Channel4 10=Channel6,ADS1196/8only 11=Channel8,ADS1198only Bits[2:1] PACEO[1:0]:PACEoddchannels ThesebitscontroltheselectionoftheoddnumberchannelsavailableonTEST_PACE_OUT2.Notethatonlyonechannel maybeselectedatanytime. 00=Channel1(default) 01=Channel3 10=Channel5,ADS1196/8only(default) 11=Channel7,ADS1198only Bit[0] PD_PACE:PACEdetectbuffer Thisbitisusedtoenable/disablethePACEdetectbuffer. 0=PACEdetectbufferturnedoff(default) 1=PACEdetectbufferturnedon Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com RESERVED Address=16h BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 0 0 0 0 0 0 0 0 Bits[7:0] Mustalwaysbesetto'0' CONFIG4:ConfigurationRegister4 Address=17h BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 0 0 0 0 SINGLE_SHOT WCT_TO_RLD PD_LOFF_COMP 0 Bits[7:4] Mustalwaysbesetto'0' Bit[3] SINGLE_SHOT:Single-shotconversion Thisbitsetstheconversionmode. 0=Continuousconversionmode(default) 1=Single-shotmode Bit[2] WCT_TO_RLD:ConnectstheWCTtotheRLD 0=WCTtoRLDconnectionoff(default) 1=WCTtoRLDconnectionon Bit[1] PD_LOFF_COMP:Lead-offcomparatorpower-down Thisbitpowersdownthelead-offcomparators. 0=Lead-offcomparatorsdisabled(default) 1=Lead-offcomparatorsenabled Bit[0] Mustalwaysbesetto'0' 48 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 WCT1:WilsonCenterTerminalandAugmentedLeadControlRegister Address=18h BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 aVF_CH6 aVL_CH5 aVR_CH7 aVR_CH4 PD_WCTA WCTA2 WCTA1 WCTA0 TheWCT1controlregisterconfiguresthedeviceWCTcircuitchannelselectionandtheaugmentedleads. Bit[7] aVF_CH6:Enable(WCTA+WCTB)/2tothenegativeinputofchannel6(ADS1196/8only) 0=Disabled(default) 1=Enabled Bit[6] aVL_CH5:Enable(WCTA+WCTC)/2tothenegativeinputofchannel5(ADS1196/8only) 0=Disabled(default) 1=Enabled Bit[5] aVR_CH7:Enable(WCTB+WCTC)/2tothenegativeinputofchannel7(ADS1198only) 0=Disabled(default) 1=Enabled Bit[4] aVR_CH4:Enable(WCTB+WCTC)/2tothenegativeinputofchannel4 0=Disabled(default) 1=Enabled Bit[3] PD_WCTA:Power-downWCTA 0=Powereddown(default) 1=Poweredon Bits[2:0] WCTA[2:0]:WCTamplifierAchannelselection;typicallyconnectedtoRAelectrode. Thesebitsselectoneoftheeightelectrodeinputsofchannels1to4. 000=Channel1positiveinputconnectedtoWCTAamplifier(default) 001=Channel1negativeinputconnectedtoWCTAamplifier 010=Channel2positiveinputconnectedtoWCTAamplifier 011=Channel2negativeinputconnectedtoWCTAamplifier 100=Channel3PositiveinputconnectedtoWCTAamplifier 101=Channel3negativeinputconnectedtoWCTAamplifier 110=Channel4positiveinputconnectedtoWCTAamplifier 111=Channel4negativeinputconnectedtoWCTAamplifier Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 49 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com WCT2:WilsonCenterTerminalControlRegister Address=19h BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 PD_WCTC PD_WCTB WCTB2 WCTB1 WCTB0 WCTC2 WCTC1 WCTC0 TheWCT2configurationregisterconfiguresthedeviceWCTcircuitchannelselection. Bit[7] PD_WCTC:Power-downWCTC 0=Powereddown(default) 1=Poweredon Bit[6] PD_WCTB:Power-downWCTB 0=Powereddown(default) 1=Poweredon Bits[5:3] WCTB[2:0]:WCTamplifierBchannelselection;typicallyconnectedtoLAelectrode. Thesebitsselectoneoftheeightelectrodeinputsofchannels1to4. 000=Channel1positiveinputconnectedtoWCTBamplifier 001=Channel1negativeinputconnectedtoWCTBamplifier 010=Channel2positiveinputconnectedtoWCTBamplifier(default) 011=Channel2negativeinputconnectedtoWCTBamplifier 100=Channel3positiveinputconnectedtoWCTBamplifier 101=Channel3negativeinputconnectedtoWCTBamplifier 110=Channel4positiveinputconnectedtoWCTBamplifier 111=Channel4negativeinputconnectedtoWCTBamplifier Bits[2:0] WCTC[2:0]:WCTamplifierCchannelselection;typicallyconnectedtoLLelectrode. Thesebitsselectoneoftheeightelectrodeinputsofchannels1to4. 000=Channel1positiveinputconnectedtoWCTCamplifier 001=Channel1negativeinputconnectedtoWCTCamplifier 010=Channel2positiveinputconnectedtoWCTCamplifier 011=Channel2negativeinputconnectedtoWCTCamplifier 100=Channel3positiveinputconnectedtoWCTCamplifier(default) 101=Channel3negativeinputconnectedtoWCTCamplifier 110=Channel4positiveinputconnectedtoWCTCamplifier 111=Channel4negativeinputconnectedtoWCTCamplifier 50 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 ECG-SPECIFIC FUNCTIONS INPUT MULTIPLEXER (REROUTING THE RIGHT LEG DRIVE SIGNAL) The input multiplexer has ECG-specific functions for the right-leg drive signal. The RLD signal is available at the RLDOUT pin once the appropriate channels are selected for the RLD derivation, feedback elements are installed external to the chip, and the loop is closed. This signal can be fed after filtering or fed directly into the RLDIN pin as shown in Figure 42. This RLDIN signal can be multiplexed into any one of the input electrodes by setting the MUX bits of the appropriate channel set registers to 110 for P-side or 111 for N-side. Figure 42 shows the RLD signal generated from channels 1, 2, and 3 and routed to the N-side of channel 8. This feature can be used to dynamically change the electrode that is used as the reference signal to drive the patient body. Note that the correspondingchannelcannotbeusedandcanbepowereddown. IN1P RLD_SENSP[0] = 1 EMI Filter PGA1 RLD_SENSN[0] = 1 MUX1[2:0] = 000 IN1N IN2P RLD_SENSP[1] = 1 EMI Filter PGA2 RLD_SENSN[1] = 1 MUX2[2:0] = 000 IN2N IN3P RLD_SENSP[2] = 1 EMI Filter PGA3 RLD_SENSN[2] = 1 MUX3[2:0] = 000 IN3N ¼ ¼ ¼ IN8P RLD_SENSP[7] = 0 EMI PGA8 RLD_SENSN[7] = 0 Filter MUX8[2:0] = 111 IN8N MUX R RLDREF_INT L D (AVDD + AVSS)/2 R E F_ RLD_AMP Device INT RLDIN RLDREF RLDOUT RLDINV 1 MW(1) Filter or Feedthrough 1.5 nF(1) (1) Typicalvaluesforexampleonly. Figure42. ExampleofRLDOUTSignalConfiguredtobeRoutedtoIN8N Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 51 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com INPUT MULTIPLEXER (MEASURING THE RIGHT LEG DRIVE SIGNAL) Also, the RLDOUT signal can be routed to a channel (that is not used for the calculation of RLD) for measurement.Figure43showstheregistersettingstoroutetheRLDINsignaltochannel8.Themeasurementis donewithrespecttothevoltageontheRLDREFpin.IfRLDREFischosentobeinternal,itwouldbeat(AVDD+ AVSS)/2.Thisfeatureisusefulfordebuggingpurposesduringproductdevelopment. IN1P RLD_SENSP[0] = 1 EMI Filter PGA1 RLD_SENSN[0] = 1 MUX1[2:0] = 000 IN1N IN2P RLD_SENSP[1] = 1 EMI Filter PGA2 RLD_SENSN[1] = 1 MUX2[2:0] = 000 IN2N IN3P RLD_SENSP[2] = 1 EMI Filter PGA3 RLD_SENSN[2] = 1 MUX3[2:0] = 000 IN3N ¼ ¼ ¼ IN8P RLD_SENSP[7] = 0 EMI PGA8 RLD_SENSN[7] = 0 Filter MUX8[2:0] =010 IN8N MUX MUX8[2:0] = 010 AND R L RLD_MEAS = 1 D R E RLD_AMP RLDREF_INT F_ IN (AVDD + AVSS)/2 T Device RLD_IN RLD_REF RLD_OUT RLD_INV 1 MW(1) Filter or Feedthrough 1.5 nF(1) (1) Typicalvaluesforexampleonly. Figure43. RLDOUTSignalConfiguredtobeReadBackbyChannel8 52 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 WILSON CENTER TERMINAL (WCT) AND CHEST LEADS In the standard 12-lead ECG, WCT voltage is defined as the average of Right Arm (RA), Left Arm (LA), and Left Leg (LL) electrodes. This voltage is used as the reference voltage for the measurement of the chest leads. The ADS1194/6/8 has three integrated low-noise amplifiers that generate the WCT voltage. Figure 44 shows the blockdiagramoftheimplementation. IN1P IN1N IN2P IN2N To Channel IN3P PGAs IN3N IN4P IN4N 8:1 MUX 8:1 MUX 8:1 MUX W Wcta W Wctb W Wctc C C C T T T 1 2 2 [2 [5 [2 :0 :3 :0 ] ] ] 30kW 30kW 30kW WCT ADS1194/6/8 80pF AVSS Figure44. WCTVoltage The devices provide flexibility to choose any one of the eight signals (IN1P to IN4N) to be routed to each of the amplifierstogeneratetheaverage.HavingthisflexibilityallowstheRA,LA,andLLelectrodestobeconnectedto anyinputofthefirstfourchannelsdependingontheleadconfiguration. Each of the three amplifiers in the WCT circuitry can be powered down individually with register settings. By powering up two amplifiers, the average of any two electrodes can be generated at the WCT pin. Powering up one amplifier provides the buffered electrode voltage at the WCT pin. Note that the WCT amplifiers have limited drivestrengthandthusshouldbebufferedifusedtodrivealow-impedanceload. SeeTable3forperformancewhenusingany1,2,or3oftheWCTbuffers. As can be seen in Table 3, the overall noise reduces when more than one WCT amplifier is powered up. This noise reduction is due to the fact that noise is averaged by the passive summing network at the output of the amplifiers. Powering down individual buffers gives negligible power savings because a significant portion of the circuitry is shared between the three amplifiers. The bandwidth of the WCT node is limited by the RC network. The internal summing network consists of three 30kΩ resistors and a 80pF capacitor. It is recommended that an external 100pF capacitor be added for optimal performance. The effective bandwidth depends on the number of amplifiersthatarepoweredup,asshowninTable3. The WCT node should be only be used to drive very high input impedances (typically greater than 500MΩ). Typical application would be to connect this WCT signal to the negative inputs of a ADS1194/6/8 to be used as a referencesignalforthechestleads. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 53 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com As mentioned previously in this section, all three WCT amplifiers can be connected to one of the eight analog input pins. The inputs of the amplifiers are chopped and the chopping frequency is at 8kHz. The chop frequency shows itself at the output of the WCT amplifiers as a small square-wave riding on dc. The amplitude of the square-wave is the offset of the amplifier and is typically 5mV . This artifact as a result of the chopping function PP is out-of-band and thus does not interfere with ECG-related measurements. Note that if the output of a channel connectedtotheWCT(forexample,V channels)isconnectedtooneofthepaceamplifiersforexternalpace LEAD detection,theartifactofchoppingappearsatthePaceamplifieroutput. AugmentedLeads In the typical implementation of the 12-lead ECG with eight channels, the augmented leads are calculated digitally. In certain applications, it may be required that all leads be derived in analog rather than digital. The ADS1198 provides the option to generate the augmented leads by routing appropriate averages to channels 5 to 7. The same three amplifiers that are used to generate the WCT signal are used to generate the Goldberger terminalsignalsaswell.Figure45showsanexampleofgeneratingtheaugmentedleadsinanalogdomain.Note that in this implementation it takes more than eight channels to generate the standard 12 leads. Also, this feature isnotavailableintheADS1196andADS1194. IN1P IN1N IN2P IN2N To Channel IN3P PGAs IN3N IN4P IN4N 8:1 MUX 8:1 MUX 8:1 MUX W Wcta W Wctb W Wctc CT CT CT avF_ch4 1 2 2 [2 [5 [2 :0 :3 :0 ] ] ] ADS1198 avF_ch6 avF_ch5 avF_ch7 IN5P IN5N IN6P To Channel IN6N PGAs IN7P IN7N Figure45. AnalogDomainAugmentedLeads RightLegDrivewiththeWCTPoint In certain applications, the out-of-phase version of the WCT is used as the right leg drive reference. The ADS1198 provides the option to have a buffered version of the WCT terminal at the RLD_OUT pin. This signal can be inverted in phase using an external amplifier and used as the right leg drive. Refer to the Right Leg Drive (RLDDCBiasCircuit)sectionformoredetails. 54 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 LEAD-OFF DETECTION Patient electrode impedances are known to decay over time. It is necessary to continuously monitor these electrode connections to verify a suitable connection is present. The ADS1194/6/8 lead-off detection functional blockprovidessignificantflexibilitytotheusertochoosefromvariouslead-offdetectionstrategies.Thoughcalled lead-offdetection,thisisinfactanelectrode-offdetection. The basic principle is to inject an excitation signal and measure the response to find out if the electrode is off. As shown in the lead-off detection functional block diagram in Figure 46, this circuit provides two different methods of determining the state of the patient electrode. The methods differ in the frequency content of the excitation signal. Lead-off can be selectively done on a per channel basis using the LOFF_SENSP and LOFF_SENSN registers.Also,theinternalexcitationcircuitrycanbedisabledandjustthesensingcircuitrycanbeenabled. AVDD AVSS FLEAD_OFF[0:1] Vx FLEAD_OFF[1:0] 10pF 10pF 7MW 7MW (AVDD + AVSS)/2 3.3MW 12pF 3.3MW Skin, Patient Patient Electrode Contact Protection 3.3MW 3.3MW Antialiasing Filter 12pF Model Resistor < 512kHz 3.3MW 3.3MW 47nF LOFF_STATP LOFF_SENSPAND LOFF_SENSNAND VLEAD_OFF_EN VLEAD_OFF_EN 51kW 100kW V INP EMI 51kW 100kW Filter VINN PGA To ADC LOFF_SENSPAND LOFF_SENSNAND 47nF VLEAD_OFF_EN VLEAD_OFF_EN LOFF_STATN 47nF AVDD AVSS 4-Bit COMP_TH[2:0] DAC 51kW 100kW RLD OUT Figure46. Lead-OffDetection Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 55 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com DCLead-Off In this method, the lead-off excitation is with a dc signal. The dc excitation signal can be chosen from either a pull-up/pull-down resistor or a current source/sink, shown in Figure 47. The selection is done by setting the VLEAD_OFF_ENbitintheLOFFregister.Onesideofthechannelispulledtosupplyandtheothersideispulled to ground. The pull-up resistor and pull-down resistor can be swapped (as shown in Figure 48) by setting the bits in the LOFF_FLIP register. In case of current source/sink, the magnitude of the current can be set by using the ILEAD_OFF[1:0]bitsintheLOFFregister.Thecurrentsource/sinkgiveslargerinputimpedancecomparedtothe 10MΩ pull-up/pull-downresistor. AVDD AVDD AVDD AVDD ADS119x ADS119x ADS119x ADS119x 10MW 10MW 10MW INP INP INP INP PGA PGA PGA PGA INN INN INN INN 10MW 10MW 10MW a) Pull-Up/Pull-Down Resistors b) Current Source a) LOFF_FLIP = 0 a) LOFF_FLIP = 1 Figure47.DCLead-OffExcitationOptions Figure48.LOFF_FLIPUsage Sensingoftheresponsecanbedoneeitherbylookingatthedigitaloutputcodefromthedeviceorbymonitoring the input voltages with an on-chip comparator. If either of the electrodes is off, the pull-up resistors and/or the pull-downresistorssaturatethechannel.BylookingattheoutputcodeitcanbedeterminedthateithertheP-side or the N-side is off. To pinpoint which one is off, the comparators must be used. The input voltage is also monitored using a comparator and a 4-bit DAC whose levels are set by the COMP_TH[2:0] bits in the LOFF register. The output of the comparators are stored in the LOFF_STATP and LOFF_STATN registers. These two registers are available as a part of the output data stream. (See the Data Output (DOUT) subsection of the SPI Interface section.) If dc lead-off is not used, the lead-off comparators can be powered down by setting the PD_LOFF_COMPbitintheCONFIG4register. Anexampleproceduretoturnondclead-offisgivenintheLead-OffsubsectionoftheQuick-StartGuidesection. 56 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 ACLead-Off In this method, an out-of-band ac signal is used for excitation. The ac signal is generated by alternatively providing pull-up resistors and pull-down resistors at the input with a fixed frequency. The ac signal is passed through an anti-aliasing filter to avoid aliasing. The frequency can be chosen by the FLEAD_OFF[1:0] bits in the LOFF register. The excitation frequency is a function of the output data rate and can be chosen to be either f /2 DR orf /4.Thisout-of-bandexcitationsignalispassedthroughthechannelandmeasuredattheoutput. DR Sensing of the ac signal is done by passing the signal through the channel to digitize it and measure at the output. The ac excitation signals are introduced at a frequency that is above the band of interest, generating an out-of-band differential signal that can be filtered out separately and processed. By measuring the magnitude of the excitation signal at the output spectrum, the lead-off status can be calculated. Therefore, the ac lead-off detectioncanbeaccomplishedsimultaneouslywiththeECGsignalacquisition. RLD LEAD-OFF TheADS1194/6/8providetwomodesfordeterminingwhethertheRLDiscorrectlyconnected: • RLDlead-offdetectionduringnormaloperation • RLDlead-offdetectionduringpower-up Thefollowingsectionsprovidedetailsofthetwomodesofoperation. RLDLead-OffDetectionDuringNormalOperation During normal operation, the ADS1194/6/8 RLD lead-off at power-up function cannot be used because it is necessarytopowerofftheRLDamplifier. RLDLeadOffDetectionAtPower-Up This feature is included in the ADS1194/6/8 for use in determining whether the right leg electrode is suitably connected. At power-up, the ADS1194/6/8 provide two measurement procedures to determine the RLD electrode connection status using either a current or a voltage pull-down resistor, as shown in Figure 49. The reference levelofthecomparatorissettodeterminetheacceptableRLDimpedancethreshold. Skin, Patient Patient Electrode Contact Protection Model Resistor To ADC input (through V REF connection to any of the channels). 47nF RLD_STAT 51kW 100kW RLD_SENSAND RLD_SENSAND VLEAD_OFF_EN VLEAD_OFF_EN ILGND_OFF[1:0] AVSS AVSS Figure49. RLDLead-OffDetectionatPower-Up When the RLD amplifier is powered on, the current source has no function. Only the comparator can be used to sense the voltage at the output of the RLD amplifier. The comparator thresholds are set by the same LOFF[7:5] bitsusedtosetthethresholdsforothernegativeinputs. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 57 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com RIGHT LEG DRIVE (RLD DC BIAS CIRCUIT) The right leg drive (RLD) circuitry is used as a means to counter the common-mode interference in a ECG system as a result of power lines and other sources, including fluorescent lights. The RLD circuit senses the common-mode of a selected set of electrodes and creates a negative feedback loop by driving the body with an inverted common-mode signal. The negative feedback loop restricts the common-mode movement to a narrow range, depending on the loop gain. Stabilizing the entire loop is specific to the individual user system based on the various poles in the loop. The ADS1194/6/8 integrates the muxes to select the channel and an operational amplifier. All the amplifier terminals are available at the pins, allowing the user to choose the components for the feedbackloop.ThecircuitinFigure50showstheoverallfunctionalconnectivityfortheRLDbiascircuit. The reference voltage for the right leg drive can be chosen to be internally generated (AVDD + AVSS)/2 or it can be provided externally with a resistive divider. The selection of an internal versus external reference voltage for theRLDloopisdefinedbywritingtheappropriatevaluetotheRLDREF_INTbitintheCOFIG3register. If the RLD function is not used, the amplifier can be powered down using the PD_RLD bit (see the CONFIG3: Configuration Register 3 subsection of the Register Map section for details). This bit is also used in daisy-chain modetopower-downallbutoneoftheRLDamplifiers. The functionality of the RLDIN pin is explained in the Input Multiplexer section. An example procedure to use the RLDamplifierisshownintheRightLegDrivesubsectionoftheQuick-StartGuidesection. 58 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 From MUX1P RLD1P 220kW PGA1P 50kW 220kW RLD2P FMrUomX2P PGA2P 20kW 50kW 50kW 220kW 20kW PGA1N MUFXro1mN RLD1N 220kW 50kW PGA2N From RLD2N From MUX3P RLD3P 220kW MUX2N PGA3P 50kW 220kW RLD4P FMrUomX4P PGA4P 20kW 50kW 50kW 220kW 20kW PGA3N MUFXro3mN RLD3N 220kW 50kW PGA4N From RLD4N From MUX5P RLD5P 220kW MUX4N PGA5P 50kW 220kW RLD6P FMrUomX6P PGA6P 20kW 50kW 50kW 220kW 20kW PGA5N MUFXro5mN RLD5N 220kW 50kW PGA6N From RLD6N From MUX7P RLD7P 220kW MUX6N PGA7P 50kW 220kW RLD8P FMrUomX8P PGA8P 20kW 50kW 50kW 220kW 20kW PGA7N MUFXro7mN RLD7N 220kW 50kW PGA8N RLDINV RLD8N From C (1) R (1) MUX8N EXT EXT 1.5nF 1MW RLD RLDOUT Amp (AVDD + AVSS)/2 RLDREF RLDREF_INT RLDREF_INT (1) Typicalvalues. (2) When CONFIG3.RLDREF_INT = 0, the RLDREF_INT switch is closed and the RLDREF_INT switch is open. When CONFIG3.RLDREF_INT=1,theRLDREF_INTswitchisopenandtheRLDREF_INTswitchisclosed. Figure50. RLDChannelSelection(2) Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 59 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com WCTasRLD In certain applications, the right leg drive is derived as the average of RA, LA, and LL. This level is the same as the WCT voltage. The WCT amplifier has limited drive strength and thus should be used only to drive very high impedances directly. As shown in Figure 51, the ADS1194/6/8 provide an option to internally buffer the WCT signal by setting the WCT_TO_RLD bit in the CONFIG4 register. The RLD_OUT and RLD_INV pins should be shorted external to the device. Note that before the RLD_OUT signal is connected to the RLD electrode, an externalamplifiershouldbeusedtoinvertthephaseofthesignalfornegativefeedback. ADS119x RLD_INV RLD_OUT RLD Amp RLD (AVDD + AVSS)/2 RLD_REF RLDREF_INT From WCT Amplifiers WCT_TO_RLD RLD_REF RLDREF_INT WCT Figure51. UsingtheWCTastheRightLegDrive RLDConfigurationwithMultipleDevices Figure52showsmultipledevicesconnectedtoanRLD. Device N Device 2 Device 1 Power-Down Power-Down X X X U U U M VA1-8 VA1-8 M VA1-8 VA1-8 M VA1-8 VA1-8 ut ut ut p p p n n n To I To I To I RLDIN RLD RLD RLDINV RLDIN RLD RLD RLDINV RLDIN RLD RLD RLDINV REF OUT REF OUT REF OUT Figure52. RLDConnectionforMultipleDevices 60 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 PACE DETECT The ADS1194/6/8 provide flexibility for pace detection with external hardware by bringing out the output of the PGAattwopins:TESTP_PACE_OUT1andTESTN_PACE_OUT2. ExternalHardwareApproach The ADS1194/6/8 provide the option of bringing out the output of the PGA; see Figure 53. External hardware circuitry can be used to detect the presence of the pulse. The output of the pace detection logic can then be fed into the device through one of the GPIO pins. The GPIO data are transmitted through the SPI port. Two of the eight channels can be selected using register bits in the PACE register, one from the odd-numbered channels and the other from the even-numbered channels. During the differential to single-ended conversion, there is an attenuation of 0.4. Therefore, the total gain in the pace path is equal to (0.4 × PGA_GAIN). The pace out signals are multiplexed with the TESTP and TESTN signals through the TESTP_PACE_OUT1 and TESTN_PACE_OUT2 pins respectively. The channel selection is done by setting bits[4:1] of the PACE register. If the pace circuitry is not used, the pace amplifiers can be turned off using the PD_PACE bit in the PACE register. Note that if the output of a channel connected to the WCT amplifier (for example, the V channels) is LEAD connected to one of the pace amplifiers for external pace detection, the artifact of chopping appears at the pace amplifieroutput.RefertotheWilsonCenterTerminal(WCT)andChestLeadssectionformoredetials. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 61 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com PACE[4:3] PACE[2:1] From 00 MUX1P PGA1P 50kW 00 From MUX2P PGA2P 20kW 50kW 50kW 20kW PGA1N MUFXro1mN 00 50kW PGA2N From 00 From MUX3P 01 MUX2N PGA3P 50kW 01 From MUX4P PGA4P 20kW 50kW 50kW 20kW PGA3N MUFXro3mN 01 50kW PGA4N From 01 From MUX5P 10 MUX4N PGA5P 50kW 10 From MUX6P PGA6P 20kW 50kW 50kW 20kW PGA5N MUFXro5mN 10 50kW PGA6N From 10 From MUX7P 11 MUX6N PGA7P 50kW 11 From MUX8P PGA8P 20kW 50kW 50kW 20kW PGA7N MUFXro7mN 11(AVDD-AVSS) 50kW PGA8N 2 11 From MUX8N 200kW PDB_PACE PACE TESTN_PACE_OUT2 Amp 500kW GPIO1 PACE_IN (GPIO1)(1) 200kW (AVDD-AVSS) 2 200kW PDB_PACE PACE TESTP_PACE_OUT1 500kW Amp 200kW (1) GPIO1canbeusedasthePACE_INsignal. Figure53. HardwarePaceDetectionOption 62 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 QUICK-START GUIDE PCB LAYOUT PowerSuppliesandGrounding The ADS1194/6/8 have three supplies: AVDD, AVDD1, and DVDD. Both AVDD and AVDD1 should be as quiet as possible. AVDD1 provides the supply to the charge pump block and has transients at f . Therefore, it is CLK recommended that AVDD1 and AVSS1 be star-connected to AVDD and AVSS. It is important to eliminate noise from AVDD and AVDD1 that is non-synchronous with the ADS1194/6/8 operation. Each supply of the ADS1194/6/8 should be bypassed with 1μF and a 0.1μF solid ceramic capacitors. It is recommended that placement of the digital circuits (DSP, microcontrollers, FPGAs, etc.) in the system is done such that the return currents on those devices do not cross the analog return path of the ADS1194/6/8. The ADS1194/6/8 can be poweredfromunipolarorbipolarsupplies. The capacitors used for decoupling can be of the surface-mount, low-cost, low-profile, multi-layer ceramic type. In most cases, the VCAP1 capacitor can also be a multi-layer ceramic, but in systems where the board is subjected to high or low frequency vibration, it is recommend to install a non-ferroelectric capacitor such as a tantalumorclass1capacitor(forexample,C0GorNPO).EIAclass2andclass3dielectrics(suchasX7R,X5R, X8R, etc.) are ferroelectric. The piezoelectric property of these capacitors can appear as electrical noise coming fromthecapacitor.Whenusinginternalreference,noiseontheVCAP1noderesultsinperformancedegradation. ConnectingtheDevicetoUnipolar(+3V/+1.8V)Supplies Figure 54 illustrates the ADS1194/6/8 connected to a unipolar supply. In this example, analog supply (AVDD) is referencedtoanalogground(AVSS)anddigitalsupplies(DVDD)arereferencedtodigitalground(DGND). +3V +1.8V 0.1mF 1mF 1mF 0.1mF AVDD AVDD1 DVDD VREFP 0.1mF 10mF VREFN VCAP1 ADS1198 VCAP2 VCAP3 VCAP4 WCT AVSS1 AVSS DGND RESV1 100pF 1mF 1mF 0.1mF 1mF 22mF NOTE:Placethecapacitorsforsupply,reference,WCT,andVCAP1toVCAP4asclosetothepackageaspossible. Figure54. Single-SupplyOperation Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 63 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com ConnectingtheDevicetoBipolar(±1.5V/1.8V)Supplies Figure 55 illustrates the ADS1194/6/8 connected to a bipolar supply. In this example, the analog supplies connect to the device analog supply (AVDD). This supply is referenced to the device analog return (AVSS), and thedigitalsupplies(DVDDandDVDD)arereferencedtothedevicedigitalgroundreturn(DVDD). +1.5V +1.8V 1mF 0.1mF 0.1mF 1mF AVDD AVDD1 DVDD VREFP 0.1mF 10mF VREFN -1.5V VCAP1 ADS1198 VCAP2 VCAP3 VCAP4 WCT AVSS1 AVSS DGND RESV1 100pF 1mF 1mF 0.1mF 1mF 22mF 1mF 0.1mF -1.5V NOTE:Placethecapacitorsforsupply,reference,WCT,andVCAP1toVCAP4asclosetothepackageaspossible. Figure55. BipolarSupplyOperation ShieldingAnalogSignalPaths As with any precision circuit, careful printed circuit board (PCB) layout ensures the best performance. It is essential to make short, direct interconnections and avoid stray wiring capacitance—particularly at the analog input pins and AVSS. These analog input pins are high-impedance and extremely sensitive to extraneous noise. The AVSS pin should be treated as a sensitive analog signal and connected directly to the supply ground with proper shielding. Leakage currents between the PCB traces can exceed the input bias current of the ADS1194/6/8 if shielding is not implemented. Digital signals should be kept as far as possible from the analog inputsignalsonthePCB. AnalogInputStructure TheanaloginputoftheADS119xisshowninFigure56. AVDD 5kW INxP, INxN 10pF AVSS Figure56. AnalogInputProtectionCircuit 64 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 POWER-UP SEQUENCING Before device power-up, all digital and analog inputs must be low. At the time of power-up, all of these signals should remain low until the power supplies have stabilized, as shown in Figure 57. At this time, begin supplying the master clock signal to the CLK pin. Wait for time t , then transmit a RESET pulse. After releasing RESET, POR the configuration register must be programmed, see the CONFIG1: Configuration Register 1 subsection of the RegisterMapsectionfordetails.Thepower-upsequencetimingisshowninTable11. t POR PowerSupplies RESET tRST Start Using the Device 18 t CLK Figure57. Power-UpTimingDiagram Table11.Power-UpSequenceTiming SYMBOL DESCRIPTION MIN TYP MAX UNIT t Waitafterpower-upuntilreset 216 t POR CLK t Resetlowwidth 2 t RST CLK SETTING THE DEVICE FOR BASIC DATA CAPTURE The following section outlines the procedure to configure the device in a basic state and capture data. This procedure is intended to put the device in a data sheet condition to check if the device is working properly in the user's system. It is recommended that this procedure be followed initially to get familiar with the device settings. Once this procedure has been verified, the device can be configured as needed. For details on the timings for commands refer to the appropriate sections in the data sheet. Also, some sample programming codes are added fortheECG-specificfunctions.Figure58illustratesaflowchartoutliningtheinitialflowatpower-up. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 65 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com Analog/DigitalPower-Up // Follow Power-Up Sequencing Set CLKSEL Pin = 0 Yes External and Provide External Clock Clock f = 2.048MHz CLK No Set CLKSEL Pin = 1 // If START is TiedHigh,After This Step and Wait for Oscillator //DRDYToggles at f /16384 to Wake Up CLK SetPWDN= 1 SetRESET= 1 // Delay for Power-On Reset and OscillatorStart-Up Waitfor1sfor Power-On Reset // Activate DUT Issue ResetPulse, //CScan be Either Tied Permanently Low Wait for 18 t s // Or Selectively Pulled Low Before Sending CLK // Commands or Reading/Sending Data from/to Device // DeviceWakes Up in RDATAC Mode, so Send Send SDATAC // SDATAC Command so Registers can be Written Command SDATAC Set PDB_REFBUF=1 No External // If UsingInternal Reference, Send This Command and Wait for Internal Reference Reference ¾WREG CONFIG3 0x80 to Settle Yes // Set Device toDR = f /1024 MOD Write Certain Registers, WREG CONFIG1 0x06 Including Input Short WREG CONFIG2 0x00 // Set All Channels to Input Short WREG CHnSET 0x01 // ActivateConversion Set START = 1 // After This PointDRDYShould Toggle at // f /16384 CLK // Put theDevice Back in RDATACMode RDATAC RDATAC Capture Data //LookforDRDYandIssue24 + n´16 SCLKs and Check Noise //Activatea(1mV´V /2.4)Square-WaveTest Signal REF // On All Channels Set Test Signals SDATAC WREG CONFIG2 0x10 WREG CHnSET 0x05 RDATAC Capture Data and Test Signal // LookforDRDYand Issue24 + n´16 SCLKs Figure58. InitialFlowatPower-Up 66 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 Lead-Off Samplecodetosetdclead-offwithpull-up/pull-downresistorsonallchannels WREGLOFF0x13//Comparatorthresholdat95%and5%,pull-up/pull-downresistor//DClead-off WREGCONFIG40x02//Turn-ondclead-offcomparators WREGLOFF_SENSP0xFF//TurnontheP-sideofallchannelsforlead-offsensing WREGLOFF_SENSN0xFF//TurnontheN-sideofallchannelsforlead-offsensing Observethestatusbitsoftheoutputdatastreamtomonitorlead-offstatus. RightLegDrive SamplecodetochooseRLDasanaverageofthefirstthreechannels. WREGRLD_SENSP0x07//Selectchannel1—3P-sideforRLDsensing WREGRLD_SENSN0x07//Selectchannel1—3N-sideforRLDsensing WREGCONFIG3b’x1xx1100//TurnonRLDamplifier,setinternalRLDREFvoltage Sample code to route the RLD_OUT signal through channel 4 N-side and measure RLD with channel 5. Make suretheexternalsidetothechipRLDOUTisconnectedtoRLDIN. WREGCONFIG3b’xxx11100//TurnonRLDamplifier,setinternalRLDREFvoltage,setRLDmeasurementbit WREGCH4SETb’1xxx0111//RouteRLDINtochannel4N-side WREGCH5SETb’1xxx0010//RouteRLDINtobemeasuredatchannel5w.r.tRLDREF PaceDetection Samplecodetoselectchannel5and6outputsforPACE WREGPACEb’00010101//Power-uppaceamplifierandselectchannel5and6forpaceout Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 67 ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 SBAS471C–APRIL2010–REVISEDNOVEMBER2011 www.ti.com REVISION HISTORY NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(April2011)toRevisionC Page • AddedeighthFeaturesbullet ................................................................................................................................................ 1 • ChangedfirstparagraphofDescriptionsection ................................................................................................................... 1 • DeletedduplicateDigitalinputvoltageandDigitaloutputvoltagerowsfromAbsoluteMaximumRatingstable ................. 2 • ChangedACChannelPerformance,Common-moderejectionratioandPower-supplyrejectionratioparameter namesinElectricalCharacteristicstable .............................................................................................................................. 3 • ChangeddescriptionofAnalogInputsection ..................................................................................................................... 19 • UpdatedFigure20 .............................................................................................................................................................. 21 • ChangeddescriptionofDataReady(DRDY)section......................................................................................................... 28 • ChangeddescriptionofSTARTpininSTARTsection ....................................................................................................... 29 • ChangedconversiondesacriptioninContinuousModesection ......................................................................................... 30 • ChangedSTARTpindescriptioninSingle-ShotModesection .......................................................................................... 31 • ChangeddefaultsettinginbitdescriptiontableforCONFIG1:ConfigurationRegister1section ...................................... 41 • Changedsettingdescriptionofbit7inCHnSET:IndividualChannelSettingssection ...................................................... 45 • UpdatedFigure42 .............................................................................................................................................................. 51 • UpdatedFigure43 .............................................................................................................................................................. 52 68 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS1194ADS1196 ADS1198

ADS1194, ADS1196 ADS1198 www.ti.com SBAS471C–APRIL2010–REVISEDNOVEMBER2011 ChangesfromRevisionA(September2010)toRevisionB Page • UpdatedFamilyandOrderingInformationtable................................................................................................................... 2 • AddedDigitalFiltersectiontoElectricalCharacteristicstable.............................................................................................. 3 • UpdatedtestconditionsofInternalReference,OutputvoltageparameterinElectricalCharacteristicstable ..................... 4 • UpdatedformatofPowerDissipation(AnalogSupply=3V)sectionintheElectricalCharacteristicstable ........................ 6 • Changed3VPowerDissipation,QuiescentchannelpowertestconditionsintheElectricalCharacteristicstable .............. 6 • UpdatedformatofPowerDissipation(AnalogSupply=5V)sectionintheElectricalCharacteristicstable ........................ 6 • Changed5VPowerDissipation,QuiescentchannelpowertestconditionsintheElectricalCharacteristicstable .............. 6 • Changedvaluesof-3dBBandwidthcolumnofTable1 ....................................................................................................... 7 • Changedvaluesof-3dBBandwidthcolumnofTable2 ....................................................................................................... 7 • ChangeddescriptionofVCAP3inBGAPinAssignmentstable........................................................................................... 9 • ChangedCLKrowinBGAPinAssignmentstable ............................................................................................................... 9 • ChangedCLKrowofPAGPinAssignmentstable ............................................................................................................. 11 • ChangeddescriptionofVCAP3inPAGPinAssignmentstable......................................................................................... 11 • UpdatedandmovedFigure14 ........................................................................................................................................... 16 • ChangeddescriptionofCHnSETsettinginDeviceNoiseMeasurementssection ............................................................ 18 • Changeddescriptionof(MVDDP–MVDDN)forchannels1,2,5,6,7,and8inSupplyMeasurements(MVDDP, MVDDN)section ................................................................................................................................................................. 19 • UpdatedEquation4 ............................................................................................................................................................ 22 • UpdatedEquation5 ............................................................................................................................................................ 22 • Updatedfootnote1ofFigure26 ......................................................................................................................................... 24 • Addedfootnote1toTable6 ............................................................................................................................................... 25 • AddedstatusandGPIOregisterbitdescriptiontoDataRetrievalsection ......................................................................... 27 • ChangedtitleofFigure29 .................................................................................................................................................. 28 • UpdatedFigure31 .............................................................................................................................................................. 29 • UpdatedFigure32 .............................................................................................................................................................. 30 • UpdatedFigure35 .............................................................................................................................................................. 32 • ChangedSTANDBY:EnterSTANDBYModedescription .................................................................................................. 35 • ChangedIDregisterrowofTable10.................................................................................................................................. 39 • ChangedID:IDControlRegistersection ........................................................................................................................... 40 • ChangedbitdescriptionsofID:IDControlRegistersection .............................................................................................. 40 • Changeddescriptionforbits4to1ofPACE:PACEDetectRegistersection.................................................................... 47 • UpdatedFigure42 .............................................................................................................................................................. 51 • UpdatedFigure43 .............................................................................................................................................................. 52 • UpdatedFigure46 .............................................................................................................................................................. 55 • UpdatedFigure49 .............................................................................................................................................................. 57 • UpdatedFigure50andaddedfootnote2 ........................................................................................................................... 59 • UpdatedFigure51 .............................................................................................................................................................. 60 • UpdatedFigure52 .............................................................................................................................................................. 60 • UpdatedFigure53 .............................................................................................................................................................. 62 • AddedAnalogInputStructuresection ................................................................................................................................ 64 Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 69 ProductFolderLink(s):ADS1194ADS1196 ADS1198

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS1194CPAG ACTIVE TQFP PAG 64 160 Green (RoHS NIPDAU Level-3-260C-168 HR 0 to 70 ADS1194 & no Sb/Br) ADS1194CPAGR ACTIVE TQFP PAG 64 1500 Green (RoHS NIPDAU Level-3-260C-168 HR 0 to 70 ADS1194 & no Sb/Br) ADS1194CZXGR ACTIVE NFBGA ZXG 64 1000 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 70 ADS1194 & no Sb/Br) ADS1194CZXGT ACTIVE NFBGA ZXG 64 250 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 70 ADS1194 & no Sb/Br) ADS1196CPAG ACTIVE TQFP PAG 64 160 Green (RoHS NIPDAU Level-3-260C-168 HR 0 to 70 ADS1196 & no Sb/Br) ADS1196CPAGR ACTIVE TQFP PAG 64 1500 Green (RoHS NIPDAU Level-3-260C-168 HR 0 to 70 ADS1196 & no Sb/Br) ADS1196CZXGR ACTIVE NFBGA ZXG 64 1000 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 70 ADS1196 & no Sb/Br) ADS1196CZXGT ACTIVE NFBGA ZXG 64 250 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 70 ADS1196 & no Sb/Br) ADS1198CPAG ACTIVE TQFP PAG 64 160 Green (RoHS NIPDAU Level-3-260C-168 HR 0 to 70 ADS1198 & no Sb/Br) ADS1198CPAGR ACTIVE TQFP PAG 64 1500 Green (RoHS NIPDAU Level-3-260C-168 HR 0 to 70 ADS1198 & no Sb/Br) ADS1198CZXGR ACTIVE NFBGA ZXG 64 1000 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 70 ADS1198 & no Sb/Br) ADS1198CZXGT ACTIVE NFBGA ZXG 64 250 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 70 ADS1198 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS1194CPAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 ADS1194CZXGR NFBGA ZXG 64 1000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1 ADS1194CZXGT NFBGA ZXG 64 250 180.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1 ADS1196CPAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 ADS1196CZXGR NFBGA ZXG 64 1000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1 ADS1196CZXGT NFBGA ZXG 64 250 180.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1 ADS1198CPAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 ADS1198CZXGR NFBGA ZXG 64 1000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1 ADS1198CZXGT NFBGA ZXG 64 250 180.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS1194CPAGR TQFP PAG 64 1500 350.0 350.0 43.0 ADS1194CZXGR NFBGA ZXG 64 1000 350.0 350.0 43.0 ADS1194CZXGT NFBGA ZXG 64 250 213.0 191.0 55.0 ADS1196CPAGR TQFP PAG 64 1500 350.0 350.0 43.0 ADS1196CZXGR NFBGA ZXG 64 1000 350.0 350.0 43.0 ADS1196CZXGT NFBGA ZXG 64 250 213.0 191.0 55.0 ADS1198CPAGR TQFP PAG 64 1500 350.0 350.0 43.0 ADS1198CZXGR NFBGA ZXG 64 1000 350.0 350.0 43.0 ADS1198CZXGT NFBGA ZXG 64 250 213.0 191.0 55.0 PackMaterials-Page2

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MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 M 0,17 48 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 0,25 SQ 0,05 MIN 11,80 0°–7° 1,05 0,95 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282/C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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