ADS1110 SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003 16-Bit ANALOG-TO-DIGITAL CONVERTER with Onboard Reference FEATURES DESCRIPTION (cid:1) COMPLETE DATA ACQUISITION SYSTEM IN The ADS1110 is a precision, continuously self−calibrating A TINY SOT23-6 PACKAGE Analog-to-Digital (A/D) converter with differential inputs and (cid:1) up to 16 bits of resolution in a small SOT23-6 package. The ONBOARD REFERENCE: onboard 2.048V reference provides an input range of Accuracy: 2.048V ±0.05% ±2.048V differentially. The ADS1110 uses an I2C-compatible Drift: 5ppm/°C serial interface and operates from a single power supply (cid:1) ONBOARD PGA ranging from 2.7V to 5.5V. (cid:1) ONBOARD OSCILLATOR The ADS1110 can perform conversions at rates of 15, 30, 60, (cid:1) or 240 samples per second. The onboard programmable 16-BITS NO MISSING CODES gain amplifier (PGA), which offers gains of up to 8, allows (cid:1) INL: 0.01% of FSR max smaller signals to be measured with high resolution. In (cid:1) CONTINUOUS SELF-CALIBRATION single-conversion mode, the ADS1110 automatically powers (cid:1) down after a conversion, greatly reducing current SINGLE-CYCLE CONVERSION consumption during idle periods. (cid:1) PROGRAMMABLE DATA RATE: 15SPS TO The ADS1110 is designed for applications requiring 240SPS high-resolution measurement, where space and power (cid:1) I2CINTERFACE—EIGHT AVAILABLE consumption are major considerations. Typical applications ADDRESSES include portable instrumentation, industrial process control, (cid:1) and smart transmitters. POWER SUPPLY: 2.7V to 5.5V (cid:1) LOW CURRENT CONSUMPTION: 240µA APPLICATIONS (cid:1) PORTABLE INSTRUMENTATION (cid:1) INDUSTRIAL PROCESS CONTROL (cid:1) SMART TRANSMITTERS (cid:1) CONSUMER GOODS (cid:1) FACTORY AUTOMATION (cid:1) TEMPERATURE MEASUREMENT Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:3)(cid:9) (cid:4)(cid:10)(cid:7)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:16)(cid:17)(cid:18)(cid:11)(cid:14)(cid:12) (cid:11)(cid:19) (cid:20)(cid:21)(cid:15)(cid:15)(cid:22)(cid:12)(cid:18) (cid:17)(cid:19) (cid:14)(cid:13) (cid:23)(cid:21)(cid:24)(cid:25)(cid:11)(cid:20)(cid:17)(cid:18)(cid:11)(cid:14)(cid:12) (cid:26)(cid:17)(cid:18)(cid:22)(cid:27) (cid:1)(cid:15)(cid:14)(cid:26)(cid:21)(cid:20)(cid:18)(cid:19) Copyright  2003, Texas Instruments Incorporated (cid:20)(cid:14)(cid:12)(cid:13)(cid:14)(cid:15)(cid:16) (cid:18)(cid:14) (cid:19)(cid:23)(cid:22)(cid:20)(cid:11)(cid:13)(cid:11)(cid:20)(cid:17)(cid:18)(cid:11)(cid:14)(cid:12)(cid:19) (cid:23)(cid:22)(cid:15) (cid:18)(cid:28)(cid:22) (cid:18)(cid:22)(cid:15)(cid:16)(cid:19) (cid:14)(cid:13) (cid:7)(cid:22)(cid:29)(cid:17)(cid:19) (cid:8)(cid:12)(cid:19)(cid:18)(cid:15)(cid:21)(cid:16)(cid:22)(cid:12)(cid:18)(cid:19) (cid:19)(cid:18)(cid:17)(cid:12)(cid:26)(cid:17)(cid:15)(cid:26) (cid:30)(cid:17)(cid:15)(cid:15)(cid:17)(cid:12)(cid:18)(cid:31)(cid:27) (cid:1)(cid:15)(cid:14)(cid:26)(cid:21)(cid:20)(cid:18)(cid:11)(cid:14)(cid:12) (cid:23)(cid:15)(cid:14)(cid:20)(cid:22)(cid:19)(cid:19)(cid:11)(cid:12)! (cid:26)(cid:14)(cid:22)(cid:19) (cid:12)(cid:14)(cid:18) (cid:12)(cid:22)(cid:20)(cid:22)(cid:19)(cid:19)(cid:17)(cid:15)(cid:11)(cid:25)(cid:31) (cid:11)(cid:12)(cid:20)(cid:25)(cid:21)(cid:26)(cid:22) (cid:18)(cid:22)(cid:19)(cid:18)(cid:11)(cid:12)! (cid:14)(cid:13) (cid:17)(cid:25)(cid:25) (cid:23)(cid:17)(cid:15)(cid:17)(cid:16)(cid:22)(cid:18)(cid:22)(cid:15)(cid:19)(cid:27) www.ti.com

ADS1110 www.ti.com SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003 ABSOLUTE MAXIMUM RATINGS(1) This integrated circuit can be damaged by ESD. Texas Instruments recommends that all VDD to GND −0.3V to +6V integrated circuits be handled with appropriate Input Current 100mA, Momentary precautions. Failure to observe proper handling and installation procedures can cause damage. Input Current 10mA, Continuous Voltage to GND, VIN+, VIN− −0.3V to VDD + 0.3V ESD damage can range from subtle performance degradation Voltage to GND, SDA, SCL −0.5V to 6V to complete device failure. Precision integrated circuits may Maximum Junction Temperature +150°C be more susceptible to damage because very small parametric changes could cause the device not to meet its Operating Temperature Range −40°C to +125°C published specifications. Storage Temperature Range −60°C to +150°C Lead Temperature (soldering, 10s) +300°C (1)Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION I2C PACKAGE SPECIFIED PACKAGE ORDERING TRANSPORT PRODUCT ADDRESS PACKAGE−LEAD DESIGNATOR(1) TEMPERATURE MARKING NUMBER MEDIA, QUANTITY RANGE ADS1110A0IDBVT Tape and Reel, 250 AADDSS11111100 11000011 000000 SSOOTT2233--66 DDBBVV −−4400°°CC ttoo ++8855°°CC EEDD00 ADS1110A0IDBVR Tape and Reel, 3000 ADS1110A1IDBVT Tape and Reel, 250 AADDSS11111100 11000011 000011 SSOOTT2233--66 DDBBVV −−4400°°CC ttoo ++8855°°CC EEDD11 ADS1110A1IDBVR Tape and Reel, 3000 ADS1110A2IDBVT Tape and Reel, 250 AADDSS11111100 11000011 001100 SSOOTT2233--66 DDBBVV −−4400°°CC ttoo ++8855°°CC EEDD22 ADS1110A2IDBVR Tape and Reel, 3000 ADS1110A3IDBVT Tape and Reel, 250 AADDSS11111100 11000011 001111 SSOOTT2233--66 DDBBVV −−4400°°CC ttoo ++8855°°CC EEDD33 ADS1110A3IDBVR Tape and Reel, 3000 ADS1110A4IDBVT Tape and Reel, 250 AADDSS11111100 11000011 110000 SSOOTT2233--66 DDBBVV −−4400°°CC ttoo ++8855°°CC EEDD44 ADS1110A4IDBVR Tape and Reel, 3000 ADS1110A5IDBVT Tape and Reel, 250 AADDSS11111100 11000011 110011 SSOOTT2233--66 DDBBVV −−4400°°CC ttoo ++8855°°CC EEDD55 ADS1110A5IDBVR Tape and Reel, 3000 ADS1110A6IDBVT Tape and Reel, 250 AADDSS11111100 11000011 111100 SSOOTT2233--66 DDBBVV −−4400°°CC ttoo ++8855°°CC EEDD66 ADS1110A6IDBVR Tape and Reel, 3000 ADS1110A7IDBVT Tape and Reel, 250 AADDSS11111100 11000011 111111 SSOOTT2233--66 DDBBVV −−4400°°CC ttoo ++8855°°CC EEDD77 ADS1110A7IDBVR Tape and Reel, 3000 (1)For the most current specification and package information, refer to our web site at www.ti.com. Top View SOT23 2

ADS1110 www.ti.com SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003 ELECTRICAL CHARACTERISTICS All specifications at −40°C to +85°C, VDD = 5V, and all PGAs, unless otherwise noted. ADS1110 PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-Scale Input Voltage (VIN+) − (VIN−) ±2.048/PGA V Analog Input Voltage VIN+ to GND or VIN− to GND GND − 0.2 VDD + 0.2 V Differential Input Impedance 2.8/PGA MΩ Common-Mode Input Impedance PGA = 1 3.5 MΩ PGA = 2 3.5 MΩ PGA = 4 1.8 MΩ PGA = 8 0.9 MΩ SYSTEM PERFORMANCE RReessoolluuttiioonn aanndd NNoo MMiissssiinngg CCooddeess DR = 00 12 12 Bits DR = 01 14 14 Bits DR = 10 15 15 Bits DR = 11 16 16 Bits DDaattaa RRaattee DR = 00 180 240 308 SPS DR = 01 45 60 77 SPS DR = 10 22 30 39 SPS DR = 11 11 15 20 SPS Output Noise See Typical Characteristic Curves Integral Nonlinearity DR = 11, PGA = 1, End Point Fit(1) ±0.004 ±0.010 % of FSR(2) OOffffsseett EErrrroorr PGA = 1 1.2 8 mV PGA = 2 0.7 4 mV PGA = 4 0.5 2.5 mV PGA = 8 0.4 1.5 mV OOffffsseett DDrriifftt PGA = 1 1.2 µV/°C PGA = 2 0.6 µV/°C PGA = 4 0.3 µV/°C PGA = 8 0.3 µV/°C OOffffsseett vvss VVDDDD PGA = 1 800 µV/V PGA = 2 400 µV/V PGA = 4 200 µV/V PGA = 8 150 µV/V Gain Error(3) 0.05 0.40 % PGA Gain Error Match(3) Match Between Any Two PGA Gains 0.02 0.10 % Gain Error Drift(3) 5 40 ppm/°C Gain vs VDD 80 ppm/V CCoommmmoonn--MMooddee RReejjeeccttiioonn At DC and PGA = 8 95 105 dB At DC and PGA = 1 100 dB DIGITAL INPUT/OUTPUT Logic Level VIH 0.7 • VDD 6 V VIL GND − 0.5 0.3 • VDD V VOL IOL = 3mA GND 0.4 V Input Leakage IH VIH = 5.5V 10 µA IL VIL = GND −10 µA POWER-SUPPLY REQUIREMENTS Power-Supply Voltage VDD 2.7 5.5 V SSuuppppllyy CCuurrrreenntt Power Down 0.05 2 µA Active Mode 240 350 µA PPoowweerr DDiissssiippaattiioonn VDD = 5.0V 1.2 1.75 mW VDD = 3.0V 0.675 mW (1)99% of full-scale. (2)FSR = full-scale range = 2 × 2.048V/PGA = 4.096V/PGA. (3)Includes all errors from onboard PGA and reference. 3

ADS1110 www.ti.com SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003 TYPICAL CHARACTERISTICS At TA = 25°C and VDD = 5V, unless otherwise noted. 4

ADS1110 www.ti.com SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003 TYPICAL CHARACTERISTICS (continued) At TA = 25°C and VDD = 5V, unless otherwise noted. 5

ADS1110 www.ti.com SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003 TYPICAL CHARACTERISTICS (continued) At TA = 25°C and VDD = 5V, unless otherwise noted. THEORY OF OPERATION The ADS1110 is a fully differential, 16-bit, self-calibrating, mance of the onboard reference as well as the perfor- delta-sigma A/D converter. Extremely easy to design with mance of the A/D converter core. There are no separate and configure, the ADS1110 allows precise measure- specifications for the onboard reference itself. ments to be obtained with a minimum of effort. The ADS1110 consists of a delta-sigma A/D converter OUTPUT CODE CALCULATION core with adjustable gain, a 2.048V reference, a clock os- cillator, and an I2C interface. Each of these blocks are de- The output code is a scalar value that is, except for clip- ping, proportional to the voltage difference between the scribed in detail in the sections that follow. two analog inputs. The output code is confined to a finite range of numbers; this range depends on the number of bits needed to represent the code. The number of bits ANALOG-TO-DIGITAL CONVERTER needed to represent the output code for the ADS1110 de- pends on the data rate, as shown in Table 1. The ADS1110 A/D converter core consists of a differential switched-capacitor delta-sigma modulator followed by a digital filter. The modulator measures the voltage differ- NUMBER OF MINIMUM MAXIMUM ence between the positive and negative analog inputs and DATA RATE BITS CODE CODE compares it to a reference voltage, which, in the ADS1110, 15SPS 16 −32,768 32,767 is 2.048V. The digital filter receives a high-speed bitstream 30SPS 15 −16,384 16,383 from the modulator and outputs a code, which is a number 60SPS 14 −8192 8191 proportional to the input voltage. 240SPS 12 −2048 2047 Table 1. Minimum and Maximum Codes VOLTAGE REFERENCE For a minimum output code of Min Code, gain setting of PGA, and positive and negative input voltages of V and IN+ The ADS1110 contains an onboard 2.048V voltage refer- VIN−, the output code is given by the expression: ence. This reference is always used as the A/D converter’s voltage reference; an external reference cannot be con- Output Code(cid:1)−1(cid:2)Min Code(cid:2)PGA(cid:2)(VIN(cid:3))(cid:4)(VIN(cid:4)) 2.048V nected. The ADS1110’s voltage reference is internal only, In the previous expression, it is important to note that the and cannot be measured directly or used by external cir- negated minimum output code is used. The ADS1110 cuitry. outputs codes in binary two’s complement format, so the The onboard reference’s specifications are part of the absolute values of the minima and maxima are not the ADS1110’s overall gain and drift specifications. The con- same; the maximum n−bit code is 2n−1 − 1, while the verter’s drift and gain error specifications reflect the perfor- minimum n−bit code is −1 × 2n−1. 6

ADS1110 www.ti.com SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003 For example, the ideal expression for output codes with a generated by the onboard clock oscillator, so its frequency, data rate of 16SPS and PGA = 2 is: nominally 275kHz, is dependent on supply voltage and temperature. (V )(cid:4)(V ) Output Code(cid:1)16384(cid:2)2(cid:2) IN(cid:3) IN(cid:4) 2.048V The common-mode and differential input impedances are different. For a gain setting of PGA, the differential input The ADS1110 outputs all codes right-justified and impedance is typically: sign-extended. This makes it possible to perform averaging on the higher data rate codes using only a 16-bit 2.8MΩ/PGA accumulator. The common-mode impedance also depends on the PGA Table 2 shows the output codes for various input levels. setting. See the Electrical Characteristics for details. The typical value of the input impedance often cannot be neglected. Unless the input source has a low impedance, SELF-CALIBRATION the ADS1110’s input impedance may affect the measurement accuracy. For sources with high output The previous expressions for the ADS1110’s output code impedance, buffering may be necessary. Bear in mind, do not account for the gain and offset errors in the however, that active buffers introduce noise, and also modulator. To compensate for these, the ADS1110 introduce offset and gain errors. All of these factors should incorporates self-calibration circuitry. be considered in high-accuracy applications. The self-calibration system operates continuously and Because the clock oscillator frequency drifts slightly with requires no user intervention. No adjustments can be temperature, the input impedances will also drift. For many made to the self-calibration system, and none need to be applications, this input impedance drift can be neglected, made. The self-calibration system cannot be deactivated. and the expression given above for typical input impedance can be used. The offset and gain error figures shown in the Electrical Characteristics include the effects of calibration. ALIASING CLOCK OSCILLATOR If frequencies are input to the ADS1110 that exceed half the data rate, aliasing will occur. To prevent aliasing, the The ADS1110 features an onboard clock oscillator, which input signal must be bandlimited. Some signals are drives the operation of the modulator and digital filter. The inherently bandlimited. For example, a thermocouple’s Typical Characteristics show variations in data rate over output, which has a limited rate of change, may supply voltage and temperature. nevertheless contain noise and interference components. It is not possible to operate the ADS1110 with an external These can fold back into the sampling band just as any system clock. other signal can. The ADS1110’s digital filter provides some attenuation of high-frequency noise, but the digital filter’s Sinc1 INPUT IMPEDANCE frequency response cannot completely replace an anti-aliasing filter. For a few applications, some external The ADS1110 uses a switched-capacitor input stage. To filtering may be needed; in such applications, a simple RC external circuitry, it looks roughly like a resistance. The filter will suffice. resistance value depends on the capacitor values and the rate at which they are switched. The switching frequency When designing an input filter circuit, remember to take is the same as the modulator frequency; the capacitor into account the interaction between the filter network and values depend on the PGA setting. The switching clock is the input impedance of the ADS1110. DIFFERENTIAL INPUT SIGNAL DDAATTAA RRAATTEE −2.048V(1) −1LSB ZERO +1LSB +2.048V 15SPS 8000H FFFFH 0000H 0001H 7FFFH 30SPS C000H FFFFH 0000H 0001H 3FFFH 60SPS E000H FFFFH 0000H 0001H 1FFFH 240SPS F800H FFFFH 0000H 0001H 07FFH (1)Differential input only; do not drive the ADS1110’s inputs below −200mV. Table 2. Output Codes for Different Input Signals 7

ADS1110 www.ti.com SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003 USING THE ADS1110 An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is transmitted across the I2C bus in groups of eight bits. To OPERATING MODES send a bit on the I2C bus, the SDA line is driven to the appropriate level while SCL is LOW (a LOW on SDA The ADS1110 operates in one of two modes: continuous indicates the bit is zero; a HIGH indicates the bit is one). conversion or single conversion. Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on SCL clocks the SDA bit In continuous conversion mode, the ADS1110 continuous- into the receiver’s shift register. ly performs conversions. Once a conversion has been completed, the ADS1110 places the result in the output register and immediately begins another conversion. The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads from In single conversion mode, the ADS1110 waits until the a slave, the slave drives the data line; when a master ST/DRDY bit in the conversion register is set to 1. When sends to a slave, the master drives the data line. The this happens, the ADS1110 powers up and performs a master always drives the clock line. The ADS1110 never single conversion. After the conversion completes, the drives SCL, because it cannot act as a master. On the ADS1110 places the result in the output register, resets the ADS1110, SCL is an input only. ST/DRDY bit to 0, and powers down. Writing a 1 to ST/DRDY while a conversion is in progress has no effect. Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When communication is When switched from continuous conversion mode to taking place, the bus is active. Only master devices can single conversion mode, the ADS1110 completes the start a communication. They do this by causing a START current conversion, resets the ST/DRDY bit to 0, and condition on the bus. Normally, the data line is only allowed powers down. to change state while the clock line is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or its counterpart, a STOP condition. A RESET AND POWER−UP START condition is when the clock line is HIGH and the data line goes from HIGH to LOW. A STOP condition is When the ADS1110 powers up, it automatically performs when the clock line is HIGH and the data line goes from a reset. As part of the reset, the ADS1110 sets all of the bits LOW to HIGH. in the configuration register to their default settings. The ADS1110 responds to the I2C General Call Reset After the master issues a START condition, it sends a byte that indicates which slave device it wants to communicate command. When the ADS1110 receives a General Call with. This byte is called the address byte. Each device on Reset, it performs an internal reset, exactly as though it had just been powered on. an I2C bus has a unique 7-bit address to which it responds. (Slaves can also have 10-bit addresses; see the I2C specification for details.) The master sends an address in the address byte, together with a bit that indicates whether I2C INTERFACE it wishes to read from or write to the slave device. The ADS1110 communicates through an I2C Every byte transmitted on the I2C bus, whether it is (inter-integrated circuit) interface. I2C is a two-wire address or data, is acknowledged with an acknowledge open-drain interface supporting multiple devices and bit. When a master has finished sending a byte (eight data masters on a single bus. Devices on the I2C bus only drive bits) to a slave, it stops driving SDA and waits for the slave the bus lines LOW by connecting them to ground; they to acknowledge the byte. The slave acknowledges the never drive the bus lines HIGH. Instead, the bus wires are byte by pulling SDA LOW. The master then sends a clock pulled HIGH by pull-up resistors, so the bus wires are pulse to clock the acknowledge bit. Similarly, when a HIGH when no device is driving them LOW. This way, two master has finished reading a byte, it pulls SDA LOW to devices cannot conflict; if two devices drive the bus acknowledge this to the slave. It then sends a clock pulse simultaneously, there is no driver contention. to clock the bit. (Remember that the master always drives Communication on the I2C bus always takes place the clock line.) between two devices, one acting as the master and the other acting as the slave. Both masters and slaves can A not-acknowledge is performed by simply leaving SDA read and write, but slaves can only do so under the HIGH during an acknowledge cycle. If a device is not direction of the master. Some I2C devices can act as present on the bus, and the master attempts to address it, masters or slaves, but the ADS1110 can only act as a slave it will receive a not−acknowledge because no device is device. present at that address to pull the line LOW. 8

ADS1110 www.ti.com SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003 When a master has finished communicating with a slave, Each variant of the ADS1110 is marked with EDx, where it may issue a STOP condition. When a STOP condition is x identifies the address variant. For example, the issued, the bus becomes idle again. A master may also ADS1110A0 is marked ED0, and the ADS1110A3 is issue another START condition. When a START condition marked ED3. See the Package/Ordering Information table is issued while the bus is active, it is called a repeated for a complete listing. START condition. A timing diagram for an ADS1110 I2C transaction is shown in Figure 1. The parameters for this diagram are given in I2C GENERAL CALL Table 3. The ADS1110 responds to a General Call Reset, which is an address byte of 00h followed by a data byte of 06 . The H ADS1110 I2C ADDRESSES ADS1110 acknowledges both bytes. The ADS1110 I2C address is 1001aaa, where aaa are bits On receiving a General Call Reset, the ADS1110 performs set at the factory. The ADS1110 is available in eight a full internal reset, just as though it had been powered off different versions, each having a different I2C address. For and then on. If a conversion is in process, it is interrupted; example, the ADS1110A0 has address 1001000, and the the output register is set to zero, and the configuration ADS1110A3 has address 1001011. See the Ordering register is set to its default setting. Information table for a complete listing. The ADS1110 always acknowledges the General Call The I2C address is the only difference between the eight address byte of 00 , but it does not acknowledge any H variants. In all other respects, they operate identically. General Call data bytes other than 04 or 06 . H H Figure 1. I2C Timing Diagram FAST MODE HIGH-SPEED MODE PARAMETER MIN MAX MIN MAX UNITS SCLK operating frequency t(SCLK) 0.4 3.4 MHz Bus free time between START and STOP condition t(BUF) 600 160 ns Hold time after repeated START condition. t(HDSTA) 600 160 ns After this period, the first clock is generated. Repeated START condition setup time t(SUSTA) 600 160 ns Stop condition setup time t(SUSTO) 600 160 ns Data hold time t(HDDAT) 0 0 ns Data setup time t(SUDAT) 100 10 ns SCLK clock LOW period t(LOW) 1300 160 ns SCLK clock HIGH period t(HIGH) 600 60 ns Clock/data fall time tF 300 160 ns Clock/data rise time tR 300 160 ns Table 3. Timing Diagram Definitions 9

ADS1110 www.ti.com SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003 I2C DATA RATES For more information on High-speed mode, consult the I2C specification. The I2C bus operates in one of three speed modes: Standard, which allows a clock frequency of up to 100kHz; Fast, which allows a clock frequency of up to 400kHz; and REGISTERS High-speed mode (also called Hs mode), which allows a clock frequency of up to 3.4MHz. The ADS1110 is fully The ADS1110 has two registers that are accessible via its compatible with all three modes. I2C port. The output register contains the result of the last No special action needs to be taken to use the ADS1110 conversion; the configuration register allows the user to in Standard or Fast modes, but High-speed mode must be change the ADS1110 operating mode and query the status activated. To activate High-speed mode, send a special of the device. address byte of 00001xxx following the START condition, where xxx are bits unique to the Hs-capable master. This byte is called the Hs master code. (Note that this is different OUTPUT REGISTER from normal address bytes: the low bit does not indicate read/write status.) The ADS1110 will not acknowledge this The 16-bit output register contains the result of the last byte; the I2C specification prohibits acknowledgment of conversion in binary two’s complement format. Following the Hs master code. On receiving a master code, the reset or power−up, the output register is cleared to zero; ADS1110 will switch on its Hs mode filters, and it remains zero until the first conversion is completed. communicate at up to 3.4MHz. The ADS1110 will switch out of Hs mode with the next STOP condition. The output register’s format is shown in Table 4. BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 4. Output Register 10

ADS1110 www.ti.com SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003 CONFIGURATION REGISTER Note that the output register is returned from the ADS1110 before the configuration register. The state of the The 8-bit configuration register can be used to control the ST/DRDY bit applies to the data just read from the output ADS1110’s operating mode, data rate, and PGA settings. register, and not to the data from the next read operation. The configuration register format is shown in Table 5. The default setting is 8C . Bits 6−5: Reserved H Bits 6 and 5 must be set to zero. BIT 7 6 5 4 3 2 1 0 NAME ST/DRDY 0 0 SC DR1 DR0 PGA1 PGA0 Bit 4: SC DEFAULT 1 0 0 0 1 1 0 0 SC controls whether the ADS1110 is in continuous Table 5. Configuration Register conversion or single conversion mode. When SC is 1, the ADS1110 is in single conversion mode; when SC is 0, the Bit 7: ST/DRDY ADS1110 is in continuous conversion mode. The default setting is 0. The meaning of the ST/DRDY bit depends on whether it is being written to or read from. Bits 3−2: DR In single conversion mode, writing a 1 to the ST/DRDY bit Bits 3 and 2 control the ADS1110’s data rate, as shown in causes a conversion to start, and writing a 0 has no effect. Table 6. In continuous conversion mode, the ADS1110 ignores the value written to ST/DRDY. DR1 DR0 DATA RATE When read, ST/DRDY indicates whether the data in the 0 0 240SPS output register is new data. If ST/DRDY is 0, the data just 0 1 60SPS read from the output register is new, and has not been read 1 0 30SPS before. If ST/DRDY is 1, the data just read from the output 1(1) 1(1) 15SPS(1) register has been read before. (1)Default setting. The ADS1110 sets ST/DRDY to 0 when it writes data into Table 6. DR Bits the output register. It sets ST/DRDY to 1 after any of the bits in the configuration register have been read. (Note that the read value of the bit is independent of the value written Bits 1−0: PGA to this bit.) Bits 1 and 0 control the ADS1110’s gain setting, as shown In continuous-conversion mode, use ST/DRDY to in Table 7. determine when new conversion data is ready. If ST/DRDY is 1, the data in the output register has already been read, and is not new. If it is 0, the data in the output PGA1 PGA0 GAIN register is new, and has not yet been read. 0(1) 0(1) 1(1) In single-conversion mode, use ST/DRDY to determine 0 1 2 1 0 4 when a conversion has completed. If ST/DRDY is 1, the 1 1 8 output register data is old, and the conversion is still in (1)Default setting. process; if it is 0, the output register data is the result of the new conversion. Table 7. PGA Bits 11

ADS1110 www.ti.com SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003 READING FROM THE ADS1110 register is read more than once during a conversion cycle, it will return the same data each time. New data will be To read the output register and the configuration register returned only when the output register has been updated. from the ADS1110, address the ADS1110 for reading, then A timing diagram of a typical ADS1110 read operation is read three bytes. The first two bytes will be the output shown in Figure 2. register’s contents, and the third will be the configuration register’s contents. WRITING TO THE ADS1110 It is not required to read the configuration register byte. It To write to the configuration register, address the ADS1110 is permissible to read fewer than three bytes during a read for writing, and send one byte. The byte will be written to operation. the configuration register. Note that the output register cannot be written to. Reading more than three bytes from the ADS1110 has no Writing more than one byte to the ADS1110 has no effect. effect. All bytes following the third will be FF . H The ADS1110 will ignore any bytes sent to it after the first It is possible to ignore the ST/DRDY bit and read data from one, and it will only acknowledge the first byte. the ADS1110’s output register at any time, without regard A timing diagram of a typical ADS1110 write operation is to whether a new conversion is complete. If the output shown in Figure 3. Figure 2. Timing Diagram for Reading From the ADS1110 Figure 3. Timing Diagram for Writing To the ADS1110 12

ADS1110 www.ti.com SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003 APPLICATIONS INFORMATION Pull-up resistors are necessary on both the SDA and SCL lines because I2C bus drivers are open-drain. The size of these resistors depends on the bus operating speed and The sections that follow give example circuits and tips for capacitance of the bus lines. Higher-value resistors using the ADS1110 in various situations. consume less power, but increase the transition times on the bus, limiting the bus speed. Lower-value resistors allow higher speed at the expense of higher power BASIC CONNECTIONS consumption. Long bus lines have higher capacitance and require smaller pull-up resistors to compensate. The For many applications, connecting the ADS1110 is resistors should not be too small; if they are, the bus drivers extremely simple. A basic connection diagram for the may not be able to pull the bus lines low. ADS1110 is shown in Figure 4. CONNECTING MULTIPLE DEVICES Connecting multiple ADS1110s to a single bus is trivial. The ADS1110 is available in eight different versions, each of which has a different I2C address. An example showing three ADS1110s connected on a single bus is shown in Figure 5. Up to eight ADS1110s (provided their addresses are different) can be connected to a single bus. Figure 4. Typical Connections of the ADS1110 The fully differential voltage input of the ADS1110 is ideal for connection to differential sources with moderately low source impedance, such as bridge sensors and thermistors. Although the ADS1110 can read bipolar differential signals, it cannot accept negative voltages on either input. It may be helpful to think of the ADS1110 positive voltage input as non−inverting, and of the negative input as inverting. When the ADS1110 is converting, it draws current in short spikes. The 0.1µF bypass capacitor supplies the momentary bursts of extra current needed from the supply. The ADS1110 interfaces directly to standard mode, fast mode, and high−speed mode I2C controllers. Any microcontroller’s I2C peripheral, including master-only Figure 5. Connecting Multiple ADS1110s and non-multiple-master I2C peripherals, will work with the ADS1110. The ADS1110 does not perform Note that only one set of pull-up resistors is needed per clock-stretching (i.e., it never pulls the clock line low), so bus. The pull-up resistor values may need to be lowered it is not necessary to provide for this unless slightly to compensate for the additional bus capacitance clock-stretching devices are on the same I2C bus. presented by multiple devices and increased line length. 13

ADS1110 www.ti.com SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003 Figure 6 shows a circuit with several different devices connected to a single I2C bus. A Texas Instruments TMP100 temperature sensor and a Texas Instruments DAC8574 4-channel 16-bit digital-to-analog converter share the bus with two ADS1110s. Figure 7. Using GPIO with a Single ADS1110 Bit-banging I2C with GPIO pins can be done by setting the GPIO line to zero and toggling it between input and output modes to apply the proper bus states. To drive the line low, the pin is set to output a zero; to let the line go high, the pin is set to input. When the pin is set to input, the state of the pin can be read; if another device is pulling the line low, this will read as a zero in the port’s input register. Note that no pull-up resistor is shown on the SCL line. In this simple case, the resistor is not needed; the microcontroller can simply leave the line on output, and set it to one or zero as appropriate. It can do this because the ADS1110 never drives its clock line low. This technique can also be used with multiple devices, and has the advantage of lower current consumption due to the absence of a resistive pull-up. If there are any devices on the bus that may drive their Figure 6. Connecting Multiple Device Types clock lines low, the above method should not be used; the SCL line should be high-Z or zero and a pull-up resistor The TMP100 and DAC8574 devices detect their I2C bus provided as usual. Note also that this cannot be done on addresses based on the states of pins. In the example, the the SDA line in any case, because the ADS1110 does drive TMP100 has the address 1001011, and the DAC8574 has the SDA line low from time to time, as all I2C devices do. the address 1001100. Consult the DAC8574 and TMP100 data sheets, located at www.ti.com, for details. Some microcontrollers have selectable strong pull-up circuits built in to their GPIO ports. In some cases, these can be switched on and used in place of an external pull-up USING GPIO PORTS FOR I2C resistor. Weak pull-ups are also provided on some microcontrollers, but usually these are too weak for I2C Most microcontrollers have programmable input/output communication. If there is any doubt about the matter, test pins that can be set in software to act as inputs or outputs. the circuit before committing it to production. If an I2C controller is not available, the ADS1110 can be connected to GPIO pins and the I2C bus protocol simulated, or “bit-banged”, in software. An example of this for a single ADS1110 is shown in Figure 7. 14

ADS1110 www.ti.com SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003 SINGLE-ENDED INPUTS Although the ADS1110 has a fully differential input, it can easily measure single-ended signals. A simple single-ended connection scheme is shown in Figure 8. The ADS1110 is configured for single-ended measurement by grounding either of its input pins, usually V , and applying the input signal to V . The IN− IN+ single-ended signal can range from 0V to 2.048V. The ADS1110 loses no linearity anywhere in its input range. Negative voltages cannot be applied to this circuit because the ADS1110 inputs can only accept positive voltages. Figure 9. Low-Side Current Measurement It is suggested that the ADS1110 be operated at a gain of 8. The gain of the OPA335 can then be set lower. For a gain of 8, the op amp should be set up to give a maximum output voltage of no greater than 0.256V. If the shunt resistor is sized to provide a maximum voltage drop of 50mV at full-scale current, the full-scale input to the ADS1110 is 0.2V. Figure 8. Measuring Single-Ended Inputs ADVICE The ADS1110 input range is bipolar differential with The ADS1110 is fabricated in a small-geometry respect to the reference, i.e. 2.048V. The single-ended low-voltage process. The analog inputs feature protection circuit shown in Figure 8 covers only half the ADS1110 diodes to the supply rails. However, the current-handling input scale because it does not produce differentially ability of these diodes is limited, and the ADS1110 can be negative inputs; therefore, one bit of resolution is lost. permanently damaged by analog input voltages that remain more than approximately 300mV beyond the rails for extended periods. One way to protect against LOW-SIDE CURRENT MONITOR overvoltage is to place current-limiting resistors on the input lines. The ADS1110 analog inputs can withstand Figure 9 shows a circuit for a low-side shunt-type current momentary currents of as large as 10mA. monitor. The circuit reads the voltage across a shunt The previous paragraph does not apply to the I2C ports, resistor, which is sized as small as possible while still which can both be driven to 6V regardless of the supply. giving a readable output voltage. This voltage is amplified by an OPA335 low-drift op amp and the result is read by the If the ADS1110 is driven by an op amp with high-voltage ADS1110. supplies, such as ±12V, protection should be provided, even if the op amp is configured so that it does not output out-of-range voltages. Many op amps seek to one of the supply rails immediately when power is applied, usually before the input has stabilized; this momentary spike can damage the ADS1110. Sometimes this damage is incremental and results in slow, long-term failure—which can be disastrous for permanently installed, low-maintenance systems. If an op amp or other front-end circuitry is used with the ADS1110, its performance characteristics must be taken into account. A chain is only as strong as its weakest link. 15

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS1110A0IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 ED0 & no Sb/Br) ADS1110A0IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM ED0 & no Sb/Br) ADS1110A0IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM ED0 & no Sb/Br) ADS1110A1IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM ED1 & no Sb/Br) ADS1110A1IDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM ED1 & no Sb/Br) ADS1110A1IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM ED1 & no Sb/Br) ADS1110A1IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM ED1 & no Sb/Br) ADS1110A2IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM ED2 & no Sb/Br) ADS1110A2IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM ED2 & no Sb/Br) ADS1110A2IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM ED2 & no Sb/Br) ADS1110A3IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM ED3 & no Sb/Br) ADS1110A4IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM ED4 & no Sb/Br) ADS1110A4IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM ED4 & no Sb/Br) ADS1110A4IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM ED4 & no Sb/Br) ADS1110A5IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM ED5 & no Sb/Br) ADS1110A5IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM ED5 & no Sb/Br) ADS1110A5IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM ED5 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS1110A6IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM ED6 & no Sb/Br) ADS1110A7IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM ED7 & no Sb/Br) ADS1110A7IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM ED7 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS1110A0IDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 ADS1110A0IDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 ADS1110A1IDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 ADS1110A1IDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 ADS1110A2IDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 ADS1110A2IDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 ADS1110A3IDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 ADS1110A4IDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 ADS1110A4IDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 ADS1110A5IDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 ADS1110A5IDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 ADS1110A6IDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 ADS1110A7IDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 ADS1110A7IDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS1110A0IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 ADS1110A0IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 ADS1110A1IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 ADS1110A1IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 ADS1110A2IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 ADS1110A2IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 ADS1110A3IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 ADS1110A4IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 ADS1110A4IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 ADS1110A5IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 ADS1110A5IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 ADS1110A6IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 ADS1110A7IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 ADS1110A7IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0006A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 B A 1.45 MAX PIN 1 INDEX AREA 1 6 2X 0.95 3.05 2.75 1.9 5 2 4 3 0.50 6X 0.25 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214840/B 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178. www.ti.com

EXAMPLE BOARD LAYOUT DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214840/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214840/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated