100 MHz to 1000 MHz Integrated Broadband Receiver ADRF6850 FEATURES GENERAL DESCRIPTION IQ quadrature demodulator The ADRF6850 is a highly integrated broadband quadrature Integrated fractional-N PLL and VCO demodulator, frequency synthesizer, and variable gain amplifier Gain control range: 60 dB (VGA). The device covers an operating frequency range from Input frequency range: 100 MHz to 1000 MHz 100 MHz to 1000 MHz for use in both narrow-band and wideband Input P1dB: +12 dBm at 0 dB gain communications applications, performing quadrature demodu- Input IP3: +22.5 dBm at 0 dB gain lation from IF directly to baseband frequencies. Noise figure: 11 dB at >39 dB gain, 49 dB at 0 dB gain The ADRF6850 demodulator includes a high modulus Baseband 1 dB bandwidth: 250 MHz in wideband mode, fractional-N frequency synthesizer with integrated VCO, 50 MHz in narrow-band mode providing better than 1 Hz frequency resolution, and a 60 dB SPI/I2C serial interface gain control range provided by a front-end VGA. Power supply: +3.3 V/350 mA Control of all the on-chip registers is through a user-selected APPLICATIONS SPI interface or I2C interface. The device operates from a single Broadband communications power supply ranging from 3.15 V to 3.45 V. Cellular communications Satellite communications FUNCTIONAL BLOCK DIAGRAM VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 LOMON LOMON IBB IBB 60dB CCOMP1 GAIN CONTROL CCOMP2 RANGE CCOMP3 RFI 0°/90° DRIVER RFDIV RFI VCO VTUNE CORE RFCM VOCM SEQUENCED VGAIN GAIN QBB INTERFACE QBB RSET REFERENCE REFIN DOU×B2LER DI5V-BIDITER ÷2 + PHASE –FDREETQEUCETNOCRY CHPUAMRGPE CP CURRENT SETTING LF3 N-COUNTER LF2 THIRD-ORDER LDET CSLDKI//SSDCAL SI2PCI/ INFTREARCPTOIOLANTAOLR RFCP4 RFCP3 RFCP2 RFCP1 TTEESSTTLLOO SDO INTERFACE CS FRACTIONAL MODULUS INTEGER REGISTER 225 REGISTER ADRF6850 GND MUXOUT 09316-001 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.

ADRF6850 TABLE OF CONTENTS Features .............................................................................................. 1 I2C Interface ................................................................................ 20 Applications ....................................................................................... 1 SPI Interface ................................................................................ 22 General Description ......................................................................... 1 Program Modes .......................................................................... 24 Functional Block Diagram .............................................................. 1 Register Map ................................................................................... 26 Revision History ............................................................................... 2 Register Map Summary ............................................................. 26 Specifications ..................................................................................... 3 Register Bit Descriptions ........................................................... 27 Timing Characteristics ................................................................ 5 Suggested Power-Up Sequence ..................................................... 30 Absolute Maximum Ratings ............................................................ 7 Initial Register Write Sequence ................................................ 30 ESD Caution .................................................................................. 7 Evaluation Board ............................................................................ 31 Pin Configuration and Function Descriptions ............................. 8 General Description ................................................................... 31 Typical Performance Characteristics ........................................... 10 Hardware Description ............................................................... 31 Theory of Operation ...................................................................... 18 PCB Schematic............................................................................ 33 Overview ...................................................................................... 18 PCB Artwork............................................................................... 34 PLL Synthesizer and VCO ......................................................... 18 Bill of Materials ........................................................................... 35 Quadrature Demodulator.......................................................... 20 Outline Dimensions ....................................................................... 36 Variable Gain Amplifier (VGA) ............................................... 20 Ordering Guide .......................................................................... 36 REVISION HISTORY 10/10—Revision 0: Initial Version Rev. 0 | Page 2 of 36

ADRF6850 SPECIFICATIONS V = 3.3 V; ambient temperature (T ) = 25°C; Z = 50 Ω; Z = 100 Ω differential; PLL loop bandwidth = 50 kHz; REFIN = 13.5 MHz; CC A S L PFD = 27 MHz; baseband frequency = 20 MHz, narrow-band mode, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit RF INPUT RFI, RFI, VGAIN pins Operating Frequency Range 100 1000 MHz Input P1dB 0 dB gain +12 dBm 60 dB gain −48 dBm Input IP3 0 dB gain +22.5 dBm 60 dB gain −38 dBm Input IP2 0 dB gain, single-ended input +40 dBm 60 dB gain, single-ended input −20 dBm Noise Figure (NF) 0 dB gain 49 dB <39 dB gain NF rises 1:1 as gain in dB falls >39 dB gain 11 dB Maximum Gain Z = 50 Ω single-ended, Z = 100 Ω differential 60 dB S L Minimum Gain Z = 50 Ω single-ended, Z = 100 Ω differential 0 dB S L Gain Conformance Error1 V from 200 mV to 1.3 V 0.5 dB GAIN Gain Slope 25 mV/dB VGAIN Input Impedance 20 kΩ Return Loss Relative to Z = 50 Ω, 100 MHz to 1 GHz 15 dB S REFERENCE CHARACTERISTICS REFIN pin Input Frequency With R divide-by-2 divider enabled 10 300 MHz With R divide-by-2 divider disabled 10 165 MHz REFIN Input Sensitivity 0.4 V V p-p CC REFIN Input Capacitance 10 pF REFIN Input Current ±100 µA CHARGE PUMP CP and RSET pins I Sink/Source Programmable CP High Value With R = 4.7 kΩ 5 mA SET Low Value 312.5 µA Absolute Accuracy With R = 4.7 kΩ 2.5 % SET VCO Gain K 15 MHz/V VCO SYNTHESIZER SPECIFICATIONS Loop bandwidth = 50 kHz Frequency Increment 1 Hz Phase Frequency Detector 10 30 MHz Spurs Integer boundary < loop bandwidth −55 dBc >10 MHz offset from carrier −70 dBc Phase Noise LO frequency = 1000 MHz @ 10 Hz offset −75 dBc/Hz @ 100 Hz offset −80 dBc/Hz @ 1 kHz offset −90 dBc/Hz @ 10 kHz offset −98 dBc/Hz @ 100 kHz offset −110 dBc/Hz @ 1 MHz offset −136 dBc/Hz >10 MHz offset −149 dBc/Hz Integrated Phase Noise 1 kHz to 8 MHz integration bandwidth 0.26 °rms Rev. 0 | Page 3 of 36

ADRF6850 Parameter Test Conditions/Comments Min Typ Max Unit Frequency Settling Any step size, maximum frequency error = 1 kHz 260 μs Maximum Frequency Step for No Frequency step with no autocalibration routine; 100 kHz Autocalibration Register CR24, Bit 0 = 1 BASEBAND OUTPUTS IBB, IBB, QBB, QBB, VOCM pins Maximum Swing Driving Z = 100 Ω differential 2.5 V p-p L Common-Mode Range 1.2 1.6 V Output Impedance Differential 28 Ω Output DC Offset RFI terminated in Z = 50 Ω ±20 mV S 1 dB Bandwidth Wideband Mode 250 MHz Narrow-Band Mode 50 MHz IQ Balance Amplitude Wideband Mode Baseband frequency ≤ 250 MHz ±0.1 dB Narrow-Band Mode Baseband frequency ≤ 33.2 MHz ±0.1 dB Phase Wideband Mode Baseband frequency ≤ 250 MHz ±0.5 Degrees Narrow-Band Mode Baseband frequency ≤ 33.2 MHz ±0.25 Degrees IQ Output Impedance Mismatch Baseband frequency = 10 MHz ±0.3 % Group Delay Variation Wideband Mode Baseband frequency ≤ 210 MHz 0.25 ns Baseband frequency ≤ 250 MHz 0.35 ns Narrow-Band Mode Baseband frequency ≤ 33.2 MHz 0.2 ns LO to IQ Leakage 1× LO −40 dBm 2× LO −60 dBm 4× LO −60 dBm RF to IQ Leakage Relative to IQ output level −40 dBc MONITOR OUTPUT LOMON and LOMON pins Nominal Output Power −24 dBm LOGIC INPUTS SDI/SDA, CLK/SCL, CS pins Input High Voltage, V CS 1.4 V INH Input Low Voltage, V CS 0.6 V INL Input High Voltage, V SDI/SDA, CLK/SCL 2.1 V INH Input Low Voltage, V SDI/SDA, CLK/SCL 1.1 V INL Input Current, I /I CS, SDI/SDA, CLK/SCL ±1 µA INH INL Input Capacitance, C CS, SDI/SDA, CLK/SCL 10 pF IN LOGIC OUTPUTS Output High Voltage, V SDO, LDET pins; I = 500 μA 2.8 V OH OH Output Low Voltage, V SDO, LDET pins; I = 500 μA 0.4 V OL OL SDA (SDI/SDA) pins; I = 3 mA 0.4 V OL POWER SUPPLIES VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8, and VCC9 pins Voltage Range 3.15 3.3 3.45 V Supply Current 350 440 mA Operating Temperature −40 +85 °C 1 Difference between channel gain and linear fit to channel gain. Rev. 0 | Page 4 of 36

ADRF6850 TIMING CHARACTERISTICS I2C Interface Timing Table 2. Parameter1 Symbol Limit Unit SCL Clock Frequency f 400 kHz max SCL SCL Pulse Width High t 600 ns min HIGH SCL Pulse Width Low t 1300 ns min LOW Start Condition Hold Time t 600 ns min HD;STA Start Condition Setup Time t 600 ns min SU;STA Data Setup Time t 100 ns min SU;DAT Data Hold Time t 300 ns min HD;DAT Stop Condition Setup Time t 600 ns min SU;STO Data Valid Time t 900 ns max VD;DAT Data Valid Acknowledge Time t 900 ns max VD;ACK Bus Free Time t 1300 ns min BUF 1 See Figure 2. tSU;DAT ttVVDD;;DAACTK A(ANCDK SIGNAL ONLY) tBUF SDA tHD;STA tSU;STA tSU;STO tLOW SCL COSNTDASIRTITON 1/tfHSCDL;DAT tHIGH S COSNTDPOITPION S 09316-002 Figure 2. I2C Port Timing Diagram Rev. 0 | Page 5 of 36

ADRF6850 SPI Interface Timing Table 3. Parameter1 Symbol Limit Unit CLK Frequency f 20 MHz max CLK CLK Pulse Width High t 15 ns min 1 CLK Pulse Width Low t 15 ns min 2 Start Condition Hold Time t 5 ns min 3 Data Setup Time t 10 ns min 4 Data Hold Time t 5 ns min 5 Stop Condition Setup Time t 5 ns min 6 SDO Access Time t 15 ns min 7 CS to SDO High Impedance t 25 ns max 8 1 See Figure 3. t3 CS t1 CLK t6 t2 SDI t4 t5 SDO t7 t8 09316-003 Figure 3. SPI Port Timing Diagram Rev. 0 | Page 6 of 36

ADRF6850 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 4. Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Supply Voltage Pins (VCC1, VCC2, VCC3, −0.3 V to +4.0 V VCC4, VCC5, VCC6, VCC7, VCC8, VCC9) other conditions above those indicated in the operational Analog Input/Output −0.3 V to +4.0 V section of this specification is not implied. Exposure to absolute Digital Input/Output −0.3 V to +4.0 V maximum rating conditions for extended periods may affect RFI, RFI, RFCM 0 V to 3.0 V device reliability. θ (Exposed Paddle Soldered Down) 26°C/W ESD CAUTION JA Maximum Junction Temperature 125°C Storage Temperature Range −65°C to +150°C Rev. 0 | Page 7 of 36

ADRF6850 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DNIFDNMCFDNFIDN9CCDNDNDNDNDNNAIG GRGRGRGVGGGGGV 65432109876543 55555554444444 VCC1 1 PIN 1 42VCC8 IBB 2 INDICATOR 41GND IBB 3 40LDET QBB 4 39MUXOUT QBB 5 38VTUNE GND 6 ADRF6850 37GND VOCM 7 36VCC7 GND 8 TOP VIEW 35CCOMP3 RSET 9 (Not to Scale) 34CCOMP2 LF310 33CCOMP1 CP11 32GND LF212 31VCC6 VCC213 30CLK/SCL VCC314 29SDI/SDA 5161718191021222324252627282 45NNDDDOODNNSO CCVCCVIFERIFERNGNGNGLTSETLTSETNGOMOLOMOLCDS N1 . O CATO ELNSONWE CIMTP EEXDPAONSCEED P PAATDH .TO GROUND PLANE VIA 09316-004 Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1, 13, 14, 15, 16, VCC1 to VCC9 Positive Power Supplies. Apply a 3.3 V power supply to all VCCx pins. Decouple each pin with a power 31, 36, 42, 49 supply decoupling capacitor. 6, 8, 19, 20, 21, GND Analog Ground. Connect to a low impedance ground plane. 24, 32, 37, 41, 44, 45, 46, 47, 48, 50, 52, 54, 56 2, 3, 4, 5 IBB, IBB, QBB, Differential In-Phase and Quadrature Baseband Outputs. These low impedance outputs can drive QBB 2.5 V p-p into 100 Ω differential loads. 7 VOCM Baseband Common-Mode Voltage Input. When ac coupling the baseband output pins, ground VOCM. There is an option to apply an external voltage, which may be relevant when dc coupling the baseband output pins. Note that Register CR29, Bit 6 must be set accordingly. 33 CCOMP1 Internal Compensation Node. This pin must be decoupled to ground with a 100 nF capacitor. 34 CCOMP2 Internal Compensation Node. This pin must be decoupled to ground with a 100 nF capacitor. 35 CCOMP3 Internal Compensation Node. This pin must be decoupled to ground with a 100 nF capacitor. 38 VTUNE Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output voltage. 9 RSET Charge Pump Current Set. Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relationship between I and R is CP SET 23.5 I = CPmax R SET where R = 4.7 kΩ and I = 5 mA. SET CP max 11 CP Charge Pump Output. When enabled, this provides ±I to the external loop filter, which in turn, CP drives the internal VCO. 27 CS Chip Select. CMOS input. When CS is high, the data stored in the shift registers is loaded into one of the 31 registers. In I2C mode, when CS is high, the slave address of the device is 0x78, and when CS is low, the slave address is 0x58. 29 SDI/SDA Serial Data Input for SPI Port, Serial Data Input/Output for I2C Port. In SPI mode. This input is a high impedance CMOS data input, and data is loaded in an 8-bit word. In I2C mode, this pin is a bidirectional port. 30 CLK/SCL Serial Clock Input for SPI/I2C Port. This serial clock is used to clock in the serial data to the registers. This input is a high impedance CMOS input. 28 SDO Serial Data Output for SPI Port. Register states can be read back on the SDO data output line in an 8-bit word. 17 REFIN Reference Input. AC couple this high impedance CMOS input. 18 REFIN Reference Input Bar. Ground this pin. Rev. 0 | Page 8 of 36

ADRF6850 Pin No. Mnemonic Description 51, 55 RFI, RFI RF Inputs. 50 Ω internally biased RF inputs. For single-ended operation, RFI must be ac-coupled to the source, and RFI must be ac-coupled to the ground plane. 53 RFCM RF Input Common Mode. Connect to RFI when driving the input in single-ended mode. When driving the input differentially using a balun, connect this pin to the common terminal of the output coil of the balun. Decouple RFCM to the ground plane. 25, 26 LOMON, Differential Monitor Outputs. These pins provide a replica of the internal local oscillator frequency LOMON (1× LO) at four different power levels: −6 dBm, −12 dBm, −18 dBm, and −24 dBm, approximately. These open-collector outputs must be terminated with external resistors to VCCx. These outputs can be disabled through serial port programming and should be connected to VCCx if not used. 10, 12 LF3/LF2 Extra Loop Filter Pins for Fastlock. Use these pins to reduce lock time. 40 LDET Lock Detect. This pin provides an active high output when the PLL frequency is locked. The lock detect timing is controlled by Register CR14 (Bit 7) and Register CR23 (Bit 3). 39 MUXOUT Muxout. This output is a test output for diagnostic use only. Allow this pin to remain open circuit. 22, 23 TESTLO, TESTLO Differential Test Inputs. For internal use only. These pins should be grounded. 43 VGAIN VGA Gain Input. Drive this pin by a voltage in the range from 0 V to 1.5 V. This voltage controls the gain of the VGA. A 0 V input sets the VGA gain to 0 dB, whereas a 1.5 V input sets the VGA gain to +60 dB if the VGA Gain Mode Polarity Bit CR30, Bit 2, is set to 0. If the VGA gain mode polarity bit is set to 1, a 0 V input sets the VGA gain to +60 dB, whereas a 1.5 V input sets the VGA gain to 0 dB. EP Exposed Paddle. Connect the exposed pad to the ground plane via a low impedance path. Rev. 0 | Page 9 of 36

ADRF6850 TYPICAL PERFORMANCE CHARACTERISTICS A nominal condition is defined as 25°C, 3.30 V, and worst-case frequency. A worst-case condition is defined as having the worst-case temperature, supply voltage, and frequency. 20 50 RF = 100MHz NOMINAL RF = 300MHz 45 WORST-CASE 10 RF = 550MHz 40 RF = 800MHz 0 RF = 1000MHz 35 %) P1dB (dBm) ––2100 URRENCE ( 2350 I –30 CC 20 O 15 –40 10 ––6500 09316-011 05 09316-008 0 10 20 30 40 50 60 8.6 9.0 9.4 9.8 10.2 10.6 11.0 11.4 11.8 12.2 12.6 13.0 13.4 CHANNEL GAIN (dB) INPUT P1dBAT CHANNEL GAIN OF 0dB (dBm) Figure 5. Input 1dB Compression Point (IP1dB) vs. Channel Gain, and RF Figure 8. Input 1dB Compression Point (IP1dB) Distribution with Channel Input Frequency, Nominal Conditions, Narrow-Band Mode Gain = 0 dB at Nominal and Worst-Case Conditions 20 60 3.30V, 25°C NOMINAL 3.15V,–40°C 55 WORST-CASE 10 3.45V,–40°C 50 3.15V, 85°C 0 45 3.45V, 85°C %) 40 1dB (dBm) ––2100 RRENCE ( 3350 P U 25 I –30 CC O 20 –40 15 10 ––6500 09316-012 05 09316-009 0 10 20 30 40 50 60 50.4 50.0 49.6 49.2 48.8 48.4 48.0 47.6 47.2 46.8 CHANNEL GAIN (dB) – – – – – – – – – – INPUT P1dBAT CHANNEL GAIN OF 60dB (dBm) Figure 6. Input 1dB Compression Point (IP1dB) vs. Channel Gain, Supply, and Figure 9. Input 1dB Compression Point (IP1dB) Distribution with Channel Temperature, RF Input Frequency = 100 MHz, Narrow-Band Mode Gain = 60 dB at Nominal and Worst-Case Conditions 20 20 3.30V, +25°C RF = 100MHz 3.15V, –40°C RF = 300MHz 10 3.45V, –40°C 10 RF = 550MHz 3.15V, +85°C RF = 800MHz 3.45V, +85°C RF = 1000MHz 0 0 IP1dB (dB) –––321000 IP1dB (dBm) –––321000 –40 –40 –50 –50 –600 10 20CHANNEL3 0GAIN (dB4)0 50 60 09316-034 –60–10 0 10 C2H0ANNEL3 0GAIN (4d0B) 50 60 70 09316-033 Figure 7. Input 1dB Compression Point (IP1dB) vs. Channel Gain, Supply, and Figure 10. Input 1dB Compression Point (IP1dB) vs. Channel Gain, and RF Temperature, RF Input Frequency = 1000 MHz, Narrow-Band Mode Input Frequency, V = 1.2 V, Nominal Conditions, Narrow-Band Mode OCM Rev. 0 | Page 10 of 36

ADRF6850 20 30 RF = 100MHz RF = 100MHz RF = 300MHz 10 RF = 550MHz 20 RF = 300MHz RF = 800MHz RF = 550MHz RF = 1000MHz 0 10 RF = 800MHz m) RF = 1000MHz m) –10 dB 0 IP1dB (dB ––3200 INPUT IP3 ( ––2100 –40 –30 ––6500–10 0 10 C2H0ANNEL3 0GAIN (4d0B) 50 60 70 09316-057 ––54000 10 20 CHAN3N0EL GA4IN0 (dB) 50 60 7009316-016 Figure 11. Input 1dB Compression Point (IP1dB) vs. Channel Gain, and RF Figure 14. Input IP3 vs. Channel Gain, and RF Input Frequency, Input Frequency, V = 1.6 V, Nominal Conditions, Narrow-Band Mode Worst-Case Conditions OCM 20 70 IQ = 20MHz NOMINAL IQ = 50MHz WORST-CASE 10 60 IQ = 100MHz IQ = 200MHz 0 IQ = 250MHz 50 %) m) –10 E ( B C 40 d N B ( –20 RE IP1d –30 CCUR 30 O 20 –40 10 ––65000 10 20 30 40 50 6009316-010 019.6 20.0 20.4IIP230 A.8T C21H.A2NN21E.L6 G2A2I.N0 =2 02d.4B (2d2B.8m)23.2 23.6 24.009316-035 CHANNEL GAIN (dB) Figure 12. Input 1dB Compression Point (IP1dB) vs. Channel Gain, and IQ Figure 15. Input IP3 Distribution with Channel Gain = 0 dB at Nominal and Output Frequency, LO = 1000 MHz, Nominal Conditions, Wideband Mode Worst-Case Conditions 30 35 RF = 100MHz NOMINAL WORST-CASE 20 RF = 300MHz 30 RF = 550MHz 10 RF = 800MHz m) RF = 1000MHz %) 25 dB 0 E ( INPUT IP3 ( ––2100 OCCURRENC 1250 10 –30 5 ––54000 10 20 CHAN3N0EL GA4IN0 (dB) 50 60 7009316-015 –040.4–40.0–39.I6IP–33A9.T2 C–3H8A.8N–N3E8L.4 G–A38IN.0 =– 3670.d6B– (3d7B.2m–)36.8–36.4–36.0 09316-036 Figure 13. Input IP3 vs. Channel Gain, and RF Input Frequency, Figure 16. Input IP3 Distribution with Channel Gain = 60 dB at Nominal and Nominal Conditions Worst-Case Conditions Rev. 0 | Page 11 of 36

ADRF6850 30 70 20 60 50 10 40 m) 0 m) B B 30 d d P3 ( –10 P2 ( 20 T I T I U U NP –20 NP 10 I I 0 –30 IQ FREQUENCIES = 16MHz AND 19MHz –10 IQ FREQUENCIES = 46MHz AND 49MHz ––5400–10 IIIQQQ FFF0RRREEEQQQUUUEEE1NNN0CCCIIIEEESSSC 2H===0 A912N694M66NMMHEHHzL3 zz 0AG AANANNDINDD 9 (9124dM940B99HMM)zHHzz50 60 70 09316-037 ––2300–10 DDIOR0WECNT-C IOIP1N20VERTCE2HD0A NIIPN2EL3 0GAIN (4d0B) 50 60 7009316-014 Figure 17. Input IP3 vs. Channel Gain, and IQ Output Frequency, Figure 20. Input IP2 vs. Channel Gain, Wideband Mode, Wideband Mode, Nominal Conditions Worst-Case Conditions 30 60 RF = 100MHz RF = 300MHz 20 50 RF = 550MHz RF = 800MHz 10 RF = 1000MHz Bm) 0 E (dB) 40 d R INPUT IP3 ( ––2100 NOISE FIGU 2300 –30 IQ FREQUENCIES = 16MHz AND 19MHz IQ FREQUENCIES = 46MHz AND 49MHz 10 ––5400–10 IIIQQQ FFF0RRREEEQQQUUUEEE1NNN0CCCIIIEEESSSC 2H===0 A912N694M66NMMHEHHzL3 zz 0AG AANANNDINDD 9 (9124dM940B99HMM)zHHzz50 60 70 09316-038 00 10 20 CHAN3N0EL GA4IN0 (dB) 50 60 7009316-023 Figure 18. Input IP3 vs. Channel Gain, and IQ Output Frequency, Figure 21. Noise Figure vs. Channel Gain, and RF Input Frequency, Wideband Mode, Worst-Case Conditions Narrow-Band Mode, Nominal Conditions 70 60 RF = 100MHz RF = 300MHz 60 50 RF = 550MHz 50 RF = 800MHz RF = 1000MHz Bm) 40 E (dB) 40 P2 (d 30 GUR 30 UT I 20 E FI P S N OI I 10 N 20 0 10 ––2100 DDIORWECNT-C IOIPN2VERTED IIP2 09316-013 0 09316-024 –10 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 CHANNEL GAIN (dB) CHANNEL GAIN (dB) Figure 19. Input IP2 vs. Channel Gain, Wideband Mode, Nominal Conditions Figure 22. Noise Figure vs. Channel Gain, and RF Input Frequency, Narrow-Band Mode, Worst-Case Conditions Rev. 0 | Page 12 of 36

ADRF6850 60 70 RF = 100MHz RF = 300MHz 60 50 RF = 550MHz RF = 800MHz 50 RF = 1000MHz B) 40 B) E (d N (d 40 E FIGUR 30 NEL GAI 30 NOIS 20 CHAN 20 10 10 0 –100 09316-007 0 10 20 CHAN3N0EL GA4IN0 (dB) 50 60 70 09316-045 0 0.2 0.4 0.6 VGA0IN.8 (V) 1.0 1.2 1.4 Figure 23. Noise Figure Distribution vs. Channel Gain, Narrow-Band Mode, Figure 26. Channel Gain vs. V and RF Input Frequency, GAIN Nominal Conditions Nominal Conditions 60 60 NOMINAL WORST-CASE 50 50 dB) 40 %) 40 FIGURE ( 30 RENCE ( 30 NOISE 20 OCCUR 20 10 10 00 10 20 CHAN30NEL GA4IN0 (dB) 50 60 70 09316-046 0 59.6 59.8 60.0 60.2 60.4 60.6 60.8 61.0 61.2 61.4 61.6 861. 62.0 62.209316-006 CHANNEL GAIN RANGE (dB) Figure 24. Noise Figure Distribution vs. Channel Gain, Narrow-Band Mode, Figure 27. Channel Gain Range Distribution at Nominal and Worst-Case Conditions Worst-Case Conditions 60 1.0 RF = 100MHz 3.30V, 25°C 3.15V, 85°C RF = 300MHz 3.15V,–40°C 3.45V, 85°C 50 RF = 550MHz 0.5 3.45V,–40°C RF = 800MHz RF = 1000MHz URE (dB) 40 AIN (dB) 0 FIG 30 L G –0.5 OISE ANNE N 20 H –1.0 C 10 –1.5 0 09316-025 –2.0 09316-021 0 10 20 30 40 50 60 70 100 200 300 400 500 600 700 800 900 1000 CHANNEL GAIN (dB) RF INPUT FREQUENCY (MHz) Figure 25. Noise Figure vs. Channel Gain, and RF Input Frequency, Figure 28. Minimum Channel Gain vs. RF Input Frequency, Wideband Mode, Nominal Conditions Supply, and Temperature Rev. 0 | Page 13 of 36

ADRF6850 30 3 25 NWOOMRISNTA-LCASE OR (dB) 2 RRRFFF === 135005000MMMHHHzzz R R RF = 800MHz E %) 20 CE 1 RF = 1000MHz E ( AN C M OCCURREN 1150 N CONFOR –10 AI G L E 5 N –2 0 09316-019 CHAN –3 09316-005 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 – – – – – – – – – – – VGAIN (V) MINIMUM CHANNEL GAIN (dB) Figure 29. Minimum Channel Gain Distribution at Nominal and Figure 32. Channel Gain Conformance Error vs. V and RF Input Frequency, GAIN Worst-Case Conditions Nominal Conditions 63.0 0 3.30V, 25°C 3.15V, 85°C VGAIN = 0V 62.5 33..1455VV,,––4400°°CC 3.45V, 85°C –5 VVVGGGAAAIIINNN === 011...505VVV B) d N ( –10 AI 62.0 B) EL G SS (d –15 N O N 61.5 L M CHA TURN –20 MU 61.0 RE XI –25 A M 60.5 –30 60.0100 200 300RF 4IN00PUT 5F0R0EQU6E0N0CY (7M00Hz) 800 900 100009316-018 –35100 200 300RF4 I0N0PUT5 F0R0EQU6E00NCY 7(M00Hz)800 900 1000 09316-039 Figure 30. Maximum Channel Gain vs. RF Input Frequency, Figure 33. Input Return Loss vs. RF Input Frequency and Channel Gain, Supply, and Temperature Nominal Conditions 25 0 INTEGER BOUNDARY SPUR AT 9.6kHz OFFSET NOMINAL –10 INTEGER BOUNDARY SPUR AT 19.2kHz OFFSET WORST-CASE INTEGER BOUNDARY SPUR AT 38.4kHz OFFSET c) 20 dB –20 S ( R –30 CE (%) 15 Y SPU –40 N R RE DA –50 R N CU 10 OU –60 C B O ER –70 G E 5 T –80 N I 059.6 59.8 60.0 60.2 60.4 60.6 60.8 61.0 61.2 61.4 61.6 61.8 62.0 62.209316-017 –1–0900100 200 300 4L0O0 FR5E0Q0UEN6C0Y0 (MH7z0)0 800 900 1000 09316-044 MAXIMUM CHANNEL GAIN (dB) Figure 31. Maximum Channel Gain Distribution at Nominal and Figure 34. Integer Boundary Spurs vs. LO Frequency, Channel Gain, Worst-Case Conditions Supply, and Temperature Rev. 0 | Page 14 of 36

ADRF6850 0 TABLE OF DISTRIBUTION DATA: OFFSET FREQUENCY (Hz): 10 100 1k 10k 100k 1M 10M TYPICAL RANGE (dBc/Hz): –75/–85–78/–89 –84/–95–97/–100–110/–113 –136/–138 –149/–153 WORST-CASE RANGE (dBc/Hz):–72/–82–74/–89 –89/–96–97/–100–110/–112 –136/–138 –149/–152 –20 –60 c) –70 B d –40 R ( –80 U EFERENCE SP ––8600 VVGGAAIINN ≤= 11..05VV OISE (dBc/Hz)––1–1091000 R N E –120 S –100 A PH–130 –120 –140 100 200 300 4L0O0 FR5E0Q0UEN6C0Y0 (MH7z0)0 800 900 1000 09316-049 –150 –16010 100 O1FkFSET FR1E0QkUENCY1 (0H0zk) 1M 10M 09316-051 Figure 35. Reference Spurs at 13.5 MHz from Carrier vs. LO Frequency, Figure 38. Phase Noise Performance Including Distribution Table at LO Channel Gain, Supply, and Temperature Frequency = 1000 MHz at Nominal and Worst-Case Conditions 0 0.4 3.30V; +25°C 3.15V; +85°C 3.45V; +85°C –20 3.15V; –40°C 3.45V; –40°C 0.3 s) Bc) –40 gree PUR (d –60 VGAIN = 1.5V ER (De 0.2 PFD S –80 VGAIN ≤ 1.0V RMS JITT 0.1 –100 –120 0 100 200 300 4L0O0 FR5E0Q0UEN6C0Y0 (MH7z0)0 800 900 1000 09316-048 100 200 300 4L0O0 FR5E0Q0UEN6C0Y0 (MH7z0)0 800 900 1000 09316-041 Figure 36. PFD Spurs at 27 MHz from Carrier vs. LO Frequency, Channel Gain, Figure 39. Integrated Phase Noise vs. LO Frequency, Supply, and Supply, and Temperature Temperature TABLE OF DISTRIBUTION DATA: 30 OFFSET FREQUENCY (Hz): 10 100 1k 10k 100k 1M 10M NOMINAL TYPICAL RANGE (dBc/Hz): –91/–100–99/–111–107/–115–118/–121–129/–132–150/–154–151/–153 WORST-CASE WORST-CASE RANGE (dBc/Hz):–90/–105–95/–108–105/–116–118/–121–128/–131–151/–154–151/–153 –60 25 –70 –80 %) 20 E ( Bc/Hz)–1–0900 RRENC 15 d U E (–110 CC NOIS–120 O 10 E S–130 A 5 H P–140 –150 0 –160 0.19 0.21 0.2R3MS J0I.T2T5ER (0D.2e7grees0).29 0.31 0.33 09316-040 –170 10 100 O1FkFSET FR1E0QkUENCY1 (0H0zk) 1M 10M 09316-052 Figure 37. Phase Noise Performance Including Distribution Table at LO Figure 40. Integrated Phase Noise Distribution with LO Frequency = Frequency = 100 MHz at Nominal and Worst-Case Conditions 1000 MHz at Nominal and Worst-Case Conditions Rev. 0 | Page 15 of 36

ADRF6850 1G 30 BEST CASE 100M TYPICAL WORST CASE 10M 25 Hz) 1M ACQUISITION REQUENCY (101001kkk TO 1kHz RRENCE (%) 1250 OR F 100 START OF ACQUISITION CCU ERR 10 ON CR0 WRITE O 10 1 LDET CR23[3] = 1 5 0.00.11–5L0DET0 50 C1R0203[31]5 0= 020T0IM2E5 0(µs3)00 350 400 450 500 550 09316-055 0 0 0.005 0.0100.015 0.0200.025 0.0300.035 0.040 0.045 0.050 0.0550.060 0.065 0.0700.075 0.0800.085 0.0900.0950.10009316-031 ABSOLUTE IQAMPLITUDE BALANCE (dB) Figure 41. PLL Frequency Settling Time with Typical, Best-Case, and Worst- Figure 44. Absolute IQ Amplitude Balance, Narrow-Band Mode, Case Frequency Hop with Lock Detect Shown, Nominal Conditions Nominal Conditions 20 20 I OUTPUT 18 Q OUTPUT 18 16 16 14 14 %) %) NCE ( 12 NCE ( 12 CCURRE 108 CCURRE 108 O O 6 6 4 4 2 2 0–18 –14 –10 –6 O–U2TPUT2 DC 6OFFS10ET (m14V) 18 22 26 30 09316-050 0 –0.45 –0.35 –0.I2Q5 P–H0A.1S5E– B0A.0L5AN0C.0E5 (D0e.g15rees0).25 0.35 0.45 09316-042 Figure 42. Output DC Offset Distribution for I and Q Outputs, Figure 45. IQ Phase Balance, Narrow-Band Mode, Nominal Conditions Nominal Conditions 5 0 –10 0 m) –20 B) –5 dB –30 WER (d –10 OUGH ( –40 VGAIN = 1.5V O R P H –50 OUTPUT ––2105 LO FEEDT ––7600 × WB MODE 1 –80 ––32050.1 NNNNBBBB MMMMOOOODDDDEEEE= === 1I5 3Q430037 MMOMMHHUHHzzTzzPUT FR1E0QUENCY (MHz1)00 1000 09316-047 –1–0900100 200 300 4L00O FVR5GE0AQ0INU E= N600CV0,Y 0 (.M5V7H,0 z10)V 800 900 1000 09316-026 Figure 43. Normalized IQ Output Bandwidth, Narrow-Band, and Figure 46. 1× LO Feedthrough vs. LO Frequency, V , Supply, and GAIN Wideband Modes, Nominal Conditions Temperature (Narrow-Band Mode) Rev. 0 | Page 16 of 36

ADRF6850 0 0 –20 –20 m) m) dB dB VGAIN = 1.5V H ( –40 H ( –40 G G U U RO RO VGAIN = 1.3V H –60 H –60 T T D D E E E E O F –80 O F –80 L L 2× 1× VGAIN = 0V, 0.5V, 1V –100 –100 –120 09316-029 –120 09316-022 100 200 300 400 500 600 700 800 900 1000 330 430 530 630 730 830 930 LO FREQUENCY (MHz) LO FREQUENCY (MHz) Figure 47. 2× LO Feedthrough vs. LO Frequency, V , Supply, and Figure 50. 1× LO Feedthrough vs. LO Frequency, V , Supply, and GAIN GAIN Temperature (Narrow-Band Mode) Temperature, Fourth-Order Filter at 300 MHz Applied, Wideband Mode 0 0 –20 –20 m) c) DTHROUGH (dB ––6400 Q LEAKAGE (dB ––6400 VGAIN = 1.5V EE O I O F –80 FT –80 L R 4× 1× –100 –100 –120 09316-030 –120 VGAIN = 0V, 0.5V, 1V 09316-028 100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000 LO FREQUENCY (MHz) RF FREQUENCY (MHz) Figure 48. 4× LO Feedthrough vs. LO Frequency, V , Supply, and Figure 51. 1× RF Feedthrough vs. RF Input Frequency, V , Supply, and GAIN GAIN Temperature (Narrow-Band Mode) Temperature, Narrow-Band Mode 25 0 NOMINAL WORST-CASE –20 20 c) VGAIN = 1.0V B %) E (d –40 VGAIN = 1.5V CCURRENCE ( 1105 O IQ LEAKAG ––8600 VGAIN = 1.3V O T F R –100 × 5 1 0 09316-020 ––114200 VGAIN = 0V, 0.5V, 1V 09316-027 6.56.05.55.04.54.03.53.02.52.01.51.00.50.09.59.08.58.07.57.06.56.0 330 430 530 630 730 830 930 4444444444444433333333 –––––––––––––––––––––– RF FREQUENCY (MHz) 1× LO FEEDTHOUGH (dBm) Figure 49. 1× LO Feedthrough Distribution at Nominal and Worst-Case Figure 52. 1× RF Feedthrough vs. RF Input Frequency, V , Supply, and GAIN Conditions with LO Frequency > 300 MHz, Temperature, Fourth-Order Filter at 300 MHz Applied, Wideband Mode Narrow-Band Mode Rev. 0 | Page 17 of 36

ADRF6850 THEORY OF OPERATION OThVeE ARDVRIFE6W85 0 device can be separated into the following basic RFREPFOIIMNN DOU×B2LER R-D5I-VBIIDTER ÷2 TPOFD 09316-061 Figure 54. Reference Input Path building blocks: The PFD frequency equation is • PLL synthesizer and VCO • Quadrature demodulator f = f × [(1 + D)/(R × (1 + T))] (1) PFD REFIN • Variable gain amplifier (VGA) where: • I2C/SPI interface f is the reference input frequency. REFIN D is the doubler bit. Each of these building blocks is described in detail in the R is the programmed divide ratio of the binary 5-bit sections that follow. programmable reference divider (1 to 32). PLL SYNTHESIZER AND VCO T is the ÷2 bit (0 or 1). Overview RF Fractional-N Divider The phase-locked loop (PLL) consists of a fractional-N frequency The RF fractional-N divider allows a division ratio in the PLL synthesizer with a 25-bit fixed modulus, allowing a frequency feedback path that can range from 23 to 4095. The relationship resolution of less than 1 Hz over the entire frequency range. It between the fractional-N divider and the LO frequency is also has an integrated voltage controlled oscillator (VCO) with described in the following section. a fundamental output frequency ranging from 2000 MHz to INT and FRAC Relationship 4000 MHz. An RF divider, controlled by Register CR28, Bits[2:0], extends the lower limit of the frequency range to less than The integer (INT) and fractional (FRAC) values make it 400 MHz. This 400 MHz to 4000 MHz frequency output is possible to generate output frequencies that are spaced by then applied to a divide-by-4 quadrature circuit to provide a fractions of the phase frequency detector (PFD) frequency. local oscillator (LO) ranging from 100 MHz to 1000 MHz to the See the Programming the Correct LO Frequency section for quadrature demodulator. more information. Reference Input Section The LO frequency equation is The reference input stage is shown in Figure 53. SW1 and SW2 LO = f × (INT + (FRAC/225))/2 × 2RFDIV (2) PFD are normally closed switches. SW3 is normally open. When where: power-down is initiated, SW3 is closed, and SW1 and SW2 are LO is the local oscillator frequency. open. This ensures that there is no loading of the REFIN pin at f is the PFD frequency. PFD power-down. INT is the integer component of the required division factor POWER-DOWN and is controlled by the CR6 and CR7 registers. CONTROL FRAC is the fractional component of the required division NC 100kΩ factor and is controlled by the CR0 to CR3 registers. SW2 TO RFDIV is the setting in Register CR28, Bits[2:0], and controls REFIN NC BUFFER R-DIVIDER the setting of a divider at the output of the PLL. SW1 NC SW3 09316-060 FROM VCO RF N-DIVIDER N = INT + FRAC/225 PTFOD Figure 53. Reference Input Stage OUTPUT N-COUNTER DIVIDERS Reference Input Path THIRD-ORDER FRACTIONAL INTERPOLATOR The on-chip reference frequency doubler allows the input frequency of the reference signal to be doubled. This is useful INT FRAC fforerq iunecnrecays hiniggh tehre i mPFpDro vceosm thpea nriosiosne pfreerqfouremnacny.c Me oafk tihneg s tyhstee mPF. D REG VALUE 09316-062 Figure 55. RF Fractional-N Divider Doubling the PFD frequency usually improves the in-band phase noise performance by 3 dBc/Hz. Phase Frequency Detector (PFD) and Charge Pump The 5-bit R-divider allows the input reference frequency The PFD takes inputs from the R-divider and the N-counter and (REF ) to be divided down to produce the reference clock produces an output proportional to the phase and frequency differ- IN to the PFD. Division ratios from 1 to 32 are allowed. ence between them (see Figure 56 for a simplified schematic). The PFD includes a fixed delay element that sets the width of An additional divide-by-2 (÷2) function in the reference input the antibacklash pulse, ensuring that there is no dead zone in path allows for a greater division range. the PFD transfer function. Rev. 0 | Page 18 of 36

ADRF6850 UP The correct VCO and band are chosen automatically by the HI D1 Q1 U1 VCO and band select circuitry when Register CR0 is updated. +IN CLR1 This is referred to as autocalibration. The autocalibration time is set by Register CR25. DELAY U3 CHPUAMRGPE CP Autocalibration Time = (BSCDIV × 24)/PFD (3) where: BSCDIV = Register CR25, Bits[7:0]. PFD = PFD frequency. CLR2 DOWN HI D2 Q2 For a PFD frequency of 27 MHz, BSCDIV = 112 to set an –IN U2 09316-063 autocalibration time of 100 µs. Figure 56. PFD Simplified Schematic Note that BSCDIV must be recalculated if the PFD frequency is changed. The recommended autocalibration setting is 100 µs. Lock Detect (LDET) During this time, the VCO V is disconnected from the output TUNE LDET (Pin 40) signals when the PLL has achieved lock to an of the loop filter and is connected to an internal reference voltage. error frequency of less than 1 kHz. On a write to Register CR0, A typical frequency acquisition is shown in Figure 58. a new PLL acquisition cycle starts, and the LDET signal goes 1G low. When lock has been achieved, this signal returns high. 100M Voltage Controlled Oscillator (VCO) 10M The VCO core in the ADRF6850 consists of three separate VCOs, Hz) each with 16 overlapping bands. This configuration of 48 bands OR ( 1M ATIUMTEO (CµAs)L R allows the VCO frequency range to extend from 2000 MHz to ER100k 4000 MHz. The three VCOs are divided externally by a program- CY ACQUISITION TO 1kHz N 10k E mable divider (RFDIV controlled by Register CR28, Bits[2:0]). U This divider provides divisions of 1, 2, 4, and 8 to ensure that the REQ 1k F frequency range is extended from 250 MHz (2000 MHz/8) to 100 4000 MHz (4000 MHz/1). A lower limit of only 400 MHz is 10 required. A divide-by-4 quadrature circuit provides the full LO far eswqueeenp coyf rVange fvrso. mLO 1 f0r0e qMueHnzc yt od e1m00o0n sMtrHatzin. gF itghue rteh r5e7e sVhCowOss 10 50 100 150 200TIM2E5 0(µs)300 350 400 450 500 09316-054 TUNE Figure 58. PLL Acquisition overlapping and the multiple overlapping bands within each VCO at the LO frequency range of 100 MHz to 1000 MHz. Note After autocalibration, normal PLL action resumes, and the that this plot includes the RFDIV divider being incorporated to correct frequency is acquired to within a frequency error of provide further divisions of the fundamental VCO frequency; 1 kHz in 260 μs typically. For a maximum cumulative step of thus, each VCO is used on four different occasions throughout the 100 kHz, autocalibration can be turned off by Register CR24, full LO frequency range. The choice of three 16-band VCOs and Bit 0. This enables cumulative PLL acquisitions of 100 kHz or an RFDIV divider allows the wide frequency range to be covered less to occur without the autocalibration procedure, which without large VCO sensitivity (KVCO) or resultant poor phase improves acquisition times significantly (see Figure 59). noise and spurious performance. 1G 2.5 100M 2.3 10M Hz) 2.1 R ( 1M O R 1.9 ER100k V) Y ACQUISITION TO 1kHz V (TUNE 11..57 REQUENC 101kk F 100 1.3 10 1.1 1 0.9100 200 300 4L0O0 FR5E0Q0UEN6C0Y0 (MH7z0)0 800 900 1000 09316-056 Figure 509. PL2L0 Acq4u0isitio6n0 Wit8h0oTuIMt1 AE0 u0(µtso)c1a20libra14ti0on f1o6r0 a 110800 kH2z0 0Ste09316-053p Figure 57. V vs. LO Frequency TUNE Rev. 0 | Page 19 of 36

ADRF6850 The VCO displays a variation of K as V varies within Example to Program the Correct LO Frequency VCO TUNE the band and from band to band. Figure 60 shows how the Assume that the PFD frequency is 27 MHz and the required LO K varies across the fundamental LO frequency range from VCO frequency is 330 MHz. 500 MHz to 1000 MHz. Note that K is shown at the LO VCO Step 1. From Table 6, 2RFDIV = 2. frequency rather than at the VCO frequency. Figure 60 is useful when calculating the loop filter bandwidth and individual loop Step 2. N = (2 × 2 × 330E+6)/(27E+6) = 48.88888889. filter components using ADISimPLL™. ADISimPLL is an The N-divider value is composed of integer (INT) and Analog Devices, Inc., simulator that aids in PLL design, fractional (FRAC) components according to the following particularly with respect to the loop filter. It reports parameters equation: such as phase noise, integrated phase noise, acquisition time, N = INT + FRAC/225 (5) and so forth for a particular set of input conditions. ADISimPLL can be downloaded from www.analog.com. INT = 48 and FRAC = 29,826,162. 25 The appropriate registers must then be programmed according to the register map, ensuring that Register CR0 is the last register to be programmed because this write starts a new PLL acquisi- 20 V) tion cycle. Hz/ M QUADRATURE DEMODULATOR Y ( 15 T TIVI The quadrature demodulator can be powered up by Register CR29, ENSI 10 Bit 0. It has an output filter with narrow-band and wideband O S modes, which are selected by Register CR29, Bit 3. Wideband C V mode has a 1 dB filter cutoff of 250 MHz. Narrow-band mode 5 has selectable cutoff filters of 30 MHz through 50 MHz by pro- gramming Register CR29, Bits[5:4]. A dc bias voltage of 1.4 V 0500 550 600 650LO 7F0R0EQU75E0NCY8 0(M0Hz)850 900 950 1000 09316-059 T(Vo OsCeMle)c cta ann b eex steert ninalt edrcn ablilays bvyo lsteatgtein, gse Rt eRgeigsitsetre rC CRR2299, ,B Biti t6 6 = = 1 0. , and drive Pin 7, VOCM, with the requisite external bias voltage. Figure 60. K vs. LO Frequency VCO VARIABLE GAIN AMPLIFIER (VGA) Programming the Correct LO Frequency There are two steps to programming the correct LO frequency. The variable gain amplifier (VGA) at the input to the demodulator The user can calculate the N-divider ratio that is required in the can be driven either single-ended or differentially. PLL and the RFDIV value based on the required LO frequency To drive single-ended, connect Pin 53, RFCM, to Pin 51, RFI, and PFD frequency. and decouple both pins to ground with a 10 nF capacitor. Drive 1. Calculate the value of RFDIV, which is used to program the input signal through Pin 55, RFI. Register CR28, Bits[2:0], from the following lookup table To drive differentially, use a balun with the RFI and RFI pins (Table 6). See also Table 24. driven by the balanced outputs of the balun, and connect the RFCM pin to the common balun output terminal. Decouple Table 6. RFDIV Lookup Table RFCM to ground. LO Frequency (MHz) RFDIV = Register CR28[2:0] 500 to 1000 000 = divide-by-1 The VGA gain range is approximately 60 dB and is achieved by 250 to 500 001 = divide-by-2 varying the VGAIN voltage from 0 V to 1.5 V. The Typical 125 to 250 010 = divide-by-4 Performance Characteristics section has more information on 100 to 125 011 = divide-by-8 the VGA gain performance. A 0 V input on VGAIN sets the VGA gain to 0 dB, whereas a 1.5 V input sets the VGA gain to 2. Using the following equation, calculate the value of the +60 dB if the VGA Gain Mode Polarity Bit CR30, Bit 2, is set N-divider: to 0. If the VGA gain mode polarity bit is set to 1, a 0 V input N = (2RFDIV × 2 × LO)/(f ) (4) voltage on VGAIN sets the VGA gain to +60 dB, whereas a 1.5 V PFD input sets the VGA gain to 0 dB. where: N is the N-divider value. The VGA can be powered down by setting Register CR30, Bit 0, RFDIV is the setting in Register CR28, Bits[2:0]. to 0 and can be powered up by setting this same bit to 1. LO is the local oscillator frequency. I2C INTERFACE f is the PFD frequency. PFD The ADRF6850 supports a 2-wire, I2C-compatible serial bus This equation is a different representation of Equation 2. that drives multiple peripherals. The part powers up in I2C mode but is not locked in this mode. To remain in I2C mode, it is Rev. 0 | Page 20 of 36

ADRF6850 recommended that the user tie the CS line to either 3.3 V or monitors the SDA and SCL lines waiting for the start GND, thus disabling SPI mode. condition and the correct transmitted address. 5. The R/W bit determines the direction of the data. Logic 0 The serial data (SDA) and serial clock (SCL) inputs carry infor- on the LSB of the first byte indicates that the master writes mation between any devices that are connected to the bus. Each information to the peripheral. Logic 1 on the LSB of the slave device is recognized by a unique address. The ADRF6850 first byte indicates that the master reads information from has two possible 7-bit slave addresses for both read and write the peripheral. operations, 0x78 and 0x58. The MSB of the 7-bit slave address is set to 1. Bit 5 of the slave address is set by the CS pin (Pin 27). The ADRF6850 acts as a standard slave device on the bus. The Bits[4:0] of the slave address are set to 11000. The slave address data on the SDA pin is eight bits long, supporting the 7-bit consists of the seven MSBs of an 8-bit word. The LSB of the word addresses plus the R/W bit. The ADRF6850 has 34 subaddresses sets either a read or a write operation (see Figure 61). Logic 1 cor- to enable the user-accessible internal registers; therefore, it responds to a read operation, whereas Logic 0 corresponds to a interprets the first byte as the device address and the second write operation. byte as the starting subaddress. To control the device on the bus, the following protocol must Auto-increment mode is supported, which allows data to be followed: be read from or written to the starting subaddress, and each 1. The master initiates a data transfer by establishing a start subsequent address, without manually addressing the subsequent condition, defined by a high-to-low transition on SDA subaddress. A data transfer is always terminated by a stop con- while SCL remains high. This indicates that an address/ dition. The user can also access any unique subaddress register data stream follows. on a one-by-one basis without updating all registers. 2. All peripherals respond to the start condition and shift the Stop and start conditions can be detected at any stage of the data next eight bits (the 7-bit address and the R/W bit). The bits transfer. If these conditions are asserted out of sequence with are transferred from MSB to LSB. normal read and write operations, they cause an immediate jump 3. The peripheral that recognizes the transmitted address to the idle condition. If an invalid subaddress is issued by the user, responds by pulling the data line low during the ninth the ADRF6850 does not issue an acknowledge and returns to the clock pulse. This is known as an acknowledge bit. idle condition. In a no acknowledge condition, the SDA line is 4. All other devices then withdraw from the bus and maintain not pulled low on the ninth pulse. See Figure 62 and Figure 63 an idle condition. During the idle condition, the device for sample write and read data transfers, Figure 64 for the timing protocol, and Figure 2 for a more detailed timing diagram. R/W SLAVEADDRESS[6:0] CTRL MSB1 = 1 SPEIANT5 2B7Y 0 0 0 0 0 01 ==X WRDR 09316-064 Figure 61. Slave Address Configuration S SLAVEADDR, LSB = 0 (WR) A(S) SUBADDR A(S) DATA A(S) DATA A(S) P SA (=S )S =TAARCTK NBOITWLEDGE BY SLAVE P = STOP BIT 09316-067 Figure 62. I2C Write Data Transfer S SLAVEADDR, LSB = 0 (WR) A(S) SUBADDR A(S) S SLAVEADDR, LSB = 1 (RD) A(S) DATA A(M) DATA A(M) P SA (=S )S =TAARCTK NBOITWLEDGE BY SLAVE AP (=M S) T=OAPC KBNITOWLEDGE BY MASTERA(M) = NOACKNOWLEDGE BY MASTER 09316-065 Figure 63. I2C Read Data Transfer START BIT STOPBIT SLAVEADDRESS SUBADDRESS DATA SDA A6 A5 A7 A0 D7 D0 SCL S ADSDLRAV[4E:0] WR ACK SUBADDR[6:1] ACK DATA[6:1] ACK P 09316-066 Figure 64. I2C Data Transfer Timing Rev. 0 | Page 21 of 36

ADRF6850 SPI INTERFACE of the part. The SDI line is used to write to the registers. The SDO pin is a dedicated output for the read mode. The part The ADRF6850 supports the SPI protocol; however, the part operates in slave mode and requires an externally applied serial powers up in I2C mode. To select and lock the SPI mode, three clock to the CLK pin. The serial interface is designed to allow pulses must be sent to the CS pin, as shown in Figure 65. When the part to be interfaced to systems that provide a serial clock the SPI protocol is locked in, it cannot be unlocked while the that is synchronized to the serial data. device remains powered up. To reset the serial interface, the part must be powered down and powered up again. Figure 66 shows an example of a write operation to the ADRF6850. Data is clocked into the registers on the rising edge of CLK using Serial Interface Selection a 24-bit write command. The first eight bits represent the write The CS pin controls selection of the I2C or SPI interface. command (0xD4), the next eight bits are the register address, and Figure 65 shows the selection process that is required to lock the final eight bits are the data to be written to the specific register. in the SPI mode. To communicate with the part using the SPI Figure 67 shows an example of a read operation. In this example, protocol, three pulses must be sent to the CS pin. On the third a shortened 16-bit write command is first used to select the appro- rising edge, the part selects and locks the SPI protocol. Consistent priate register for a read operation, the first eight bits representing with most SPI standards, the CS pin must be held low during all the write command (0xD4) and the final eight bits representing SPI communication to the part and held high at all other times. the specific register. Then the CS line is pulsed low for a second SPI Serial Interface Functionality time to retrieve data from the selected register using a 16-bit The SPI serial interface of the ADRF6850 consists of the CS, read command, the first eight bits representing the read command SDI (SDI/SDA), CLK (CLK/SCL), and SDO pins. CS is used to (0xD5) and the final eight bits representing the contents of the select the device when more than one device is connected to the register being read. Figure 3 shows the timing for both SPI read and SPI write operations. serial clock and data lines. CLK is used to clock data in and out A B C CS (STARTING HIGH) SPILOCKED ON SPIFRAMING THIRDRISINGEDGE EDGE CS (STARTING A B C LOW) THIRSDPIRLISOINCGKEEDD OGNE SEPDIGFERAMING 09316-077 Figure 65. Selecting the SPI Protocol Rev. 0 | Page 22 of 36

ADRF6850 • • • CS CLK • • • • • • SDI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 START WRITE REGISTER COMMAND [0xD4] ADDRESS CS • • • (CONTINUED) CLK • • • (CONTINUED) SDI • • • D7 D6 D5 D4 D3 D2 D1 D0 (CONTINUED) BDYATTAE STOP 09316-068 Figure 66. SPI Byte Write Example • • • CS CLK • • • • • • SDI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 START WRITE REGISTER COMMAND [0xD4] ADDRESS CS CLK SDI D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X SDO X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 START COMMRAENADD [0xD5] BDYATTAE STOP 09316-069 Figure 67. SPI Byte Read Example Rev. 0 | Page 23 of 36

ADRF6850 PROGRAM MODES 5-bit divider is enabled by programming Register CR5, Bit 4; and the division ratio is programmed through Register CR10, The ADRF6850 has 34 8-bit registers to allow program control Bits[4:0]. The R ÷2 divider is programmed through Register CR10, of a number of functions. Only 31 of these registers are writeable. Bit 6. Note that these registers are double buffered. Either an SPI or an I2C interface can be used to program the register set. For details about the interfaces and timing, see Charge Pump Current Figure 61 to Figure 67. The registers are documented in Table 8 Register CR9, Bits[7:4], set the charge pump current setting. to Table 27. With an R value of 4.7 kΩ, the maximum charge pump SET Several settings in the ADRF6850 are double buffered. These current is 5 mA. The following equation applies: settings include the FRAC value, the INT value, the RFDIV I = 23.5/R (6) CP max SET value, the 5-bit R-divider value, the reference doubler, the R ÷2 The charge pump current has 16 settings from 325 μA to 5 mA. divider, and the charge pump current setting. This means that two events must occur before the part uses a new value for any Power-Down/Power-Up Control Bits of the double buffered settings. First, the new value is latched The four programmable power-up and power-down control bits into the device by writing to the appropriate register. Next, a new are as follows: write must be performed on Register CR0. When Register CR0 is  Register CR12, Bit 2. Master power control bit for the PLL, written, a new PLL acquisition occurs. including the VCO. This bit is normally set to a default For example, updating the fractional value involves a write to value of 0 to power up the PLL. Register CR3, Register CR2, Register CR1, and Register CR0.  Register CR27, Bit 2. Controls the LO monitor outputs, Register CR3 should be written to first, followed by Register CR2 LOMON and LOMON. The default is 0 when the monitor and Register CR1 and, finally, Register CR0. The new acquisition outputs are powered down. Setting this bit to 1 powers up begins after the write to Register CR0. Double buffering ensures the monitor outputs to one of −6 dBm, −12 dBm, −18 dBm, that the bits written to do not take effect until after the write to or −24 dBm, as controlled by Register CR27, Bits[1:0]. Register CR0.  Register CR29, Bit 0. Controls the quadrature demodulator 12-Bit Integer Value power. The default is 0, which powers down the demodulator. Register CR7 and Register CR6 program the integer value (INT) Write a 1 to this bit to power up the demodulator. of the feedback division factor (N); see Equation 5 for details.  Register CR30, Bit 0. This bit controls the VGA power and The INT value is a 12-bit number whose MSBs are programmed must be set to a 1 to power up the VGA. through Register CR7, Bits[3:0]. The LSBs are programmed Lock Detect (LDET) through Register CR6, Bits[7:0]. The LO frequency setting is Lock detect is enabled by setting Register CR23, Bit 4, to 1. described by Equation 2. An alternative to this equation is pro- Register CR23, Bit 3, in conjunction with Register CR14, Bit 7, vided by Equation 4, which details how to set the N-divider sets the number of up/down pulses generated by the PFD before value. Note that these registers are double buffered. lock detect is declared by the LDET pin returning high. The 25-Bit Fractional Value options are 2048 pulses, 3072 pulses, and 4096 pulses. Register CR3 to Register CR0 program the fractional value (FRAC) The default setting is 3072 pulses, which is selected by program- of the feedback division factor (N); see Equation 5 for details. The ming Register CR23, Bit 3, to 0, and Register CR14, Bit 7, to 0. A FRAC value is a 25-bit number whose MSB is programmed more aggressive setting of 2048 is selected when Register CR23, through Register CR3, Bit 0. The LSB is programmed through Bit 3, is set to 1 and Register CR14, Bit 7, is set to 0. This improves Register CR0, Bit 0. The LO frequency setting is described by the lock detect time by 50 μs (for a PFD frequency of 27 MHz). Equation 2. Again, an alternative to this equation is described Note, however, that it does not affect the acquisition time to an by Equation 4, which details how to set the N-divider value. error frequency of 1 kHz. A setting of 4096 pulses is selected Note that these registers are double buffered. when Register CR14, Bit 7, is set to 1. For best operation, set RFDIV Value Register CR23, Bit 2 to 0. This bit sets up the PFD up/down The RFDIV value is dependent on the value of the LO frequency. pulses to a coarse or low precision setting. The RFDIV value can be selected from the list in Table 6. Apply Baseband VOCM Reference the selected RFDIV value to Equation 4, together with the LO Register CR29, Bit 6, selects whether the common-mode reference frequency and PFD frequency values, to calculate the correct N- for the baseband outputs is internal or external. When the base- divider value. band outputs are ac-coupled, then the internal reference must Reference Input Path be selected by setting Register CR29, Bit 6, to 1, and by The reference input path consists of a reference doubler, a 5-bit grounding Pin 7, VOCM. frequency divider, and a divide-by-2 function (see Figure 54). When the baseband outputs are dc-coupled, it is likely that an The doubler is programmed through Register CR10, Bit 5. The external bias is needed unless the internal dc bias provided is Rev. 0 | Page 24 of 36

ADRF6850 within a suitable range to match the specification of the follow- Table 7. Baseband Filter Settings on device. This is accomplished by setting Register CR29, Bit 6, CR29[5:4] Filter Cutoff Frequency (MHz) to 0, and driving Pin 7, VOCM, with the requisite external bias 00 50 voltage. 01 43 Narrow-Band and Wideband Filter Mode 10 37 11 30 By default, the second-order low-pass filter in the output buffers VGA Gain Mode Polarity of the baseband output signal paths is selected, and the baseband outputs are in narrow-band mode. By setting Register CR29, The polarity of the VGA gain is set by programming Bit 2 of Bits[5:4], this filter can be set to a cutoff frequency of 50 MHz, Register CR30. By setting Register CR30, Bit 2, to 0, a positive 43 MHz, 37 MHz, or 30 MHz. By setting Register CR29, Bit 3, to 1, gain slope is selected where V = 0 V sets the VGA gain to be 0 GAIN this filter is bypassed and wideband mode is selected. dB, and V = 1.5 V sets the VGA gain to be 60 dB. By setting GAIN Register CR30, Bit 2, to 1, a negative gain slope is selected. Rev. 0 | Page 25 of 36

ADRF6850 REGISTER MAP REGISTER MAP SUMMARY Table 8. Register Map Summary Register Address (Hex) Register Name Type Description 0x00 CR0 Read/write Fractional Word 4 0x01 CR1 Read/write Fractional Word 3 0x02 CR2 Read/write Fractional Word 2 0x03 CR3 Read/write Fractional Word 1 0x04 CR4 Read/write Reserved 0x05 CR5 Read/write Reference 5-bit, R-divider enable 0x06 CR6 Read/write Integer Word 2 0x07 CR7 Read/write Integer Word 1 0x08 CR8 Read/write Reserved 0x09 CR9 Read/write Charge pump current setting 0x0A CR10 Read/write Reference frequency control 0x0B CR11 Read/write Reserved 0x0C CR12 Read/write PLL power-up 0x0D CR13 Read/write Reserved 0x0E CR14 Read/write Lock Detector Control 2 0x0F CR15 Read/write Reserved 0x10 CR16 Read/write Reserved 0x11 CR17 Read/write Reserved 0x12 CR18 Read/write Reserved 0x13 CR19 Read/write Reserved 0x14 CR20 Read/write Reserved 0x15 CR21 Read/write Reserved 0x16 CR22 Read/write Reserved 0x17 CR23 Read/write Lock Detector Control 1 0x18 CR24 Read/write Autocalibration 0x19 CR25 Read/write Autocalibration timer 0x1A CR26 Read/write Reserved 0x1B CR27 Read/write LO monitor output 0x1C CR28 Read/write LO selection 0x1D CR29 Read/write Demodulator power and filter selection 0x1E CR30 Read/write VGA 0x1F CR31 Read only Reserved 0x20 CR32 Read only Reserved 0x21 CR33 Read only Revision code Rev. 0 | Page 26 of 36

ADRF6850 REGISTER BIT DESCRIPTIONS Table 13. Register CR5 (Address 0x05), Reference 5-Bit, R-Divider Enable Table 9. Register CR0 (Address 0x00), Fractional Word 4 Bit Description Bit Description 7 Reserved 7 Fractional Word F71 6 Reserved 6 Fractional Word F61 5 Reserved 5 Fractional Word F51 4 5-bit R-divider enable1 4 Fractional Word F41 0 = disable 5-bit R-divider (default) 3 Fractional Word F31 1 = enable 5-bit R-divider 2 Fractional Word F21 3 Reserved 1 Fractional Word F11 2 Reserved 0 Fractional Word F0 (LSB)1 1 Reserved 1 Double buffered. Load on the write to Register CR0. 0 Reserved Table 10. Register CR1 (Address 0x01), Fractional Word 3 1 Double buffered. Load on the write to Register CR0. Bit Description Table 14. Register CR6 (Address 0x06), Integer Word 2 7 Fractional Word F151 Bit Description 6 Fractional Word F141 7 Integer Word N71 5 Fractional Word F131 6 Integer Word N61 4 Fractional Word F121 5 Integer Word N51 3 Fractional Word F111 4 Integer Word N41 2 Fractional Word F101 3 Integer Word N31 1 Fractional Word F91 2 Integer Word N21 0 Fractional Word F81 1 Integer Word N11 1 Double buffered. Load on the write to Register CR0. 0 Integer Word N01 Table 11. Register CR2 (Address 0x02), Fractional Word 2 1 Double buffered. Load on the write to Register CR0. Bit Description Table 15. Register CR7 (Address 0x07), Integer Word 1 7 Fractional Word F231 Bit Description 6 Fractional Word F221 [7:4] MUXOUT control 5 Fractional Word F211 0000 = tristate 4 Fractional Word F201 0001 = logic high 3 Fractional Word F191 0010 = logic low 2 Fractional Word F181 1101 = RCLK/2 1 Fractional Word F171 1110 = NCLK/2 0 Fractional Word F161 3 Integer Word N111 1 Double buffered. Load on the write to Register CR0. 2 Integer Word N101 1 Integer Word N91 Table 12. Register CR3 (Address 0x03), Fractional Word 1 0 Integer Word N81 Bit Description 1 Double buffered. Load on the write to Register CR0. 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 Fractional Word F24 (MSB)1 1 Double buffered. Load on the write to Register CR0. Rev. 0 | Page 27 of 36

ADRF6850 Table 16. Register CR9 (Address 0x09), Charge Pump Table 18. Register CR12 (Address 0x0C), PLL Power-Up Current Setting Bit Description Bit Description 7 Reserved [7:4] Charge pump current1 6 Reserved 0000 = 0.31 mA (default) 5 Reserved 0001 = 0.63 mA 4 Reserved 0010 = 0.94 mA 3 Reserved 0011 = 1.25 mA 2 PLL power-down 0100 = 1.57 mA 0 = power up PLL (default) 0101 = 1.88 mA 1 = power down PLL 0110 = 2.19 mA 1 Reserved 0111 = 2.50 mA 0 Reserved 1000 = 2.81 mA Table 19. Register CR14 (Address 0x0E), Lock Detector 1001 = 3.13 mA Control 2 1010 = 3.44 mA Bit Description 1011 = 3.75 mA 1100 = 4.06 mA 7 Lock Detector Up/Down Count 2 1101 = 4.38 mA 0 = 2048/3072 up/down pulses 1110 = 4.69 mA 1 = 4096 up/down pulses 1111 = 5.00 mA 6 Reserved 3 Reserved 5 Reserved 2 Reserved 4 Reserved 1 Reserved 3 Reserved 0 Reserved 2 Reserved 1 Reserved 1 Double buffered. Load on the write to Register CR0. 0 Reserved Table 17. Register CR10 (Address 0x0A), Reference Table 20. Register CR23 (Address 0x17), Lock Detector Frequency Control Control 1 Bit Description Bit Description 7 Reserved1 6 R divide-by-2 divider enable1 7 Reserved 6 Reserved 0 = bypass R divide-by-2 divider 5 Reserved 1 = enable R divide-by-2 divider 5 R-doubler enable1 4 Lock detector enable 0 = lock detector disabled (default) 0 = disable doubler (default) 1 = lock detector enabled 1 = enable doubler [4:0] 5-bit R-divider setting1 3 Lock detector up/down count With Register CR14[7] = 0: 00000 = divide by 32 (default) 0 = 3072 up/down pulses 00001 = divide by 1 1 = 2048 up/down pulses 00010 = divide by 2 2 Lock detector precision … 0 = low, coarse (16 ns) 11110 = divide by 30 1 = high, fine (6 ns) 11111 = divide by 31 1 Reserved 1 Double buffered. Load on the write to Register CR0. 0 Reserved Rev. 0 | Page 28 of 36

ADRF6850 Table 21. Register CR24 (Address 0x18), Autocalibration Table 25. Register CR29 (Address 0x1D), Demodulator Bit Description Power and Filter Selection 7 Reserved Bit Description 6 Reserved 7 Reserved 5 Reserved 6 Internal baseband (V ) select OCM 4 Reserved 0 = select external baseband (V ) reference OCM 3 Reserved 1 = select internal baseband (V ) reference OCM 2 Reserved [5:4] Narrow-band filter cut off 1 Reserved 00 = 50 MHz 0 Disable autocalibration 01 = 43 MHz 0 = enable autocalibration (default) 10 = 37 MHz 1 = disable autocalibration 11 = 30 MHz 3 Baseband wideband/narrow-band modes Table 22. Register CR25 (Address 0x19), Autocalibration 0 = narrow-band mode Timer 1 = wideband mode Bit Description 2 Reserved; set to 0 [7:0] Autocalibration timer 1 Reserved; set to 0 0 Power-up demodulator Table 23. Register CR27 (Address 0x1B), LO Monitor Output 0 = power down (default) Bit Description 1 = power up 7 Reserved 6 Reserved Table 26. Register CR30 (Address 0x1E), VGA 5 Reserved Bit Description 4 Reserved 7 Reserved 3 Reserved 6 Reserved 2 Power-up monitor output 5 Reserved 0 = power down (default) 4 Reserved 1 = power up 3 Reserved [1:0] Monitor output power into 50 Ω 2 VGA gain mode polarity 00 = −24 dBm (default) 0 = positive gain slope 01 = −18 dBm 1 = negative gain slope 10 = −12 dBm 1 Reserved 11 = −6 dBm 0 Power-up VGA 0 = power down Table 24. Register CR28 (Address 0x1C), LO Selection 1 = power up Bit Description 7 Reserved Table 27. Register CR33 (Address 0x21), Revision Code1 6 Reserved Bit Description 5 Reserved 7 Revision code 4 Reserved 6 Revision code 3 Reserved; set to 1 5 Revision code [2:0] RFDIV 4 Revision code 000 = divide by 1; LO = 500 MHz to 1000 MHz 3 Revision code 001 = divide by 2; LO = 250 MHz to 500 MHz 2 Revision code 010 = divide by 4; LO = 125 MHz to 250 MHz 1 Revision code 011 = divide by 8; LO = 100 MHz to 125 MHz 0 Revision code 1 Read-only register. Rev. 0 | Page 29 of 36

ADRF6850 SUGGESTED POWER-UP SEQUENCE INITIAL REGISTER WRITE SEQUENCE 16. Write the following to Register CR15: 0x00. Reserved register. After applying power to the device, adhere to the following 17. Write Register CR14: 0x00. Lock Detector Control 2. write sequence, particularly with respect to the reserved register 18. Write Register CR13: 0x08. Reserved register. settings. Note that Register CR33, Register CR32, and 19. Write the following to Register CR12: 0x18. PLL powered up. Register CR31 are read-only registers. Also note that all 20. Write the following to Register CR11: 0x00. Reserved writeable registers should be written to on power-up. Refer to register. the Register Map section for more details on all registers. 21. Write the following to Register CR10: 0x21. The reference 1. Write the following to Register CR30 = 0x00. Set VGA path doubler is enabled and the 5-bit divider and R divide- power to off and the VGA gain slope to be positive. by-2 divider are bypassed. 2. Write the following to Register CR29: 0x41. The 22. Write the following to Register CR9: 0x70. With the demodulator is powered up. The baseband narrow-band recommended loop filter component values and R = SET mode is selected and set to a cutoff frequency of 50 MHz. 4.7 kΩ, the charge pump current is set to 2.5 mA for a loop The internal baseband V reference is selected. OCM bandwidth of 50 kHz. 3. Write the following to Register CR28: 0x0X RFDIV 23. Write the following to Register CR8: 0x00. Reserved depends on the value of the LO frequency to be used and is register. set according to Table 6. Note that Register CR28, Bit 3, is 24. Write the following to Register CR7: 0x0X. Set according to set to 1. Equation 4 and Equation 5 in the Theory of Operation 4. Write the following to Register CR27: 0x00. Power the LO section. monitor in a power-down state. 25. Write the following to Register CR6: 0xXX. Set according 5. Write the following to Register CR26: 0x00. Reserved to Equation 4 and Equation 5 in the Theory of Operation register. section. 6. Write the following to Register CR25: 0x70. Set the 26. Write Register CR5: 0x00. Disable the 5-bit reference autocalibration time to 100 μs with a PFD frequency divider. setting of 27 MHz. If the PFD frequency is different, set 27. Write the following to Register CR4: 0x01. Reserved CR25 according to Equation 3. register. 7. Write the following to Register CR24: 0x38. Enable 28. Write the following to Register CR3: 0x0X. Set according to autocalibration. Equation 4 and Equation 5 in the Theory of Operation 8. Write the following to Register CR23: 0x70. Enable lock section. detector and set lock detector counter = 3072 up/down 29. Write the following to Register CR2: 0xXX. Set according pulses. to Equation 4 and Equation 5 in the Theory of Operation 9. Write the following to Register CR22: 0x00. Reserved section. register. 30. Write the following to Register CR1: 0xXX. Set according 10. Write the following to Register CR21: 0x00. Reserved to Equation 4 and Equation 5 in the Theory of Operation register. section. 11. Write the following to Register CR20: 0x00. Reserved 31. Write the following to Register CR0: 0xXX. Set according register. to Equation 4 and Equation 5 in the Theory of Operation 12. Write the following to Register CR19: 0x00. Reserved section. Register CR0 must be the last register written for register. all the double buffered bit writes to take effect. 13. Write the following to Register CR18: 0x60. Reserved 32. Monitor the LDET output or wait 260 μs to ensure that the register. PLL is locked. 14. Write the following to Register CR17: 0x00. Reserved 33. Write the following to Register CR30: 0x01. Set the VGA to register. power on. 15. Write the following to Register CR16: 0x00. Reserved register. Rev. 0 | Page 30 of 36

ADRF6850 EVALUATION BOARD GENERAL DESCRIPTION and 56 pF capacitors that are placed as close to the DUT as possible for good local decoupling. The impedance of all these The evaluation board is designed to allow the user to evaluate capacitors should be low and constant across a broad frequency the performance of the ADRF6850. It contains the following: range. Surface-mount multilayered ceramic chip (MLCC) Class II • The ADRF6850 DUT. This is an I/Q demodulator with an capacitors provide very low ESL and ESR, which assist in integrated fractional-N PLL and VCO. decoupling supply noise effectively. They also provide good • SPI and I2C interface connectors. temperature stability and good aging characteristics. Capacitance • Baseband output connectors. changes per the bias voltage that is applied. Larger case sizes have • Fourth-order low-pass loop filter circuitry. less capacitance change vs. applied bias voltage, and also lower • 13.5 MHz reference clock, and the ability to drive the ESR but higher ESL. A combination of 0402 size cases for the reference input external to the board. 56 pF capacitors and 0603 size cases for the 100 nF capacitors • Circuitry to support differential signaling to the TESTLO give a good compromise allowing the 56 pF capacitors to be inputs, including dc biasing circuitry. placed as close as possible to the supply pins on the top side of • Circuitry to monitor the LOMON outputs. the PCB with the 100 nF capacitors placed on the bottom side • SMA connectors for power supplies, the VGAIN input and of the PCB quite close to the supply pins. X5R and X7R capacitors are examples of these types of capacitors and are a single-ended RF input. recommended for decoupling. The evaluation board comes with associated software to allow SPI and I2C Interface easy programming of the ADRF6850. The SPI interface connector is a nine-way, D-type connector that HARDWARE DESCRIPTION can be connected to the printer port of a PC. Figure 68 shows For more information, refer to the circuit diagram in Figure 69. the PC cable diagram that must be used with the provided Power Supplies software. An external +3.3 V supply (DUT + 3.3 V) powers each of the There is also an option to use the I2C interface by using the I2C nine VCCx supplies on the ADRF6850 as well as the 13.5 MHz receptacle connector. This is a standard I2C connector. A supply clock reference. voltage of +3.3 V is provided by the I2C bus master. Pull-up resistors are required on the signal lines. The CS pin can be Recommended Decoupling for Supplies used to set the slave address of the ADRF6850. CS high sets the Initially, the external +3.3 V supply is decoupled by a 10 µF slave address to 0x78, and CS low sets the slave address to 0x58. capacitor and then further by a parallel combination of 100 nF 1 1 CLK 2 14 67 2 DATA 3 15 8 3 LE 4 16 4 9 5 17 5 18 PC 6 9-WAY GND 19 FEMALE 7 D-TYPE 20 8 21 9 10 22 23 11 24 12 25 13 25-WAY MALE PRINDTT-OTE YRPP CPEORT 09316-070 Figure 68. SPI PC Cable Diagram Rev. 0 | Page 31 of 36

ADRF6850 Baseband Outputs and VOCM LOMON Outputs The pair of I and Q baseband outputs are connected to the These pins are differential LO monitor outputs that provide a board by SMA connectors. They are ac-coupled to the output replica of the internal LO frequency at 1× LO. The single-ended connectors. VOCM, which sets the common-mode output power in a 50 Ω load can be programmed to −24 dBm, −18 dBm, voltage, is grounded and the internal baseband (V ) reference −12 dBm, or −6 dBm. These open-collector outputs must be OCM is selected by Register CR29, Bit 6. If the external baseband terminated to 3.3 V. Because both outputs must be terminated (V ) reference is selected by setting this bit to a 0, then a to 50 Ω, options are provided to terminate to 3.3 V using on- OCM voltage needs to be applied through J6 and R20 needs to be board 50 Ω resistors or by series inductors (or a ferrite bead), in removed. which case the 50 Ω termination is provided by the measuring Loop Filter instrument. CCOMPx Pins A fourth-order loop filter is provided at the output of the charge pump and is required to adequately filter noise from the Σ-Δ The CCOMPx pins are internal compensation nodes that must modulator used in the N-divider. With the charge pump current be decoupled to ground with a 100 nF capacitor. set to a midscale value of 2.5 mA and using the on-chip VCO, MUXOUT the loop bandwidth is approximately 50 kHz, and the phase MUXOUT is a test output that allows different internal nodes margin is 55°. C0G capacitors are recommended for use in the to be monitored. It is a CMOS output stage that requires no loop filter because they have low dielectric absorption, which is termination. required for fast and accurate settling time. The use of non C0G capacitors may result in a long tail being introduced into the Lock Detect (LDET) PLL settling time transient. Lock detect is a CMOS output that indicates the state of the Reference Input PLL. A high level indicates a locked condition, and a low level indicates a loss of lock condition. The reference input can be supplied by a 13.5 MHz Jauch clock generator or by an external clock through the use of Connector J7. RF Inputs (RFI, RFCM, and RFI) The frequency range of the reference input is from 10 MHz to RFI and RFI are 50 Ω internally biased RF inputs. For single- 300 MHz with the PFD frequency limited to a maximum of ended operation as demonstrated on the evaluation board, RFI 30 MHz. Double the 13.5 MHz clock to 27 MHz by using the on- must be ac-coupled to the source and RFI must be ac-coupled chip reference frequency doubler to optimize phase noise to the ground plane. RFCM is the RF input common-mode pin. performance. It should be connected to RFI when driving the input in single- TESTLO Inputs ended mode. When driving the input differentially using a These pins are differential test inputs that allow a variety of debug balun, connect this pin to the common terminal of the output options. On this board, the capability is provided to drive these coil of the balun. pins with an external 4× LO signal that is then applied to an VGAIN Anaren balun to provide a differential input signal. The VGAIN pin sets the gain of the VGA. The V voltage GAIN When driving the TESTLO pins, the PLL can be bypassed, and range is from 0 V to 1.5 V. This allows the gain of the VGA to the demodulator can be driven directly by this external LO vary from 0 dB to +60 dB. signal. The frequency of the LO signal needs to be 4 times the operating frequency. These inputs also require a dc bias. A dc bias of 3.3 V is the default option used on the board. Rev. 0 | Page 32 of 36

ADRF6850 PCB SCHEMATIC 850-61390 Figure 69. Applications Circuit Rev. 0 | Page 33 of 36

ADRF6850 PCB ARTWORK Component Placement 09316-071 09316-072 Figure 70. Evaluation Board, Top Side Component Figure 73. Evaluation Board, Bottom Side Component Placement 09316-073 09316-076 Figure 71. Evaluation Board, Top Side—Layer 1 Figure 74. Evaluation Board Power—Layer 3 09316-075 09316-074 Figure 72. Evaluation Board, Ground—Layer 2 Figure 75. Evaluation Board, Bottom Side—Layer 4 Rev. 0 | Page 34 of 36

ADRF6850 BILL OF MATERIALS Table 28. Bill of Materials Qty. Reference Designator Description Manufacturer Part Number 1 DUT ADRF6850 LFCSP, 56-lead 8 mm × 8 mm Analog Devices ADRF6850BCPZ 1 Y2 VCO, 13.5 MHz Jauch 0 13.50-VX7-G-3.3-1- T1-LF 1 SPI Connector, 9-pin, D-sub plug, D-SUB9MR ITW McMurdo FEC 1071806 1 I2C Connector, I2C, SEMCONN receptacle Digikey 5-1761185-1-ND 2 C1, C34 Capacitor, 10 µF, 25 V, tantalum, TAJ-C AVX FEC 197518 10 C4, C6, C10, C12, C14, C16, C40, Capacitor, 56 pF, 50 V, ceramic, C0G, 0402 AVX FEC 1658861 C48, C53, C55 14 C5, C7, C11, C13, C15, C17, C22, Capacitor, 100 nF, 25 V, X7R, ceramic, 0603 AVX FEC 317287 C27, C47, C49 to C52, C54 1 C3 Capacitor, 1.8 nF, 50 V, C0G, ceramic, 0603 Murata FEC 1402814 1 C35 Capacitor, 68 nF, 50 V, NPO, ceramic, 1206 Kemet FEC 1535582 4 C2, C21, C38, C39 Capacitor, 1 nF, 50 V, C0G, ceramic, 0603 Murata FEC 8819920 2 C44, C46 Capacitor, 100 pF, 50 V, C0G, ceramic, 0402 Murata FEC 8819572 2 C43, C56 Capacitor, 10 nF, 50 V, X7R, ceramic, 0402 Murata FEC 1414575 1 C18 Capacitor, 10 pF, 50 V, C0G, ceramic, 0402 Murata FEC 8819564 4 C30 to C33 Capacitor, 10 μF, 6.3 V, X5R, ceramic, 0603 Phycomp FEC 1458902 12 J2 to J12, J14 SMA end launch connector Johnson/Emerson 142-0701-851 2 J20, J21 Jumper, 3-pin plus shunt Harwin FEC 148533 + FEC 150411 2 L1, L2 Inductor, 20 nH, 0402, LQW series Murata LQW15AN20N 2 L3, L4 Inductor, 10 µH, 0805, LQM series Murata LQM21FN1N100M 2 R20, R36 Resistor, 0 Ω, 1/16 W, 1%, 0402 Vishay Draloric FEC 1158241 1 R13 Resistor, 4.7 kΩ, 1/10 W, 1%, 0603 Multicomp FEC 1576293 2 R14, R39 Resistor, 1.2 kΩ, 1/10 W, 5%, 0603 Phycomp FEC 9233393 1 R1 Resistor, 220 Ω, 1/16 W, 1%, 0603 Multicomp FEC 9330801 2 R3, R4 Resistor, 200 Ω, 1/16 W, 5%, 0402 Vishay Dale FEC 1514682 2 R17, R18 Resistor, 0603, spacing (do not install) 3 R35, R44, R45 Resistor, 51 Ω, 1/16 W, 1%, 0402 Multicomp FEC 1358008 4 R48 to R51 Resistor, 330 Ω, 1/10 W, 5%, 0805 Vishay Draloric FEC 1739223 2 R60, R61 Resistor, 100 Ω, 1/10 W, 5%, 0805 Bourns Digi Key RR12P100DTR-ND 2 R46, R47 Resistor, 10 kΩ, 1/16 W, 1%, 0402 Phycomp FEC 9239359 7 CS, LDET, MUXOUT, VTUNE, SCLK, Test point, 1-pin, 0.035 inch diameter Not inserted SDA, SDO 1 BAL1 Balun, 0805, 50 Ω to 100 Ω balanced (1.3 GHz to Anaren BD1631J50100A00 3.1 GHz) Rev. 0 | Page 35 of 36

ADRF6850 OUTLINE DIMENSIONS 8.10 0.60MAX 0.30 8.00SQ 0.23 7.90 0.60 0.18 MAX PIN1 43 56 INDICATOR 42 1 PIN1 0.50 INDICATOR BSC 7.85 7.75SQ EXPOSED 5.25 PAD 7.65 5.10SQ 4.95 14 29 TOPVIEW 00..5400 28 BOTTOMVIEW 15 0.25MIN 0.30 6.50REF 1.00 12°MAX 0.80MAX 0.85 0.65TYP FORPROPERCONNECTIONOF 0.80 0.05MAX TTHHEEEPXINPCOOSNEDFIGPAUDR,ARTEIOFNERANTOD 0.02NOM FUNCTIONDESCRIPTIONS COPLANARITY SECTIONOFTHISDATASHEET. SEATING 0.20REF 0.08 PLANE COMPLIANTTOJEDECSTANDARDSMO-220-VLLD-2 081809-B Figure 76. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 mm × 8 mm Body, Very Thin Quad (CP-56-5) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADRF6850BCPZ −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Tray CP-56-5 ADRF6850BCPZ-R7 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7" Tape and Reel CP-56-5 EVAL-ADRF6850EB1Z Evaluation Board 1 Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09316-0-10/10(0) Rev. 0 | Page 36 of 36

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