100 MHz to 2400 MHz I/Q Modulator with Integrated Fractional-N PLL and VCO Data Sheet ADRF6755 FEATURES GENERAL DESCRIPTION I/Q modulator with integrated fractional-N PLL and VCO The ADRF6755 is a highly integrated quadrature modulator, Gain control span: 47 dB in 1 dB steps frequency synthesizer, and programmable attenuator. The device Output frequency range: 100 MHz to 2400 MHz covers an operating frequency range from 100 MHz to 2400 MHz Output 1 dB compression: 8 dBm at LO = 1800 MHz for use in satellite, cellular, and broadband communications. Output IP3: 20.5 dBm at LO = 1800 MHz The ADRF6755 modulator includes a high modulus, fractional-N Noise floor: −161 dBm/Hz at LO = 1800 MHz frequency synthesizer with integrated VCO, providing less than Baseband modulation bandwidth: 600 MHz (3 dB) 1 Hz frequency resolution, and a 47 dB digitally controlled output Output frequency resolution: 1 Hz attenuator with 1 dB steps. SPI and I2C-compatible serial interfaces Power supply: 5 V/380 mA Control of all the on-chip registers is through a user-selected SPI interface or I2C interface. The device operates from a single power supply ranging from 4.75 V to 5.25 V. VCC1 VCC2 VCC3 VCC4 LOMON LOMON REGOUT REG3U.3LVATOR IBB VREG1 IBB VREG2 VREG3 VREG4 47dB CCOMP1 VREG5 GAINCONTROL CCOMP2 VREG6 RANGE CCOMP3 RFOUT 0°/90° RFDIVIDER VCO VTUNE CORE TXDIS QBB QBB RSET REFERENCE REFIN DOU×B2LER DI5V-BIDITER ÷2 + PHASE REFIN –FDREETQEUCETNOCRY CHPUAMRGPE CP NC CURRENT SETTING N-COUNTER NC THIRD-ORDER LDET SDI/SDA FRACTIONAL CR9[7:4] CLK/SCL SPI/I2C INTERPOLATOR INTERFACE SDO CS FRACTIONAL MODULUS INTEGER REGISTER 225 REGISTER ADRF6755 AGND DGND 10465-001 Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADRF6755 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SPI Interface ................................................................................ 27 General Description ......................................................................... 1 Program Modes .......................................................................... 29 Revision History ............................................................................... 2 Register Map ................................................................................... 31 Specifications ..................................................................................... 3 Register Map Summary ............................................................. 31 Timing Characteristics ................................................................ 8 Register Bit Descriptions ........................................................... 32 Absolute Maximum Ratings .......................................................... 10 Suggested Power-Up Sequence ..................................................... 35 ESD Caution ................................................................................ 10 Initial Register Write Sequence ................................................ 35 Pin Configuration and Function Descriptions ........................... 11 Evaluation Board ............................................................................ 37 Typical Performance Characteristics ........................................... 13 General Description ................................................................... 37 Theory of Operation ...................................................................... 21 Hardware Description ............................................................... 37 Overview ...................................................................................... 21 PCB Artwork............................................................................... 41 PLL Synthesizer and VCO ......................................................... 21 Bill of Materials ........................................................................... 44 Quadrature Modulator .............................................................. 24 Outline Dimensions ....................................................................... 45 Attenuator .................................................................................... 25 Ordering Guide .......................................................................... 45 Voltage Regulator ....................................................................... 25 I2C Interface ................................................................................ 25 REVISION HISTORY 4/13—Rev. A to Rev. B Changes to Ordering Guide .......................................................... 45 11/12—Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Input Frequency Parameter, Table 1 .......................... 6 Changes to Bit 7 Description, Table 27 and Bit 6 Description, Table 27 ............................................................................................ 34 Changed 0x00 to 0x60 in Step 13 ................................................. 35 Updated Outline Dimensions ....................................................... 45 Changes to Ordering Guide .......................................................... 45 7/12—Revision 0: Initial Version Rev. B | Page 2 of 48

Data Sheet ADRF6755 SPECIFICATIONS V = 5 V ± 5%, operating temperature range = −40°C to +85°C, I/Q inputs = 0.9 V p-p differential sine waves in quadrature on a 500 mV dc CC bias, REFIN = 80 MHz, PFD = 40 MHz, baseband frequency = 1 MHz, LOMON off, loop bandwidth (LBW) = 100 kHz, I = 5 mA, unless CP otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit OPERATING FREQUENCY RANGE 100 2400 MHz RF OUTPUT = 100 MHz RFOUT pin Nominal Output Power V = 0.9 V p-p differential −0.2 dBm IQ Gain Flatness Any 40 MHz ±2.0 dB Output P1dB 9.0 dBm Output IP3 f1 = 3.5 MHz, f2 = 4.5 MHz, P = −6 dBm per tone 21.0 dBm BB BB OUT Output Return Loss Attenuator setting = 0 dB −12 dB LO Carrier Feedthrough1 Attenuator setting = 0 dB to 47 dB −55 dBc 2× LO Carrier Feedthrough Attenuator setting = 0 dB to 47 dB −80 dBm Sideband Suppression −70 dBc Noise Floor I/Q inputs = 0 V p-p differential, attenuator setting = 0 dB −153 dBm/Hz Baseband Harmonics −60 dBc Synthesizer Spurs Integer boundary < loop bandwidth −85 dBc >10 MHz offset from carrier −90 dBc Phase Noise 100 Hz offset −106 dBc/Hz 1 kHz offset −116 dBc/Hz 10 kHz offset −127 dBc/Hz 100 kHz offset −131 dBc/Hz 1 MHz offset −146 dBc/Hz 10 MHz offset −152 dBc/Hz Integrated Phase Noise 1 kHz to 8 MHz integration bandwidth 0.02 ° rms RF OUTPUT = 300 MHz RFOUT pin Nominal Output Power V = 0.9 V p-p differential 0.2 dBm IQ Gain Flatness Any 40 MHz ±0.5 dB Output P1dB 9.3 dBm Output IP3 f1 = 3.5 MHz, f2 = 4.5 MHz, P = −6 dBm per tone 23.0 dBm BB BB OUT Output Return Loss Attenuator setting = 0 dB −20 dB LO Carrier Feedthrough1 Attenuator setting = 0 dB to 47 dB −50 dBc 2× LO Carrier Feedthrough Attenuator setting = 0 dB to 47 dB −75 dBm Sideband Suppression −70 dBc Noise Floor I/Q inputs = 0 V p-p differential, attenuator setting = 0 dB −158 dBm/Hz Baseband Harmonics −60 dBc Synthesizer Spurs Integer boundary < loop bandwidth −85 dBc >10 MHz offset from carrier −85 dBc Phase Noise 100 Hz offset −105 dBc/Hz 1 kHz offset −113 dBc/Hz 10 kHz offset −117 dBc/Hz 100 kHz offset −122 dBc/Hz 1 MHz offset −145 dBc/Hz 10 MHz offset −150 dBc/Hz Integrated Phase Noise 1 kHz to 8 MHz integration bandwidth 0.04 ° rms Rev. B | Page 3 of 48

ADRF6755 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit RF OUTPUT = 700 MHz RFOUT pin Nominal Output Power V = 0.9 V p-p differential 0.2 dBm IQ Gain Flatness Any 40 MHz ±0.5 dB Output P1dB 9.4 dBm Output IP3 f1 = 3.5 MHz, f2 = 4.5 MHz, P = −6 dBm per tone 23.0 dBm BB BB OUT Output Return Loss Attenuator setting = 0 dB −16 dB LO Carrier Feedthrough1 Attenuator setting = 0 dB to 47 dB −48 dBc 2× LO Carrier Feedthrough Attenuator setting = 0 dB to 47 dB −70 dBm Sideband Suppression −70 dBc Noise Floor I/Q inputs = 0 V p-p differential, attenuator setting = 0 dB −158 dBm/Hz Baseband Harmonics −60 dBc Synthesizer Spurs Integer boundary < loop bandwidth −60 dBc >10 MHz offset from carrier −85 dBc Phase Noise 100 Hz offset −97 dBc/Hz 1 kHz offset −106 dBc/Hz 10 kHz offset −112 dBc/Hz 100 kHz offset −115 dBc/Hz 1 MHz offset −139 dBc/Hz 10 MHz offset −154 dBc/Hz Integrated Phase Noise 1 kHz to 8 MHz integration bandwidth 0.07 ° rms RF OUTPUT = 900 MHz RFOUT pin Nominal Output Power V = 0.9 V p-p differential 0.0 dBm IQ Gain Flatness Any 40 MHz ±0.5 dB Output P1dB 9.2 dBm Output IP3 f1 = 3.5 MHz, f2 = 4.5 MHz, P = −6 dBm per tone 22.8 dBm BB BB OUT Output Return Loss Attenuator setting = 0 dB −15 dB LO Carrier Feedthrough1 Attenuator setting = 0 dB to 47 dB −48 dBc 2× LO Carrier Feedthrough Attenuator setting = 0 dB to 47 dB −68 dBm Sideband Suppression −60 dBc Noise Floor I/Q inputs = 0 V p-p differential, attenuator setting = 0 dB −158.5 dBm/Hz Attenuator setting = 0 dB to 21 dB, carrier offset = 10 MHz −152 dBc/Hz Attenuator setting = 21 dB to 47 dB, carrier offset = 10 MHz −171 dBm/Hz Baseband Harmonics −60 dBc Synthesizer Spurs Integer boundary < loop bandwidth −60 dBc >10 MHz offset from carrier −80 dBc Phase Noise 100 Hz offset −94 dBc/Hz 1 kHz offset −104 dBc/Hz 10 kHz offset −109 dBc/Hz 100 kHz offset −114 dBc/Hz 1 MHz offset −139 dBc/Hz 10 MHz offset −154 dBc/Hz Integrated Phase Noise 1 kHz to 8 MHz integration bandwidth 0.11 ° rms RF OUTPUT = 1800 MHz RFOUT pin Nominal Output Power V = 0.9 V p-p differential −0.4 dBm IQ Gain Flatness Any 40 MHz ±0.5 dB Output P1dB 8.0 dBm Output IP3 f1 = 3.5 MHz, f2 = 4.5 MHz, P = −6 dBm per tone 20.5 dBm BB BB OUT Output Return Loss Attenuator setting = 0 dB −13 dB LO Carrier Feedthrough1 Attenuator setting = 0 dB to 47 dB −45 dBc 2× LO Carrier Feedthrough Attenuator setting = 0 dB to 47 dB −53 dBm Sideband Suppression −45 dBc Rev. B | Page 4 of 48

Data Sheet ADRF6755 Parameter Test Conditions/Comments Min Typ Max Unit Noise Floor I/Q inputs = 0 V p-p differential, attenuator setting = 0 dB −161 dBm/Hz Attenuator setting = 0 dB to 21 dB, carrier offset = 10 MHz −150 dBc/Hz Attenuator setting = 21 dB to 47 dB, carrier offset = 10 MHz −170 dBm/Hz Baseband Harmonics −58 dBc Synthesizer Spurs Integer boundary < loop bandwidth −60 dBc >10 MHz offset from carrier −75 dBc Phase Noise 100 Hz offset −89 dBc/Hz 1 kHz offset −99 dBc/Hz 10 kHz offset −103 dBc/Hz 100 kHz offset −108 dBc/Hz 1 MHz offset −133 dBc/Hz 10 MHz offset −152 dBc/Hz Integrated Phase Noise 1 kHz to 8 MHz integration bandwidth 0.17 ° rms RF OUTPUT = 1875 MHz RFOUT pin Nominal Output Power V = 0.9 V p-p differential −0.6 dBm IQ Gain Flatness Any 40 MHz ±0.5 dB Output P1dB 7.8 dBm Output IP3 f1 = 3.5 MHz, f2 = 4.5 MHz, P = −6 dBm per tone 20.2 dBm BB BB OUT Output Return Loss Attenuator setting = 0 dB −13 dB LO Carrier Feedthrough1 Attenuator setting = 0 dB to 47 dB −45 dBc 2× LO Carrier Feedthrough Attenuator setting = 0 dB to 47 dB −52 dBm Sideband Suppression −50 dBc Noise Floor I/Q inputs = 0 V p-p differential, attenuator setting = 0 dB −160 dBm/Hz Attenuator setting = 0 dB to 21 dB, carrier offset = 10 MHz −150 dBc/Hz Attenuator setting = 21 dB to 47 dB, carrier offset = 10 MHz −170 dBm/Hz Baseband Harmonics −60 dBc Synthesizer Spurs Integer boundary < loop bandwidth −60 dBc >10 MHz offset from carrier −73 dBc Phase Noise 100 Hz offset −89 dBc/Hz 1 kHz offset −97 dBc/Hz 10 kHz offset −103 dBc/Hz 100 kHz offset −108 dBc/Hz 1 MHz offset −133 dBc/Hz 10 MHz offset −152 dBc/Hz Integrated Phase Noise 1 kHz to 8 MHz integration bandwidth 0.18 ° rms RF OUTPUT = 2100 MHz RFOUT pin Nominal Output Power V = 0.9 V p-p differential −1.0 dBm IQ Gain Flatness Any 40 MHz ±0.5 dB Output P1dB 7.4 dBm Output IP3 f1 = 3.5 MHz, f2 = 4.5 MHz, P = −6 dBm per tone 19.5 dBm BB BB OUT Output Return Loss Attenuator setting = 0 dB −12 dB LO Carrier Feedthrough1 Attenuator setting = 0 dB to 47 dB −44 dBc 2× LO Carrier Feedthrough Attenuator setting = 0 dB to 47 dB −51 dBm Sideband Suppression −45 dBc Noise Floor I/Q inputs = 0 V p-p differential, attenuator setting = 0 dB −161 dBm/Hz Attenuator setting = 0 dB to 21 dB, carrier offset = 10 MHz −149 dBc/Hz Attenuator setting = 21 dB to 47 dB, carrier offset = 10 MHz −170 dBm/Hz Baseband Harmonics −60 dBc Synthesizer Spurs Integer boundary < loop bandwidth −60 dBc >10 MHz offset from carrier −67 dBc Rev. B | Page 5 of 48

ADRF6755 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit Phase Noise 100 Hz offset −88 dBc/Hz 1 kHz offset −98 dBc/Hz 10 kHz offset −101 dBc/Hz 100 kHz offset −108 dBc/Hz 1 MHz offset −134 dBc/Hz 10 MHz offset −152 dBc/Hz Integrated Phase Noise 1 kHz to 8 MHz integration bandwidth 0.25 ° rms RF OUTPUT = 2400 MHz RFOUT pin Nominal Output Power V = 0.9 V p-p differential −1.7 dBm IQ Gain Flatness Any 40 MHz ±0.5 dB Output P1dB 6.5 dBm Output IP3 f1 = 3.5 MHz, f2 = 4.5 MHz, P = −6 dBm per tone 18.5 dBm BB BB OUT Output Return Loss Attenuator setting = 0 dB −11 dB LO Carrier Feedthrough1 Attenuator setting = 0 dB to 47 dB −43 dBc 2× LO Carrier Feedthrough Attenuator setting = 0 dB to 47 dB −60 dBm Sideband Suppression −40 dBc Noise Floor I/Q inputs = 0 V p-p differential, attenuator setting = 0 dB −160.5 dBm/Hz Attenuator setting = 0 dB to 21 dB, carrier offset = 10 MHz −148 dBc/Hz Attenuator setting = 21 dB to 47 dB, carrier offset = 10 MHz −170 dBm/Hz Baseband Harmonics −55 dBc Synthesizer Spurs Integer boundary < loop bandwidth −55 dBc >10 MHz offset from carrier −64 dBc Phase Noise 100 Hz offset −85 dBc/Hz 1 kHz offset −96 dBc/Hz 10 kHz offset −100 dBc/Hz 100 kHz offset −107 dBc/Hz 1 MHz offset −132 dBc/Hz 10 MHz offset −152 dBc/Hz Integrated Phase Noise 1 kHz to 8 MHz integration bandwidth 0.25 ° rms REFERENCE CHARACTERISTICS REFIN pin Input Frequency With reference divide-by-2 enabled 10 300 MHz With reference divide-by-2 disabled 10 165 MHz With reference doubler enabled 10 80 MHz Input Sensitivity AC-coupled 0.4 VREG V p-p Input Capacitance 10 pF Input Current ±100 µA CHARGE PUMP I Sink/Source Programmable, RSET = 4.7 kΩ CP High Value 5 mA Low Value 312.5 µA Absolute Accuracy 4.0 % VCO Gain K 25 MHz/V VCO SYNTHESIZER LO = 100 MHz to 2400 MHz Frequency Resolution 1 Hz Frequency Settling Any step size, maximum frequency error = 100 Hz 0.17 ms Maximum Frequency Step for Frequency step with no autocalibration routine; 100/2RFDIV kHz No Autocalibration Register CR24, Bit 0 = 1 Phase Detector Frequency 10 40 MHz Rev. B | Page 6 of 48

Data Sheet ADRF6755 Parameter Test Conditions/Comments Min Typ Max Unit GAIN CONTROL Gain Range 47 dB Step Size 1 dB Relative Step Accuracy Fixed frequency, adjacent steps, all attenuation steps, ±0.3 dB LO > 300 MHz2 Over full frequency range, adjacent steps, all attenuation ±1.5 dB steps, LO > 300 MHz3 Absolute Step Accuracy4 47 dB attenuation step, LO > 300 MHz5 −2.0 dB Output Settling Time Any step; output power settled to ±0.2 dB 15 µs OUTPUT DISABLE TXDIS pin Off Isolation RFOUT, attenuator setting = 0 dB to 47 dB, TXDIS high −100 dBm LO, attenuator setting = 0 dB to 47 dB, TXDIS high −75 dBm 2× LO, attenuator setting = 0 dB to 47 dB, TXDIS high −50 dBm Turn-On Settling Time TXDIS high to low: output power to 90% of envelope 180 ns Frequency settling to 100 Hz 20 µs Turn-Off Settling Time TXDIS low to high (to −55 dBm) 350 ns MONITOR OUTPUT LOMON, LOMON pins Nominal Output Power −24 dBm BASEBAND INPUTS IBB, IBB, QBB, QBB pins I and Q Input Bias Level 500 mV 3 dB Bandwidth 600 MHz LOGIC INPUTS Input High Voltage, V CS, TXDIS pins 1.4 V INH Input Low Voltage, V CS, TXDIS pins 0.6 V INL Input High Voltage, V SDI/SDA, CLK/SCL pins 2.1 V INH Input Low Voltage, V SDI/SDA, CLK/SCL pins 1.1 V INL Input Current, I /I CS, TXDIS, SDI/SDA, CLK/SCL pins ±1 µA INH INL Input Capacitance, C CS, TXDIS, SDI/SDA, CLK/SCL pins 10 pF IN LOGIC OUTPUTS Output High Voltage, V SDO, LDET pins; I = 500 μA 2.8 V OH OH Output Low Voltage, V SDO, LDET pins; I = 500 μA 0.4 V OL OL SDA (SDI/SDA); I = 3 mA 0.4 V OL POWER SUPPLIES VCC1, VCC2, VCC3, VCC4, VREG1, VREG2, VREG3, VREG4, VREG5, VREG6, and REGOUT pins; REGOUT normally connected to VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6 Voltage Range VCC1, VCC2, VCC3, and VCC4 4.75 5 5.25 V REGOUT, VREG1, VREG2, VREG3, VREG4, VREG5, and 3.3 V VREG6 Supply Current VCC1, VCC2, VCC3, and VCC4 combined; REGOUT con- 380 420 mA nected to VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6 Power-Down Current CR29[0] = 0, power down modulator, 7 mA CR12[2] = 1, power down PLL, CR28[4] = 1, power down RFDIVIDER, CR27[2] = 0, power down LOMON Operating Temperature −40 +85 °C 1 LO carrier feedthrough is expressed in dBc relative to the RF output power changing as the attenuator is stepped. LO carrier feedthrough is constant as the RF output is altered due to a change in the I/Q input amplitude. 2 For relative step accuracy at LO < 300 MHz, refer to Figure 37. 3 For relative step accuracy over frequency range at LO < 300 MHz, refer to Figure 39. 4 All other attenuation steps have an absolute error of <±2.0 dB. 5 For absolute step accuracy at LO < 300 MHz, refer to Figure 40. Rev. B | Page 7 of 48

ADRF6755 Data Sheet TIMING CHARACTERISTICS I2C Interface Timing Table 2. Parameter1 Symbol Limit Unit SCL Clock Frequency f 400 kHz max SCL SCL Pulse Width High t 600 ns min HIGH SCL Pulse Width Low t 1300 ns min LOW Start Condition Hold Time t 600 ns min HD;STA Start Condition Setup Time t 600 ns min SU;STA Data Setup Time t 100 ns min SU;DAT Data Hold Time t 300 ns min HD;DAT Stop Condition Setup Time t 600 ns min SU;STO Data Valid Time t 900 ns max VD;DAT Data Valid Acknowledge Time t 900 ns max VD;ACK Bus Free Time t 1300 ns min BUF 1 See Figure 2. tSU;DAT ttVVDD;;DAACTK A(ANCDK SIGNAL ONLY) tBUF SDA tHD;STA tSU;STA tSU;STO tLOW SCL COSNTDASIRTTION 1/tfHSDC;LDAT tHIGH S COSNTDPOITPION S 10465-002 Figure 2. I2C Port Timing Diagram Rev. B | Page 8 of 48

Data Sheet ADRF6755 SPI Interface Timing Table 3. Parameter1 Symbol Limit Unit CLK Frequency f 20 MHz max CLK CLK Pulse Width High t 15 ns min 1 CLK Pulse Width Low t 15 ns min 2 Start Condition Hold Time t 5 ns min 3 Data Setup Time t 10 ns min 4 Data Hold Time t 5 ns min 5 Stop Condition Setup Time t 5 ns min 6 SDO Access Time t 15 ns min 7 CS to SDO High Impedance t 25 ns max 8 1 See Figure 3. t3 CS t1 CLK t6 t2 SDI t4 t5 SDO t7 t8 10465-003 Figure 3. SPI Port Timing Diagram Rev. B | Page 9 of 48

ADRF6755 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress VCC1, VCC2, VCC3, and VCC4 Supply Voltage −0.3 V to +6 V rating only; functional operation of the device at these or any VREG1, VREG2, VREG3, VREG4, VREG5, and −0.3 V to +4 V other conditions above those indicated in the operational VREG6 Supply Voltage section of this specification is not implied. Exposure to absolute IBB, IBB, QBB, and QBB 0 V to 2.5 V maximum rating conditions for extended periods may affect Digital I/O −0.3 V to +4 V device reliability. Analog I/O (Other Than IBB, IBB, QBB, and −0.3 V to +4 V QBB) ESD CAUTION Maximum Junction Temperature 125°C Storage Temperature Range −65°C to +150°C Rev. B | Page 10 of 48

Data Sheet ADRF6755 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS T 2CCV2CCVDNGADNGADNGADNGADNGADNGATUOFRDNGADNGASDIXTTEDLUOXUM 65432109876543 55555554444444 VCC4 1 PIN 1 42VCC3 IBB 2 INDICATOR 41VCC3 IBB 3 40AGND QBB 4 39AGND QBB 5 38VTUNE AGND 6 ADRF6755 37AGND RSET 7 36VREG6 NC 8 TOP VIEW 35CCOMP3 CP 9 (Not to Scale) 34CCOMP2 NC10 33CCOMP1 VCC111 32DGND REGOUT12 31VREG5 VREG113 30CLK/SCL VREG214 29SDI/SDA 5161718191021222324252627282 34NNDDDDDDNNSO GERVGERVIFERIFERNGANGANGANGANGANGAOMOLOMOLCDS N12..O NCTCOE NS=N NEOC TC OENXPNOECSTE.D D POA NDO TTO C GORNONUENCDT PTLOA TNHEI SV IPAIN. 10465-004 A LOW IMPEDANCE PATH. Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 11, 55, 56, 41, 42, 1 VCC1 to VCC4 Positive Power Supplies for I/Q Modulator. Apply a 5 V power supply to VCC1, which should be decoupled with power supply decoupling capacitors. Connect VCC2, VCC3, and VCC4 to the same 5 V power supply. 12 REGOUT 3.3 V Output Supply. Drives VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6. 13, 14, 15, 16, 31, VREG1 to Positive Power Supplies for PLL Synthesizer, VCO, and Serial Port. Connect these pins to REGOUT 36 VREG6 (3.3 V) and decouple them separately. 6, 19, 20, 21, 22, 23, AGND Analog Ground. Connect to a low impedance ground plane. 24, 37, 39, 40, 46, 47, 49, 50, 51, 52, 53, 54 32 DGND Digital Ground. Connect to the same low impedance ground plane as the AGND pins. 2, 3 IBB, IBB Differential In-Phase Baseband Inputs. These high impedance inputs must be dc biased to approx- imately 500 mV dc and should be driven from a low impedance source. Nominal characterized ac signal swing is 450 mV p-p on each pin. These inputs are not self-biased and must be externally biased. 4, 5 QBB, QBB Differential Quadrature Baseband Inputs. These high impedance inputs must be dc-biased to approximately 500 mV dc and should be driven from a low impedance source. Nominal charac- terized ac signal swing is 450 mV p-p on each pin. These inputs are not self-biased and must be externally biased. 33, 34, 35 CCOMP1 to Internal Compensation Nodes. These pins must be decoupled to ground with a 100 nF capacitor. CCOMP3 38 VTUNE Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output voltage. 7 RSET Charge Pump Current Set. Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relationship between I and R is as follows: CP SET 23.5 I = CPmax R SET where R = 4.7 kΩ and I = 5 mA. SET CP max 9 CP Charge Pump Output. When enabled, this output provides ±I to the external loop filter, which, in CP turn, drives the internal VCO. 27 CS Chip Select, CMOS Input. When CS is high, the data stored in the shift registers is loaded into one of 31 latches. In I2C mode, when CS is high, the slave address of the device is 0x60, and, when CS is low, the slave address is 0x40. Rev. B | Page 11 of 48

ADRF6755 Data Sheet Pin No. Mnemonic Description 29 SDI/SDA Serial Data Input for SPI Port/Serial Data Input/Output for I2C Port. In SPI mode, this pin is a high impedance CMOS data input, and data is loaded in an 8-bit word. In I2C mode, this pin is a bidirec- tional port. 30 CLK/SCL Serial Clock Input for SPI/I2C Port. This serial clock is used to clock in the serial data to the registers. This input is a high impedance CMOS input. 28 SDO Serial Data Output for SPI Port. Register states can be read back on the SDO data output line. 17 REFIN Reference Input. This high impedance CMOS input should be ac-coupled. 18 REFIN Reference Input Bar. This pin should be either grounded or ac-coupled to ground. 48 RFOUT RF Output. Single-ended, 50 Ω, internally biased RF output. This pin must be ac-coupled to the load. 45 TXDIS Output Disable. This pin can be used to disable the RF output. Connect to a high logic level to disable the output. Connect to a low logic level for normal operation. 25, 26 LOMON, Differential Monitor Outputs. These pins provide a replica of the internal local oscillator frequency LOMON (1× LO) at four different power levels: −6 dBm, −12 dBm, −18 dBm, and −24 dBm, approximately. These open-collector outputs must be terminated with external resistors to REGOUT. These outputs can be disabled through serial port programming and should be tied to REGOUT if not used. 8, 10 NC No Connect. Do not connect to these pins. 44 LDET Lock Detect. This output pin indicates the state of the PLL: a high level indicates a locked condition, whereas a low level indicates a loss of lock condition. 43 MUXOUT Mux Output. This pin is a test output for diagnostic use only. Do not connect to this pin. Exposed Paddle EP Exposed Paddle. Connect to ground plane via a low impedance path. Rev. B | Page 12 of 48

Data Sheet ADRF6755 TYPICAL PERFORMANCE CHARACTERISTICS V = 5 V ± 5%, operating temperature range = −40°C to +85°C, I/Q inputs = 0.9 V p-p differential sine waves in quadrature on a 500 mV dc CC bias, REFIN = 80 MHz, PFD = 40 MHz, baseband frequency = 1 MHz, LOMON is off, loop bandwidth (LBW) = 100 kHz, I = 5 mA, CP unless otherwise noted. A nominal condition is defined as 25°C, 5.00 V, and an LO frequency of 1800 MHz. A worst-case condition is defined as having the worst-case temperature, supply voltage, and LO frequency. 2 60 NOMINAL WORST CASE 1 50 m) 0 dB %) 40 R ( E ( E –1 C W N T PO –2 URRE 30 U C P C UT O 20 O –3 25°C; 5V 85°C; 4.75V 10 –4 85°C; 5.25V –40°C; 4.75V –40°C; 5.25V –5100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-005 0–60 –55 SIDE–B5A0ND SUP–P45RESSION–4 (0dBc) –35 –30 10465-009 Figure 5. Output Power vs. LO Frequency, Supply, and Temperature Figure 8. Sideband Suppression Distribution at Nominal and Worst-Case Conditions 25 –30 NOMINAL WORST CASE –35 20 c) –40 B d %) GH ( –45 E ( 15 OU –50 C R N H RE DT –55 R E U E C 10 F –60 C R O E RI –65 R A 5 C –70 –75 0–4.2–3.8–3.4–3.0–2.6OU–2T.P2U–T1. 8PO–1W.4E–R1 (.d0B–m0.)6–0.2 0.2 0.6 1.0 10465-006 –80100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-110 Figure 6. Output Power Distribution at Nominal and Figure 9. LO Carrier Feedthrough vs. LO Frequency, Attenuation, Worst-Case Conditions Supply, and Temperature 0 80 +25°C, 5.00V NOMINAL +85°C, 4.75V WORST CASE –10 +85°C, 5.25V 70 –40°C, 4.75V Bc) –20 –40°C, 5.25V d 60 ON ( –30 %) RESSI –40 NCE ( 50 UPP –50 RRE 40 AND S –60 OCCU 30 B –70 DE 20 SI –80 10 –90 –100100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-108 0–60–58–56–54LO–5 C2A–R50RI–E4R8 F–E46ED–T44HR–4O2U–G4H0 (–d3B8c–)36–34–32–30 10465-011 Figure 7. Sideband Suppression vs. LO Frequency, Supply, and Temperature Figure 10. LO Carrier Feedthrough Distribution at Nominal and Worst-Case Conditions and Attenuation Setting Rev. B | Page 13 of 48

ADRF6755 Data Sheet –40 45 NOMINAL WORST CASE m) –50 40 B d H ( –60 35 G OU %) 30 HR –70 E ( DT NC 25 EE –80 RE R F UR 20 RRIE –90 OCC 15 A O C–100 10 L ATTENUATION = 0dB × ATTENUATION = 12dB 2 –110 ATTENUATION = 21dB 5 ATTENUATION = 33dB ATTENUATION = 47dB –120100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-112 03.5 4.0 4.5 5.0 O5U.5TPU6T.0 P1d6B.5 (dB7m.0) 7.5 8.0 8.5 9.0 10465-014 Figure 11. 2× LO Carrier Feedthrough vs. LO Frequency, Attenuation, Figure 14. Output P1dB Compression Point Distribution at Nominal Supply, and Temperature and Worst-Case Conditions 10 1.0 m) 30 B 5 0.5 R (d m) 28 E B W d 26 UT POWER (dBm) –1–050 1CPdOOBIMNPTRESSION 0––10..05 WER – OUTPUT PO NTERCEPT POINT ( 12228024 OUTP –15 –1.5 UT PO T IP3 I 16 P U UT TP 14 –20 –2.0 AL O OU 12 E D –250.1 DIFFERENTIAL INPU1T VOLTAGE (V p-p) 10–2.5 I 10465-013 10100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-117 Figure 12. Output P1dB Compression Point at Worst-Case LO Frequency Figure 15. Output IP3 vs. LO Frequency at Nominal Conditions vs. Supply and Temperature 10.5 50 NOMINAL WORST CASE 10.0 45 9.5 40 Bm) 9.0 %) 35 dB (d 8.5 NCE ( 30 UT P1 8.0 URRE 25 P C 20 T C U 7.5 O O 15 7.0 10 6.5 5 6.0100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-115 015 16 17 OUT1P8UT IP3 1(d9Bm) 20 21 22 10465-016 Figure 13. Output P1dB Compression Point vs. LO Frequency at Figure 16. Output IP3 Distribution at Nominal and Worst-Case Nominal Conditions Conditions Rev. B | Page 14 of 48

Data Sheet ADRF6755 –60 –145 –147 –70 ATTENUATION=21dB –149 ATTENUATION=0dB Bm) –80 Hz)–151 (d m/ TION –90 R (dB–153 OLA OO–155 F IS–100 E FL–157 F S O O–110 NOI–159 L –161 –120 –163 ATTENUATION=47dB –130100 300 500 700 9L0O0F1R10E0Q1U3E0N0C1Y50(0MH17z0)01900210023002500 10465-118 –165–25 –20 –15OUTP–U1T0 POWE–R5(dBm) 0 5 10 10465-022 Figure 17. LO Off Isolation vs. LO Frequency, Attenuation, Supply, Figure 20. Noise Floor at 0 dB Attenuation vs. Output Power and Temperature at Nominal Conditions –30 100 ATTENUATION –40 ATTENUATION = 0dB 90 = 21dB (dBc/Hz) m) –50 80 B N (d –60 %) 70 ATTENUATION LATIO –70 NCE ( 60 = 0dB (dBc/Hz) FF ISO ––9800 CURRE 4500 LO O–100 OC 30 A= T2T1EdBN U(dABTmIO/HNz) 2 x –110 ATTENUATION = 47dB 20 A= T4T7EdBN U(dABTmIO/HNz) –120 10 ATTENUATION = 21dB –130100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-119 NO–01IS8E0 F–L1O7O6R–A1T7 210M–1H6z8 OF–1F6S4ET– F16R0EQ–U1E56NCY–1 (5d2Bm–/1H4z8)A–N1D44 (dB–1c4/H0z) 10465-167 Figure 18. 2 × LO Off Isolation vs. LO Frequency, Attenuation, Supply, Figure 21. Noise Floor at 10 MHz Offset Frequency Distribution at and Temperature Worst-Case Conditions and Different Attenuation Settings –40 1.0 UPPER THIRD –50 HARMONIC (fLO + 3 ×fBB) 0.5 B) (d 0 WER (dBc) ––7600 HARMUPOPNEICR (SfLEOC +O N2 D×fBB) PUT POWER––10..05 PO –80 UT–1.5 UT D O–2.0 P –90 E T Z OU ALI–2.5 –100 M HARLMOOWNEICR ( SfLEOC –O 2N ×DfBB) NOR–3.0 –110 LOWER THIRD –3.5 HARMONIC (fLO – 3 ×fBB) –120100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-120 –4.01 IAND Q BAS1E0BAND INPUT FREQ1U00ENCY (MHz) 1000 10465-023 Figure 19. Second-Order and Third-Order Harmonic Distortion vs. Figure 22. Normalized I and Q Input Bandwidth LO Frequency, Supply, and Temperature Rev. B | Page 15 of 48

ADRF6755 Data Sheet –10 0 LOWER SIDEBAND –12 –10 3 × LO ATTENUATION = 0dB HARMONIC –14 –20 –16 Bm) –30 4 × LO HA5R ×M LOONIC S22 (dB)––2108 ATTENUATION = 21dB AND 47dB UTPUT (d ––5400 HA2R ×M LOONIC HARMONIC O F –22 R –60 –24 –70 –26 –80 –28100 300 500 700OU9T00PU1T1 0F0RE13Q0U0E1N5C00Y 1(M70H0z1)900210023002500 10465-123 –900 1 2 3 FRE4QUEN5CY(M6Hz) 7 8 9 10 10465-027 Figure 23. Output Return Loss at Different Attenuation Settings vs. Output Figure 26. RF Output Spectral Plot over a Wide Span Frequency, Supply, and Temperature 0 –60 LO FREQUENCY = 2400MHz LO FREQUENCY = 1200MHz –10 –70 LO FREQUENCY = 580MHz LO FREQUENCY = 290MHz LOWER –80 LO FREQUENCY = 100MHz –20 SIDEBAND Hz) –90 m) –30 CARRIER c/ PUT (dB –40 FEEDTHRSOUSUPIGDPEHRBEASNSDED OISE (dB––110100 OUT –50 HATRHMIRODNIC E N–120 RF –60 SECOND PHAS–130 HARMONIC –70 –140 –80 –150 –910870 1871 1872 1873F1R8E7Q4UE18N7C5Y (1M87H6z)1877 1878 1879 1880 10465-025 –160100 1k OF1F0SkET FREQ10U0EkNCY (Hz1)M 10M 10465-160 Figure 24. RF Output Spectral Plot over a 10 MHz Span Figure 27. Phase Noise Performance vs. LO Frequency, Nominal Conditions 0 –60 LOWER –10 SIDEBAND –70 –20 –80 LO FREQUENCY = 2500MHz Bm) –30 FEECDATRHRRIOERUGH Bc/Hz) –90 d d–100 T ( –40 E ( UTPU –50 SUSPIDPERBEASNSDED NOIS–110 O E –120 RF –60 THIRD AS HARMONIC PH–130 –70 –140 LO FREQUENCY = 100MHz –80 –150 –910825 1835 1845 1855F1R8E6Q5UE18N7C5Y (1M88H5z)1895 1905 1915 1925 10465-026 –160100 1k OF1F0SkET FREQ10U0EkNCY (Hz1)M 10M 10465-128 Figure 25. RF Output Spectral Plot over a 100 MHz Span Figure 28. Phase Noise Performance vs. LO Frequency, Supply, and Temperature Rev. B | Page 16 of 48

Data Sheet ADRF6755 –60 –60 900MHz PHASE NOISE (dBc/Hz) 1800MHz PHASE NOISE (dBc/Hz) –70 –70 2100MHz PHASE NOISE (dBc/Hz) –80 –80 Hz) –90 Hz) –90 dBc/–100 dBc/ –100 E ( E ( OIS–110 OIS –110 N N E –120 E –120 S S A A PH–130 PH –130 –140 –140 –150 –150 –160100 1k OF1F0SkET FREQ10U0EkNCY (Hz1)M 10M 10465-129 –160100 1k OF1F0SkET FREQ10U0EkNCY (Hz1)M 10M 10465-168 Figure 29. Phase Noise Performance Distribution at Worst-Case Conditions Figure 32. Phase Noise Performance vs. LO Frequency, Nominal Conditions with Narrow Loop Bandwidth 0.50 –50 0.45 –55 c) 0.40 B d Degrees)00..3305 Y SPURS ( ––6650 ER (0.25 DAR –70 T N S JIT0.20 BOU –75 RM0.15 ER EG –80 0.10 T +25°C 5V MAX SPUR IN +85°C 4.75V MAX SPUR 0.05 –85 +85°C 5.25V MAX SPUR –40°C 4.75V MAX SPUR –40°C 5.25V MAX SPUR 0100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-133 –90100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-166 Figure 30. Integrated Phase Noise over an Integration Bandwidth of 1 kHz to Figure 33. Integer Boundary Spur Performance vs. LO Frequency, 8 MHz vs. LO Frequency at Nominal Conditions Supply, and Temperature 90 –50 1875MHz REFERENCE SPURS AT 80MHz OFFSET 2310MHz c) PFD SPURS AT 40MHz OFFSET 80 B d Y ( –60 70 NC E U %) 60 Q –70 NCE( 50 T FRE RE SE –80 OCCUR 3400 MHz OFF –90 0 1 20 > RS –100 10 PU S 00.10 0.15 0R.2M0SJITT0E.R25 (Degree0s.3)0 0.35 0.40 10465-034 –110100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-132 Figure 31. Integrated Phase Noise Distribution over an Integration Figure 34. Spurs > 10 MHz from Carrier vs. LO Frequency, Bandwidth of 1 kHz to 8 MHz at 1875 MHz and 2310 MHz Supply, and Temperature Rev. B | Page 17 of 48

ADRF6755 Data Sheet 1G 60 NOMINAL 100M WORST CASE 50 10M R (Hz) 1M %) 40 RO100k E ( R C E N REQUENCY 110010kk SATCAQRUTIS OITFION ATOCQ 1U00ISHIzTION OCCURRE 2300 F 10 LDET 10 NUMBER OF PFD 1 CYCLES TO DECLARE LDET = 4096 0.1–50–30–10 10 30 50 70TI9M0E 1(1µ0s)130150170190210230250 10465-134 0–1.0 –0.8ATT–E0N.6UA–T0O.4R R–E0L.2ATIVE0 STE0P.2ACC0U.4RAC0Y.6 (dB)0.8 1.0 10465-136 Figure 35. PLL Frequency Settling Time at Worst-Case LO Frequency Figure 38. Attenuator Relative Step Accuracy Distribution at Nominal with Lock Detect Shown and Worst-Case Conditions, LO > 300 MHz, All Attenuation Steps 5 14 NOMINAL 0 WORST CASE 12 –5 m) –10 10 B %) WER (d ––2105 ENCE ( 8 O R P –25 R UT CU 6 P –30 C T O OU –35 4 –40 2 –45 –50100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-131 0–3.25–2A.7T5–T2E.2NF5U–U1AL.T7L5O –O1RU. 2RT5–EP0LU.7AT5T– F0IVR.2EE5 Q0S.UT2E5EPN0.CA7Y5C C1R.UA25RNA1G.C7E5Y (2dA.B2C)5R2O.7S5S3.25 10465-137 Figure 36. Attenuator Gain vs. LO Frequency by Gain Code, All Attenuator Figure 39. Attenuator Relative Step Accuracy Across Full Output Code Steps Frequency Range Distribution at Nominal and Worst-Case Conditions, LO > 300 MHz, All Attenuation Steps 1.0 2 B) B) Y (d Y (d ACCURAC 0.5 ACCURAC –20 ATTENUATOR RELATIVE STEP––10..050 ATTENUATORABSOLUTE STEP –––864 –1.5100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-138 –10100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-141 Figure 37. Attenuator Relative Step Accuracy over all Attenuation Steps Figure 40. Attenuator Absolute Step Accuracy over all Attenuation Steps vs. LO Frequency, Nominal Conditions vs. LO Frequency, Nominal Conditions Rev. B | Page 18 of 48

Data Sheet ADRF6755 30 10 NOMINAL WORST CASE 9 25 8 CE (%) 20 ME (µs) 67 N TI URRE 15 LING 5 C T 4 OC 10 SET 3 2 5 1 0–5.0–4.6A–T4T.2EN–U3.A8T–O3R.4A–B3S.0O–L2U.6TE– 2S.2TE–P1.A8C–C1U.4R–A1C.0Y– (0d.B6)–0.2 0.2 10465-139 00 5 10 ST1A5RTIN2G0ATT2E5NUAT3O0R ST35EP 40 45 50 10465-162 Figure 41. Attenuator Absolute Step Accuracy Distribution at Nominal Figure 44. Attenuator Settling Time to 0.5 dB for Small Steps and Worst-Case Conditions, LO > 300 MHz, All Attenuation Steps (1 dB to 6 dB) at Nominal Conditions 2.0 20 1.5 18 B) Hz (d 1.0 16 0M s) 14 N FLATNEES INANY 4––100...0505 SETTLING TIME (µ 110268 AI 4 G –1.5 2 –2.0100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-145 00 5 10 ST1A5RTIN2G0ATT2E5NUAT30OR S3T5EP 40 45 50 10465-161 Figure 42. Gain Flatness in any 40 MHz for all Attenuation Steps vs. Figure 45. Attenuator Settling Time to 0.2 dB for Large Steps LO Frequency at Nominal Conditions (7 dB to 47 dB) at Nominal Conditions 10 20 9 18 8 16 ME (µs) 67 ME (µs) 1124 G TI 5 G TI 10 N N ETTLI 4 ETTLI 8 S 3 S 6 2 4 1 2 0 0 5 10 ST1A5RTIN2G0ATT2E5NUAT3O0R ST3E5P 40 45 50 10465-163 00 5 10 ST1A5RTIN2G0ATT2E5NUAT3O0R ST35EP 40 45 50 10465-164 Figure 43. Attenuator Setting Time to 0.2 dB for Small Steps (1 dB to 6 dB) at Figure 46. Attenuator Settling Time to 0.5 dB for Large Steps Nominal Conditions (7 dB to 47 dB) at Nominal Conditions Rev. B | Page 19 of 48

ADRF6755 Data Sheet 100 50 NOMINAL SETTLING TIME TO 0.2dB NOMINAL SETTLING TIME TO 0.2dB 90 WNOOMRISNTA LC ASSEET TSLEITNTGL TINIMGE T TIMOE 0 T.5Od B0.2dB 45 WNOOMRISNTA LC ASSEET TSLEITNTGL TINIMGE T TIMOE 0 T.5Od B0.2dB WORST CASE SETTLING TIME TO 0.5dB WORST CASE SETTLING TIME TO 0.5dB 80 40 70 35 %) %) E ( 60 E ( 30 C C N N RE 50 RE 25 R R U U C 40 C 20 C C O O 30 15 20 10 10 5 00 0.5 1.0ATT1E.5NUAT2.O0R SE2.T5TLIN3G.0 TIM3E.5 (µs)4.0 4.5 5.0 10465-146 00 3 6 AT9TENU1A2TOR1 5SETT1L8ING2 T1IME2 (4µs) 27 30 33 10465-149 Figure 47. Attenuator Settling Time to 0.2 dB and 0.5 dB Distribution at Figure 50. Attenuator Settling Time to 0.2 dB and 0.5 dB Distribution at Nominal and Worst-Case Conditions for Typical Small Step Nominal and Worst-Case Conditions for Worst-Case Large Step (47 dB to 0 dB) 100 0 NOMINAL SETTLING TIME TO 0.2dB WORST CASE SETTLING TIME TO 0.2dB 90 NOMINAL SETTLING TIME TO 0.5dB WORST CASE SETTLING TIME TO 0.5dB –10 80 70 m) –20 E (%) 60 R (dB TURN-ON = 180ns C E –30 N W URRE 50 T PO –40 TURN-OFF= 350ns C 40 U C P O 30 OUT –50 20 –60 10 TXDIS 00 3 A6TTENUA9TOR SE1T2TLING1 5TIME (µ1s8) 21 24 10465-147 –700 1 2 TXDIS3 SETTL4ING TIM5E (μs) 6 7 8 10465-144 Figure 48. Attenuator Settling Time to 0.2 dB and 0.5 dB Distribution at Figure 51. TXDIS Settling Time at Worst-Case Supply Nominal and Worst-Case Conditions for Worst-Case Small Step (36 dB to 42 dB) and Temperature 100 NOMINAL SETTLING TIME TO 0.2dB WORST CASE SETTLING TIME TO 0.2dB 90 NOMINAL SETTLING TIME TO 0.5dB WORST CASE SETTLING TIME TO 0.5dB 80 70 %) E ( 60 C N RE 50 R U C 40 C O 30 20 10 00 3 ATT6ENUATO9R SETTL1I2NG TIME1 5(µs) 18 21 10465-148 Figure 49. Attenuator Settling Time to 0.2 dB and 0.5 dB Distribution at Nominal and Worst-Case Conditions for Typical Large Step Rev. B | Page 20 of 48

Data Sheet ADRF6755 THEORY OF OPERATION OThVeE ARDVRIFE6W75 5 device can be divided into the following basic RFREPFOIIMNN DOU×B2LER R-D5I-VBIIDTER ÷2 TPOFD 10465-053 Figure 53. Reference Input Path building blocks: • PLL synthesizer and VCO The PFD frequency equation is • Quadrature modulator fPFD = fREFIN × [(1 + D)/(R × (1 + T))] (1) • Attenuator where: • Voltage regulator f is the reference input frequency. REFIN • I2C/SPI interface D is the doubler bit. R is the programmed divide ratio of the binary 5-bit Each of these building blocks is described in detail in the programmable reference divider (1 to 32). sections that follow. T is the R/2 divider setting bit (CR10[6] = 0 or 1). PLL SYNTHESIZER AND VCO If no division is required, it is recommended that the 5-bit Overview R-divider and the divide-by-2 be disabled by setting CR5[4] = 0. The phase-locked loop (PLL) consists of a fractional-N frequency If an even numbered division is required, enable the divide-by-2 synthesizer with a 25-bit fixed modulus, allowing a frequency by setting CR5[4] = 1 and CR10[6] = 1 and implement the resolution of less than 1 Hz over the entire frequency range. It remainder of the division in the 5-bit R-divider. If an odd number also has an integrated voltage-controlled oscillator (VCO) with division is required, set CR5[4] = 1 and implement all of the a fundamental output frequency ranging from 2310 MHz to division in the 5-bit R-divider. 4800 MHz. An RF divider, controlled by Register CR28, RF Fractional-N Divider Bits[2:0], extends the lower limit of the local oscillator (LO) The RF fractional-N divider allows a division ratio in the PLL frequency range to 100 MHz. See Table 6 for more details on feedback path that can range from 23 to 4095. The relationship Register CR28. between the fractional-N divider and the LO frequency is Reference Input Section described in the INT and FRAC Relationship section. The reference input stage is shown Figure 52. SW1 and SW2 are INT and FRAC Relationship normally closed switches. SW3 is normally open. When power- The integer (INT) and fractional (FRAC) values make it possible to down is initiated, SW3 is closed, and SW1 and SW2 are open. This generate output frequencies that are spaced by fractions of the ensures that there is no loading of the REFIN pin at power-down. phase frequency detector (PFD) frequency. See the Example— POWER-DOWN CONTROL Changing the LO Frequency section for more information. The LO frequency equation is NC 100kΩ SW2 TO LO = fPFD × (INT + (FRAC/225))/2RFDIV (2) REFIN NC R-DIVIDER BUFFER where: SW1 NC SW3 10465-052 fLPOFD iiss tthhee PloFcDal forsecqiulleantocry .f requency. Figure 52. Reference Input Stage INT is the integer component of the required division factor Reference Input Path and is controlled by the CR6 and CR7 registers. FRAC is the fractional component of the required division The on-chip reference frequency doubler allows the input factor and is controlled by the CR0 to CR3 registers. reference signal to be doubled. This is useful for increasing the RFDIV is set in Register CR28, Bits[2:0], and controls the PFD comparison frequency. Making the PFD frequency higher setting of the divider at the output of the PLL. improves the noise performance of the system. Doubling the PFD frequency usually improves the in-band phase noise RF N-DIVIDER N = INT + FRAC/225 TO performance by up to 3 dBc/Hz. FROM VCO PFD OUTPUT N-COUNTER DIVIDERS The 5-bit R-divider allows the input reference frequency (REF ) to IN THIRD-ORDER be divided down to produce the reference clock to the PFD. FRACTIONAL INTERPOLATOR Division ratios from 1 to 32 are allowed. pAant ha dadlloitwiosn faolr d aiv girdeea-tbeyr- d2i v(÷is2io) nfu rnacntgioe.n in the reference input RINETG VFARLAUCE 10465-054 Figure 54. RF Fractional-N Divider Rev. B | Page 21 of 48

ADRF6755 Data Sheet Phase Frequency Detector (PFD) and Charge Pump 2.5 The PFD takes inputs from the R-divider and the N-counter and 2.3 produces an output proportional to the phase and frequency differ- 2.1 ence between them (see Figure 55 for a simplified schematic). 1.9 The PFD includes a fixed delay element that sets the width of V) 1.7 the antibacklash pulse, ensuring that there is no dead zone in (NE 1.5 the PFD transfer function. U T V 1.3 UP HI D1 Q1 1.1 U1 0.9 +IN CLR1 0.7 DELAY U3 CHPUAMRGPE CP 0.5100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-157 Figure 56. VTUNE vs. LO Frequency The VCO displays a variation of K as V varies within the CLR2 DOWN VCO TUNE HI D2 Q2 band and from band to band. Figure 57 shows how K varies VCO –IN U2 10465-055 acacrlcoussla tthineg f uthlle f rleoqoupe nficltye rra bnagned. Fwiigdutrhe a5n7d i si nudseivfuidl uwahl elno op filter Figure 55. PFD Simplified Schematic components using ADISimPLL™. ADISimPLL is an Analog Lock Detect (LDET) Devices, Inc., simulator that aids in PLL design, particularly with respect to the loop filter. It reports parameters such as phase LDET (Pin 44) signals when the PLL has achieved lock to an noise, integrated phase noise, and acquisition time for a error frequency of less than 100 Hz. On a write to Register CR0, particular set of input conditions. ADISimPLL can be a new PLL acquisition cycle starts, and the LDET signal goes downloaded from www.analog.com/adisimpll. low. When lock has been achieved, this signal returns high. 40 Voltage-Controlled Oscillator (VCO) The VCO core in the ADRF6755 consists of three separate VCOs, each with 16 overlapping bands. This configuration of 48 bands 30 allows the VCO frequency range to extend from 2310 MHz to 4800 MHz. The three VCOs are divided by a programmable Hz/V) divider, RFDIV, controlled by Register CR28, Bits[2:0]. This (MO 20 divider provides divisions of 1, 2, 4, 8, and 16 to ensure that the C V K frequency range is extended from 144.375 MHz (2310 MHz/16) to 4800 MHz (4800 MHz/1). A divide-by-2 quadrature circuit in 10 the path to the modulator then provides the full LO frequency range from 100 MHz to 2400 MHz. tFhieg uthrere 5e6 V sChOows so vae srwlaepeppin ogf aVnTdU NtEh ves m. LuOlt ifpreleq uoevnecryla dpepminogn bstarnadtisn g 0100 300 500 700 9L0O0 F1R10E0Q1U3E0N0C1Y5 0(0MH17z0)01900210023002500 10465-158 within each VCO at the LO frequency range of 100 MHz to Figure 57. KVCO vs. LO Frequency 2400 MHz. Note that Figure 56 includes the RFDIV being Autocalibration incorporated to provide further divisions of the fundamental VCO The correct VCO and band are chosen automatically by the frequency; thus, each VCO is used on multiple different occasions VCO and band select circuitry when Register CR0 is updated. throughout the full LO frequency range. The choice of three This is referred to as autocalibration. The autocalibration time 16-band VCOs and an RFDIV allows the wide frequency range to is set by Register CR25. be covered without large VCO sensitivity (K ) or resultant VCO poor phase noise and spurious performance. Autocalibration Time = (BSCDIV × 28)/PFD (3) where: BSCDIV = Register CR25, Bits[7:0]. PFD = PFD frequency. For a PFD frequency of 40 MHz, set BSCDIV = 100 to set an autocalibration time of 70 µs. Rev. B | Page 22 of 48

Data Sheet ADRF6755 Note that BSCDIV must be recalculated if the PFD frequency is Programming the Correct LO Frequency changed. The recommended autocalibration setting is 70 µs. There are two steps to programming the correct LO frequency. During this time, the VCO V is disconnected from the output TUNE The user must calculate the RFDIV value based on the required of the loop filter and is connected to an internal reference voltage. LO frequency and PFD frequency, and the N-divider ratio that A typical frequency acquisition is shown in Figure 58. is required in the PLL. 1G 1. Calculate the value of RFDIV, which is used to program 100M Register CR28, Bits[2:0] and CR27, Bit 4 from the 10M following lookup table, Table 6. R (Hz) 1M Table 6. RFDIV Lookup Table O AUTOCAL R100k TIME (μs) R CR28[2:0] E Y 10k LO Frequency (MHz) RFDIVIDER = RFDIV CR27[4] NC ACQUISITION TO 100Hz UE 1k 1155 < LO < 2400 Divide-by-1 000 1 Q RE 100 577.5 < LO ≤ 1155 Divide-by-2 001 0 F 288.75 < LO ≤ 577.5 Divide-by-4 010 0 10 144.375 < LO ≤ 288.75 Divide-by-8 011 0 1 100 < LO ≤ 144.375 Divide-by-16 100 0 0.10 25 50 75 100TIM1E2 5(µs)150 175 200 225 250 10465-156 2. Using the following equation, calculate the value of the N-divider: Figure 58. PLL Acquisition After autocalibration, normal PLL action resumes, and the N = (2RFDIV × LO)/fPFD (4) correct frequency is acquired to within a frequency error of where: 100 Hz in 170 μs typically. For a maximum cumulative step of N is the N-divider value. 100 kHz/2RFDIV, autocalibration can be turned off by setting RFDIV is the setting in Register CR28, Bits[2:0]. Register CR24, Bit 0 = 1. This enables cumulative PLL acquisi- LO is the local oscillator frequency. tions of ≤100 kHz (for RFDIV = ÷1, 50 kHz for RFDIV = ÷2, f is the PFD frequency. PFD and so on) to occur without the autocalibration procedure, This equation is a different representation of Equation 2. which improves acquisition times significantly (see Figure 59). Example to Program the Correct LO Frequency 1M Assume that the PFD frequency is 40 MHz and that the 100k required LO frequency is 1875 MHz. Hz) From Table 6, 2RFDIV = 1 (RFDIV = 0) R ( 10k O N = (1 × 1875 × 106)/(40 × 106) = 46.875 R R E Y 1k The N-divider value is composed of integer (INT) and C UEN ACQUISITION TO 100Hz fractional (FRAC) components according to the following EQ 100 equation: R F N = INT + FRAC/225 (5) 10 INT = 46 and FRAC = 29,360,128 10 50 TIM1E0 0(μs) 150 200 10465-159 Tthhee r eagpipstreorp mriaatpe. rTehgeis oterrdse mr iuns tw thhiecnh bthe ep rreoggirsatemrsm aerde parcocogrrdaminmg teod is important. Writing to CR0 initiates a PLL acquisition cycle. Figure 59. PLL Acquisition Without Autocalibration for a 100 kHz Step If the programmed LO frequency requires a change in the value of CR27[4] (see Table 6), CR27 should be the last register programmed, preceded by CR0. If the programmed LO frequency does not require a change in the value of CR27[4], it is optional to omit the write to CR27 and, in that case, CR0 should be the last register programmed. Rev. B | Page 23 of 48

ADRF6755 Data Sheet QUADRATURE MODULATOR differential termination is recommended at the baseband inputs, Overview and this dominates the input impedance as seen by the input baseband signal. This ensures that the input impedance, as seen by A basic block diagram of the ADRF6755 quadrature modulator the input circuit, remains flat across the baseband bandwidth. circuit is shown in Figure 60. The VCO/RFDIVIDER generates See Figure 62 for a typical configuration. a signal at the 2× LO frequency, which is then divided down to give a signal at the LO frequency. This signal is then split into in-phase CURRENT OUTPUT DAC (EXAMPLE: AD9779) ADRF6755 and quadrature components to provide the LO signals that drive the mixers. OUT1_P IBB 50Ω LOW- V-TO-I PASS FILTER 100Ω IBB 50Ω IBB OUT1_N IBB OUT2_N QBB ATTREFNOUUATT OTOR PQHUAASDE ÷2 RF DIVIDER VCO 50Ω FPLILOATSWES-R 100Ω SPLITTER 50Ω V-TO-I OUT2_P QBB 10465-062 QQBBBB 10465-060 The swing oFfi gthuree A62D. T9y7p7ic9a lo Buatspeubat ncdu Irnrpeuntt Cso rnafniggueras tfioronm 0 mA to Figure 60. Block Diagram of the Quadrature Modulator 20 mA. The ac voltage swing is 1 V p-p single-ended or 2 V p-p The I and Q baseband input signals are converted to currents by differential with the 50 Ω resistors in place. The 100 Ω differen- the V-to-I stages, which then drive the two mixers. The outputs tial termination resistors at the baseband inputs have the effect of these mixers combine to feed the single-ended output. This of limiting this swing without changing the dc bias condition of single-ended output is then fed to the attenuator and, finally, to 500 mV. The low-pass filter is used to filter the DAC outputs the external RFOUT signal pin. and remove images when driving a modulator. Baseband Inputs Another consideration is that the baseband inputs actually source a The baseband inputs, QBB, QBB, IBB, and IBB, must be driven current of 240 μA out of each of the four inputs. This current must be taken into account when setting up the dc bias of 500 mV. In from a differential source. The nominal drive level of 0.9 V p-p the initial example based on Figure 61, an error of 12 mV occurs differential (450 mV p-p on each pin) should be biased to a due to the 240 μA current flowing through the 50 Ω resistor. common-mode level of 500 mV dc. Analog Devices recommends that the accuracy of the dc bias To set the dc bias level at the baseband inputs, refer to Figure 61. should be 500 mV ± 25 mV. It is also important that this 240 μA The average output current on each of the AD9779 outputs is current have a dc path to ground. 10 mA. A current of 10 mA flowing through each of the 50 Ω Optimization resistors to ground produces the desired dc bias of 500 mV at each of the baseband inputs. The carrier feedthrough and the sideband suppression performance of the ADRF6755 can be improved over the CURRENT OUTPUT DAC ADRF6755 (EXAMPLE: AD9779) specifications in Table 1 by using the following optimization techniques. OUT1_P IBB 50Ω Carrier Feedthrough Nulling Carrier feedthrough results from dc offsets that occur between 50Ω OUT1_N IBB the P and N inputs of each of the differential baseband inputs. Normally these inputs are set to a dc bias of approximately 500 mV. OUT2_N QBB 50Ω However, if a dc offset is introduced between the P and N inputs of either or both I and Q inputs, the carrier feedthrough is affected 50Ω OUT2_P QBB 10465-061 ilenv eeilt hreemr aa ipnos saitt i5v0e 0o rm aV n (eagvaetrivaeg efa Ps hainodn .N N loetvee tl)h. aTt hthee I dcch abnianse l Figure 61. Establishing DC Bias Level on Baseband Inputs offset is often held constant while the Q channel offset is varied until a minimum carrier feedthrough level is obtained. Then, The differential baseband inputs (QBB, QBB, IBB, and IBB) while retaining the new Q channel offset, the I channel offset is consist of the bases of PNP transistors, which present a high adjusted until a new minimum is reached. This is usually per- impedance of about 30 kΩ in parallel with approximately 2 pF formed at a single frequency and, thus, is not optimized over of capacitance. The impedance is approximately 30 kΩ below the complete frequency range. Multiple optimizations at different 1 MHz and starts to roll off at higher frequency. A 100 Ω Rev. B | Page 24 of 48

Data Sheet ADRF6755 frequencies must be performed to ensure optimum carrier feed- the CS pin (Pin 27). Bits[4:0] of the slave address are set to all through across the full frequency range. 0s. The slave address consists of the seven MSBs of an 8-bit word. The LSB of the word sets either a read or a write operation Sideband Suppression Nulling (see Figure 63). Logic 1 corresponds to a read operation, whereas Sideband suppression results from relative gain and relative phase Logic 0 corresponds to a write operation. offsets between the I channel and Q channel and can be optimized To control the device on the bus, the following protocol must through adjustments to those two parameters. Adjusting only be followed. The master initiates a data transfer by establishing one parameter improves the sideband suppression only to a a start condition, defined by a high-to-low transition on SDA point. For optimum sideband suppression, an iterative adjustment while SCL remains high. This indicates that an address/data between phase and amplitude is required. stream follows. All peripherals respond to the start condition ATTENUATOR and shift the next eight bits (the 7-bit address and the R/W bit). The digital attenuator consists of six attenuation blocks: 1 dB, The bits are transferred from MSB to LSB. The peripheral that 2 dB, 4 dB, 8 dB, and two 16 dB blocks; each is separately recognizes the transmitted address responds by pulling the data controlled. Each attenuation block consists of field effect transistor line low during the ninth clock pulse. This is known as an (FET) switches and resistors that form either a pi-shaped or a acknowledge bit. All other devices then withdraw from the bus T-shaped attenuator. By controlling the states of the FET switches and maintain an idle condition. During the idle condition, the through the control lines, each attenuation block can be set to device monitors the SDA and SCL lines waiting for the start the pass state (0 dB) or the attenuation state (1 dB to 47 dB). condition and the correct transmitted address. The R/W bit The various combinations of the six blocks provide the determines the direction of the data. Logic 0 on the LSB of the attenuation states from 0 dB to 47 dB in 1 dB increments. first byte indicates that the master writes information to the peripheral. Logic 1 on the LSB of the first byte indicates that the VOLTAGE REGULATOR master reads information from the peripheral. The voltage regulator is powered from a 5 V supply that is The ADRF6755 acts as a standard slave device on the bus. The data provided by VCC1 (Pin 11) and produces a 3.3 V nominal on the SDA pin (Pin 29) is eight bits long, supporting the 7-bit regulated output voltage, REGOUT, on Pin 12. This pin must addresses plus the R/W bit. The ADRF6755 has 34 subaddresses be connected (external to the IC) to the VREG1 through VREG6 to enable the user-accessible internal registers. Therefore, it package pins. interprets the first byte as the device address and the second Decouple the regulator output (REGOUT) with a parallel byte as the starting subaddress. Auto-increment mode is supported, combination of 10 pF and 220 µF capacitors. The 220 µF which allows data to be read from or written to the starting sub- capacitor, which is recommended for best performance, address and each subsequent address without manually addressing decouples broadband noise, leading to better phase noise. Each the subsequent subaddress. A data transfer is always terminated VREGx pin should have the following decoupling capacitors: by a stop condition. The user can also access any unique subaddress 100 nF multilayer ceramic with an additional 10 pF in parallel, register on a one-by-one basis without updating all registers. both placed as close as possible to the device under test (DUT) Stop and start conditions can be detected at any stage of the data power supply pins. X7R or X5R capacitors are recommended. transfer. If these conditions are asserted out of sequence with See the Evaluation Board section for more information. normal read and write operations, they cause an immediate jump I2C INTERFACE to the idle condition. If an invalid subaddress is issued by the The ADRF6755 supports a 2-wire, I2C-compatible serial bus user, the ADRF6755 does not issue an acknowledge and returns to that drives multiple peripherals. The serial data (SDA) and serial the idle condition. In a no acknowledge condition, the SDA line is clock (SCL) inputs carry information between any devices that not pulled low on the ninth pulse. See Figure 64 and Figure 65 are connected to the bus. Each slave device is recognized by a for sample write and read data transfers, Figure 66 for the timing unique address. The ADRF6755 has two possible 7-bit slave protocol, and Figure 2 for a more detailed timing diagram. addresses for both read and write operations. The MSB of the 7-bit slave address is set to 1. Bit A5 of the slave address is set by R/W SLAVEADDRESS[6:0] CTRL 1 A5 0 0 0 0 0 X MSB = 1 SPE(ICNTS 2B)7Y 01 == WRDR 10465-063 Figure 63. Slave Address Configuration Rev. B | Page 25 of 48

ADRF6755 Data Sheet S SLAVEADDR, LSB = 0 (WR) A(S) SUBADDR A(S) DATA A(S) DATA A(S) P SA (=S )S =TAARCTK NBOITWLEDGE BY SLAVE P = STOP BIT 10465-064 Figure 64. I2C Write Data Transfer S SLAVEADDR, LSB = 0 (WR) A(S) SUBADDR A(S) S SLAVEADDR, LSB = 1 (RD) A(S) DATA A(M) DATA A(M) P SA (=S )S =TAARCTK NBOITWLEDGE BY SLAVE PA (=M S) T=OAPC KBNITOWLEDGE BY MASTERA(M) = NOACKNOWLEDGE BY MASTER 10465-065 Figure 65. I2C Read Data Transfer START BIT STOPBIT SLAVEADDRESS SUBADDRESS DATA SDA A6 A5 A7 A0 D7 D0 SCL S ADSDLRAV[4E:0] WR ACK SUBADDR[6:1] ACK DATA[6:1] ACK P 10465-066 Figure 66. I2C Data Transfer Timing Rev. B | Page 26 of 48

Data Sheet ADRF6755 SPI INTERFACE SPI Serial Interface Functionality The ADRF6755 also supports the SPI protocol. The part powers The SPI serial interface of the ADRF6755 consists of the CS, up in I2C mode but is not locked in this mode. To stay in I2C SDI (SDI/SDA), CLK (CLK/SCL), and SDO pins. CS is used to mode, it is recommended that the user tie the CS line to either select the device when more than one device is connected to the 3.3 V or GND, thus disabling SPI mode. It is not possible to lock serial clock and data lines. CLK is used to clock data in and out the I2C mode, but it is possible to select and lock the SPI mode. of the part. The SDI pin is used to write to the registers. The SDO pin is a dedicated output for the read mode. The part operates To select and lock the SPI mode, three pulses must be sent to the in slave mode and requires an externally applied serial clock to CS pin, as shown in Figure 67. When the SPI protocol is locked the CLK pin. The serial interface is designed to allow the part to be in, it cannot be unlocked while the device is still powered up. To interfaced to systems that provide a serial clock that is synchronized reset the serial interface, the part must be powered down and to the serial data. powered up again. Figure 68 shows an example of a write operation to the Serial Interface Selection ADRF6755. Data is clocked into the registers on the rising edge The CS pin controls selection of the I2C or SPI interface. of CLK using a 24-bit write command. The first eight bits Figure 67 shows the selection process that is required to lock represent the write command, 0xD4; the next eight bits are the the SPI mode. To communicate with the part using the SPI register address; and the final eight bits are the data to be written protocol, three pulses must be sent to the CS pin. On the third to the specific register. Figure 69 shows an example of a read rising edge, the part selects and locks the SPI protocol. Consistent operation. In this example, a shortened 16-bit write command is with most SPI standards, the CS pin must be held low during all first used to select the appropriate register for a read operation, SPI communication to the part and held high at all other times. the first eight bits representing the write command, 0xD4, and the final eight bits representing the specific register. Then the CS line is pulsed low for a second time to retrieve data from the selected register using a 16-bit read command, the first eight bits representing the read command, 0xD5, and the final eight bits representing the contents of the register being read. Figure 3 shows the timing for both SPI read and SPI write operations. A B C CS (STARTING HIGH) SPI LOCKED ON SPI FRAMING THIRD RISING EDGE EDGE CS (STARTING A B C LOW) THIRSDP IR LISOINCGKE EDD OGNE SEPDIG FERAMING 10465-067 Figure 67. Selecting the SPI Protocol Rev. B | Page 27 of 48

ADRF6755 Data Sheet • • • CS CLK • • • • • • SDI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 START WRITE REGISTER COMMAND [0xD4] ADDRESS CS (CONTINUED) CLK (CONTINUED) SDI D7 D6 D5 D4 D3 D2 D1 D0 (CONTINUED) BDYATTAE STOP 10465-068 Figure 68. SPI Byte Write Example • • • CS CLK • • • • • • SDI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 START WRITE REGISTER COMMAND [0xD4] ADDRESS CS CLK SDI D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X SDO X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 START COMMRAENADD [0xD5] BDYATTAE STOP 10465-069 Figure 69. SPI Byte Read Example Rev. B | Page 28 of 48

Data Sheet ADRF6755 PROGRAM MODES Reference Input Path The ADRF6755 has 34 8-bit registers to allow program control The reference input path consists of a reference frequency doubler, of a number of functions. Either an SPI or an I2C interface can a 5-bit reference divider, and a divide-by-2 function (see Figure 53). be used to program the register set. For details about the interfaces The doubler is programmed through Register CR10, Bit 5. The and timing, see Figure 63 to Figure 69. The registers are 5-bit divider and divide-by-2 are enabled by programming documented in Table 8 to Table 28. Register CR5, Bit 4, and the division ratio is programmed through Register CR10, Bits[4:0]. The R/2 divider is programmed through Several settings in the ADRF6755 are double-buffered. These Register CR10, Bit 6. Note that these registers are double-buffered. settings include the FRAC value, the INT value, the 5-bit R-divider value, the reference frequency doubler, the R/2 divider, the RFDIV Charge Pump Current value, and the charge pump current setting. This means that Register CR9, Bits[7:4], specify the charge pump current setting. two events must occur before the part uses a new value for any With an R value of 4.7 kΩ, the maximum charge pump current is SET of the double-buffered settings. First, the new value is latched 5 mA. The following equation applies: into the device by writing to the appropriate register. Next, a I = 23.5/R new write must be performed on Register CR0. When CPmax SET Register CR0 is written, a new PLL acquisition takes place. The charge pump current has 16 settings from 312.5 μA to 5 mA. For the loop filter that is specified in the application solution, a For example, updating the fractional value involves a write to charge pump current of 5 mA (Register CR9[7:4] = 0xF) gives a Register CR3, Register CR2, Register CR1, and Register CR0. loop bandwidth of 100 kHz, which is the recommended loop Register CR3 should be written to first, followed by Register CR2 bandwidth setting. and Register CR1, and, finally, Register CR0. The new acquisition begins after the write to Register CR0. Double buffering ensures Transmit Disable Control (TXDIS) that the bits written to do not take effect until after the write to The transmit disable control (TXDIS) is used to disable the RF out- Register CR0. put. TXDIS is normally held low. When asserted (brought high), it 12-Bit Integer Value disables the RF output. Register CR14 is used to control which circuit blocks are powered down when TXDIS is asserted. To meet Register CR7 and Register CR6 program the integer value (INT) both the off isolation power specifications and the turn-on/ of the feedback division factor (N); see Equation 5 for details. turn-off settling time specifications, a value of 0x80 should be The INT value is a 12-bit number whose MSBs are programmed loaded into Register CR14. This effectively ensures that the through Register CR7, Bits[3:0]. The LSBs are programmed attenuator is always enabled when TXDIS is asserted, even if other through Register CR6, Bits[7:0]. The LO frequency setting is circuitry is disabled. described by Equation 2. An alternative to this equation is provided by Equation 4, which details how to set the N-divider Power-Down/Power-Up Control Bits value. Note that these registers are double buffered. The four programmable power-up and power-down control bits 25-Bit Fractional Value are as follows: Register CR3 to Register CR0 program the fractional value (FRAC)  Register CR12, Bit 2. Master power control bit for the PLL, of the feedback division factor (N); see Equation 5 for details. including the VCO. This bit is normally set to a default value The FRAC value is a 25-bit number whose MSB is programmed of 0 to power up the PLL. through Register CR3, Bit 0. The LSB is programmed through  Register CR28, Bit 4. Controls the RFDIVIDER. This bit is Register CR0, Bit 0. The LO frequency setting is described by normally set to a default value of 0 to power up the Equation 2. An alternative to this equation is described by RFDIVIDER. Equation 4, which details how to set the N-divider value. Note  Register CR27, Bit 2. Controls the LO monitor outputs, that these registers are double buffered. LOMON and LOMON. The default is 0 when the monitor RFDIV Value outputs are powered down. Setting this bit to 1 powers up the monitor outputs to one of four options, −6 dBm, The RFDIV value is dependent on the value of the LO frequency. −12 dBm, −18 dBm, or −24 dBm, as controlled by The RFDIV value can be selected from the list in Table 6. Apply Register CR27, Bits[1:0]. the selected RFDIV value to Equation 4, together with the LO  Register CR29, Bit 0. Controls the quadrature modulator frequency and PFD frequency values, to calculate the correct power. The default is 0, which powers down the modulator. N-divider value. Write a 1 to this bit to power up the modulator. Rev. B | Page 29 of 48

ADRF6755 Data Sheet Lock Detect (LDET) The appropriate setting to use depends on the PFD frequency as well as the desired accuracy when LDET is declared. The LDET Lock detect is enabled by setting Register CR23, Bit 4, to 1. The setting does not affect the acquisition time of the PLL. It only lock detect circuit is based on monitoring the up/down pulses affects the time at which LDET goes high. from the PFD. As acquisition proceeds, the width of these pulses reduces until they are less than a target width (set by VCO Autocalibration CR23[2]). At this point, a count of the number of successive The VCO uses an autocalibration technique to select the correct PFD cycles is initiated, where the width of the up/down pulses VCO and band, as explained in the Autocalibration section. remains less that the target width. When this count reaches a Register CR24, Bit 0, controls whether the autocalibration is target count (set by CR13[6] and CR23[3]), LDET is set. The enabled. For normal operation, autocalibration must be enabled. truth table for declaring LDET is given in Table 7. However, if using cumulative frequency steps of 100 kHz/2RFDIV or less, autocalibration can be disabled by setting this bit to 1 Table 7. Declaring LDET and then a new acquisition is initiated by writing to Register CR0. LDCount1 LDCount0 Number of PFD Cycles to CR13[6] CR23[3] Declare LDET Attenuator 0 0 2048 The attenuator can be programmed from 0 dB to 47 dB in steps 0 1 3072 of 1 dB. Control is through Register CR30, Bits[5:0]. 1 0 4096 Revision Readback 1 1 16,384 The revision of the silicon die can be read back via Register CR33. Rev. B | Page 30 of 48

Data Sheet ADRF6755 REGISTER MAP REGISTER MAP SUMMARY Table 8. Register Map Summary Register Address (Hex) Register Name Type Description 0x00 CR0 Read/write Fractional Word 4 0x01 CR1 Read/write Fractional Word 3 0x02 CR2 Read/write Fractional Word 2 0x03 CR3 Read/write Fractional Word 1 0x04 CR4 Read/write Reserved 0x05 CR5 Read/write 5-bit reference dividers enable 0x06 CR6 Read/write Integer Word 2 0x07 CR7 Read/write Integer Word 1 and MUXOUT control 0x08 CR8 Read/write Reserved 0x09 CR9 Read/write Charge pump current setting 0x0A CR10 Read/write Reference frequency control 0x0B CR11 Read/write Reserved 0x0C CR12 Read/write PLL power-up 0x0D CR13 Read/write Lock Detector Control 2 0x0E CR14 Read/write TXDIS control 0x0F CR15 Read/write Reserved 0x10 CR16 Read/write Reserved 0x11 CR17 Read/write Reserved 0x12 CR18 Read/write Reserved 0x13 CR19 Read/write Reserved 0x14 CR20 Read/write Reserved 0x15 CR21 Read/write Reserved 0x16 CR22 Read/write Reserved 0x17 CR23 Read/write Lock Detector Control 1 0x18 CR24 Read/write Autocalibration 0x19 CR25 Read/write Autocalibration Timer 0x1A CR26 Read/write Reserved 0x1B CR27 Read/write LO monitor output and LO selection 0x1C CR28 Read/write LO selection 0x1D CR29 Read/write Modulator 0x1E CR30 Read/write Attenuator 0x1F CR31 Read only Reserved 0x20 CR32 Read only Reserved 0x21 CR33 Read only Revision code Rev. B | Page 31 of 48

ADRF6755 Data Sheet REGISTER BIT DESCRIPTIONS Table 9. Register CR0 (Address 0x00), Fractional Word 4 Table 13. Register CR5 (Address 0x05), 5-Bit Reference Bit Description1 Divider Enable 7 Fractional Word F7 Bit Description 6 Fractional Word F6 7 Set to 0 5 Fractional Word F5 6 Set to 0 4 Fractional Word F4 5 Set to 0 3 Fractional Word F3 4 5-bit R-divider and divide-by-2 enable1 2 Fractional Word F2 0 = disable 5-bit R-divider and divide-by-2 (default) 1 Fractional Word F1 1 = enable 5-bit R-divider and divide-by-2 0 Fractional Word F0 (LSB) 3 Set to 0 2 Set to 0 1 Double-buffered. Loaded on a write to Register CR0. 1 Set to 0 Table 10. Register CR1 (Address 0x01), Fractional Word 3 0 Set to 0 Bit Description1 1 Double-buffered. Loaded on a write to Register CR0. 7 Fractional Word F15 6 Fractional Word F14 Table 14. Register CR6 (Address 0x06), Integer Word 2 5 Fractional Word F13 Bit Description1 4 Fractional Word F12 7 Integer Word N7 3 Fractional Word F11 6 Integer Word N6 2 Fractional Word F10 5 Integer Word N5 1 Fractional Word F9 4 Integer Word N4 0 Fractional Word F8 3 Integer Word N3 2 Integer Word N2 1 Double-buffered. Loaded on a write to Register CR0. 1 Integer Word N1 Table 11. Register CR2 (Address 0x02), Fractional Word 2 0 Integer Word N0 Bit Description1 1 Double-buffered. Loaded on a write to Register CR0. 7 Fractional Word F23 6 Fractional Word F22 Table 15. Register CR7 (Address 0x07), Integer Word 1 and 5 Fractional Word F21 MUXOUT Control 4 Fractional Word F20 Bit Description 3 Fractional Word F19 [7:4] MUXOUT control 2 Fractional Word F18 0000 = tristate 1 Fractional Word F17 0001 = logic high 0 Fractional Word F16 0010 = logic low 1101 = reference clock/2 1 Double-buffered. Loaded on a write to Register CR0. 1110 = RF fractional-N divider clock/2 Table 12. Register CR3 (Address 0x03), Fractional Word 1 3 Integer Word N111 Bit Description 2 Integer Word N101 7 Set to 0 1 Integer Word N91 6 Set to 0 0 Integer Word N81 5 Set to 0 1 Double-buffered. Loaded on a write to Register CR0. 4 Set to 0 3 Set to 0 2 Set to 1 1 Set to 0 0 Fractional Word F24 (MSB)1 1 Double-buffered. Loaded on a write to Register CR0. Rev. B | Page 32 of 48

Data Sheet ADRF6755 Table 16. Register CR9 (Address 0x09), Charge Pump Table 18. Register CR12 (Address 0x0C), PLL Power-Up Current Setting Bit Description Bit Description 7 Set to 0 [7:4] Charge pump current1 6 Set to 0 0000 = 0.3125 mA (default) 5 Set to 0 0001 = 0.63 mA 4 Set to 1 0010 = 0.94 mA 3 Set to 1 0011 = 1.25 mA 2 Power down PLL 0100 = 1.57 mA 0 = power up PLL (default) 0101 = 1.88 mA 1 = power down PLL 0110 = 2.19 mA 1 Set to 0 0111 = 2.50 mA 0 Set to 0 1000 = 2.81 mA 1001 = 3.13 mA Table 19. Register CR13 (Address 0x0D), Lock Detector Control 2 1010 = 3.44 mA Bit Description 1011 = 3.75 mA 7 Set to 1 1100 = 4.06 mA 6 LDCount1 (see Table 7) 1101 = 4.38 mA 5 Set to 1 1110 = 4.69 mA 4 Set to 0 1111 = 5.00 mA 3 Set to 1 3 Set to 0 2 Set to 0 2 Set to 0 1 Set to 0 1 Set to 0 0 Set to 0 0 Set to 0 Table 20. Register CR14 (Address 0x0E), TXDIS Control 1 Double-buffered. Loaded on a write to Register CR0. Bit Description Table 17. Register CR10 (Address 0x0A), Reference 7 TXDIS_LOCLK 0 = LO clock always running Frequency Control 1 = stop LO clock when TXDIS = 1 Bit Description 6 Set to 0 7 Set to 01 5 Set to 0 6 R/2 divider setting1 4 Set to 0 0 = bypass R/2 divider (default) 3 Set to 0 1 = select R/2 divider 2 Set to 0 5 Reference frequency doubler (R-doubler) enable1 1 Set to 0 0 = disable doubler (default) 0 Set to 0 1 = enable doubler [4:0] 5-bit R-divider setting1 Table 21. Register CR23 (Address 0x17), Lock Detector Control 1 00000 = divide by 32 (default) Bit Description 00001 = divide by 1 7 Set to 0 00010 = divide by 2 6 Set to 1 … 5 Set to 1 11110 = divide by 30 4 Lock detector enable 11111 = divide by 31 0 = lock detector disabled (default) 1 Double-buffered. Loaded on a write to Register CR0. 1 = lock detector enabled 3 Lock detector up/down count, LDCount0 (see Table 7) 2 Lock detector precision 0 = low, coarse (10 ns) 1 = high, fine (6 ns) 1 Set to 0 0 Set to 0 Rev. B | Page 33 of 48

ADRF6755 Data Sheet Table 22. Register CR24 (Address 0x18), Autocalibration Table 26. Register CR29 (Address 0x1D), Modulator Bit Description Bit Description 7 Set to 0 7 Set to 1 6 Set to 0 6 Set to 0 5 Set to 0 5 Set to 0 4 Set to 1 4 Set to 0 3 Set to 1 3 Set to 0 2 Set to 0 2 Set to 0 1 Set to 0 1 Set to 0 0 Disable autocalibration 0 Power up modulator 0 = enable autocalibration (default) 0 = power down (default) 1 = disable autocalibration 1 = power up Table 23. Register CR25 (Address 0x19), Autocalibration Timer Table 27. Register CR30 (Address 0x1E), Attenuator Bit Description Bit Description [7:0] Autocalibration timer 7 Set to 0 6 Set to 0 Table 24. Register CR27 (Address 0x1B), LO Monitor Output [5:0] Attenuator A5 to Attenuator A0 and LO Selection 000000 = 0 dB Bit Description 000001 = 1 dB 7 Set to 0 000010 = 2 dB 6 Set to 0 … 5 Set to 0 011111 = 31 dB 4 Frequency range; set according to Table 6 110000 = 32 dB 3 Set to 0 110001 = 33 dB 2 Power up LO monitor output … 0 = power down (default) 111101 = 45 dB 1 = power up 111110 = 46 dB [1:0] Monitor output power into 50 Ω 111111 = 47 dB 00 = −24 dBm (default) 01 = −18 dBm Table 28. Register CR33 (Address 0x21), Revision Code1 10 = −12 dBm Bit Description 11 = −6 dBm [7:0] Revision code 1 Read-only register. Table 25. Register CR28 (Address 0x1C), LO Selection Bit Description 7 Set to 0 6 Set to 0 5 Set to 0 4 Power down RFDIVIDER 0 = power up (default) 1 = power down 3 Set to 1 [2:0] RFDIV1, set according to Table 6 1 Double-buffered. Loaded on a write to Register CR0. Rev. B | Page 34 of 48

Data Sheet ADRF6755 SUGGESTED POWER-UP SEQUENCE INITIAL REGISTER WRITE SEQUENCE 22. Write 0xF0 to Register CR9. With the recommended loop filter component values and R = 4.7 kΩ, as shown in After applying power to the part, perform the initial register write SET Figure 70, the charge pump current is set to 5 mA for a sequence that follows. Note that Register CR33, Register CR32, and loop bandwidth of 100 kHz. Register CR31 are read-only registers. Also, note that all writable 23. Write 0x00 to Register CR8. Reserved register. registers should be written to on power-up. Refer to the Register 24. Write 0x0X to Register CR7. Set according to Equation 2 in Map section for more details on all registers. the Theory of Operation section. Also, set the MUXOUT 1. Write 0x00 to Register CR30. Set the attenuator to 0 dB gain. pin to tristate. 2. Write 0x80 to Register CR29. The modulator is powered 25. Write 0xXX to Register CR6. Set according to Equation 2 down. The modulator is powered down by default to ensure in the Theory of Operation section. that no spurious signals can occur on the RF output when 26. Write to Register CR5. Refer to the Reference Input Path the PLL is carrying out its first acquisition. The modulator section, in particular Equation 1. should be powered up only when the PLL is locked. 27. Write 0x01 to Register CR4. Reserved register. 3. Write 0x0X to Register CR28. RFDIV depends on the value 28. Write 0000010X binary to Register CR3. Set according to of the LO frequency to be used and is set according to Equation 2 in the Theory of Operation section. Table 6. Note that Register CR28, Bit 3, is set to 1. 29. Write 0xXX to Register CR2. Set according to Equation 2 4. Write 0xX0 to Register CR27. Bit 4 depends on the LO in the Theory of Operation section. frequency to be used and is set according to Table 6. 30. Write 0xXX to Register CR1. Set according to Equation 2 5. Write 0x00 to Register CR26. Reserved register. in the Theory of Operation section. 6. Write 0x64 to Register CR25, the autocalibration timer. 31. Write 0xXX to Register CR0. Set according to Equation 2 This setting applies for PFD = 40 MHz. For other PFDs, in the Theory of Operation section. Register CR0 must be refer to Equation 3 in the VCO Autocalibration section. the last register written for all the double-buffered bit 7. Write 0x18 to Register CR24. Enable autocalibration. writes to take effect. 8. Write 0x70 to Register CR23. Enable the lock detector and 32. Write to Register CR27, setting Bit 4 according to Table 6. choose the recommended lock detect timing. This setting 33. Monitor the LDET output or wait 170 μs to ensure that the applies to PFD = 40 MHz. For other PFDs, refer to the PLL is locked. Lock Detect (LDET) section in the Program Modes 34. Write 0x81 to Register CR29. Power up the modulator. The section. write to Register CR29 does not need to be followed by a write 9. Write 0x80 to Register CR22. Reserved register. to Register CR0 because this register is not double-buffered. 10. Write 0x00 to Register CR21. Reserved register. Example—Changing the LO Frequency 11. Write 0x00 to Register CR20. Reserved register. 12. Write 0x80 to Register CR19. Reserved register. Following is an example of how to change the LO frequency 13. Write 0x60 to Register CR18. Reserved register. after the initialization sequence. Using an example in which 14. Write 0x00 to Register CR17. Reserved register. the PLL is locked to 2000 MHz, the following conditions apply: 15. Write 0x00 to Register CR16. Reserved register. • f = 40 MHz (assumed) 16. Write 0x00 to Register CR15. Reserved register. PFD • Divide ratio N = 50; therefore, INT = 50 decimal and 17. Write 0x80 to Register CR14. Stop LO when TXDIS = 1. FRAC = 0 18. Write 0xE8 to Register CR13. This setting applies to PFD = • RFDIVIDER = divide-by-1. See Table 6. 40 MHz. For other PFDs, refer to the Lock Detect (LDET) section in the Program Modes section. Register CR28[2:0] = 000 19. Write 0x18 to Register CR12. Power up the PLL. Register CR27[4] = 1 20. Write 0x00 to Register CR11. Reserved register. The INT registers contain the following values: 21. Write to Register CR10. Refer to the Reference Input Path Register CR7 = 0x00 and Register CR6 = 0x32 section, in particular Equation 1. The FRAC registers contain the following values: Register CR3 = 0x04, Register CR2 = 0x00, Register CR1 = 0x00, and Register CR0 = 0x00 Rev. B | Page 35 of 48

ADRF6755 Data Sheet To change the LO frequency to 925 MHz, The FRAC registers contain the following values: Register CR3 = 0x04, Register CR2 = 0x80, • f = 40 MHz (assumed) PFD Register CR1 = 0x00, and Register CR0 = 0x00 • Divide ratio N = 46.25; therefore, INT = 46 decimal and FRAC = 8,388,608 Note that Register CR27 should be the last write in this • RFDIVIDER = divide-by-2. See Table 6. sequence, preceded by CR0. Writing to Register CR0 causes all double-buffered registers to be updated, including the INT, Register CR28[2:0] = 001 FRAC, and RFDIV registers, and starts a new PLL acquisition. Register CR27[4] = 0 The INT registers contain the following values: Register CR7 = 0x00 and Register CR6 = 0x2E Rev. B | Page 36 of 48

Data Sheet ADRF6755 EVALUATION BOARD GENERAL DESCRIPTION SPI Interface The EVAL-ADRF6755SDZ evaluation board is designed to allow The SPI interface is provided by an additional SPD-S board. This the user to evaluate the performance of the ADRF6755. It contains must be ordered with the ADRF6755 evaluation board. The system the following: demonstration platform (SDP) is a hardware and software platform that provides a means to communicate from the PC to Analog • I/Q modulator with integrated fractional-N PLL and VCO Devices products and systems that require digital control and/or • Connector to interface to a standard USB interface board readback (see Figure 71). (SPD-S) that must be ordered with the EVAL-ADRF6755SDZ board. The SDP-S controller board connects to the PC via USB 2.0 and • DC biasing and filter circuitry for the baseband inputs to the ADRF6755 evaluation board via a small footprint, 120-pin connector. The SDP-S (serial only interface) is a low cost, small • Low-pass loop filter circuitry form factor, SDP controller board. • An 80 MHz reference clock • Circuitry to monitor the LOMON outputs Baseband Inputs • SMA connectors for power supplies and the RF output The pair of I and Q baseband inputs are served by SMA inputs (J2 to J5) so that they can be driven directly from an external The evaluation board is supplied with the associated driver generator or a DAC board, both of which can also provide the software to allow easy programming of the ADRF6755. dc bias required. There is also an option to filter the baseband HARDWARE DESCRIPTION inputs, although filtering may not be required, depending on For more information, refer to the circuit diagram in Figure 70. the quality of the baseband source. Power Supplies Loop Filter An external 5 V supply, DUT +5 V (J14), drives both an on-chip A fourth-order loop filter is provided at the output of the charge 3.3 V regulator and the quadrature modulator. pump and is required to adequately filter noise from the Σ-Δ modulator used in the N-divider. With the charge pump current The regulator feeds the VREG1 through VREG6 pins on the set to a value of 5 mA and using the on-chip VCO, the loop chip with 3.3 V. These pins power the PLL circuitry. bandwidth is approximately 100 kHz, and the phase margin is The external reference clock generator should be driven by a 55°. C0G capacitors are recommended for use in the loop filter 3.3 V supply. This supply should be connected via an SMA because they have low dielectric absorption, which is required connector, OSC +V (J15). for fast and accurate settling time. The use of non-C0G capacitors Recommended Decoupling for Supplies may result in a long tail being introduced into the settling time transient. The external DUT +5 V supply is decoupled initially by a 10 µF capacitor and then further by a parallel combination of 100 nF Reference Input and 10 pF capacitors that are placed as close to the DUT as The reference input can be supplied by an 80 MHz Jauch clock possible for good local decoupling. The regulator output should generator or by an external clock through the use of Connector be decoupled by a parallel combination of 10 pF and 220 µF REFIN (J7). The frequency range of the PFD input is from 10 MHz capacitors. The 220 µF capacitor decouples broadband noise, to 40 MHz; if the 80 MHz clock generator is used, the on-chip 5-bit which leads to better phase noise and is recommended for best reference frequency divider or the divide-by-2 divider should be performance. Case Size C 220 µF capacitors are used to minimize used to set the PFD frequency to 40 MHz to optimize phase noise area. Place a parallel combination of 100 nF and 10 pF capacitors performance. on each VREGx pin, as close to the pins as possible. The impedance LOMON Outputs of these capacitors should be low and constant across a broad frequency range. Surface-mount multilayered ceramic chip These pins are differential LO monitor outputs that provide a (MLCC) Class II capacitors provide very low ESL and ESR, which replica of the internal LO frequency at 1× LO. The single-ended assist in decoupling supply noise effectively. They also provide power in a 50 Ω load can be programmed to −24 dBm, −18 dBm, good temperature stability and good aging characteristics. −12 dBm, or −6 dBm. These open-collector outputs must be terminated to 3.3 V. Because both outputs must be terminated Capacitance also changes vs. applied bias voltage. Larger case to 50 Ω, options are provided to terminate to 3.3 V using on- sizes have less capacitance change vs. applied bias voltage and board 50 Ω resistors or by series inductors (or a ferrite bead), have lower ESR but higher ESL. The 0603 size capacitors provide a in which case the 50 Ω termination is provided by the measuring good compromise. X5R and X7R capacitors are examples of instrument. If not used, these outputs should be tied to REGOUT. these types of capacitors and are recommended for decoupling. Rev. B | Page 37 of 48

ADRF6755 Data Sheet CCOMPx Pins Lock Detect (LDET) The CCOMPx pins are internal compensation nodes that must Lock detect is a CMOS output that indicates the state of the be decoupled to ground with a 100 nF capacitor. PLL. A high level indicates a locked condition, and a low level MUXOUT indicates a loss of lock condition. TXDIS MUXOUT is a test output that allows different internal nodes to be monitored. It is a CMOS output stage that requires no This input disables the RF output. It can be driven from an external termination. stimulus or simply connected high or low by Jumper J18. RF Output (RFOUT) RFOUT (J12) is the RF output of the ADRF6755. Rev. B | Page 38 of 48

Data Sheet ADRF6755 170-56401 Figure 70. Applications Circuit Schematic Rev. B | Page 39 of 48

ADRF6755 Data Sheet 10465-078 Figure 71. Applications Circuit Schematic—SDP-S Rev. B | Page 40 of 48

Data Sheet ADRF6755 PCB ARTWORK Component Placement 10465-072 Figure 72. Evaluation Board, Top Side Component Placement 10465-073 Figure 73. Evaluation Board, Bottom Side Component Placement Rev. B | Page 41 of 48

ADRF6755 Data Sheet PCB Layer Information 10465-074 Figure 74. Evaluation Board, Top Side—Layer 1 10465-075 Figure 75. Evaluation Board, Bottom Side—Layer 4 Rev. B | Page 42 of 48

Data Sheet ADRF6755 10465-076 Figure 76. Evaluation Board, Ground—Layer 2 10465-077 Figure 77. Evaluation Board Power—Layer 3 Rev. B | Page 43 of 48

ADRF6755 Data Sheet BILL OF MATERIALS Table 29. Bill of Materials Qty Reference Designator Description Manufacturer Part Number 1 DUT ADRF6755, 56-lead 8 mm × 8 mm LFCSP Analog Devices ADRF6755ACPZ 1 Y2 Crystal Oscillator, 80 MHz Jauch O 80.0-JO75-B-3.3-2-T1 1 CONN1 Connector, FX8-120S-SV(21) Hirose FEC 1324660 2 C1, C21 Capacitor, 10 µF, 25 V, tantalum, TAJ-C AVX FEC 197518 12 C4, C6, C8, C10, C12, C14, C16, Capacitor, 10 pF, 50 V, ceramic, C0G, 0402 Murata FEC 8819564 C18, C19, C48, C53, C55 14 C5, C7, C9, C11, C13, C15, C17, Capacitor, 100 nF, 25 V, X7R, ceramic, 0603 AVX FEC 317287 C22, C47, C49 to C52, C54 1 C20 Capacitor, 220 µF, 6.3 V, tantalum, Case Size C AVX FEC 197087 4 C30 to C33 Capacitor spacing, 0402 (do not install) 1 C26 Capacitor, 1.2 nF, 50 V, C0G, ceramic, 0603 Kemet FEC 1813421 1 C24 Capacitor, 47 nF, 50 V, C0G, ceramic, 1206 Murata FEC 8820201 2 C23, C25 Capacitor, 560 pF, 50 V, NP0, ceramic, 0603 Murata FEC 1828912 2 C38, C39 Capacitor, 1 nF, 50 V, C0G, ceramic, 0402 Murata FEC 8819556 3 C44, C46, C57 Capacitor, 100 pF, 50 V, C0G, ceramic, 0402 Murata FEC 8819572 11 J2 to J5, J7, J10 to J12, J14, J15, TXDIS SMA end launch connector Johnson/Emerson 142-0701-851 2 J18, J21 Jumper, 3-pin + shunt Harwin FEC 148533 and FEC 150411 2 L1, L2 Inductor, 20 nH, 0402, 5% TE Connectivity FEC 1265424 2 L3, L4 Inductor, 10 µH, 0805, LQM series Vishay FEC 1653752 5 R6 to R9, R36 Resistor, 0 Ω, 1/16 W, 1%, 0402 Multicomp FEC 1357983 2 R10, R11 Resistor, 0402, spacing (do not install) 1 R13 Resistor, 4.7 kΩ, 1/10 W, 1%, 0603 Bourns FEC 2008358 2 R12, R16 Resistor, 160 Ω, 1/16 W, 1%, 0603 Multicomp FEC 9330658 1 R15 Resistor, 150 Ω, 1/16 W, 1%, 0603 Multicomp FEC 9330593 2 R62 Resistor, 0603, spacing (do not install) 3 R35, R44, R45 Resistor, 51 Ω, 1/16 W, 5%, 0402 Bourns FEC 2008358 4 R48 to R51 Resistor, 330 Ω, 1/10 W, 5%, 0805 Vishay FEC 1739223 3 R59 to R61 Resistor, 100 Ω, 1/10 W, 5%, 0805 Vishay FEC 1652907 2 R63, R64 Resistor, 100 kΩ, 1/16 W, 1%, 0603 Multicomp FEC 9330402 1 D1 LED, red, 0805, 1.8 V, low current Rohm FEC 1685056 1 U1 IC 24LC32A-I/MS EEPROM MSOP-8 Microchip FEC 133-4660 Rev. B | Page 44 of 48

Data Sheet ADRF6755 OUTLINE DIMENSIONS 8.10 0.60 MAX 0.30 8.00 SQ 0.23 7.90 0.60 0.18 MAX PIN 1 43 56 INDICATOR 42 1 PIN 1 0.50 INDICATOR BSC 7.85 7.75 SQ EXPOSED 6.65 PAD 7.65 6.50 SQ 6.35 29 14 TOP VIEW 00..5400 28 BOTTOM VIEW 15 0.20 MIN 0.30 6.50 REF 0.80 MAX 1.00 12° MAX 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.80 0.05 MAX THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SIDE VIEW COPLANARITY SECTION OF THIS DATA SHEET. SEPALTAINNGE COMPLIANTT0O.2 0J ERDEEFC STA0N.0D8ARDS MO-220-VLLD-2 06-11-2012-A Figure 78. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 mm × 8 mm Body, Very Thin Quad (CP-56-4) Dimensions shown in millimeters ORDERING GUIDE Package Model1, 2 Temperature Range Package Description Option ADRF6755ACPZ −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Tray CP-56-4 ADRF6755ACPZ-R7 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7" Tape and Reel CP-56-4 EVAL-ADRF6755SDZ Evaluation Board EVAL-SDP-CS1Z SDP-S Controller Board; Interface to EVAL-ADRF6755SDZ (also required) EVAL-SDP-CB1Z SDP-B Controller Board; Interface to EVAL-ADRF6755SDZ (alternative solution) 1 Z = RoHS Compliant Part. 2 Choose either EVAL-SDP-CS1Z or EVAL-SDP-CB1Z as EVAL-ADRF6755SDZ interface solution. Rev. B | Page 45 of 48

ADRF6755 Data Sheet NOTES Rev. B | Page 46 of 48

Data Sheet ADRF6755 NOTES Rev. B | Page 47 of 48

ADRF6755 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10465-0-4/13(B) Rev. B | Page 48 of 48

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