1000 MHz to 3100 MHz Rx Mixer with Integrated Fractional-N PLL and VCO Data Sheet ADRF6602 FEATURES The PLL can support input reference frequencies from 12 MHz to 160 MHz. The PFD output controls a charge pump whose Rx mixer with integrated fractional-N PLL output drives an off-chip loop filter. RF input frequency range: 1000 MHz to 3100 MHz Internal LO frequency range: 1550 MHz to 2150 MHz The loop filter output is then applied to an integrated VCO. The Input P1dB: 14.8 dBm VCO output at 2× f is applied to an LO divider, as well as to a LO Input IP3: 30 dBm programmable PLL divider. The programmable PLL divider is IIP3 optimization via external pin controlled by a Σ-Δ modulator (SDM). The modulus of the SDM SSB noise figure can be programmed from 1 to 2047. IP3SET pin open: 13.8 dB The active mixer converts the single-ended 50 Ω RF input to IP3SET pin at 3.3 V: 15 dB a 200 Ω differential IF output. The IF output can operate up Voltage conversion gain: 6.5 dB to 500 MHz. Matched 200 Ω IF output impedance IF 3 dB bandwidth: 500 MHz The ADRF6602 is fabricated using an advanced silicon-germanium Programmable via 3-wire SPI interface BiCMOS process. It is available in a 40-lead, RoHS-compliant, 40-lead, 6 mm × 6 mm LFCSP 6 mm × 6 mm LFCSP with an exposed paddle. Performance is specified over the −40°C to +85°C temperature range. APPLICATIONS Table 1. Cellular base stations Internal LO ±3 dB RF ±1 dB RF IN IN GENERAL DESCRIPTION Part No. Range Balun Range Balun Range The ADRF6602 is a high dynamic range active mixer with ADRF6601 750 MHz 300 MHz 450 MHz integrated phase-locked loop (PLL) and voltage controlled 1160 MHz 2500 MHz 1600 MHz oscillator (VCO). The PLL/synthesizer uses a fractional-N ADRF6602 1550 MHz 1000 MHz 1350 MHz PLL to generate a f input to the mixer. The reference input 2150 MHz 3100 MHz 2750 MHz LO can be divided or multiplied and then applied to the PLL phase ADRF6603 2100 MHz 1100 MHz 1450 MHz frequency detector (PFD). 2600 MHz 3200 MHz 2850 MHz ADRF6604 2500 MHz 1200 MHz 1600 MHz 2900 MHz 3600 MHz 3200 MHz FUNCTIONAL BLOCK DIAGRAM VCC1 VCC2 VCC_LO VCC_MIX VCC_V2I VCC_LO NC NC 1 10 17 22 27 34 32 33 ADRF6602 LODRV_EN 36 LON 37 I1N5T5E0MRNHAz LT OLO 2 1R5A0MNGHEz L3.D3OV 2 DECL3P3 BUFFER 2.5V LOP 38 LDO 9 DECL2P5 PLDLA_ETAN 1126 SPI FRARCETGION MODULUS INTREEGGER BUFFER M2U:1X 2DB,I YV1 VLDCOO 40 DECLVCO CLK 13 INTERFACE LE 14 THIRD-ORDER 26 RFIN FRACTIONAL INTERPOLATOR VCO ×2 N COUNTER PRESCALER CORE 29 IP3SET 21 TO 123 ÷2 REF_IN 6 ÷2 MUX CHARGE PUMP – PHASE 250µA, ÷4 TEMP + FREQUENCY 500µA (DEFAULT), SENSOR DETECTOR 750µA, MUXOUT 8 1000µA 4 7 11 15 20 21G2N3D24 25 28 30 31 35 RS5ET C3P VT3U9NE IF1P8 1IF9N 08545-001 Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2010–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADRF6602 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register 3—Σ-Δ Modulator Dither Control (Default: Applications ....................................................................................... 1 0x10000B) .................................................................................... 17 General Description ......................................................................... 1 Register 4—PLL Charge Pump, PFD, and Reference Path Control (Default: 0x0AA7E4) ................................................... 18 Functional Block Diagram .............................................................. 1 Register 5—PLL Enable and LO Path Control (Default: Revision History ............................................................................... 2 0x0000E5) .................................................................................... 19 Specifications ..................................................................................... 3 Register 6—VCO Control and VCO Enable (Default: RF Specifications .......................................................................... 3 0x1E2106) .................................................................................... 19 Synthesizer/PLL Specifications ................................................... 4 Register 7—Mixer Bias Enable and External VCO Enable Logic Input and Power Specifications ....................................... 4 (Default: 0x000007) .................................................................... 19 Timing Characteristics ................................................................ 5 Theory of Operation ...................................................................... 20 Absolute Maximum Ratings ............................................................ 6 Programming the ADRF6602 ................................................... 20 ESD Caution .................................................................................. 6 Initialization Sequence .............................................................. 20 Pin Configuration and Function Descriptions ............................. 7 LO Selection Logic ..................................................................... 21 Typical Performance Characteristics ............................................. 9 Applications Information .............................................................. 22 RF Frequency Sweep .................................................................... 9 Basic Connections for Operation ............................................. 22 IF Frequency Sweep ................................................................... 10 AC Test Fixture ............................................................................... 23 Spurious Performance................................................................ 15 Evaluation Board ............................................................................ 24 Register Structure ........................................................................... 16 Evaluation Board Control Software ......................................... 24 Register 0—Integer Divide Control (Default: 0x0001C0)..... 16 Schematic and Artwork ............................................................. 26 Register 1—Modulus Divide Control (Default: 0x003001) .. 16 Evaluation Board Configuration Options ............................... 28 Register 2—Fractional Divide Control (Default: 0x001802) 17 Outline Dimensions ....................................................................... 29 Ordering Guide .......................................................................... 29 REVISION HISTORY 10/13—Rev. C to Rev. D Changes to Figure 20 ...................................................................... 14 Changed “1550 MHz to 2150 MHz” to “1000 MHz to Changes to Figure 21 ...................................................................... 17 3100 MHz” in Product Title ............................................................ 1 Changes to Figure 22 ...................................................................... 18 Updated Outline Dimensions ....................................................... 29 Changes to Figure 23 ...................................................................... 19 9/10—Rev. B to Rev. C 4/10—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Added Table 1 .................................................................................... 1 Changes to Table 2 ............................................................................ 3 Changes to Figure 1 ........................................................................... 1 Changes to Table 3 and Table 4 ....................................................... 4 Change to Synthesizer/PLL Specifications Section ....................... 4 Changes to Table 6 ............................................................................ 6 Change to Table 3 .............................................................................. 4 Changes to Typical Performance Characteristics Section ........... 9 Changes to Initializing Sequence Section ................................... 15 Added Spurious Performance Section ......................................... 15 Changes to Figure 16 ...................................................................... 12 Changes to Programming the ADRF6602 Section .................... 20 Changes to Figure 17 ...................................................................... 13 Added AC Test Fixture Section and Figure 47 ........................... 23 Changes to Figure 19 ...................................................................... 14 Changes to Evaluation Board Control Software Section ........... 24 Changes to Figure 21 ...................................................................... 17 Changes to Figure 24 ...................................................................... 20 7/10—Rev. A to Rev. B Changes to Table 1 ............................................................................ 1 1/10—Revision 0: Initial Version Changes to Table 6 ............................................................................ 6 Rev. D | Page 2 of 32

Data Sheet ADRF6602 SPECIFICATIONS RF SPECIFICATIONS V = 5 V; ambient temperature (T ) = 25°C; f = 153.6 MHz; f = 38.4 MHz; high-side LO injection; f = 140 MHz; IIP3 optimized S A REF PFD IF using CDAC (0x0) and IP3SET (3.3 V), unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit INTERNAL LO FREQUENCY RANGE 1550 2150 MHz RF INPUT FREQUENCY RANGE ±3 dB RF input range 1000 3100 MHz RF INPUT AT 1410 MHz Input Return Loss Relative to 50 Ω (can be improved with external match) −9 dB Input P1dB 15.5 dBm Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 54.0 dBm Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 33.5 dBm Single-Side Band Noise Figure IP3SET = 3.3 V 15.2 dB IP3SET = open 14.1 dB LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −45 dBm RF INPUT AT 1760 MHz Input Return Loss Relative to 50 Ω (can be improved with external match) −15 dB Input P1dB 15 dBm Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 53.5 dBm Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 30.8 dBm Single-Side Band Noise Figure IP3SET = 3.3 V 14.9 dB IP3SET = open 13.5 dB LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −43 dBm RF INPUT AT 2010 MHz Input Return Loss Relative to 50 Ω (can be improved with external match) <(−20) dB Input P1dB 14.8 dBm Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 60 dBm Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 29.5 dBm Single-Side Band Noise Figure IP3SET = 3.3 V 15.8 dB IP3SET = open 14.9 dB LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −45 dBm IF OUTPUT Voltage Conversion Gain Differential 200 Ω load 6.5 dB IF Bandwidth Small signal 3 dB bandwidth 500 MHz Output Common-Mode Voltage External pull-up balun or inductors required 5 V Gain Flatness Over frequency range, any 5 MHz/50 MHz 0.2/0.5 dB Gain Variation Over full temperature range 1.2 dB Output Swing Differential 200 Ω load 2 V p-p Differential Output Return Loss Measured through 4:1 balun −12 dB LO INPUT/OUTPUT (LOP, LON) Externally applied 1× LO input, internal PLL disabled Frequency Range 250 6000 MHz Output Level (LO as Output) 1× LO into a 50 Ω load, LO output buffer enabled −7 dBm Input Level (LO as Input) −6 0 +6 dBm Input Impedance 50 Ω Rev. D | Page 3 of 32

ADRF6602 Data Sheet SYNTHESIZER/PLL SPECIFICATIONS V = 5 V; ambient temperature (T ) = 25°C; f = 153.6 MHz; f power = 4 dBm; f = 38.4 MHz; high-side LO injection; S A REF REF PFD f = 140 MHz; IIP3 optimized using CDAC (0x0) and IP3SET (3.3 V), unless otherwise noted. IF Table 3. Parameter Test Conditions/Comments Min Typ Max Unit SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to 1× LO Frequency Range Internally generated LO 1550 2150 MHz Figure of Merit1 P = 0 dBm −220.5 dBc/Hz REF_IN Reference Spurs f = 38.4 MHz PFD f /4 −105 dBc PFD f −80 dBc PFD >f −80 dBc PFD PHASE NOISE f = 1550 MHz to 2150 MHz, f = 38.4 MHz LO PFD 1 kHz to 10 kHz offset −92 dBc/Hz 100 kHz offset −103 dBc/Hz 500 kHz offset −122 dBc/Hz 1 MHz offset −128 dBc/Hz 5 MHz offset −140 dBc/Hz 10 MHz offset −147 dBc/Hz 20 MHz offset −150 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth 0.3 °rms PFD Frequency 20 40 MHz REFERENCE CHARACTERISTICS REF_IN, MUXOUT pins REF_IN Input Frequency 12 160 MHz REF_IN Input Capacitance 4 pF MUXOUT Output Level V (lock detect output selected) 0.25 V OL V (lock detect output selected) 2.7 V OH MUXOUT Duty Cycle 50 % CHARGE PUMP Pump Current Programmable to 250 µA, 500 µA, 750 µA, 1 mA 500 µA Output Compliance Range 1 2.8 V 1 The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10Log10(fPFD) – 20Log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 80 MHz, fREF power = 10 dBm (500 V/µs slew rate) with a 40 MHz fPFD. The FOM was computed at 50 kHz offset. LOGIC INPUT AND POWER SPECIFICATIONS V = 5 V; ambient temperature (T ) = 25°C; f = 153.6 MHz; f = 38.4 MHz; high-side LO injection; f = 140 MHz; IIP3 optimized S A REF PFD IF using CDAC (0x0) and IP3SET (3.3 V), unless otherwise noted. Table 4. Parameter Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS CLK, DATA, LE Input High Voltage, V 1.4 3.3 V INH Input Low Voltage, V 0 0.7 V INL Input Current, I /I 0.1 µA INH INL Input Capacitance, C 5 pF IN POWER SUPPLIES VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins Voltage Range 4.75 5 5.25 V Supply Current PLL only 97 mA External LO mode (internal PLL disabled, LO output buffer off, IP3SET pin = 3.3 V) 168 mA Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer on) 277 mA Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer off) 263 mA Power-down mode 30 mA Rev. D | Page 4 of 32

Data Sheet ADRF6602 TIMING CHARACTERISTICS VCC2 = 5 V ± 5%. Table 5. Parameter Limit Unit Description t 20 ns min LE setup time 1 t 10 ns min DATA-to-CLK setup time 2 t 10 ns min DATA-to-CLK hold time 3 t 25 ns min CLK high duration 4 t 25 ns min CLK low duration 5 t 10 ns min CLK-to-LE setup time 6 t 20 ns min LE pulse width 7 Timing Diagram t4 t5 CLK t2 t3 DB2 DB1 DB0(LSB) DATA DB23(MSB) DB22 (CONTROLBITC3) (CONTROLBITC2) (CONTROLBITC1) t1 t6 t7 LE 08545-002 Figure 2. Timing Diagram Rev. D | Page 5 of 32

ADRF6602 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 6. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Supply Voltage, VCC1, VCC2, VCC_LO, −0.5 V to +5.5 V rating only; functional operation of the device at these or any VCC_MIX, VCC_V2I other conditions above those indicated in the operational Digital I/O, CLK, DATA, LE −0.3 V to +3.6 V section of this specification is not implied. Exposure to absolute IFP, IFN −0.3 V to VCC_V2I + 0.3 V maximum rating conditions for extended periods may affect RFIN 16 dBm device reliability. LOP, LON 13 dBm θ (Exposed Paddle Soldered Down) 35°C/W JA Maximum Junction Temperature 150°C ESD CAUTION Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Rev. D | Page 6 of 32

Data Sheet ADRF6602 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS N O E C _ O VLCEDENUTVPOLNOLVRDOLDNGL_CCVCNCNDNG 0987654321 4333333333 VCC1 1 PIN 1 30GND DECL3P3 2 INDICATOR 29IP3SET CP 3 28GND GND 4 27VCC_V2I RSET 5 ADRF6602 26RFIN REF_IN 6 TOP VIEW 25GND GND 7 (Not to Scale) 24GND MUXOUT 8 23GND DECL2P5 9 22VCC_MIX VCC210 21GND 11213141516171819102 DAKEDNOPND NGTADLCLNGE_LL_CFIFING LPCV NOTES 12 .. NTLHOCE W= E NIXMOPP OCEOSDENADNNECPCAE DTG.DRLOEU SNHDO PULLADN BEE. SOLDEREDTO A 08545-003 Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1 VCC1 Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin. 2 DECL3P3 Decoupling Node for 3.3 V LDO. Connect a 0.1 µF capacitor between this pin and ground. 3 CP Charge Pump Output Pin. Connect to VTUNE through loop filter. 4, 7, 11, 15, 20, GND Ground. Connect these pins to a low impedance ground plane. 21, 23, 24, 25, 28, 30, 31, 35 5 R Charge Pump Current. The nominal charge pump current can be set to 250 µA, 500 µA, 750 µA, or 1 mA using SET Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 in Register 4 to 0 (internal reference current). In this mode, no external R is required. If Bit DB18 is set to 1, the four nominal charge pump currents (I ) SET NOMINAL can be externally adjusted according to the following equation: 217.4 × I  R =  CP  −37.8Ω SET  I  NOMINAL 6 REF_IN Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. 8 MUXOUT Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect signal. The output is selected by programming the appropriate register. 9 DECL2P5 Decoupling Node for 2.5 V LDO. Connect a 0.1 µF capacitor between this pin and ground. 10 VCC2 Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin. 12 DATA Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits. 13 CLK Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz. 14 LE Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the eight registers. The relevant latch is selected by the three control bits of the 24-bit word. 16 PLL_EN PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be used to switch modes. 17, 34 VCC_LO Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin. 18, 19 IFP, IFN Mixer IF Outputs. These outputs should be pulled to VCC with RF chokes. Rev. D | Page 7 of 32

ADRF6602 Data Sheet Pin No. Mnemonic Description 22 VCC_MIX Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin. 26 RF RF Input (Single-Ended, 50 Ω). IN 27 VCC_V2I Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin. 29 IP3SET Connect a resistor from this pin to a 5 V supply to adjust IIP3. Normally leave open. 32, 33 NC No Connection. 36 LODRV_EN LO Driver Enable. Together with Pin 16 (PLL_EN), this digital input pin determines whether the LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the PLL_EN pin is low or if the PLL_EN pin is set high with the PLEN bit (DB6 in Register 5) set to 0. LOP and LON become outputs if either the LODRV_EN pin or the LDRV bit (DB3 in Register 5) is set to 1 while the PLL_EN pin is set high. External LO drive frequency must be 1× LO. This pin should not be left floating. 37, 38 LON, LOP Local Oscillator Input/Output. The internally generated 1× LO is available on these pins. When internal LO generation is disabled, an external 1× LO can be applied to these pins. 39 VTUNE VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal input voltage range on this pin is 1.5 V to 2.5 V. 40 DECLVCO Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 µF capacitor between this pin and ground. EPAD Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane. Rev. D | Page 8 of 32

Data Sheet ADRF6602 TYPICAL PERFORMANCE CHARACTERISTICS RF FREQUENCY SWEEP CDAC = 0x0, internally generated high-side LO, RF = −5 dBm, f = 140 MHz, unless otherwise noted. IN IF 5 45 IP3SET = OPEN TA = +85°C IP3SET = OPEN TA = +85°C 4 IP3SET = 3.3V TA = +25°C IP3SET = 3.3V TA = +25°C TA = –40°C TA = –40°C 3 40 2 m) B) 1 dB 35 N (d 0 P3 ( AI T I G –1 PU 30 N I –2 –3 25 –4 –15410 1510 16R1F0 FREQ1U7E1N0CY (M1H8z1)0 1910 2010 08545-104 210410 1510 16R1F0 FREQ1U7E1N0CY (M1H8z1)0 1910 2010 08545-107 Figure 4. Gain vs. RF Frequency Figure 7. Input IP3 vs. RF Frequency 90 20 IP3SET = OPEN TA = +85°C IP3SET = OPEN TA = +85°C IP3SET = 3.3V TA = +25°C 19 IP3SET = 3.3V TA = +25°C 80 TA = –40°C TA = –40°C 18 17 m) 70 Bm) B d 16 UT IP2 (d 60 T P1dB ( 15 P U 14 N P I 50 N I 13 12 40 11 310410 1510 16R1F0 FREQ1U7E1N0CY (M1H8z1)0 1910 2010 08545-105 110410 1510 16R1F0 FREQ1U7E1N0CY (M1H8z1)0 1910 2010 08545-108 Figure 5. Input IP2 vs. RF Frequency Figure 8. Input P1dB vs. RF Frequency 2109 IP3SET = OPEN 18 IP3SET = 3.3V 17 16 15 B) 14 d 13 E ( 12 UR 11 G 10 E FI 9 S 8 OI 7 N 6 5 4 3 TA = +85°C 2 TA = +25°C 1 TA = –40°C 10410 1510 16R1F0 FREQ1U7E1N0CY (M1H8z1)0 1910 2010 08545-106 Figure 6. Noise Figure vs. RF Frequency Rev. D | Page 9 of 32

ADRF6602 Data Sheet IF FREQUENCY SWEEP CDAC = 0x0, internally generated swept low-side LO, f = 1960 MHz, RF = −5 dBm, unless otherwise noted. RF IN 5 45 IP3SET = OPEN TA = +85°C IP3SET = OPEN TA = +85°C 4 IP3SET = 3.3V TA = +25°C IP3SET = 3.3V TA = +25°C TA = –40°C 40 TA = –40°C 3 35 2 B) 1 dBm) 30 N (d 0 P3 ( 25 AI T I G –1 NPU 20 I –2 15 –3 10 –4 –525 50 75 10012515IF0 F1R75EQ20U0E2N2C5Y2 (5M0H2z7)5300325350375400 08545-110 525 50 75 10012515IF0 F1R75EQ20U0E2N2C5Y2 (5M0H2z7)5300325350375400 08545-113 Figure 9. Gain vs. IF Frequency Figure 12. Input IP3 vs. IF Frequency, RFIN = −5 dBm 90 20 IP3SET = OPEN TA = +85°C IP3SET = OPEN TA = +85°C IP3SET = 3.3V TA = +25°C 18 IP3SET = 3.3V TA = +25°C 80 TA = –40°C TA = –40°C 16 14 m) 70 Bm) B d 12 UT IP2 (d 60 T P1dB ( 10 P U 8 N P I 50 N I 6 4 40 2 3025 50 75 10012515IF0 F1R75EQ20U0E2N2C5Y2 (5M0H2z7)5300325350375400 08545-111 025 50 75 10012515IF0 F1R75EQ20U0E2N2C5Y2 (5M0H2z7)5300325350375400 08545-114 Figure 10. Input IP2 vs. IF Frequency, RFIN = −5 dBm Figure 13. Input P1dB vs. IF Frequency 20 IP3SET = OPEN 18 IP3SET = 3.3V 16 B) 14 d E ( 12 R U G 10 FI E S 8 OI N 6 4 TA = +85°C 2 TA = +25°C TA = –40°C 025 50 75 10012515IF0 F1R75EQ20U0E2N2C5Y2 (5M0H2z7)5300325350375400 08545-112 Figure 11. Noise Figure vs. IF Frequency Rev. D | Page 10 of 32

Data Sheet ADRF6602 0 0 IP3SET = OPEN TA = +85°C –5 IP3SET = 3.3V TA = +25°C –2 m) –10 TA = –40°C –4 dB –15 ROUGH ( ––2250 SS (dB) ––86 H O T –30 L –10 O-IF FEED ––4305 RETURN ––1142 O-T –45 L –16 –50 –55 –18 –610550 1650 17L5O0 FREQ1U8E5N0CY (M1H9z5)0 2050 2150 08545-115 –210400 1500 1600 17L0O0 FR1E8Q00UEN19C0Y0 (M2H0z0)0 2100 2200 2300 08545-117 Figure 14. LO-to-IF Feedthrough vs. LO Frequency, Figure 17. LO Input Return Loss vs. LO Frequency (Including TC1-1-13 Balun) LO Output Turned Off, CDAC = 0x0 –30 350 3.5 IP3SET = OPEN TA = +85°C IP3SET = 3.3V TA = +25°C –40 TA = –40°C 300 3.0 m) RESISTANCE B 250 2.5 TO-RF LEAKAGE (d –––567000 RESISTANCE (Ω) 125000 CAPACITANCE 12..50 CAPACITANCE (pF) O- 100 1.0 L –80 50 0.5 –910550 1650 17L5O0 FREQ1U8E5N0CY (M1H9z5)0 2050 2150 08545-109 050 100 150 20IF0 FRE25Q0UEN3C0Y0 (MH3z5)0 400 450 5000 08545-118 Figure 15. LO-to-RF Leakage vs. LO Frequency, LO Output Turned Off Figure 18. IF Differential Output Impedance (R Parallel C Equivalent) 0 35 IP3SET = OPEN IP3SET = 3.3V –10 30 –20 B) B) S (d –30 E (d 25 S R O U L –40 G N FI ETUR –50 OISE 20 R N –60 15 –70 –810400 1500 1600 17R0F0 FR1E8Q00UEN19C0Y0 (M2H0z0)0 2100 2200 2300 08545-116 10–60 –50 CW–4 B0LOCKE–R3 0LEVEL (–d2B0m) –10 0 08545-200 Figure 16. RF Input Return Loss vs. RF Frequency Figure 19. SSB Noise Figure vs. 5 MHz Offset Blocker Level, LO Frequency = 2105 MHz, RF Frequency = 1965 MHz Rev. D | Page 11 of 32

ADRF6602 Data Sheet 0 5.0 IP3SET = OPEN TA = +85°C TA = +85°C –5 IP3SET = 3.3V TA = +25°C 4.5 TA = +25°C –10 TA = –40°C TA = –40°C 4.0 c) –15 B TION (d ––2250 AGE (V) 33..50 A T OL –30 OL 2.5 S V F-TO-IF I ––4305 VTUNE 21..05 R –45 1.0 –50 –55 0.5 –610300 1500 RF1 F7R00EQUENCY19 (0M0Hz) 2100 2300 08545-119 10550 1650 17L5O0 FREQ1U8E5N0CY (M1H9z5)0 2050 2150 08545-122 Figure 20. RF-to-IF Leakage vs. RF Frequency, High-Side LO, IF = 140 MHz, Figure 23. VTUNE vs. LO Frequency LO Output Turned Off 0 350 IP3SET = OPEN TA = +85°C IP3SET = OPEN TA = +85°C –1 IP3SET = 3.3V TA = +25°C IP3SET = 3.3V TA = +25°C TA = –40°C TA = –40°C m) –2 300 B E (d –3 mA) MPLITUD ––45 URRENT ( 250 A C PUT –6 PLY 200 UT –7 UP O S O L –8 150 –9 –110550 1650 17L5O0 FREQ1U8E5N0CY (M1H9z5)0 2050 2150 08545-120 1010550 1650 17L5O0 FREQ1U8E5N0CY (M1H9z5)0 2050 2150 08545-123 Figure 21. LO Output Amplitude vs. LO Frequency Figure 24. Supply Current vs. LO Frequency 20 2.0 MHz) 1.9 IIPP33SSEETT == O3.P3VEN MHz ( 15 1.8 60 10 19 V) 1.7 ON FROM 05 OLTAGE ( 11..56 Y DEVIATI –5 VPTAT V 11..34 C –10 EN 1.2 U Q –15 E 1.1 R F –200 50 100TIME (ns)150 200 250 08545-222 1.0–55 –35 –15 TE5MPERA25TURE (4°5C) 65 85 105 08545-124 Figure 22. Frequency Deviation from LO Frequency at Figure 25. VPTAT Voltage vs. Temperature (IP3SET = Optimized, Open) LO = 1.97 GHz to 1.96 GHz vs. Lock Time Rev. D | Page 12 of 32

Data Sheet ADRF6602 Complementary cumulative distribution function (CCDF), f = 1960 MHz, f = 140 MHz. RF IF 100 100 IP3SET = OPEN IP3SET = OPEN 90 IP3SET = 3.3V 90 IP3SET = 3.3V %) 80 %) 80 E ( E ( G G A 70 A 70 T T N N E 60 E 60 C C R R PE 50 PE 50 N N TIO 40 TIO 40 U U RIB 30 RIB 30 T T DIS 20 DIS 20 TA = +85°C TA = +85°C 10 TA = +25°C 10 TA = +25°C TA = –40°C TA = –40°C 0–1.5 –1.0 –0.5 0 GAI0N.5 (dB) 1.0 1.5 2.0 2.5 08545-125 020 22 24 2I6NPUT I2P83 (dBm3)0 32 34 36 08545-128 Figure 26. Gain Figure 29. Input IP3 100 100 IP3SET = OPEN IP3SET = OPEN 90 IP3SET = 3.3V 90 IP3SET = 3.3V %) 80 %) 80 E ( E ( G G A 70 A 70 T T N N E 60 E 60 C C R R PE 50 PE 50 N N TIO 40 TIO 40 U U RIB 30 RIB 30 T T DIS 20 DIS 20 TA = +85°C TA = +85°C 10 TA = +25°C 10 TA = +25°C TA = –40°C TA = –40°C 040 45 50 5I5NPUT I6P02 (dBm6)5 70 75 80 08545-126 09 10 11 12INPU1T3 P1dB1 4(dBm)15 16 17 18 08545-129 Figure 27. Input IP2 Figure 30. Input P1dB 100 100 IP3SET = OPEN IP3SET = OPEN 90 90 IP3SET = 3.3V %) 80 %) 80 E ( E ( G G A 70 A 70 T T N N E 60 E 60 C C R R PE 50 PE 50 N N TIO 40 TIO 40 U U RIB 30 RIB 30 T T DIS 20 DIS 20 TA = +85°C TA = +85°C 10 TA = +25°C 10 TA = +25°C TA = –40°C TA = –40°C 011 12 13 NOIS1E4 FIGUR1E5 (dB) 16 17 18 08545-127 0–55 –53 –51 –4L9O FE–4E7DTH–R4O5UG–H4 3(dB–m4)1 –39 –37 –35 08545-130 Figure 28. Noise Figure Figure 31. LO Feedthrough to IF, LO Output Turned Off Rev. D | Page 13 of 32

ADRF6602 Data Sheet Measured at IF output, CDAC = 0x0, IP3SET = open, internally generated high-side LO, f = 153.6 MHz, f = 38.4 MHz, REF PFD RF = −5 dBm, f = 140 MHz, unless otherwise noted. Phase noise measurements made at LO output, unless otherwise noted. IN IF –80 1.0 LO FREQUENCY = 2134.4MHz TA = +85°C TA = +85°C TA = +25°C 0.9 TA = +25°C –90 TA = –40°C s) TA = –40°C m 0.8 Hz) –100 SE (°r 0.7 E (dBc/ –110 SE NOI 0.6 OIS –120 HA 0.5 PHASE N ––114300 LO FREQUENCY = 1558.4MHz EGRATED P 00..43 NT 0.2 I –150 0.1 –1601k 10k OFFS1E00Tk FREQUEN1MCY (Hz) 10M 100M 08545-131 10550 1650 17L5O0 FREQ1U8E5N0CY (M1H9z5)0 2050 2150 08545-133 Figure 32. Phase Noise vs. Offset Frequency Figure 35. Integrated Phase Noise vs. LO Frequency –75 –80 2× PFD FREQUENCY TA = +85°C TA = +85°C 4× PFD FREQUENCY TA = +25°C TA = +25°C –80 TA = –40°C –90 TA = –40°C –100 VEL (dBc) ––9805 E (dBc/Hz) –110 OFFSET = 1kHz SPURRS LE –1–0905 PHASE NOIS ––112300 OFFSET = 100kHz –140 OFFSET = 5MHz –105 –150 –1110550 1650 17L5O0 FREQ1U8E5N0CY (M1H9z5)0 2050 2150 08545-132 –1610550 1650 17L5O0 FREQ1U8E5N0CY (M1H9z5)0 2050 2150 08545-134 Figure 33. PLL Reference Spurs vs. LO Frequency (2× PFD and 4× PFD) Figure 36. Phase Noise vs. LO Frequency (1 kHz, 100 kHz, and 5 MHz Steps) –75 –80 –80 31×× PPFFDD FFRREEQQUUEENNCCYY TTTAAA === –++428055°°°CCC –90 TTTAAA === –++428055°°°CCC –100 VEL (dBc) ––9805 E (dBc/Hz) –110 OFFSET = 10kHz SPURRS LE –1–0905 PHASE NOIS ––112300 –140 0.25× PFD FREQUENCY OFFSET = 1MHz –105 –150 –1110550 1650 17L5O0 FREQ1U8E5N0CY (M1H9z5)0 2050 2150 08545-232 –1610550 1650 17L5O0 FREQ1U8E5N0CY (M1H9z5)0 2050 2150 08545-135 Figure 34. PLL Reference Spurs vs. LO Frequency (0.25× PFD, 1× PFD, and 3× PFD) Figure 37. Phase Noise vs. LO Frequency (10 kHz, 1 MHz Steps) Rev. D | Page 14 of 32

Data Sheet ADRF6602 SPURIOUS PERFORMANCE (N × f ) − (M × f ) spur measurements were made using the standard evaluation board (see the Evaluation Board section). Mixer spurious RF LO products were measured in dB relative to the carrier (dBc) from the IF output power level. All spurious components greater than −125 dBc are shown. LO = 1550 MHz, RF = 1410 MHz (horizontal axis is m, vertical axis is n), and RF power = −10 dBm. IN M 0 1 2 3 4 0 −95.78 −36.11 −38.06 −43.03 1 −27.96 0.00 −75.14 −44.01 −81.04 2 −80.82 −84.22 −70.69 −83.52 −90.50 N 3 −105.61 −93.37 −112.15 −84.67 −121.89 4 −120.72 −121.95 −123.15 −120.95 −123.77 5 −122.11 −122.03 −122.97 −123.53 6 −122.02 −121.46 −122.62 7 −122.03 −121.44 LO = 1900 MHz, RF = 1760 MHz (horizontal axis is m, vertical axis is n), and RF power = −10 dBm. IN M 0 1 2 3 4 0 −96.17 −35.62 −23.14 −51.42 1 −23.66 0.00 −63.13 −40.94 −68.37 2 −69.90 −80.06 −71.05 −86.55 −95.26 N 3 −105.85 −107.79 −104.24 −78.66 −121.43 4 −122.72 −121.39 −122.69 −124.20 5 −122.78 −122.48 −117.55 6 −122.39 −123.67 7 −119.57 LO = 2150 MHz, RF = 2010 MHz (horizontal axis is m, vertical axis is n), and RF power = −10 dBm. IN M 0 1 2 3 4 0 −94.96 −36.89 −22.24 +9.56 +9.56 1 −21.91 0.00 −69.83 −31.34 +9.56 2 −76.22 −77.24 −75.74 −80.30 −87.09 N 3 −97.36 −101.06 −76.16 −121.60 4 −122.66 −122.37 −120.59 −125.16 5 −122.76 −121.11 −124.51 6 −122.63 −122.41 7 −122.93 Rev. D | Page 15 of 32

ADRF6602 Data Sheet REGISTER STRUCTURE This section provides the register maps for the ADRF6602. The three LSBs determine the register that is programmed. REGISTER 0—INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0) DIVIDE RESERVED MODE INTEGER DIVIDE RATIO CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM ID6 ID5 ID4 ID3 ID2 ID1 ID0 C3(0) C2(0) C1(0) DM DIVIDE MODE 0 FRACTIONAL (DEFAULT) 1 INTEGER ID6 ID5 ID4 ID3 ID2 ID1 ID0 INTEGER DIVIDE RATIO 0 0 1 0 1 0 1 21 (INTEGER MODE ONLY) 0 0 1 0 1 1 0 22 (INTEGER MODE ONLY) 0 0 1 0 1 1 1 23 (INTEGER MODE ONLY) 0 0 1 1 0 0 0 24 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1 1 1 0 0 0 56 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 1 0 1 1 1 119 1 1 1 1 0 0 0 120 (INTEGER MODE ONLY) 1 1 1 1 0 0 1 121 (INTEGER MODE ONLY) 11 11 11 11 00 11 10 112223 ((IINNTTEEGGEERR MMOODDEE OONNLLYY)) 08545-004 Figure 38. Register 0—Integer Divide Control Register Map REGISTER 1—MODULUS DIVIDE CONTROL (DEFAULT: 0x003001) RESERVED MODULUS VALUE CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1) MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 MODULUS VALUE 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 2 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 0 0 0 0 0 0 0 0 0 1536 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... .1.. .1.. .1.. .1.. .1.. .1.. .1.. .1.. .1.. .1.. .1.. .2.0.47 08545-005 Figure 39. Register 1—Modulus Divide Control Register Map Rev. D | Page 16 of 32

Data Sheet ADRF6602 REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802) RESERVED FRACTIONAL VALUE CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 C3(0) C2(1) C1(0) FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 FRACTIONAL VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1 1 0 0 0 0 0 0 0 0 768 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... ... ... FR.A..CTION..A.L VA.L..UE MU..S.T BE. .L.ESS T...HAN M..O.DULU...S ... .<.M. DR 08545-006 Figure 40. Register 2—Fractional Divide Control Register Map REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL (DEFAULT: 0x10000B) MADGITNHITEURDE EDNITAHBELRE DITHER RESTART VALUE CONTROL BITS DB23 DB22 DB21 DB20 DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 DITH1 DITH0 DEN DV16DV15DV14DV13DV12DV11DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0)C2(1)C1(1) DITH1 DITH0 DITHER MAGNITUDE 0 0 15 (DEFAULT) 0 1 7 1 0 3 1 1 1 (RECOMMENDED) DEN DITHER ENABLE 0 DISABLE 1 ENABLE (DEFAULT, RECOMMENDED) DV16 DV15DV14DV13DV12DV11DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 DVAITLHUEER RESTART 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0x00001 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1... 1... 1... 1... 1... 1... 1... 1... 1... 1... 1... 1... 1... 1... 1... 1... .1.. .0.x.1FFFF 08545-007 Figure 41. Register 3—Σ-Δ Modulator Dither Control Register Map Rev. D | Page 17 of 32

ADRF6602 Data Sheet REGISTER 4—PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL (DEFAULT: 0x0AA7E4) CP MREUFX OSUETLPEUCTT INPPUATT HREF CURRREEFNT PPOFDL PFDM PUHLATSIEP LOIEFRFSET CURCRPENT SCRPC CONCTPROL PFD EDGE BPAFCDK ALANSTHI CONTROL BITS SOURCE DELAY DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RMS2 RMS1 RMS0 RS1 RS0 CPM CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0) PAB0 PAB1 PFD ANTI BACKLASH DELAY 0 0 0ns (DEFAULT) 0 1 0.5ns 1 0 0.75ns 1 1 0.9ns PE0 REFERENCE PATH EDGE SENSITIVITY 0 FALLING EDGE (RECOMMENDED) 1 RISING EDGE (DEFAULT) PE1 DIVIDER PATH EDGE SENSITIVITY 0 FALLING EDGE (RECOMMENDED) 1 RISING EDGE (DEFAULT) CPC1CPC0 CHARGE PUMP CONTROL 0 0 BOTH ON 0 1 PUMP DOWN 1 0 PUMP UP 1 1 TRISTATE (DEFAULT) CPS CHARGE PUMP CONTROL SOURCE 0 CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL) 1 CONTROL FROM PFD (DEFAULT) CPP1 CPP0 CHARGE PUMP CURRENT 0 0 250µA 0 1 500µA (DEFAULT) 1 0 750µA 1 1 1000µA CPB4 CPB3 CPB2 CPB1 CPB0 PFD PHASE OFFSET MULTIPLIER 0 0 0 0 0 0 × 22.5°/ICPMULT 0 0 0 0 1 1 × 22.5°/ICPMULT 0 0 1 1 0 6 × 22.5°/ICPMULT (RECOMMENDED) 0 1 0 1 0 10 × 22.5°/ICPMULT (DEFAULT) 1 0 0 0 0 16 × 22.5°/ICPMULT 1 1 1 1 1 31 × 22.5°/ICPMULT CPBD PFD PHASE OFFSET POLARITY 0 NEGATIVE 1 POSITIVE (DEFAULT) CPM CHARGE PUMP CURRENT REFERENCE SOURCE 0 INTERNAL (DEFAULT) 1 EXTERNAL INPUT REFERENCE RS0 RS1 PATH SOURCE 0 0 2× REFIN 0 1 REFIN (DEFAULT) 1 0 0.5× REFIN 1 1 0.25× REFIN RMS2 RMS1 RMS0 REF OUTPUT MUX SELECT 0 0 0 LOCK DETECT (DEFAULT) 0 0 1 VPTAT 0 1 0 REFIN (BUFFERED) 0 1 1 0.5× REFIN (BUFFERED) 1 0 0 2× REFIN (BUFFERED) 111 110 101 TRRREEISSSEETRRAVVTEEEDD 08545-008 Figure 42. Register 4—PLL Charge Pump, PFD, and Reference Path Control Register Map Rev. D | Page 18 of 32

Data Sheet ADRF6602 REGISTER 5—PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5) PLL LO LO LO RESERVED CAP DAC RES EN DIV1 EXT DRV CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 CD3 CD2 CD1 CD0 0 PLEN LDV1 LXL LDRV C3(1)C2(0)C1(1) CAPACITOR DAC LO OUTPUT DRIVER CD3 CD2 CD1 CD0 CONTROL FOR IIP3 LDRV ENABLE OPTIMIZATION 0 0 0 0 MIN 0 DRIVER OFF (DEFAULT) 1 1 1 1 MAX 1 DRIVER ON EXTERNAL LO DRIVE LXL ENABLE (PIN 37, PIN 38) 0 INTERNAL LO OUTPUT (DEFAULT) 1 EXTERNAL LO INPUT LDV1 DIVIDE-BY-2 IN LO CHAIN ENABLE 0 DIVIDE BY 1 1 DIVIDE BY 2 (DEFAULT) PLEN PLL ENABLE 01 DENISAABBLLEE (DEFAULT) 08545-009 Figure 43. Register 5—PLL Enable and LO Path Control Register Map REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106) RESERVED CEHPNUAAMRBGPLEE ENL3A.D3BOVLEVECNOA BLDLEO ENVACBOLE SWVCITOCH VCO AMPLITUDE BCVWTC RSOLW VCO BAND SELECT FROM SPI CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15DB14DB13DB12DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 CPEN L3EN LVEN VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5VBS4VBS3VBS2VBS1VBS0C3(1)C2(1)C1(0) CPEN CHARGE PUMP ENABLE VC[5:0] VCO AMPLITUDE VBS[5:0] VCO BAND SELECT FROM SPI 0 DISABLE 0x00 0 0x00 1 ENABLE (DEFAULT) …. …. 0x01 0x18 24 (DEFAULT) …. DEFAULT 0x20 …. …. 0x3F L3EN 3.3V LDO ENABLE 0x2B 43 …. …. 0 DISABLE 0x3F 63 (RECOMMENDED) VBSRC VCO BW CAL AND SW SOURCE CONTROL 1 ENABLE (DEFAULT) 0 BAND CAL (DEFAULT) VCO SW VCO SWITCH CONTROL FROM SPI 1 SPI LVEN VCO LDO ENABLE 0 REGULAR (DEFAULT) 0 DISABLE 1 BAND CAL 1 ENABLE (DEFAULT) VCO EN VCO ENABLE 01 DENISAABBLLEE (DEFAULT) 08545-010 Figure 44. Register 6—VCO Control and VCO Enable Register Map REGISTER 7—MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE (DEFAULT: 0x000007) MIXER RES XVCO B_EN RESERVED CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18DB17DB16DB15DB14DB13DB12DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 XVCO MBE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(1)C2(1) C1(1) MBE MIXER BIAS ENABLE 0 DISABLE 1 ENABLE (DEFAULT) XVCO EXTERNAL VCO 10 IENXTTEERRNNAALL V VCCOO (DEFAULT) 08545-011 Figure 45. Register 7—Mixer Bias Enable and External VCO Enable Register Map Rev. D | Page 19 of 32

ADRF6602 Data Sheet THEORY OF OPERATION The ADRF6602 integrates a high performance downconverting Table 8. Register Functions mixer with a state-of-the-art fractional-N PLL. The PLL also Register Function integrates a low noise VCO. The SPI port allows the user to control Register 0 Integer divide control for the PLL the fractional-N PLL functions and the mixer optimization Register 1 Modulus divide control for the PLL functions, as well as allowing for an externally applied LO or VCO. Register 2 Fractional divide control for the PLL The mixer core within the ADRF6602 is the next generation of Register 3 Σ-Δ modulator dither control an industry-leading family of mixers from Analog Devices, Inc. Register 4 PLL charge pump, PFD, reference path control The RF input is converted to a current and then mixed down to IF Register 5 PLL enable and LO path control using high performance NPN transistors. The mixer output currents Register 6 VCO control and VCO enable are transformed to a differential output. The high performance active Register 7 Mixer bias enable and external VCO enable mixer core results in an exceptional IIP3 and IP1dB, with a very low output noise floor for excellent dynamic range. Over the Note that internal calibration for the PLL must be run when the specified frequency range, the ADRF6602 typically provides IF ADRF6602 is initialized at a given frequency. This calibration is input P1dB of 14.5 dBm and IIP3 of 30 dBm. run automatically whenever Register 0, Register 1, or Register 2 is programmed. Because the other registers affect PLL performance, Improved performance at specific frequencies can be achieved Register 0, Register 1, and Register 2 should always be programmed with the use of the internal capacitor DAC (CDAC), which is last and in this order: Register 0, Register 1, Register 2. programmable via the SPI port, and by using a resistor to a 5 V supply from the IP3SET pin (Pin 29). Adjustment of the capacitor To program the frequency of the ADRF6602, the user typically DAC allows increments in phase shift at internal nodes in the programs only Register 0, Register 1, and Register 2. However, ADRF6602, thus allowing cancellation of third-order distortion if registers other than these are programmed first, a short delay with no change in supply current. Connecting a resistor to a 5 V should be inserted before programming Register 0. This delay supply from the IP3SET pin increases the internal mixer core current, ensures that the VCO band calibration has sufficient time to thereby improving overall IIP2 and IIP3, as well as IP1dB. Using complete before the final band calibration for Register 0 is initiated. the IP3SET pin for this purpose increases the overall supply current. Software is available on the ADRF6602 product page under the The fractional divide function of the PLL allows the frequency Evaluation Boards & Development Kits section that allows easy multiplication value from REF_IN to LO output to be a fractional programming from a PC running Windows XP or Vista. value rather than be restricted to an integer value as in traditional INITIALIZATION SEQUENCE PLLs. In operation, this multiplication value is INT + (FRAC/MOD), To ensure proper power-up of the ADRF6602, it is important to where INT is the integer value, FRAC is the fractional value, reset the PLL circuitry after the VCC supply rail settles to 5 V ± and MOD is the modulus value, all programmable via the SPI 0.25 V. Resetting the PLL ensures that the internal bias cells are port. In other fractional-N PLL designs, fractional multiplication properly configured, even under poor supply start-up conditions. is achieved by periodically changing the fractional value in a deterministic way. The disadvantage of this approach is often To ensure that the PLL is reset after power-up, follow this procedure: spurious components close to the fundamental signal. In the 1. Disable the PLL by setting the PLEN bit to 0 (Register 5, ADRF6602, a Σ-Δ modulator is used to distribute the fractional Bit DB6). value randomly, thus significantly reducing the spurious content 2. After a delay of >100 ms, set the PLEN bit to 1 (Register 5, due to the fractional function. Bit DB6). PROGRAMMING THE ADRF6602 After this procedure is followed, the other registers should be The ADRF6602 is programmed via a 3-pin SPI port. The timing programmed in this order: Register 7, Register 6, Register 4, requirements for the SPI port are shown in Figure 2. Eight pro- Register 3, Register 2, Register 1. Then, after a delay of >100 ms, grammable registers, each with 24 bits, control the operation of Register 0 should be programmed. the device. The register functions are listed in Table 8. Rev. D | Page 20 of 32

Data Sheet ADRF6602 LO SELECTION LOGIC The operation of the LO generation and whether LOP and LON are inputs or outputs are determined by the logic levels applied The downconverting mixer in the ADRF6602 can be used at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN), as well as Bit DB3 without the internal PLL by applying an external differential (LDRV) and Bit DB6 (PLEN) in Register 5. The combination of LO to Pin 37 and Pin 38 (LON and LOP). In addition, when externally applied logic and internal bits required for particular using an LO generated by the internal PLL, the LO signal can LO functions is given in Table 9. be accessed directly at these same pins. This function can be used for debugging purposes, or the internally generated LO can be used as the LO for a separate mixer. Table 9. LO Selection Logic Pins1 Register 5 Bits1 Outputs Pin 16 (PLL_EN) Pin 36 (LODRV_EN) Bit DB6 (PLEN) Bit DB3 (LDRV) Output Buffer LO 0 X 0 X Disabled External 0 X 1 X Disabled External 1 X 0 X Disabled External 1 0 1 0 Disabled Internal 1 X 1 1 Enabled Internal 1 1 1 X Enabled Internal 1 X = don’t care. Rev. D | Page 21 of 32

ADRF6602 Data Sheet APPLICATIONS INFORMATION BASIC CONNECTIONS FOR OPERATION be ac-coupled and terminated with a 50 Ω resistor as shown in Figure 46. The reference signal, or a divided-down version of Figure 46 shows the schematic for the ADRF6602 evaluation the reference signal, can be brought back off chip at the multiplexer board. The six power supply pins should be individually decoupled output pin (MUXOUT). A lock detect signal and a voltage using 100 pF and 0.1 µF capacitors located as close as possible proportional to the ambient temperature can also be selected to the device. In addition, the internal decoupling nodes on the multiplexer output pin. (DECL3P3, DECL2P5, and DECLVCO) should be decoupled with the capacitor values shown in Figure 46. The loop filter is connected between the CP and VTUNE pins. When connected in this way, the internal VCO is operational. The RF input is internally ac-coupled and needs no external For information about the loop filter components, see the bias. The IF outputs are open collector, and a bias inductor is Evaluation Board Configuration Options section. required from these outputs to VCC. Operation with an external VCO is also possible. In this case, A peak-to-peak differential swing on RF of 1 V (0.353 V rms IN the loop filter components should be referred to ground. The for a sine wave input) results in an IF output power of 3.8 dBm. output of the loop filter is connected to the input voltage pin of The reference frequency for the PLL should be from 12 MHz to the external VCO. The output of the VCO is brought back into 160 MHz and should be applied to the REF_IN pin, which should the device on the LOP and LON pins, using a balun if necessary. P1 9-PIN 1 2 3 4 5 6 7 8 9 DSUB VCC R36 R19 R35 R30 0Ω R54 0Ω 0Ω 0Ω (0402) 1(004k0Ω2) (0R042Ω002)(0402) (0402) (0402) 0(R0Ω54702) S2 R53 10kΩ C34 R52 (0402) OPEN OPEN VCC (0402) (0402) RED +5V C7 C25 C23 C20 C19 C9 C33 R51 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF OPEN OPEN (0402) (0402) (0402) (0402) (0402) (0402) (0402) (0402) OPESN1VRCECDO(R105P45E02N) VCC_LO R0(0VΩ64C0C1(C02084_)00Vp22F)I 0(R0VΩ24C601(CC02024_)040Mp2FI)X 0(R0Ω24V501(CC0202C4)020_p2LF)O 0(R0Ω24501(C0202V4)01C0p2CF)2 0(R0Ω14701(C0201V4)08C0p2CF)1 R0(0Ω7401(C02014)000p2F) PLL_EN CLK DATA LE O(C03P42E02N) O(R05P40E02N) R56 34 27 22 17 10 1 16 13 12 14 DECL2P5 (04002Ω) LODRVL_OENN36 INTESRPFIACE 9 (1C0014060p2F)(0R041Ω082) (0C0.1147µ0F2) 1(C0046µ20F3) LO IN/OUT 37 TC541T-18-1313+(011CC4nn056FF2)LOP38 FRARCETGION MODULUS INTREEGGER BBUUFFFFEERR M2U:1XDIV÷I2DBD2,IYEV1R 2DECL3P3 (1C0014020p2F)(00R4Ω082) (0C0.1141µ0F2) O(C04P61E03N) (0402) ADRF6602 RFIN THIRD-ORDER 26 RFIN FRACTIONAL R28 C31 INTERPOLATOR VCO 0Ω REF_IN (014n0F2)REF_IN ×2 N2C1OTUON1T2E3R PRES÷C2ALER CORE (0402) 6 REFO(U409T4R.0972Ω0) ÷÷24 MUX SETNEMSOPR +–FDREEPTQHEUACESTNEOCRY 57C2055H000AµµµRAAAG,,(DEEPFUAMUPLT), 29 IP3SET(0R042Ω072) (0C0.2147µ0F2) MUXOUT 8 1000µA R16 (004Ω02) 4 7 11 15 20 21 23 24 25 28 30 31 35 RSERT25 3CP 39VTUNE40DECLVCO IFP18 19IFN 1 4 RFOUT R38 (0R043Ω072)(O0P40E2N) 0(R0Ω64202) V+C5CV R05Ω9 23 5(0R044Ω032) TECSPT (004Ω02) R(9041002k)ΩR(60540120)kΩ VTUNE (C024902) (ORAPNOGINET) 3R.100kΩ ORP6E3N (00.14µ0F2) C14 (0603) C13 C40 (0402) 22pF 6.8pF 22pF (0603) C15 (0603) (0603) 2.7nF (1206) O(R01P41E02N) (00R4Ω012) 0(R0Ω14202) (016C00µ43F3) (O0P40EC2N2) 1(00400Cp2F1) 08545-024 Figure 46. Basic Connections for Operation of the ADRF6602 Rev. D | Page 22 of 32

Data Sheet ADRF6602 AC TEST FIXTURE Characterization data for the ADRF6602 was taken under very the signal generation and measurement equipment. Figure 47 strict test conditions. All possible techniques were used to shows the typical AC test set up used in the characterization of achieve optimum accuracy and to remove degrading effects of the ADRF6602. ADRF6602 CHARACTERIZATION RACK DIAGRAM. ALL INSTRUMENTS ARE CONTROLLED BY A LAB COMPUTER VIA A USB TO GPIB CONTROLLER, DAISY CHAINED TO EACH INDIVIDUAL INSTRUMENT. RF1 AGILENT N5181A HP 11636A POWER DIVIDER RF2 AGILENT N5181A REF_IN AGILENT N5181A RFIN REF_IN ADRF6602 EVALUATION BOARD IF_OUT D ROHDE & SCHWARTZ AN FSEA30 B UR SE DD LLER C HEA OD NTRPIN O0- C1 AGILENT 34401A SET TO IDC N (SET FOR SUPPLY CURRENT) PI 9- 5V dc VIA GND VIA 10-PIN DC HEADER 10-PIN DC HEADER 3.3V dc VIA 10-PIN DC HEADER AGILENT 34980A WITH THREE 34921 MODULES AND ONE 34950 MODULE 5V dc MEASURED FOR SUPPLY CURRENT AGILENT E3631A 25V SET TO JU3M.3RPVEE, TR6UVE RDSN ETSTO ATGROEE T5HVE.R 08545-047 Figure 47. ADRF6602 AC Test Set Up Rev. D | Page 23 of 32

ADRF6602 Data Sheet EVALUATION BOARD Figure 50 shows the schematic of the RoHS-compliant evaluation To connect the evaluation board to a USB port, a USB adapter board board for the ADRF6602. This board has four layers and was (EVAL-ADF4XXXZ-USB) must be purchased from Analog Devices. designed using Rogers 4350 hybrid material to minimize high This board connects to the PC using a standard USB cable with a frequency losses. FR4 material is also adequate if the design can USB mini-connector at one end. An additional 25-pin male to 9-pin accept the slightly higher trace loss of this material. female adapter is required to mate the ADF4XXXZ-USB board to the 9-pin D-Sub connector on the ADRF6602 evaluation board. The evaluation board is designed to operate using the internal VCO of the device (the default configuration) or with an external VCO. To use an external VCO, R62 and R12 should be removed. Place 0 Ω resistors in R63 and R11. The input of the external VCO should be connected to the VTUNE SMA connector, and the external VCO output should be connected to the LO IN/OUT SMA connector. In addition to these hardware changes, internal register settings must also be changed to enable operation with an external VCO (see the Register 6—VCO Control and VCO Enable (Default: 0x1E2106) section). Additional configuration options for the evaluation board are described in Table 10. EVALUATION BOARD CONTROL SOFTWARE Software to program the ADRF6602 is available for download on the ADRF6602 product page under the Evaluation Boards & Development Kits section. To install the software 1. DADowRnFl6oxa0dx a_n3dp 0epx0tr_aXctP t_hine sztiapl lf.eilxee: file. 08545-025 2. Follow the instructions in the read me file. Figure 48. Control Software Opening Menu The evaluation board can be connected to the PC using a PC Figure 49 shows the main menu of the control software with the parallel port or a USB port. These options are selectable from the default settings displayed. opening menu of the software interface (see Figure 48). The evaluation board is shipped with a 25-pin parallel port cable for connection to the PC parallel port. Rev. D | Page 24 of 32

Data Sheet ADRF6602 08545-026 Figure 49. Main Screen of the ADRF6602 Evaluation Board Software Rev. D | Page 25 of 32

ADRF6602 Data Sheet SCHEMATIC AND ARTWORK 320-54580 AGND GND21 J110 9J1 J18 7J1 6J1 5J1 4J1 3J1 2J1 1J1 6 W1-4CT3 R590 VCC GND1NDG11 AGND OUT AGND 4 T3 12 C29 0.1UF AGND R44 DNI 0 VCC_SENSE VCO_LDO LO_EXTERN 2P5V_LDO 3P3V_LDO AGND VCC_SENSE AGND VCC 34R 0 SNS1 SNS 66R VCC1VCC 0 FU8021C AGND R68 0DNI R67 0 VCC_RF RFIN AGND IFP AGND NIF AGND OBFBRL___CCCCCCVVV 12900332RRR LO AGND OUTPUT_EN IP3SET R27VCC_BBBDTC27 0.1UF AGND VCC_RF1R26 0C24C25 100PF0.1UF AGNDAGND R28 0VCC_BB11BR25VCC_B 0C23 0.1UF AGND C35 DNI L1 DTB47R 0 R48 0C36L2 TBDDNI R69 0 VCC_LO IP3SET1 R60TBD AGND C22 100PF AGND VCC R58DNI VCC T7 66A5AGND5AP4-T74P4-T74A T8AGND5 4P1-T72NC VCC_LO1R6 0C8C7 100PF0.1UF AGNDAGND IP3SET AGND 30GND 29IP3SET 28GND 27VCC_V2I 26RFIN25GND 24GND 23GND 22VCC_MIX 21GND PADE-PAD AGND VCC_LO11R24 0_LOVCCC20 0.1UF AGND P1-T71P1-T71A2AGND2AP3-T73P3-T73A P1-61P4-T7 207P3-T73R EVTUNLO_EXTERN R63100KAGND 3C5C603R1NF1NF2C4006RVCC122PF1VCC R56R5510K10K 32AGND1S1 AGND 32343537403133363839OOECCNDDNPNOLENNONCN__UGGLVLCVTLRCVCVDEODL1VCC1 2DECL3P3 3CP 4GNDR25RSETZ1DNI6REF_IN 7GND 8MUXOUT 9DECL2P5 10VCC2 ONLEA__DDDCTKLNPNANNCLLEFFGGGDCVPLII17613191115118201412 CLK1 C32R501KDNI100PFDNIAGND 5P103RAGND1-1P1R192034DATAR30150400032RRP1-66R5770R368091AGNDC21AMP745781-4DIG_GND100PF 1DAGNC33SR512KDNI1100PFDNI23OUTPUT_ENAGND R53R5410K10KC34R521KDNI100PFDNIVCCAGND11AGNDLE5VCC R65 10K AGND C16 100PF AGND C18 100PF AGND R9 10K 0K13R C136.8PFC15 2.7NF 201R VCO_LDO 1R1 0C2C1 100PF0.1UF AGNDAGNDC43 10UFAGND P1-1AGND D17BRT 2P5V1R18 0C17C4210UF0.1UF AGNDAGND VCC21R17VCC0C19 0.1UF AGND C1470322PFR 1IN1DR AGND VCO_LDO R49 DNI REFOUTR16 0 AGND2P5V_LDO R38 0 C10 100PF AGND C12 100PF AGND 1Y 4IN1DR 1CP VCC41R7VCC 0C9 0.1UF AGND 3P3V11R8 0C11C41 0.1UFUF10 AGNDAGND OSC_3P3V1R15 0 C4 22000PFC3 F10PAGND C31 1000PF R7049.9 AGND OSC_3P3V REFIN AGND DO3P3V_L Figure 50. Evaluation Board Schematic Rev. D | Page 26 of 32

Data Sheet ADRF6602 08545-013 08545-012 Figure 51. Evaluation Board Layout (Bottom) Figure 52. Evaluation Board Layout (Top) Rev. D | Page 27 of 32

ADRF6602 Data Sheet EVALUATION BOARD CONFIGURATION OPTIONS Table 10. Default Condition/ Component Description Option Settings S1, R55, R56, R33 LO select. Switch and resistors to ground the LODRV_EN pin. The LODRV_EN pin setting, in S1 = R55 = open combination with internal register settings, determines whether the LOP and LON pins (not installed), function as inputs or outputs (see the LO Selection Logic section for more information). R56 = R33 = 0 Ω, LODRV_EN = 0 V LO IN/OUT LO input/output. An external 1× LO or 2× LO can be applied to this single-ended input LO input SMA Connector connector. REFIN Reference input. The input reference frequency for the PLL is applied to this connector. SMA Connector Input impedance is 50 Ω. REFOUT Multiplexer output. The REFOUT connector connects directly to the MUXOUT pin. The Lock detect SMA Connector on-board multiplexer can be programmed to bring out the following signals: REFIN, 2× REFIN, REFIN/2, and REFIN/4; temperature sensor output voltage; and lock detect indicator. CP Test Point Charge pump test point. The unfiltered charge pump signal can be probed at this test point. Note that the CP pin should not be probed during critical measurements such as phase noise. R37, C14, R9, R10, Loop filter. Loop filter components. C15, C13, R65, C40 R11, R12 Loop filter return. When the internal VCO is used, the loop filter components should be R12 = 0 Ω (0402), returned to Pin 40 (DECLVCO) by installing a 0 Ω resistor in R12. When an external VCO is used, R11 = open (0402) the loop filter components can be returned to ground by installing a 0 Ω resistor in R11. R62, R63, VTUNE Internal vs. external VCO. When the internal VCO is enabled, the loop filter components are R62 = 0 Ω (0402), SMA Connector connected directly to the VTUNE pin (Pin 39) by installing a 0 Ω resistor in R62. To use an R63 = open (0402) external VCO, R62 should be left open. A 0 Ω resistor should be installed in R63, and the voltage input of the VCO should be connected to the VTUNE SMA connector. The output of the VCO is brought back into the PLL via the LO IN/OUT SMA connector. R2 R pin. This pin is unused and should be left open. R2 = open (0402) SET RFIN SMA Connector RF input. The RF input signal should be applied to the RFIN SMA connector. The RF input of R3 = R23 = open (0402) the ADRF6602 is ac-coupled, so no bias is necessary. T3 IF output. The differential IF output signals from the ADRF6602 (IFP and IFN) are converted to a single-ended signal by T3. Rev. D | Page 28 of 32

Data Sheet ADRF6602 OUTLINE DIMENSIONS 6.10 0.60 MAX 6.00 SQ 5.90 0.60 MAX PIN 1 INDICATOR 3031 401 PIN 1 5.85 0.50 EXPOSED 4.25 INDICATOR 5.75 SQ BSC PAD 4.10 SQ 5.65 (BOTTOM VIEW) 3.95 21 10 20 11 TOP VIEW 00..5400 0.20 MIN 4.50 REF 0.30 12° MAX 0.80 MAX FOR PROPER CONNECTION OF 1.00 0.65 TYP THE EXPOSED PAD, REFER TO 0.85 0.05 MAX THE PIN CONFIGURATION AND 0.80 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. SEATING 0.30 COPL0A.0N8ARITY PLANE 00C..21O38MPLIANTTO0 J.2E0D REECF STANDARDS MO-220-VJJD-2 06-01-2012-D Figure 53. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADRF6602ACPZ-R7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-1 ADRF6602-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. D | Page 29 of 32

ADRF6602 Data Sheet NOTES Rev. D | Page 30 of 32

Data Sheet ADRF6602 NOTES Rev. D | Page 31 of 32

ADRF6602 Data Sheet NOTES ©2010–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08545-0-10/13(D) Rev. D | Page 32 of 32